IMPLEMENTATION OF CISC MICROPROCESSOR USING VHDL

B.Tech. Major Project Report

BY
Abhinandan Sharma (08401) Abhishek Bhasker Dharam Pal Rao Hiteshwar Gaur (08404) (08417) (08420)

DEPARTMENT OFELECTRONICS & COMMUNICATION ENGINEERING NATIONAL INSTITUTE OF TECHNOLOGY HAMIRPUR-177005, HP (INDIA) DECEMBER, 2011

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IMPLEMENTATION OF CISC MICROPROCESSOR USING VHDL

A Major Project Report

Submitted in partial fulfillment of the Requirements for the award of the degree of Bachelor of Technology in ELECTRONICS & COMMUNICATION ENGINEERING BY Abhinandan Sharma (08401) Abhishek Bhasker Dharam Pal Rao Hiteshwar Gaur (08404) (08417) (08420)

DEPARTMENT ELECTRONICS & COMMUNICATION ENGINEERING NATIONAL INSTITUTE OF TECHNOLOGY HAMIRPUR-177005, HP (INDIA) DECEMBER, 2011

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CERTIFICATE
This is to certify that the work being presented in the B.Tech. Major project report entitled IMPLEMENTATION OF CISC MICROPROCESSOR USING VHDLin partial fulfillment of the requirements for the award of the degree in BACHELOR OF TECHNOLOGY IN ELECTRONICS AND COMMUNICATION ENGINEERING and submitted to the department of Electronics & Communication Engineering of National Institute of Technology Hamirpur (H.P) is an authentic record of our work carried out during a period from July 2010 to December 2011 under the supervision of Dr. ASHWANI RANA, Electronics & Communication Engineering department. The matter presented in this thesis has not been submitted by us for award of any other degree elsewhere. Signature of the candidates Abhinandan Sharma(08401) Abhishek Bhasker Dharam Pal Rao Hiteshwar Gaur (08404) (08417) (08420)

This is to certify that the above statement made by candidates is correct to the best of my knowledge. Signature of Supervisor: Dr. ASHWANI RANA ECED, NIT HAMIRPUR Date: Head Electronics and Communication Engineering Department National Institute of Technology, Hamirpur

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Acknowledgement
We are overwhelmed in all humbleness to acknowledge our depth to all those who have helped and supported us to put our ideas related to this project well above the level of simplicity and into something concrete. Our deepest thanks to Dr. ASHWANI RANA, the Guide of our project for guiding and correcting us with attention and care. They took the pain to go through the project and make necessary corrections as and when needed. We also express our thanks to the H.O.D. of our department Dr. VINOD KAPOOR for providing us this bright opportunity to realize our ideas. We would also thank our Institution and other faculty members without whom this project would have been a distant reality.

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PREFACE
Microprocessor design isnt hard, but sometimes it seems that way. As processors have grown in complexity and processor design teams have grown in size, individual design engineers have become more specialized, focusing on only one part of the design process. Each step in the design flow has its own jargon; today it is not at all hard to be working on a processor design team and still not have a clear understanding of aspects of design that dont involve you personally. Likewise, most textbooks focus on one particular aspect of processor design, often leaving out information about what steps came before or what will happen afterward. This project provides the key concepts of processor design and the vocabulary to enable the reader to learn more about each step. This project gives a broad knowledge of design and implementation of CISC microprocessor. We would also like to thank all technical and non technical staff of the college for providing us resources and helping in every possible manner for completion of this project.

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Contents

1 Introduction to CISC Microprocessor

2 Instruction Set Architecture 2.1 Instruction format . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 Functional Units 3.1 Block Diagram of Design . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Instruction and Data Memory . . . . . . . . . . . . . . . . . . . . . . 3.3 Micro control store . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Microword Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 Instruction Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 VHDL Code 4.1 CISC Microprocessor: execution unit . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Data Memory: DMEM . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 Instruction Memory: IMEM . . . . . . . . . . . . . . . . . . . . . . . 4.4 Instruction Decoder code . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 Micro Control Store . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6 Microword Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5 Simulation Results

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Abstract
The aim of the project is to implement CISC processor incorporating micro programmed control unit. The instruction set architecture uses two instructions and One addressing modes. The instructions are orthogonal with one another which implies that any instruction can use any addressing mode. We have used fixed instruction format, in which each instruction is encoded as a 32 bit word. The processor is designed in VHDL.

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1 Introduction to CISC microprocessor

A complex instruction set computer (CISC) is a computer where single instructions can execute several low-level operations (such as a load from memory,

an arithmetic operation, and a memory store) and/or are capable of multi-step operations or addressing modes within single instructions.

2 Instruction Set Architecture.

This chapter includes the instruction set architecture used in the design. Instruction set architecture is an interface between software and hardware in a microprocessor. Software describes the functionalities and resources available to the programmer and Hardware details the implementation used for providing the required functionality. The following sections describe the issues associated with ISA design :

2.1 Instruction format

Fixed length instruction format is chosen, each instruction is encoded as a 32 bit word. Each byte of the word indicates the following in order. Byte 0 : b7-b0 indicates the destination register Byte 1 : b15-b8 indicates the source register Byte 2 : b23-b16 indicates the addressing mode Byte 3 : b31-b24 indicates the Operation to be performed

2.2 Registers

There are a total of 8 data register R7-R0 that can be accessed by the program. A separate set of 8 address registers are available for pointing to memory locations for use as stack pointers. The design contains two registers IR and IRE which holds the next instruction and the current instruction being executed. PC(Program counter) points to the next

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instruction in the instruction memory. The addressing mode sequence automatically updates the program counter depending on a regular instruction or a branch instruction.

2.3 Addressing modes

There are three possible addressing modes which are describe below.

Direct Addressing:

The operands are the contents of the registers specified in the Instruction. As an example consider

RX <= RX Where

RY

(1)

denotes an operation on the data, the instruction has the following format OPER RX; RY (2)

2.4 Operations

All the operations are performed on 32 bit data. Negative number are represented as 2's complement numbers. The design is capable of the following operations.

1. ADD : Adds the two integers.

2. SUB : Subtracts two integers.

3 Functional Units
This section describes the functional units used in the implementation of process. The VHDL code is included in section 4.

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3.1 Block Diagram of Design

Control Unit

Execution Unit

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The block diagram of the design is shown in Fig. 1. Instruction and Data memory are part of the design. These modules store the instructions and data, the instruction decoder fetches the next instruction based on the location pointed by PC and loads it to IR. The data is fetched from the data memory.

3.2 Instruction and Data Memory These modules store the instructions and data. The data memory has both read and Write capability but instruction memory is read only type. In the interest of brevity Both data and instruction memory contain only 16 locations of 32 bit wide word each. The contents of instruction memory are initialized in the code. When the processor is Reset, the first instruction is fetched from the instruction memory and loaded to IRE and the instruction decoder decodes this instruction and fetches the required data from the data memory. After performing the required operation on the data the data Is written back to the data memory to the memory location pointed by the address register (A0).

3.3 Micro control store

The micro control store stores the micro control words, the 4 states are encoded in 12 bit format b11-b0. Bits b11,10 represented as TY indicates one the following 00 : Access next microword. 01 : Sequential branch (Addressing mode to Execution mode sequence) 10 : Branch on Zero 11 : Instruction branch The bits b9- b5 indicate the present state and b4-b0 indicate the next state under the condition that it is not a Sequential or an Instruction branch.

3.4 Microword Decoder

The microword decoder uses the microword fetched from the control store and decodes the same to generate the control signal for the execution unit using a lookup table. ALU Function: Selects the type of operation to be performed by ALU.

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ALU Source: Selects one of the many possible operands to the ALU. Register Transfer: Indicated the data to be loaded onto a register. External Device Enable: These signals enable the data and instruction memory. 3.5 Instruction Decoder The instruction decoder decodes the instruction stored in IRE and determines the next address to the micro control store based on TY, next micro address indicated by the current microword and the status register.

4. VHDL Code
The subsequent sections contain the VHDL code for implementing the design.

4.1 Execution unit:----------------------------------------------------------------------------------- Company: -- Engineer: -- Create Date: -- Design Name: -- Module Name: -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- Dependencies: -- Revision: -- Revision 0.01 - File Created -- Additional Comments: ----------------------------------------------------------------------------------execution_unit - Behavioral 21:39:04 11/08/2011

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library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity execution_unit is Port ( Reset : in STD_LOGIC; clk : in STD_LOGIC); end execution_unit;

architecture Behavioral of execution_unit is component microword_decoder Port ( clk : in std_logic; ALU_src1 : out std_logic_vector(2 downto 0); ALU_src2 : out std_logic_vector(2 downto 0); ALU_fun_sel: out std_logic_vector(1 downto 0); IR_IRE_en : out std_logic; ALU_en : out std_logic; flag_reg_update_en : out std_logic; DM_en : out std_logic; IM_en : out std_logic; SW_en : out std_logic; Din_sel : out std_logic_vector(1 downto 0);

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Dout_sel : out std_logic_vector(1 downto 0); A0_sel : out std_logic_vector(2 downto 0); PC_sel : out std_logic; T2_sel : out std_logic_vector(2 downto 0); data_regset_xsel : out std_logic_vector(1 downto 0); data_regset_ysel : out std_logic_vector(1 downto 0); next_address_from_microdecoder :out std_logic_vector(4 downto 0); next_address_to_microdecoder :in std_logic_vector(4 downto 0); TY_from_microdecoder : out std_logic_vector(1 downto 0)); end component; component IMEM Port ( DoutI : out STD_LOGIC_VECTOR (31 downto 0); ADDRI : in STD_LOGIC_VECTOR (31 downto 0); RDI : in STD_LOGIC; CEI : in STD_LOGIC); end component; component DMEM Port ( DIND : in STD_LOGIC_VECTOR (31 downto 0); DoutD : out STD_LOGIC_VECTOR (31 downto 0); ADDRD : in STD_LOGIC_VECTOR (31 downto 0); RDD : in STD_LOGIC; WRD : in STD_LOGIC; CED : in STD_LOGIC; reset: in std_logic); end component; component Instruction_decoder Port ( IR_read : in std_logic_vector(31 downto 0); IRE_read : in STD_LOGIC_VECTOR (31 downto 0); pres_mc_addr : in std_logic_vector (4 downto 0 ); Flag_reg : in std_logic; next_mc_addr : out STD_LOGIC_vector(4 downto 0); Rx_index_out : out STD_LOGIC_vector(2 downto 0);

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Ry_index_out : out STD_LOGIC_VECTOR(2 downto 0); ALU_func : out STD_LOGIC_VECTOR (1 downto 0); TY_from_mcmem : in std_logic_vector (1 downto 0)); end component; signal T1 : std_logic_vector(31 downto 0):=(others=>'0'); signal T2_sel : std_logic_vector(2 downto 0):=(others=>'0'); signal T2 : std_logic_vector(31 downto 0):=(others=>'0'); signal ALU_en : std_logic:='0'; signal ALU_fun_sel:std_logic_vector(3 downto 0):=(others=>'0'); signal ALU_src1 :std_logic_vector(2 downto 0):=(others=>'0'); signal ALU_src2 : std_logic_vector(2 downto 0):=(others=>'0'); signal ALU_in1 : std_logic_vector(31 downto 0):=(others=>'0'); signal ALU_in2 : std_logic_vector(31 downto 0):=(others=>'0'); signal Rx_index : std_logic_vector (2 downto 0):=(others=>'0'); signal Ry_index : std_logic_vector(2 downto 0):=(others=>'0'); signal IR_IRE_en : std_logic:='0'; signal IR : std_logic_vector(31 downto 0):=(others=>'0'); signal IRE : std_logic_vector(31 downto 0):="00000000"&"00000000"&"00000000"&"00000000"; signal flag_reg_update_en :std_logic:='0'; signal Flag_reg : std_logic:='0'; signal data_regset_xsel :std_logic_vector(1 downto 0):=(others=>'0'); signal data_regset_ysel :std_logic_vector(1 downto 0):=(others=>'0'); type regarray_type is array (0 to 7) of integer range 0 to 1023; signal data_regset : regarray_type:=(1,2,3,4,5,6,7,8); signal address_regset : regarray_type; signal A0_sel : std_logic_vector(2 downto 0):=(others=>'0'); signal A0 : std_logic_vector(31 downto 0):=(others=>'0'); signal Dout_sel : std_logic_vector(1 downto 0):=(others=>'0'); signal Dout : std_logic_vector(31 downto 0):=(others=>'0'); signal Din_sel : std_logic_vector(1 downto 0):=(others=>'0'); signal Din : std_logic_vector(31 downto 0):=(others=>'0');

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signal PC_sel : std_logic:='0'; signal PC : std_logic_vector(31 downto 0):="00000000000000000000000000000001"; signal DM_en :std_logic:='0'; signal edb : std_logic_vector(31 downto 0):=(others=>'0'); signal IM_en :std_logic:='0'; signal eib : std_logic_vector(31 downto 0):=(others=>'0'); signal SW_en :std_logic:='0'; signal edbw : std_logic_vector(31 downto 0):=(others=>'0'); signal next_address_from_microdecoder :std_logic_vector(4 downto 0):=(others=>'0'); signal next_address_to_microdecoder :std_logic_vector(4 downto 0):=(others=>'0'); signal TY_from_microdecoder :std_logic_vector(1 downto 0):=(others=>'0'); signal condition_code_reg : std_logic_vector(15 downto 0); begin mcwdec1 : component microword_decoder port map (clk,ALU_src1, ALU_src2,ALU_fun_sel(3 downto 2), IR_IRE_en, ALU_en, flag_reg_update_en,DM_en, IM_en,SW_en, Din_sel, Dout_sel, A0_sel, PC_sel,T2_sel, data_regset_xsel, data_regset_ysel, next_address_from_microdecoder , next_address_to_microdecoder,TY_from_microdecoder); imem1 : component IMEM port map(eib,A0,IM_en,'1'); dmem1 : component DMEM port map(edbw,edb,A0,DM_en,SW_en,'1',reset); Inst_decode : component Instruction_decoder Port map ( IR,IRE ,next_address_from_microdecoder, Flag_reg,next_address_to_microdecoder, Rx_index,Ry_index,ALU_fun_sel(1 downto 0),TY_from_microdecoder); process(ALU_src1,ALU_src2,ALU_fun_sel,ALU_en) begin case ALU_src1 is when "000" =>ALU_in1 <= T2; when "001" =>ALU_in1 <=PC; when "010" =>ALU_in1 <= Din;

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when "011" =>ALU_in1 <= conv_std_logic_vector(data_regset(conv_integer(unsigned(Rx_index))),32); when "100" =>ALU_in1 <= conv_std_logic_vector(data_regset(conv_integer(unsigned(Ry_index))),32); when others => ALU_in1 <=(others => 'Z'); end case; case ALU_src2 is when "000" =>ALU_in2 <= (others => '0'); when "001" =>ALU_in2 <="00000000000000000000000000000001"; when "010" =>ALU_in2 <= (others =>'1'); when "011" =>ALU_in2 <= conv_std_logic_vector(data_regset(conv_integer(unsigned(Ry_index))),32); when "100" =>ALU_in2 <= Din; when others => ALU_in2 <=(others =>'Z'); end case; end process; process(clk,Din_sel,edb,eib,A0,A0_sel,t1,Ry_index,data_regset,Dout_sel,Rx_index) begin if clk'event and clk = '1' then if ALU_fun_sel(3 downto 2) = "00" then T1 <= ALU_in1 + ALU_in2 ; elsif ALU_fun_sel(3 downto 2) = "10" then case ALU_fun_sel(1 downto 0) is when "00" => T1 <= ALU_in1 + ALU_in2 ; when "01" => T1<= ALU_in1 - ALU_in2 ; when others =>T1 <= (others => 'Z'); end case; end if; if IR_IRE_en = '1' then IRE <= IR; end if; if IM_en = '1' then

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if Din_sel /="01" then IR <= eib; end if; end if; if PC_sel ='1' then PC <= T1; end if; if data_regset_xsel(1) = '1' then if data_regset_xsel(0) = '1' then data_regset(conv_integer(unsigned(Rx_index))) <=conv_integer(Din); else data_regset(conv_integer(unsigned(Rx_index)))<= data_regset(conv_integer(unsigned(Ry_index))); end if; end if; if data_regset_ysel(1) = '1' then if data_regset_ysel(0) = '1' then data_regset(conv_integer(unsigned(Ry_index))) <= conv_integer(T1); else data_regset(conv_integer(unsigned(Ry_index)))<=data_regset(conv_integer(unsigned(Rx _index))); end if; end if; end if; -- end if for clock if A0_sel(2) = '1' then if A0_sel(1 downto 0) = "00" then A0 <= PC; elsif A0_sel(1 downto 0) = "01" then A0 <=T1; elsif A0_sel(1 downto 0) = "10" then A0 <= conv_std_logic_vector(data_regset(conv_integer(unsigned(Ry_index))),32) ; else

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A0 <= T2; end if; end if; end process; process(T1) begin if flag_reg_update_en ='1' then if T1 = 0 then Flag_reg <= '1'; else Flag_reg <= '0'; end if; end if; end process; process(Dout,SW_en) begin if SW_en ='1' then edbw <= Dout ; end if; end process; end Behavioral;

4.2 Data Memory : DMEM ----------------------------------------------------------------------------------- Company: -- Engineer: --- Create Date: -- Design Name: -- Module Name: -- Project Name: -- Target Devices: DMEM - Behavioral 13:09:28 10/30/2011

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-- Tool versions: -- Description: --- Dependencies: --- Revision: -- Revision 0.01 - File Created -- Additional Comments: ----------------------------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity DMEM is Port ( DIND : in STD_LOGIC_VECTOR (31 downto 0); DoutD : out STD_LOGIC_VECTOR (31 downto 0); ADDRD : in STD_LOGIC_VECTOR (31 downto 0); RDD : in STD_LOGIC; WRD : in STD_LOGIC; CED : in STD_LOGIC; reset : in STD_LOGIC);

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end DMEM;

architecture Behavioral of DMEM is type DATARR is array (0 to 15) of integer range 0 to 1023; signal DATMEM : DATARR:= (44,1,22,3,4,5,6,7,8,9,10,11,12,13,14,15); begin process(DIND,ADDRD,RDD,WRD,CED) begin if CED='1' then if RDD = '1' then DoutD <= conv_std_logic_vector(DATMEM(conv_integer(unsigned(ADDRD(3 downto 0)))),32); elsif WRD = '1' then DATMEM(conv_integer(unsigned(ADDRD(3 downto 0))))<= conv_integer(DIND) ; else DoutD <= (others=>'Z'); end if; else DoutD <= (others=>'Z'); end if; end process; end Behavioral;

4.3 Instruction Memory : IMEM ----------------------------------------------------------------------------------- Company: -- Engineer: -- Create Date: -- Design Name: -- Module Name: -- Project Name: -- Target Devices: IMEM - Behavioral 12:06:32 10/30/2011

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-- Tool versions: -- Description: -- Dependencies: -- Revision: -- Revision 0.01 - File Created -- Additional Comments: ---------------------------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity IMEM is Port ( DoutI : out STD_LOGIC_VECTOR (31 downto 0); ADDRI : in STD_LOGIC_VECTOR (31 downto 0); RDI : in STD_LOGIC; CEI : in STD_LOGIC); end IMEM;

architecture Behavioral of IMEM is type MEMARR is array (15 downto 0) of std_logic_vector(31 downto 0); signal INSMEM : MEMARR:=(others=>(others=>'0'));

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begin INSMEM(1) <="00000001"&"00000000"&"00000000"&"00000010"; process(ADDRI,RDI,CEI) begin if CEI='1' then if RDI = '1' then DoutI <= INSMEM(conv_integer(unsigned(ADDRI(3 downto 0)))); else DoutI <= (others=>'Z'); end if; else DoutI <= (others=>'Z'); end if; end process; end Behavioral; 4.4 Instruction Decoder code ----------------------------------------------------------------------------------- Company: -- Engineer: -- Create Date: -- Design Name: -- Module Name: -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- Dependencies: -- Revision: -- Revision 0.01 - File Created -- Additional Comments: ----------------------------------------------------------------------------------Instruction_decoder - Behavioral 13:28:55 10/30/2011

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library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity Instruction_decoder is Port ( IR_read : in STD_LOGIC_VECTOR (31 downto 0); IRE_read : in STD_LOGIC_VECTOR (31 downto 0); pres_mc_addr : in STD_LOGIC_VECTOR (4 downto 0); Flag_reg : in STD_LOGIC; next_mc_addr : out STD_LOGIC_VECTOR (4 downto 0); Rx_index_out : out STD_LOGIC_VECTOR (2 downto 0); Ry_index_out : out STD_LOGIC_VECTOR (2 downto 0); ALU_func : out STD_LOGIC_VECTOR (1 downto 0); TY_from_mcmem : in STD_LOGIC_VECTOR (1 downto 0)); end Instruction_decoder;

architecture Behavioral of Instruction_decoder is

begin process(IRE_read,TY_from_mcmem,pres_mc_addr,Flag_reg,IR_read) begin if TY_from_mcmem = "00" then next_mc_addr <= pres_mc_addr;

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case IRE_read(31 downto 24) is when "00000000" => -- add ALU_func <= "00"; Rx_index_out <= IRE_read(10 downto 8); Ry_index_out <= IRE_read(2 downto 0); when "00000001" =>ALU_func <= "01"; Rx_index_out <= IRE_read(10 downto 8); Ry_index_out <= IRE_read(2 downto 0); when others => ALU_func <= "ZZ"; Rx_index_out <= "ZZZ"; Ry_index_out <= "ZZZ"; end case; elsif TY_from_mcmem = "11" then case IR_read(31 downto 24) is when "00000000" =>ALU_func <= "00"; Rx_index_out <= IRE_read(10 downto 8); Ry_index_out <= IRE_read(2 downto 0); if IR_read(23 downto 16) ="00000000" then next_mc_addr <= "10000"; else next_mc_addr <= "ZZZZZ"; end if; when "00000001" => ALU_func <= "01"; Rx_index_out <= IRE_read(10 downto 8); Ry_index_out <= IRE_read(2 downto 0); if IR_read(23 downto 16) ="00000000" then next_mc_addr <= "10000"; else next_mc_addr <= "ZZZZZ"; end if; when others => ALU_func <= "ZZ"; Rx_index_out <= "ZZZ"; Ry_index_out <= "ZZZ"; next_mc_addr <= "ZZZZZ";

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end case; end if; end process; end Behavioral;

4.5 Micro Control Store ----------------------------------------------------------------------------------- Company: -- Engineer: -- Create Date: -- Design Name: -- Module Name: -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- Dependencies: -- Revision: -- Revision 0.01 - File Created -- Additional Comments: ---------------------------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; microcontrol_store - Behavioral 14:43:57 10/30/2011

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code.

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--library UNISIM; --use UNISIM.VComponents.all;

entity microcontrol_store is Port ( mc_address : in STD_LOGIC_VECTOR (4 downto 0); microcode_out : out STD_LOGIC_VECTOR (11 downto 0)); end microcontrol_store;

architecture Behavioral of microcontrol_store is type mc_array_type is array (31 downto 0) of std_logic_vector(11 downto 0); signal mc_store_reg : mc_array_type:=(others=>(others=>'U')); begin mc_store_reg(1) <= "00" & std_logic_vector(conv_unsigned(1,5))& std_logic_vector(conv_unsigned(2,5)); mc_store_reg(6) <= "11" & std_logic_vector(conv_unsigned(6,5))& std_logic_vector(conv_unsigned(1,5)); --end of instruction mc_store_reg(16) <= "00" & std_logic_vector(conv_unsigned(16,5))& std_logic_vector(conv_unsigned(17,5)); mc_store_reg(17) <= "00" & std_logic_vector(conv_unsigned(17,5))& std_logic_vector(conv_unsigned(6,5)); microcode_out <= mc_store_reg(conv_integer(unsigned(mc_address))); end Behavioral;

4.6 Microword Decoder ----------------------------------------------------------------------------------- Company: -- Engineer: -- Create Date: -- Design Name: -- Module Name: -- Project Name: -- Target Devices: microword_decoder - Behavioral 19:48:04 10/31/2011

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-- Tool versions: -- Description: -- Dependencies: -- Revision: -- Revision 0.01 - File Created -- Additional Comments: ---------------------------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity microword_decoder is Port ( clk : in STD_LOGIC; ALU_src1 : out STD_LOGIC_VECTOR (2 downto 0); ALU_src2 : out STD_LOGIC_VECTOR (2 downto 0); ALU_fun_sel : out STD_LOGIC_VECTOR (1 downto 0):="00"; IR_IRE_en : out STD_LOGIC; ALU_en : out STD_LOGIC; flag_reg_update_en : out STD_LOGIC; DM_en : out STD_LOGIC; IM_en : out STD_LOGIC; SW_en : out STD_LOGIC;

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Din_sel : out STD_LOGIC_VECTOR (1 downto 0); Dout_sel : out STD_LOGIC_VECTOR (1 downto 0); A0_sel : out STD_LOGIC_VECTOR (2 downto 0); PC_sel : out STD_LOGIC; T2_sel : out STD_LOGIC_VECTOR (2 downto 0); data_regset_xsel : out STD_LOGIC_VECTOR (1 downto 0); data_regset_ysel : out STD_LOGIC_VECTOR (1 downto 0); next_address_from_microdecoder : out STD_LOGIC_VECTOR (4 downto 0); next_address_to_microdecoder : in STD_LOGIC_VECTOR (4 downto 0):="10001"; TY_from_microdecoder : out STD_LOGIC_VECTOR (1 downto 0)); end microword_decoder;

architecture Behavioral of microword_decoder is component microcontrol_store port (mc_address: in std_logic_vector(4 downto 0); microcode_out : out std_logic_vector(11 downto 0)); end component; signal microcode_reg : std_logic_vector(11 downto 0):="001000010001"; signal microcode_net : std_logic_vector(11 downto 0):="001000010001"; signal next_address_reg : std_logic_vector(4 downto 0):="10001"; signal TY_reg : std_logic_vector(1 downto 0):="00"; begin mcs1 : component microcontrol_store port map(next_address_to_microdecoder,microcode_net); process(clk,microcode_net) begin if clk'event and clk='1' then microcode_reg <= microcode_net; end if; end process; next_address_reg <= microcode_reg(4 downto 0);

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next_address_from_microdecoder <= next_address_reg; TY_from_microdecoder <= microcode_reg(11 downto 10); process(microcode_reg) begin case microcode_reg(9 downto 5) is when "00001" => ALU_src1 <= "000"; ALU_src2 <="000"; ALU_fun_sel <="00"; IR_IRE_en <= '0'; ALU_en <= '0'; flag_reg_update_en <='0'; DM_en <='0'; IM_en <='0'; SW_en <='0'; Din_sel <="00"; Dout_sel <="00"; A0_sel <="000"; PC_sel <='1'; T2_sel <="000"; data_regset_xsel <="00"; data_regset_ysel <="00"; when "00110" => ALU_src1 <= "000"; ALU_src2 <="000"; ALU_fun_sel <="00"; IR_IRE_en <= '1'; ALU_en <= '0'; flag_reg_update_en <='0'; DM_en <='0'; IM_en <='0'; SW_en <='0'; Din_sel <="00"; Dout_sel <="00";

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A0_sel <="000"; PC_sel <='1'; T2_sel <="000"; data_regset_xsel <="00"; data_regset_ysel <="00"; when "10000" => ALU_src1 <= "011"; ALU_src2 <="011"; ALU_fun_sel <="10"; IR_IRE_en <= '0'; ALU_en <= '1'; flag_reg_update_en <='1'; DM_en <='0'; IM_en <='0'; SW_en <='0'; Din_sel <="00"; Dout_sel <="00"; A0_sel <="000"; PC_sel <='0'; T2_sel <="000"; data_regset_xsel <="00"; data_regset_ysel <="00"; when "10001" => ALU_src1 <= "001"; ALU_src2 <="001"; ALU_fun_sel <="00"; IR_IRE_en <= '0'; ALU_en <= '1'; flag_reg_update_en <='0'; DM_en <='0'; IM_en <='1'; SW_en <='0'; Din_sel <="00"; Dout_sel <="00";

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A0_sel <="100"; PC_sel <='0'; T2_sel <="000"; data_regset_xsel <="00"; data_regset_ysel <="11"; when others => ALU_src1 <= "ZZZ"; ALU_src2 <="ZZZ"; ALU_fun_sel <="ZZ"; IR_IRE_en <= 'Z'; ALU_en <= 'Z'; flag_reg_update_en <='Z'; DM_en <='Z'; IM_en <='Z'; SW_en <='Z'; Din_sel <="ZZ"; Dout_sel <="ZZ"; A0_sel <="ZZZ"; PC_sel <='Z'; T2_sel <="ZZZ"; data_regset_xsel <="ZZ"; data_regset_ysel <="ZZ"; end case; end process; end Behavioral;

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5. Simulation Results References

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