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Unit-1 - Binary Counter

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138 views7 pages

Unit-1 - Binary Counter

Uploaded by

Manesh Patel
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Assi. Prof.

MANESH PATEL
PRESIDENT INSTITUTE OF COMPUTER APPLICAION COLLEGE, SHAYONA CAMPUS, A’BAD

BCA SEM: 3 Unit-1 - Binary Counter COMP

 Counter is a device that stores (and sometimes displays) the number of


times a particular event or process has occurred. Often in relationship to a
clock.
 A binary counter can counter from 0 to 2(n-1), where n is the total number of bits in the
counter.
 The counter increases its count by one whenever a clock pulse occurs.
 A counter that pursues the binary number sequence is known as a binary counter.

 A sequence of binary numbers including 0000, 0001, 0010, 0011, etc.

Types of Binary Counters

There are many types of binary counters present. Some common types of binary counters
are defined as follows −
 Asynchronous Counter –
 This type of binary counter in which the flip flops do not receive the same clock
pulse at the same time is called an asynchronous counter.
 The asynchronous counter is also known as ripple counter.
 It is the simplest type of binary counter.
 In the case of asynchronous binary counter, each flip flop is triggered by the
output of the previous flip flop.
 Therefore, the asynchronous counters suffer from propagation delay.

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 Synchronous Counter –
 This type of binary counter in which all the flip flops receive the same clock
pulse at the same time is known as a synchronous counter.
 Since, all the flip flops of the synchronous counter are triggered by the same
clock pulse, therefore, their outputs change simultaneously.
 This will result in the no propagation delay between the flip flops.

 Up Counter –

 This type of binary counter that counts upwards from zero to its maximum count
value is known as up counter.
 In the case of up counter, the count is increased by one on each clock pulse.

 Down Counter –
 This type of binary counter that counts downwards from its maximum count
value to zero is known as a down counter.
 In the down counter, the count value of the counter is decreased by one on each
clock pulse.

 Up/Down Counter –

 This type of binary counter that can count in both upward and downward
directions is known as a up/down counter.
 In the up/down counter, the direction of count is determined by a control input
signal

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Difference

S.NO Synchronous Counter Asynchronous Counter


In asynchronous counter main clock is only
In synchronous counter we use a applied to the first flip flop and then for rest
universal clock that is common to of flip flops the output of previous flip flop is
1. all flip flops through out the circuit. taken as a clock.
Synchronous Counter is faster in
operation as compared to Asynchronous Counter is slower as compared
2. Asynchronous Counter. to synchronous counter in operation.
Synchronous Counter does not Asynchronous Counter produces decoding
3. produce any decoding errors. error.
Synchronous Counter is also called Asynchronous Counter is also called Serial
4. Parallel Counter. Counter.

Synchronous Counter designing is Asynchronous Counter designing is very


5. complex. easy.
Synchronous Counter will operate Asynchronous Counter will operate only in
6. in any desired count sequence. fixed count sequence (UP/DOWN).
Asynchronous Counter examples
Synchronous Counter examples are: Ripple UP counter, Ripple DOWN
7. are: Ring counter, Johnson counter. counter.
In synchronous counter, In asynchronous counter, there is high
8. propagation/output delay is less. propagation/output delay

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PREPARED BY: PATEL MANESH - M.Sc(CA & IT), B.ED Contact: 90165 17796 3
PATEL MANESH

4 bit asynchronous
4 bit = 4 Flip flops
2n = 24 = 16 total number of states
Maximum count = 2n-1 = 24-1 = 16-1 = 15

Truth Table

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PREPARED BY: PATEL MANESH - M.Sc(CA & IT), B.ED Contact: 90165 17796 4
PATEL MANESH

4 bit Synchronous
 Synchronous binary counters have a normal pattern, as can be view from the 4-bit
binary counter demonstrated in the diagram.

 The C inputs of all flip-flops obtain the common clock.

 If the count allow is 0, all J and K inputs are supported at 0 and the output of the
counter does not modify.

 The first stage A0 is complemented when the counter is allowed and the clock goes
through a positive transition.
 Each of the other three flip-flops is complemented when all preceding smallest
significant flip-flops are similar to 1 and the count is allowed.
 The chain of AND gates creates the needed logic for the J and K inputs.
 The output carry can be used to develop the counter to further procedures, with each
procedure having an extra flip-flop and an AND gate.

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PATEL MANESH

Timing Diagram

Truth Table

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PREPARED BY: PATEL MANESH - M.Sc(CA & IT), B.ED Contact: 90165 17796 6
PATEL MANESH

3 bit Synchronous and Asynchronous


Truth Table

Q2 Q1 Q0 Q2 Q1 Q0

For objective question

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