ARM ARCHITECTURE

INTRODUCTION OF ARM:

• Arm stands for Advance RISC Machine, was developed by ARCON Computers, but
Later that company have renamed as ARM, Acorn developed a 32-bit RISC processor.
• Arm does not make different applications, make only CPU Core.
• With IC there will be having CPU core, That is designed by the Arm Company.
• The Arm is a 16bit/32bit RISC Architecture.
• Most ARM's implement two Instruction sets.Such as

• A] 32 -bit Arm instruction set [for data processing and I/O device control]
• B}16 -bit Thumb instruction set.[for data processing and I/O device control]
• ARM Data types are following below:
• 1]Byte means 8 bits
• 2]Half-word means 16 bits[2 bytes]
• 3]Word means 32 bits[4 bytes]
• ARM is 32-bit Reduced Instruction Set Computer (RISC) Reduced Instruction Set
Architecture (ISA) Developed by ARM Holdings.
• Arm Processor Core is the Central Processing Unit (CPU) of Microcontroller Chip
• Arm Holds all the copyrights for the Architecture, Set of Instructions, Registers,
Memory maps, and timings of the ARM CPU.
• The ARM7TDMI Processor is based on the ARMV4T Processor.
• The Arm7tdmi Supports two instructions sets:
1. Arm instruction set with 32-bit instructions (the instruction size is 32 -bits)
2. Thumb instruction set with 16-bit instructions(the instruction size is 16-bits)
• •Processor cores: ARM6, ARM7, ARM9, ARM10, ARM11

• •Extensions: Thumb, El Segundo, Jazelle etc.

1) ARM-32-BIT INSTRUCTION SET:

• When the CPSR is set to zero[0], then its Arm Mode.

• Instruction size is 32 bits and core instructions are around 68.

• It is widely used for high end Applications such as Mobile Devices, Embedded Systems, Consumer
Electronics, Network Equipment, Automotive Systems and more.

• It has Less code Density.

• 15 General Purpose Registers + Program Counter.

1) ARM-16-BIT INSTRUCTION SET:
• When the CPSR is set to zero[1], then its Thumb Mode.

• Instruction size is 16 bits and core instructions are around 30.

• It is widely used for Low end Applications such as Microcontrollers, Wearable Devices, IOT Devices,
Automotive Applications, Battery Powerd Devices and more.

• It has High code Density.

• 7 General Purpose Registers + 8 High Level Register+Program Counter.

v CPSR Flag Register:

• D31,d30,d29,d28 d7,d6,d5,d4,d3,d2,d1,d0

• D0 to d4 [These bits indicated the arm of 7 operating modes]

• 1.User
• 2.FIQ
• 3.IRQ
• 4.Supervisior
• 5.abort
• 6.system
• •D5[indicated Thum instruction mode ,if this bit is set =1,then Thum mode, if incase is
set to '0' then ARM mode]
• •D6[fast interrupt mode, if this bit is set '1' then FIQ masked, if incase is set to '0' then
FIQ unmasked mode]
• D7 [IRQ mode, it means normal interrupt mode ,if this bit is set to '1' then IRQ
masked mode, if is set to '0' then IRQ unmasked mode,
• D8 to d27 [not working on the ARM processor]
• D28 [over flow flag]
• D29[carry flag]
• D30[zero flag]
• D31[negative flag]
Ø FAST INTERRUPT REQUEST[FIQ]:
• In Arm Architecture, The term FIQ stands for Fast Interrupt Request, The FIQ is
type of Interrupt in the Arm Processor. That has Higher Prority then the Normal
interrupt requests[IRQ].
• When FIQ occures, The processor can quickly switches to different mode to
handle it, and providing fast response time then the Normal interrupt
requests[IRQ].
• The term FIQ MASKED refers to the condition, that means that where the FIQ
interrupts are temporarly disable or masked. this means that the processor
ignores FIQ even if they occurs.
• if FIQ is masked, it means that The Fast interrupt request line is temporarly
disabled, and the processor won’t responds to FIQ untill is unmasked.
• Interrupts are generally controlled through the Nested Vector Interrupt
Controller[NVIC]
RISC COMPUTER ARCHITECTURE:
Ø Simple instruction, since simple instruction decoding.
Ø Instruction takes a single clock cycle to get execute.
Ø Less memory access is need to complete an instruction.
Ø More general purpose registers.
Ø Simple addressing modes.
Ø A pipeline can be Achieved.
Ø RISC Architecture Processor consume less power than CISC Architecture Processor.
• Disadvantages:
1. Risc Processor require more memory to store the additional instructions needed to
perform complex taasks.
2. Risc Processor requires more instructions to perform complex instructions then CISC
Processor.
CISC COMPUTER ARCHITECTURE:
Ø Complex instructions, hence complex instruction decoding.
Ø Instructions may take more than a single clock to get execute.
Ø Instructions can perform complex operations.
Ø Less number of general purpose registers as operation get performed in
memory itsef.
Ø Complex addressing modes.
• Disadvantages:
1. CISC Processor Consumes more power.
2. CISC Processor takes a longer time to execute instructions because they have
more complex instructions.
MODES OF ARM:

• Basically we have 7 operating mode on arm ,lets we must should know about memory
types in arm, they are typically two memory, one system memory and user memory.
• When you Turn on the system or Reset the system, at the time Arm will go inside
Supervisior Mode. In the Supervisior Mode, there will be having BIOS/OS Programs,
• During this time, It will execute BIOS/OS Programs, Once setup is completed, It will
entered into the USER MODE.
• If User wants to execute The BIOS/OS Programs,then User will invoke the Supervisior
Mode,by Executing some Software Interrupts [SWI].
• The BIOS/OS Programs will be contained in the System Memory.
• If User wants to access The complete Memory,and CPSR, Then User can Invoke SYSTEM
MODE.
• In the System Mode, Its contained full control of CPSR and Overall Memory.
• IRQ-MODE and FIQ-MODE.
• In the USER MODE will be having User code,and Program. If User want to access The
system code and Program, then will invoked to the ABORT MODE.
• If User want to execute the undefined instructions in the code, then will invoked to the
UNDEFINED MODE.
v ARM PIPELINING :
• In early Microprocessor such as 8085, The CPU could either fetch or execute at given time.
• In other words, the CPU had to fetch an instruction from memory, decode and then
Execute it and then fetch the next instruction, decode and execute it,
• A pipeline Technique is mostly used in CPU design to increase the speed of execution of
Instructions.
• Arm 7 has 3 stage pipelining, such as Fetch, decode, executing.
FEATURES OF ARM:

• It is initially developed by Arcon Computer in the year of 1980, All CPU's are designed by
ARM that is based on RICS architecture.
• ARM 7 has 32 bits of ALU &MAC
• ARM 7 has 32 bits of data bus with aligned memory space[ means with one machine cycle
it will execute 32 bits via data bus.
• ARM 7 has all the instruction with 32 bits of size.
• ARM 7 has 32 bits of address bus.[so we can interface 4GB memory with it directly]
• ARM 7 has follows Von-Neuman Architecture [so 4GB of memory is common for both data
and program ]
• ARM 7 has 7 operating mode.
• ARM 7 has 3 stage pipelining.
• Fetch, decode, execute.
• ARM 7 has 37 registers ,at a time only 16 general purpose register are avaliable
[R0-R15]
• ARM 7 has load and Store architecture, it means to store the data from memory and
load the data into the register ,so we have two separate instructions required.
• ARM 7 has 7 interrupts / exceptional
• ARM 7 has 7 addressing modes.
• ARM 7 has data frames [8 bits -byte, 16 bits- half word, 32 bits –word]
ARM-CORTEX-A:

• Which stands for Application Processor.

• These are Application Processor, which are designed to provide High Performance and include
features to support advanced Operating Systems (eg: Andriod, Linux, Windows, IOS)
• Cortex-A has very good response time and also has ARM set of instructions.
• The CPU is mainly used for High performance applications.
• It will consumed more power upto 80uw/mhz.
• It has Long Pipeline and also clock is high.
• It has Cache Memory with more size.
• It has Optional Floating Point unit [FPU]
APPLICATION OF CORTEX-A:

§ Laptops and Notpad.

§ Smart TV’s and set-top boxes.
§ Automotive infotainment systems.
§ Embedded Systems.
§ Networking Equipments.
§ Home Automation and IOT devices.
§ Mobile Devices, Tablets.
§ Medical Devices.
ARM-CORTEX-R:

• The performance Demonstrated of the Cortex-R is very High, and Response time is
good.
• The processor is used for the Real time Applications [RTOS].
• It has Medium Pipeline,and also High Clock.
• The Processor has set of ARM Instructions.
• It will consume the power up to the value of 120uw/mhz.
• It has Cache Memory with Tightly coupled Memory.
• It needs Floating Point Unit [FPU]
APPLICATIONS OF CORTEX-R:

§ Automotive Systems.
§ Aerospace and Defense.
§ Industrial Control Systems.
§ Medical Devices.
§ Railway Systems.
§ Automated Test Equipment.
§ Robotics.
ARM-CORTEX-M:

• The Processor has Medium Response Time and Performance.

• It has short Pipeline.
• It will consume the power upto 8uw/mhz.
• The Processor is designed for specifically for Embedded System Applications.
• It has less Clock compared to other series Microprocessors.
• It has Thumb set of Instructions.
• It has Cache Memory with less size.
• It need Floating Point Unit for Optional [FPU]
APPLICATIONS OF CORTEX-M:

§ Microcontrollers.
§ IOT Devices.
§ Wireless Communications.
§ Motor Control.
§ Audio Processing.
§ Security Systems.
§ Automated Control Systems.
CACHE MEMORY:

• •It is small memory,and it is SRAM,High speed memory,and temparory storage

memory,it has fast data access.
• •cache memory holds recently&frequently accessed fiels.
• cache memory may be on chip or off chip of the microcontroller or microprocessor.

cache primary
cpu mem secondary
memory memory
• Accessig of the data from CPU is very fast.
• The data and Program are transferred from primary or secondary memory to cache memory by
OS.

• if data is not avaliable in cache memory then by different memory mapping schemes,data will
be mapped to cache memory.
• it is very nearest to CPU.
• when CPU is accessing data from cache and if it is Avaliable with cache memory then operation
will be SuperFast.
• operating system OS updates currently accessed files into cache memory for faster execution of
programs.
FLOATING POINT UNIT[FPU]:

• The Floating Point Unit[FPU] is a math Coprocessor designed to carry out

operations on floating point numbers.
• FPU is an Optional, some Cortex-m4 do not have an FPU,
• A Floating Point Number can be single precision, which is declared as Float in C,
and can be Double Precision, which is declared as Double in C.
• For Float, 32 bit are used to represent a Floating point number.
• For Double, 64 bit are used to represent a Floating point number.
Ø This sample c program calculate the area of rectangular.
• float area_reactangle(float length, float width)
• {
• float area;
• area = length * width;
• return area;
• }

The Floating Point multiplication is directly performed by the FPU. without using any
software library.
Ø some key reasons for having an FPU in ARM Cortex-A,R series microprocessors:
1. Improved Performance.
2. Graphics Processing.
3. Digital Signal Processing.
4. Compatibility with Software Libraries.
5. precision.
• ARM-CORTEX-A5
Ø The Cortex-A5 MPCore processor is a high-performance, low-power, ARM macrocell with
an L1 cache subsystem that provides full virtual memory capabilities.
Ø Up to four individual cores can be linked in a cache-coherent cluster, under the control of
a Snoop Control Unit (SCU), that maintains L1 data cache coherency for memory marked
as shared.
Ø The Cortex-A5 MPCore processor implements the ARMv7 architecture and runs 32-bit
ARM instructions, 16-bit and 32-bit Thumb instructions, and 8-bit Java bytecodes in Jazelle
state.
Ø The Cortex-A5 MPCore processor consists of:
Ø up to four Cortex-A5 cores
Ø an SCU responsible for maintaining coherency among L1 data caches
Ø an Interrupt Controller (IC) with support for legacy ARM interrupts
Ø The Cortex-A5 processor is a high performance, low power,
Ø It features a level 1 (L1) cache for both instructions and data, typically with sizes
ranging from 8 KB to 32 KB.
Ø a private timer and a private watchdog per processor
Ø a global timer
Ø one or two AXI high-speed Advanced Microprocessor Bus Architecture (AMBA)
L2 interfaces.
Ø an Acceleration Coherency Port (ACP), an optional AXI 64-bit slave port that can
be connected to a noncached peripheral such as a DMA engine.
CORTEX-A5 PROCESSOR BLOCK DIAGRAM(OR) TOP LEVEL DIAGRAM:
ARM-CORTEX-A5 MICROPROCESSOR ARCHITECTURE:
PERIPHERALS OF ARM-CORTEX-A5 MICROPROCESSOR ARCHITECTURE:

Ø NEON SIMD(Single Instruction, Multiple Data):

• NEON is an SIMD architecture extension that provides additional instruction sets for
accelerating multimedia and signal processing operations. It enables parallel processing of
multiple data elements in a single instruction, improving performance for certain types of
applications.
Ø ARMv7 32b CPU:
• The core is the central processing unit (CPU) responsible for executing instructions. In the
case of the Cortex-A5, it is an ARM processor core. It handles instruction fetch, decode,
execution, and manages the overall flow of program execution.
Ø I-Cache (Instruction Cache):
• Size Range: 4 KB to 64 KB
• The Instruction Cache (I-Cache) is a small, high-speed memory unit that stores copies of
frequently used instructions. The I-Cache is positioned close to the processor core,
allowing for rapid access to instructions during program execution. When the processor
needs to fetch an instruction, it first checks the I-Cache. If the instruction is found in the
cache (a cache hit), it can be quickly retrieved. If the instruction is not present (a cache
miss), it needs to be fetched from the slower main memory.
• Purpose: The primary purpose of the I-Cache is to reduce the time it takes to fetch
instructions, as fetching from the cache is faster than fetching from the main memory.
This helps improve the overall performance of the processor by reducing the latency of
instruction fetch operations.
Ø D-Cache (Data Cache):
• Size Range: 4 KB to 64 KB
• The Data Cache (D-Cache) is another small, high-speed memory unit that stores copies of
frequently used data. It is used to cache data that the processor reads from or writes to
memory. Similar to the I-Cache, the D-Cache allows the processor to quickly access
frequently used data without having to wait for it to be fetched from the main memory.
• Purpose: The primary purpose of the D-Cache is to improve data access times. By storing
frequently used data in the cache, the processor can reduce the time spent waiting for
data to be retrieved from slower main memory. This is particularly beneficial for
applications that exhibit temporal locality, where the same data is accessed repeatedly
within a short period.
Ø ACP - Accelerator Coherency Port:
• The Accelerator Coherency Port (ACP) is a component that provides a high-bandwidth and
low-latency connection between the processor core and certain accelerators or co-
processors.
• It plays a role in ensuring data coherency in systems where multiple processing units, such
as the CPU and co-processors, need to access shared data.

Ø SCU - Snoop Control Unit:

• The Snoop Control Unit (SCU) is responsible for managing the cache coherency in a multi-
core or multi-processor system.
• It monitors and controls the flow of cache-related information between different
processor cores, ensuring that each core has a consistent view of the shared memory.
Ø Debug and Trace Components:
• The Cortex-A5 architecture includes components for debugging and tracing. These
features assist developers in identifying and fixing software issues by providing insights
into program execution, memory access, and other system events.
Ø Bus Interfaces:
• Bus interfaces provide connectivity between the core and other components, including
memory, peripherals, and external devices. They manage the data and control signals that
facilitate communication within the system.
Ø AMBA Interface:
• AMBA (Advanced Microcontroller Bus Architecture) is a set of specifications developed by
ARM (Advanced RISC Machines) for designing on-chip communication buses. The AMBA
interface is widely used in ARM-based systems.
• The primary components of the AMBA interface include the following:
ü AMBA Advanced High-performance Bus (AHB):
• AHB is a high-performance bus protocol designed for connecting high-speed modules like
processors and memory. It supports multiple masters and slaves in a hierarchical structure
and provides a burst transfer mode for efficient data transfer.

ü AMBA Advanced Peripheral Bus (APB):

• APB is a lower-performance bus protocol designed for connecting peripherals with slower
data rates. It is suitable for connecting devices like timers, UARTs, and I/O controllers.
ü AMBA Advanced eXtensible Interface (AXI):
• AXI is an evolution of AHB and is designed for high-performance and high-frequency
applications. AXI supports burst transfers, out-of-order data transfers, and a more flexible
and scalable interconnect.
ü AMBA Advanced Trace Bus (ATB):
• ATB is used for trace and debug purposes, enabling the collection of trace information
from different components in the system.
ü AMBA Advanced Debug Bus (ADeB):
• ADeB provides an interface for debugging and trace purposes.

ü AMBA Interconnects:
• AMBA Crossbar Switch: A crossbar switch is a common type of interconnect used to
connect multiple masters to multiple slaves. It allows efficient communication between
different IP blocks by providing simultaneous connections.
• AMBA Matrix Switch: A matrix switch is another type of interconnect that allows flexible
connections between masters and slaves in a matrix configuration.
ü AMBA System Components:
• AMBA Bridge: A bridge is used to connect different versions of AMBA buses, allowing
components with different bus protocols to communicate seamlessly.
• AMBA Memory Controller: Memory controllers are responsible for managing the flow of
data between the processor and external memory devices, ensuring efficient and timely
access to memory.
• AMBA DMA Controller: DMA (Direct Memory Access) controllers manage data transfers
between memory and peripherals without involving the processor, improving system
performance.
• AMBA Peripherals: Various peripherals such as UARTs, timers, GPIO controllers, and more
are designed to comply with the AMBA specifications, ensuring compatibility and ease of
integration.
Ø Floating-Point Unit (FPU):
• The Floating-Point Unit handles floating-point arithmetic operations, providing hardware
support for tasks involving real numbers with fractional parts. This is particularly beneficial
for applications requiring precise mathematical calculations.
Ø Memory Protection Unit (MPU):
• The Memory Protection Unit (MPU) is a hardware component within a microprocessor
that provides memory management and protection features.
• It enables the enforcement of access control policies on memory regions to prevent
unauthorized access, enhance system security, and ensure reliable and controlled
execution of software.
Ø Global Interrupt Controller (GIC):
• In systems with multiple processors or cores, the Global Interrupt Controller manages
interrupts at a system level. It ensures proper handling and distribution of interrupts
across all processors.
• GICv1: Basic interrupt handling capabilities.
• GICv2: Enhanced features, including support for priority levels and preemption.
• GICv3: Further enhancements, including support for virtualization.
• Number of Interrupt Lines:
• The GIC supports a variable number of interrupt lines. The actual number depends on the
GIC version and the specific configuration of the SoC.
• Priority Levels:
• The GIC supports multiple priority levels for interrupts. The number of priority levels is
determined by the GIC version and configuration.
• Interrupt Sources:
• Interrupts can be sourced from various peripherals and system events. Common sources
include timers, UARTs, GPIOs, external devices, and system exceptions.
ARM-CORTEX-A5 REGISTERS:
FEATURES OF ARM-CORTEX-A5 MICROPROCESSOR:

Ø The Arm Cortex -A5 is a single core Processor.

Ø The Arm Cortex-A5 is designed to offer a good balance between performance and
power Efficiency.
Ø It has 8-stage-Pipeline, which is the key component of Modern Processor Design.
Ø and it break down the flow of instructions Execution into the multiple stages.

Ø a) Fetch:
Ø In the stage, The Processor fetches the instructions from the memory, The Program
Counter is used to determine the address of the next instruction to be fetched.

Ø b) Decode:
Ø The fetched Instruction is decoded in the stage. The Processor determines the type of
instructions and Identifies the Operands.
Ø c) Issue:
Ø In the Issue Stage, The Processor Issue the Instructions to the Executive Unit.

Ø d)Execute:
Ø In the Stage, The Arthmatic and logic operations are involved.
Ø Depending on the instructions, it may invloved [ALU] operations.
Ø e) Memory Access:
Ø In the stage, if the instructions involves memory access, such as Load and Store
operations.
Ø The memory Access stage is where the data read from or write in to the memory.
Ø f) Write Back:
Ø In the stage, The results of the executed instructions are written back to the register,
Ø The Processor updates the register value.
Ø g) Exception:
Ø In the stages handles the exceptions and interrupts,
Ø h) Control:
Ø In the stage, manage the overall control and coordination of the pipeline stages.
Ø Clock speeds for Cortex-A5 cores can vary depending on the implementation
and application requirements. They typically operate in the range of a few
hundred megahertz to around 1 GHz.
Ø The Arm Cortex -A5 Processor implements The ETM architecture,
Ø The term "Trace Macrocell" typically refers to a hardware component designed
for debugging and performance analysis in microprocessor systems.
Ø In the context of ARM processors, including the Cortex-A5, the Trace Macrocell
(TMC) is often associated with ARM's Embedded Trace Macrocell (ETM).
PERIPHERALS :

Ø LCD TFT controller (LCDC) up to 1024x768 or 1280x768 (still image). Four overlays,
rotation, post-processing and alpha blending, 24-bit parallel RGB interface
Ø ITU-R BT. 601/656/1120 Image Sensor Controller (ISC) supporting up to 5 Mpixel sensors
with a parallel 12-bit interface for Raw Bayer, YCbCr, Monochrome and JPEG-compressed
sensor interface
Ø Two Synchronous Serial Controllers (SSC), two Inter-IC Sound Controllers (I2SC), and one
Stereo Class D amplifier (CLASSD)
Ø One Peripheral Touch Controller (PTC) with up to 8 X-lines and 8 Y-lines (64-channel
capacitive touch)
Ø One Pulse Density Modulation Interface Controller (PDMIC)
Ø One USB device high-speed port (UDPHS) and one USB host high-speed port or two USB
host high-speed ports (UHPHS)
Ø One USB host high-speed port with a High-Speed Inter-Chip (HSIC) interface
Ø Two host/client Serial Peripheral Interfaces (SPI)
Ø Two Quad Serial Peripheral Interfaces (QSPI)
Ø Five FLEXCOMs (USART, SPI and TWI)
Ø Five UARTs
Ø Two host CAN-FD (MCAN) controllers with SRAM-based mailboxes, time- and event-
triggered transmission, and 32-bit Time Stamping Unit (TSU)
Ø One Rx only UART in backup area (RXLP)
Ø One Analog Comparator Controller (ACC) in backup area
Ø Two 2-wire interfaces (TWIHS) up to 400 Kbits/s supporting the I2C protocol and SMBUS
Ø One full-featured 4-channel 16-bit Pulse Width Modulation (PWM) controller
Ø Two 3-channel 32-bit Timer/Counters (TC), supporting basic PWM modes
Ø One 12-channel, 12-bit, Analog-to-Digital Converter (ADC) with resistive touchscreen
capability
DATA TYPES IN ARM-CORTEX-A5 MICROPROCESSOR:

• The Cortex-A5 processor supports the following data types:

• Byte 8 bits
• Halfword 16 bits
• Word 32 bits
• Doubleword 64 bits.
• Note:
• When any of these types are described as unsigned, the N-bit data value
represents a non-negative integer in the range 0 to +2N-1, using normal binary
format.
• When any of these types are described as signed, the N-bit data value
represents an integer in the range -2N-1 to +2N-1-1, using two’s complement
format.
MEMORY ARCHITECTURE OF ARM-CORTEX-A5:

• Memory Management Unit (MMU)

• 32-Kbyte L1 data cache, 32-Kbyte L1 instruction cache

• 128-Kbyte L2 cache configurable to be used as an internal SRAM

• One 128-Kbyte scrambled internal SRAM

• One 160-Kbyte internal ROM

• 64-Kbyte scrambled and maskable ROM embedding bootloader/Secure bootloader

• 96-Kbyte unscrambled, unmaskable ROM for NAND Flash BCH ECC table

• High-bandwidth scramblable 16-bit or 32-bit Double Data Rate (DDR) multiport dynamic RAM
controller supporting up to 512 Mbytes 8-bank DDR2/DDR3 (DLL off only) / DDR3L (DLL off only) /
LPDDR1/LPDDR2/LPDDR3, including “on-the-fly” encryption/decryption path

• 8-bit SLC/MLC NAND controller, with up to 32-bit Error Correcting Code (PMECC)
MEMORY MANAGEMENT UNIT[MMU]:

• The MMU works with the L1 and L2 memory system to translate virtual addresses to
physical addresses. It also controls accesses to and from external memory.
• The ARM v7 Virtual Memory System Architecture (VMSA) features include the following:
• Page table entries that support:
• 16 Mbyte supersections. The processor supports supersections that consist of 16 Mbyte
blocks of memory.
• 1 Mbyte sections
• 64 Kbyte large pages
• 4 Kbyte small pages
• 16 access domains
• Global and application-specific identifiers to remove the requirement for
context switch TLB flushes.
• Extended permissions checking capability.
Ø Memory Management System:
• The Cortex-A5 processor supports the ARM v7 VMSA including the TrustZone security
extension.
• The translation of a Virtual Address (VA) used by the instruction set architecture to a
Physical Address (PA) used in the memory system and the management of the associated
attributes and permissions is carried out using a two-level MMU.
MEMORY MAPPING ARM ARCITECTRE:

• Memory Mapping in ARM Architecture, involves assigning addresses to various memory

and devices, within the address space accessible to the ARM Processor.
• This mapping Provides astructured way for the processor to access different types of
memory and peripherals.
• Memory Mapping in ARM can be categorized in to Following ways:
• Virtual Memory Mapping.
• Phisical Memory Mapping.
• Memory Mapping I/O
• Phisical Memory Mapping:
• Phisical memory mapping involves assigning addresses to phisical memory locations, This
includes RAM, ROM, and more.............The memory mapping defines the address range
for these memory types..........
• Memory Mapped I/O:
• Memory mapped I/O extends the concept of memory mapping to peripherals and I/O
devices. In ARM Architecture, various peripherals are assigned specific memory
addresses.
• Reading and Writting to these addresses allows the processor to interact with
peripherals.
• This simples the programming interface.
• Virtual Memory Mapping:
• Virtual Memory Mapping invloves mapping virtual addresses used by software to
phisical addresses in the RAM.
APPLICATION OF ARM-CORTEX-A5 MICROPROCESSOR:

1. Embedded Systems:Cortex-A5 is widely used in embedded systems, including industrial

control systems, robotics, and automation applications. Its performance is suitable for
running control algorithms and managing interfaces with sensors and actuators.
2. Networking Equipment:Cortex-A5 is employed in networking devices such as routers,
switches, and network-attached storage (NAS) systems.
3. Automotive Systems: Cortex-A5 is found in automotive applications, including in-vehicle
infotainment (IVI) systems, navigation systems, and engine control units.
4. Smart TVs and Set-Top Boxes: Smart TVs and set-top boxes often use Cortex-A5
processors for multimedia playback, user interface management, and internet
connectivity.
5. IoT (Internet of Things) Devices: Cortex-A5 is suitable for IoT devices, including smart
home devices, environmental sensors, and edge computing devices.