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DRV8814
SLVSAB9E – MAY 2010 – REVISED NOVEMBER 2015

DRV8814 DC Motor Driver IC

1 Features 3 Description
•
1 8 V to 45 V Operating Supply Voltage Range The DRV8814 provides an integrated motor driver
solution for printers, scanners, and other automated
• 2.5 A Maximum Drive Current at 24 V and TA = equipment applications. The device has two H-bridge
25°C drivers, and is intended to drive DC motors. The
• Dual H-Bridge Current-Control Motor Driver output driver block for each consists of N-channel
– Drives Two DC Motors power MOSFET’s configured as H-bridges to drive
the motor windings. The DRV8814 can supply up to
– Four Level Winding Current Control 2.5-A peak or 1.75-A RMS output current (with proper
• Multiple Decay Modes heatsinking at 24 V and 25°C) per H-bridge.
– Slow Decay A simple parallel digital control interface is compatible
– Fast Decay with industry-standard devices. Decay mode is
• Industry Standard Parallel Digital Control Interface programmable to allow braking or coasting of the
motor when disabled.
• Low Current Sleep Mode
• Built-In 3.3-V Reference Output Internal shutdown functions are provided for over
current protection, short circuit protection, under
• Small Package and Footprint voltage lockout, and over temperature.
• Protection Features
The DRV8814 is available in a 28-pin HTSSOP
– Overcurrent Protection (OCP) package with PowerPAD™ (Eco-friendly: RoHS & no
– Thermal Shutdown (TSD) Sb/Br).
– VM Undervoltage Lockout (UVLO)
Device Information(1)
– Fault Condition Indication Pin (nFAULT)
PART NUMBER PACKAGE BODY SIZE (NOM)

2 Applications DRV8814 HTSSOP (28) 9.70 mm x 4.40 mm

(1) For all available packages, see the orderable addendum at
• Printers the end of the datasheet.
• Scanners
• Office Automation Machines
• Gaming Machines
• Factory Automation
• Robotics
Simplified Schematic
8 V to 45 V

PHASE DRV8814
+

ENBL 2.5 A M
Controller

Decay Mode
-

Stepper
Current Lvl Motor
nFAULT Driver
Current
2.5 A M
Control

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features .................................................................. 1 8 Application and Implementation ........................ 13
2 Applications ........................................................... 1 8.1 Application Information............................................ 13
3 Description ............................................................. 1 8.2 Typical Application .................................................. 13
4 Revision History..................................................... 2 9 Power Supply Recommendations...................... 15
5 Pin Configuration and Functions ......................... 3 9.1 Bulk Capacitance .................................................... 15
9.2 Power Supply and Logic Sequencing ..................... 15
6 Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5 10 Layout................................................................... 16
6.2 ESD Ratings.............................................................. 5 10.1 Layout Guidelines ................................................. 16
6.3 Recommended Operating Conditions....................... 5 10.2 Layout Example .................................................... 16
6.4 Thermal Information .................................................. 5 10.3 Thermal Considerations ........................................ 16
6.5 Electrical Characteristics........................................... 6 11 Device and Documentation Support ................. 18
6.6 Typical Characteristics .............................................. 7 11.1 Documentation Support ........................................ 18
7 Detailed Description .............................................. 8 11.2 Community Resources.......................................... 18
7.1 Overview ................................................................... 8 11.3 Trademarks ........................................................... 18
7.2 Functional Block Diagram ......................................... 8 11.4 Electrostatic Discharge Caution ............................ 18
7.3 Feature Description................................................... 9 11.5 Glossary ................................................................ 18
7.4 Device Functional Modes........................................ 10 12 Mechanical, Packaging, and Orderable
Information ........................................................... 18

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision D (August 2013) to Revision E Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1

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5 Pin Configuration and Functions

PWP Package
28-Pin HTSSOP with PowerPAD™
Top View

Pin Functions
PIN EXTERNAL COMPONENTS
I/O (1) DESCRIPTION
NAME NO. OR CONNECTIONS
POWER AND GROUND
GND 14, 28 - Device ground
VMA 4 - Bridge A power supply Connect to motor supply (8 V to 45 V). Both pins must be
connected to the same supply, bypassed with a 0.1-µF
VMB 11 - Bridge B power supply capacitor to GND, and connected to appropriate bulk
capacitance.
Bypass to GND with a 0.47-μF 6.3-V ceramic capacitor. Can be
V3P3OUT 15 O 3.3-V regulator output
used to supply VREF.
CP1 1 IO Charge pump flying capacitor
Connect a 0.01-μF 50-V capacitor between CP1 and CP2.
CP2 2 IO Charge pump flying capacitor
VCP 3 IO High-side gate drive voltage Connect a 0.1-μF 16-V ceramic capacitor and a 1-MΩ to VM.
CONTROL
AENBL 21 I Bridge A enable Logic high to enable bridge A
APHASE 20 I Bridge A phase (direction) Logic high sets AOUT1 high, AOUT2 low
AI0 24 I
Bridge A current set Sets bridge A current: 00 = 100%, 01 = 71%, 10 = 38%, 11 = 0
AI1 25 I
BENBL 22 I Bridge B enable Logic high to enable bridge B
BPHASE 23 I Bridge B phase (direction) Logic high sets BOUT1 high, BOUT2 low
BI0 26 I
Bridge B current set Sets bridge B current: 00 = 100%, 01 = 71%, 10 = 38%, 11 = 0
BI1 27 I
DECAY 19 I Decay (brake) mode Low = brake (slow decay), high = coast (fast decay)
Active-low reset input initializes internal logic and disables the
nRESET 16 I Reset input
H-bridge outputs
Logic high to enable device, logic low to enter low-power sleep
nSLEEP 17 I Sleep mode input
mode
AVREF 12 I Bridge A current set reference input Reference voltage for winding current set. Can be driven
individually with an external DAC for microstepping, or tied to a
BVREF 13 I Bridge B current set reference input reference (e.g., V3P3OUT).

(1) Directions: I = input, O = output, OZ = tri-state output, OD = open-drain output, IO = input/output

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Pin Functions (continued)

PIN EXTERNAL COMPONENTS
I/O (1) DESCRIPTION
NAME NO. OR CONNECTIONS
STATUS
nFAULT 18 OD Fault Logic low when in fault condition (overtemp, overcurrent)
OUTPUT
ISENA 6 IO Bridge A ground / Isense Connect to current sense resistor for bridge A
ISENB 9 IO Bridge B ground / Isense Connect to current sense resistor for bridge B
AOUT1 5 O Bridge A output 1
Connect to motor winding A
AOUT2 7 O Bridge A output 2
BOUT1 10 O Bridge B output 1
Connect to motor winding B
BOUT2 8 O Bridge B output 2

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range, unless otherwise noted. (1)
MIN MAX UNIT
Power supply voltage range VMx –0.3 47 V
Power supply ramp rate VMx 1 V/µs
Digital pin voltage range –0.5 7 V
Input voltage VREF –0.3 4 V
(2)
ISENSEx pin voltage –0.8 0.8 V
Peak motor drive output current, t < 1 μS Internally limited A
Continuous motor drive output current (3) 0 2.5 A
Continuous total power dissipation See Thermal Information
Operating virtual junction temperature range, TJ –40 150 °C
Operating ambient temperature range, TA –40 85 °C
Storage temperature, TSTG –60 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Transients of ±1 V for less than 25 ns are acceptable.
(3) Power dissipation and thermal limits must be observed.

6.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
(1)
VM Motor power supply voltage range 8 45 V
VREF VREF input voltage (2) 1 3.5 V
IV3P3 V3P3OUT load current 0 1 mA
fPWM Externally applied PWM frequency 0 100 kHz

(1) All VM pins must be connected to the same supply voltage.

(2) Operational at VREF between 0 V and 1 V, but accuracy is degraded.

6.4 Thermal Information

DRV8814
THERMAL METRIC (1) PWP (HTSSOP) UNIT
28 PINS
RθJA Junction-to-ambient thermal resistance 31.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 15.9 °C/W
RθJB Junction-to-board thermal resistance 5.6 °C/W
ψJT Junction-to-top characterization parameter 0.2 °C/W
ψJB Junction-to-board characterization parameter 5.5 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 1.4 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.

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6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLIES
IVM VM operating supply current VM = 24 V, fPWM 50 kHz 5 8 mA
IVMQ VM sleep mode supply current VM = 24 V 10 20 μA
VUVLO VM undervoltage lockout voltage VM rising 7.8 8.2 V
V3P3OUT REGULATOR
V3P3 V3P3OUT voltage IOUT = 0 to 1 mA 3.2 3.3 3.4 V
LOGIC-LEVEL INPUTS
VIL Input low voltage 0.6 0.7 V
VIH Input high voltage 2 5.25 V
VHYS Input hysteresis 0.3 0.45 0.6 V
IIL Input low current VIN = 0 –20 20 μA
IIH Input high current VIN = 3.3 V 33 100 μA
nFAULT OUTPUT (OPEN-DRAIN OUTPUT)
VOL Output low voltage IO = 5 mA 0.5 V
IOH Output high leakage current VO = 3.3 V 1 μA
DECAY INPUT
VIL Input low threshold voltage For slow decay (brake) mode 0 0.8 V
VIH Input high threshold voltage For fast decay (coast) mode 2 V
IIN Input current VIN = 0 V to 3.3 V ±40 μA
H-BRIDGE FETS
VM = 24 V, IO = 1 A, TJ = 25°C 0.2
RDS(ON) HS FET on resistance Ω
VM = 24 V, IO = 1 A, TJ = 85°C 0.25 0.32
VM = 24 V, IO = 1 A, TJ = 25°C 0.2
RDS(ON) LS FET on resistance Ω
VM = 24 V, IO = 1 A, TJ = 85°C 0.25 0.32
IOFF Off-state leakage current –20 20 μA
MOTOR DRIVER
fPWM Internal current control PWM frequency 50 kHz
tBLANK Current sense blanking time 3.75 μs
tR Rise time 50 300 ns
tF Fall time 50 300 ns
PROTECTION CIRCUITS
IOCP Overcurrent protection trip level 3 A
tTSD Thermal shutdown temperature Die temperature 150 160 180 °C
CURRENT CONTROL
IREF VREF input current VREF = 3.3 V –3 3 μA
xVREF = 3.3 V, 100% current setting 635 660 685
VTRIP xISENSE trip voltage xVREF = 3.3 V, 71% current setting 445 469 492 mV
xVREF = 3.3 V, 38% current setting 225 251 276
AISENSE Current sense amplifier gain Reference only 5 V/V

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6.6 Typical Characteristics

7 14

6.5
12
6

IVMQ (PA)
IVM (mA)

5.5 10

5
-40qC 8 -40qC
4.5 25qC 25qC
85qC 85qC
125qC 125qC
4 6
10 15 20 25 30 35 40 45 10 15 20 25 30 35 40 45
V(VMx) (V) D001
V(VMx) (V) D002

Figure 1. IVMx vs V(VMx) Figure 2. IVMxQ vs V(VMx)

750 750
-40qC 85qC
700 25qC 125qC 700
RDS(ON) HS + LS (m:)

RDS(ON) HS + LS (m:)
650 650

600 600

550 550

500 500

8V
450 450 24 V
45 V
400 400
8 13 18 23 28 33 38 43 -50 -25 0 25 50 75 100 125
V(VMx) (V) D003
TA (qC) D004

Figure 3. RDS(ON) vs V(MVx) Figure 4. RDS(ON) vs Temperature

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7 Detailed Description

7.1 Overview
The DRV8814 is an integrated motor driver solution for two brushed DC motors. The device integrates two
NMOS H-bridges, current sense, regulation circuitry, and detailed fault detection. The DRV8814 can be powered
with a supply voltage between 8 V and 45 V and is capable of providing an output current up to 2.5 A full-scale.
A PHASE/ENBL interface allows for simple interfacing to the controller circuit. The winding current control allows
the external controller to adjust the regulated current that is provided to the motor. The current regulation is
highly configurable, with two decay modes of operation. Fast and slow decay can be selected depending on the
application requirements.
A low-power sleep mode is included which allows the system to save power when not driving the motor.

7.2 Functional Block Diagram

VM VM

CP1
Internal Int. VCC
Reference & LS Gate 0.01mF
Regs Drive CP2
Charge VM
V3P3OUT Pump
3.3V VCP
3.3V 0.1mF
Thermal HS Gate
Shut down Drive 1MW
VM
AVREF VMA

BVREF
AOUT1

APHASE Motor
DCM
Driver A
AENBL AOUT2

AI0
ISENA
AI1

BPHASE

BENBL
Control VM
BI0 Logic
VMB
BI1
BOUT1
DECAY
Motor
DCM
nRESET Driver B
BOUT2
nSLEEP
ISENB
nFAULT

GND GND

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7.3 Feature Description

7.3.1 PWM Motor Drivers
The DRV8814 contains two H-bridge motor drivers with current-control PWM circuitry. A block diagram of the
motor control circuitry is shown in Figure 5.

OCP VM

VM
VCP, VGD

AOUT1

Pre-
AENBL drive DCM
APHASE
DECAY AOUT2

PWM

OCP

- AISEN

+ A=5

AI[1:0]
DAC
2

AVREF

VM
OCP
VM
VCP, VGD

BOUT1

Pre-
BENBL drive DCM
BPHASE
BOUT2

PWM

OCP

BISEN
-
+ A =5

BI[1:0]
DAC
2

BVREF

Figure 5. Motor Control Circuitry

NOTE
There are multiple VM pins. All VM pins must be connected together to the motor supply
voltage.

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7.4 Device Functional Modes

7.4.1 Bridge Control

The xPHASE input pins control the direction of current flow through each H-bridge, and hence the direction of
rotation of a DC motor. The xENBL input pins enable the H-bridge outputs when active high, and can also be
used for PWM speed control of the motor. Note that the state of the DECAY pin selects the behavior of the
bridge when xENBL = 0, allowing the selection of slow decay (brake) or fast decay (coast). Table 1 shows the
logic.

Table 1. H-Bridge Logic

DECAY xENBL xPHASE xOUT1 xOUT2
0 0 X L L
1 0 X Z Z
X 1 1 H L
X 1 0 L H

7.4.2 Current Regulation

The maximum current through the motor winding is regulated by a fixed-frequency PWM current regulation, or
current chopping. When the H-bridge is enabled, current rises through the winding at a rate dependent on the
DC voltage and inductance of the winding. Once the current hits the current chopping threshold, the bridge
disables the current until the beginning of the next PWM cycle.
For DC motors, current regulation is used to limit the start-up and stall current of the motor. Speed control is
typically performed by providing an external PWM signal to the ENBLx input pins.
If the current regulation feature is not needed, it can be disabled by connecting the xISENSE pins directly to
ground, and connecting the xVREF pins to V3P3.
The PWM chopping current is set by a comparator which compares the voltage across a current sense resistor
connected to the xISEN pins, multiplied by a factor of 5, with a reference voltage. The reference voltage is input
from the xVREF pins, and is scaled by a 2-bit DAC that allows current settings of 100%, 71%, 38% of full-scale,
plus zero.
The full-scale (100%) chopping current is calculated in Equation 1.
VREFX
ICHOP
5 u RISENSE (1)
Example:
If a 0.25-Ω sense resistor is used and the VREFx pin is 2.5 V, the full-scale (100%) chopping current will be
2.5 V / (5 x 0.25 Ω) = 2 A.
Two input pins per H-bridge (xI1 and xI0) are used to scale the current in each bridge as a percentage of the full-
scale current set by the VREF input pin and sense resistance. The function of the pins is shown in Table 2.

Table 2. H-Bridge Pin Functions

RELATIVE CURRENT
xI1 xI0
(% FULL-SCALE CHOPPING CURRENT)
1 1 0% (Bridge disabled)
1 0 38%
0 1 71%
0 0 100%

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NOTE
When both xI bits are 1, the H-bridge is disabled and no current flows.
Example:
If a 0.25-Ω sense resistor is used and the VREF pin is 2.5 V, the chopping current will
be 2 A at the 100% setting (xI1, xI0 = 00). At the 71% setting (xI1, xI0 = 01) the
current will be 2 A x 0.71 = 1.42 A, and at the 38% setting (xI1, xI0 = 10) the current
will be 2 A x 0.38 = 0.76 A. If (xI1, xI0 = 11) the bridge will be disabled and no current
will flow.

7.4.3 Decay Mode and Braking

During PWM current chopping, the H-bridge is enabled to drive current through the motor winding until the PWM
current chopping threshold is reached. This is shown in Figure 6 as case 1. The current flow direction shown
indicates the state when the xENBL pin is high.
Once the chopping current threshold is reached, the H-bridge can operate in two different states, fast decay or
slow decay.
In fast decay mode, once the PWM chopping current level has been reached, the H-bridge reverses state to
allow winding current to flow in a reverse direction. As the winding current approaches zero, the bridge is
disabled to prevent any reverse current flow. Fast decay mode is shown in Figure 6 as case 2.
In slow decay mode, winding current is re-circulated by enabling both of the low-side FETs in the bridge. This is
shown in Figure 6 as case 3.

Figure 6. Decay Mode

The DRV8814 supports fast decay and slow decay mode. Slow or fast decay mode is selected by the state of
the DECAY pin - logic low selects slow decay, and logic high sets fast decay mode. Note that the DECAY pin
sets the decay mode for both H-bridges.
DECAY mode also affects the operation of the bridge when it is disabled (by taking the ENBL pin inactive). This
applies if the ENABLE input is being used for PWM speed control of the motor, or if it is simply being used to
start and stop motor rotation.

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If the DECAY pin is high (fast decay), when the bridge is disabled fast decay mode will be entered until the
current through the bridge reaches zero. Once the current is at zero, the bridge is disabled to prevent the motor
from reversing direction. This allows the motor to coast to a stop.
If the DECAY pin is low (slow decay), both low-side FETs will be turned on when ENBL is made inactive. This
essentially shorts out the back EMF of the motor, causing the motor to brake, and stop quickly. The low-side
FETs will stay in the ON state even after the current reaches zero.

7.4.4 Blanking Time

After the current is enabled in an H-bridge, the voltage on the xISEN pin is ignored for a fixed period of time
before enabling the current sense circuitry. This blanking time is fixed at 3.75 μs. Note that the blanking time also
sets the minimum on time of the PWM.

7.4.5 nRESET and nSLEEP Operation

The nRESET pin, when driven active low, resets the internal logic. It also disables the H-bridge drivers. All inputs
are ignored while nRESET is active.
Driving nSLEEP low will put the device into a low power sleep state. In this state, the H-bridges are disabled, the
gate drive charge pump is stopped, the V3P3OUT regulator is disabled, and all internal clocks are stopped. In
this state all inputs are ignored until nSLEEP returns inactive high. When returning from sleep mode, some time
(approximately 1 ms) needs to pass before the motor driver becomes fully operational.

7.4.6 Protection Circuits

The DRV8814 is fully protected against undervoltage, overcurrent and overtemperature events.

7.4.6.1 Overcurrent Protection (OCP)

An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this
analog current limit persists for longer than the OCP time, all FETs in the H-bridge will be disabled and the
nFAULT pin will be driven low. The device will remain disabled until either nRESET pin is applied, or VM is
removed and re-applied.
Overcurrent conditions on both high and low side devices; i.e., a short to ground, supply, or across the motor
winding will all result in an overcurrent shutdown. Note that overcurrent protection does not use the current sense
circuitry used for PWM current control, and is independent of the ISENSEresistor value or VREF voltage.

7.4.6.2 Thermal Shutdown (TSD)

If the die temperature exceeds safe limits, all FETs in the H-bridge will be disabled and the nFAULT pin will be
driven low. Once the die temperature has fallen to a safe level operation will automatically resume.

7.4.6.3 Undervoltage Lockout (UVLO)

If at any time the voltage on the VM pins falls below the undervoltage lockout threshold voltage, all circuitry in the
device will be disabled and internal logic will be reset. Operation will resume when VMrises above the UVLO
threshold.

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8 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

8.1 Application Information

The DRV8814 can be used to control two brushed DC motors. The PHASE/ENBL interface controls the outputs
and current control can be implemented with the internal current regulation circuitry. Detailed fault reporting is
provided with the internal protection circuits and nFAULT pin.

8.2 Typical Application

DRV8814

CP1 GND
0.01 µF
CP2 BI1

VCP BI0
0.01 µF 1 MΩ 0.1 µF
VMA AI1

AOUT1 AI0
+

200 mΩ
VM Brushed DC ISENA BPHASE
Motor
-

+ AOUT2 BENBL
100 µF
BOUT2 AENBL
-

200 mΩ
Brushed DC ISENB APHASE
Motor V3P3OUT
+

BOUT1 DECAY
10 kΩ
VMB nFAULT
0.01 µF V3P3OUT
AVREF nSLEEP
10 kΩ
BVREF nRESET
PPAD

30 kΩ V3P3OUT
GND V3P3OUT
0.47 µF

Figure 7. Typical Application Schematic

8.2.1 Design Requirements

Specific parameters for designing a dual brushed DC motor drive system.

Table 3. Design Parameters

DESIGN PARAMETER REFERENCE EXAMPLE VALUE
Supply Voltage VM 24 V
Motor Winding Resistance RL 3.9 Ω
Moto Winding Inductance IL 2.9 mH
Sense Resistor Value RSENSE 200 mΩ
Target Full-Scale Current IFS 1.25 A

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8.2.2 Detailed Design Procedure

8.2.2.1 Current Regulation

In a stepper motor, the set full-scale current (IFS) is the maximum current driven through either winding. This
quantity depends on the xVREF analog voltage and the sense resistor value (RSENSE). During stepping, IFS
defines the current chopping threshold (ITRIP) for the maximum current step. The gain of DRV8814 is set for 5
V/V.
xVREF(V) xVREF(V)
IFS (A)
A v u RSENSE (:) 5 u RSENSE (:) (2)
To achieve IFS = 1.25 A with RSENSE of 0.2 Ω, xVREF should be 1.25 V.

8.2.2.2 Decay Modes

The DRV8814 supports two different decay modes: slow decay and fast decay. The current through the motor
windings is regulated using a fixed-frequency PWM scheme. This means that after any drive phase, when a
motor winding current has hit the current chopping threshold (ITRIP), the DRV8814 places the winding in one of
the two decay modes until the PWM cycle has expired. Afterward, a new drive phase starts. The blanking time,
tBLANK, defines the minimum drive time for the current chopping. ITRIP is ignored during tBLANK, so the winding
current may overshoot the trip level.

8.2.2.3 Sense Resistor

The power dissipated by the sense resistor equals Irms2 × R. For example, if the rms motor current is 2-A and a
100-mΩ sense resistor is used, the resistor dissipates 2 A2 × 0.1 Ω = 0.4 W. The power quickly increases with
greater current levels.
Resistors typically have a rated power within some ambient temperature range, along with a derated power curve
for high ambient temperatures. When a PCB is shared with other components generating heat, margin should be
added. It is always best to measure the actual sense resistor temperature in a final system, along with the power
MOSFETs, as those are often the hottest components.
Because power resistors are larger and more expensive than standard resistors, it is common practice to use
multiple standard resistors in parallel, between the sense node and ground. This distributes the current and heat
dissipation.

8.2.3 Application Curves

Figure 8. Direction Change Figure 9. Current Limiting

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www.ti.com SLVSAB9E – MAY 2010 – REVISED NOVEMBER 2015

9 Power Supply Recommendations

The DRV8814 is designed to operate from an input voltage supply (VMx) range from 8 V to 45 V. Two 0.1-μF
ceramic capacitors rated for VMx must be placed as close as possible to the VMA and VMB pins respectively
(one on each pin). In addition to the local decoupling caps, additional bulk capacitance is required and must be
sized accordingly to the application requirements.

9.1 Bulk Capacitance

Bulk capacitance sizing is an important factor in motor drive system design. It is dependent on a variety of factors
including:
• Type of power supply
• Acceptable supply voltage ripple
• Parasitic inductance in the power supply wiring
• Type of motor (brushed DC, brushless DC, stepper)
• Motor start-up current
• Motor braking method
The inductance between the power supply and motor drive system limits the rate current can change from the
power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or
dumps from the motor with a change in voltage. You should size the bulk capacitance to meet acceptable
voltage ripple levels.
The data sheet generally provides a recommended value but system level testing is required to determine the
appropriate sized bulk capacitor.

Parasitic Wire
Inductance
Power Supply Motor Drive System

VM

+ + Motor
± Driver

GND

Local IC Bypass
Bulk Capacitor Capacitor

Figure 10. Setup of Motor Drive System With External Power Supply

9.2 Power Supply and Logic Sequencing

There is no specific sequence for powering-up the DRV8814. It is okay for digital input signals to be present
before VMx is applied. After VMx is applied to the DRV8814, it begins operation based on the status of the
control pins.

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10 Layout

10.1 Layout Guidelines

• The VMA and VMB pins should be bypassed to GND using low-ESR ceramic bypass capacitors with a
recommended value of 0.1-μF rated for VMx. This capacitor should be placed as close to the VMA and VMB
pins as possible with a thick trace or ground plane connection to the device GND pin.
• The VMA and VMB pins must be bypassed to ground using an appropriate bulk capacitor. This component
may be an electrolytic and should be located close to the DRV8814.
• A low-ESR ceramic capacitor must be placed in between the CPL and CPH pins. TI recommends a value of
0.01-μF rated for VMx. Place this component as close to the pins as possible.
• A low-ESR ceramic capacitor must be placed in between the VMA and VCP pins. TI recommends a value of
0.1-μF rated for 16 V. Place this component as close to the pins as possible. Also, place a 1-MΩ resistor
between VCP and VMA.
• Bypass V3P3 to ground with a ceramic capacitor rated 6.3 V. Place this bypass capacitor as close to the pin
as possible.

10.2 Layout Example

CP1 GND
0.1 µF
0.01 µF
CP2 BI1

VCP BI0
1 0Ÿ 0.1 µF
VMA AI1

AOUT1 AI0

ISENA BPHASE

RISENA AOUT2 BENBL

BOUT2 AENBL

ISENB APHASE

RISENB BOUT1 DECAY

VMB nFAULT
0.1 µF
+

AVREF nSLEEP

BVREF nRESET

GND V3P3OUT

0.47 µF

Figure 11. DRV8814 Layout Example

10.3 Thermal Considerations

10.3.1 Thermal Protection
The DRV8814 has thermal shutdown (TSD) as described in Thermal Shutdown (TSD). If the die temperature
exceeds approximately 150°C, the device will be disabled until the temperature drops to a safe level.
Any tendency of the device to enter TSD is an indication of either excessive power dissipation, insufficient
heatsinking, or too high an ambient temperature.

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 DRV8814
www.ti.com SLVSAB9E – MAY 2010 – REVISED NOVEMBER 2015

Thermal Considerations (continued)

10.3.2 Power Dissipation
Power dissipation in the DRV8814 is dominated by the power dissipated in the output FET resistance, or
RDS(ON). Average power dissipation when running a stepper motor can be roughly estimated by Equation 3.
2
PTOT 4 u RDS(ON) u IOUT(RMS)

where
• PTOT is the total power dissipation
• RDS(ON) is the resistance of each FET
• IOUT(RMS) is the RMS output current being applied to each winding
• IOUT(RMS) is equal to approximately 0.7 × the full-scale output current setting (3)
The factor of 4 comes from the fact that there are two motor windings, and at any instant two FETs are
conducting winding current for each winding (one high-side and one low-side).
The maximum amount of power that can be dissipated in the device is dependent on ambient temperature and
heatsinking.
RDS(ON) increases with temperature, so as the device heats, the power dissipation increases. This must be taken
into consideration when sizing the heatsink.

10.3.3 Heatsinking
The PowerPAD™ package uses an exposed pad to remove heat from the device. For proper operation, this pad
must be thermally connected to copper on the PCB to dissipate heat. On a multi-layer PCB with a ground plane,
this can be accomplished by adding a number of vias to connect the thermal pad to the ground plane. On PCBs
without internal planes, copper area can be added on either side of the PCB to dissipate heat. If the copper area
is on the opposite side of the PCB from the device, thermal vias are used to transfer the heat between top and
bottom layers.
For details about how to design the PCB, refer to TI application report PowerPAD™ Thermally Enhanced
Package, SLMA002, and TI application brief PowerPAD™ Made Easy, SLMA004, available at www.ti.com.
In general, the more copper area that can be provided, the more power can be dissipated.

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11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related Documentation
For related documentation see the following:
• PowerPAD™ Thermally Enhanced Package, SLMA002
• PowerPAD™ Made Easy, SLMA004

11.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

11.3 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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Product Folder Links: DRV8814

 PACKAGE OPTION ADDENDUM

www.ti.com 20-Oct-2014

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

DRV8814PWP ACTIVE HTSSOP PWP 28 50 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 DRV8814
& no Sb/Br)
DRV8814PWPR ACTIVE HTSSOP PWP 28 2000 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 DRV8814
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 20-Oct-2014

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 20-Oct-2014

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DRV8814PWPR HTSSOP PWP 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 20-Oct-2014

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DRV8814PWPR HTSSOP PWP 28 2000 367.0 367.0 38.0

Pack Materials-Page 2
 IMPORTANT NOTICE

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