UART Serial Port Programming

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Serial vs. Parallel Data Transfer

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• Serial data communication uses two methods,
asynchronous and synchronous.
• With synchronous communication, the clock is transmitted
alongside with the data.
• With asynchronous communication, no clock is transmitted.
• The transmitter and receiver agree on a clock speed for data
transmission. They may have slight speed differences so the
receiver will try to synchronize the clock to the incoming
data for every character received.

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• The synchronous method usually transfers a block of data (characters) at
a time while the asynchronous transfers a single byte at a time.
• It is possible to write software to use either of these methods, but the
programs can be tedious and inefficient. For this reason, special IC chips
are made by many manufacturers for serial data communications.
• These chips are commonly referred to as UART (universal asynchronous
receiver transmitter) and USART (universal synchronous-asynchronous
receiver-transmitter).
• The COM port in the PC uses a UART. When this function is incorporated
into a microcontroller, it is often referred to as SCI (Serial Communication
Interface).

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Parallel In – Serial Out

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Serial In – Parallel Out

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Simplex, Half-, and Full-Duplex Data Transmission methods

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 Classification of Data Comm (Data Terminal
Equipment PC – Data Communication Equipment
MODEM)

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Framing ASCII "A" (0x41)

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 Data Transfer Rate
• The rate of data transfer in serial data communication is specified in
bps (bits per second). Another often used term for bps is Baud rate.
• However, the baud and bps rates are not necessarily equal.
• This is due to the fact that baud rate is defined as the number of signal
changes per second. In modems, it is possible for each signal to
transfer multiple bits of data.
• As far as the unmodulated signal is concerned, the baud rate and bps
are the same
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RS232 to TTL Conversion

MAX232

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MAX232 IC (RS232 Serial to TTL Converter)

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 RS232 DB9 Connector Pins
Pin Description
1 Data carrier detect (DCD)
2 Received data (RxD)
3 Transmitted data (TxD)
4 Data terminal ready (DTR)
5 Signal ground (GND)
6 Data set ready (DSR)
7 Request to send (RTS)
8 Clear to send (CTS)
9 Ring indicator (RI)

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• DTR (data terminal ready): When the terminal (or a PC COM
port) is turned on, after going through a self-test, it sends out a
signal DTR to indicate that it is ready for communication.
• DSR (data set ready): When a DCE (modem) is turned on and
has gone through the self-test, it asserts DSR to indicate that it is
ready to communicate.
• RTS (request to send): When the DTE device (such as a PC) has
a byte to transmit, it asserts RTS to signal the modem that it has a
byte of data to transmit.

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• CTS (clear to send): In response to RTS, when the modem has
room for storing the data it is to receive, it sends out signal CTS to
the DTE (PC) to indicate that it can receive the data now.
• CD (carrier detect, or DCD, data carrier detect): The modem
asserts signal DCD to inform the DTE (PC) that a valid carrier has
been detected and that contact between it and the other modem is
established.
• RI (ring indicator): An output from the modem (DCE) and an
input to a PC (DTE) indicates that the telephone is ringing.

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 PC- Modem Communication

• While signals DTR and DSR are used by the PC and modem, - to
indicate that they are alive, it is RTS and CTS that actually control
the flow of data.
• When the PC wants to send data it asserts RTS, and in response, if
the modem is ready to accept the data, it sends back CTS.
• If Modem is not ready, the modem does not activate CTS, the PC
will de-assert DTR and try again.
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Programming the UART Ports

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18
MSP432 LaunchPad board

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XDS110-ET emulator USB Port

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Partial list of UART0 Registers and their
addresses
Register
Register Name Register Function
Address
UCA0CTLW0 Control Word 0 4000_1000
UCA0BRW Baud Rate Control Word 4000_1006
UCA0STATW Status 4000_100A
UCA0RXBUF Receive Buffer 4000_100C
UCA0TXBUF Transfer Buffer 4000_100E
UCA0IFG Interrupt Flag 4000_101C

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A Simplified Block Diagram of UART

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Clock Circuit of UART0

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UART pins in MSP432

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PxSEL1 and PxSEL0 Alternate Function
Selection registers (P1.3 & P1.2)

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 Alternate Function Selection - UARTs
I/O pin Function PxSEL1=0 PxSEL0=1
P1.2 UCA0RXD P1SEL1=00000000 P1SEL0=00000100
P1.3 UCA0TXD P1SEL1=00000000 P1SEL0=00001000
FOR UART0: P1SEL1=0x00 P1SEL0=00001100=0x0C
P2.2 UCA1RXD P2SEL1=00000000 P2SEL0=00000100
P2.3 UCA1TXD P2SEL1=00000000 P2SEL0=00001000
For UART1 P2SEL1=0x00 P2SEL0=00001100=0x0C
P3.2 UCA2RXD P3SEL1=00000000 P3SEL0=00000100
P3.3 UCA2TXD P3SEL1=00000000 P3SEL0=00001000
For UART2 P3SEL1=0x00 P3SEL0=00001100=0x0C
P9.6 UCA3RXD P9SEL1=00000000 P9SEL0=01000000
P9.7 UCA3TXD P9SEL1=00000000 P9SEL0=10000000
For UART3 P9SEL1=0x00 P9SEL0=11000000=0xC0

P1->SEL0 |= 0x0C; /* Set Bit 2 & Bit 3 of P1SEL0 – UART0 */

P1->SEL1 &= ~0x0C; /* Clear Bit 2 & Bit 3 of P1SEL1 – UART0 */
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 UART Control Word 0 (UCAxCTLW0) register

Field Bit Description

0b = Parity disabled
UCPEN D15 1b = Parity enabled. Parity bit is generated (UCAxTXD) and expected
(UCAxRXD).
0b = Odd parity
UCPAR D14
1b = Even parity
0b = LSB first
UCMSB D13
1b = MSB first
0b = 8-bit data
UC7BIT D12
1b = 7-bit data
0b = One stop bit
UCSPB D11
1b = Two stop bits
00b = UART mode
D10: 01b = Idle-line multiprocessor mode
UCMODEx
9 10b = Address-bit multiprocessor mode
11b = UART mode with automatic baud-rate detection
0b = Asynchronous mode
UCSYNC D8
1b = Synchronous mode
EUSCI_A0->CTLW0 = 0x0081 0 0 0 0 0 0 0 0 27

0 0
 UART Control Word 0 (UCAxCTLW0) register
Field Bit Description
00b = UCLK
01b = ACLK
UCSSELx D7:6
10b = SMCLK
11b = SMCLK
0b = Erroneous characters rejected and UCRXIFG is not set.
UCRXEIE D5
1b = Erroneous characters received set UCRXIFG.
0b = Received break characters do not set UCRXIFG.
UCBRKIE D4
1b = Received break characters set UCRXIFG.
0b = Not dormant. All received characters set UCRXIFG.
1b = Dormant. Only characters that are preceded by an idle-line or
UCDORM D3 with address bit set UCRXIFG. In UART mode with automatic
baud-rate detection, only the combination of a break and synch
field sets UCRXIFG.
0b = Next frame transmitted is data.
UCTXADDR D2
1b = Next frame transmitted is an address.
0b = Next frame transmitted is not a break.
UCTXBRK D1
1b = Next frame transmitted is a break or a break/synch.
0b = Disabled. eUSCI_A reset released for operation.
UCSWRST D0
1b = Enabled. eUSCI_A logic held in reset state.

EUSCI_A0->CTLW0 = 0x0081 1 0 0 0 0 0 0 1 28
8 1
UART Control Word 1(UCAxCTLW1) register

Field Bit Description

Reserved D15:2 Reserved
Deglitch time
00b = Approximately 2 ns
UCGLITx D0 01b = Approximately 50 ns
10b = Approximately 100 ns
11b = Approximately 200 ns

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 Clock Circuit Modes

• Low Frequency Baud Rate Mode

• Oversampling Baud Rate Mode

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 UCAxMCTLW ModulationCTLW
(UCOS16 = 0 Low Freq. BR Mode)

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 UCAxBRW

EUSCI_A0->BRW = Clock/Baud Rate

= SMCLK/BR
= 3MHz/9600 = 312
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UART0 BRW Values for Some Standard Baud Rates
using default OSCO16=0 and Clock of 3 MHz

Baud rate BRW (in decimal) BRW (in hex)

4,800 625 0x271
9,600 312 0x138
19,200 156 0x9C
38,400 78 0x4E
115,200 26 0x1A

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 UART Status Register (UCAxSTATW)

Field Bit Description

Reserved D15:8 Reserved
UCFE D6 Framing error flag. UCFE is cleared when UCAxRXBUF is read.
0b = No error
1b = Character received with low stop bit
UCOE D5 Overrun error flag. This bit is set when a character is transferred into
UCAxRXBUF before the previous character was read. UCOE is cleared
automatically when UCxRXBUF is read.
0b = No error
1b = Overrun error occurred
UCPE D4 Parity error flag. When UCPEN = 0, UCPE is read as 0. UCPE is cleared when UCAxRXBUF is
read.
0b = No error
1b = Character received with parity error
UCRXERR D2 Receive error flag. This bit indicates a character was received with one or more errors. When
UCRXERR = 1, on or more error flags, UCFE, UCPE, or UCOE is also set. UCRXERR is
cleared when UCAxRXBUF is read.
0b = No receive errors detected
1b = Receive error detected
UCBUSY D0 eUSCI_A busy. This bit indicates if a transmit or receive operation is in progress. 34
0b = eUSCI_A inactive
1b = eUSCI_A transmitting or receiving
 UART Interrupt Flag (UCAxIFG) and Interrupt
Enable (UCAxIE) Registers

while((EUSCI_A0->IFG & 0x02)==0); OR while(!(EUSCI_A0->IFG & 0x02));

EUSCI – Enhanced Universal Serial Communication Interface 35

IFG – Interrupt Flag Register
UART TX and RX Buffer registers

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 void UART0_init(void)
{
EUSCI_A0->CTLW0 |= 1; /* put in reset mode for
#include "msp.h" config */
EUSCI_A0->MCTLW = 0; /* disable oversampling
void UART0_init(void); */
void delayMs(int n); EUSCI_A0->CTLW0 = 0x0081; /* 1 stop bit, no parity,
SMCLK, 8-bit data */
int main(void) { EUSCI_A0->BRW = 26; /* 3,000,000 / 115200 =
UART0_init(); 26 */
while (1) { P1->SEL0 |= 0x0C; /* P1.3, P1.2 for UART */
while(!(EUSCI_A0->IFG & 0x02)) { } /* wait for P1->SEL1 &= ~0x0C;
transmit buffer empty */ EUSCI_A0->CTLW0 &= ~1; /* take UART out of
EUSCI_A0->TXBUF = 'Y'; /* send a char */ reset mode */
while(!(EUSCI_A0->IFG & 0x02)) { } }
EUSCI_A0->TXBUF = 'e'; /* send a char */
while(!(EUSCI_A0->IFG & 0x02)) { } /* delay milliseconds when system clock is at 3 MHz */
EUSCI_A0->TXBUF = 's'; /* send a char */ void delayMs(int n) {
delayMs(2); /* leave a gap between int i, j;
messages */
} for (j = 0; j < n; j++)
} for (i = 750; i > 0; i--); /* Delay */
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