Unit 3
Unit 3
Unit 3
Introduction
• Program must be brought into memory and
placed within a process for it to be run.
• Single-partition allocation
– Relocation-register scheme used to protect user
processes from each other, and from changing
operating-system code and data.
– Relocation register contains value of smallest physical
address; limit register contains range of logical
addresses – each logical address must be less than the
limit register.
Hardware Support for Relocation
and Limit Registers
• Multiple-partition allocation
– Hole – block of available memory; holes of
various size are scattered throughout memory.
– When a process arrives, it is allocated memory
from a hole large enough to accommodate it.
– Operating system maintains information about:
a) allocated partitions b) free partitions (hole)
OS OS OS OS
process 8 process 10
10 10 12
where pi is an index into the outer page table, and p2 is the displacement
within the page of the outer page table.
Two-Level Page-Table Scheme
Address-Translation Scheme
• Address-translation scheme for a two-level 32-
bit paging architecture
Hashed Page Tables
• Common in address spaces > 32 bits.
4
1
3 2
4
• Sharing.
– shared segments
– same segment number
• Allocation.
– first fit/best fit
– external fragmentation
Segmentation Architecture
• Protection. With each entry in segment table
associate:
– validation bit = 0 illegal segment
– read/write/execute privileges
• Protection bits associated with segments; code
sharing occurs at segment level.
• Since segments vary in length, memory
allocation is a dynamic storage-allocation
problem.
Segmentation Hardware
Example of Segmentation
Sharing of Segments
Segmentation with Paging
Intel 30386 Address Translation
Virtual Memory
Introduction
• Virtual memory – separation of user logical memory
from physical memory.
– Only part of the program needs to be in memory for
execution.
– Logical address space can therefore be much larger than
physical address space.
– Allows address spaces to be shared by several processes.
– Allows for more efficient process creation.
0
0
page table
1 1 4 5
2 2 1 3 9 page faults
• 4 frames
3 3 2 4
1 1 5 4
2 2 1 5 10 page faults
3 3 2
4 4 3
• FIFO Replacement – Belady’s Anomaly
– more frames less page faults
FIFO Page Replacement
FIFO Illustrating Belady’s Anamoly
Optimal Algorithm
• Replace page that will not be used for longest period of time.
• 4 frames example
1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5
1 4
2 6 page faults
3
4 5
• How do you know this?
• Used for measuring how well your algorithm performs.
Optimal Page Replacement
Least Recently Used (LRU) Algorithm
• Reference string: 1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5
1 5
2
3 5 4
4 3
• Counter implementation
– Every page entry has a counter; every time page is
referenced through this entry, copy the clock into the
counter.
– When a page needs to be changed, look at the counters to
determine which are to change.
– Stack
LRU Page Replacement
LRU Approximation Algorithms
• Reference bit
– With each page associate a bit, initially = 0
– When page is referenced bit set to 1.
– Replace the one which is 0 (if one exists). We do not
know the order, however.
• Second chance
– Need reference bit.
– Clock replacement.
– If page to be replaced (in clock order) has reference
bit = 1. then:
• set reference bit 0.
• leave page in memory.
• replace next page (in clock order), subject to same rules.
Second-Chance (clock) Page-Replacement Algorithm
Counting Algorithms
• Keep a counter of the number of references
that have been made to each page.