Fundamentals of DIGITAL Chapter 1

LOGIC with VHDL design Design Concepts

• Stephen Brown and Zvonko Vranesic

• McGraw-Hill, 2000 • Read as introduction

• Slides prepared by P.J. Bakkes (2000)

(Edited in June 2003)

July 2000 Univ. of Stellenbosch - Digital 1 July 2000 Univ. of Stellenbosch - Digital 2
Systems 144 Systems 144

Chapter 2
2.1 Variables and Functions
Introduction to Logic Circuits
• Reference figure 2.1
• Digital versus analog circuits
• Controlled switches
• Binary logic (Afr. Binêre logika)
• Input variable controls a switch
• Switches
• Logic expression e.g. L(x) = x describes the
• 0 or 1, ON or OFF, HIGH or LOW output as a function of the input variable
• If x = 0, L = 0 and light is off
• If x = 1, L = 1 and light is on
July 2000 Univ. of Stellenbosch - Digital 3 July 2000 Univ. of Stellenbosch - Digital 4
Systems 144 Systems 144

S
Battery x L Light
x = 0 x = 1

(a) Two states of a switch (a) Simple connection to a battery

S
S
x Power
supply x L
(b) Symbol for a switch

(b) Using a ground connection as the return path

July 2000 Figure 2.1 A binary switch 5 July 2000 Figure 2.2 A light controlled by a switch 6

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 Other functions Power
S S

supply x x L Light
1 2

• Reference figure 2.3 and 2.4

(a) The logical AND function (series connection)
• AND (Afr. EN): L(x1,x2) = x1 • x2
S
• OR (Afr. OF): L(x1,x2) = x1 + x2
x
• Other: L(x1,x2,x3) = (x1 + x2) • x3 1
Power Light
supply S L

x
2
(b) The logical OR function (parallel connection)

July 2000 Univ. of Stellenbosch - Digital 7 July 2000 Figure 2.3 Two basic functions 8
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2.2 Inversion (Afr. Inversie)

S
• L(x) = x’
x1 S • L(x) = !x
Power
supply S x3 L Light • L(x) = not x
x2 • If x = 0, L = 1
• If x = 1, L = 0

July 2000 Figure 2.4 A series-parallel connection 9 July 2000 Univ. of Stellenbosch - Digital 10
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2.3 Truth tables

R
(Afr. Waarheidstabelle)
• Reference figures 2.6 and 2.7
Power
supply x S L
• Alternative description of a logic function
for combinatorial circuits

July 2000 Figure 2.5 An inverting circuit 11 July 2000 Univ. of Stellenbosch - Digital 12
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July 2000 Figure 2.6 A truth table for AND and OR 13 July 2000 Figure 2.7 Three-input AND and OR 14

x1
x2
2.4 Logic gates and networks x1 ⋅ x2 x1 ⋅ x2 ⋅ … ⋅ xn
x1
x2

(Afr. Logiese hekke en netwerke) xn

• The three basic functions (AND, OR and NOT) (a) AND gates

can be combined to form logic functions of any

complexity. x1
x2
• They can be represented by symbols (Afr. x1
x1 + x2 x1 + x2 + … + xn
Simbole) (figure 2.8) x2

• A combination of these symbols in a drawing is xn

called a circuit diagram or a schematic (Afr. (b) OR gates

Stroombaandiagram). Figure 2.9.
• Larger circuit uses a network of gates x x

July 2000 Univ. of Stellenbosch - Digital 15 (c) NOT gate 16

Figure 2.8 The basic gates
Systems 144

2.4.1 Analysis of a Logic

Network
• Analysis (Afr. analise)
x
– Determine the function of an existing circuit
1

f = (x + x ) ⋅ x
x
2
1 2 3
• Synthesis (Afr. sintese)
x
3
– Create a new circuit for an application (main
task of an engineer!)
– Optimization is important
• Reference figure 2.10a

July 2000 Figure 2.9 An OR-AND function 17 July 2000 Univ. of Stellenbosch - Digital 18
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 Timing diagram
0→ 0→1→ 1 1→ 1→0→ 0
x
1 A
1→1→ 0→ 1
(Afr. tyddiagram)
f
0→ 0→0→ 1
0→ 1→0→ 1 • Reference figure 2.10b
B
x
2

(a) Network that implements f = x +x ⋅x

• Logic variables can change rapidly with
1 1 2

time (up to 1 GHz)

x x f (x , x )
1 2 1 2

0 0 1
0 1 1
1 0 0
1 1 1

(b) Truth table for f

July 2000 Figure 2.10 a Logic network 19 July 2000 Univ. of Stellenbosch - Digital 20
Systems 144

1
x
1 0

x 1
2 0 Functional equivalent networks
1
A
0

B
1 • Reference figure 2.10d
0

f
1 • Function g is functionally equivalent to f,
0 Time
(c) Timing diagram
but timing, cost, etc. can be different.
• Optimization offunctions (later).
0→ 0→1→ 1 1→ 1→ 0→ 0
x
1→1→ 0→ 1
1

0→ 1→0→ 1 g
x
2

(d) Network that implements g = x + x

1 2

July 2000 Figure 2.10 b Logic network 21 July 2000 Univ. of Stellenbosch - Digital 22
Systems 144

2.5 Boolean Algebra Axioms of Boolean Algebra

• In 1849 George Boole defined an algebraic • 0• 0=0
description of processes involved in thought • 1+1=1
and reasoning. • 1• 1 = 1
• In the late 1930’s Shannon applied this to • 0+0=0
logic circuits. • 0• 1=1• 0=0
• Boolean algebra developed into a powerful • 1+0=0+1=1
tool to describe logic circuits. • If x = 0, then x’ = 1
• If x = 1, then x’ = 0
July 2000 Univ. of Stellenbosch - Digital 23 July 2000 Univ. of Stellenbosch - Digital 24
Systems 144 Systems 144

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 Single variable theorems Duality
• x• 0=0 • Replace all 0’s with 1’s,all 1’s with 0’s, all
• x+1 = 1 AND’s with OR’s and all OR’s with AND’s
• x• 1=x
• More later
• x+0 = x
• x• x=x
• x+x = x
• x • x’ = 0
• x+x’ = 1
• x’’ = x
July 2000 Univ. of Stellenbosch - Digital 25 July 2000 Univ. of Stellenbosch - Digital 26
Systems 144 Systems 144

Two and three variable properties

• Commutative • Absorption
– x• y = y • x – x+x • y = x
– x+y = y+x
– x • (x+y) = x
• Associative
– x • (y • z) = (x • y) • z
• Combining
– x+(y+z) = (x+y)+z – x • y + x • y’ = x
• Distributive – (x+y) • (x+y’) = x
– x • (y+z) = x • y + x • z • x + x’ • y = x + y
– x+(y • z) = (x+y) • (x+z)
• x • (x’ + y) = x • y
July 2000 Univ. of Stellenbosch - Digital 27 July 2000 Univ. of Stellenbosch - Digital 28
Systems 144 Systems 144

DeMorgan’s Theorem

• (x • y)’ = x’ + y’
• (x+y)’ = x’ • y’

Next page: prove by perfect induction

July 2000 Univ. of Stellenbosch - Digital 29 July 2000 Figure 2.11 Proof of DeMorgan’s theorem 30
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 Applying identities (a) Constant 1 (b) Constant 0

x x x x

(c) Variable x (d) x

• See examples 2.1 and 2.2

x y x y

(e) x ⋅ y (f) x + y

x y
x y
z

(g) x ⋅ y (h) x⋅y+z

July 2000 Univ. of Stellenbosch - Digital 31 July 2000 32
Systems 144 Figure 2.12 The Venn diagram representation

x y x y

x y x y z z

z z x⋅y x⋅y

(a) x (d) x ⋅ y
x y x y

x y x y z z

z z x⋅z x⋅z

(b) y + z (e) x ⋅ z
x y x y

x y x y z z

z z
y⋅z x⋅y+x⋅z

(c) x ⋅ ( y + z ) (f) x ⋅ y + x ⋅ z
x y

x⋅y+x⋅z+y⋅z

Verification of x ⋅ y + x ⋅ z + y ⋅ z = x ⋅ y + x ⋅ z
July 2000 33 July 2000 34
Figure 2.13 Verification of the distributive property Figure 2.14

2.5.2 Alternative Notation 2.5.3 Precedence of Operators

• AND: x∧ y • NOT, AND and then OR

• OR: x∨ y

July 2000 Univ. of Stellenbosch - Digital 35 July 2000 Univ. of Stellenbosch - Digital 36
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 2.6 Synthesis using AND, OR
and NOT gates

• Synthesis: generate a circuit that

implements a function from specifications.
• Simple example:

July 2000 Univ. of Stellenbosch - Digital 37 July 2000 Figure 2.15 A function to be synthesized 38
Systems 144

x1
x2
Example
f
• Reference figure 2.15 and 2.16
• Concept of sum-of-products
• Simplify expression using theorems
• f(x1,x2) = x1 • x2 + x1’ • x2’ + x1’ • x2 (a) Canonical sum-of-products

• = x1 • x2 + x1’ • x2’ + x1’ • x2 + x1’ • x2

• = x1 • x2 + x1’ • x2 + x1’ • x2’ + x1’ • x2 x1
f
x2
• = (x1 + x1’) • x2 + x1’ • (x2’ + x2)
(b) Minimal-cost realization
• = x2 + x1’
July 2000 Univ. of Stellenbosch - Digital 39 July 2000 Figure 2.16 Two implementations of a function 40
Systems 144

2.6.1 Sum-of-Products and

Product-of-Sums
• Introduce more formal terms
• Minterm: for a function of n variables, a
product term in which each of the n
variables appears once, is called a minterm.
• Sum-of-Products form: A function f can be
represented by an expression that is a
logical sum of sum of the minterms.
• See figure 2.17
July 2000 Figure 2.17 Three-variable Minterms and Maxterms 41 July 2000 Univ. of Stellenbosch - Digital 42
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 Another example
• See figure 2.18 and 2.19
• f(x1,x2,x3) = x1’ • x2’ • x3 + x1 • x2’ • x3’
+ x1 • x2’ • x3 + x1 • x2 • x2’
• This form is not minimal, but can be
reduced to: f = x2’ • x3 + x1 • x3’
• Alternative forms:
– f=

July 2000 Figure 2.18 A three-variable function 43 July 2000 Univ. of Stellenbosch - Digital 44
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 2.7 Design examples 2.7.1 Three-way light control
• Design process: • Three doors in room each with switch
– Specification of solution to a problem in words • One or three on switches must turn light on
– Formal specification with truth table • See truth table in figure 2.20
– Synthesis
• f = m1 + m2 + m4 + m7
– Implementation
• or f = M0• M3 • M5 • M6
– Testing
– Possible iteration • See figure 2.21. For implementation

July 2000 Univ. of Stellenbosch - Digital 49 July 2000 Univ. of Stellenbosch - Digital 50
Systems 144 Systems 144

x
1
x
2
x
3

(a) Sum-of-products realization

July 2000 Figure 2.20 Truth table for a three-way light controller 51 July 2000 Figure 2.21 SOP implementation of the three-way light controller 52

x
3
2.7.2 Multiplexer Circuit
x
2
x
1
• Circuit often used in digital and computer
f
designs
• Switches one of multiple sources of data to
a single destination
• See figure 2.22
(b) Product-of-sums realization

July 2000 Figure 2.21 POS implementation of the three-way light controller 53 July 2000 Univ. of Stellenbosch - Digital 54
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 s x1 x2 f (s, x1, x2)
000 0
001
010
0
1
x1 2.8 Introduction to CAD tools
011 1 f
100 0 s • Lecturers comment: Read only at this stage
101 1 x2
110 0 • 2.8.1 Design Entry
111 1
– Truth table (figure 2.23)
(a)Truth table (b) Circuit
– Schematic entry (figure 2.24)
s
s f (s, x1, x2) – Hardware description languages (HDL)
x1 0 0 x1
x2
f
1 x2
• 2.8.2 Synthesis
1
• 2.8.3 Functional simulation
(c) Graphical symbol (d) More compact truth-table representation

July 2000 Figure 2.22 Multiplexer 55 July 2000 Univ. of Stellenbosch - Digital 56
Systems 144

July 2000 Figure 2.23 Screen capture of the Waveform Editor 57 July 2000 Figure 2.24 Screen capture of the Graphic Editor 58

Design conception

Truth table
DESIGN ENTRY

Schematic capture VHDL

2.9 Introduction to VHDL
Simple synthesis
Translation
• IEEE standard 1164
(see section 2.8.2)

Merge
• Used for the algorithmic description of
INITIAL SYNTHESIS TOOLS Boolean equations digital circuits
Functional simulation
• Used for synthesis and simulation
No
• See figures 2.27 to 2.31
Design correct?

Yes

Logic synthesis, physical design, timing simulation

(see section 4.12)

July 2000 59 July 2000 Univ. of Stellenbosch - Digital 60

Figure 2.25 The first stages of a CAD system Systems 144

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 x1
x2
f

x3

July 2000 Figure 2.26 A simple logic function and corresponding VHDL code 61 July 2000 Figure 2.30 VHDL code for a four-input function 62

x1
x3

x2

x4

July 2000 Figure 2. 31 Logic circuit for four-input function 63

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