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4 Retiming

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81 views36 pages

4 Retiming

Uploaded by

dejiachenxinyu98
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Retiming

Shao-Yi Chien

1
Introduction (1/2)
 Retiming
A transformation technique used to change the
locations of delay elements in circuit without
affecting the input/output characteristics

DSP in VLSI Design Shao-Yi Chien 2


Introduction (2/2)
 Applications of retiming
 Reducing the clock period
 Reducing the number of registers
 Reducing the power consumption
 Logic synthesis

DSP in VLSI Design Shao-Yi Chien 3


Reducing the Clock Period

Critical path=3u.t. Critical path=2u.t.


Min. clock period=3u.t. Min. clock period=2u.t.

DSP in VLSI Design Shao-Yi Chien 4


Reducing the Number of
Registers

Number of registers: 4 Number of registers: 5

DSP in VLSI Design Shao-Yi Chien 5


Reducing the Power
Consumption
 Placing registers at the inputs of nodes with
large capacitances can reduce the switching
activities at these nodes
Complex Combinational Circuits High Fan-Out Node

Register

Large power consumption due to glitch Lower power consumption

DSP in VLSI Design Shao-Yi Chien 6


Quantitative Description of
Retiming
 Map circuit GGr
 Retiming can be presented with r(V), V is one of
the nodes in the circuit
Destination Source
 For an edge

 w(e): weight (delay) of the edge e in the origin circuit


 wr(e): weight of the edge e in the retimed circuit

DSP in VLSI Design Shao-Yi Chien 7


An Example (1/2)

Origin DFG Retimed DFG with


r(1)=0
r(2)=1
r(3)=0
r(4)=0

DSP in VLSI Design Shao-Yi Chien 8


An Example (2/2)

wr (e)  0 e  G

 A retiming solution is feasible if


wr (e)  0 e  G

DSP in VLSI Design Shao-Yi Chien 9


Properties of Retiming (1/2)
 The weight of the retimed path
is given by

 Prof:

DSP in VLSI Design Shao-Yi Chien 10


Properties of Retiming (2/2)
 Retiming does not change the number of
delays in a cycle
 Retiming does not alter the iteration bound
in a DFG
 Adding the constant value j to the retiming
value of each node does not change the
mapping from G to Gr

DSP in VLSI Design Shao-Yi Chien 11


Solving Systems of Inequalities
(1/3)
 Given a set of M equalities in N variables,
use shortest path algorithm to solve the
results

DSP in VLSI Design Shao-Yi Chien 12


Solving Systems of Inequalities
(2/3)
 Step 1: draw a constraint graph
 Draw the node i for each of the N variables ri,
i=1,2,…,N
 Draw the node N+1
 For each inequality ri-rj<=k, draw the edge ji from
the node j to node i with length k
 For each node i, i=1,2,…n, draw the edge N+1i
from the node N+1 to the node i with length 0

DSP in VLSI Design Shao-Yi Chien 13


Solving Systems of Inequalities
(3/3)
 Step 2: solve using a shortest path
algorithm
 The system of inequalities has a solution if
and only if the constraint graph contains no
negative cycles
 If a solution exists, one solution is where ri is
the minimum-length path from the node N+1
to the node i

DSP in VLSI Design Shao-Yi Chien 14


Example

Bellman-Ford shortest path algorithm:

r1=0, r2=0, r3=0, r4=-1

DSP in VLSI Design Shao-Yi Chien 15


Retiming Techniques
 Cutset retiming and pipelining
 Retiming for clock period minimization
 Retiming for register minimization

DSP in VLSI Design Shao-Yi Chien 16


Cutset Retiming
 A special case of retiming that only affects
the weights of the edges in the cutset
 For the disconnected subgraph G1 and G2
 Addingk delays to each edge from G1 to G2
 Removing k delays from each edge from G2
to G1

DSP in VLSI Design Shao-Yi Chien 17


An Example of Cutset Retiming

K=1

DSP in VLSI Design Shao-Yi Chien 18


Feasibility of Cutset Retiming
 For each edge from G1 to G2

 For each edge from G2 to G1

DSP in VLSI Design Shao-Yi Chien 19


Special Case of Cutset
Retiming: Single Node Cutset

 Choose a node as a cutset


 Substract one delay from each edge outgoing from the
node
 Add one delay from each edge incident into the node
DSP in VLSI Design Shao-Yi Chien 20
Special Case of Cutset
Retiming: Pipelining

K=2

DSP in VLSI Design Shao-Yi Chien 21


Special Case: Combining with
Slow-Down (1/2)
 Create N-slow version of the DFG first
 Replace each delay element with N delays
 In an N-slow system, N-1 null operations
(or 0 samples) must be interleaved after
each useful signal sample to preserve the
functionality

DSP in VLSI Design Shao-Yi Chien 22


Special Case: Combining with
Slow-Down (2/2)
Assume addition: 1 u.t.,
multiplication: 2 u.t.
Critical path is 105 u.t.
Minimum sample period
is 105 u.t.

2-slow version

Retimed version. The


critical path is 6 u.t. The
minumum sample period
is 12 u.t.

DSP in VLSI Design Shao-Yi Chien 23


Example: Reduce the Critical Path
of a Recursive DFG
 For the IIR filter y(n+1)=ay(n)+bu(n)
TM=3u.t., TA=1u.t.
u(n)

b a

D y(n)
 Critical path=?
 Iteration bound=?
 Can we reduce the sampling period to 2u.t.?
DSP in VLSI Design Shao-Yi Chien 24
Example: Reduce the Critical Path
of a Recursive DFG
 Employ look-ahead transformation
 Consider more than one iterations
 y(n+2)= ay(n+1) + bu(n+1)
= a[ay(n)+bu(n)] + bu(n+1)
= a2y(n)+abu(n)+bu(n+1)

DSP in VLSI Design Shao-Yi Chien 25


Example: Reduce the Critical Path
of a Recursive DFG
u(n+1) D

b ab a2

2D y(n)
Pre-computation terms

 Critical path=?
 Iteration bound=?
 Can we reduce the sampling period to 2u.t.?
DSP in VLSI Design Shao-Yi Chien 26
Remarks
Cutset

kD

kD

-kD

-kD

D
D

DSP in VLSI Design Shao-Yi Chien 27


Retiming for Clock Period
Minimization (1/7)
 Minimum feasible clock period or critical
path

 Define two quantities, UV


 Minimum number of registers of UV

 Maximum computation time of UV

DSP in VLSI Design Shao-Yi Chien 28


Retiming for Clock Period
Minimization (2/7)
 Method to compute W(U,V) and D(U,V)

DSP in VLSI Design Shao-Yi Chien 29


Retiming for Clock Period
Minimization (3/7)

G G’

DSP in VLSI Design Shao-Yi Chien 30


Retiming for Clock Period
Minimization (4/7)

DSP in VLSI Design Shao-Yi Chien 31


Retiming for Clock Period
Minimization (5/7)
 Constraints
If the desired clock period is c

DSP in VLSI Design Shao-Yi Chien 32


Retiming for Clock Period
Minimization (6/7)
 If c=3

Feasibility constraints Critical path constraints

DSP in VLSI Design Shao-Yi Chien 33


Retiming for Clock Period
Minimization (7/7)

How about c=2?

Constraint graph r(1)=r(2)=r(3)=r(4)=0

DSP in VLSI Design Shao-Yi Chien 34


Retiming for Register
Minimization (1/2)

Ex: RU=7

DSP in VLSI Design Shao-Yi Chien 35


Retiming for Register
Minimization (2/2)
 Minimize subject to

DSP in VLSI Design Shao-Yi Chien 36

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