Efr32fg13 Datasheet

EFR32FG13 Flex Gecko Proprietary
Protocol SoC Family Data Sheet
The Flex Gecko proprietary protocol family of SoCs is part of the

KEY FEATURES
Wireless Gecko portfolio. Flex Gecko SoCs are ideal for enabling
energy-friendly proprietary protocol networking for IoT devices. • 32-bit ARM® Cortex®-M4 core with 40
MHz maximum operating frequency
The single-die solution provides industry-leading energy efficiency, ultra-fast wakeup • 512 kB of flash and 64 kB of RAM
times, a scalable power amplifier, an integrated balun and no-compromise MCU fea-
• Pin-compatible across EFR32FG families
tures.
(exceptions apply for 5V-tolerant pins)
Flex Gecko applications include: • 12-channel Peripheral Reflex System
enabling autonomous interaction of MCU
• Home and Building Automation and Security peripherals
• Metering • Autonomous Hardware Crypto Accelerator
and True Random Number Generator
• Electronic Shelf Labels
• Integrated PA with up to 19 dBm (2.4
• Industrial Automation GHz) or 20 dBm (Sub-GHz) tx power
• Commercial and Retail Lighting and Sensing • Integrated balun for 2.4 GHz
• Robust peripheral set and up to 32 GPIO
Core / Memory Clock Management Energy Management Other
H-F Crystal H-F Voltage CRYPTO

Voltage Monitor
Oscillator RC Oscillator Regulator
ARM CortexTM M4 processor Flash Program
with DSP extensions, FPU and MPU Memory CRC
Auxiliary H-F RC L-F DC-DC
Power-On Reset
Oscillator RC Oscillator Converter True Random
Number Generator
LDMA L-F Crystal Ultra L-F RC Brown-Out
ETM Debug Interface RAM Memory Oscillator
Controller Oscillator Detector SMU
32-bit bus
Peripheral Reflex System
Radio Transceiver Serial I/O Ports Timers and Triggers Analog I/F
RFSENSE Sub GHz
Interfaces
DEMOD
I External ADC
BUFC
FRC
LNA USART Timer/Counter Protocol Timer

Interrupts
RF Frontend Analog
PGA IFADC Comparator
PA Low Energy General Low Energy Low Energy
Q
UARTTM Purpose I/O Timer Sensor Interface IDAC
To Sub GHz
receive I/Q AGC
RFSENSE mixers and PA Capacitive
CRC
RAC
2.4 GHz I2C Pin Reset Pulse Counter Watchdog Timer Touch
I Frequency
LNA MOD VDAC
Synthesizer Real Time
BALUN RF Frontend
Pin Wakeup Counter and Cryotimer
Calendar Op-Amp
PA To 2.4 GHz receive To Sub GHz
Q
I/Q mixers and PA and 2.4 GHz PA
Lowest power mode with peripheral operational:

EM0—Active EM1—Sleep EM2—Deep Sleep EM3—Stop EM4—Hibernate EM4—Shutoff
silabs.com | Building a more connected world. Rev. 1.6

EFR32FG13 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Feature List
1. Feature List
The EFR32FG13 highlighted features are listed below.

• Low Power Wireless System-on-Chip • Wide selection of MCU peripherals
• High Performance 32-bit 40 MHz ARM Cortex®-M4 with • • 12-bit 1 Msps SAR Analog to Digital Converter (ADC)
DSP instruction and floating-point unit for efficient signal • 2 × Analog Comparator (ACMP)
processing • 2 × Digital to Analog Converter (VDAC)
• Embedded Trace Macrocell (ETM) for advanced debugging • 3 × Operational Amplifier (Opamp)
• 512 kB flash program memory • Digital to Analog Current Converter (IDAC)
• 64 kB RAM data memory • Low-Energy Sensor Interface (LESENSE)
• 2.4 GHz and Sub-GHz radio operation • Multi-channel Capacitive Sense Interface (CSEN)
• Transmit power: • Up to 32 pins connected to analog channels (APORT)
• 2.4 GHz radio: Up to 19 dBm shared between analog peripherals
• Sub-GHz radio: Up to 20 dBm • Up to 32 General Purpose I/O pins with output state re-
• Low Energy Consumption tention and asynchronous interrupts
• 8.4 mA RX current at 38.4 kbps, GFSK, 169 MHz • 8 Channel DMA Controller
• 9.5 mA RX current at 1 Mbps, GFSK, 2.4 GHz • 12 Channel Peripheral Reflex System (PRS)
• 10.3 mA RX current at 250 kbps, DSSS-OQPSK, 2.4 GHz • 2 × 16-bit Timer/Counter
• 8.5 mA TX current at 0 dBm output power at 2.4 GHz • 3 or 4 Compare/Capture/PWM channels
• 35.3 mA TX current at 14 dBm output power at 868 MHz • 1 × 32-bit Timer/Counter
• 69 μA/MHz in Active Mode (EM0) • 3 Compare/Capture/PWM channels
• 1.3 μA EM2 DeepSleep current (16 kB RAM retention and • 32-bit Real Time Counter and Calendar
RTCC running from LFRCO) • 16-bit Low Energy Timer for waveform generation
• High Receiver Performance • 32-bit Ultra Low Energy Timer/Counter for periodic
• -94.8 dBm sensitivity at 1 Mbit/s GFSK, 2.4 GHz wake-up from any Energy Mode
• -102.7 dBm sensitivity at 250 kbps DSSS-OQPSK, 2.4 GHz • 16-bit Pulse Counter with asynchronous operation
• -126.2 dBm sensitivity at 600 bps, GFSK, 915 MHz • 2 × Watchdog Timer with dedicated RC oscillator
• -120.6 dBm sensitivity at 2.4 kbps, GFSK, 868 MHz • 3 × Universal Synchronous/Asynchronous Receiver/
• -107.4 dBm sensitivity at 4.8 kbps, OOK, 433 MHz Transmitter (UART/SPI/SmartCard (ISO 7816)/IrDA/I2S)
• -112.2 dBm sensitivity at 38.4 kbps, GFSK, 169 MHz • Low Energy UART (LEUART™)
• Supported Modulation Formats • 2 × I2C interface with SMBus support and address rec-
• 2/4 (G)FSK with fully configurable shaping ognition in EM3 Stop
• BPSK / DBPSK TX • Wide Operating Range
• OOK / ASK • 1.8 V to 3.8 V single power supply
• Shaped OQPSK / (G)MSK • Integrated DC-DC, down to 1.8 V output with up to 200 mA
load current for system
• Configurable DSSS and FEC
• Standard (-40 °C to 85 °C) and Extended (-40 °C to 125 °C)
• Supported Protocols
temperature grades available
• Proprietary Protocols
• Support for Internet Security
• Wireless M-Bus
• General Purpose CRC
• Selected IEEE 802.15.4g SUN-FSK PHYs
• True Random Number Generator
• Low Power Wide Area Networks
• 2 × Hardware Cryptographic Acceleration for AES 128/256,
• Suitable for Systems Targeting Compliance With: SHA-1, SHA-2 (SHA-224 and SHA-256) and ECC
• FCC Part 90.210 Mask D, FCC part 15.247, 15.231, 15.249 • QFN32 5x5 mm Package
• ETSI Category I Operation, EN 300 220, EN 300 328 • QFN48 7x7 mm Package
• ARIB T-108, T-96
• China regulatory
silabs.com | Building a more connected world. Rev. 1.6 | 2

Ordering Information
2. Ordering Information
Table 2.1. Ordering Information
Frequency Band
Protocol Flash RAM
Ordering Code Stack @ Max TX Power (kB) (kB) GPIO Package Temp Range
EFR32FG13P233F512GM48-D Proprietary 2.4 GHz @ 19 dBm 512 64 28 QFN48 -40 to +85°C
Sub-GHz @ 20 dBm
EFR32FG13P231F512GM48-D Proprietary Sub-GHz @ 20 dBm 512 64 32 QFN48 -40 to +85°C
EFR32FG13P231F512IM48-D Proprietary Sub-GHz @ 20 dBm 512 64 32 QFN48 -40 to +125°C
EFR32FG13P231F512GM32-D Proprietary Sub-GHz @ 20 dBm 512 64 16 QFN32 -40 to +85°C
EFR32FG13P231F512IM32-D Proprietary Sub-GHz @ 20 dBm 512 64 16 QFN32 -40 to +125°C
EFR32 X G 1 3 P 132 F 512 G M 48 – A R
Tape and Reel (Optional)

Revision
Pin Count
Package – M (QFN), L (BGA)
Temperature Grade – G (-40 to +85 °C), -I (-40 to +125 °C)
Flash Memory Size in kB
Memory Type (Flash)
Feature Set Code – r2r1r0
r2: Reserved
r1: RF Type – 3 (TRX), 2 (RX), 1 (TX)
r0: Frequency Band – 1 (Sub-GHz), 2 (2.4 GHz), 3 (Dual-Band)
Performance Grade – P (Performance), B (Basic), V (Value)
Device Configuration
Series
Gecko
Family – M (Mighty), B (Blue), F (Flex)
Wireless Gecko 32-bit
Figure 2.1. Ordering Code Key

Table of Contents
1. Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2 Radio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2.1 Antenna Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2.2 Fractional-N Frequency Synthesizer . . . . . . . . . . . . . . . . . . . . . 8
3.2.3 Receiver Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2.4 Transmitter Architecture . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2.5 Wake on Radio . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2.6 RFSENSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2.7 Flexible Frame Handling . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2.8 Packet and State Trace . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2.9 Data Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2.10 Radio Controller (RAC) . . . . . . . . . . . . . . . . . . . . . . . . .10
3.2.11 Random Number Generator . . . . . . . . . . . . . . . . . . . . . . .10
3.3 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.3.1 Energy Management Unit (EMU) . . . . . . . . . . . . . . . . . . . . . .11
3.3.2 DC-DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.3.3 Power Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.4 General Purpose Input/Output (GPIO) . . . . . . . . . . . . . . . . . . . . . .11
3.5 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.5.1 Clock Management Unit (CMU) . . . . . . . . . . . . . . . . . . . . . . .12
3.5.2 Internal and External Oscillators. . . . . . . . . . . . . . . . . . . . . . .12
3.6 Counters/Timers and PWM . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.6.1 Timer/Counter (TIMER) . . . . . . . . . . . . . . . . . . . . . . . . .12
3.6.2 Wide Timer/Counter (WTIMER) . . . . . . . . . . . . . . . . . . . . . . .12
3.6.3 Real Time Counter and Calendar (RTCC) . . . . . . . . . . . . . . . . . . .12
3.6.4 Low Energy Timer (LETIMER) . . . . . . . . . . . . . . . . . . . . . . .13
3.6.5 Ultra Low Power Wake-up Timer (CRYOTIMER) . . . . . . . . . . . . . . . . .13
3.6.6 Pulse Counter (PCNT) . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.6.7 Watchdog Timer (WDOG) . . . . . . . . . . . . . . . . . . . . . . . . .13
3.7 Communications and Other Digital Peripherals . . . . . . . . . . . . . . . . . . .13
3.7.1 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) . . . . . . . . . .13
3.7.2 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART) . . . . . . . . . .13
3.7.3 Inter-Integrated Circuit Interface (I2C) . . . . . . . . . . . . . . . . . . . . .13
3.7.4 Peripheral Reflex System (PRS) . . . . . . . . . . . . . . . . . . . . . .13
3.7.5 Low Energy Sensor Interface (LESENSE) . . . . . . . . . . . . . . . . . . .14
3.8 Security Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.8.1 General Purpose Cyclic Redundancy Check (GPCRC) . . . . . . . . . . . . . . .14
3.8.2 Crypto Accelerator (CRYPTO) . . . . . . . . . . . . . . . . . . . . . . .14
3.8.3 True Random Number Generator (TRNG) . . . . . . . . . . . . . . . . . . .14
3.8.4 Security Management Unit (SMU) . . . . . . . . . . . . . . . . . . . . . .14
3.9 Analog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.9.1 Analog Port (APORT) . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.9.2 Analog Comparator (ACMP) . . . . . . . . . . . . . . . . . . . . . . . .14
3.9.3 Analog to Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . .15
3.9.4 Capacitive Sense (CSEN) . . . . . . . . . . . . . . . . . . . . . . . . .15
3.9.5 Digital to Analog Current Converter (IDAC) . . . . . . . . . . . . . . . . . . .15
3.9.6 Digital to Analog Converter (VDAC) . . . . . . . . . . . . . . . . . . . . .15
3.9.7 Operational Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.10 Reset Management Unit (RMU) . . . . . . . . . . . . . . . . . . . . . . . .15
3.11 Core and Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.11.1 Processor Core . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.11.2 Memory System Controller (MSC) . . . . . . . . . . . . . . . . . . . . .16
3.11.3 Linked Direct Memory Access Controller (LDMA) . . . . . . . . . . . . . . . .16
3.12 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
3.13 Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . .19
4. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.1.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . .21
4.1.2 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.1.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .25
4.1.4 DC-DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . .26
4.1.5 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . .28
4.1.6 Wake Up Times . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
4.1.7 Brown Out Detector (BOD) . . . . . . . . . . . . . . . . . . . . . . . .39
4.1.8 Frequency Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . .40
4.1.9 2.4 GHz RF Transceiver Characteristics . . . . . . . . . . . . . . . . . . . .41
4.1.10 Sub-GHz RF Transceiver Characteristics . . . . . . . . . . . . . . . . . . .55
4.1.11 Modem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
4.1.12 Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
4.1.13 Flash Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . .85
4.1.14 General-Purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . .86
4.1.15 Voltage Monitor (VMON) . . . . . . . . . . . . . . . . . . . . . . . . .88
4.1.16 Analog to Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . .89
4.1.17 Analog Comparator (ACMP) . . . . . . . . . . . . . . . . . . . . . . .91
4.1.18 Digital to Analog Converter (VDAC) . . . . . . . . . . . . . . . . . . . . .94
4.1.19 Current Digital to Analog Converter (IDAC) . . . . . . . . . . . . . . . . . .97
4.1.20 Capacitive Sense (CSEN) . . . . . . . . . . . . . . . . . . . . . . . .99
4.1.21 Operational Amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . 1
. 01
4.1.22 Pulse Counter (PCNT) . . . . . . . . . . . . . . . . . . . . . . . 1. 04
4.1.23 Analog Port (APORT) . . . . . . . . . . . . . . . . . . . . . . . . . 104
4.1.24 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
4.1.25 USART SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
4.2 Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . .109
4.2.1 Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . 1. 10
4.2.2 DC-DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . 115
.
4.2.3 2.4 GHz Radio . . . . . . . . . . . . . . . . . . . . . . . . . . 117
.

5. Typical Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . .119
5.1 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
5.2 RF Matching Networks . . . . . . . . . . . . . . . . . . . . . . . . . .121
5.3 Other Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
6. Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

6.1 QFN48 2.4 GHz and Sub-GHz Device Pinout. . . . . . . . . . . . . . . . . . . 123
6.2 QFN48 2.4 GHz Device Pinout . . . . . . . . . . . . . . . . . . . . . . 125
.
6.3 QFN48 Sub-GHz Device Pinout . . . . . . . . . . . . . . . . . . . . . . .127
6.4 QFN32 2.4 GHz Device Pinout . . . . . . . . . . . . . . . . . . . . . . 129
.
6.5 QFN32 Sub-GHz Device Pinout . . . . . . . . . . . . . . . . . . . . . . .131
6.6 GPIO Functionality Table . . . . . . . . . . . . . . . . . . . . . . . . 1
. 33
6.7 Alternate Functionality Overview . . . . . . . . . . . . . . . . . . . . . . . 161
6.8 Analog Port (APORT) Client Maps . . . . . . . . . . . . . . . . . . . . . .173
7. QFN48 Package Specifications. . . . . . . . . . . . . . . . . . . . . . . . 182

7.1 QFN48 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 182
7.2 QFN48 PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . .184
7.3 QFN48 Package Marking . . . . . . . . . . . . . . . . . . . . . . . . .186
8. RQFN32 Package Specifications . . . . . . . . . . . . . . . . . . . . . . . 187

8.1 RQFN32 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . 187
.
8.2 RQFN32 PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . 189
.
8.3 RQFN32 Package Marking . . . . . . . . . . . . . . . . . . . . . . . . . 191
9. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192

System Overview
3. System Overview
3.1 Introduction
The EFR32 product family combines an energy-friendly MCU with a highly integrated radio transceiver. The devices are well suited for
any battery operated application as well as other systems requiring high performance and low energy consumption. This section gives a
short introduction to the full radio and MCU system. The detailed functional description can be found in the EFR32xG13 Reference
Manual.
A block diagram of the EFR32FG13 family is shown in Figure 3.1 Detailed EFR32FG13 Block Diagram on page 7. The diagram
shows a superset of features available on the family, which vary by OPN. For more information about specific device features, consult
Ordering Information.
Radio Transceiver Port I/O Configuration IOVDD

Sub-GHz RF
SUBGRF_IP I
LNA DEMOD
Digital Peripherals
BUFC
SUBGRF_IN
FRC
SUBGRF_OP LETIMER
PA
SUBGRF_ON Q PGA IFADC Port A
PAn
TIMER Drivers
RFSENSE 2.4 GHz RF
I Frequency AGC CRYOTIMER
CRC
RAC
LNA
Synthesizer Port B
2G4RF_IOP PCNT PBn
To RF MOD Drivers
BALUN PA Frontend
2G4RF_ION Q Circuits RTC / RTCC
Port
USART Port C
Mapper PCn
Drivers
LEUART
Reset
RESETn Management ARM Cortex-M4 Core
I2C
Unit Port D
Serial Wire 512 KB ISP Flash PDn
CRYPTO Drivers
Debug Signals and ETM Brown Out / Program Memory
(shared w/GPIO) Debug / Power-On CRC
Reset 64 KB RAM A A
Programming Port F
H P LESENSE PFn
Drivers
Memory Protection Unit B B
Energy Management Floating Point Unit Analog Peripherals

PAVDD
RFVDD DMA Controller
IDAC
IOVDD
Voltage Mux & FB
AVDD Watchdog
Monitor -
DVDD Timer VDAC +
bypass
Internal Op-Amp
Clock Management Reference
VREGVDD DC-DC Voltage APORT
Converter Regulator
Input Mux
VREGSW VDD
ULFRCO
DECOUPLE 12-bit ADC
AUXHFRCO Temp
LFRCO Sense
LFXTAL_P
LFXO Capacitive
LFXTAL_N Touch
HFRCO
HFXTAL_P +
HFXO -
HFXTAL_N
Analog Comparator
Figure 3.1. Detailed EFR32FG13 Block Diagram
3.2 Radio
The Flex Gecko family features a radio transceiver supporting proprietary wireless protocols.

System Overview
3.2.1 Antenna Interface
The EFR32FG13 family includes devices which support both single-band and dual-band RF communication over separate physical RF
interfaces.
The 2.4 GHz antenna interface consists of two pins (2G4RF_IOP and 2G4RF_ION) that interface directly to the on-chip BALUN. The
2G4RF_ION pin should be grounded externally.
The sub-GHz antenna interface consists of a differential transmit interface (pins SUBGRF_OP and SUBGRF_ON) and a differential re-
ceive interface (pinsSUBGRF_IP and SUBGRF_IN).
The external components and power supply connections for the antenna interface typical applications are shown in the RF Matching
Networks section.
3.2.2 Fractional-N Frequency Synthesizer
The EFR32FG13 contains a high performance, low phase noise, fully integrated fractional-N frequency synthesizer. The synthesizer is
used in receive mode to generate the LO frequency used by the down-conversion mixer. It is also used in transmit mode to directly
generate the modulated RF carrier.
The fractional-N architecture provides excellent phase noise performance combined with frequency resolution better than 100 Hz, with
low energy consumption. The synthesizer has fast frequency settling which allows very short receiver and transmitter wake up times to
optimize system energy consumption.
3.2.3 Receiver Architecture
The EFR32FG13 uses a low-IF receiver architecture, consisting of a Low-Noise Amplifier (LNA) followed by an I/Q down-conversion
mixer, employing a crystal reference. The I/Q signals are further filtered and amplified before being sampled by the IF analog-to-digital
converter (IFADC).
The IF frequency is configurable from 150 kHz to 1371 kHz. The IF can further be configured for high-side or low-side injection, provid-
ing flexibility with respect to known interferers at the image frequency.
The Automatic Gain Control (AGC) block adjusts the receiver gain to optimize performance and avoid saturation for excellent selectivity
and blocking performance. The 2.4 GHz radio is calibrated at production to improve image rejection performance. The sub-GHz radio
can be calibrated on-demand by the user for the desired frequency band.
Demodulation is performed in the digital domain. The demodulator performs configurable decimation and channel filtering to allow re-
ceive bandwidths ranging from 0.1 to 2530 kHz. High carrier frequency and baud rate offsets are tolerated by active estimation and
compensation. Advanced features supporting high quality communication under adverse conditions include forward error correction by
block and convolutional coding as well as Direct Sequence Spread Spectrum (DSSS) for 2.4 GHz and sub-GHz bands.
A Received Signal Strength Indicator (RSSI) is available for signal quality metrics, for level-based proximity detection, and for RF chan-
nel access by Collision Avoidance (CA) or Listen Before Talk (LBT) algorithms. An RSSI capture value is associated with each received
frame and the dynamic RSSI measurement can be monitored throughout reception.
The EFR32FG13 features integrated support for antenna diversity to mitigate the problem of frequency-selective fading due to multipath
propagation and improve link budget. Support for antenna diversity is available for specific PHY configurations in 2.4 GHz and sub-GHz
bands. Internal configurable hardware controls an external switch for automatic switching between antennae during RF receive detec-
tion operations.
Note: Due to the shorter preamble of 802.15.4 and BLE packets, RX diversity is not supported.
3.2.4 Transmitter Architecture
The EFR32FG13 uses a direct-conversion transmitter architecture. For constant envelope modulation formats, the modulator controls
phase and frequency modulation in the frequency synthesizer. Transmit symbols or chips are optionally shaped by a digital shaping
filter. The shaping filter is fully configurable, including the BT product, and can be used to implement Gaussian or Raised Cosine shap-
ing.
Carrier Sense Multiple Access - Collision Avoidance (CSMA-CA) or Listen Before Talk (LBT) algorithms can be automatically timed by
the EFR32FG13. These algorithms are typically defined by regulatory standards to improve inter-operability in a given bandwidth be-
tween devices that otherwise lack synchronized RF channel access.

System Overview
3.2.5 Wake on Radio
The Wake on Radio feature allows flexible, autonomous RF sensing, qualification, and demodulation without required MCU activity, us-
ing a subsystem of the EFR32FG13 including the Radio Controller (RAC), Peripheral Reflex System (PRS), and Low Energy peripher-
als.
3.2.6 RFSENSE
The RFSENSE peripheral generates a system wakeup interrupt upon detection of wideband RF energy at the antenna interface, provid-
ing true RF wakeup capabilities from low energy modes including EM2, EM3 and EM4.
RFSENSE triggers on a relatively strong RF signal and is available in the lowest energy modes, allowing exceptionally low energy con-
sumption. RFSENSE does not demodulate or otherwise qualify the received signal, but software may respond to the wakeup event by
enabling normal RF reception.
Various strategies for optimizing power consumption and system response time in presence of false alarms may be employed using
available timer peripherals.
3.2.7 Flexible Frame Handling
EFR32FG13 has an extensive and flexible frame handling support for easy implementation of even complex communication protocols.
The Frame Controller (FRC) supports all low level and timing critical tasks together with the Radio Controller and Modulator/Demodula-
tor:
• Highly adjustable preamble length
• Up to 2 simultaneous synchronization words, each up to 32 bits and providing separate interrupts
• Frame disassembly and address matching (filtering) to accept or reject frames
• Automatic ACK frame assembly and transmission
• Fully flexible CRC generation and verification:
• Multiple CRC values can be embedded in a single frame
• 8, 16, 24 or 32-bit CRC value
• Configurable CRC bit and byte ordering
• Selectable bit-ordering (least significant or most significant bit first)
• Optional data whitening
• Optional Forward Error Correction (FEC), including convolutional encoding / decoding and block encoding / decoding
• Half rate convolutional encoder and decoder with constraint lengths from 2 to 7 and optional puncturing
• Optional symbol interleaving, typically used in combination with FEC
• Symbol coding, such as Manchester or DSSS, or biphase space encoding using FEC hardware
• UART encoding over air, with start and stop bit insertion / removal
• Test mode support, such as modulated or unmodulated carrier output
• Received frame timestamping
3.2.8 Packet and State Trace
The EFR32FG13 Frame Controller has a packet and state trace unit that provides valuable information during the development phase.
It features:
• Non-intrusive trace of transmit data, receive data and state information
• Data observability on a single-pin UART data output, or on a two-pin SPI data output
• Configurable data output bitrate / baudrate
• Multiplexed transmitted data, received data and state / meta information in a single serial data stream
3.2.9 Data Buffering
The EFR32FG13 features an advanced Radio Buffer Controller (BUFC) capable of handling up to 4 buffers of adjustable size from 64
bytes to 4096 bytes. Each buffer can be used for RX, TX or both. The buffer data is located in RAM, enabling zero-copy operations.

System Overview
3.2.10 Radio Controller (RAC)
The Radio Controller controls the top level state of the radio subsystem in the EFR32FG13. It performs the following tasks:
• Precisely-timed control of enabling and disabling of the receiver and transmitter circuitry
• Run-time calibration of receiver, transmitter and frequency synthesizer
• Detailed frame transmission timing, including optional LBT or CSMA-CA
3.2.11 Random Number Generator
The Frame Controller (FRC) implements a random number generator that uses entropy gathered from noise in the RF receive chain.
The data is suitable for use in cryptographic applications.
Output from the random number generator can be used either directly or as a seed or entropy source for software-based random num-
ber generator algorithms such as Fortuna.

System Overview
3.3 Power
The EFR32FG13 has an Energy Management Unit (EMU) and efficient integrated regulators to generate internal supply voltages. Only
a single external supply voltage is required, from which all internal voltages are created. An optional integrated DC-DC buck regulator
can be utilized to further reduce the current consumption. The DC-DC regulator requires one external inductor and one external capaci-
tor.
The EFR32FG13 device family includes support for internal supply voltage scaling, as well as two different power domains groups for
peripherals. These enhancements allow for further supply current reductions and lower overall power consumption.
AVDD and VREGVDD need to be 1.8 V or higher for the MCU to operate across all conditions; however the rest of the system will
operate down to 1.62 V, including the digital supply and I/O. This means that the device is fully compatible with 1.8 V components.
Running from a sufficiently high supply, the device can use the DC-DC to regulate voltage not only for itself, but also for other PCB
components, supplying up to a total of 200 mA.
3.3.1 Energy Management Unit (EMU)
The Energy Management Unit manages transitions of energy modes in the device. Each energy mode defines which peripherals and
features are available and the amount of current the device consumes. The EMU can also be used to turn off the power to unused RAM
blocks, and it contains control registers for the DC-DC regulator and the Voltage Monitor (VMON). The VMON is used to monitor multi-
ple supply voltages. It has multiple channels which can be programmed individually by the user to determine if a sensed supply has
fallen below a chosen threshold.
3.3.2 DC-DC Converter
The DC-DC buck converter covers a wide range of load currents and provides up to 90% efficiency in energy modes EM0, EM1, EM2
and EM3, and can supply up to 200 mA to the device and surrounding PCB components. Patented RF noise mitigation allows operation
of the DC-DC converter without degrading sensitivity of radio components. Protection features include programmable current limiting,
short-circuit protection, and dead-time protection. The DC-DC converter may also enter bypass mode when the input voltage is too low
for efficient operation. In bypass mode, the DC-DC input supply is internally connected directly to its output through a low resistance
switch. Bypass mode also supports in-rush current limiting to prevent input supply voltage droops due to excessive output current tran-
sients.
3.3.3 Power Domains
The EFR32FG13 has two peripheral power domains for operation in EM2 and EM3. If all of the peripherals in a peripheral power do-
main are configured as unused, the power domain for that group will be powered off in the low-power mode, reducing the overall cur-
rent consumption of the device.
Table 3.1. Peripheral Power Subdomains
Peripheral Power Domain 1 Peripheral Power Domain 2
ACMP0 ACMP1
PCNT0 CSEN
ADC0 VDAC0
LETIMER0 LEUART0
LESENSE I2C0
APORT I2C1
- IDAC
3.4 General Purpose Input/Output (GPIO)
EFR32FG13 has up to 32 General Purpose Input/Output pins. Each GPIO pin can be individually configured as either an output or in-
put. More advanced configurations including open-drain, open-source, and glitch-filtering can be configured for each individual GPIO
pin. The GPIO pins can be overridden by peripheral connections, like SPI communication. Each peripheral connection can be routed to
several GPIO pins on the device. The input value of a GPIO pin can be routed through the Peripheral Reflex System to other peripher-
als. The GPIO subsystem supports asynchronous external pin interrupts.

System Overview
3.5 Clocking
3.5.1 Clock Management Unit (CMU)
The Clock Management Unit controls oscillators and clocks in the EFR32FG13. Individual enabling and disabling of clocks to all periph-
erals is performed by the CMU. The CMU also controls enabling and configuration of the oscillators. A high degree of flexibility allows
software to optimize energy consumption in any specific application by minimizing power dissipation in unused peripherals and oscilla-
tors.
3.5.2 Internal and External Oscillators
The EFR32FG13 supports two crystal oscillators and fully integrates four RC oscillators, listed below.
• A high frequency crystal oscillator (HFXO) with integrated load capacitors, tunable in small steps, provides a precise timing refer-
ence for the MCU. Crystal frequencies in the range from 38 to 40 MHz are supported. An external clock source such as a TCXO can
also be applied to the HFXO input for improved accuracy over temperature.
• A 32.768 kHz crystal oscillator (LFXO) provides an accurate timing reference for low energy modes.
• An integrated high frequency RC oscillator (HFRCO) is available for the MCU system, when crystal accuracy is not required. The
HFRCO employs fast startup at minimal energy consumption combined with a wide frequency range.
• An integrated auxilliary high frequency RC oscillator (AUXHFRCO) is available for timing the general-purpose ADC and the Serial
Wire Viewer port with a wide frequency range.
• An integrated low frequency 32.768 kHz RC oscillator (LFRCO) can be used as a timing reference in low energy modes, when crys-
tal accuracy is not required.
• An integrated ultra-low frequency 1 kHz RC oscillator (ULFRCO) is available to provide a timing reference at the lowest energy con-
sumption in low energy modes.
3.6 Counters/Timers and PWM
3.6.1 Timer/Counter (TIMER)
TIMER peripherals keep track of timing, count events, generate PWM outputs and trigger timed actions in other peripherals through the
PRS system. The core of each TIMER is a 16-bit counter with up to 4 compare/capture channels. Each channel is configurable in one
of three modes. In capture mode, the counter state is stored in a buffer at a selected input event. In compare mode, the channel output
reflects the comparison of the counter to a programmed threshold value. In PWM mode, the TIMER supports generation of pulse-width
modulation (PWM) outputs of arbitrary waveforms defined by the sequence of values written to the compare registers, with optional
dead-time insertion available in timer unit TIMER_0 only.
3.6.2 Wide Timer/Counter (WTIMER)
WTIMER peripherals function just as TIMER peripherals, but are 32 bits wide. They keep track of timing, count events, generate PWM
outputs and trigger timed actions in other peripherals through the PRS system. The core of each WTIMER is a 32-bit counter with up to
4 compare/capture channels. Each channel is configurable in one of three modes. In capture mode, the counter state is stored in a
buffer at a selected input event. In compare mode, the channel output reflects the comparison of the counter to a programmed thresh-
old value. In PWM mode, the WTIMER supports generation of pulse-width modulation (PWM) outputs of arbitrary waveforms defined by
the sequence of values written to the compare registers, with optional dead-time insertion available in timer unit WTIMER_0 only.
3.6.3 Real Time Counter and Calendar (RTCC)
The Real Time Counter and Calendar (RTCC) is a 32-bit counter providing timekeeping in all energy modes. The RTCC includes a
Binary Coded Decimal (BCD) calendar mode for easy time and date keeping. The RTCC can be clocked by any of the on-board oscilla-
tors with the exception of the AUXHFRCO, and it is capable of providing system wake-up at user defined instances. When receiving
frames, the RTCC value can be used for timestamping. The RTCC includes 128 bytes of general purpose data retention, allowing easy
and convenient data storage in all energy modes down to EM4H.
A secondary RTC is used by the RF protocol stack for event scheduling, leaving the primary RTCC block available exclusively for appli-
cation software.

System Overview
3.6.4 Low Energy Timer (LETIMER)
The unique LETIMER is a 16-bit timer that is available in energy mode EM0 Active, EM1 Sleep, EM2 Deep Sleep, and EM3 Stop. This
allows it to be used for timing and output generation when most of the device is powered down, allowing simple tasks to be performed
while the power consumption of the system is kept at an absolute minimum. The LETIMER can be used to output a variety of wave-
forms with minimal software intervention. The LETIMER is connected to the Real Time Counter and Calendar (RTCC), and can be
configured to start counting on compare matches from the RTCC.
3.6.5 Ultra Low Power Wake-up Timer (CRYOTIMER)
The CRYOTIMER is a 32-bit counter that is capable of running in all energy modes. It can be clocked by either the 32.768 kHz crystal
oscillator (LFXO), the 32.768 kHz RC oscillator (LFRCO), or the 1 kHz RC oscillator (ULFRCO). It can provide periodic Wakeup events
and PRS signals which can be used to wake up peripherals from any energy mode. The CRYOTIMER provides a wide range of inter-
rupt periods, facilitating flexible ultra-low energy operation.
3.6.6 Pulse Counter (PCNT)
The Pulse Counter (PCNT) peripheral can be used for counting pulses on a single input or to decode quadrature encoded inputs. The
clock for PCNT is selectable from either an external source on pin PCTNn_S0IN or from an internal timing reference, selectable from
among any of the internal oscillators, except the AUXHFRCO. The peripheral may operate in energy mode EM0 Active, EM1 Sleep,
EM2 Deep Sleep, and EM3 Stop.
3.6.7 Watchdog Timer (WDOG)
The watchdog timer can act both as an independent watchdog or as a watchdog synchronous with the CPU clock. It has windowed
monitoring capabilities, and can generate a reset or different interrupts depending on the failure mode of the system. The watchdog can
also monitor autonomous systems driven by PRS.
3.7 Communications and Other Digital Peripherals
3.7.1 Universal Synchronous/Asynchronous Receiver/Transmitter (USART)
The Universal Synchronous/Asynchronous Receiver/Transmitter is a flexible serial I/O interface. It supports full duplex asynchronous
UART communication with hardware flow control as well as RS-485, SPI, MicroWire and 3-wire. It can also interface with devices sup-
porting:
• ISO7816 SmartCards
• IrDA
• I2S
3.7.2 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART)
The unique LEUARTTM provides two-way UART communication on a strict power budget. Only a 32.768 kHz clock is needed to allow
UART communication up to 9600 baud. The LEUART includes all necessary hardware to make asynchronous serial communication
possible with a minimum of software intervention and energy consumption.
3.7.3 Inter-Integrated Circuit Interface (I2C)
The I2C interface enables communication between the MCU and a serial I2C bus. It is capable of acting as both a master and a slave
and supports multi-master buses. Standard-mode, fast-mode and fast-mode plus speeds are supported, allowing transmission rates
from 10 kbit/s up to 1 Mbit/s. Slave arbitration and timeouts are also available, allowing implementation of an SMBus-compliant system.
The interface provided to software by the I2C peripheral allows precise timing control of the transmission process and highly automated
transfers. Automatic recognition of slave addresses is provided in active and low energy modes.
3.7.4 Peripheral Reflex System (PRS)
The Peripheral Reflex System provides a communication network between different peripherals without software involvement. Peripher-
als producing Reflex signals are called producers. The PRS routes Reflex signals from producers to consumer peripherals, which in
turn perform actions in response. Edge triggers and other functionality such as simple logic operations (AND, OR, NOT) can be applied
by the PRS to the signals. The PRS allows peripheral to act autonomously without waking the MCU core, saving power.

System Overview
3.7.5 Low Energy Sensor Interface (LESENSE)
The Low Energy Sensor Interface LESENSETM is a highly configurable sensor interface with support for up to 16 individually configura-
ble sensors. By controlling the analog comparators, ADC, and DAC, LESENSE is capable of supporting a wide range of sensors and
measurement schemes, and can for instance measure LC sensors, resistive sensors and capacitive sensors. LESENSE also includes a
programmable finite state machine which enables simple processing of measurement results without CPU intervention. LESENSE is
available in energy mode EM2, in addition to EM0 and EM1, making it ideal for sensor monitoring in applications with a strict energy
budget.
3.8 Security Features
3.8.1 General Purpose Cyclic Redundancy Check (GPCRC)
The GPCRC block implements a Cyclic Redundancy Check (CRC) function. It supports both 32-bit and 16-bit polynomials. The suppor-
ted 32-bit polynomial is 0x04C11DB7 (IEEE 802.3), while the 16-bit polynomial can be programmed to any value, depending on the
needs of the application.
3.8.2 Crypto Accelerator (CRYPTO)
The Crypto Accelerator is a fast and energy-efficient autonomous hardware encryption and decryption accelerator. EFR32 devices sup-
port AES encryption and decryption with 128- or 256-bit keys, ECC over both GF(P) and GF(2m), SHA-1 and SHA-2 (SHA-224 and
SHA-256).
Supported block cipher modes of operation for AES include: ECB, CTR, CBC, PCBC, CFB, OFB, GCM, CBC-MAC, GMAC and CCM.
Supported ECC NIST recommended curves include P-192, P-224, P-256, K-163, K-233, B-163 and B-233.
The CRYPTO1 block is tightly linked to the Radio Buffer Controller (BUFC) enabling fast and efficient autonomous cipher operations on
data buffer content. It allows fast processing of GCM (AES), ECC and SHA with little CPU intervention.
CRYPTO also provides trigger signals for DMA read and write operations.
3.8.3 True Random Number Generator (TRNG)
The TRNG is a non-deterministic random number generator based on a full hardware solution. The TRNG is validated with NIST800-22
and AIS-31 test suites as well as being suitable for FIPS 140-2 certification (for the purposes of cryptographic key generation).
3.8.4 Security Management Unit (SMU)
The Security Management Unit (SMU) allows software to set up fine-grained security for peripheral access, which is not possible in the
Memory Protection Unit (MPU). Peripherals may be secured by hardware on an individual basis, such that only priveleged accesses to
the peripheral's register interface will be allowed. When an access fault occurs, the SMU reports the specific peripheral involved and
can optionally generate an interrupt.
3.9 Analog
3.9.1 Analog Port (APORT)
The Analog Port (APORT) is an analog interconnect matrix allowing access to many analog peripherals on a flexible selection of pins.
Each APORT bus consists of analog switches connected to a common wire. Since many clients can operate differentially, buses are
grouped by X/Y pairs.
3.9.2 Analog Comparator (ACMP)
The Analog Comparator is used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is high-
er. Inputs are selected from among internal references and external pins. The tradeoff between response time and current consumption
is configurable by software. Two 6-bit reference dividers allow for a wide range of internally-programmable reference sources. The
ACMP can also be used to monitor the supply voltage. An interrupt can be generated when the supply falls below or rises above the
programmable threshold.

System Overview
3.9.3 Analog to Digital Converter (ADC)
The ADC is a Successive Approximation Register (SAR) architecture, with a resolution of up to 12 bits at up to 1 Msps. The output
sample resolution is configurable and additional resolution is possible using integrated hardware for averaging over multiple samples.
The ADC includes integrated voltage references and an integrated temperature sensor. Inputs are selectable from a wide range of
sources, including pins configurable as either single-ended or differential.
3.9.4 Capacitive Sense (CSEN)
The CSEN peripheral is a dedicated Capacitive Sensing block for implementing touch-sensitive user interface elements such a
switches and sliders. The CSEN peripheral uses a charge ramping measurement technique, which provides robust sensing even in
adverse conditions including radiated noise and moisture. The peripheral can be configured to take measurements on a single port pin
or scan through multiple pins and store results to memory through DMA. Several channels can also be shorted together to measure the
combined capacitance or implement wake-on-touch from very low energy modes. Hardware includes a digital accumulator and an aver-
aging filter, as well as digital threshold comparators to reduce software overhead.
3.9.5 Digital to Analog Current Converter (IDAC)
The IDAC can source or sink a configurable constant current. This current can be driven on an output pin or routed to the selected ADC
input pin for capacitive sensing. The full-scale current is programmable between 0.05 µA and 64 µA with several ranges consisting of
various step sizes.
3.9.6 Digital to Analog Converter (VDAC)
The Digital to Analog Converter (VDAC) can convert a digital value to an analog output voltage. The VDAC is a fully differential, 500
ksps, 12-bit converter. The opamps are used in conjunction with the VDAC, to provide output buffering. One opamp is used per single-
ended channel, or two opamps are used to provide differential outputs. The VDAC may be used for a number of different applications
such as sensor interfaces or sound output. The VDAC can generate high-resolution analog signals while the MCU is operating at low
frequencies and with low total power consumption. Using DMA and a timer, the VDAC can be used to generate waveforms without any
CPU intervention. The VDAC is available in all energy modes down to and including EM3.
3.9.7 Operational Amplifiers
The opamps are low power amplifiers with a high degree of flexibility targeting a wide variety of standard opamp application areas, and
are available down to EM3. With flexible built-in programming for gain and interconnection they can be configured to support multiple
common opamp functions. All pins are also available externally for filter configurations. Each opamp has a rail to rail input and a rail to
rail output. They can be used in conjunction with the VDAC peripheral or in stand-alone configurations. The opamps save energy, PCB
space, and cost as compared with standalone opamps because they are integrated on-chip.
3.10 Reset Management Unit (RMU)
The RMU is responsible for handling reset of the EFR32FG13. A wide range of reset sources are available, including several power
supply monitors, pin reset, software controlled reset, core lockup reset, and watchdog reset.
3.11 Core and Memory
3.11.1 Processor Core
The ARM Cortex-M processor includes a 32-bit RISC processor integrating the following features and tasks in the system:
• ARM Cortex-M4 RISC processor achieving 1.25 Dhrystone MIPS/MHz
• Memory Protection Unit (MPU) supporting up to 8 memory segments
• Up to 512 kB flash program memory
• Up to 64 kB RAM data memory
• Configuration and event handling of all peripherals
• 2-pin Serial-Wire debug interface

System Overview
3.11.2 Memory System Controller (MSC)
The Memory System Controller (MSC) is the program memory unit of the microcontroller. The flash memory is readable and writable
from both the Cortex-M and DMA. The flash memory is divided into two blocks; the main block and the information block. Program code
is normally written to the main block, whereas the information block is available for special user data and flash lock bits. There is also a
read-only page in the information block containing system and device calibration data. Read and write operations are supported in en-
ergy modes EM0 Active and EM1 Sleep.
3.11.3 Linked Direct Memory Access Controller (LDMA)
The Linked Direct Memory Access (LDMA) controller allows the system to perform memory operations independently of software. This
reduces both energy consumption and software workload. The LDMA allows operations to be linked together and staged, enabling so-
phisticated operations to be implemented.

System Overview
3.12 Memory Map
The EFR32FG13 memory map is shown in the figures below. RAM and flash sizes are for the largest memory configuration.
Figure 3.2. EFR32FG13 Memory Map — Core Peripherals and Code Space

System Overview
Figure 3.3. EFR32FG13 Memory Map — Peripherals

System Overview
3.13 Configuration Summary
The features of the EFR32FG13 are a subset of the feature set described in the device reference manual. The table below describes
device specific implementation of the features. Remaining peripherals support full configuration.
Table 3.2. Configuration Summary
Peripheral Configuration Pin Connections
USART0 IrDA US0_TX, US0_RX, US0_CLK, US0_CS
SmartCard
USART1 I2S US1_TX, US1_RX, US1_CLK, US1_CS
SmartCard
USART2 IrDA US2_TX, US2_RX, US2_CLK, US2_CS
SmartCard
TIMER0 with DTI TIM0_CC[2:0], TIM0_CDTI[2:0]
TIMER1 - TIM1_CC[3:0]
WTIMER0 with DTI WTIM0_CC[2:0], WTIM0_CDTI[2:0]

Electrical Specifications
4. Electrical Specifications
4.1 Electrical Characteristics
All electrical parameters in all tables are specified under the following conditions, unless stated otherwise:
• Typical values are based on TAMB=25 °C and VDD= 3.3 V, by production test and/or technology characterization.
• Radio performance numbers are measured in conducted mode, based on Silicon Laboratories reference designs using output pow-
er-specific external RF impedance-matching networks for interfacing to a 50 Ω source or load.
• Minimum and maximum values represent the worst conditions across supply voltage, process variation, and operating temperature,
unless stated otherwise.
Refer to 4.1.2.1 General Operating Conditions for more details about operational supply and temperature limits.

4.1.1 Absolute Maximum Ratings
Stresses above those listed below may cause permanent damage to the device. This is a stress rating only and functional operation of
the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure
to maximum rating conditions for extended periods may affect device reliability. For more information on the available quality and relia-
bility data, see the Quality and Reliability Monitor Report at http://www.silabs.com/support/quality/pages/default.aspx.
Table 4.1. Absolute Maximum Ratings
Parameter Symbol Test Condition Min Typ Max Unit
Storage temperature range TSTG -50 — 150 °C
Voltage on any supply pin VDDMAX -0.3 — 3.8 V
Voltage ramp rate on any VDDRAMPMAX — — 1 V / µs

supply pin
DC voltage on any GPIO pin VDIGPIN 5V tolerant GPIO pins1 2 3 -0.3 — Min of 5.25 V
and IOVDD
+2
Standard GPIO pins -0.3 — IOVDD+0.3 V
Voltage on HFXO pins VHFXOPIN -0.3 — 1.4 V
Input RF level on pins PRFMAX2G4 — — 10 dBm

2G4RF_IOP and
2G4RF_ION
Voltage differential between VMAXDIFF2G4 -50 — 50 mV

RF pins (2G4RF_IOP -
2G4RF_ION)
Absolute voltage on RF pins VMAX2G4 -0.3 — 3.8 V

2G4RF_IOP and
2G4RF_ION
Absolute voltage on Sub- VMAXSUBG Pins SUBGRF_OP and -0.3 — 3.8 V

GHz RF pins SUBGRF_ON
Pins SUBGRF_IP and -0.3 — 0.3 V

SUBGRF_IN,
Total current into VDD power IVDDMAX Source — — 200 mA

lines
Total current into VSS IVSSMAX Sink — — 200 mA

ground lines
Current per I/O pin IIOMAX Sink — — 50 mA
Source — — 50 mA
Current for all I/O pins IIOALLMAX Sink — — 200 mA
Source — — 200 mA
Junction temperature TJ -G grade devices -40 — 105 °C
-I grade devices -40 — 125 °C

Note:
1. When a GPIO pin is routed to the analog block through the APORT, the maximum voltage = IOVDD.
2. Valid for IOVDD in valid operating range or when IOVDD is undriven (high-Z). If IOVDD is connected to a low-impedance source
below the valid operating range (e.g. IOVDD shorted to VSS), the pin voltage maximum is IOVDD + 0.3 V, to avoid exceeding the
maximum IO current specifications.
3. To operate above the IOVDD supply rail, over-voltage tolerance must be enabled according to the GPIO_Px_OVTDIS register.
Pins with over-voltage tolerance disabled have the same limits as Standard GPIO.

4.1.2 Operating Conditions
When assigning supply sources, the following requirements must be observed:

• VREGVDD must be greater than or equal to AVDD, DVDD, RFVDD, PAVDD and all IOVDD supplies.
• VREGVDD = AVDD
• DVDD ≤ AVDD
• IOVDD ≤ AVDD
• RFVDD ≤ AVDD
• PAVDD ≤ AVDD

4.1.2.1 General Operating Conditions
Table 4.2. General Operating Conditions
Operating ambient tempera- TA -G temperature grade -40 25 85 °C

ture range1
-I temperature grade -40 25 125 °C
AVDD supply voltage2 VAVDD 1.8 3.3 3.8 V
VREGVDD operating supply VVREGVDD DCDC in regulation 2.4 3.3 3.8 V

voltage2 3
DCDC in bypass, 50mA load 1.8 3.3 3.8 V
DCDC not in use. DVDD external- 1.8 3.3 3.8 V

ly shorted to VREGVDD
VREGVDD current IVREGVDD DCDC in bypass, T ≤ 85 °C — — 200 mA
DCDC in bypass, T > 85 °C — — 100 mA
RFVDD operating supply VRFVDD 1.62 — VVREGVDD V

voltage
DVDD operating supply volt- VDVDD 1.62 — VVREGVDD V

age
PAVDD operating supply VPAVDD 1.62 — VVREGVDD V

voltage
IOVDD operating supply volt- VIOVDD All IOVDD pins4 1.62 — VVREGVDD V
age
DECOUPLE output capaci- CDECOUPLE 0.75 1.0 2.75 µF

tor5 6
Difference between AVDD dVDD — — 0.1 V

and VREGVDD, ABS(AVDD-
VREGVDD)2
HFCORECLK frequency fCORE VSCALE2, MODE = WS1 — — 40 MHz
VSCALE2, MODE = WS0 — — 25 MHz
HFCLK frequency fHFCLK VSCALE2 — — 40 MHz
VSCALE0 — — 20 MHz

Note:
1. The maximum limit on TA may be lower due to device self-heating, which depends on the power dissipation of the specific appli-
cation. TA (max) = TJ (max) - (THETAJA x PowerDissipation). Refer to the Absolute Maximum Ratings table and the Thermal
Characteristics table for TJ and THETAJA.
2. VREGVDD must be tied to AVDD. Both VREGVDD and AVDD minimum voltages must be satisfied for the part to operate.
3. The minimum voltage required in bypass mode is calculated using RBYP from the DCDC specification table. Requirements for
other loads can be calculated as VDVDD_min+ILOAD * RBYP_max.
4. When the CSEN peripheral is used with chopping enabled (CSEN_CTRL_CHOPEN = ENABLE), IOVDD must be equal to AVDD.
5. The system designer should consult the characteristic specs of the capacitor used on DECOUPLE to ensure its capacitance val-
ue stays within the specified bounds across temperature and DC bias.
6. VSCALE0 to VSCALE2 voltage change transitions occur at a rate of 10 mV / usec for approximately 20 usec. During this transi-
tion, peak currents will be dependent on the value of the DECOUPLE output capacitor, from 35 mA (with a 1 µF capacitor) to 70
mA (with a 2.7 µF capacitor).
4.1.3 Thermal Characteristics
Table 4.3. Thermal Characteristics
Thermal resistance, QFN48 THETAJA_QFN48 2-Layer PCB, Air velocity = 0 m/s — 75.7 — °C/W
Package
2-Layer PCB, Air velocity = 1 m/s — 61.5 — °C/W
Thermal resistance, QFN32 THETAJA_QFN32 4-Layer PCB, Air velocity = 0 m/s — 30.1 — °C/W
Package

Test conditions: L_DCDC=4.7 µH (Murata LQH3NPN4R7MM0L), C_DCDC=4.7 µF (Samsung CL10B475KQ8NQNC), V_DCDC_I=3.3

V, V_DCDC_O=1.8 V, I_DCDC_LOAD=50 mA, Heavy Drive configuration, F_DCDC_LN=7 MHz, unless otherwise indicated.
Table 4.4. DC-DC Converter
Input voltage range VDCDC_I Bypass mode, IDCDC_LOAD = 50 1.8 — VVREGVDD_ V

mA MAX
Low noise (LN) mode, 1.8 V out- 2.4 — VVREGVDD_ V

put, IDCDC_LOAD = 100 mA, or MAX
Low power (LP) mode, 1.8 V out-
put, IDCDC_LOAD = 10 mA
Low noise (LN) mode, 1.8 V out- 2.6 — VVREGVDD_ V

put, IDCDC_LOAD = 200 mA MAX
Output voltage programma- VDCDC_O 1.8 — VVREGVDD V

ble range1
Regulation DC accuracy ACCDC Low Noise (LN) mode, 1.8 V tar- 1.7 — 1.9 V
get output
Regulation window2 WINREG Low Power (LP) mode, 1.63 — 2.2 V

LPCMPBIASEMxx3 = 0, 1.8 V tar-
get output, IDCDC_LOAD ≤ 75 µA
Low Power (LP) mode, 1.63 — 2.1 V

LPCMPBIASEMxx3 = 3, 1.8 V tar-
get output, IDCDC_LOAD ≤ 10 mA
Steady-state output ripple VR Radio disabled — 3 — mVpp
Output voltage under/over- VOV CCM Mode (LNFORCECCM3 = — 25 60 mV

shoot 1), Load changes between 0 mA
and 100 mA
DCM Mode (LNFORCECCM3 = — 45 90 mV

0), Load changes between 0 mA
and 10 mA
Overshoot during LP to LN — 200 — mV

CCM/DCM mode transitions com-
pared to DC level in LN mode
Undershoot during BYP/LP to LN — 40 — mV

CCM (LNFORCECCM3 = 1) mode
transitions compared to DC level
in LN mode
Undershoot during BYP/LP to LN — 100 — mV

DCM (LNFORCECCM3 = 0) mode
transitions compared to DC level
in LN mode
DC line regulation VREG Input changes between — 0.1 — %

VVREGVDD_MAX and 2.4 V
DC load regulation IREG Load changes between 0 mA and — 0.1 — %

100 mA in CCM mode

Max load current ILOAD_MAX Low noise (LN) mode, Heavy — — 200 mA
Drive4, T ≤ 85 °C
Low noise (LN) mode, Heavy — — 100 mA

Drive4, T > 85 °C
Low noise (LN) mode, Medium — — 100 mA

Drive4
Low noise (LN) mode, Light — — 50 mA

Drive4
Low power (LP) mode, — — 75 µA

LPCMPBIASEMxx3 = 0
Low power (LP) mode, — — 10 mA

LPCMPBIASEMxx3 = 3
DCDC nominal output ca- CDCDC 25% tolerance 1 4.7 4.7 µF

pacitor5
DCDC nominal output induc- LDCDC 20% tolerance 4.7 4.7 4.7 µH
tor
Resistance in Bypass mode RBYP — 1.2 2.5 Ω
Note:
1. Due to internal dropout, the DC-DC output will never be able to reach its input voltage, VVREGVDD.
2. LP mode controller is a hysteretic controller that maintains the output voltage within the specified limits.
3. LPCMPBIASEMxx refers to either LPCMPBIASEM234H in the EMU_DCDCMISCCTRL register or LPCMPBIASEM01 in the
EMU_DCDCLOEM01CFG register, depending on the energy mode.
4. Drive levels are defined by configuration of the PFETCNT and NFETCNT registers. Light Drive: PFETCNT=NFETCNT=3; Medi-
um Drive: PFETCNT=NFETCNT=7; Heavy Drive: PFETCNT=NFETCNT=15.
5. Output voltage under/over-shoot and regulation are specified with CDCDC 4.7 µF. Different settings for DCDCLNCOMPCTRL
must be used if CDCDC is lower than 4.7 µF. See Application Note AN0948 for details.

4.1.5 Current Consumption
4.1.5.1 Current Consumption 3.3 V without DC-DC Converter
Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = DVDD = RFVDD = PAVDD = 3.3 V. T = 25 °C. DCDC is off.
Minimum and maximum values in this table represent the worst conditions across process variation at T = 25 °C.
Table 4.5. Current Consumption 3.3 V without DC-DC Converter
Current consumption in EM0 IACTIVE 38.4 MHz crystal, CPU running — 128 — µA/MHz
mode with all peripherals dis- while loop from flash1
abled
38 MHz HFRCO, CPU running — 97 — µA/MHz
Prime from flash
38 MHz HFRCO, CPU running — 98 107 µA/MHz

while loop from flash

CoreMark from flash


Current consumption in EM0 IACTIVE_VS 19 MHz HFRCO, CPU running — 86 — µA/MHz

mode with all peripherals dis- while loop from flash
abled and voltage scaling
enabled 1 MHz HFRCO, CPU running — 209 — µA/MHz
Current consumption in EM1 IEM1 38.4 MHz crystal1 — 76 — µA/MHz

mode with all peripherals dis-
abled 38 MHz HFRCO — 47 51 µA/MHz
26 MHz HFRCO — 49 55 µA/MHz
1 MHz HFRCO — 195 374 µA/MHz
Current consumption in EM1 IEM1_VS 19 MHz HFRCO — 43 — µA/MHz

abled and voltage scaling 1 MHz HFRCO — 167 — µA/MHz
enabled
Current consumption in EM2 IEM2_VS Full 64 kB RAM retention and — 1.9 — µA

mode, with voltage scaling RTCC running from LFXO
enabled
Full 64 kB RAM retention and — 2.2 — µA
RTCC running from LFRCO
1 bank (16 kB) RAM retention and — 1.9 3.3 µA

RTCC running from LFRCO2
Current consumption in EM3 IEM3_VS Full 64 kB RAM retention and — 1.53 3.0 µA
mode, with voltage scaling CRYOTIMER running from ULFR-
enabled CO
Current consumption in IEM4H_VS 128 byte RAM retention, RTCC — 0.93 — µA

EM4H mode, with voltage running from LFXO
scaling enabled
128 byte RAM retention, CRYO- — 0.45 — µA
TIMER running from ULFRCO
128 byte RAM retention, no RTCC — 0.44 0.9 µA

Current consumption in IEM4S No RAM retention, no RTCC — 0.04 0.085 µA

EM4S mode
Note:
1. CMU_HFXOCTRL_LOWPOWER=0.
2. CMU_LFRCOCTRL_ENVREF = 1, CMU_LFRCOCTRL_VREFUPDATE = 1

4.1.5.2 Current Consumption 3.3 V using DC-DC Converter
Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD = 1.8 V DC-DC
output. T = 25 °C. Minimum and maximum values in this table represent the worst conditions across process variation at T = 25 °C.
Table 4.6. Current Consumption 3.3 V using DC-DC Converter
Current consumption in EM0 IACTIVE_DCM 38.4 MHz crystal, CPU running — 87 — µA/MHz
abled, DCDC in Low Noise
DCM mode1 38 MHz HFRCO, CPU running — 69 — µA/MHz
Prime from flash


CoreMark from flash


Current consumption in EM0 IACTIVE_CCM 38.4 MHz crystal, CPU running — 97 — µA/MHz
abled, DCDC in Low Noise
CCM mode3 38 MHz HFRCO, CPU running — 80 — µA/MHz
Prime from flash


CoreMark from flash


Current consumption in EM0 IACTIVE_CCM_VS 19 MHz HFRCO, CPU running — 101 — µA/MHz
enabled, DCDC in Low 1 MHz HFRCO, CPU running — 1124 — µA/MHz
Noise CCM mode3 while loop from flash
Current consumption in EM1 IEM1_DCM 38.4 MHz crystal2 — 56 — µA/MHz

abled, DCDC in Low Noise 38 MHz HFRCO — 39 — µA/MHz
DCM mode1
26 MHz HFRCO — 46 — µA/MHz
Current consumption in EM1 IEM1_DCM_VS 19 MHz HFRCO — 50 — µA/MHz

enabled, DCDC in Low
Noise DCM mode1


enabled, DCDC in LP mode4
1 bank RAM retention and RTCC — 1.3 — µA

running from LFRCO5

enabled CO

scaling enabled
128 byte RAM retention, no RTCC — 0.42 — µA
Current consumption in IEM4S No RAM retention, no RTCC — 0.07 — µA

EM4S mode
Note:
1. DCDC Low Noise DCM Mode = Light Drive (PFETCNT=NFETCNT=3), F=3.0 MHz (RCOBAND=0), ANASW=DVDD.
3. DCDC Low Noise CCM Mode = Light Drive (PFETCNT=NFETCNT=3), F=6.4 MHz (RCOBAND=4), ANASW=DVDD.
4. DCDC Low Power Mode = Medium Drive, LPOSCDIV=1, LPCMPBIASEM234H=0, LPCLIMILIMSEL=1, ANASW=DVDD.

4.1.5.3 Current Consumption 1.8 V without DC-DC Converter
Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = DVDD = RFVDD = PAVDD = 1.8 V. T = 25 °C. DCDC is off.
Minimum and maximum values in this table represent the worst conditions across process variation at T = 25 °C.
Table 4.7. Current Consumption 1.8 V without DC-DC Converter
Current consumption in EM0 IACTIVE 38.4 MHz crystal, CPU running — 128 — µA/MHz
abled
Prime from flash


CoreMark from flash


Current consumption in EM0 IACTIVE_VS 19 MHz HFRCO, CPU running — 86 — µA/MHz

enabled 1 MHz HFRCO, CPU running — 206 — µA/MHz
Current consumption in EM1 IEM1 38.4 MHz crystal1 — 76 — µA/MHz

abled 38 MHz HFRCO — 47 — µA/MHz
Current consumption in EM1 IEM1_VS 19 MHz HFRCO — 43 — µA/MHz

enabled

enabled
1 bank (16 kB) RAM retention and — 1.6 — µA

RTCC running from LFRCO2

enabled CO

scaling enabled
128 byte RAM retention, no RTCC — 0.36 — µA
Current consumption in IEM4S no RAM retention, no RTCC — 0.05 — µA

EM4S mode

Note:

4.1.5.4 Current Consumption Using Radio 3.3 V with DC-DC
Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD = 1.8 V. T = 25
°C. Minimum and maximum values in this table represent the worst conditions across process variation at T = 25 °C.
Table 4.8. Current Consumption Using Radio 3.3 V with DC-DC
Current consumption in re- IRX_ACTIVE 500 kbit/s, 2GFSK, F = 915 MHz, — 9.3 10.2 mA
ceive mode, active packet Radio clock prescaled by 4
reception (MCU in EM1 @
38.4 MHz, peripheral clocks 38.4 kbit/s, 2GFSK, F = 868 MHz, — 8.6 10.2 mA
disabled), T ≤ 85 °C Radio clock prescaled by 4
38.4 kbit/s, 2GFSK, F = 490 MHz, — 8.6 10.2 mA

Radio clock prescaled by 4
50 kbit/s, 2GFSK, F = 433 MHz, — 8.6 10.2 mA



125 kbit/s, 2GFSK, F = 2.4 GHz, — 9.2 — mA


1 Mbit/s, 2GFSK, F = 2.4 GHz, — 9.5 — mA

2 Mbit/s, 2GFSK, F = 2.4 GHz, — 10.6 — mA

802.15.4 receiving frame, F = 2.4 — 10.3 — mA

GHz, Radio clock prescaled by 3
Current consumption in re- IRX_ACTIVE_HT 500 kbit/s, 2GFSK, F = 915 MHz, — — 13 mA

ceive mode, active packet Radio clock prescaled by 4
reception (MCU in EM1 @
38.4 MHz, peripheral clocks 38.4 kbit/s, 2GFSK, F = 868 MHz, — — 13 mA
disabled), T > 85 °C Radio clock prescaled by 4
38.4 kbit/s, 2GFSK, F = 490 MHz, — — 13 mA

50 kbit/s, 2GFSK, F = 433 MHz, — — 13 mA




Current consumption in re- IRX_LISTEN 500 kbit/s, 2GFSK, F = 915 MHz, — 10.2 11 mA
ceive mode, listening for No radio clock prescaling
packet (MCU in EM1 @ 38.4
MHz, peripheral clocks disa- 38.4 kbit/s, 2GFSK, F = 868 MHz, — 9.5 11 mA
bled), T ≤ 85 °C No radio clock prescaling
38.4 kbit/s, 2GFSK, F = 490 MHz, — 9.5 11 mA

No radio clock prescaling
50 kbit/s, 2GFSK, F = 433 MHz, — 9.5 11 mA





1 Mbit/s, 2GFSK, F = 2.4 GHz, No — 10.5 — mA

radio clock prescaling
2 Mbit/s, 2GFSK, F = 2.4 GHz, No — 11.3 — mA

radio clock prescaling
802.15.4, F = 2.4 GHz, No radio — 11.9 — mA

clock prescaling
Current consumption in re- IRX_LISTEN_HT 500 kbit/s, 2GFSK, F = 915 MHz, — — 14 mA

ceive mode, listening for No radio clock prescaling
packet (MCU in EM1 @ 38.4
MHz, peripheral clocks disa- 38.4 kbit/s, 2GFSK, F = 868 MHz, — — 14 mA
bled), T > 85 °C No radio clock prescaling

50 kbit/s, 2GFSK, F = 433 MHz, — — 14 mA




Current consumption in ITX F = 915 MHz, CW, 20 dBm — 90.2 134.3 mA

transmit mode (MCU in EM1 match, External PA supply = 3.3V
@ 38.4 MHz, peripheral
clocks disabled), T ≤ 85 °C F = 915 MHz, CW, 14 dBm — 36 42.5 mA
match, External PA supply con-
nected to DCDC output
F = 868 MHz, CW, 20 dBm — 79.7 106.7 mA

match, External PA supply = 3.3V
F = 868 MHz, CW, 14 dBm — 35.3 41 mA

F = 490 MHz, CW, 20 dBm — 93.8 125.4 mA

F = 433 MHz, CW, 10 dBm — 20.3 24 mA

nected to DC-DC output
F = 433 MHz, CW, 14 dBm — 34 41.5 mA

F = 315 MHz, CW, 14 dBm — 33.5 42 mA

F = 169 MHz, CW, 20 dBm — 88.6 116.7 mA

F = 2.4 GHz, CW, 0 dBm output — 8.5 — mA

power, Radio clock prescaled by 3

power, Radio clock prescaled by 1

power

power
F = 2.4 GHz, CW, 10.5 dBm out- — 34.0 — mA

put power
F = 2.4 GHz, CW, 16.5 dBm out- — 86.0 — mA

put power, PAVDD connected di-
rectly to external 3.3V supply
F = 2.4 GHz, CW, 19.5 dBm out- — 131.0 — mA

put power, PAVDD connected di-
rectly to external 3.3V supply

Current consumption in ITX_HT F = 915 MHz, CW, 20 dBm — — 134.3 mA

transmit mode (MCU in EM1 match, External PA supply = 3.3V
@ 38.4 MHz, peripheral
clocks disabled), T > 85 °C F = 915 MHz, CW, 14 dBm — — 42.5 mA
F = 868 MHz, CW, 20 dBm — — 109.8 mA

F = 868 MHz, CW, 14 dBm — — 41.3 mA

F = 490 MHz, CW, 20 dBm — — 130.8 mA

F = 433 MHz, CW, 10 dBm — — 24.4 mA

nected to DC-DC output
F = 433 MHz, CW, 14 dBm — — 41.5 mA

F = 315 MHz, CW, 14 dBm — — 42 mA

F = 169 MHz, CW, 20 dBm — — 122.8 mA


4.1.6 Wake Up Times
Table 4.9. Wake Up Times
Wake up time from EM1 tEM1_WU — 3 — AHB

Clocks
Wake up from EM2 tEM2_WU Code execution from flash — 10.9 — µs
Code execution from RAM — 3.8 — µs
Wake up from EM3 tEM3_WU Code execution from flash — 10.9 — µs
Code execution from RAM — 3.8 — µs
Wake up from EM4H1 tEM4H_WU Executing from flash — 90 — µs
Wake up from EM4S1 tEM4S_WU Executing from flash — 300 — µs
Time from release of reset tRESET Soft Pin Reset released — 51 — µs

source to first instruction ex-
ecution Any other reset released — 358 — µs
Power mode scaling time tSCALE VSCALE0 to VSCALE2, HFCLK = — 31.8 — µs

19 MHz2 3
VSCALE2 to VSCALE0, HFCLK = — 4.3 — µs

19 MHz4
Note:
1. Time from wake up request until first instruction is executed. Wakeup results in device reset.
2. Scaling up from VSCALE0 to VSCALE2 requires approximately 30.3 µs + 28 HFCLKs.
3. VSCALE0 to VSCALE2 voltage change transitions occur at a rate of 10 mV/µs for approximately 20 µs. During this transition,
peak currents will be dependent on the value of the DECOUPLE output capacitor, from 35 mA (with a 1 µF capacitor) to 70 mA
(with a 2.7 µF capacitor).
4. Scaling down from VSCALE2 to VSCALE0 requires approximately 2.8 µs + 29 HFCLKs.

4.1.7 Brown Out Detector (BOD)
Table 4.10. Brown Out Detector (BOD)
DVDD BOD threshold VDVDDBOD DVDD rising — — 1.62 V
DVDD falling (EM0/EM1) 1.35 — — V
DVDD falling (EM2/EM3) 1.3 — — V
DVDD BOD hysteresis VDVDDBOD_HYST — 18 — mV
DVDD BOD response time tDVDDBOD_DELAY Supply drops at 0.1V/µs rate — 2.4 — µs
AVDD BOD threshold VAVDDBOD AVDD rising — — 1.8 V
AVDD falling (EM0/EM1) 1.62 — — V
AVDD falling (EM2/EM3) 1.53 — — V
AVDD BOD hysteresis VAVDDBOD_HYST — 20 — mV
AVDD BOD response time tAVDDBOD_DELAY Supply drops at 0.1V/µs rate — 2.4 — µs
EM4 BOD threshold VEM4DBOD AVDD rising — — 1.7 V
AVDD falling 1.45 — — V
EM4 BOD hysteresis VEM4BOD_HYST — 25 — mV
EM4 BOD response time tEM4BOD_DELAY Supply drops at 0.1V/µs rate — 300 — µs

4.1.8 Frequency Synthesizer
Table 4.11. Frequency Synthesizer
RF synthesizer frequency fRANGE 2400 - 2483.5 MHz 2400 — 2483.5 MHz

range
779 - 956 MHz 779 — 956 MHz
584 - 717 MHz 584 — 717 MHz
358 - 574 MHz 358 — 574 MHz
191 - 358 MHz 191 — 358 MHz
110 - 191 MHz 110 — 191 MHz
LO tuning frequency resolu- fRES 2400 - 2483.5 MHz — — 73 Hz

tion with 38.4 MHz crystal
779 - 956 MHz — — 24 Hz
584 - 717 MHz — — 18.3 Hz
358 - 574 MHz — — 12.2 Hz
191 - 358 MHz — — 7.3 Hz
110 - 191 MHz — — 4.6 Hz
Frequency deviation resolu- dfRES 2400 - 2483.5 MHz — — 73 Hz

779 - 956 MHz — — 24 Hz
584 - 717 MHz — — 18.3 Hz
358 - 574 MHz — — 12.2 Hz
191 - 358 MHz — — 7.3 Hz
110 - 191 MHz — — 4.6 Hz
Maximum frequency devia- dfMAX 2400 - 2483.5 MHz — — 1677 kHz

779 - 956 MHz — — 559 kHz
584 - 717 MHz — — 419 kHz
358 - 574 MHz — — 280 kHz
191 - 358 MHz — — 167 kHz
110 - 191 MHz — — 105 kHz

4.1.9 2.4 GHz RF Transceiver Characteristics
4.1.9.1 RF Transmitter General Characteristics for 2.4 GHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 2.45 GHz.
Table 4.12. RF Transmitter General Characteristics for 2.4 GHz Band
Maximum TX power1 POUTMAX 19 dBm-rated part numbers. — 19.5 — dBm

PAVDD connected directly to ex-
ternal 3.3V supply
Minimum active TX Power POUTMIN CW -30 — dBm
Output power step size POUTSTEP -5 dBm< Output power < 0 dBm — 1 — dB
0 dBm < output power < — 0.5 — dB

POUTMAX
Output power variation vs POUTVAR_V 1.8 V < VVREGVDD < 3.3 V, — 4.5 — dB
supply at POUTMAX PAVDD connected directly to ex-
ternal supply, for output power >
10 dBm.
1.8 V < VVREGVDD < 3.3 V using — 2.2 — dB

DC-DC converter
Output power variation vs POUTVAR_T From -40 to +85 °C, PAVDD con- — 1.5 — dB
temperature at POUTMAX nected to DC-DC output
From -40 to +125 °C, PAVDD — 2.2 — dB

connected to DC-DC output
From -40 to +85 °C, PAVDD con- — 1.5 — dB

nected to external supply
From -40 to +125 °C, PAVDD — 3.4 — dB

connected to external supply
Output power variation vs RF POUTVAR_F Over RF tuning frequency range — 0.4 — dB

frequency at POUTMAX
RF tuning frequency range FRANGE 2400 — 2483.5 MHz
Note:
1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices cov-
ered in this datasheet can be found in the Max TX Power column of the Ordering Information Table.

4.1.9.2 RF Receiver General Characteristics for 2.4 GHz Band
Table 4.13. RF Receiver General Characteristics for 2.4 GHz Band
RF tuning frequency range FRANGE 2400 — 2483.5 MHz
Receive mode maximum SPURRX 30 MHz to 1 GHz — -57 — dBm

spurious emission
1 GHz to 12 GHz — -47 — dBm
Max spurious emissions dur- SPURRX_FCC 216 MHz to 960 MHz, Conducted — -55.2 — dBm
ing active receive mode, per Measurement
FCC Part 15.109(a)
Above 960 MHz, Conducted — -47.2 — dBm
Measurement
Level above which RFSENSETRIG CW at 2.45 GHz — -24 — dBm

RFSENSE will trigger1
Level below which RFSENSETHRES CW at 2.45 GHz — -50 — dBm

RFSENSE will not trigger1
1% PER sensitivity SENS2GFSK 2 Mbps 2GFSK signal — -89.6 — dBm
250 kbps 2GFSK signal — -100.7 — dBm
Note:
1. RFSENSE performance is only valid from 0 to 85 °C. RFSENSE should be disabled outside this temperature range.

4.1.9.3 RF Transmitter Characteristics for 2GFSK in the 2.4GHz Band, 1 Mbps Data Rate
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency = 38.4MHz. RF center frequency 2.45 GHz. Maximum duty cycle of
85%.
Table 4.14. RF Transmitter Characteristics for 2GFSK in the 2.4GHz Band, 1 Mbps Data Rate
Transmit 6dB bandwidth TXBW 10 dBm — 763 — kHz
Power spectral density limit PSDLIMIT Per FCC part 15.247 at 10 dBm — -9.1 — dBm/
3kHz
Per FCC part 15.247 at 20 dBm — -2 — dBm/

3kHz
Per ETSI 300.328 at 10 dBm/1 — 10 — dBm

MHz
Occupied channel bandwidth OCPETSI328 99% BW at highest and lowest — 1.1 — MHz
per ETSI EN300.328 channels in band, 10 dBm
Emissions of harmonics out- SPURHRM_FCC 2nd,3rd, 5, 6, 8, 9,10 harmonics; — -47 — dBm

of-band, per FCC part continuous transmission of modu-
15.247 lated carrier
Spurious emissions out-of- SPUROOB_FCC Per FCC part 15.205/15.209, — -47 — dBm
band, excluding harmonics Above 2.483 GHz or below 2.4
captured in SPURHARM,FCC. GHz; continuous transmission of
Emissions taken at CW carrier, Restricted Bands1 2
POUTMAX, PAVDD connec-
ted to external 3.3 V supply Per FCC part 15.247, Above — -26 — dBc
2.483 GHz or below 2.4 GHz;
continuous transmission of CW
carrier, Non-Restricted Bands
Spurious emissions out-of- SPURETSI328 [2400-BW to 2400] MHz, [2483.5 — -16 — dBm
band; per ETSI 300.328 to 2483.5+BW] MHz
[2400-2BW to 2400-BW] MHz, — -26 — dBm

[2483.5+BW to 2483.5+2BW]
MHz per ETSI 300.328
Spurious emissions per ETSI SPURETSI440 47-74 MHz,87.5-108 MHz, — -60 — dBm
EN300.440 174-230 MHz, 470-862 MHz
25-1000 MHz — -42 — dBm
1-12 GHz — -36 — dBm
Note:
1. For 2476 MHz, 1.5 dB of power backoff is used to achieve this value.

4.1.9.4 RF Receiver Characteristics for 2GFSK in the 2.4GHz Band, 1 Mbps Data Rate
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency = 38.4MHz. RF center frequency 2.45 GHz.
Table 4.15. RF Receiver Characteristics for 2GFSK in the 2.4GHz Band, 1 Mbps Data Rate
Max usable receiver input SAT Signal is reference signal1. Packet — 10 — dBm
level, 0.1% BER length is 20 bytes.
Sensitivity, 0.1% BER SENS Signal is reference signal1. Using — -94.8 — dBm
DC-DC converter.
Signal to co-channel interfer- C/ICC Desired signal 3 dB above refer- — 10.4 — dB

er, 0.1% BER ence sensitivity.
N+1 adjacent channel selec- C/I1+ Interferer is reference signal at +1 — -1.7 — dB

tivity, 0.1% BER, with allowa- MHz offset. Desired frequency
ble exceptions. Desired is 2402 MHz ≤ Fc ≤ 2480 MHz
reference signal at -67 dBm
N-1 adjacent channel selec- C/I1- Interferer is reference signal at -1 — -0.5 — dB

Alternate selectivity, 0.1% C/I2 Interferer is reference signal at ± 2 — -40.8 — dB

BER, with allowable excep- MHz offset. Desired frequency
tions. Desired is reference 2402 MHz ≤ Fc ≤ 2480 MHz
signal at -67 dBm

signal at -67 dBm
Selectivity to image frequen- C/IIM Interferer is reference signal at im- — -38.2 — dB

cy, 0.1% BER. Desired is ref- age frequency with 1 MHz preci-
erence signal at -67 dBm sion
Selectivity to image frequen- C/IIM+1 Interferer is reference signal at im- — -45.7 — dB

cy ± 1 MHz, 0.1% BER. De- age frequency ± 1 MHz with 1
sired is reference signal at MHz precision
-67 dBm
Blocking, less than 0.1% BLOCKOOB Interferer frequency 30 MHz ≤ f ≤ -5 — — dBm

BER. Desired is -67dBm 2000 MHz
BLE reference signal at
2426MHz. Interferer is CW in Interferer frequency 2003 MHz ≤ f -24 — — dBm
OOB range2 ≤ 2399 MHz
Interferer frequency 2484 MHz ≤ f -10 — — dBm

≤ 2997 MHz
Interferer frequency 3 GHz ≤ f ≤ 6 -10 — — dBm

GHz
Interferer frequency 6 GHz ≤ f ≤ -17 — — dBm

12.75 GHz
Note:
1. Reference signal is defined 2GFSK at -67 dBm, Modulation index = 0.5, BT = 0.5, Bit rate = 1 Mbps, desired data = PRBS9;
interferer data = PRBS15; frequency accuracy better than 1 ppm.
2. Interferer max power limited by equipment capabilities and path loss. Minimum specified at 25 °C.

4.1.9.5 RF Transmitter Characteristics for 2GFSK in the 2.4GHz Band, 2 Mbps Data Rate
85%.
Table 4.16. RF Transmitter Characteristics for 2GFSK in the 2.4GHz Band, 2 Mbps Data Rate
3kHz
Per FCC part 15.247 at 20 dBm — -4.7 — dBm/

3kHz
Per ETSI 300.328 at 10 dBm/1 — 10 — dBm

MHz

Emissions taken at CW carrier, Restricted Bands1 2 3
POUTMAX, PAVDD connec- 4
ted to external 3.3 V supply
Per FCC part 15.247, Above — -26 — dBc
[2400-2BW to 2400-BW] MHz, — -26 — dBm

[2483.5+BW to 2483.5+2BW]
EN300.440 174-230 MHz, 470-862 MHz
25-1000 MHz — -42 — dBm
1-12 GHz — -36 — dBm
Note:
3. For 2476 MHz, 7 dB of power backoff is used to achieve this value.

4.1.9.6 RF Receiver Characteristics for 2GFSK in the 2.4GHz Band, 2 Mbps Data Rate
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency = 38.4MHz. RF center frequency 2.45 GHz1.
Table 4.17. RF Receiver Characteristics for 2GFSK in the 2.4GHz Band, 2 Mbps Data Rate
DC-DC converter.
Signal to co-channel interfer- C/ICC Desired signal 3 dB above refer- — 7.3 — dB

er, 0.1% BER ence sensitivity.



signal at -67 dBm

signal at -67 dBm

Selectivity to image frequen- C/IIM+1 Interferer is reference signal at im- — -39 — dB

-67 dBm
Note:
1. For the BLE 2Mbps in-band blocking performance, there may be up to 5 spurious response channels where the requirement of
30.8% PER is not met and therefore an exception will need to be taken for each of these frequencies to meet the requirements of
the BLE standard.
2. Reference signal is defined 2GFSK at -67 dBm, Modulation index = 0.5, BT = 0.5, Bit rate = 2 Mbps, desired data = PRBS9;

4.1.9.7 RF Transmitter Characteristics for 2GFSK in the 2.4GHz Band, 500 kbps Data Rate
85%.
Table 4.18. RF Transmitter Characteristics for 2GFSK in the 2.4GHz Band, 500 kbps Data Rate
3kHz
Per FCC part 15.247 at 20 dBm1 — — 8 dBm/

3kHz

[2400-2BW to 2400-BW] MHz, — -26 — dBm

[2483.5+BW to 2483.5+2BW]
EN300.440 174-230 MHz, 470-862 MHz
25-1000 MHz — -42 — dBm
1-12 GHz — -36 — dBm
Note:
1. Output power limited to 14 dBm to ensure compliance with FCC specifications.

4.1.9.8 RF Receiver Characteristics for 2GFSK in the 2.4GHz Band, 500 kbps Data Rate
Table 4.19. RF Receiver Characteristics for 2GFSK in the 2.4GHz Band, 500 kbps Data Rate
Sensitivity, 0.1% BER SENS Signal is reference signal1. Using — -99 — dBm
DC-DC converter.
N+1 adjacent channel selec- C/I1+ Interferer is reference signal at +1 — -9 — dB

N-1 adjacent channel selec- C/I1- Interferer is reference signal at -1 — -9 — dB


signal at -72 dBm


-72 dBm
Note:
1. Reference signal is defined 2GFSK at -72 dBm, Modulation index = 0.5, BT = 0.5, Bit rate = 500 kbps, desired data = PRBS9;

4.1.9.9 RF Transmitter Characteristics for 2GFSK in the 2.4GHz Band, 125 kbps Data Rate
85%.
Table 4.20. RF Transmitter Characteristics for 2GFSK in the 2.4GHz Band, 125 kbps Data Rate
Power spectral density limit PSDLIMIT Per FCC part 15.247 at 10 dBm — -9 — dBm/
3kHz
Per FCC part 15.247 at 20 dBm1 — — 8 dBm/

3kHz

[2400-2BW to 2400-BW] MHz, — -26 — dBm

[2483.5+BW to 2483.5+2BW]
EN300.440 174-230 MHz, 470-862 MHz
25-1000 MHz — -42 — dBm
1-12 GHz — -36 — dBm
Note:
1. Output power limited to 14 dBm to ensure compliance with FCC specifications.

4.1.9.10 RF Receiver Characteristics for 2GFSK in the 2.4GHz Band, 125 kbps Data Rate
Table 4.21. RF Receiver Characteristics for 2GFSK in the 2.4GHz Band, 125 kbps Data Rate
DC-DC converter.




-79 dBm
Note:
1. Reference signal is defined 2GFSK at -79 dBm, Modulation index = 0.5, BT = 0.5, Bit rate = 125 kbps, desired data = PRBS9;

4.1.9.11 RF Transmitter Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 2.45 GHz. Maximum duty cycle
of 66%.
Table 4.22. RF Transmitter Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band
Error vector magnitude (off- EVM Average across frequency. Signal — 3.8 — % rms
set EVM), per 802.15.4-2011 is DSSS-OQPSK reference pack-
et1
Power spectral density limit PSDLIMIT Relative, at carrier ± 3.5 MHz, out- — -26 — dBc/
put power at POUTMAX 100kHz
Absolute, at carrier ± 3.5 MHz, — -36 — dBm/

output power at POUTMAX2 100kHz
Per FCC part 15.247, output pow- — -4.0 — dBm/

er at POUTMAX 3kHz
ETSI — 12.1 — dBm
per ETSI EN300.328 channels in band
Spurious emissions of har- SPURHRM_FCC_ Continuous transmission of modu- — -45.8 — dBm

monics in restricted bands R lated carrier
per FCC Part 15.205/15.209,
Emissions taken at
ted to external 3.3 V supply,
Test Frequency is 2450 MHz
Spurious emissions of har- SPURHRM_FCC_ Continuous transmission of modu- — -26 — dBc

monics in non-restricted NRR lated carrier
bands per FCC Part
15.247/15.35, Emissions tak-
en at POUTMAX, PAVDD
connected to external 3.3 V
supply, Test Frequency is
2450 MHz
Spurious emissions out-of- SPUROOB_FCC_ Restricted bands 30-88 MHz; con- — -61 — dBm
band (above 2.483 GHz or R tinuous transmission of modulated
below 2.4 GHz) in restricted carrier
bands, per FCC part
15.205/15.209, Emissions Restricted bands 88-216 MHz; — -58 — dBm
taken at POUTMAX, PAVDD continuous transmission of modu-
connected to external 3.3 V lated carrier
supply, Test Frequency = Restricted bands 216-960 MHz; — -55 — dBm
2450 MHz continuous transmission of modu-
lated carrier
Restricted bands >960 MHz; con- — -47 — dBm

tinuous transmission of modulated
carrier3 4

Spurious emissions out-of- SPUROOB_FCC_ Above 2.483 GHz or below 2.4 — -26 — dBc
band in non-restricted bands NR GHz; continuous transmission of
per FCC Part 15.247, Emis- modulated carrier
sions taken at POUTMAX,
PAVDD connected to exter-
nal 3.3 V supply, Test Fre-
quency = 2450 MHz
Spurious emissions out-of- SPURETSI328 [2400-BW to 2400], [2483.5 to — -16 — dBm

band; per ETSI 300.3285 2483.5+BW];
[2400-2BW to 2400-BW], — -26 — dBm

[2483.5+BW to 2483.5+2BW]; per
ETSI 300.328
EN300.4405 174-230 MHz, 470-862 MHz
25-1000 MHz, excluding above — -42 — dBm

frequencies
1G-14G — -36 — dBm
Note:
1. Reference packet is defined as 20 octet PSDU, modulated according to 802.15.4-2011 DSSS-OQPSK in the 2.4GHz band, with
pseudo-random packet data content.
5. Specified at maximum power output level of 10 dBm.

4.1.9.12 RF Receiver Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band
Table 4.23. RF Receiver Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band
level, 1% PER length is 20 octets.
Sensitivity, 1% PER SENS Signal is reference signal. Packet — -102.7 — dBm

length is 20 octets. Using DC-DC
converter.
Signal is reference signal. Packet — -102.7 — dBm

length is 20 octets. Without DC-
DC converter.
Co-channel interferer rejec- CCR Desired signal 3 dB above sensi- — -4.6 — dB

tion, 1% PER tivity limit
High-side adjacent channel ACRP1 Interferer is reference signal at +1 — 40.7 — dB

rejection, 1% PER. Desired channel-spacing.
is reference signal at 3dB
above reference sensitivity Interferer is filtered reference sig- — 47 — dB
level2 nal3 at +1 channel-spacing.
Interferer is CW at +1 channel- — 54.3 — dB

spacing4.
Low-side adjacent channel ACRM1 Interferer is reference signal at -1 — 40.8 — dB

rejection, 1% PER. Desired channel-spacing.
above reference sensitivity Interferer is filtered reference sig- — 47.5 — dB
level2 nal3 at -1 channel-spacing.
Interferer is CW at -1 channel- — 56.5 — dB

spacing.
Alternate channel rejection, ACR2 Interferer is reference signal at ± 2 — 51.5 — dB

1% PER. Desired is refer- channel-spacing
ence signal at 3dB above
reference sensitivity level2 Interferer is filtered reference sig- — 53.7 — dB
nal3 at ± 2 channel-spacing
Interferer is CW at ± 2 channel- — 62.4 — dB

spacing
Image rejection , 1% PER, IR Interferer is CW in image band4 — 50.4 — dB

Desired is reference signal at
3dB above reference sensi-
tivity level2
Blocking rejection of all other BLOCK Interferer frequency < Desired fre- — 58.5 — dB
channels. 1% PER, Desired quency - 3 channel-spacing
above reference sensitivity Interferer frequency > Desired fre- — 56.4 — dB
level2. Interferer is reference quency + 3 channel-spacing
signal
Blocking rejection of 802.11g BLOCK80211G Desired is reference signal at 6dB — 50 — dB

signal centered at +12MHz above reference sensitivity level2
or -13MHz5

Upper limit of input power RSSIMAX — — 5 dBm

range over which RSSI reso-
lution is maintained
Lower limit of input power RSSIMIN -98 — — dBm

RSSI resolution RSSIRES over RSSIMIN to RSSIMAX — 0.25 — dB
RSSI accuracy in the linear RSSILIN — +/-6 — dB

region as defined by
802.15.4-2003
Note:
1. Reference signal is defined as O-QPSK DSSS per 802.15.4, Frequency range = 2400-2483.5 MHz, Symbol rate = 62.5 ksym-
bols/s.
2. Reference sensitivity level is -85 dBm.
3. Filter is characterized as a symmetric bandpass centered on the adjacent channel having a 3dB bandwidth of 4.6 MHz and stop-
band rejection better than 26 dB beyond 3.15 MHz from the adjacent carrier.
4. Due to low-IF frequency, there is some overlap of adjacent channel and image channel bands. Adjacent channel CW blocker
tests place the Interferer center frequency at the Desired frequency ± 5 MHz on the channel raster, whereas the image rejection
test places the CW interferer near the image frequency of the Desired signal carrier, regardless of the channel raster.
5. This is an IEEE 802.11b/g ERP-PBCC 22 MBit/s signal as defined by the IEEE 802.11 specification and IEEE 802.11g adden-
dum.

4.1.10 Sub-GHz RF Transceiver Characteristics

4.1.10.1 Sub-GHz RF Transmitter characteristics for 915 MHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA
Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 915 MHz.
Table 4.24. Sub-GHz RF Transmitter characteristics for 915 MHz Band
RF tuning frequency range FRANGE 902 — 930 MHz
Maximum TX Power1 POUTMAX External PA supply = 3.3V, 20 18 19.8 23.3 dBm

dBm output power setting
External PA supply connected to 12.6 14.2 16.1 dBm

DC-DC output, 14 dBm output
power setting
Minimum active TX Power POUTMIN — -45.5 — dBm
Output power step size POUTSTEP output power > 0 dBm — 0.5 — dB
Output power variation vs POUTVAR_V 1.8 V < VVREGVDD < 3.3 V, Exter- — 4.8 — dB
supply at POUTMAX nal PA supply = 3.3 V, T = 25 °C
1.8 V < VVREGVDD < 3.3 V, Exter- — 1.9 — dB

nal PA supply connected to DC-
DC output, T = 25 °C
Output power variation vs POUTVAR_T -40 to +85 °C with External PA — 0.6 1.3 dB
temperature, peak to peak supply = 3.3 V
-40 to +125 °C with External PA — 0.8 1.6 dB

supply = 3.3 V

supply connected to DC-DC out-
put

put
Output power variation vs RF POUTVAR_F External PA supply = 3.3 V, T = — 0.2 0.6 dB

frequency 25 °C
External PA supply connected to — 0.3 0.6 dB

DC-DC output, T = 25 °C
Spurious emissions of har- SPURHARM_FCC In restricted bands, per FCC Part — -45 -42 dBm
monics at 20 dBm output _20 15.205 / 15.209
power, Conducted measure-
ment, 20dBm match, Exter- In non-restricted bands, per FCC — -26 -20 dBc
nal PA supply = 3.3V, Test Part 15.247
Frequency = 915 MHz

Spurious emissions out-of- SPUROOB_FCC_ In non-restricted bands, per FCC — -26 -20 dBc
band at 20 dBm output pow- 20 Part 15.247
er, Conducted measurement,
20dBm match, External PA In restricted bands (30-88 MHz), — -62 -56 dBm
supply = 3.3V, Test Frequen- per FCC Part 15.205 / 15.209
cy = 915 MHz
In restricted bands (88-216 MHz), — -61 -56 dBm
per FCC Part 15.205 / 15.209
In restricted bands (216-960 — -58 -52 dBm

MHz), per FCC Part 15.205 /
15.209
In restricted bands (>960 MHz), — -47 -42 dBm

per FCC Part 15.205 / 15.209
monics at 14 dBm output _14 15.205 / 15.209
nal PA supply connected to Part 15.247
DC-DC output, Test Fre-
quency = 915 MHz
Spurious emissions out-of- SPUROOB_FCC_ In non-restricted bands, per FCC — -26 -20 dBc
band at 14 dBm output pow- 14 Part 15.247
supply connected to DC-DC per FCC Part 15.205 / 15.209
output, Test Frequency =
915 MHz
per FCC Part 15.205 / 15.209

15.209

per FCC Part 15.205 / 15.209
Error vector magnitude (off- EVM Signal is DSSS-OQPSK reference — 1.0 2.8 %rms
set EVM), per 802.15.4-2011 packet. Modulated according to
802.15.4-2011 DSSS-OQPSK in
the 915MHz band, with pseudo-
random packet data content. Ex-
ternal PA supply = 3.3V.
Power spectral density limit2 PSD Relative, at carrier ± 1.2 MHz. — -37.1 -24.8 dBc/
Average spectral power shall be 100kHz
measured using a 100kHz resolu-
tion bandwidth. The reference lev-
el shall be the highest average
spectral power measured within ±
600kHz of the carrier frequency.
External PA supply = 3.3V.
Absolute, at carrier ± 1.2 MHz. — -24.2 -20 dBm/

Average spectral power shall be 100kHz
measured using a 100kHz resolu-
tion bandwidth. External PA sup-
ply = 3.3V.

Note:
2. Definition of reference signal is O-QPSK DSSS per 802.15.4, Frequency Range = 902-928 MHz, Data rate = 250 kbps, 16-chip
PN sequence mapping.

4.1.10.2 Sub-GHz RF Receiver Characteristics for 915 MHz Band
Table 4.25. Sub-GHz RF Receiver Characteristics for 915 MHz Band
Tuning frequency range FRANGE 902 — 930 MHz
Max usable input level, 0.1% SAT500K Desired is reference 500 kbps — 10 — dBm
BER GFSK signal1
Sensitivity SENS Desired is reference 4.8 kbps — -105.2 -100.7 dBm

OOK signal2, 20% PER, T ≤ 85 °C
Desired is reference 4.8 kbps — — -99.5 dBm

OOK signal2, 20% PER, T > 85
°C
Desired is reference 600 bps — -126.2 — dBm

GFSK signal3, 0.1% BER
Desired is reference 50 kbps — -108.2 -104.2 dBm

GFSK signal4, 0.1% BER, T ≤ 85
°C
Desired is reference 50 kbps — — -103.1 dBm

GFSK signal4, 0.1% BER, T > 85
°C

°C

°C

°C

°C
Desired is reference 400 kbps — -95.2 -91 dBm

4GFSK signal6, 1% PER, T ≤ 85
°C
Desired is reference 400 kbps — — -91 dBm

4GFSK signal6, 1% PER, T > 85
°C
Desired is reference O-QPSK — -100.1 — dBm

DSSS signal7, 1% PER, Payload
length is 20 octets
Level above which RFSENSETRIG CW at 915 MHz — -28.1 — dBm

Level below which RFSENSETHRES CW at 915 MHz — -50 — dBm


Adjacent channel selectivity, C/I1 Desired is 4.8 kbps OOK signal2 — 48.1 — dB
Interferer is CW at ± 1 × at 3dB above sensitivity level,
channel-spacing 20% PER
Desired is 600 bps GFSK signal3 — 71.4 — dB

at 3dB above sensitivity level,
0.1% BER
Desired is 50 kbps GFSK signal4 — 49.8 — dB

0.1% BER

0.1% BER

0.1% BER
Desired is 400 kbps 4GFSK sig- — 41.4 — dB

nal6 at 3dB above sensitivity level,
0.1% BER
Desired is reference O-QPSK — 49.1 — dB

DSSS signal7 at 3dB above sensi-
tivity level, 1% PER
Alternate channel selectivity, C/I2 Desired is 4.8 kbps OOK signal2 — 56.3 — dB
Desired is 600 bps GFSK signal3 — 74.7 — dB

0.1% BER

0.1% BER

0.1% BER

0.1% BER

0.1% BER


Image rejection, Interferer is C/IIMAGE Desired is 4.8 kbps OOK signal2 — 48.4 — dB
CW at image frequency at 3dB above sensitivity level,
20% PER

0.1% BER

0.1% BER

0.1% BER

0.1% BER

Blocking selectivity, 0.1% C/IBLOCKER Interferer CW at Desired ± 1 MHz — 58.7 — dB

BER. Desired is 100 kbps
GFSK signal at 3dB above Interferer CW at Desired ± 2 MHz — 62.5 — dB
sensitivity level
Interferer CW at Desired ± 10 — 76.4 — dB
MHz
Intermod selectivity, 0.1% C/IIM Desired is 100 kbps GFSK signal5 — 45 — dB

BER. CW interferers at 400 at 3dB above sensitivity level
kHz and 800 kHz offsets


RSSI resolution RSSIRES Over RSSIMIN to RSSIMAX range — 0.25 — dBm
Max spurious emissions dur- SPURRX_FCC 216-960 MHz — -55 -49.2 dBm
ing active receive mode, per
FCC Part 15.109(a) Above 960 MHz — -47 -41.2 dBm
Max spurious emissions dur- SPURRX_ARIB Below 710 MHz, RBW=100kHz — -60 -54 dBm
ing active receive mode,per
ARIB STD-T108 Section 3.3 710-900 MHz, RBW=1MHz — -61 -55 dBm
900-915 MHz, RBW=100kHz — -61 -55 dBm
915-930 MHz, RBW=100kHz — -61 -55 dBm
930-1000 MHz, RBW=100kHz — -61 -55 dBm
Above 1000 MHz, RBW=1MHz — -53 -47 dBm

Note:
1. Definition of reference signal is 500 kbps 2GFSK, BT=0.5, Δf = 175 kHz, RX channel BW = 835.076 kHz, channel spacing = 1
MHz.
2. Definition of reference signal is 4.8 kbps OOK, RX channel BW = 306.036 kHz, channel spacing = 500 kHz.
3. Definition of reference signal is 600 bps 2GFSK, BT=0.5, Δf = 0.3 kHz, RX channel BW = 1.2 kHz, channel spacing = 300 kHz.
4. Definition of reference signal is 50 kbps 2GFSK, BT=0.5, Δf = 25 kHz, RX channel BW = 99.012 kHz, channel spacing = 200 kHz.
kHz.
6. Definition of reference signal is 400 kbps 4GFSK, BT=0.5, inner deviation = 33.3 kHz, RX channel BW = 368.920 kHz, channel
spacing = 600 kHz.
7. Definition of reference signal is O-QPSK DSSS per 802.15.4, Frequency Range = 902-928 MHz, Data rate = 250 kbps, 16-chip
PN sequence mapping.

Maximum TX Power1 POUTMAX External PA supply = 3.3V, 20 17.1 19.3 22.9 dBm
dBm output power setting

DC-DC output, 14 dBm output
power setting
Minimum active TX Power POUTMIN — -43.5 — dBm
Output power variation vs POUTVAR_V 1.8 V < VVREGVDD < 3.3 V, Exter- — 5 — dB
supply at POUTMAX nal PA supply = 3.3 V, T = 25 °C
1.8 V < VVREGVDD < 3.3 V, Exter- — 2 — dB

nal PA supply connected to DC-
DC output, T = 25 °C
Output power variation vs POUTVAR_T -40 to +85 °C with External PA — 0.6 0.9 dB
temperature, peak to peak supply = 3.3 V

supply = 3.3 V

put

put
Output power variation vs RF POUTVAR_F External PA supply = 3.3 V, T = — 0.2 0.6 dB

frequency 25 °C
External PA supply connected to — 0.2 0.8 dB

DC-DC output, T = 25 °C
Spurious emissions of har- SPURHARM_ETSI Per ETSI EN 300-220, Section — -35 -30 dBm
monics, Conducted meas- 7.8.2.1, External PA supply con-
urement, Test Frequency = nected to: DCDC at 14 dBm, or
868 MHz 3.3 V at 19.5 dBm

Spurious emissions out-of- SPUROOB_ETSI Per ETSI EN 300-220, Section — -59 -54 dBm
band, Conducted measure- 7.8.2.1 (47-74 MHz, 87.5-118
ment, Test Frequency = 868 MHz, 174-230 MHz, and 470-862
MHz MHz), External PA supply connec-
ted to: DCDC at 14 dBm, or 3.3 V
at 19.5 dBm
Per ETSI EN 300-220, Section — -42 -36 dBm

7.8.2.1 (other frequencies below 1
GHz), External PA supply connec-
at 19.5 dBm

7.8.2.1 (frequencies above 1
GHz), External PA supply connec-
at 19.5 dBm
Error vector magnitude (off- EVM Signal is DSSS-BPSK reference — 5.7 — %rms
set EVM), per 802.15.4-2015 packet. Modulated according to
802.15.4-2015 DSSS-BPSK in the
868MHz band, with pseudo-ran-
dom packet data content. External
PA supply connected to external
3.3V supply
Note:

Max usable input level, 0.1% SAT2k4 Desired is reference 2.4 kbps — 10 — dBm
BER GFSK signal1
BER GFSK signal2
Sensitivity SENS Desired is reference 2.4 kbps — -120.6 — dBm

Desired is reference 38.4 kbps — -109.5 -105.4 dBm

°C

°C
Desired is reference 500 kbps — -96.4 — dBm



Adjacent channel selectivity, C/I1 Desired is 2.4 kbps GFSK signal1 44.5 56.9 — dB
channel-spacing 0.1% BER
Desired is 38.4kbps GFSK signal2 35.4 43 — dB

0.1% BER
Alternate channel selectivity, C/I2 Desired is 2.4kbps GFSK signal1 — 56.8 — dB

Desired is 38.4kbps GFSK signal2 — 48.2 — dB

0.1% BER
Image rejection, Interferer is C/IIMAGE Desired is 2.4kbps GFSK signal1 — 50.2 — dB

0.1% BER

0.1% BER

BER. Desired is 2.4 kbps
GFSK signal1 at 3 dB above Interferer CW at Desired ± 2 MHz — 77.5 — dB
sensitivity level Interferer CW at Desired ± 10 — 90.4 — dB
MHz



Max spurious emissions dur- SPURRX 30 MHz to 1 GHz — -63 -57 dBm
ing active receive mode
1 GHz to 12 GHz — -53 -47 dBm
Note:
1. Definition of reference signal is 2.4 kbps 2GFSK, BT=0.5, Δf = 1.2 kHz, RX channel BW = 4.797 kHz, channel spacing = 12.5
kHz.
2. Definition of reference signal is 38.4 kbps 2GFSK, BT=0.5, Δf = 20 kHz, RX channel BW = 74.809 kHz, channel spacing = 100
kHz.
3. Definition of reference signal is 500 kbps 2GFSK, BT=0.5, Δf = 125 kHz, RX channel BW = 753.320 kHz.

Maximum TX Power1 POUTMAX External PA supply = 3.3V 18.1 20.3 23.7 dBm
Minimum active TX Power POUTMIN -44.9 — dBm
Output power variation vs POUTVAR_V at 20 dBm;1.8 V < VVREGVDD < — 4.3 — dB

supply, peak to peak 3.3 V, External PA supply connec-
ted directly to external supply, T =
25 °C
Output power variation vs POUTVAR_T -40 to +85 °C at 20 dBm — 0.2 0.9 dB

temperature, peak to peak
-40 to +125 °C at 20 dBm — 0.3 1.3 dB
Output power variation vs RF POUTVAR_F T = 25 °C — 0.2 0.4 dB

frequency
Harmonic emissions, 20 SPURHARM_CN Per China SRW Requirement, — -40 -36 dBm
dBm output power setting, Section 2.1, frequencies below
490 MHz 1GHz
Per China SRW Requirement, — -36 -30 dBm

Section 2.1, frequencies above
1GHz
Spurious emissions, 20 dBm SPUROOB_CN Per China SRW Requirement, — -54 — dBm
output power setting, 490 Section 3 (48.5-72.5MHz,
MHz 76-108MHz, 167-223MHz,
470-556MHz, and 606-798MHz)
Per China SRW Requirement, — -42 — dBm

Section 2.1 (other frequencies be-
low 1GHz)
Per China SRW Requirement, — -36 — dBm

Section 2.1 (frequencies above
1GHz)
Note:

BER GFSK signal1
BER GFSK signal2


°C

°C

°C

°C

°C

°C
Level above which RFSENSETRIG Desired is reference 100 kbps — -28.1 — dBm
RFSENSE will trigger5 GFSK signal4, 0.1% BER

Adjacent channel selectivity, C/I1 Desired is 2.4 kbps GFSK signal1 48 60.3 — dB
Desired is 38.4kbps GFSK signal2 38.3 45.6 — dB

0.1% BER


0.1% BER


0.1% BER

0.1% BER

sensitivity level Interferer CW at Desired ± 10 — 90.2 — dB
MHz


1 GHz to 12 GHz — -53 -47 dBm
Note:
kHz.
kHz.

Maximum TX Power1 POUTMAX External PA supply connected to 12.5 15.1 17.4 dBm
DC-DC output, 14dBm output
power

DC-DC output, 10dBm output
power
Minimum active TX Power POUTMIN — -42 — dBm
Output power variation vs POUTVAR_V At 10 dBm;1.8 V < VVREGVDD < — 1.7 — dB

supply, peak to peak, Pout = 3.3 V, External PA supply = DC-
10dBm DC output, T = 25 °C
Output power variation vs POUTVAR_T -40 to +85C at 10dBm — 0.5 1.2 dB

temperature, peak to peak,
Pout= 10dBm -40 to +125C at 10dBm — 0.7 1.7 dB

frequency, Pout = 10dBm
monics FCC, Conducted 15.205 / 15.209
measurement, 14dBm
match, External PA supply In non-restricted bands, per FCC — -26 -20 dBc
connected to DC-DC output, Part 15.231
Test Frequency = 434 MHz
Spurious emissions out-of- SPUROOB_FCC In non-restricted bands, per FCC — -26 -20 dBc
band FCC, Conducted Part 15.231
measurement, 14dBm
match, External PA supply In restricted bands (30-88 MHz), — -52 -46 dBm
connected to DC-DC output, per FCC Part 15.205 / 15.209
per FCC Part 15.205 / 15.209

15.209

per FCC Part 15.205 / 15.209
Spurious emissions of har- SPURHARM_ETSI Per ETSI EN 300-220, Section — -42 -36 dBm
monics ETSI, Conducted 7.8.2.1 (frequencies below 1Ghz)
measurement, 14dBm
match, External PA supply Per ETSI EN 300-220, Section — -36 -30 dBm
connected to DC-DC output, 7.8.2.1 (frequencies above 1Ghz)

band ETSI, Conducted 7.8.2.1 (47-74 MHz, 87.5-118
measurement, 14dBm MHz, 174-230 MHz, and 470-862
match, External PA supply MHz)
connected to DC-DC output,
Test Frequency = 434 MHz Per ETSI EN 300-220, Section — -42 -36 dBm
GHz)

GHz)
Note:

BER GFSK signal1
Max usable input level, 0.1% SAT50k Desired is reference 50 kbps — 10 — dBm
BER GFSK signal2

OOK signal3, 20% PER

°C

°C

°C

°C
Desired is reference 2.4 kbps — -123.1 — dBm

Desired is reference 9.6 kbps — -112.6 -109 dBm

GFSK signal5, 1% PER, T ≤ 85 °C
Desired is reference 9.6 kbps — — -108 dBm

GFSK signal5, 1% PER, T > 85 °C



Adjacent channel selectivity, C/I1 Desired is 4.8 kbps OOK signal3 — 51.6 — dB
Desired is 100 kbps GFSK signal4 35 44.1 — dB

0.1% BER
Desired is 2.4 kbps GFSK signal1 47 61.5 — dB

0.1% BER
Desired is 50 kbps GFSK signal2 45.6 53.1 — dB

0.1% BER
Desired is 9.6 kbps 4GFSK sig- — 35.7 — dB

1% PER
Alternate channel selectivity, C/I2 Desired is 4.8 kbps OOK signal3 — 57.8 — dB

0.1% BER
Desired is 2.4 kbps GFSK signal1 — 62.4 — dB

0.1% BER

0.1% BER
Desired is 9.6 kbps 4GFSK sig- — 50.6 — dB

1% PER
Image rejection, Interferer is C/IIMAGE Desired is 4.8 kbps OOK signal3 — 46.5 — dB
20% PER

0.1% BER
Desired is 2.4 kbps GFSK signal1 — 57.5 — dB

0.1% BER

0.1% BER
Desired is 9.6 kbps 4GFSK sig- — 48 — dB

1% PER

GFSK signal1 at 3dB above Interferer CW at Desired ± 2 MHz — 77.2 — dB
sensitivity level Interferer CW at Desired ± 10 — 92 — dB
MHz

Intermod selectivity, 0.1% C/IIM Desired is 2.4 kbps GFSK signal1 — 58.8 — dB
BER. CW interferers at 12.5 at 3dB above sensitivity level
kHz and 25 kHz offsets


Max spurious emissions dur- SPURRX_FCC 216-960 MHz — -55 -49 dBm
FCC Part 15.109(a) Above 960 MHz — -47 -41 dBm
Max spurious emissions dur- SPURRX_ETSI Below 1000 MHz — -63 -57 dBm
ETSI 300-220 Section 8.6 Above 1000 MHz — -53 -47 dBm
Max spurious emissions dur- SPURRX_ARIB Below 710 MHz, RBW=100kHz — -60 -54 dBm
ARIB STD T67 Section
3.3(5)
Note:
kHz.
2. Definition of reference signal is 50 kbps 2GFSK, BT=0.5, Δf = 25 kHz, RX channel BW = 99.012 kHz, channel spacing = 200 kHz.
3. Definition of reference signal is 4.8 kbps OOK, RX channel BW = 306.036 kHz, channel spacing = 500 kHz.
kHz.
5. Definition of reference signal is 9.6 kbps 4GFSK, BT=0.5, inner deviation = 0.8 kHz, RX channel BW = 8.5 kHz, channel spacing
= 12.5 kHz.

Maximum TX Power1 POUTMAX External PA supply connected to 13.8 17.2 21.1 dBm
DC-DC output
Output power variation vs POUTVAR_V 1.8 V < VVREGVDD < 3.3 V, Exter- — 1.8 — dB
supply nal PA supply = DC-DC output, T
= 25 °C
Output power variation vs POUTVAR_T -40 to +85C — 0.5 1.2 dB

temperature
-40 to +125C — 0.7 1.5 dB

frequency
monics at 14 dBm output 15.205 / 15.209
nal PA supply connected to Part 15.231
DC-DC output, Test Fre-
quency = 303 MHz
Spurious emissions out-of- SPUROOB_FCC In non-restricted bands, per FCC — -26 -20 dBc
band at 14 dBm output pow- Part 15.231
supply connected to DC-DC per FCC Part 15.205 / 15.209
output, Test Frequency =
303 MHz
per FCC Part 15.205 / 15.209

15.209

per FCC Part 15.205 / 15.209
Note:

BER GFSK signal1
BER GFSK signal2
Sensitivity SENS Desired is reference 2.4 kbps — -123.2 -120.7 dBm

°C

°C

°C

°C

°C

°C


Adjacent channel selectivity, C/I1 Desired is 2.4 kbps GFSK signal1 54.1 63.6 — dB

0.1% BER


at 3dB above sensitivity level2,
0.1% BER

Image rejection, Interferer is C/IIMAGE Desired is 2.4kbps GFSK signal1 — 53 — dB

0.1% BER

0.1% BER
Blocking selectivity, 0.1% C/IBLOCKER Interferer CW at Desired ± 1 MHz — 75 — dB

sensitivity level Interferer CW at Desired ± 10 72.6 91.9 — dB
MHz


Max spurious emissions dur- SPURRX_FCC 216-960 MHz — -63 -57 dBm
FCC Part 15.109(a) Above 960MHz — -53 -47 dBm
Note:
kHz.
kHz.

4.1.10.11 Sub-GHz RF Transmitter Characteristics for 169 MHz Band
Table 4.34. Sub-GHz RF Transmitter Characteristics for 169 MHz Band
Maximum TX Power1 POUTMAX External PA supply = 3.3 V 18.1 19.7 22.4 dBm
Output power variation vs POUTVAR_V 1.8 V < VVREGVDD < 3.3 V, Exter- — 4.8 5.0 dB
supply, peak to peak nal PA supply = 3.3 V, T = 25 °C
Output power variation vs POUTVAR_T -40 to +85 °C at 20 dBm — 0.6 1.2 dB

temperature, peak to peak
-40 to +125 °C at 20 dBm — 0.8 1.5 dB
Spurious emissions of har- SPURHARM_ETSI Per ETSI EN 300-220, Section — -42 — dBm
monics, Conducted meas- 7.8.2.1 (47-74 MHz, 87.5-118
urement, External PA supply MHz, 174-230 MHz, and 470-862
= 3.3 V, Test Frequency = MHz)
169 MHz
Per ETSI EN 300-220, Section — -38 — dBm
GHz)2
Per ETSI EN 300-220, Section — -36 — dBm

GHz)2
band, Conducted measure- 7.8.2.1 (47-74 MHz, 87.5-118
ment, External PA supply = MHz, 174-230 MHz, and 470-862
3.3 V, Test Frequency = 169 MHz)
MHz
GHz)

GHz)
Note:
2. Typical value marginally passes specification. Additional margin can be obtained by increasing the order of the harmonic filter.

BER GFSK signal1
BER GFSK signal2
Sensitivity SENS Desired is reference 2.4 kbps — -124 — dBm

Desired is reference 38.4 kbps — -112.2 -108 dBm

°C

°C

°C

°C


Adjacent channel selectivity, C/I1 Desired is 2.4 kbps GFSK signal1 — 64.8 — dB
Interferer is CW at ± 1 x at 3dB above sensitivity level,
Desired is 38.4kbps GFSK signal1 43.3 51.4 — dB

0.1% BER

Interferer is CW at ± 2 x at 3dB above sensitivity level,

0.1% BER

0.1% BER

0.1% BER


GFSK signal1 at 3 dB above Interferer CW at Desired ± 2 MHz — 75 — dB
sensitivity level Interferer CW at Desired ± 10 80 90.1 — dB
MHz


1 GHz to 12 GHz — -53 -47 dBm
Note:
kHz.
kHz.
4.1.11 Modem
Table 4.36. Modem
Receive bandwidth BWRX Configurable range with 38.4 MHz 0.1 — 2530 kHz
crystal
IF frequency fIF Configurable range with 38.4 MHz 150 — 1371 kHz
crystal. Selected steps available.
DSSS symbol length SLDSSS Configurable in steps of 1 chip 2 — 32 chips
DSSS bits per symbol BPSDSSS Configurable 1 — 4 bits/

symbol

4.1.12 Oscillators
4.1.12.1 Low-Frequency Crystal Oscillator (LFXO)
Table 4.37. Low-Frequency Crystal Oscillator (LFXO)
Crystal frequency fLFXO — 32.768 — kHz
Supported crystal equivalent ESRLFXO — — 70 kΩ

series resistance (ESR)
Supported range of crystal CLFXO_CL 6 — 18 pF

load capacitance 1
On-chip tuning cap range 2 CLFXO_T On each of LFXTAL_N and 8 — 40 pF

LFXTAL_P pins
On-chip tuning cap step size SSLFXO — 0.25 — pF
Current consumption after ILFXO ESR = 70 kOhm, CL = 7 pF, — 273 — nA

startup 3 GAIN4 = 2, AGC4 = 1
Start- up time tLFXO ESR = 70 kOhm, CL = 7 pF, — 308 — ms

GAIN4 = 2
Note:
1. Total load capacitance as seen by the crystal.
2. The effective load capacitance seen by the crystal will be CLFXO_T /2. This is because each XTAL pin has a tuning cap and the
two caps will be seen in series by the crystal.
3. Block is supplied by AVDD if ANASW = 0, or DVDD if ANASW=1 in EMU_PWRCTRL register.
4. In CMU_LFXOCTRL register.

4.1.12.2 High-Frequency Crystal Oscillator (HFXO)
Table 4.38. High-Frequency Crystal Oscillator (HFXO)
Crystal frequency fHFXO 38.4 MHz required for radio trans- 38 38.4 40 MHz
ciever operation
Supported crystal equivalent ESRHFXO_38M4 Crystal frequency 38.4 MHz — — 60 Ω

series resistance (ESR)
Supported range of crystal CHFXO_CL 6 — 12 pF

load capacitance 1
On-chip tuning cap range 2 CHFXO_T On each of HFXTAL_N and 9 20 25 pF

HFXTAL_P pins
On-chip tuning capacitance SSHFXO — 0.04 — pF

step
Startup time tHFXO 38.4 MHz, ESR = 50 Ohm, CL = — 300 — µs

10 pF
Frequency tolerance for the FTHFXO 38.4 MHz, ESR = 50 Ohm, CL = -40 — 40 ppm
crystal 10 pF
Note:
1. Total load capacitance as seen by the crystal.
2. The effective load capacitance seen by the crystal will be CHFXO_T /2. This is because each XTAL pin has a tuning cap and the
two caps will be seen in series by the crystal.
4.1.12.3 Low-Frequency RC Oscillator (LFRCO)
Table 4.39. Low-Frequency RC Oscillator (LFRCO)
Oscillation frequency fLFRCO ENVREF1 = 1, T ≤ 85 °C 31.3 32.768 33.6 kHz
ENVREF1 = 1, T > 85 °C 31.6 32.768 36.8 kHz
ENVREF1 = 0, T ≤ 85 °C 31.3 32.768 33.4 kHz
ENVREF1 = 0, T > 85 °C 30 32.768 33.4 kHz
Startup time tLFRCO — 500 — µs
Current consumption 2 ILFRCO ENVREF = 1 in — 342 — nA

CMU_LFRCOCTRL
ENVREF = 0 in — 494 — nA
CMU_LFRCOCTRL
Note:
1. In CMU_LFRCOCTRL register.
2. Block is supplied by AVDD if ANASW = 0, or DVDD if ANASW=1 in EMU_PWRCTRL register.

4.1.12.4 High-Frequency RC Oscillator (HFRCO)
Table 4.40. High-Frequency RC Oscillator (HFRCO)
Frequency accuracy fHFRCO_ACC At production calibrated frequen- -2.5 — 2.5 %

cies, across supply voltage and
temperature
Start-up time tHFRCO fHFRCO ≥ 19 MHz — 300 — ns
4 < fHFRCO < 19 MHz — 1 — µs
fHFRCO ≤ 4 MHz — 2.5 — µs
Current consumption on all IHFRCO fHFRCO = 38 MHz — 267 299 µA

supplies
fHFRCO = 32 MHz — 224 248 µA
fHFRCO = 26 MHz — 189 211 µA
fHFRCO = 19 MHz — 154 172 µA
fHFRCO = 16 MHz — 133 148 µA
fHFRCO = 13 MHz — 118 135 µA
fHFRCO = 7 MHz — 89 100 µA
Coarse trim step size (% of SSHFRCO_COARS — 0.8 — %

period) E
Fine trim step size (% of pe- SSHFRCO_FINE — 0.1 — %

riod)
Period jitter PJHFRCO — 0.2 — % RMS
Frequency limits fHFRCO_BAND FREQRANGE = 0, FINETUNIN- 3.47 — 6.15 MHz

GEN = 0
FREQRANGE = 3, FINETUNIN- 6.24 — 11.45 MHz

GEN = 0

GEN = 0

GEN = 0

GEN = 0

GEN = 0
FREQRANGE = 11, FINETUNIN- 27.27 — 48 MHz

GEN = 0
FREQRANGE = 12, FINETUNIN- 33.33 — 54 MHz

GEN = 0

4.1.12.5 Auxiliary High-Frequency RC Oscillator (AUXHFRCO)
Table 4.41. Auxiliary High-Frequency RC Oscillator (AUXHFRCO)
Frequency accuracy fAUXHFRCO_ACC At production calibrated frequen- -3 — 3 %

cies, across supply voltage and
temperature
Start-up time tAUXHFRCO fAUXHFRCO ≥ 19 MHz — 400 — ns
4 < fAUXHFRCO < 19 MHz — 1.4 — µs
fAUXHFRCO ≤ 4 MHz — 2.5 — µs
Current consumption on all IAUXHFRCO fAUXHFRCO = 38 MHz — 187 207 µA

supplies
fAUXHFRCO = 32 MHz — 152 168 µA
Coarse trim step size (% of SSAUXHFR- — 0.8 — %

period) CO_COARSE
Fine trim step size (% of pe- SSAUXHFR- — 0.1 — %

riod) CO_FINE
Period jitter PJAUXHFRCO — 0.2 — % RMS
4.1.12.6 Ultra-low Frequency RC Oscillator (ULFRCO)
Table 4.42. Ultra-low Frequency RC Oscillator (ULFRCO)
Oscillation frequency fULFRCO 0.95 1 1.07 kHz

4.1.13 Flash Memory Characteristics1
Table 4.43. Flash Memory Characteristics1
Flash erase cycles before ECFLASH 10000 — — cycles

failure
Flash data retention RETFLASH T ≤ 85 °C 10 — — years
T ≤ 125 °C 10 — — years
Word (32-bit) programming tW_PROG Burst write, 128 words, average 20 26.3 30 µs
time time per word
Single word 62 68.9 80 µs
Page erase time2 tPERASE 20 29.5 40 ms
Mass erase time3 tMERASE 20 30 40 ms
Device erase time4 5 tDERASE T ≤ 85 °C — 56.2 70 ms
T ≤ 125 °C — 56.2 75 ms
Erase current6 IERASE Page Erase — — 2.0 mA
Write current6 IWRITE — — 3.5 mA
Supply voltage during flash VFLASH 1.62 — 3.6 V

erase and write
Note:
1. Flash data retention information is published in the Quarterly Quality and Reliability Report.
2. From setting the ERASEPAGE bit in MSC_WRITECMD to 1 until the BUSY bit in MSC_STATUS is cleared to 0. Internal setup
and hold times for flash control signals are included.
3. Mass erase is issued by the CPU and erases all flash.
4. Device erase is issued over the AAP interface and erases all flash, SRAM, the Lock Bit (LB) page, and the User data page Lock
Word (ULW).
5. From setting the DEVICEERASE bit in AAP_CMD to 1 until the ERASEBUSY bit in AAP_STATUS is cleared to 0. Internal setup
and hold times for flash control signals are included.
6. Measured at 25 °C.

4.1.14 General-Purpose I/O (GPIO)
Table 4.44. General-Purpose I/O (GPIO)
Input low voltage1 VIL GPIO pins — — IOVDD*0.3 V
Input high voltage1 VIH GPIO pins IOVDD*0.7 — — V
Output high voltage relative VOH Sourcing 3 mA, IOVDD ≥ 3 V, IOVDD*0.8 — — V

to IOVDD
DRIVESTRENGTH2 = WEAK
Sourcing 1.2 mA, IOVDD ≥ 1.62 IOVDD*0.6 — — V

V,
Sourcing 20 mA, IOVDD ≥ 3 V, IOVDD*0.8 — — V
DRIVESTRENGTH2 = STRONG
Sourcing 8 mA, IOVDD ≥ 1.62 V, IOVDD*0.6 — — V
Output low voltage relative to VOL Sinking 3 mA, IOVDD ≥ 3 V, — — IOVDD*0.2 V

IOVDD
Sinking 1.2 mA, IOVDD ≥ 1.62 V, — — IOVDD*0.4 V
Sinking 20 mA, IOVDD ≥ 3 V, — — IOVDD*0.2 V
Sinking 8 mA, IOVDD ≥ 1.62 V, — — IOVDD*0.4 V
Input leakage current IIOLEAK All GPIO except LFXO pins, GPIO — 0.1 30 nA
≤ IOVDD, T ≤ 85 °C
LFXO Pins, GPIO ≤ IOVDD, T ≤ — 0.1 50 nA

85 °C
All GPIO except LFXO pins, GPIO — — 110 nA

≤ IOVDD, T > 85 °C
LFXO Pins, GPIO ≤ IOVDD, T > — — 250 nA

85 °C
Input leakage current on I5VTOLLEAK IOVDD < GPIO ≤ IOVDD + 2 V — 3.3 15 µA

5VTOL pads above IOVDD
I/O pin pull-up/pull-down re- RPUD 30 40 65 kΩ

sistor3
Pulse width of pulses re- tIOGLITCH 15 25 45 ns

moved by the glitch suppres-
sion filter

Output fall time, From 70% tIOOF CL = 50 pF, — 1.8 — ns

to 30% of VIO
DRIVESTRENGTH2 = STRONG,
SLEWRATE2 = 0x6
CL = 50 pF, — 4.5 — ns
DRIVESTRENGTH2 = WEAK,
SLEWRATE2 = 0x6
Output rise time, From 30% tIOOR CL = 50 pF, — 2.2 — ns

to 70% of VIO
DRIVESTRENGTH2 = STRONG,
SLEWRATE = 0x62
CL = 50 pF, — 7.4 — ns
DRIVESTRENGTH2 = WEAK,
SLEWRATE2 = 0x6
Note:
1. GPIO input threshold are proportional to the IOVDD supply, except for RESETn which is proportional to AVDD.
2. In GPIO_Pn_CTRL register.
3. GPIO pull-ups are referenced to the IOVDD supply, except for RESETn, which connects to AVDD.

4.1.15 Voltage Monitor (VMON)
Table 4.45. Voltage Monitor (VMON)
Supply current (including IVMON In EM0 or EM1, 1 active channel, — 6.3 8 µA

I_SENSE) T ≤ 85 °C
In EM0 or EM1, 1 active channel, — — 10 µA

T > 85 °C
In EM0 or EM1, All channels ac- — 12.5 15 µA

tive, T ≤ 85 °C
In EM0 or EM1, All channels ac- — — 18 µA

tive, T > 85 °C
In EM2, EM3 or EM4, 1 channel — 62 — nA

active and above threshold
In EM2, EM3 or EM4, 1 channel — 62 — nA

active and below threshold
In EM2, EM3 or EM4, All channels — 99 — nA

active and above threshold
In EM2, EM3 or EM4, All channels — 99 — nA

active and below threshold
Loading of monitored supply ISENSE In EM0 or EM1 — 2 — µA
In EM2, EM3 or EM4 — 2 — nA
Threshold range VVMON_RANGE 1.62 — 3.4 V
Threshold step size NVMON_STESP Coarse — 200 — mV
Fine — 20 — mV
Response time tVMON_RES Supply drops at 1V/µs rate — 460 — ns
Hysteresis VVMON_HYST — 26 — mV

4.1.16 Analog to Digital Converter (ADC)
Specified at 1 Msps, ADCCLK = 16 MHz, BIASPROG = 0, GPBIASACC = 0, unless otherwise indicated.
Table 4.46. Analog to Digital Converter (ADC)
Resolution VRESOLUTION 6 — 12 Bits
Input voltage range1 VADCIN Single ended — — VFS V
Differential -VFS/2 — VFS/2 V
Input range of external refer- VADCREFIN_P 1 — VAVDD V

ence voltage, single ended
and differential
Power supply rejection2 PSRRADC At DC — 80 — dB
Analog input common mode CMRRADC At DC — 80 — dB

rejection ratio
Current from all supplies, us- IADC_CONTINU- 1 Msps / 16 MHz ADCCLK, BIA- — 270 290 µA
ing internal reference buffer. OUS_LP SPROG = 0, GPBIASACC = 1 4
Continuous operation. WAR-
MUPMODE3 = KEEPADC- 250 ksps / 4 MHz ADCCLK, BIA- — 125 — µA
WARM SPROG = 6, GPBIASACC = 1 4
62.5 ksps / 1 MHz ADCCLK, BIA- — 80 — µA

SPROG = 15, GPBIASACC = 1 4
Current from all supplies, us- IADC_NORMAL_LP 35 ksps / 16 MHz ADCCLK, BIA- — 45 — µA
ing internal reference buffer. SPROG = 0, GPBIASACC = 1 4
Duty-cycled operation. WAR-
MUPMODE3 = NORMAL 5 ksps / 16 MHz ADCCLK BIA- — 8 — µA
Current from all supplies, us- IADC_STAND- 125 ksps / 16 MHz ADCCLK, BIA- — 105 — µA
ing internal reference buffer. BY_LP SPROG = 0, GPBIASACC = 1 4
Duty-cycled operation.
AWARMUPMODE3 = KEEP- 35 ksps / 16 MHz ADCCLK, BIA- — 70 — µA
INSTANDBY or KEEPIN- SPROG = 0, GPBIASACC = 1 4
SLOWACC
Current from all supplies, us- IADC_CONTINU- 1 Msps / 16 MHz ADCCLK, BIA- — 325 — µA
ing internal reference buffer. OUS_HP SPROG = 0, GPBIASACC = 0 4
Continuous operation. WAR-
MUPMODE3 = KEEPADC- 250 ksps / 4 MHz ADCCLK, BIA- — 175 — µA
WARM SPROG = 6, GPBIASACC = 0 4
62.5 ksps / 1 MHz ADCCLK, BIA- — 125 — µA

Current from all supplies, us- IADC_NORMAL_HP 35 ksps / 16 MHz ADCCLK, BIA- — 85 — µA
ing internal reference buffer. SPROG = 0, GPBIASACC = 0 4
Duty-cycled operation. WAR-
MUPMODE3 = NORMAL 5 ksps / 16 MHz ADCCLK BIA- — 16 — µA
Current from all supplies, us- IADC_STAND- 125 ksps / 16 MHz ADCCLK, BIA- — 160 — µA
ing internal reference buffer. BY_HP SPROG = 0, GPBIASACC = 0 4
Duty-cycled operation.
AWARMUPMODE3 = KEEP- 35 ksps / 16 MHz ADCCLK, BIA- — 125 — µA
INSTANDBY or KEEPIN- SPROG = 0, GPBIASACC = 0 4
SLOWACC
Current from HFPERCLK IADC_CLK HFPERCLK = 16 MHz — 140 — µA

ADC clock frequency fADCCLK — — 16 MHz
Throughput rate fADCRATE — — 1 Msps
Conversion time5 tADCCONV 6 bit — 7 — cycles
8 bit — 9 — cycles
12 bit — 13 — cycles
Startup time of reference tADCSTART WARMUPMODE3 = NORMAL — — 5 µs

generator and ADC core
WARMUPMODE3 = KEEPIN- — — 2 µs
STANDBY
WARMUPMODE3 = KEEPINSLO- — — 1 µs
WACC
SNDR at 1Msps and fIN = SNDRADC Internal reference6, differential 58 67 — dB

10kHz measurement
External reference7, differential — 68 — dB

measurement
Spurious-free dynamic range SFDRADC 1 MSamples/s, 10 kHz full-scale — 75 — dB

(SFDR) sine wave
Differential non-linearity DNLADC 12 bit resolution, No missing co- -1 — 2 LSB

(DNL) des
Integral non-linearity (INL), INLADC 12 bit resolution -6 — 6 LSB

End point method
Offset error VADCOFFSETERR -3 0 3 LSB
Gain error in ADC VADCGAIN Using internal reference — -0.2 3.5 %
Using external reference — -1 — %
Temperature sensor slope VTS_SLOPE — -1.84 — mV/°C
Note:
1. The absolute voltage allowed at any ADC input is dictated by the power rail supplied to on-chip circuitry, and may be lower than
the effective full scale voltage. All ADC inputs are limited to the ADC supply (AVDD or DVDD depending on
EMU_PWRCTRL_ANASW). Any ADC input routed through the APORT will further be limited by the IOVDD supply to the pin.
2. PSRR is referenced to AVDD when ANASW=0 and to DVDD when ANASW=1 in EMU_PWRCTRL.
3. In ADCn_CTRL register.
4. In ADCn_BIASPROG register.
5. Derived from ADCCLK.
6. Internal reference option used corresponds to selection 2V5 in the SINGLECTRL_REF or SCANCTRL_REF register field. The
differential input range with this configuration is ± 1.25 V. Typical value is characterized using full-scale sine wave input. Minimum
value is production-tested using sine wave input at 1.5 dB lower than full scale.
7. External reference is 1.25 V applied externally to ADCnEXTREFP, with the selection CONF in the SINGLECTRL_REF or
SCANCTRL_REF register field and VREFP in the SINGLECTRLX_VREFSEL or SCANCTRLX_VREFSEL field. The differential
input range with this configuration is ± 1.25 V.

4.1.17 Analog Comparator (ACMP)
Table 4.47. Analog Comparator (ACMP)
Input voltage range VACMPIN ACMPVDD = — — VACMPVDD V

ACMPn_CTRL_PWRSEL 1
Supply voltage VACMPVDD BIASPROG2 ≤ 0x10 or FULL- 1.8 — VVREGVDD_ V

BIAS2 = 0 MAX
0x10 < BIASPROG2 ≤ 0x20 and 2.1 — VVREGVDD_ V

FULLBIAS2 = 1 MAX
Active current not including IACMP BIASPROG2 = 1, FULLBIAS2 = 0 — 50 — nA

voltage reference3
BIASPROG2 = 0x10, FULLBIAS2 — 306 — nA
=0
BIASPROG2 = 0x02, FULLBIAS2 — 6.1 11 µA

=1
BIASPROG2 = 0x20, FULLBIAS2 — 74 92 µA

=1
Current consumption of inter- IACMPREF VLP selected as input using 2.5 V — 50 — nA

nal voltage reference3 Reference / 4 (0.625 V)
VLP selected as input using VDD — 20 — nA
VBDIV selected as input using — 4.1 — µA

1.25 V reference / 1
VADIV selected as input using — 2.4 — µA

VDD/1

Hysteresis (VCM = 1.25 V, VACMPHYST HYSTSEL4 = HYST0 -3 0 3 mV

BIASPROG2 = 0x10, FULL-
HYSTSEL4 = HYST1 5 18 27 mV
BIAS2 = 1)
HYSTSEL4 = HYST8 -3 0 3 mV
HYSTSEL4 = HYST9 -27 -18 -5 mV
HYSTSEL4 = HYST13 -104 -67 -26 mV
HYSTSEL4 = HYST14 -130 -78 -30 mV
HYSTSEL4 = HYST15 -155 -88 -34 mV
Comparator delay5 tACMPDELAY BIASPROG2 = 1, FULLBIAS2 = 0 — 30 95 µs
BIASPROG2 = 0x10, FULLBIAS2 — 3.7 10 µs

=0
BIASPROG2 = 0x02, FULLBIAS2 — 360 1000 ns

=1
BIASPROG2 = 0x20, FULLBIAS2 — 35 — ns

=1
Offset voltage VACMPOFFSET BIASPROG2 =0x10, FULLBIAS2 -35 — 35 mV

=1
Reference voltage VACMPREF Internal 1.25 V reference 1 1.25 1.47 V
Internal 2.5 V reference 1.98 2.5 2.8 V
Capacitive sense internal re- RCSRES CSRESSEL6 = 0 — infinite — kΩ

sistance
CSRESSEL6 = 1 — 15 — kΩ

Note:
1. ACMPVDD is a supply chosen by the setting in ACMPn_CTRL_PWRSEL and may be IOVDD, AVDD or DVDD.
2. In ACMPn_CTRL register.
3. The total ACMP current is the sum of the contributions from the ACMP and its internal voltage reference. IACMPTOTAL = IACMP +
IACMPREF.
4. In ACMPn_HYSTERESIS registers.
5. ± 100 mV differential drive.
6. In ACMPn_INPUTSEL register.

4.1.18 Digital to Analog Converter (VDAC)
DRIVESTRENGTH = 2 unless otherwise specified. Primary VDAC output.
Table 4.48. Digital to Analog Converter (VDAC)
Output voltage VDACOUT Single-Ended 0 — VVREF V
Differential1 -VVREF — VVREF V
Current consumption includ- IDAC 500 ksps, 12-bit, DRIVES- — 396 — µA

ing references (2 channels)2 TRENGTH = 2, REFSEL = 4
44.1 ksps, 12-bit, DRIVES- — 72 — µA

TRENGTH = 1, REFSEL = 4
200 Hz refresh rate, 12-bit Sam- — 1.2 — µA

ple-Off mode in EM2, DRIVES-
TRENGTH = 2, REFSEL = 4,
SETTLETIME = 0x02, WARMUP-
TIME = 0x0A
Current from HFPERCLK3 IDAC_CLK — 5.8 — µA/MHz
Sample rate SRDAC — — 500 ksps
DAC clock frequency fDAC — — 1 MHz
Conversion time tDACCONV fDAC = 1MHz 2 — — µs
Settling time tDACSETTLE 50% fs step settling to 5 LSB — 2.5 — µs
Startup time tDACSTARTUP Enable to 90% fs output, settling — — 12 µs

to 10 LSB
Output impedance ROUT DRIVESTRENGTH = 2, 0.4 V ≤ — 2 — Ω

VOUT ≤ VOPA - 0.4 V, -8 mA <
IOUT < 8 mA, Full supply range
DRIVESTRENGTH = 0 or 1, 0.4 V — 2 — Ω
≤ VOUT ≤ VOPA - 0.4 V, -400 µA <
IOUT < 400 µA, Full supply range
DRIVESTRENGTH = 2, 0.1 V ≤ — 2 — Ω
VOUT ≤ VOPA - 0.1 V, -2 mA <
IOUT < 2 mA, Full supply range
≤ VOUT ≤ VOPA - 0.1 V, -100 µA <
IOUT < 100 µA, Full supply range
Power supply rejection ratio4 PSRR Vout = 50% fs. DC — 65.5 — dB

Signal to noise and distortion SNDRDAC 500 ksps, single-ended, internal — 60.4 — dB
ratio (1 kHz sine wave), 1.25V reference
Noise band limited to 250
kHz 500 ksps, single-ended, internal — 61.6 — dB
2.5V reference
500 ksps, single-ended, 3.3V — 64.0 — dB

VDD reference
500 ksps, differential, internal — 63.3 — dB

1.25V reference

2.5V reference
500 ksps, differential, 3.3V VDD — 65.8 — dB

reference
Signal to noise and distortion SNDRDAC_BAND 500 ksps, single-ended, internal — 65.3 — dB
ratio (1 kHz sine wave), 1.25V reference
Noise band limited to 22 kHz
500 ksps, single-ended, internal — 66.7 — dB
2.5V reference
500 ksps, single-ended, 3.3V — 70.0 — dB

VDD reference

1.25V reference

2.5V reference
500 ksps, differential, 3.3V VDD — 68.5 — dB

reference
Total harmonic distortion THD — 70.2 — dB
Differential non-linearity5 DNLDAC -0.99 — 1 LSB
Intergral non-linearity INLDAC -4 — 4 LSB
Offset error6 VOFFSET T = 25 °C -8 — 8 mV
Across operating temperature -25 — 25 mV

range
Gain error6 VGAIN T = 25 °C, Low-noise internal ref- -2.5 — 2.5 %

erence (REFSEL = 1V25LN or
2V5LN)
T = 25 °C, Internal reference (RE- -5 — 5 %

FSEL = 1V25 or 2V5)
T = 25 °C, External reference -1.8 — 1.8 %

(REFSEL = VDD or EXT)
Across operating temperature -3.5 — 3.5 %

range, Low-noise internal refer-
ence (REFSEL = 1V25LN or
2V5LN)

range, Internal reference (RE-
FSEL = 1V25 or 2V5)

range, External reference (RE-
FSEL = VDD or EXT)

External load capactiance, CLOAD — — 75 pF

OUTSCALE=0
Note:
1. In differential mode, the output is defined as the difference between two single-ended outputs. Absolute voltage on each output is
limited to the single-ended range.
2. Supply current specifications are for VDAC circuitry operating with static output only and do not include current required to drive
the load.
3. Current from HFPERCLK is dependent on HFPERCLK frequency. This current contributes to the total supply current used when
the clock to the DAC peripheral is enabled in the CMU.
4. PSRR calculated as 20 * log10(ΔVDD / ΔVOUT), VDAC output at 90% of full scale
5. Entire range is monotonic and has no missing codes.
6. Gain is calculated by measuring the slope from 10% to 90% of full scale. Offset is calculated by comparing actual VDAC output at
10% of full scale to ideal VDAC output at 10% of full scale with the measured gain.

4.1.19 Current Digital to Analog Converter (IDAC)
Table 4.49. Current Digital to Analog Converter (IDAC)
Number of ranges NIDAC_RANGES — 4 — ranges
Output current IIDAC_OUT RANGESEL1 = RANGE0 0.05 — 1.6 µA
RANGESEL1 = RANGE1 1.6 — 4.7 µA
RANGESEL1 = RANGE2 0.5 — 16 µA
RANGESEL1 = RANGE3 2 — 64 µA
Linear steps within each NIDAC_STEPS — 32 — steps

range
Step size SSIDAC RANGESEL1 = RANGE0 — 50 — nA
RANGESEL1 = RANGE1 — 100 — nA
RANGESEL1 = RANGE2 — 500 — nA
RANGESEL1 = RANGE3 — 2 — µA
Total accuracy, STEPSEL1 = ACCIDAC EM0 or EM1, AVDD=3.3 V, T = 25 -3 — 3 %

0x10 °C
EM0 or EM1, Across operating -18 — 22 %

temperature range
EM2 or EM3, Source mode, RAN- — -2 — %

GESEL1 = RANGE0, AVDD=3.3
V, T = 25 °C
EM2 or EM3, Source mode, RAN- — -1.7 — %

V, T = 25 °C

V, T = 25 °C

V, T = 25 °C
EM2 or EM3, Sink mode, RAN- — -0.7 — %

V, T = 25 °C

V, T = 25 °C

V, T = 25 °C

V, T = 25 °C

Start up time tIDAC_SU Output within 1% of steady state — 5 — µs

value
Settling time, (output settled tIDAC_SETTLE Range setting is changed — 5 — µs

within 1% of steady state val-
ue), Step value is changed — 1 — µs
Current consumption2 IIDAC EM0 or EM1 Source mode, ex- — 11 15 µA

cluding output current, Across op-
erating temperature range
EM0 or EM1 Sink mode, exclud- — 13 18 µA

ing output current, Across operat-
ing temperature range
EM2 or EM3 Source mode, ex- — 0.023 — µA

cluding output current, T = 25 °C
EM2 or EM3 Sink mode, exclud- — 0.041 — µA

ing output current, T = 25 °C
EM2 or EM3 Source mode, ex- — 11 — µA

cluding output current, T ≥ 85 °C
EM2 or EM3 Sink mode, exclud- — 13 — µA

ing output current, T ≥ 85 °C
Output voltage compliance in ICOMP_SRC RANGESEL1 = RANGE0, output — 0.11 — %

source mode, source current voltage = min(VIOVDD,
change relative to current VAVDD2-100 mV)
sourced at 0 V
RANGESEL1 = RANGE1, output — 0.06 — %
voltage = min(VIOVDD,
VAVDD2-100 mV)

VAVDD2-150 mV)

VAVDD2-250 mV)
Output voltage compliance in ICOMP_SINK RANGESEL1 = RANGE0, output — 0.12 — %

sink mode, sink current voltage = 100 mV
change relative to current
sunk at IOVDD RANGESEL1 = RANGE1, output — 0.05 — %
voltage = 100 mV

voltage = 150 mV

voltage = 250 mV
Note:
1. In IDAC_CURPROG register.
2. The IDAC is supplied by either AVDD, DVDD, or IOVDD based on the setting of ANASW in the EMU_PWRCTRL register and
PWRSEL in the IDAC_CTRL register. Setting PWRSEL to 1 selects IOVDD. With PWRSEL cleared to 0, ANASW selects be-
tween AVDD (0) and DVDD (1).

4.1.20 Capacitive Sense (CSEN)
Table 4.50. Capacitive Sense (CSEN)
Single conversion time (1x tCNV 12-bit SAR Conversions — 20.2 — µs

accumulation)
16-bit SAR Conversions — 26.4 — µs
Delta Modulation Conversion (sin- — 1.55 — µs

gle comparison)
Maximum external capacitive CEXTMAX IREFPROG=7 (Gain = 1x), includ- — 68 — pF

load ing routing parasitics
IREFPROG=0 (Gain = 10x), in- — 680 — pF

cluding routing parasitics
Maximum external series im- REXTMAX — 1 — kΩ

pedance
Supply current, EM2 bonded ICSEN_BOND 12-bit SAR conversions, 20 ms — 326 — nA

conversions, WARMUP- conversion rate, IREFPROG=7
MODE=NORMAL, WAR- (Gain = 1x), 10 channels bonded
MUPCNT=0 (total capacitance of 330 pF)1
Delta Modulation conversions, 20 — 226 — nA

ms conversion rate, IRE-
FPROG=7 (Gain = 1x), 10 chan-
nels bonded (total capacitance of
330 pF)1
12-bit SAR conversions, 200 ms — 33 — nA

conversion rate, IREFPROG=7
(Gain = 1x), 10 channels bonded
(total capacitance of 330 pF)1
Delta Modulation conversions, — 25 — nA

200 ms conversion rate, IRE-
FPROG=7 (Gain = 1x), 10 chan-
nels bonded (total capacitance of
330 pF)1
Supply current, EM2 scan ICSEN_EM2 12-bit SAR conversions, 20 ms — 690 — nA

conversions, WARMUP- scan rate, IREFPROG=0 (Gain =
MODE=NORMAL, WAR- 10x), 8 samples per scan1
MUPCNT=0
Delta Modulation conversions, 20 — 515 — nA
ms scan rate, 8 comparisons per
sample (DMCR = 1, DMR = 2),
IREFPROG=0 (Gain = 10x), 8
samples per scan1
12-bit SAR conversions, 200 ms — 79 — nA

scan rate, IREFPROG=0 (Gain =
10x), 8 samples per scan1
Delta Modulation conversions, — 57 — nA

200 ms scan rate, 8 comparisons
per sample (DMCR = 1, DMR =
2), IREFPROG=0 (Gain = 10x), 8
samples per scan1

Supply current, continuous ICSEN_ACTIVE SAR or Delta Modulation conver- — 90.5 — µA

conversions, WARMUP- sions of 33 pF capacitor, IRE-
MODE=KEEPCSENWARM FPROG=0 (Gain = 10x), always
on
HFPERCLK supply current ICSEN_HFPERCLK Current contribution from — 2.25 — µA/MHz

HFPERCLK when clock to CSEN
block is enabled.
Note:
1. Current is specified with a total external capacitance of 33 pF per channel. Average current is dependent on how long the periph-
eral is actively sampling channels within the scan period, and scales with the number of samples acquired. Supply current for a
specific application can be estimated by multiplying the current per sample by the total number of samples per period (total_cur-
rent = single_sample_current * (number_of_channels * accumulation)).

4.1.21 Operational Amplifier (OPAMP)
Unless otherwise indicated, specified conditions are: Non-inverting input configuration, VDD = 3.3 V, DRIVESTRENGTH = 2, MAIN-
OUTEN = 1, CLOAD = 75 pF with OUTSCALE = 0, or CLOAD = 37.5 pF with OUTSCALE = 1. Unit gain buffer and 3X-gain connection as
specified in table footnotes1 2.
Table 4.51. Operational Amplifier (OPAMP)
Supply voltage (from AVDD) VOPA HCMDIS = 0, Rail-to-rail input 2 — 3.8 V

range
HCMDIS = 1 1.62 — 3.8 V
Input voltage VIN HCMDIS = 0, Rail-to-rail input VVSS — VOPA V

range
HCMDIS = 1 VVSS — VOPA-1.2 V
Input impedance RIN 100 — — MΩ
Output voltage VOUT VVSS — VOPA V
Load capacitance3 CLOAD OUTSCALE = 0 — — 75 pF
OUTSCALE = 1 — — 37.5 pF
Output impedance ROUT DRIVESTRENGTH = 2 or 3, 0.4 V — 0.25 — Ω

≤ VOUT ≤ VOPA - 0.4 V, -8 mA <
IOUT < 8 mA, Buffer connection,
Full supply range
DRIVESTRENGTH = 0 or 1, 0.4 V — 0.6 — Ω

≤ VOUT ≤ VOPA - 0.4 V, -400 µA <
IOUT < 400 µA, Buffer connection,
Full supply range
DRIVESTRENGTH = 2 or 3, 0.1 V — 0.4 — Ω

≤ VOUT ≤ VOPA - 0.1 V, -2 mA <
IOUT < 2 mA, Buffer connection,
Full supply range
≤ VOUT ≤ VOPA - 0.1 V, -100 µA <
IOUT < 100 µA, Buffer connection,
Full supply range
Internal closed-loop gain GCL Buffer connection 0.99 1 1.01 -
3x Gain connection 2.93 2.99 3.05 -
16x Gain connection 15.07 15.7 16.33 -
Active current4 IOPA DRIVESTRENGTH = 3, OUT- — 580 — µA

SCALE = 0
DRIVESTRENGTH = 2, OUT- — 176 — µA

SCALE = 0
DRIVESTRENGTH = 1, OUT- — 13 — µA
SCALE = 0
DRIVESTRENGTH = 0, OUT- — 4.7 — µA

SCALE = 0

Open-loop gain GOL DRIVESTRENGTH = 3 — 135 — dB
DRIVESTRENGTH = 2 — 137 — dB
Loop unit-gain frequency5 UGF DRIVESTRENGTH = 3, Buffer — 3.38 — MHz

connection
DRIVESTRENGTH = 2, Buffer — 0.9 — MHz

connection
DRIVESTRENGTH = 1, Buffer — 132 — kHz

connection
DRIVESTRENGTH = 0, Buffer — 34 — kHz

connection
DRIVESTRENGTH = 3, 3x Gain — 2.57 — MHz

connection
DRIVESTRENGTH = 2, 3x Gain — 0.71 — MHz

connection
DRIVESTRENGTH = 1, 3x Gain — 113 — kHz

connection
DRIVESTRENGTH = 0, 3x Gain — 28 — kHz

connection
Phase margin PM DRIVESTRENGTH = 3, Buffer — 67 — °

connection
DRIVESTRENGTH = 2, Buffer — 69 — °
connection
connection
connection
Output voltage noise NOUT DRIVESTRENGTH = 3, Buffer — 146 — µVrms

connection, 10 Hz - 10 MHz
DRIVESTRENGTH = 2, Buffer — 163 — µVrms



DRIVESTRENGTH = 3, 3x Gain — 313 — µVrms





Slew rate6 SR DRIVESTRENGTH = 3, — 4.7 — V/µs

INCBW=17
DRIVESTRENGTH = 3, — 1.5 — V/µs

INCBW=0

INCBW=17

INCBW=0

INCBW=17

INCBW=0

INCBW=17

INCBW=0
Startup time8 TSTART DRIVESTRENGTH = 2 — — 12 µs
Input offset voltage VOSI DRIVESTRENGTH = 2 or 3, T = -2 — 2 mV

25 °C
DRIVESTRENGTH = 1 or 0, T = -2 — 2 mV
25 °C
DRIVESTRENGTH = 2 or 3, -12 — 12 mV
across operating temperature
range
DRIVESTRENGTH = 1 or 0, -30 — 30 mV
across operating temperature
range
DC power supply rejection PSRRDC Input referred — 70 — dB

ratio9
DC common-mode rejection CMRRDC Input referred — 70 — dB

ratio9
Total harmonic distortion THDOPA DRIVESTRENGTH = 2, 3x Gain — 90 — dB

connection, 1 kHz, VOUT = 0.1 V
to VOPA - 0.1 V
DRIVESTRENGTH = 0, 3x Gain — 90 — dB
connection, 0.1 kHz, VOUT = 0.1 V
to VOPA - 0.1 V

Note:
1. Specified configuration for Unit gain buffer configuration is: INCBW = 0, HCMDIS = 0, RESINSEL = DISABLE. VINPUT = 0.5 V,
VOUTPUT = 0.5 V.
2. Specified configuration for 3X-Gain configuration is: INCBW = 1, HCMDIS = 1, RESINSEL = VSS, VINPUT = 0.5 V, VOUTPUT = 1.5
V. Nominal voltage gain is 3.
3. If the maximum CLOAD is exceeded, an isolation resistor is required for stability. See AN0038 for more information.
4. Current into the load resistor is excluded. When the OPAMP is connected with closed-loop gain > 1, there will be extra current to
drive the resistor feedback network. The internal resistor feedback network has total resistance of 143.5 kOhm, which will cause
another ~10 µA current when the OPAMP drives 1.5 V between output and ground.
5. In unit gain connection, UGF is the gain-bandwidth product of the OPAMP. In 3x Gain connection, UGF is the gain-bandwidth
product of the OPAMP and 1/3 attenuation of the feedback network.
6. Step between 0.2V and VOPA-0.2V, 10%-90% rising/falling range.
7. When INCBW is set to 1 the OPAMP bandwidth is increased. This is allowed only when the non-inverting close-loop gain is ≥ 3,
or the OPAMP may not be stable.
8. From enable to output settled. In sample-and-off mode, RC network after OPAMP will contribute extra delay. Settling error < 1mV.
9. When HCMDIS=1 and input common mode transitions the region from VOPA-1.4V to VOPA-1V, input offset will change. PSRR
and CMRR specifications do not apply to this transition region.
4.1.22 Pulse Counter (PCNT)
Table 4.52. Pulse Counter (PCNT)
Input frequency FIN Asynchronous Single and Quad- — — 10 MHz

rature Modes
Sampled Modes with Debounce — — 8 kHz

filter set to 0.
4.1.23 Analog Port (APORT)
Table 4.53. Analog Port (APORT)
Supply current1 2 IAPORT Operation in EM0/EM1 — 7 — µA
Operation in EM2/EM3 — 63 — nA
Note:
1. Supply current increase that occurs when an analog peripheral requests access to APORT. This current is not included in repor-
ted peripheral currents. Additional peripherals requesting access to APORT do not incur further current.
2. Specified current is for continuous APORT operation. In applications where the APORT is not requested continuously (e.g. peri-
odic ACMP requests from LESENSE in EM2), the average current requirements can be estimated by mutiplying the duty cycle of
the requests by the specified continuous current number.

4.1.24 I2C
4.1.24.1 I2C Standard-mode (Sm)1
Table 4.54. I2C Standard-mode (Sm)1
SCL clock frequency2 fSCL 0 — 100 kHz
SCL clock low time tLOW 4.7 — — µs
SCL clock high time tHIGH 4 — — µs
SDA set-up time tSU_DAT 250 — — ns
SDA hold time3 tHD_DAT 100 — 3450 ns
Repeated START condition tSU_STA 4.7 — — µs

set-up time
(Repeated) START condition tHD_STA 4 — — µs

hold time
STOP condition set-up time tSU_STO 4 — — µs
Bus free time between a tBUF 4.7 — — µs

STOP and START condition
Note:
1. For CLHR set to 0 in the I2Cn_CTRL register.
2. For the minimum HFPERCLK frequency required in Standard-mode, refer to the I2C chapter in the reference manual.
3. The maximum SDA hold time (tHD_DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW).

4.1.24.2 I2C Fast-mode (Fm)1
Table 4.55. I2C Fast-mode (Fm)1
SCL clock high time tHIGH 0.6 — — µs
SDA hold time3 tHD_DAT 100 — 900 ns

set-up time
(Repeated) START condition tHD_STA 0.6 — — µs

hold time
STOP condition set-up time tSU_STO 0.6 — — µs

Note:
1. For CLHR set to 1 in the I2Cn_CTRL register.
2. For the minimum HFPERCLK frequency required in Fast-mode, refer to the I2C chapter in the reference manual.
3. The maximum SDA hold time (tHD,DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW).

4.1.24.3 I2C Fast-mode Plus (Fm+)1
Table 4.56. I2C Fast-mode Plus (Fm+)1
SCL clock high time tHIGH 0.26 — — µs
SDA hold time tHD_DAT 100 — — ns

set-up time
(Repeated) START condition tHD_STA 0.26 — — µs

hold time
STOP condition set-up time tSU_STO 0.26 — — µs

Note:
1. For CLHR set to 0 or 1 in the I2Cn_CTRL register.
2. For the minimum HFPERCLK frequency required in Fast-mode Plus, refer to the I2C chapter in the reference manual.

4.1.25 USART SPI
SPI Master Timing
Table 4.57. SPI Master Timing
SCLK period 1 2 3 tSCLK 2* — — ns

tHFPERCLK
CS to MOSI 1 2 tCS_MO -12.5 — 14 ns
SCLK to MOSI 1 2 tSCLK_MO -8.5 — 10.5 ns
MISO setup time 1 2 tSU_MI IOVDD = 1.62 V 90 — — ns
IOVDD = 3.0 V 42 — — ns
MISO hold time 1 2 tH_MI -9 — — ns
Note:
1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0).
2. Measurement done with 8 pF output loading at 10% and 90% of VDD (figure shows 50% of VDD).
3. tHFPERCLK is one period of the selected HFPERCLK.
CS tCS_MO
tSCKL_MO
SCLK
CLKPOL = 0
tSCLK
SCLK
CLKPOL = 1
MOSI
tSU_MI tH_MI
MISO
Figure 4.1. SPI Master Timing Diagram

SPI Slave Timing
Table 4.58. SPI Slave Timing
SCLK period 1 2 3 tSCLK 6* — — ns

tHFPERCLK
SCLK high time1 2 3 tSCLK_HI 2.5 * — — ns

tHFPERCLK
SCLK low time1 2 3 tSCLK_LO 2.5 * — — ns

tHFPERCLK
CS active to MISO 1 2 tCS_ACT_MI 4 — 70 ns
CS disable to MISO 1 2 tCS_DIS_MI 4 — 50 ns
MOSI setup time 1 2 tSU_MO 12.5 — — ns
MOSI hold time 1 2 3 tH_MO 13 — — ns
SCLK to MISO 1 2 3 tSCLK_MI 6 + 1.5 * — 45 + 2.5 * ns

tHFPERCLK tHFPERCLK
Note:
1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0).
2. Measurement done with 8 pF output loading at 10% and 90% of VDD (figure shows 50% of VDD).
3. tHFPERCLK is one period of the selected HFPERCLK.
CS tCS_ACT_MI
tCS_DIS_MI
SCLK
CLKPOL = 0
tSCLK_HI tSCLK_LO
SCLK
CLKPOL = 1 tSU_MO
tSCLK
tH_MO
MOSI
tSCLK_MI
MISO
Figure 4.2. SPI Slave Timing Diagram
4.2 Typical Performance Curves
Typical performance curves indicate typical characterized performance under the stated conditions.

4.2.1 Supply Current
Figure 4.3. EM0 Active Mode Typical Supply Current vs. Temperature

Figure 4.4. EM1 Sleep Mode Typical Supply Current vs. Temperature
Typical supply current for EM2, EM3 and EM4H using standard software libraries from Silicon Laboratories.

Figure 4.5. EM2, EM3, EM4H and EM4S Typical Supply Current vs. Temperature

Figure 4.6. EM0 and EM1 Mode Typical Supply Current vs. Supply
Typical supply current for EM2, EM3 and EM4H using standard software libraries from Silicon Laboratories.

Figure 4.7. EM2, EM3, EM4H and EM4S Typical Supply Current vs. Supply

Default test conditions: CCM mode, LDCDC = 4.7 μH, CDCDC = 4.7 μF, VDCDC_I = 3.3 V, VDCDC_O = 1.8 V, FDCDC_LN = 7 MHz
Figure 4.8. DC-DC Converter Typical Performance Characteristics

Load Step Response in LN (CCM) mode

LN (CCM) and LP mode transition (load: 5mA) (Heavy Drive)
DVDD DVDD
60mV/div 20mV/div
offset:1.8V offset:1.8V
100mA
VSW ILOAD
2V/div 1mA
offset:1.8V
100μs/div 10μs/div
Figure 4.9. DC-DC Converter Transition Waveforms

4.2.3 2.4 GHz Radio
Figure 4.10. 2.4 GHz RF Transmitter Output Power

Figure 4.11. 2.4 GHz RF Receiver Sensitivity

Typical Connection Diagrams
5. Typical Connection Diagrams
5.1 Power
Typical power supply connections for direct supply, without using the internal DC-DC converter, are shown in the following figure.
VDD
Main +
Supply –
VREGVDD AVDD IOVDD
VREGSW
HFXTAL_N
VREGVSS
HFXTAL_P
DVDD LFXTAL_N
LFXTAL_P
DECOUPLE
RFVDD PAVDD
Figure 5.1. EFR32FG13 Typical Application Circuit: Direct Supply Configuration without DC-DC converter
Typical power supply circuits using the internal DC-DC converter are shown below. The MCU operates from the DC-DC converter sup-
ply. For low RF transmit power applications less than 13dBm, the RF PA may be supplied by the DC-DC converter. For OPNs support-
ing high power RF transmission, the RF PA must be directly supplied by VDD for RF transmit power greater than 13 dBm.
VDD
Main +
Supply –
VREGVDD AVDD IOVDD
VDCDC
VREGSW
HFXTAL_N
VREGVSS
HFXTAL_P
DVDD LFXTAL_N
LFXTAL_P
DECOUPLE
RFVDD PAVDD
Figure 5.2. EFR32FG13 Typical Application Circuit: Configuration with DC-DC converter (PAVDD from VDCDC)

VDD
Main +
Supply –
VREGVDD AVDD IOVDD
VDCDC
VREGSW
HFXTAL_N
VREGVSS
HFXTAL_P
DVDD LFXTAL_N
LFXTAL_P
DECOUPLE
RFVDD PAVDD
Figure 5.3. EFR32FG13 Typical Application Circuit: Configuration with DC-DC converter (PAVDD from VDD)

5.2 RF Matching Networks
Typical RF matching network circuit diagrams are shown in Figure 5.4 Typical 2.4 GHz RF impedance-matching network circuits on
page 121 for applications in the 2.4GHz band, and in Figure 5.5 Typical Sub-GHz RF impedance-matching network circuits on page
121 for applications in the sub-GHz band. Application-specific component values can be found in application notes AN923: EFR32 sub-
GHz Matching Guide and AN930: EFR32 2.4 GHz Matching Guide. For low RF transmit power applications less than 13dBm, the two-
element match is recommended. For OPNs supporting high power RF transmission, the four-element match is recommended for high
RF transmit power (> 13dBm). As an addition resource, application note AN1081: Integrated Passive Devices for EFR32 Sub-GHz RF
Matching provides a list of supported Integrated Passive Devices (IPDs) along with design and layout considerations that can further
simplify the external RF matching network for sub-GHz applications.
2-Element Match for 2.4GHz Band 4-Element Match for 2.4GHz Band
PAVDD PAVDD
PAVDD PAVDD
L0 L0 L1
2G4RF_IOP 50Ω 2G4RF_IOP 50Ω
C0 C0 C1
2G4RF_ION 2G4RF_ION
Figure 5.4. Typical 2.4 GHz RF impedance-matching network circuits
Sub-GHz Match Topology I (169-500 MHz)
External PA Supply
L1 L2
C0 L3 C5 L5 L6 L7
SUBGRF_IN 50Ω
C2
L0 C4 C7 C8 C9 C10
C3
SUBGRF_IP
C1 L4 C6 BAL1
SUBGRF_ON
SUBGRF_OP
Sub-GHz Match Topology 2 (500-915 MHz)
C0 L3 External PA Supply L5 L6
SUBGRF_IN 50Ω
L0 C4 C7 C8 C9
SUBGRF_IP
L4 BAL1
C1
SUBGRF_ON
SUBGRF_OP
Figure 5.5. Typical Sub-GHz RF impedance-matching network circuits

5.3 Other Connections
Other components or connections may be required to meet the system-level requirements. Application Note AN0002: "Hardware De-
sign Considerations" contains detailed information on these connections. Application Notes can be accessed on the Silicon Labs web-
site (www.silabs.com/32bit-appnotes).

Pin Definitions
6. Pin Definitions
6.1 QFN48 2.4 GHz and Sub-GHz Device Pinout
Figure 6.1. QFN48 2.4 GHz and Sub-GHz Device Pinout
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the sup-
ported features for each GPIO pin, see 6.6 GPIO Functionality Table or 6.7 Alternate Functionality Overview.
Table 6.1. QFN48 2.4 GHz and Sub-GHz Device Pinout
Pin Name Pin(s) Description Pin Name Pin(s) Description
VSS 0 Ground PF0 1 GPIO (5V)
PF1 2 GPIO (5V) PF2 3 GPIO (5V)
PF7 8 GPIO (5V) RFVDD 9 Radio power supply
HFXTAL_N 10 High Frequency Crystal input pin. HFXTAL_P 11 High Frequency Crystal output pin.

Pin Definitions
Reset input, active low. This pin is inter-

nally pulled up to AVDD. To apply an
external reset source to this pin, it is re- Sub GHz Differential RF output, positive
RESETn 12 SUBGRF_OP 13
quired to only drive this pin low during path.
reset, and let the internal pull-up ensure
that reset is released.
Sub GHz Differential RF output, nega- Sub GHz Differential RF input, positive
SUBGRF_ON 14 SUBGRF_IP 15
tive path. path.
Sub GHz Differential RF input, negative

SUBGRF_IN 16 RFVSS 17 Radio Ground
path.
2.4 GHz Differential RF input/output,

Power Amplifier (PA) voltage regulator
PAVSS 18 2G4RF_ION 19 negative path. This pin should be exter-
VSS
nally grounded.
2.4 GHz Differential RF input/output, Power Amplifier (PA) voltage regulator

2G4RF_IOP 20 PAVDD 21
positive path. VDD input
PD13 22 GPIO PD14 23 GPIO
PD15 24 GPIO PA0 25 GPIO
PA1 26 GPIO PA2 27 GPIO
PA5 30 GPIO (5V) PB11 31 GPIO
PB12 32 GPIO PB13 33 GPIO
AVDD 34 Analog power supply. PB14 35 GPIO
PB15 36 GPIO VREGVSS 37 Voltage regulator VSS
VREGSW 38 DCDC regulator switching node VREGVDD 39 Voltage regulator VDD input
Decouple output for on-chip voltage

regulator. An external decoupling ca-
DVDD 40 Digital power supply. DECOUPLE 41 pacitor is required at this pin. This pin
should not be used to power any exter-
nal circuits.
IOVDD 42 Digital IO power supply. PC6 43 GPIO (5V)
PC7 44 GPIO (5V) PC8 45 GPIO (5V)
PC11 48 GPIO (5V)
Note:
1. GPIO with 5V tolerance are indicated by (5V).

Pin Definitions
6.2 QFN48 2.4 GHz Device Pinout
Figure 6.2. QFN48 2.4 GHz Device Pinout
Table 6.2. QFN48 2.4 GHz Device Pinout

Pin Definitions

external reset source to this pin, it is re-
RESETn 12 NC 13 No Connect.
quired to only drive this pin low during

RFVSS 14 Radio Ground PAVSS 15
VSS

2G4RF_ION 16 negative path. This pin should be exter- 2G4RF_IOP 17
positive path.
nally grounded.

PAVDD 18 PD10 19 GPIO (5V)
VDD input
PD11 20 GPIO (5V) PD12 21 GPIO (5V)

nal circuits.
PC11 48 GPIO (5V)
Note:

Pin Definitions
6.3 QFN48 Sub-GHz Device Pinout
Figure 6.3. QFN48 Sub-GHz Device Pinout
Table 6.3. QFN48 Sub-GHz Device Pinout

Pin Definitions

tive path. path.

path.

nal circuits.
PC11 48 GPIO (5V)
Note:

Pin Definitions
6.4 QFN32 2.4 GHz Device Pinout
Figure 6.4. QFN32 2.4 GHz Device Pinout
Table 6.4. QFN32 2.4 GHz Device Pinout

Pin Definitions

external reset source to this pin, it is re-
RESETn 8 RFVSS 9 Radio Ground
quired to only drive this pin low during

PAVSS 10 2G4RF_ION 11 negative path. This pin should be exter-
VSS
nally grounded.
2.4 GHz Differential RF input/output, Power Amplifier (PA) voltage regulator

2G4RF_IOP 12 PAVDD 13
positive path. VDD input
PA1 18 GPIO PB11 19 GPIO

nal circuits.
PC11 32 GPIO (5V)
Note:

Pin Definitions
6.5 QFN32 Sub-GHz Device Pinout
Figure 6.5. QFN32 Sub-GHz Device Pinout
Table 6.5. QFN32 Sub-GHz Device Pinout

Pin Definitions

tive path. path.

path.
PA1 18 GPIO PB11 19 GPIO

nal circuits.
PC11 32 GPIO (5V)
Note:

Pin Definitions
6.6 GPIO Functionality Table
A wide selection of alternate functionality is available for multiplexing to various pins. The following table shows the name of each GPIO
pin, followed by the functionality available on that pin. Refer to 6.7 Alternate Functionality Overview for a list of GPIO locations available
for each function.
Table 6.6. GPIO Functionality Table
GPIO Name Pin Alternate Functionality / Description
Analog Timers Communication Radio Other
US0_TX #0
TIM0_CC0 #0
US0_RX #31
TIM0_CC1 #31
US0_CLK #30
TIM0_CC2 #30
US0_CS #29
TIM0_CDTI0 #29
US0_CTS #28 FRC_DCLK #0 CMU_CLK1 #0
TIM0_CDTI1 #28
US0_RTS #27 FRC_DOUT #31 PRS_CH6 #0
TIM0_CDTI2 #27
US1_TX #0 FRC_DFRAME #30 PRS_CH7 #10
BUSDY TIM1_CC0 #0
US1_RX #31 MODEM_DCLK #0 PRS_CH8 #9
PA0 BUSCX TIM1_CC1 #31
US1_CLK #30 MODEM_DIN #31 PRS_CH9 #8
ADC0_EXTN TIM1_CC2 #30
US1_CS #29 MODEM_DOUT #30 ACMP0_O #0
TIM1_CC3 #29
US1_CTS #28 MODEM_ANT0 #29 ACMP1_O #0
WTIM0_CC0 #0
US1_RTS #27 MODEM_ANT1 #28 LES_CH8
LETIM0_OUT0 #0
LEU0_TX #0
LETIM0_OUT1 #31
LEU0_RX #31
PCNT0_S0IN #0
I2C0_SDA #0
PCNT0_S1IN #31
I2C0_SCL #31

Pin Definitions
US0_TX #1
TIM0_CC0 #1
US0_RX #0
TIM0_CC1 #0
US0_CLK #31
TIM0_CC2 #31
US0_CS #30
TIM0_CDTI0 #30
TIM0_CDTI1 #29
TIM0_CDTI2 #28
BUSCY US1_TX #1 FRC_DFRAME #31 PRS_CH7 #0
TIM1_CC0 #1
BUSDX US1_RX #0 MODEM_DCLK #1 PRS_CH8 #10
PA1 TIM1_CC1 #0
ADC0_EXTP US1_CLK #31 MODEM_DIN #0 PRS_CH9 #9
TIM1_CC2 #31
VDAC0_EXT US1_CS #30 MODEM_DOUT #31 ACMP0_O #1
TIM1_CC3 #30
WTIM0_CC0 #1
LETIM0_OUT0 #1
LEU0_TX #1
LETIM0_OUT1 #0
LEU0_RX #0
PCNT0_S0IN #1
I2C0_SDA #1
PCNT0_S1IN #0
I2C0_SCL #0
TIM0_CC0 #2 US0_TX #2
TIM0_CC1 #1 US0_RX #1
TIM0_CC2 #0 US0_CLK #0
TIM0_CDTI0 #31 US0_CS #31
TIM0_CDTI1 #30 US0_CTS #30 FRC_DCLK #2

PRS_CH6 #2
TIM0_CDTI2 #29 US0_RTS #29 FRC_DOUT #1
VDAC0_OUT1ALT / PRS_CH7 #1
TIM1_CC0 #2 US1_TX #2 FRC_DFRAME #0
OPA1_OUTALT #1 PRS_CH8 #0
TIM1_CC1 #1 US1_RX #1 MODEM_DCLK #2
PA2 BUSDY PRS_CH9 #10
TIM1_CC2 #0 US1_CLK #0 MODEM_DIN #1
BUSCX ACMP0_O #2
TIM1_CC3 #31 US1_CS #31 MODEM_DOUT #0
OPA0_P ACMP1_O #2
WTIM0_CC0 #2 US1_CTS #30 MODEM_ANT0 #31
LES_CH10
WTIM0_CC1 #0 US1_RTS #29 MODEM_ANT1 #30
LETIM0_OUT0 #2 LEU0_TX #2
LETIM0_OUT1 #1 LEU0_RX #1
PCNT0_S0IN #2 I2C0_SDA #2
PCNT0_S1IN #1 I2C0_SCL #1

Pin Definitions
TIM0_CC1 #2 US0_RX #2
TIM0_CC2 #1 US0_CLK #1
TIM0_CDTI1 #31 US0_CTS #31 FRC_DCLK #3 PRS_CH6 #3
TIM0_CDTI2 #30 US0_RTS #30 FRC_DOUT #2 PRS_CH7 #2
BUSCY TIM1_CC0 #3 US1_TX #3 FRC_DFRAME #1 PRS_CH8 #1
BUSDX TIM1_CC1 #2 US1_RX #2 MODEM_DCLK #3 PRS_CH9 #0

PA3
VDAC0_OUT0 / TIM1_CC2 #1 US1_CLK #1 MODEM_DIN #2 ACMP0_O #3
OPA0_OUT TIM1_CC3 #0 US1_CS #0 MODEM_DOUT #1 ACMP1_O #3
WTIM0_CC0 #3 US1_CTS #31 MODEM_ANT0 #0 LES_CH11
WTIM0_CC1 #1 US1_RTS #30 MODEM_ANT1 #31 GPIO_EM4WU8
LETIM0_OUT0 #3 LEU0_TX #3
PCNT0_S0IN #3 I2C0_SDA #3
TIM0_CC0 #4
US0_TX #4
TIM0_CC1 #3
US0_RX #3
TIM0_CC2 #2
US0_CLK #2
TIM0_CDTI0 #1
US0_CS #1
TIM0_CDTI1 #0
US0_CTS #0 FRC_DCLK #4
TIM0_CDTI2 #31 PRS_CH6 #4
US0_RTS #31 FRC_DOUT #3
VDAC0_OUT1ALT / TIM1_CC0 #4 PRS_CH7 #3
US1_TX #4 FRC_DFRAME #2
OPA1_OUTALT #2 TIM1_CC1 #3 PRS_CH8 #2
US1_RX #3 MODEM_DCLK #4
PA4 BUSDY TIM1_CC2 #2 PRS_CH9 #1
US1_CLK #2 MODEM_DIN #3
BUSCX TIM1_CC3 #1 ACMP0_O #4
US1_CS #1 MODEM_DOUT #2
OPA0_N WTIM0_CC0 #4 ACMP1_O #4
US1_CTS #0 MODEM_ANT0 #1
WTIM0_CC1 #2 LES_CH12
US1_RTS #31 MODEM_ANT1 #0
WTIM0_CC2 #0
LEU0_TX #4
LETIM0_OUT0 #4
LEU0_RX #3
LETIM0_OUT1 #3
I2C0_SDA #4
PCNT0_S0IN #4
I2C0_SCL #3
PCNT0_S1IN #3

Pin Definitions
US0_TX #5
US0_RX #4
US0_CLK #3
TIM0_CC0 #5
US0_CS #2
TIM0_CC1 #4
US0_CTS #1
TIM0_CC2 #3
US0_RTS #0
TIM0_CDTI0 #2
US1_TX #5
TIM0_CDTI1 #1 CMU_CLKI0 #4
US1_RX #4 FRC_DCLK #5
US1_CLK #3 FRC_DOUT #4
TIM1_CC0 #5 PRS_CH7 #4
VDAC0_OUT0ALT / US1_CS #2 FRC_DFRAME #3
OPA0_OUTALT #0 US1_CTS #1 MODEM_DCLK #5
PA5 TIM1_CC2 #3 PRS_CH9 #2
BUSCY US1_RTS #0 MODEM_DIN #4
TIM1_CC3 #2 ACMP0_O #5
BUSDX US2_TX #0 MODEM_DOUT #3
WTIM0_CC0 #5 ACMP1_O #5
US2_RX #31 MODEM_ANT0 #2
WTIM0_CC1 #3 LES_CH13
US2_CLK #30 MODEM_ANT1 #1
WTIM0_CC2 #1 ETM_TCLK #1
US2_CS #29
LETIM0_OUT0 #5
US2_CTS #28
LETIM0_OUT1 #4
US2_RTS #27
PCNT0_S0IN #5
LEU0_TX #5
PCNT0_S1IN #4
LEU0_RX #4
I2C0_SDA #5
I2C0_SCL #4

Pin Definitions
TIM0_CC0 #6
TIM0_CC1 #5
TIM0_CDTI0 #3 US0_RX #5
TIM0_CDTI1 #2 US0_CLK #4
TIM1_CC0 #6 US0_CTS #2 FRC_DCLK #6
TIM1_CC1 #5 US0_RTS #1 FRC_DOUT #5 PRS_CH6 #6
TIM1_CC2 #4 US1_TX #6 FRC_DFRAME #4 PRS_CH7 #5

BUSCY
TIM1_CC3 #3 US1_RX #5 MODEM_DCLK #6 PRS_CH8 #4
PB11 BUSDX
WTIM0_CC0 #15 US1_CLK #4 MODEM_DIN #5 PRS_CH9 #3
OPA2_P
WTIM0_CC1 #13 US1_CS #3 MODEM_DOUT #4 ACMP0_O #6
WTIM0_CC2 #11 US1_CTS #2 MODEM_ANT0 #3 ACMP1_O #6
WTIM0_CDTI0 #7 US1_RTS #1 MODEM_ANT1 #2
WTIM0_CDTI1 #5 LEU0_TX #6
WTIM0_CDTI2 #3 LEU0_RX #5
LETIM0_OUT0 #6 I2C0_SDA #6
LETIM0_OUT1 #5 I2C0_SCL #5
PCNT0_S0IN #6
PCNT0_S1IN #5

Pin Definitions
TIM0_CC0 #7
TIM0_CC1 #6

BUSDY
TIM1_CC3 #4 US1_RX #6 MODEM_DCLK #7 PRS_CH8 #5
PB12 BUSCX
WTIM0_CC0 #16 US1_CLK #5 MODEM_DIN #6 PRS_CH9 #4
OPA2_OUT
PCNT0_S0IN #7
PCNT0_S1IN #6

Pin Definitions
TIM0_CC0 #8
TIM0_CC1 #7
CMU_CLKI0 #0
PRS_CH6 #8
TIM1_CC1 #7 US0_RTS #3 FRC_DOUT #7
PRS_CH7 #7
BUSCY PRS_CH8 #6
PB13 BUSDX PRS_CH9 #5
WTIM0_CC0 #17 US1_CLK #6 MODEM_DIN #7
OPA2_N ACMP0_O #8
WTIM0_CC1 #15 US1_CS #5 MODEM_DOUT #6
ACMP1_O #8
DBG_SWO #1
GPIO_EM4WU9
PCNT0_S0IN #8
PCNT0_S1IN #7

Pin Definitions
TIM0_CC0 #9
TIM0_CC1 #8

CMU_CLK1 #1
PRS_CH6 #9
BUSDY PRS_CH7 #8
PB14 BUSCX PRS_CH8 #7
LFXTAL_N PRS_CH9 #6
ACMP0_O #9
ACMP1_O #9
PCNT0_S0IN #9
PCNT0_S1IN #8

Pin Definitions
TIM0_CC0 #10
TIM0_CC1 #9

CMU_CLK0 #1
PRS_CH6 #10
BUSCY PRS_CH7 #9
PB15 BUSDX PRS_CH8 #8
LFXTAL_P PRS_CH9 #7
ACMP0_O #10
ACMP1_O #10
PCNT0_S0IN #10
PCNT0_S1IN #9

Pin Definitions
TIM0_CC0 #11
TIM0_CC1 #10
CMU_CLK0 #2
CMU_CLKI0 #2
PRS_CH0 #8
PRS_CH9 #11
BUSBY TIM1_CC3 #8 US1_RX #10 MODEM_DCLK #11
PC6 PRS_CH10 #0
BUSAX WTIM0_CC0 #26 US1_CLK #9 MODEM_DIN #10
PRS_CH11 #5
ACMP0_O #11
ACMP1_O #11
ETM_TCLK #3
PCNT0_S0IN #11
PCNT0_S1IN #10

Pin Definitions
TIM0_CC0 #12
TIM0_CC1 #11
TIM0_CC2 #10 US0_TX #12
TIM1_CC0 #12 US0_CTS #8 FRC_DCLK #12 CMU_CLK1 #2
BUSAY TIM1_CC3 #9 US1_RX #11 MODEM_DCLK #12 PRS_CH10 #1

PC7
BUSBX WTIM0_CC0 #27 US1_CLK #10 MODEM_DIN #11 PRS_CH11 #0
WTIM0_CDTI0 #19 US1_RTS #7 MODEM_ANT1 #8 ETM_TD0
PCNT0_S0IN #12
PCNT0_S1IN #11

Pin Definitions
TIM0_CC0 #13
TIM0_CC1 #12
TIM0_CC2 #11 US0_TX #13

PRS_CH0 #10
PRS_CH9 #13
PRS_CH10 #2
BUSBY TIM1_CC3 #10 US1_RX #12 MODEM_DCLK #13
PC8 PRS_CH11 #1
BUSAX WTIM0_CC0 #28 US1_CLK #11 MODEM_DIN #12
ACMP0_O #13
ACMP1_O #13
ETM_TD1
PCNT0_S0IN #13
PCNT0_S1IN #12

Pin Definitions
TIM0_CC0 #14
TIM0_CC1 #13
TIM0_CC2 #12 US0_TX #14

PRS_CH0 #11
PRS_CH9 #14
PRS_CH10 #3
BUSAY TIM1_CC3 #11 US1_RX #13 MODEM_DCLK #14
PC9 PRS_CH11 #2
BUSBX WTIM0_CC0 #29 US1_CLK #12 MODEM_DIN #13
ACMP0_O #14
ACMP1_O #14
ETM_TD2
PCNT0_S0IN #14
PCNT0_S1IN #13

Pin Definitions
TIM0_CC0 #15
TIM0_CC1 #14 US0_TX #15
TIM0_CC2 #13 US0_RX #14
TIM0_CDTI2 #10 US0_CTS #11

CMU_CLK1 #3
TIM1_CC0 #15 US0_RTS #10 FRC_DCLK #15
PRS_CH0 #12
TIM1_CC1 #14 US1_TX #15 FRC_DOUT #14
PRS_CH9 #15
TIM1_CC2 #13 US1_RX #14 FRC_DFRAME #13
PRS_CH10 #4
BUSBY TIM1_CC3 #12 US1_CLK #13 MODEM_DCLK #15
PC10 PRS_CH11 #3
BUSAX WTIM0_CC0 #30 US1_CS #12 MODEM_DIN #14
ACMP0_O #15
WTIM0_CC1 #28 US1_CTS #11 MODEM_DOUT #13
ACMP1_O #15
WTIM0_CC2 #26 US1_RTS #10 MODEM_ANT0 #12
ETM_TD3
WTIM0_CDTI0 #22 LEU0_TX #15 MODEM_ANT1 #11
GPIO_EM4WU12
WTIM0_CDTI2 #18 I2C0_SDA #15
PCNT0_S1IN #14

Pin Definitions
TIM0_CC0 #16
TIM0_CC1 #15 US0_TX #16
TIM0_CC2 #14 US0_RX #15
TIM0_CDTI2 #11 US0_CTS #12
TIM1_CC0 #16 US0_RTS #11 FRC_DCLK #16 CMU_CLK0 #3
TIM1_CC1 #15 US1_TX #16 FRC_DOUT #15 PRS_CH0 #13
TIM1_CC2 #14 US1_RX #15 FRC_DFRAME #14 PRS_CH9 #16
BUSAY TIM1_CC3 #13 US1_CLK #14 MODEM_DCLK #16 PRS_CH10 #5

PC11
BUSBX WTIM0_CC0 #31 US1_CS #13 MODEM_DIN #15 PRS_CH11 #4
WTIM0_CC1 #29 US1_CTS #12 MODEM_DOUT #14 ACMP0_O #16
WTIM0_CC2 #27 US1_RTS #11 MODEM_ANT0 #13 ACMP1_O #16
WTIM0_CDTI0 #23 LEU0_TX #16 MODEM_ANT1 #12 DBG_SWO #3
WTIM0_CDTI2 #19 I2C0_SDA #16
PCNT0_S1IN #15

Pin Definitions
TIM0_CC0 #17
TIM0_CC1 #16
US0_TX #17
TIM0_CC2 #15
US0_RX #16
TIM0_CDTI0 #14
US0_CLK #15
TIM0_CDTI1 #13
US0_CS #14
TIM0_CDTI2 #12
TIM1_CC0 #17
TIM1_CC1 #16
TIM1_CC2 #15
BUSCY US1_RX #16 MODEM_DCLK #17 PRS_CH5 #6
PD9 TIM1_CC3 #14
BUSDX US1_CLK #15 MODEM_DIN #16 PRS_CH6 #11
WTIM0_CC1 #31
WTIM0_CC2 #29
WTIM0_CDTI0 #25
WTIM0_CDTI1 #23
LEU0_TX #17
WTIM0_CDTI2 #21
LEU0_RX #16
LETIM0_OUT0 #17
I2C0_SDA #17
LETIM0_OUT1 #16
I2C0_SCL #16
PCNT0_S0IN #17
PCNT0_S1IN #16

Pin Definitions
TIM0_CC0 #18
TIM0_CC1 #17 US0_TX #18
TIM0_CC2 #16 US0_RX #17
TIM0_CDTI2 #13 US0_CTS #14 FRC_DCLK #18 CMU_CLK1 #4
BUSDY TIM1_CC2 #16 US1_RX #17 MODEM_DCLK #18 PRS_CH5 #0

PD10
BUSCX TIM1_CC3 #15 US1_CLK #16 MODEM_DIN #17 PRS_CH6 #12
WTIM0_CDTI0 #26 US1_CTS #14 MODEM_ANT0 #15 ACMP1_O #18
WTIM0_CDTI1 #24 US1_RTS #13 MODEM_ANT1 #14 LES_CH2
PCNT0_S1IN #17

Pin Definitions
TIM0_CC0 #19
TIM0_CC1 #18 US0_TX #19
TIM0_CC2 #17 US0_RX #18
TIM0_CDTI2 #14 US0_CTS #15 FRC_DCLK #19

PRS_CH3 #10
PRS_CH4 #2
PRS_CH5 #1
BUSCY TIM1_CC2 #17 US1_RX #18 MODEM_DCLK #19
PD11 PRS_CH6 #13
BUSDX TIM1_CC3 #16 US1_CLK #17 MODEM_DIN #18
ACMP0_O #19
ACMP1_O #19
WTIM0_CDTI0 #27 US1_CTS #15 MODEM_ANT0 #16
LES_CH3
PCNT0_S1IN #18
TIM0_CC0 #20
US0_TX #20
TIM0_CC1 #19
US0_RX #19
TIM0_CC2 #18
US0_CLK #18
TIM0_CDTI0 #17
US0_CS #17
TIM0_CDTI1 #16
VDAC0_OUT1ALT / US1_TX #20 FRC_DFRAME #18
OPA1_OUTALT #0 US1_RX #19 MODEM_DCLK #20
PD12 TIM1_CC2 #18 PRS_CH6 #14
BUSDY US1_CLK #18 MODEM_DIN #19
BUSCX US1_CS #17 MODEM_DOUT #18
WTIM0_CDTI0 #28 ACMP1_O #20
WTIM0_CDTI1 #26 LES_CH4
WTIM0_CDTI2 #24
LEU0_TX #20
LETIM0_OUT0 #20
LEU0_RX #19
LETIM0_OUT1 #19
I2C0_SDA #20
PCNT0_S0IN #20
I2C0_SCL #19
PCNT0_S1IN #19

Pin Definitions
TIM0_CC0 #21
US0_TX #21
TIM0_CC1 #20
US0_RX #20
TIM0_CC2 #19
US0_CLK #19
TIM0_CDTI0 #18
US0_CS #18
TIM0_CDTI1 #17
PD13 BUSCY TIM1_CC2 #19 PRS_CH6 #15
BUSDX TIM1_CC3 #18 ACMP0_O #21
OPA1_P WTIM0_CDTI0 #29 ACMP1_O #21
WTIM0_CDTI2 #25
LEU0_TX #21
LETIM0_OUT0 #21
LEU0_RX #20
LETIM0_OUT1 #20
I2C0_SDA #21
PCNT0_S0IN #21
I2C0_SCL #20
PCNT0_S1IN #20
TIM0_CC0 #22
US0_TX #22
TIM0_CC1 #21
US0_RX #21
TIM0_CC2 #20
US0_CLK #20
TIM0_CDTI0 #19
US0_CS #19
TIM0_CDTI1 #18 CMU_CLK0 #5
BUSDY US1_TX #22 FRC_DFRAME #20
BUSCX US1_RX #21 MODEM_DCLK #22
PD14 TIM1_CC2 #20 PRS_CH6 #16
VDAC0_OUT1 / US1_CLK #20 MODEM_DIN #21
OPA1_OUT US1_CS #19 MODEM_DOUT #20
WTIM0_CDTI0 #30 ACMP1_O #22
WTIM0_CDTI2 #26 GPIO_EM4WU4
LEU0_TX #22
LETIM0_OUT0 #22
LEU0_RX #21
LETIM0_OUT1 #21
I2C0_SDA #22
PCNT0_S0IN #22
I2C0_SCL #21
PCNT0_S1IN #21

Pin Definitions
TIM0_CC0 #23
US0_TX #23
TIM0_CC1 #22
US0_RX #22
TIM0_CC2 #21
US0_CLK #21
TIM0_CDTI0 #20
US0_CS #20
TIM0_CDTI1 #19 CMU_CLK1 #5
PD15 BUSCY TIM1_CC2 #21 PRS_CH6 #17
BUSDX TIM1_CC3 #20 ACMP0_O #23
OPA1_N WTIM0_CDTI0 #31 ACMP1_O #23
WTIM0_CDTI2 #27 DBG_SWO #2
LEU0_TX #23
LETIM0_OUT0 #23
LEU0_RX #22
LETIM0_OUT1 #22
I2C0_SDA #23
PCNT0_S0IN #23
I2C0_SCL #22
PCNT0_S1IN #22

Pin Definitions
US0_TX #24
US0_RX #23
US0_CLK #22
TIM0_CC0 #24 US0_CS #21
TIM0_CC1 #23 US0_CTS #20
TIM0_CC2 #22 US0_RTS #19
TIM0_CDTI0 #21 US1_TX #24
TIM0_CDTI1 #20 US1_RX #23 FRC_DCLK #24 PRS_CH0 #0
TIM0_CDTI2 #19 US1_CLK #22 FRC_DOUT #23 PRS_CH1 #7
TIM1_CC0 #24 US1_CS #21 FRC_DFRAME #22 PRS_CH2 #6
BUSBY TIM1_CC1 #23 US1_CTS #20 MODEM_DCLK #24 PRS_CH3 #5

PF0
BUSAX TIM1_CC2 #22 US1_RTS #19 MODEM_DIN #23 ACMP0_O #24
TIM1_CC3 #21 US2_TX #14 MODEM_DOUT #22 ACMP1_O #24
WTIM0_CDTI1 #30 US2_RX #13 MODEM_ANT0 #21 DBG_SWCLKTCK
WTIM0_CDTI2 #28 US2_CLK #12 MODEM_ANT1 #20 BOOT_TX
LETIM0_OUT0 #24 US2_CS #11
LETIM0_OUT1 #23 US2_CTS #10
PCNT0_S0IN #24 US2_RTS #9
PCNT0_S1IN #23 LEU0_TX #24
LEU0_RX #23
I2C0_SDA #24
I2C0_SCL #23

Pin Definitions
US0_TX #25
US0_RX #24
US0_CLK #23
TIM0_CC0 #25 US0_CS #22
TIM0_CDTI0 #22 US1_TX #25
TIM0_CDTI1 #21 US1_RX #24 FRC_DCLK #25 PRS_CH0 #1
TIM1_CC0 #25 US1_CS #22 FRC_DFRAME #23 PRS_CH2 #7
BUSAY TIM1_CC1 #24 US1_CTS #21 MODEM_DCLK #25 PRS_CH3 #6

PF1
BUSBX TIM1_CC2 #23 US1_RTS #20 MODEM_DIN #24 ACMP0_O #25
WTIM0_CDTI1 #31 US2_RX #14 MODEM_ANT0 #22 DBG_SWDIOTMS
WTIM0_CDTI2 #29 US2_CLK #13 MODEM_ANT1 #21 BOOT_RX
LETIM0_OUT1 #24 US2_CTS #11
PCNT0_S1IN #24 LEU0_TX #25
LEU0_RX #24
I2C0_SDA #25
I2C0_SCL #24

Pin Definitions
US0_TX #26
TIM0_CC0 #26
US0_RX #25
TIM0_CC1 #25
US0_CLK #24
TIM0_CC2 #24
US0_CS #23 CMU_CLK0 #6
TIM0_CDTI0 #23
US0_CTS #22 FRC_DCLK #26 PRS_CH0 #2
TIM0_CDTI1 #22
TIM0_CDTI2 #21
TIM1_CC0 #26
BUSBY US1_RX #25 MODEM_DCLK #26 PRS_CH3 #7
PF2 TIM1_CC1 #25
BUSAX US1_CLK #24 MODEM_DIN #25 ACMP0_O #26
TIM1_CC2 #24
TIM1_CC3 #23
US1_CTS #22 MODEM_ANT0 #23 DBG_TDO
WTIM0_CDTI2 #30
US1_RTS #21 MODEM_ANT1 #22 DBG_SWO #0
LETIM0_OUT0 #26
LEU0_TX #26 GPIO_EM4WU0
LETIM0_OUT1 #25
LEU0_RX #25
PCNT0_S0IN #26
I2C0_SDA #26
PCNT0_S1IN #25
I2C0_SCL #25

Pin Definitions
US0_TX #27
US0_RX #26
US0_CLK #25
US0_CS #24
TIM0_CC0 #27
US0_CTS #23
TIM0_CC1 #26
US0_RTS #22
TIM0_CC2 #25
US1_TX #27
TIM0_CDTI0 #24
US1_RX #26 FRC_DCLK #27 CMU_CLK1 #6
TIM0_CDTI1 #23
US1_CLK #25 FRC_DOUT #26 PRS_CH0 #3
TIM0_CDTI2 #22
US1_CS #24 FRC_DFRAME #25 PRS_CH1 #2
TIM1_CC0 #27
BUSAY US1_CTS #23 MODEM_DCLK #27 PRS_CH2 #1
PF3 TIM1_CC1 #26
BUSBX US1_RTS #22 MODEM_DIN #26 PRS_CH3 #0
TIM1_CC2 #25
US2_TX #16 MODEM_DOUT #25 ACMP0_O #27
TIM1_CC3 #24
US2_RX #15 MODEM_ANT0 #24 ACMP1_O #27
WTIM0_CDTI2 #31
US2_CLK #14 MODEM_ANT1 #23 DBG_TDI
LETIM0_OUT0 #27
US2_CS #13
LETIM0_OUT1 #26
US2_CTS #12
PCNT0_S0IN #27
US2_RTS #11
PCNT0_S1IN #26
LEU0_TX #27
LEU0_RX #26
I2C0_SDA #27
I2C0_SCL #26

Pin Definitions
US0_TX #28
US0_RX #27
US0_CLK #26
US0_CS #25
TIM0_CC2 #26 US1_TX #28
TIM0_CDTI0 #25 US1_RX #27 FRC_DCLK #28
TIM0_CDTI2 #23 US1_CS #25 FRC_DFRAME #26 PRS_CH1 #3
BUSBY TIM1_CC0 #28 US1_CTS #24 MODEM_DCLK #28 PRS_CH2 #2

PF4
BUSAX TIM1_CC1 #27 US1_RTS #23 MODEM_DIN #27 PRS_CH3 #1
TIM1_CC3 #25 US2_RX #16 MODEM_ANT0 #25 ACMP1_O #28
LETIM0_OUT0 #28 US2_CLK #15 MODEM_ANT1 #24
PCNT0_S0IN #28 US2_CTS #13
LEU0_TX #28
LEU0_RX #27
I2C0_SDA #28
I2C0_SCL #27

Pin Definitions
US0_TX #29
US0_RX #28
US0_CLK #27
US0_CS #26
TIM0_CC2 #27 US1_TX #29
TIM0_CDTI2 #24 US1_CS #26 FRC_DFRAME #27 PRS_CH1 #4
BUSAY TIM1_CC0 #29 US1_CTS #25 MODEM_DCLK #29 PRS_CH2 #3

PF5
BUSBX TIM1_CC1 #28 US1_RTS #24 MODEM_DIN #28 PRS_CH3 #2
TIM1_CC3 #26 US2_RX #17 MODEM_ANT0 #26 ACMP1_O #29
LEU0_TX #29
LEU0_RX #28
I2C0_SDA #29
I2C0_SCL #28

Pin Definitions
US0_TX #30
US0_RX #29
US0_CLK #28
US0_CS #27
TIM0_CC2 #28 US1_TX #30

CMU_CLK1 #7
TIM0_CDTI1 #26 US1_CLK #28 FRC_DOUT #29
PRS_CH0 #6
TIM0_CDTI2 #25 US1_CS #27 FRC_DFRAME #28
PRS_CH1 #5
BUSBY TIM1_CC0 #30 US1_CTS #26 MODEM_DCLK #30
PF6 PRS_CH2 #4
BUSAX TIM1_CC1 #29 US1_RTS #25 MODEM_DIN #29
PRS_CH3 #3
TIM1_CC2 #28 US2_TX #19 MODEM_DOUT #28
ACMP0_O #30
TIM1_CC3 #27 US2_RX #18 MODEM_ANT0 #27
ACMP1_O #30
LEU0_TX #30
LEU0_RX #29
I2C0_SDA #30
I2C0_SCL #29

Pin Definitions
US0_TX #31
US0_RX #30
US0_CLK #29
US0_CS #28
TIM0_CC2 #29 US1_TX #31

CMU_CLKI0 #1
CMU_CLK0 #7
TIM0_CDTI1 #27 US1_CLK #29 FRC_DOUT #30
PRS_CH0 #7
TIM0_CDTI2 #26 US1_CS #28 FRC_DFRAME #29
PRS_CH1 #6
BUSAY TIM1_CC0 #31 US1_CTS #27 MODEM_DCLK #31
PF7 PRS_CH2 #5
BUSBX TIM1_CC1 #30 US1_RTS #26 MODEM_DIN #30
PRS_CH3 #4
TIM1_CC2 #29 US2_TX #20 MODEM_DOUT #29
ACMP0_O #31
TIM1_CC3 #28 US2_RX #19 MODEM_ANT0 #28
ACMP1_O #31
GPIO_EM4WU1
LEU0_TX #31
LEU0_RX #30
I2C0_SDA #31
I2C0_SCL #30

Pin Definitions
6.7 Alternate Functionality Overview
A wide selection of alternate functionality is available for multiplexing to various pins. The following table shows the name of the alter-
nate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings and the associated GPIO
pin. Refer to 6.6 GPIO Functionality Table for a list of functions available on each GPIO pin.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout
is shown in the column corresponding to LOCATION 0.
Table 6.7. Alternate Functionality Overview
Alternate LOCATION
Functionality 0-3 4-7 8 - 11 12 - 15 16 - 19 20 - 23 24 - 27 28 - 31 Description
0: PA0 4: PA4 8: PB13 12: PC7 16: PC11 20: PD12 24: PF0 28: PF4
1: PA1 5: PA5 9: PB14 13: PC8 17: PD9 21: PD13 25: PF1 29: PF5 Analog comparator
ACMP0_O ACMP0, digital out-
2: PA2 6: PB11 10: PB15 14: PC9 18: PD10 22: PD14 26: PF2 30: PF6 put.
3: PA3 7: PB12 11: PC6 15: PC10 19: PD11 23: PD15 27: PF3 31: PF7
1: PA1 5: PA5 9: PB14 13: PC8 17: PD9 21: PD13 25: PF1 29: PF5 Analog comparator
ACMP1_O ACMP1, digital out-
2: PA2 6: PB11 10: PB15 14: PC9 18: PD10 22: PD14 26: PF2 30: PF6 put.
0: PA0 Analog to digital

converter ADC0 ex-
ADC0_EXTN
ternal reference in-
put negative pin.
0: PA1 Analog to digital

converter ADC0 ex-
ADC0_EXTP
ternal reference in-
put positive pin.
BOOT_RX 0: PF1 Bootloader RX.
BOOT_TX 0: PF0 Bootloader TX.
0: PA1 4: PD9
1: PB15 5: PD14 Clock Management

CMU_CLK0 Unit, clock output
2: PC6 6: PF2 number 0.
3: PC11 7: PF7
0: PA0 4: PD10
1: PB14 5: PD15 Clock Management

CMU_CLK1 Unit, clock output
2: PC7 6: PF3 number 1.
3: PC10 7: PF6
0: PB13 4: PA5
Clock Management
CMU_CLKI0 1: PF7 Unit, clock input
number 0.
2: PC6

Pin Definitions
Alternate LOCATION
0: PF0 Debug-interface
Serial Wire clock
input and JTAG
Test Clock.
DBG_SWCLKTCK Note that this func-
tion is enabled to
the pin out of reset,
and has a built-in
pull down.
Serial Wire data in-
put / output and
JTAG Test Mode
Select.
DBG_SWDIOTMS
Note that this func-
tion is enabled to
the pin out of reset,
and has a built-in
pull up.
Serial Wire viewer
1: PB13 Output.
2: PD15 Note that this func-
DBG_SWO tion is not enabled
3: PC11
after reset, and
must be enabled by
software to be
used.
JTAG Test Data In.
Note that this func-

tion becomes avail-
DBG_TDI able after the first
valid JTAG com-
mand is received,
and has a built-in
pull up when JTAG
is active.
JTAG Test Data
Out.
DBG_TDO Note that this func-

tion becomes avail-
able after the first
valid JTAG com-
mand is received.
1: PA5 Embedded Trace

ETM_TCLK
3: PC6 Module ETM clock .
3: PC7 Embedded Trace

ETM_TD0 Module ETM data
0.

Pin Definitions
Alternate LOCATION

1.

2.

3.
1: PA1 5: PA5 9: PB14 13: PC8 17: PD9 21: PD13 25: PF1 29: PF5 Frame Controller,
FRC_DCLK
2: PA2 6: PB11 10: PB15 14: PC9 18: PD10 22: PD14 26: PF2 30: PF6 Data Sniffer Clock.
0: PA2 4: PB11 8: PB15 12: PC9 16: PD10 20: PD14 24: PF2 28: PF6
1: PA3 5: PB12 9: PC6 13: PC10 17: PD11 21: PD15 25: PF3 29: PF7 Frame Controller,
FRC_DFRAME Data Sniffer Frame
2: PA4 6: PB13 10: PC7 14: PC11 18: PD12 22: PF0 26: PF4 30: PA0 active
3: PA5 7: PB14 11: PC8 15: PD9 19: PD13 23: PF1 27: PF5 31: PA1
0: PA1 4: PA5 8: PB14 12: PC8 16: PD9 20: PD13 24: PF1 28: PF5
1: PA2 5: PB11 9: PB15 13: PC9 17: PD10 21: PD14 25: PF2 29: PF6 Frame Controller,
FRC_DOUT Data Sniffer Out-
2: PA3 6: PB12 10: PC6 14: PC10 18: PD11 22: PD15 26: PF3 30: PF7 put.
3: PA4 7: PB13 11: PC7 15: PC11 19: PD12 23: PF0 27: PF4 31: PA0
0: PF2 Pin can be used to

GPIO_EM4WU0 wake the system
up from EM4
0: PF7 Pin can be used to

up from EM4
0: PD14 Pin can be used to

up from EM4
0: PA3 Pin can be used to

up from EM4
0: PB13 Pin can be used to

up from EM4
0: PC10 Pin can be used to

up from EM4
1: PA2 5: PB11 9: PB15 13: PC9 17: PD10 21: PD14 25: PF2 29: PF6 I2C0 Serial Clock
I2C0_SCL
2: PA3 6: PB12 10: PC6 14: PC10 18: PD11 22: PD15 26: PF3 30: PF7 Line input / output.

Pin Definitions
Alternate LOCATION
1: PA1 5: PA5 9: PB14 13: PC8 17: PD9 21: PD13 25: PF1 29: PF5 I2C0 Serial Data in-
I2C0_SDA
2: PA2 6: PB11 10: PB15 14: PC9 18: PD10 22: PD14 26: PF2 30: PF6 put / output.
18: PC10 I2C1 Serial Clock

I2C1_SCL
19: PC11 Line input / output.
19: PC10 20: PC11 I2C1 Serial Data in-

I2C1_SDA
put / output.
0: PD9 LESENSE channel

LES_CH1
1.

LES_CH2
2.

LES_CH3
3.

LES_CH4
4.

LES_CH5
5.

LES_CH6
6.

LES_CH7
7.
0: PA0 LESENSE channel

LES_CH8
8.

LES_CH9
9.

LES_CH10
10.

LES_CH11
11.

LES_CH12
12.

LES_CH13
13.
1: PA1 5: PA5 9: PB14 13: PC8 17: PD9 21: PD13 25: PF1 29: PF5 Low Energy Timer
LETIM0_OUT0 LETIM0, output
2: PA2 6: PB11 10: PB15 14: PC9 18: PD10 22: PD14 26: PF2 30: PF6 channel 0.
1: PA2 5: PB11 9: PB15 13: PC9 17: PD10 21: PD14 25: PF2 29: PF6 Low Energy Timer
LETIM0_OUT1 LETIM0, output
2: PA3 6: PB12 10: PC6 14: PC10 18: PD11 22: PD15 26: PF3 30: PF7 channel 1.

Pin Definitions
Alternate LOCATION
1: PA2 5: PB11 9: PB15 13: PC9 17: PD10 21: PD14 25: PF2 29: PF6 LEUART0 Receive
LEU0_RX
2: PA3 6: PB12 10: PC6 14: PC10 18: PD11 22: PD15 26: PF3 30: PF7 input.
LEUART0 Transmit
1: PA1 5: PA5 9: PB14 13: PC8 17: PD9 21: PD13 25: PF1 29: PF5 output. Also used
LEU0_TX as receive input in
2: PA2 6: PB11 10: PB15 14: PC9 18: PD10 22: PD14 26: PF2 30: PF6 half duplex commu-
nication.
0: PB14 Low Frequency

Crystal (typically
32.768 kHz) nega-
LFXTAL_N tive pin. Also used
as an optional ex-
ternal clock input
pin.
0: PB15 Low Frequency

Crystal (typically
LFXTAL_P
32.768 kHz) posi-
tive pin.
MODEM antenna
1: PA4 5: PB13 9: PC7 13: PC11 17: PD12 21: PF0 25: PF4 29: PA0 control output 0,
MODEM_ANT0
2: PA5 6: PB14 10: PC8 14: PD9 18: PD13 22: PF1 26: PF5 30: PA1 used for antenna
diversity.
3: PB11 7: PB15 11: PC9 15: PD10 19: PD14 23: PF2 27: PF6 31: PA2
MODEM antenna
1: PA5 5: PB14 9: PC8 13: PD9 17: PD13 21: PF1 25: PF5 29: PA1 control output 1,
MODEM_ANT1
2: PB11 6: PB15 10: PC9 14: PD10 18: PD14 22: PF2 26: PF6 30: PA2 used for antenna
diversity.
3: PB12 7: PC6 11: PC10 15: PD11 19: PD15 23: PF3 27: PF7 31: PA3
1: PA1 5: PA5 9: PB14 13: PC8 17: PD9 21: PD13 25: PF1 29: PF5 MODEM data clock
MODEM_DCLK
2: PA2 6: PB11 10: PB15 14: PC9 18: PD10 22: PD14 26: PF2 30: PF6 out.
MODEM_DIN MODEM data in.
MODEM_DOUT MODEM data out.

Pin Definitions
Alternate LOCATION
0: PA4 Operational Amplifi-

OPA0_N er 0 external nega-
tive input.
0: PA2 Operational Amplifi-

OPA0_P er 0 external posi-
tive input.
0: PD15 Operational Amplifi-

tive input.
0: PD13 Operational Amplifi-

tive input.
0: PB13 Operational Amplifi-

tive input.

OPA2_OUT
er 2 output.

tive input.
1: PA1 5: PA5 9: PB14 13: PC8 17: PD9 21: PD13 25: PF1 29: PF5 Pulse Counter
PCNT0_S0IN PCNT0 input num-
2: PA2 6: PB11 10: PB15 14: PC9 18: PD10 22: PD14 26: PF2 30: PF6 ber 0.
1: PA2 5: PB11 9: PB15 13: PC9 17: PD10 21: PD14 25: PF2 29: PF6 Pulse Counter
PCNT0_S1IN PCNT0 input num-
2: PA3 6: PB12 10: PC6 14: PC10 18: PD11 22: PD15 26: PF3 30: PF7 ber 1.
0: PF0 4: PF4 8: PC6 12: PC10
1: PF1 5: PF5 9: PC7 13: PC11 Peripheral Reflex

PRS_CH0 System PRS, chan-
2: PF2 6: PF6 10: PC8 nel 0.
3: PF3 7: PF7 11: PC9
0: PF1 4: PF5
1: PF2 5: PF6 Peripheral Reflex

2: PF3 6: PF7 nel 1.
3: PF4 7: PF0
0: PF2 4: PF6
1: PF3 5: PF7 Peripheral Reflex

2: PF4 6: PF0 nel 2.
3: PF5 7: PF1

Pin Definitions
Alternate LOCATION
0: PF3 4: PF7 8: PD9 12: PD13
1: PF4 5: PF0 9: PD10 13: PD14 Peripheral Reflex

2: PF5 6: PF1 10: PD11 14: PD15 nel 3.
3: PF6 7: PF2 11: PD12
0: PD9 4: PD13
1: PD10 5: PD14 Peripheral Reflex

2: PD11 6: PD15 nel 4.
3: PD12
0: PD10 4: PD14
1: PD11 5: PD15 Peripheral Reflex

2: PD12 6: PD9 nel 5.
3: PD13
0: PA0 4: PA4 8: PB13 12: PD10 16: PD14
1: PA1 5: PA5 9: PB14 13: PD11 17: PD15 Peripheral Reflex

2: PA2 6: PB11 10: PB15 14: PD12 nel 6.
3: PA3 7: PB12 11: PD9 15: PD13
0: PA1 4: PA5 8: PB14
1: PA2 5: PB11 9: PB15 Peripheral Reflex

2: PA3 6: PB12 10: PA0 nel 7.
3: PA4 7: PB13
0: PA2 4: PB11 8: PB15
1: PA3 5: PB12 9: PA0 Peripheral Reflex

2: PA4 6: PB13 10: PA1 nel 8.
3: PA5 7: PB14
0: PA3 4: PB12 8: PA0 12: PC7 16: PC11
1: PA4 5: PB13 9: PA1 13: PC8 Peripheral Reflex

2: PA5 6: PB14 10: PA2 14: PC9 nel 9.
3: PB11 7: PB15 11: PC6 15: PC10
0: PC6 4: PC10
1: PC7 5: PC11 Peripheral Reflex

2: PC8 nel 10.
3: PC9
0: PC7 4: PC11
1: PC8 5: PC6 Peripheral Reflex

2: PC9 nel 11.
3: PC10

Pin Definitions
Alternate LOCATION
1: PA1 5: PA5 9: PB14 13: PC8 17: PD9 21: PD13 25: PF1 29: PF5 Timer 0 Capture
TIM0_CC0 Compare input /
2: PA2 6: PB11 10: PB15 14: PC9 18: PD10 22: PD14 26: PF2 30: PF6 output channel 0.
1: PA2 5: PB11 9: PB15 13: PC9 17: PD10 21: PD14 25: PF2 29: PF6 Timer 0 Capture
2: PA3 6: PB12 10: PC6 14: PC10 18: PD11 22: PD15 26: PF3 30: PF7 output channel 1.
1: PA3 5: PB12 9: PC6 13: PC10 17: PD11 21: PD15 25: PF3 29: PF7 Timer 0 Capture
2: PA4 6: PB13 10: PC7 14: PC11 18: PD12 22: PF0 26: PF4 30: PA0 output channel 2.
1: PA4 5: PB13 9: PC7 13: PC11 17: PD12 21: PF0 25: PF4 29: PA0 Timer 0 Compli-
TIM0_CDTI0 mentary Dead Time
2: PA5 6: PB14 10: PC8 14: PD9 18: PD13 22: PF1 26: PF5 30: PA1 Insertion channel 0.
1: PA5 5: PB14 9: PC8 13: PD9 17: PD13 21: PF1 25: PF5 29: PA1 Timer 0 Compli-
2: PB11 6: PB15 10: PC9 14: PD10 18: PD14 22: PF2 26: PF6 30: PA2 Insertion channel 1.
1: PB11 5: PB15 9: PC9 13: PD10 17: PD14 21: PF2 25: PF6 29: PA2 Timer 0 Compli-
2: PB12 6: PC6 10: PC10 14: PD11 18: PD15 22: PF3 26: PF7 30: PA3 Insertion channel 2.
3: PB13 7: PC7 11: PC11 15: PD12 19: PF0 23: PF4 27: PA0 31: PA4
1: PA1 5: PA5 9: PB14 13: PC8 17: PD9 21: PD13 25: PF1 29: PF5 Timer 1 Capture
2: PA2 6: PB11 10: PB15 14: PC9 18: PD10 22: PD14 26: PF2 30: PF6 output channel 0.
1: PA2 5: PB11 9: PB15 13: PC9 17: PD10 21: PD14 25: PF2 29: PF6 Timer 1 Capture
2: PA3 6: PB12 10: PC6 14: PC10 18: PD11 22: PD15 26: PF3 30: PF7 output channel 1.
1: PA3 5: PB12 9: PC6 13: PC10 17: PD11 21: PD15 25: PF3 29: PF7 Timer 1 Capture
2: PA4 6: PB13 10: PC7 14: PC11 18: PD12 22: PF0 26: PF4 30: PA0 output channel 2.

Pin Definitions
Alternate LOCATION
1: PA4 5: PB13 9: PC7 13: PC11 17: PD12 21: PF0 25: PF4 29: PA0 Timer 1 Capture
2: PA5 6: PB14 10: PC8 14: PD9 18: PD13 22: PF1 26: PF5 30: PA1 output channel 3.
1: PA3 5: PB12 9: PC6 13: PC10 17: PD11 21: PD15 25: PF3 29: PF7 USART0 clock in-
US0_CLK
2: PA4 6: PB13 10: PC7 14: PC11 18: PD12 22: PF0 26: PF4 30: PA0 put / output.
1: PA4 5: PB13 9: PC7 13: PC11 17: PD12 21: PF0 25: PF4 29: PA0 USART0 chip se-
US0_CS
2: PA5 6: PB14 10: PC8 14: PD9 18: PD13 22: PF1 26: PF5 30: PA1 lect input / output.
1: PA5 5: PB14 9: PC8 13: PD9 17: PD13 21: PF1 25: PF5 29: PA1 USART0 Clear To
US0_CTS Send hardware
2: PB11 6: PB15 10: PC9 14: PD10 18: PD14 22: PF2 26: PF6 30: PA2 flow control input.
1: PB11 5: PB15 9: PC9 13: PD10 17: PD14 21: PF2 25: PF6 29: PA2 USART0 Request
US0_RTS To Send hardware
2: PB12 6: PC6 10: PC10 14: PD11 18: PD15 22: PF3 26: PF7 30: PA3 flow control output.
0: PA1 4: PA5 8: PB14 12: PC8 16: PD9 20: PD13 24: PF1 28: PF5 USART0 Asynchro-
nous Receive.
US0_RX USART0 Synchro-
2: PA3 6: PB12 10: PC6 14: PC10 18: PD11 22: PD15 26: PF3 30: PF7 nous mode Master
Input / Slave Out-
put (MISO).
0: PA0 4: PA4 8: PB13 12: PC7 16: PC11 20: PD12 24: PF0 28: PF4 USART0 Asynchro-
nous Transmit. Al-
1: PA1 5: PA5 9: PB14 13: PC8 17: PD9 21: PD13 25: PF1 29: PF5 so used as receive
input in half duplex
US0_TX communication.
USART0 Synchro-
nous mode Master
Output / Slave In-
put (MOSI).
1: PA3 5: PB12 9: PC6 13: PC10 17: PD11 21: PD15 25: PF3 29: PF7 USART1 clock in-
US1_CLK
2: PA4 6: PB13 10: PC7 14: PC11 18: PD12 22: PF0 26: PF4 30: PA0 put / output.

Pin Definitions
Alternate LOCATION
1: PA4 5: PB13 9: PC7 13: PC11 17: PD12 21: PF0 25: PF4 29: PA0 USART1 chip se-
US1_CS
2: PA5 6: PB14 10: PC8 14: PD9 18: PD13 22: PF1 26: PF5 30: PA1 lect input / output.
1: PA5 5: PB14 9: PC8 13: PD9 17: PD13 21: PF1 25: PF5 29: PA1 USART1 Clear To
2: PB11 6: PB15 10: PC9 14: PD10 18: PD14 22: PF2 26: PF6 30: PA2 flow control input.
1: PB11 5: PB15 9: PC9 13: PD10 17: PD14 21: PF2 25: PF6 29: PA2 USART1 Request
2: PB12 6: PC6 10: PC10 14: PD11 18: PD15 22: PF3 26: PF7 30: PA3 flow control output.
0: PA1 4: PA5 8: PB14 12: PC8 16: PD9 20: PD13 24: PF1 28: PF5 USART1 Asynchro-
nous Receive.
2: PA3 6: PB12 10: PC6 14: PC10 18: PD11 22: PD15 26: PF3 30: PF7 nous mode Master
Input / Slave Out-
put (MISO).
0: PA0 4: PA4 8: PB13 12: PC7 16: PC11 20: PD12 24: PF0 28: PF4 USART1 Asynchro-
nous Transmit. Al-
1: PA1 5: PA5 9: PB14 13: PC8 17: PD9 21: PD13 25: PF1 29: PF5 so used as receive
USART1 Synchro-
nous mode Master
Output / Slave In-
put (MOSI).
12: PF0 16: PF5 30: PA5
13: PF1 17: PF6 USART2 clock in-

US2_CLK
14: PF3 18: PF7 put / output.
15: PF4
11: PF0 12: PF1 16: PF6 29: PA5
13: PF3 17: PF7 USART2 chip se-

US2_CS
14: PF4 lect input / output.
15: PF5
10: PF0 12: PF3 16: PF7 28: PA5
11: PF1 13: PF4 USART2 Clear To

14: PF5 flow control input.
15: PF6

Pin Definitions
Alternate LOCATION
9: PF0 12: PF4 27: PA5
10: PF1 13: PF5 USART2 Request

11: PF3 14: PF6 flow control output.
15: PF7
13: PF0 16: PF4 31: PA5 USART2 Asynchro-

nous Receive.
14: PF1 17: PF5
15: PF3 18: PF6 nous mode Master
Input / Slave Out-
19: PF7
put (MISO).
0: PA5 14: PF0 16: PF3 20: PF7 USART2 Asynchro-

nous Transmit. Al-
15: PF1 17: PF4 so used as receive
18: PF5
19: PF6
USART2 Synchro-
nous mode Master
Output / Slave In-
put (MOSI).
0: PA1 Digital to analog

converter VDAC0
VDAC0_EXT
external reference
input pin.
0: PA3 Digital to Analog

VDAC0_OUT0 / Converter DAC0
OPA0_OUT output channel
number 0.
0: PA5 Digital to Analog

VDAC0_OUT0AL
Converter DAC0 al-
T / OPA0_OUT- 1: PD13
ternative output for
ALT
2: PD15 channel 0.
0: PD14 Digital to Analog

VDAC0_OUT1 / Converter DAC0
OPA1_OUT output channel
number 1.
0: PD12 Digital to Analog

VDAC0_OUT1AL
Converter DAC0 al-
T / OPA1_OUT- 1: PA2
ternative output for
ALT
2: PA4 channel 1.
0: PA0 4: PA4 15: PB11 16: PB12 26: PC6 28: PC8
Wide timer 0 Cap-
1: PA1 5: PA5 17: PB13 27: PC7 29: PC9 ture Compare in-
WTIM0_CC0
2: PA2 18: PB14 30: PC10 put / output channel
0.
3: PA3 19: PB15 31: PC11

Pin Definitions
Alternate LOCATION
0: PA2 13: PB11 16: PB14 24: PC6 28: PC10

Wide timer 0 Cap-
1: PA3 14: PB12 17: PB15 25: PC7 29: PC11 ture Compare in-
WTIM0_CC1
2: PA4 15: PB13 26: PC8 31: PD9 put / output channel
1.
3: PA5 27: PC9
0: PA4 11: PB11 12: PB12 22: PC6 24: PC8 29: PD9
Wide timer 0 Cap-
1: PA5 13: PB13 23: PC7 25: PC9 30: PD10 ture Compare in-
WTIM0_CC2
14: PB14 26: PC10 31: PD11 put / output channel
2.
15: PB15 27: PC11
7: PB11 8: PB12 18: PC6 20: PC8 25: PD9 28: PD12
Wide timer 0 Com-
9: PB13 19: PC7 21: PC9 26: PD10 29: PD13 plimentary Dead
WTIM0_CDTI0
10: PB14 22: PC10 27: PD11 30: PD14 Time Insertion
channel 0.
11: PB15 23: PC11 31: PD15
5: PB11 8: PB14 16: PC6 20: PC10 24: PD10 28: PD14
Wide timer 0 Com-
6: PB12 9: PB15 17: PC7 21: PC11 25: PD11 29: PD15 plimentary Dead
WTIM0_CDTI1
7: PB13 18: PC8 23: PD9 26: PD12 30: PF0 Time Insertion
channel 1.
19: PC9 27: PD13 31: PF1
3: PB11 4: PB12 14: PC6 16: PC8 21: PD9 24: PD12 28: PF0
Wide timer 0 Com-
5: PB13 15: PC7 17: PC9 22: PD10 25: PD13 29: PF1 plimentary Dead
WTIM0_CDTI2
6: PB14 18: PC10 23: PD11 26: PD14 30: PF2 Time Insertion
channel 2.
7: PB15 19: PC11 27: PD15 31: PF3
Certain alternate function locations may have non-interference priority. These locations will take precedence over any other functions
selected on that pin (i.e. another alternate function enabled to the same pin inadvertently).
Some alternate functions may also have high speed priority on certain locations. These locations ensure the fastest possible paths to
the pins for timing-critical signals.
The following table lists the alternate functions and locations with special priority.
Table 6.8. Alternate Functionality Priority
Alternate Functionality Location Priority
CMU_CLKI0 1: PF7 High Speed

Pin Definitions
6.8 Analog Port (APORT) Client Maps
The Analog Port (APORT) is an infrastructure used to connect chip pins with on-chip analog clients such as analog comparators, ADCs,
DACs, etc. The APORT consists of a set of shared buses, switches, and control logic needed to configurably implement the signal rout-
ing. Figure 6.6 APORT Connection Diagram on page 173 shows the APORT routing for this device family (note that available features
may vary by part number). A complete description of APORT functionality can be found in the Reference Manual.
PC11
PC10
PC9
PC8
PC7
PC6
1X
DY
DX
CY
CX
2X
1X 3X POS
2X
4X
POS 3X NEXT1 PB15
PF0 4X NEXT0
NEXT1 ACMP1
PF1 NEXT0
1Y
PB14
ACMP0 2Y
1Y 3Y NEG PB13
PF2 2Y 4Y
NEG 3Y NEXT1
OPA2_N
PF3 4Y NEXT0
NEXT1
NEXT0
PF4 OUT2
1X
2X
PB12
PF5 POS 3X
4X
NEXT0
PF6 PB11
NEXT2
OPA2_P
PF7 ADC0 1Y
2Y
NEG 3Y 1X
4Y IDAC0 1Y
NEXT1
AX
BX
BY
EXTP
AY
EXTN OPA1_P
1X
VDAC0_OUT0ALT PA5
OPA0_P 2X POS
OUT0ALT
1X 3X OPA0_N
POS 2X 4X
3X PA4
4X OPA1_N VDAC0_OUT1ALT
1Y
OUT1ALT
OPA0_N 2Y NEG OUT0
1Y 3Y OPA1 PA3
NEG 2Y 4Y
OPA0 3Y OPA0_P
4Y OUT1
OUT1ALT PA2
OUT0 OUT1 VDAC0_OUT1ALT
OUT
OUT1ALT
OUT0ALT OUT2
OUT1 OUT3 ADC_EXTP
OUT OUT2 OUT4 PA1
OUT3 NEXT1
OUT4 ADC_EXTN
NEXT0 PA0
OPA2_P
1X OPA1_N
POS 2X PD15
3X VDAC0_OUT0ALT
4X OUT0ALT
OPA2_N
1Y
NEG 2Y
OPA2 3Y
4Y
OUT1ALT
OUT0ALT
OUT2
OPA1_P
OUT2ALT
OUT1
OUT1
OUT OUT2
OUT3
OUT4
NEXT2
1X
CEXT 1Y
3X
3Y
CSEN
2X
2Y
CEXT_SENSE
4X
VDAC0_OUT0ALT
VDAC0_OUT0ALT
4Y
nX, nY APORTnX, APORTnY
AX, BY, … BUSAX, BUSBY, ...

PD9
PD10
PD11
PD12
PD13
PD14
Figure 6.6. APORT Connection Diagram
Client maps for each analog circuit using the APORT are shown in the following tables. The maps are organized by bus, and show the
peripheral's port connection, the shared bus, and the connection from specific bus channel numbers to GPIO pins.

Pin Definitions
In general, enumerations for the pin selection field in an analog peripheral's register can be determined by finding the desired pin con-
nection in the table and then combining the value in the Port column (APORT__), and the channel identifier (CH__). For example, if pin
PF7 is available on port APORT2X as CH23, the register field enumeration to connect to PF7 would be APORT2XCH23. The shared
bus used by this connection is indicated in the Bus column.
Table 6.9. ACMP0 Bus and Pin Mapping

CH31
CH30
CH29
CH28
CH27
CH26
CH25
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
CH16
CH15
CH14
CH13
CH12
CH11
CH10
APORT4Y APORT4X APORT3Y APORT3X APORT2Y APORT2X APORT1Y APORT1X Port
CH9
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
Bus
BUSAX
PC10
PC8
PC6
PF6
PF4
PF2
PF0
BUSAY
PC11
PC9
PC7
PF7
PF5
PF3
PF1
BUSBX
PC11
PC9
PC7
PF7
PF5
PF3
PF1
BUSBY
PC10
PC8
PC6
PF6
PF4
PF2
PF0
BUSCX
PD14
PD12
PD10
PB14
PB12
PA4
PA2
PA0
BUSCY
PD15
PD13
PD11
PB15
PB13
PB11
PD9
PA5
PA3
PA1
BUSDX
PD15
PD13
PD11
PB15
PB13
PB11
PD9
PA5
PA3
PA1
BUSDY
PD14
PD12
PD10
PB14
PB12
PA4
PA2
PA0

BUSDY BUSDX BUSCY BUSCX BUSBY BUSBX BUSAY BUSAX Bus
PB15 PB15 CH31
PB14 PB14 CH30
PB13 PB13 CH29
PB12 PB12 CH28
PB11 PB11 CH27
CH26
CH25
CH24
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PF7 PF7 CH23
PF6 PF6 CH22
PF5 PF5 CH21
PF4 PF4 CH20
PF3 PF3 CH19
PF2 PF2 CH18
PF1 PF1 CH17
PF0 PF0 CH16
CH15
CH14
PA5 PA5 CH13
PA4 PA4 CH12
Table 6.10. ACMP1 Bus and Pin Mapping
PA3 PA3 PC11 PC11 CH11

PA1 PA1 PC9 PC9 CH9
PA0 PA0 PC8 PC8 CH8
PD15 PD15 PC7 PC7 CH7
PD13 PD13 CH5
PD12 PD12 CH4
PD11 PD11 CH3
PD10 PD10 CH2
PD9 PD9 CH1
CH0
Rev. 1.6 | 175

Pin Definitions
BUSDY BUSDX BUSCY BUSCX BUSBY BUSBX BUSAY BUSAX Bus
PB15 PB15 CH31
PB14 PB14 CH30
PB13 PB13 CH29
PB12 PB12 CH28
PB11 PB11 CH27
CH26
CH25
CH24

PF7 PF7 CH23
PF6 PF6 CH22
PF5 PF5 CH21
PF4 PF4 CH20
PF3 PF3 CH19
PF2 PF2 CH18
PF1 PF1 CH17
PF0 PF0 CH16
CH15
CH14
PA5 PA5 CH13
PA4 PA4 CH12
Table 6.11. ADC0 Bus and Pin Mapping

PA1 PA1 PC9 PC9 CH9
PA0 PA0 PC8 PC8 CH8
PD13 PD13 CH5
PD12 PD12 CH4
PD11 PD11 CH3
PD10 PD10 CH2
PD9 PD9 CH1
CH0
Rev. 1.6 | 176

Pin Definitions
APORT1Y APORT1X Port APORT4Y APORT4X APORT2Y APORT2X APORT3Y APORT3X APORT1Y APORT1X Port
CEXT
BUSCY BUSCX Bus BUSDY BUSDX BUSBY BUSBX BUSCY BUSCX BUSAY BUSAX Bus
PB15 CH31 PB15 PB15 CH31
CEXT_SENSE
CH26 CH26
CH25 CH25
CH24 CH24

CH23 PF7 PF7 CH23
CH22 PF6 PF6 CH22
CH21 PF5 PF5 CH21
CH20 PF4 PF4 CH20
CH19 PF3 PF3 CH19
CH18 PF2 PF2 CH18
CH17 PF1 PF1 CH17
CH16 PF0 PF0 CH16
CH15 CH15
CH14 CH14
PA5 CH13 PA5 PA5 CH13
PA4 CH12 PA4 PA4 CH12
Table 6.12. CSEN Bus and Pin Mapping
Table 6.13. IDAC0 Bus and Pin Mapping

PA3 CH11 PA3 PC11 PA3 PC11 CH11
PD15 CH7 PD15 PC7 PD15 PC7 CH7
PD14 CH6 PD14 PC6 PD14 PC6 CH6
PD13 CH5 PD13 PD13 CH5
PD9 CH1 PD9 PD9 CH1
CH0 CH0
Rev. 1.6 | 177

Pin Definitions
APORT4X APORT3X APORT2X APORT1X APORT4Y APORT3Y APORT2Y APORT1Y Port
BUSDX BUSCX BUSBX BUSAX BUSDY BUSCY BUSBY BUSAY Bus
OPA0_P
OPA0_N
PB15 PB15 CH31
PB14 PB14 CH30
PB13 PB13 CH29
PB12 PB12 CH28
PB11 PB11 CH27
CH26
CH25
CH24

PF7 PF7 CH23
PF6 PF6 CH22
PF5 PF5 CH21
PF4 PF4 CH20
PF3 PF3 CH19
PF2 PF2 CH18
PF1 PF1 CH17
PF0 PF0 CH16
CH15
CH14
PA5 PA5 CH13
PA4 PA4 CH12
PA3 PC11 PA3 PC11 CH11
Table 6.14. VDAC0 / OPA Bus and Pin Mapping
PA2 PC10 PA2 PC10 CH10

PA1 PC9 PA1 PC9 CH9
PA0 PC8 PA0 PC8 CH8
PD15 PC7 PD15 PC7 CH7
PD14 PC6 PD14 PC6 CH6
PD13 PD13 CH5
PD12 PD12 CH4
PD11 PD11 CH3
PD10 PD10 CH2
PD9 PD9 CH1
CH0
Rev. 1.6 | 178

Pin Definitions
APORT4Y APORT3Y APORT2Y APORT1Y APORT4X APORT3X APORT2X APORT1X APORT4Y APORT3Y APORT2Y APORT1Y Port
BUSDY BUSCY BUSBY BUSAY BUSDX BUSCX BUSBX BUSAX BUSDY BUSCY BUSBY BUSAY Bus
OPA1_P
OPA2_N
PB15 PB15 PB15 OPA1_N CH31
PB14 PB14 PB14 CH30
PB13 PB13 PB13 CH29
PB12 PB12 PB12 CH28
PB11 PB11 PB11 CH27
CH26
CH25
CH24

PF7 PF7 PF7 CH23
PF6 PF6 PF6 CH22
PF5 PF5 PF5 CH21
PF4 PF4 PF4 CH20
PF3 PF3 PF3 CH19
PF2 PF2 PF2 CH18
PF1 PF1 PF1 CH17
PF0 PF0 PF0 CH16
CH15
CH14
PA5 PA5 PA5 CH13
PA4 PA4 PA4 CH12
PA3 PC11 PA3 PC11 PA3 PC11 CH11
PD15 PC7 PD15 PC7 PD15 PC7 CH7
PD13 PD13 PD13 CH5
PD12 PD12 PD12 CH4
PD11 PD11 PD11 CH3
PD10 PD10 PD10 CH2
PD9 PD9 PD9 CH1
CH0
Rev. 1.6 | 179

Pin Definitions
APORT4Y APORT3Y APORT2Y APORT1Y APORT4X APORT3X APORT2X APORT1X APORT4Y APORT3Y APORT2Y APORT1Y Port
BUSDY BUSCY BUSBY BUSAY BUSDX BUSCX BUSBX BUSAX BUSDY BUSCY BUSBY BUSAY Bus
OPA2_P
PB15 PB15 PB15 OPA2_OUT CH31
PB14 PB14 PB14 CH30
PB13 PB13 PB13 CH29
PB12 PB12 PB12 CH28
PB11 PB11 PB11 CH27
VDAC0_OUT0 / OPA0_OUT
CH26
CH25
CH24

PF7 PF7 PF7 CH23
PF6 PF6 PF6 CH22
PF5 PF5 PF5 CH21
PF4 PF4 PF4 CH20
PF3 PF3 PF3 CH19
PF2 PF2 PF2 CH18
PF1 PF1 PF1 CH17
PF0 PF0 PF0 CH16
CH15
CH14
PA5 PA5 PA5 CH13
PA4 PA4 PA4 CH12
PD13 PD13 PD13 CH5
PD12 PD12 PD12 CH4
PD11 PD11 PD11 CH3
PD10 PD10 PD10 CH2
PD9 PD9 PD9 CH1
CH0
Rev. 1.6 | 180

Pin Definitions
APORT4Y APORT3Y APORT2Y APORT1Y Port
BUSDY BUSCY BUSBY BUSAY Bus
PB15 CH31
PB14 CH30
PB13 CH29
PB12 CH28
PB11 CH27
VDAC0_OUT1 / OPA1_OUT
CH26
CH25
CH24

PF7 CH23
PF6 CH22
PF5 CH21
PF4 CH20
PF3 CH19
PF2 CH18
PF1 CH17
PF0 CH16
CH15
CH14
PA5 CH13
PA4 CH12
PA3 PC11 CH11
PA2 PC10 CH10
PA1 PC9 CH9
PA0 PC8 CH8
PD15 PC7 CH7
PD14 PC6 CH6
PD13 CH5
PD12 CH4
PD11 CH3
PD10 CH2
PD9 CH1
CH0
Rev. 1.6 | 181

Pin Definitions
QFN48 Package Specifications
7. QFN48 Package Specifications
7.1 QFN48 Package Dimensions
Figure 7.1. QFN48 Package Drawing

Table 7.1. QFN48 Package Dimensions
Dimension Min Typ Max
A 0.80 0.85 0.90
A1 0.00 0.02 0.05
A3 0.20 REF
b 0.18 0.25 0.30
D 6.90 7.00 7.10
E 6.90 7.00 7.10
D2 5.15 5.30 5.45
E2 5.15 5.30 5.45
e 0.50 BSC
L 0.30 0.40 0.50
K 0.20 — —
R 0.09 — —
aaa 0.15
bbb 0.10
ccc 0.10
ddd 0.05
eee 0.08
fff 0.10
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220, Variation VKKD-4.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

7.2 QFN48 PCB Land Pattern
Figure 7.2. QFN48 PCB Land Pattern Drawing

Table 7.2. QFN48 PCB Land Pattern Dimensions
Dimension Typ
S1 6.01
S 6.01
L1 4.70
W1 4.70
e 0.50
W 0.26
L 0.86
Note:
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size can be 1:1 for all perimeter pads.
7. A 4x4 array of 0.75 mm square openings on a 1.00 mm pitch can be used for the center ground pad.
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

7.3 QFN48 Package Marking
EFR32
PPPPPPPPPP
YYWWTTTTTT
Figure 7.3. QFN48 Package Marking
The package marking consists of:

• PPPPPPPPP – The part number designation.
1. Family Code (B | M | F)
2. G (Gecko)
3. Series (1, 2,...)
4. Device Configuration (1, 2,...)
5. Performance Grade (P | B | V)
6. Feature Code (1, 2,...)
7. TRX Code (3 = TXRX | 2 = RX | 1 = TX)
8. Band (1 = Sub-GHz | 2 = 2.4 GHz | 3 = Dual-band)
9. Flash (J = 1024K | H = 512K | G = 256K | F = 128K | E = 64K | D = 32K)
10. Temperature Grade (G = -40 to 85 | I = -40 to 125)
• YY – The last 2 digits of the assembly year.
• WW – The 2-digit workweek when the device was assembled.
• TTTTTT – A trace or manufacturing code. The first letter is the device revision.

RQFN32 Package Specifications
8. RQFN32 Package Specifications
8.1 RQFN32 Package Dimensions
Figure 8.1. RQFN32 Package Drawing

Table 8.1. RQFN32 Package Dimensions
Dimension Min Typ Max
A 0.75 0.85 0.90
A1 — — 0.05
A2 0.70 0.75 0.80
A3 — 0.10 REF —
D/E 4.90 5.00 5.10
D2/E2 3.40 3.50 3.60
e 0.50 BSC
b 0.150 0.200 0.250
L 0.350 0.400 0.450
R 0.075 0.10 0.125
K 0.20 — —
aaa 0.150
bbb 0.100
ccc 0.100
ddd 0.050
eee 0.080
fff 0.100
Note:
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220, Variation VKKD-4.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

8.2 RQFN32 PCB Land Pattern
Figure 8.2. RQFN32 PCB Land Pattern Drawing

Table 8.2. RQFN32 PCB Land Pattern Dimensions
Dimension Typ
S1 4.01
S 4.01
L1 3.50
W1 3.50
e 0.50
W 0.26
L 0.86
Note:
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size can be 1:1 for all perimeter pads.
7. A 3x3 array of 0.85 mm square openings on a 1.00 mm pitch can be used for the center ground pad.
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

8.3 RQFN32 Package Marking
EFR32
PPPPPPPPPP
YYWWTTTTTT
Figure 8.3. RQFN32 Package Marking
The package marking consists of:

• PPPPPPPPP – The part number designation.
1. Family Code (B | M | F)
2. G (Gecko)
3. Series (1, 2,...)
4. Device Configuration (1, 2,...)
5. Performance Grade (P | B | V)
6. Feature Code (1, 2,...)
7. TRX Code (3 = TXRX | 2 = RX | 1 = TX)
8. Band (1 = Sub-GHz | 2 = 2.4 GHz | 3 = Dual-band)
9. Flash (J = 1024K | H = 512K | G = 256K | F = 128K | E = 64K | D = 32K)
10. Temperature Grade (G = -40 to 85 | I = -40 to 125)
• YY – The last 2 digits of the assembly year.
• WW – The 2-digit workweek when the device was assembled.
• TTTTTT – A trace or manufacturing code. The first letter is the device revision.

Revision History
9. Revision History
Revision 1.6
September, 2020
• Updated External PA supply connection conditions for SPURHA.RM_ETSI and SPUROOB_ETSI in section 4.1.10.3 Sub-GHz RF Trans-
mitter characteristics for 868 MHz Band.
• In 4.1.2.1 General Operating Conditions for fCORE :
• Added conditions for all usable wait state settings
• Corrected maximum specification from 20 MHz to 7 MHz for test condition VSCALE0, MODE = WS0
Revision 1.5
October 2019
• In the front page block diagram, updated the lowest energy mode for LETIMER.
• Updated 3.6.4 Low Energy Timer (LETIMER) lowest energy mode.
• In 5.2 RF Matching Networks, corrected document references for component values and added document reference to IPD solu-
tions.
• Updated 4.1.1 Absolute Maximum Ratings absolute voltage on sub-GHz and 2.4 GHz RF pins.
• In 4.1.10.1 Sub-GHz RF Transmitter characteristics for 915 MHz Band:
• Corrected FCC reference for non-restricted bands in:
• SPURHARM_FCC_20
• SPUROOB_FCC_20
• SPURHARM_FCC_14
• SPUROOB_FCC_14
• Updated typical and maximum specifications for restricted bands (30-88 MHz) in:
• SPUROOB_FCC_20
• SPUROOB_FCC_14
• Added footnote to PSD.
• In 4.1.10.2 Sub-GHz RF Receiver Characteristics for 915 MHz Band, updated typical and maximum specifications for SPURRX_ARIB,
930-1000 MHz, RBW=100 kHz.
Revision 1.4
May 2019
• Added Revision D and removed Revision C OPNs in Table 2.1 Ordering Information on page 3.
• Renamed 3.8.1 General Purpose Cyclic Redundancy Check (GPCRC) section.
• Added footnotes in Table 4.44 General-Purpose I/O (GPIO) on page 86.
• Changed the test condition in Table 4.48 Digital to Analog Converter (VDAC) on page 94.
• Edited the description of the Decouple pin and RESETn pin in Table 6.1 QFN48 2.4 GHz and Sub-GHz Device Pinout on page 123,
Table 6.2 QFN48 2.4 GHz Device Pinout on page 125, Table 6.3 QFN48 Sub-GHz Device Pinout on page 127, Table 6.4 QFN32
2.4 GHz Device Pinout on page 129 and Table 6.5 QFN32 Sub-GHz Device Pinout on page 131.
• In 7.3 QFN48 Package Marking, updated feature code.
• In 8.3 RQFN32 Package Marking, updated feature code.
• Corrected minor typos throughout the document.

Revision History
Revision 1.3
November 2018
• Updated the current consumed in receive mode under 802.15.4 receiving frame test condition at 2.4 GHz frequency with and without
radio pre-scaling - Table 4.8 Current Consumption Using Radio 3.3 V with DC-DC on page 34.
• “PAVDD” references in Sub-GHz specification tables clarified to refer to “External PA Supply”. The PAVDD pin is for the 2.4 GHz
radio.
• Table 6.6 GPIO Functionality Table on page 133 re-sorted to list pins alphabetically by GPIO Name column.
• Reworded or removed mentions of “modules” in reference to device peripherals in system overview.
• Ordered table footnotes in the order in which their references appear in the table.
• Table 4.25 Sub-GHz RF Receiver Characteristics for 915 MHz Band on page 59 - Clarified that 400 kbps reference signal is 4GFSK.
• Corrected the reference signal value in Table 4.19 RF Receiver Characteristics for 2GFSK in the 2.4GHz Band, 500 kbps Data Rate
on page 48 and Table 4.21 RF Receiver Characteristics for 2GFSK in the 2.4GHz Band, 125 kbps Data Rate on page 50.
• Corrected the Error vector magnitude parameter in Table 4.22 RF Transmitter Characteristics for 802.15.4 DSSS-OQPSK in the 2.4
GHz Band on page 51.
• Corrected minor typos throughout the document.
Revision 1.2
March 2018
• Added new orderable part numbers in QFN32 packaging.

• Figure 6.6 APORT Connection Diagram on page 173: Corrected OPA output connections to route through "Y" buses.
Revision 1.1
January 2017
• Updated 3.12 Memory Map with latest formatting and low-energy peripherals.
• 4.1.1 Absolute Maximum Ratings:
• Changed "Non-5V tolerant GPIO pins" to "Standard GPIO pins".
• Added footnotes to clarify VDIGPIN specification for 5V tolerant GPIO.
• Table 4.2 General Operating Conditions on page 24: Added footnote for additional information on peak current during voltage scal-
ing operations.
• 4.1.9.4 RF Receiver Characteristics for 2GFSK in the 2.4GHz Band, 1 Mbps Data Rate: BLOCKOOB specifications changed to show
Min values instead of Typ, and footnote added.
• 4.1.9.6 RF Receiver Characteristics for 2GFSK in the 2.4GHz Band, 2 Mbps Data Rate: BLOCKOOB specifications removed (not part
of BLE 2 Mbps specification).
• 4.1.9.7 RF Transmitter Characteristics for 2GFSK in the 2.4GHz Band, 500 kbps Data Rate and 4.1.9.9 RF Transmitter Characteris-
tics for 2GFSK in the 2.4GHz Band, 125 kbps Data Rate: PSDLIMIT changed to specify maximum instead of typ, with footnote added
for FCC output power limit.
• 4.1.9.12 RF Receiver Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band : Footnote added to BLOCK80211G specifica-
tion to clarify blocker signal definition.
• 4.1.10.2 Sub-GHz RF Receiver Characteristics for 915 MHz Band: Added O-QPSK DSSS phy specifications.
• 4.1.18 Digital to Analog Converter (VDAC): Widened VGAIN Gain error limits.
• 4.1.25 USART SPI:
• SPI Slave Timing: Corrected tSU_MO, tH_MO and tSCLK_MIN limits.
• Updated remainder of specifications to match formatting and common specs in all EFR32xG1x product families.
• 4.2.3 2.4 GHz Radio:
• Extended temperature plots to 125 degrees C.
• Updated RX sensitivity plots with latest phy characterization data.
• Added Figure 6.6 APORT Connection Diagram on page 173.

Revision History
Revision 1.0
2017-Aug-02
• Updated spcification tables with latest characterization values and production test min/max limits.
• Added high-temperature OPNs and associated specifications.
• Added performance specifications and supported radio modulations/protocols to Feature List.
• Clarified / corrected energy mode mentions in RTCC and Opamp sections of the System Overview.
• Sub-GHz RF Transmitter characteristics for 868 MHz Band Electrical Specifications Table:
• POUTVAR_V_NODCDC specification symbol corrected to POUTVAR_V
• POUTVAR_F_NODCDC specification symbol corrected to POUTVAR_F
• Sub-GHz RF Transmitter characteristice for 433 MHz Band Electrical Specifications Table: POTMIN specification symbol correc-
ted to POUTMIN
• Analog to Digital Converter (ADC) Electrical Specifications Table: Added footnote for clarification of input voltage limits.
• Typical Sub-GHz Impedance-matching network circuits Figure: Corrected split between two examples from 450 MHz to 500
MHz.
• RF Transmitter General Characteristics for 2.4 GHz Band Electrical Specifications Table:
• Test Conditions changed from "19.5 dBm" to "19 dBm" and from "10.5 dBm" to "10 dBm"
• RF Receiver Characteristics for Bluetooth Low Energy in the 2.4GHz Band, 1 Mbps Data Rate Electrical Specifications Table:
• Sensitivity (SENS) for Reference Signal changed from "-95.8 dBm" to "-94.8 dBm"
Revision 0.5
2017-Apr-25
• Added RFSENSE section to System Overview.
• Updated specification tables with latest characterization results.
• Split 2.4 GHz 2GFSK tables into separate tables for 1 Mbps, 2 Mbps, 500kbps, and 125kbps data rates.
• Added typical performance graphs.
• Condensed pin function tables with new formatting.
• Added APORT Connection Diagram.
• Corrected package marking flash size designator.
• Removed OPNs for QFN32 package options.
Revision 0.1
2016-Nov-15
Initial release.

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Disclaimer
Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or
intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and “Typical”
parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes
without further notice to the product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information.
Without prior notification, Silicon Labs may update product firmware during the manufacturing process for security or reliability reasons. Such changes will not alter the specifications or
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Efr32fg13 Datasheet

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EFR32FG13 Flex Gecko Proprietary

Protocol SoC Family Data Sheet

The Flex Gecko proprietary protocol family of SoCs is part of the

Core / Memory Clock Management Energy Management Other

H-F Crystal H-F Voltage CRYPTO

Peripheral Reflex System

LNA USART Timer/Counter Protocol Timer

Lowest power mode with peripheral operational:

silabs.com | Building a more connected world. Rev. 1.6

The EFR32FG13 highlighted features are listed below.

silabs.com | Building a more connected world. Rev. 1.6 | 2

Table 2.1. Ordering Information

EFR32FG13P233F512GM48-D Proprietary 2.4 GHz @ 19 dBm 512 64 28 QFN48 -40 to +85°C

EFR32FG13P232F512GM48-D Proprietary 2.4 GHz @ 19 dBm 512 64 31 QFN48 -40 to +85°C

EFR32FG13P232F512GM32-D Proprietary 2.4 GHz @ 19 dBm 512 64 16 QFN32 -40 to +85°C

EFR32FG13P231F512GM48-D Proprietary Sub-GHz @ 20 dBm 512 64 32 QFN48 -40 to +85°C

EFR32FG13P231F512IM48-D Proprietary Sub-GHz @ 20 dBm 512 64 32 QFN48 -40 to +125°C

EFR32FG13P231F512GM32-D Proprietary Sub-GHz @ 20 dBm 512 64 16 QFN32 -40 to +85°C

EFR32FG13P231F512IM32-D Proprietary Sub-GHz @ 20 dBm 512 64 16 QFN32 -40 to +125°C

EFR32 X G 1 3 P 132 F 512 G M 48 – A R

Tape and Reel (Optional)

Figure 2.1. Ordering Code Key

silabs.com | Building a more connected world. Rev. 1.6 | 3

silabs.com | Building a more connected world. Rev. 1.6 | 5

6. Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

7. QFN48 Package Specifications. . . . . . . . . . . . . . . . . . . . . . . . 182

8. RQFN32 Package Specifications . . . . . . . . . . . . . . . . . . . . . . . 187

9. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192

silabs.com | Building a more connected world. Rev. 1.6 | 6

Radio Transceiver Port I/O Configuration IOVDD

Energy Management Floating Point Unit Analog Peripherals

Figure 3.1. Detailed EFR32FG13 Block Diagram

silabs.com | Building a more connected world. Rev. 1.6 | 7

3.2.1 Antenna Interface

3.2.2 Fractional-N Frequency Synthesizer

3.2.3 Receiver Architecture

3.2.4 Transmitter Architecture

silabs.com | Building a more connected world. Rev. 1.6 | 8

3.2.5 Wake on Radio

3.2.7 Flexible Frame Handling

3.2.8 Packet and State Trace

3.2.9 Data Buffering

silabs.com | Building a more connected world. Rev. 1.6 | 9

3.2.10 Radio Controller (RAC)

3.2.11 Random Number Generator

silabs.com | Building a more connected world. Rev. 1.6 | 10

3.3.1 Energy Management Unit (EMU)

3.3.2 DC-DC Converter

3.3.3 Power Domains

Table 3.1. Peripheral Power Subdomains

Peripheral Power Domain 1 Peripheral Power Domain 2

3.4 General Purpose Input/Output (GPIO)

silabs.com | Building a more connected world. Rev. 1.6 | 11

3.5.1 Clock Management Unit (CMU)

3.5.2 Internal and External Oscillators

3.6 Counters/Timers and PWM

3.6.1 Timer/Counter (TIMER)

3.6.2 Wide Timer/Counter (WTIMER)

3.6.3 Real Time Counter and Calendar (RTCC)