ICT 1110 (2022/23)

Computer Systems & Architecture

Lecture 16: MIPS Instruction Set
Architecture I
Lighton Phiri <[email protected]>
Department of Library & Information Science
University of Zambia
https://bit.ly/3uJBZRc
 Lecture Outline

● Introduction
● MIPS Architecture
● QtSpim R3000 Processor Simulator
● QtSpim: Installation and Configuration
● QtSpim: Interface
● QtSpim: Loading Assembly Programs
● QtSpim: Executing Assembly Programs
● QtSpim: Interpreting Program Output
● Elements of MIPS Assembly Programs

September 20, 2023 ICT 1110 (2022/23) L16 - 2

 Computers Take in Input, Process it and
Produce Output (1/2)

https://www.gsmarena.com/lenovo_tab_7-8941.php

● A Computer is an electronic device that

accepts input, processes the input, and
presents the change input (processed
input) as output
Mwabu Tablet: Lenovo TB-7304I

September 20, 2023 ICT 1110 (2022/23) L16 - 3

 Computers Take in Input, Process it and
Produce Output (2/2)
● A Computer is an electronic device that accepts input,
processes the input, and presents the changed input
(processed input) as output.
○ Input initialises interactivity with computer system.
○ Output provides mechanisms to access computer system output.
○ The CPU performs computations.
○ Memory provides a means for storing processed data.

Input/ Central
Memory
Output Processing Unit

September 20, 2023 ICT 1110 (2022/23) L16 - 4

 Abstraction is Crucial to Understanding
Computing (1/6)
Central
Processing Unit

Input/Output
Control Unit

ALU

Registers
Abstraction

Memory Unit
[Instructions]
[Data]

September 20, 2023 ICT 1110 (2022/23) L16 - 5

 Abstraction is Crucial to Understanding
Computing (2/6)
CPU
Registers

Cache

Main Memory
RAM

ROM

Virtual

Secondary
Memory
September 20, 2023 ICT 1110 (2022/23) L16 - 6
 Abstraction is Crucial to Understanding
Computing (3/6)

RGB(0, 128, 255)

#0080FF
00000000 10000000 11111111

September 20, 2023 ICT 1110 (2022/23) L16 - 7

 Abstraction is Crucial to Understanding
Computing (4/6)
FETCH
Instruction

Central
Processing Unit
Input/Output

DECODE
Control Unit Instruction
ALU

Registers
EXECUTE
Instruction

Memory Unit
STORE
Instruction

September 20, 2023 ICT 1110 (2022/23) L16 - 8

 Abstraction is Crucial to Understanding
Computing (4/6)
FETCH
● To understand Instruction Application
how machine
instructions Compiler OS
DECODE
(so-called 1s and Instruction Von Neumann Model
0s) are executed, ISA
we focus on ISA
EXECUTE CPU Design
○ Instructions Instruction
expressed/abstr
Circuit Design
acted a level
higher than STORE
Chip Design
Instruction
machine code
September 20, 2023 ICT 1110 (2022/23) L16 - 9
 Abstraction is Crucial to Understanding
Computing (5/6)
● Software is generally created using
high-level programming languages
○ Language translators are used to convert
between different representations—e.g.
HLL to Machine Code
● To understand how machine instructions
(so-called 1s and 0s) are executed, we
focus on ISA
○ Instructions expressed/abstracted a level
higher than machine code
Patterson A. D & Hennessy J. L.
September 20, 2023 ICT 1110 (2022/23) L16 - 10
 Abstraction is Crucial to Understanding
Computing (6/6)
00100000000010000000011111010000001000000000100100000000
00010010001000000000101000000111111001010000000100001001
010110000010000000000001010010110110000000100010

addi $t0 $zero 0x07D0

addi $t1 $zero 0x0012
It is difficult/tedious to work
addi $t2 $zero 0x07E5 with machine code
add $t3 $t0 $t1
sub $t4 $t2 $t3

September 20, 2023 ICT 1110 (2022/23) L16 - 11

 Abstraction is Crucial to Understanding
Computing (6/6)
00100000000010000000011111010000001000000000100100000000
00010010001000000000101000000111111001010000000100001001
010110000010000000000001010010110110000000100010

addi $t0 $zero 0x07D0

addi $t1 $zero 0x0012 Working with a layer of
abstraction immediately above
addi $t2 $zero 0x07E5 the machine layer is much
add $t3 $t0 $t1 easier and/or convenient

sub $t4 $t2 $t3

September 20, 2023 ICT 1110 (2022/23) L16 - 12

 Abstraction is Crucial to Understanding
Computing (6/6)
00100000000010000000011111010000001000000000100100000000
00010010001000000000101000000111111001010000000100001001
010110000010000000000001010010110110000000100010

addi $t0 $zero 2000

addi $t1 $zero 18 Working with a layer of
abstraction immediately above
addi $t2 $zero 2021 the machine layer is much
add $t3 $t0 $t1 easier and/or convenient

sub $t4 $t2 $t3

September 20, 2023 ICT 1110 (2022/23) L16 - 13

 Abstraction is Crucial to Understanding
Computing (6/6)
00100000000010000000011111010000001000000000100100000000
00010010001000000000101000000111111001010000000100001001
010110000010000000000001010010110110000000100010

addi $t0 $zero 2000

addi $t1 $zero 18 Each instruction is a word long
1 word = 32 bits
addi $t2 $zero 2021 1 word = 4 bytes
add $t3 $t0 $t1 :

sub $t4 $t2 $t3

September 20, 2023 ICT 1110 (2022/23) L16 - 14

 Abstraction is Crucial to Understanding
Computing (6/6)
00100000000010000000011111010000001000000000100100000000
00010010001000000000101000000111111001010000000100001001
010110000010000000000001010010110110000000100010

addi $t0 $zero 2000

addi $t1 $zero 18 Each instruction is a word long
1 word = 32 bits
addi $t2 $zero 2021 1 word = 4 bytes
add $t3 $t0 $t1 :

sub $t4 $t2 $t3

September 20, 2023 ICT 1110 (2022/23) L16 - 15

 Introduction (6/6)

00100000000010000000011111010000001000000000100100000000
00010010001000000000101000000111111001010000000100001001
010110000010000000000001010010110110000000100010

addi $t0 $zero 2000

addi $t1 $zero 18 Each instruction is a word long
1 word = 32 bits
addi $t2 $zero 2021 1 word = 4 bytes
add $t3 $t0 $t1 :

sub $t4 $t2 $t3

September 20, 2023 ICT 1110 (2022/23) L16 - 16

 Introduction (6/6)

00100000000010000000011111010000001000000000100100000000
00010010001000000000101000000111111001010000000100001001
010110000010000000000001010010110110000000100010

addi $t0 $zero 2000

addi $t1 $zero 18 Each instruction is a word long
1 word = 32 bits
addi $t2 $zero 2021 1 word = 4 bytes
add $t3 $t0 $t1 :

sub $t4 $t2 $t3

September 20, 2023 ICT 1110 (2022/23) L16 - 17

 Introduction (6/6)

00100000000010000000011111010000001000000000100100000000
00010010001000000000101000000111111001010000000100001001
010110000010000000000001010010110110000000100010

addi $t0 $zero 2000

addi $t1 $zero 18 Each instruction is a word long
1 word = 32 bits
addi $t2 $zero 2021 1 word = 4 bytes
add $t3 $t0 $t1 :

sub $t4 $t2 $t3

September 20, 2023 ICT 1110 (2022/23) L16 - 18

 About MIPS Instruction Set Architecture

● MIPS instruction set will

be used.
● You want to make sure
you understand what is
going on
○ Go through examples
○ Work through all
practicals
○ As with most things It
gets easier with
practice
QtSpim 9.1.20
September 20, 2023 ICT 1110 (2022/23) L16 - 19
 MIPS Architecture (1/7)

● MIPS is a RISC architecture.

○ Microprocessor architecture that uses a small set of highly
optimised instructions.
○ Homework: Compare RISC and CISC.
● MIPS is a register-based architecture.
○ CPU uses registers to perform computations.
● Implements classic Fetch-Decode-Execute instruction cycle.
○ When the CPU execute an instruction, the PC is incremented and
the next address in memory is fetch [...] and the cycle begins
again.

September 20, 2023 ICT 1110 (2022/23) L16 - 20

 MIPS Architecture (2/7)

● MIPS basic data types include.

○ Character: building block for strings—sequence of characters.
○ Integer: whole numbers and corresponding negative values.
○ Floating-point: Whole numbers with floating decimal points.
● MIPS supports data storage in byte, word and halfword sizes.
○ A byte is an 8-bit integer.
○ Character data is typically a byte.
○ Floating are either a word (32-bit) or double word (64-bit).

September 20, 2023 ICT 1110 (2022/23) L16 - 21

 MIPS Architecture (3/7)

● MIPS memory appears as series of Data Size

bytes. Byte 8-bit integer
○ Memory is byte addressable.
○ A word requires four bytes. Halfword 16-bit integer
● MIPS is both little-endian and
Word 32-bit integer
big-endian
○ Little-endian: Least Significant Bit Float 32-bit floating
(LSB) is stored in lowest memory point
address. Double 64-bit floating
○ Big-endian: Most Significant Bit point
(MSB) is in lowest memory address.
September 20, 2023 ICT 1110 (2022/23) L16 - 22
 MIPS Architecture (4/7)

● MIPS uses registers for Reg. Reg. Usage

computations. Name Num
○ MIPS has 32 32-bit integer $zero $0 Hardware set to 0
registers ($0 - $31).
$at $1 Assembler temp
○ MIPS has 32 32-bit
floating-point registers $v0-$v1 $2-$3 Func result
($f0 - $f31).
$a0-$a3 $4-$7 Arg. Reg. 1
○ MIPS has special purpose
registers. $t0-$t7 $8-$15 Temp Reg

$s0-$s7 $16-$23 Saved Reg

September 20, 2023 ICT 1110 (2022/23) L16 - 23

 MIPS Architecture (5/7)

● Reserved registers must Reg. Reg. Usage

NOT be used in user Name Num
programs. $t8-$t9 $24-$25 Temp. Reg
○ $k0 - $k1.
$k0-$k1 $26-$27 Reserved for OS
○ $at is used by the
assembler. $gp $28 Global pointer
○ $gp is used to point to
$sp $29 Stack pointer
global data
$fp $30 Frame pointer

$ra $31 Return address

September 20, 2023 ICT 1110 (2022/23) L16 - 24

 MIPS Architecture (6/7)

● There are also other Reg. Reg. Usage

special purpose Name Num
registers. $t8-$t9 $24-$25 Temp. Reg
○ $pc is the program
$k0-$k1 $26-$27 Reserved for OS
counter register and
points to the next $gp $28 Global pointer
instruction
$sp $29 Stack pointer
○ $status is the processor
status and changes $fp $30 Frame pointer
after each instruction.
$ra $31 Return address

September 20, 2023 ICT 1110 (2022/23) L16 - 25

 MIPS Architecture (7/7)

● There are also other Reg. Reg. Usage

special purpose Name Num
registers. $t8-$t9 $24-$25 Temp. Reg
○ $cause is used by CPU
$k0-$k1 $26-$27 Reserved for OS
when an exception
occurs. $gp $28 Global pointer

$sp $29 Stack pointer

$fp $30 Frame pointer

$ra $31 Return address

September 20, 2023 ICT 1110 (2022/23) L16 - 26

 About MIPS Simulators

http://rivoire.cs.sonoma.edu/cs351/wemips

• Other assemblers (software) might enforce syntactic rules

• MipsIt (Standalone)
• MARS (Standalone, with IDE)
• WeMips (Web-based)
• Qemu (hypervisor that supports MIPS)
September 20, 2023 ICT 1110 (2022/23) L16 - 27
 QtSpim MIPS Simulator

● QtSpim is an R2000/R3000
processor simulator
○ Implements the MIPS32
assembler-extended
instruction set
○ QtSpim operating system
functionality through
system calls
○ QtSpim 9.1.21 will be
used

QtSpim 9.1.21
September 20, 2023 ICT 1110 (2022/23) L16 - 28
 QtSpim MIPS Simulator

● QtSpim is an R2000/R3000
processor simulator
○ Implements the MIPS32
assembler-extended
instruction set
○ QtSpim operating system
functionality through
system calls
○ QtSpim 9.1.21 will be
used

QtSpim 9.1.21
September 20, 2023 ICT 1110 (2022/23) L16 - 29
 QtSpim MIPS Simulator: Reference Text

● MIPS Assembly Language

Programming Using QtSpim.
Version 1.1.50
○ Jorgensen, E. (2019)

http://www.egr.unlv.edu/~ed/mips.html

September 20, 2023 ICT 1110 (2022/23) L16 - 30

 QtSpim MIPS Simulator: Installation and
Configuration (1/3)

http://www.egr.unlv.edu/~ed/mips.html

September 20, 2023 ICT 1110 (2022/23) L16 - 31

 QtSpim MIPS Simulator: Installation and
Configuration (2/3)

http://spimsimulator.sourceforge.net

September 20, 2023 ICT 1110 (2022/23) L16 - 32

 QtSpim MIPS Simulator: Installation and
Configuration (2/3)

http://spimsimulator.sourceforge.net

September 20, 2023 ICT 1110 (2022/23) L16 - 33

 QtSpim MIPS Simulator: Installation and
Configuration (3/3)

http://spimsimulator.sourceforge.net

September 20, 2023 ICT 1110 (2022/23) L16 - 34

 QtSpim MIPS Simulator: Installation and
Configuration (3/3)

http://spimsimulator.sourceforge.net

September 20, 2023 ICT 1110 (2022/23) L16 - 35

 QtSpim Interface: Menu Items (1/8)

QtSpim menu has

functionalities for configuring
the interface and simulator
settings
QtSpim 9.1.20
September 20, 2023 ICT 1110 (2022/23) L16 - 36
 QtSpim Interface: Menu Items (2/8)

“File” menu item used to load

programs

QtSpim 9.1.20
September 20, 2023 ICT 1110 (2022/23) L16 - 37
 QtSpim Interface: Menu Items (3/8)

“Simulator” menu item used to

configure QtSpim simulator
and, run/stop programs

QtSpim 9.1.20
September 20, 2023 ICT 1110 (2022/23) L16 - 38
 QtSpim Interface: Menu Items (4/8)

“Register” menu item used to

set visual preference for
registers

QtSpim 9.1.20
September 20, 2023 ICT 1110 (2022/23) L16 - 39
 QtSpim Interface: Menu Items (5/8)

“Text Segment” menu item used

to show/hide details in text
panel

QtSpim 9.1.20
September 20, 2023 ICT 1110 (2022/23) L16 - 40
 QtSpim Interface: Menu Items (6/8)

“Data Segment” menu item

used to show/hide details in
data panel

QtSpim 9.1.20
September 20, 2023 ICT 1110 (2022/23) L16 - 41
 QtSpim Interface: Menu Items (7/8)

“Window” menu item is used to

show/hide panel elements

QtSpim 9.1.20
September 20, 2023 ICT 1110 (2022/23) L16 - 42
 QtSpim Interface: Menu Items (8/8)

“Help” menu item is used to

access help documentation

QtSpim 9.1.20
September 20, 2023 ICT 1110 (2022/23) L16 - 43
 QtSpim Interface: Toolbar

The toolbar provides shortcuts

to features available via the
menu

QtSpim 9.1.20
September 20, 2023 ICT 1110 (2022/23) L16 - 44
 QtSpim Interface: Panels (1/6)

● QtSpim main
application window
have three panels
○ Register panel
○ Memory panel
○ Messages panel

QtSpim 9.1.20
September 20, 2023 ICT 1110 (2022/23) L16 - 45
 QtSpim Interface: Panels (2/6)

Register panel shows all 32

registers: general purpose
registers, floating point
registers, special registers
(remember the PC register?).
QtSpim 9.1.20
September 20, 2023 ICT 1110 (2022/23) L16 - 46
 QtSpim Interface: Panels (3/6)

Text panel shows assembly

language source program,
machine code equivalent
and memory addresses.
QtSpim 9.1.20
September 20, 2023 ICT 1110 (2022/23) L16 - 47
 QtSpim Interface: Panels (3/6)

Memory address of
instruction in
hexadecimal format.

QtSpim 9.1.20
September 20, 2023 ICT 1110 (2022/23) L16 - 48
 QtSpim Interface: Panels (3/6)

Contents of memory in
hexadecimal format.

QtSpim 9.1.20
September 20, 2023 ICT 1110 (2022/23) L16 - 49
 QtSpim Interface: Panels (3/6)

Assembly language
instruction using
hardware register
numbers

QtSpim 9.1.20
September 20, 2023 ICT 1110 (2022/23) L16 - 50
 QtSpim Interface: Panels (3/6)

Assembly language
program showing
symbolic register and
memory locations.
QtSpim 9.1.20
September 20, 2023 ICT 1110 (2022/23) L16 - 51
 QtSpim Interface: Panels (4/6)

QtSpim 9.1.20
September 20, 2023 ICT 1110 (2022/23) L16 - 52
 QtSpim Interface: Panels (5/6)

Output panel shows

detailed logs as
programs are executed

QtSpim 9.1.20
September 20, 2023 ICT 1110 (2022/23) L16 - 53
 QtSpim Interface: Panels (6/6)

Console is used to
view output from
programs that
return values

QtSpim 9.1.20
September 20, 2023 ICT 1110 (2022/23) L16 - 54
 Loading Source Programs

● When a program is loaded, QtSpim assembles the program

○ Programs must be syntactically correct before they are execute
○ Programmer MUST ensure program code has no error prior to
execution
● Load the source program results in a series of events.
○ The file is assembled into equivalent representation of machine
instructions.
○ The instructions are loaded into SPIM's memory. The text display
shows the result.
● The text panel shows the result.
○ The leftmost column are addresses in simulated memory.
September 20, 2023 ICT 1110 (2022/23) L16 - 55
 Executing Source Programs (1/2)

QtSpim 9.1.20
September 20, 2023 ICT 1110 (2022/23) L16 - 56
 Executing Source Programs (2/2)

QtSpim 9.1.20
September 20, 2023 ICT 1110 (2022/23) L16 - 57
 Assembly Source Programs

● Assembly source programs are created by human

programmers.
○ Program statements are placed in a source file.
○ Source files are created using editors such as vi, emacs, kile.

Kate 17.12.3

September 20, 2023 ICT 1110 (2022/23) L16 - 58

 Elements of Assembly Source Programs (1/6)

● Comments are represented by a hash: #.

○ Comments are textual description that explain why sequence of
instructions was used.
○ Comments are ignored by the assembler: no machine code.

Kate 17.12.3

September 20, 2023 ICT 1110 (2022/23) L16 - 59

 Elements of Assembly Source Programs (2/6)

● Directives are used to signal the assembler about something.

They are not converted into machine code.
○ ‘text’ specifies that instructions are text—source code.
○ ‘globl main’ specifies context of main label.

Kate 17.12.3

September 20, 2023 ICT 1110 (2022/23) L16 - 60

 Elements of Assembly Source Programs (3/6)

● Blank lines are ignored by the assembler.

○ They only ensure that the series of instructions are easily
readable.

Kate 17.12.3

September 20, 2023 ICT 1110 (2022/23) L16 - 61

 Elements of Assembly Source Programs (4/6)

● ‘main:’ specifies a symbolic address for source code.

○ This is also specified as a statement label.
○ Symbolic address provide symbol for source code name for
location in memory.
○ Symbolic address is easier to read than actual address.

Kate 17.12.3

September 20, 2023 ICT 1110 (2022/23) L16 - 62

 Elements of Assembly Source Programs (5/6)

● add $8, $0, 2’ translates into a machine instruction that puts

2 into register 8. Similar thing happens in Line 7.
● ‘add $10, $8, $9’ adds registers 8 and 9 and put the result into
register 10.

Kate 17.12.3

September 20, 2023 ICT 1110 (2022/23) L16 - 63

 Elements of Assembly Source Programs (6/6)

● All instructions have three operands.

● The operand order is fixed.
○ The destination is always the first operand.
○ add $10, $8, $9 is similar to C = A + B

Kate 17.12.3

September 20, 2023 ICT 1110 (2022/23) L16 - 64

 Register Use Chart

September 20, 2023 ICT 1110 (2022/23) L16 - 65

 Summary

● MIPS Architecture
● QtSpim R3000 Processor Simulator
● QtSpim: Installation and Configuration
● QtSpim: Interface
● QtSpim: Loading Assembly Programs
● QtSpim: Executing Assembly Programs
● QtSpim: Interpreting Program Output
● Elements of MIPS Assembly Programs

September 20, 2023 ICT 1110 (2022/23) L16 - 66

 Q & A Session

● Comments, concerns and complaints?

September 20, 2023 ICT 1110 (2022/23) L16 - 67

Bibliography
[1] Patterson D. A. and Hennesy J.L. Computer Organisation and
Design. The Hardware/Software Interface. Chapter 2
[2] Patterson D. A. and Hennesy J.L. Computer Organisation and
Design. The Hardware/Software Interface. Appendix A
[3] Getting Started with SPIM
http://pages.cs.wisc.edu/~larus/spim.pdf
[4] MIPS Assembly Language Programming Using QtSpim
http://www.egr.unlv.edu/~ed/MIPStextSMv11.pdf
[email protected]
https://bit.ly/3uJBZRc
http://bit.ly/2kK2ZkA
 ICT 1110 (2022/23)
Computer Systems & Architecture
Lecture 16: MIPS Instruction Set
Architecture I
Lighton Phiri <[email protected]>
Department of Library & Information Science
University of Zambia
https://bit.ly/3uJBZRc