Placement

BY : Abhishek Mandole
LinkedIn : Abhishek Mandole
add_buffer [get_nets –of [get_ports *] ] [get_lib_cells */SAEDRVT14_BUF_20]
▪ This code automates the process of adding buffers to all the nets connected to the chip's external
ports. Buffers are small driver circuits that strengthen the signal on a net, improving signal
integrity.
▪ [get_ports *]: This command retrieves a list of all the ports (input/output pins) of the design.
▪ [get_nets –of [get_ports *] ] : This command uses the output (-of) of the previous command (list
of ports) to find all the nets that are connected to any of those ports. Essentially it identifies all the
nets that interact with the external world.
▪ [get_lib_cells */SAEDRVT14_BUF_20] : This command retrieves information about a specific
cell from the standard cell library. In this case, it targets the cell named “SAEDRVT14_BUF_20”
which likely represents a buffer with a specific driving strength (SAEDRVT14) and size (20).

magnet_placement [get_ports *]
▪ This command instructs the tool to prioritize placing certain standard cells close to specific ports
during the placement process. These standard cells are likely I/O (input/output) buffers or cells that
are critical for signal integrity at the chip's interface.
▪ magnet_placement : This function or command suggests a placement strategy where specific cells
are “attracted” to certain locations.
▪ [get_ports *] :This part retrieves a list of all the ports (input/output pins) of the design

BY : Abhishek Mandole
LinkedIn : Abhishek Mandole
set_attribute [get_cells eco_cel *] physical_status fixed
▪ set_attribute : This command is used to modify attributes (properties) of design objects, such as
cells in this case.
▪ [get_cells eco_cel *] : This part retrieves a list of cells that match a specific criteria.
▪ get_cells : This function retrieves cells based on some criteria.
▪ eco_cell * : This specifies the criteria for selecting cells. “eco_cell” This likely refers to a
specific cell property or "cell tag" that identifies ECO (Engineering Change Order) cells.
▪ “*” : Indicates selecting all cells with this property.
▪ physical_status fixed : This defines the new value you want to set for the "physical_status"
attribute of the selected cells. Here, "fixed" indicates that the placement of these cells should be
fixed.

group_path –name MACRO2REG –from [get_cells –physical_context –filter design_type==macro]

–to [all_registers]
▪ creates a custom design grouping for easier analysis and potentially layout optimization.
▪ group_path : This function or command creates a new group within the design hierarchy.
▪ -name MACRO2REG : This option assigns a name to the group, which is "MACRO2REG" in
this case.
▪ –from [het_cells –physical_context –filter design_type==macro] –to [all_registers] : This part
defines the source objects for the group.

BY : Abhishek Mandole
LinkedIn : Abhishek Mandole
▪ get_cells : This retrieves cells based on specific criteria.
▪ -physical_context : This likely considers the physical location or placement of the cells.
▪ -filter design_type==macro : This filter selects only those cells where the “design_type”
attribute is equal to "macro". Essentially, it targets all macro cells within the design.
▪ -to [all_registers] : This part defines the destination objects for the group.

group_path –name REG2MACRO –from [all_registers] –to [get_cells –physical_context –filter

design_type==macro]
▪ This code snippet creates a group named “REG2MACRO” that contains all macro cells within
the design that have at least one register located physically close to them.
▪ –name REG2MACRO : This option assigns a name to the group, which is "REG2MACRO" in
this case.
▪ –from [all_registers] : This part defines the source objects for the group. Here, “[all_registers]”
refers to all registers present in the design.
▪ –to [get_cells –physical_context –filter design_type==macro] : This part defines the
destination objects for the group.

group_path -name INPUTS2REG -from [all_inputs] -to [all_registers]

▪ This code snippet creates a group named "INPUTS2REG" that contains all the logic cells and
routing paths that connect the design's input pins to all the registers within the design. It focuses
on the data flow specifically from inputs to registers, not necessarily all the way to outputs.

BY : Abhishek Mandole
LinkedIn : Abhishek Mandole
▪ -from [all_inputs] : This part defines the source objects for the group. Here, "[all_inputs]" refers to
all input pins of the design
▪ -to [all_registers] : This part defines the destination objects for the group. Here, "[all_registers]"
refers to all registers present in the design.

group_path –name OUTPUTS2REG –from [all_registers] –to [all_outputs]

▪ This code snippet creates a group named "OUTPUT2REG" that encompasses all the logic cells and
routing paths that connect the design's registers to its output pins. In simpler terms, it groups
everything involved in the data flow from registers to the final outputs.
▪ -from [all_registers] :This part defines the source objects for the group. Here, "[all_registers]"
refers to all registers present in the design.
▪ -to [all_outputs] : This part defines the destination objects for the group. Here, "[all_outputs]"
refers to all output pins of the design.

group_path –name REG2REG –from [all_registers] –to [all_registers]

▪ creates a group that encompasses all possible connections between registers in your design.
▪ This code snippet creates a group that includes all registers and potentially all the logic cells and
routing paths between any two registers in the design. Since both source and destination are all
registers, it captures any connection that might exist between them.
▪ –from [all_registers] : This part defines the source objects for the group. Here, "[all_registers]"
refers to all registers present in the design.
▪ –to [all_registers] : Interestingly, both source and destination are set to "[all_registers]".
BY : Abhishek Mandole
LinkedIn : Abhishek Mandole
check_design -checks pre_placement_stage
▪ check_design : This command initiates a design rule check (DRC) on your design.
▪ -checks pre_placement_stage : This option specifies the stage at which the DRC should be run.
In this case, it's the "pre-placement stage".

set_app_options –name place.coarse.continue_on_missing_scandef –value true

▪ set_app_options : This command is used to configure settings within the placement tool.
▪ –name place.coarse.continue_on_missing_scandef –value true : You are instructing the
placement tool in the "coarse" placement stage to continue even if scan definitions are missing.
▪ place :This indicates the category of the option, likely related to the placement algorithm.
▪ coarse : This might refer to a specific stage or mode within the placement process (potentially a
coarse or initial placement stage).

set_app_options -name place.coarse.max_density -value 0.6

▪ set_app_options : This command is used to configure settings within the placement tool.
▪ place.coarse.max_density -value 0.6 : you are instructing the placement tool during the "coarse"
placement stage to prioritize placing cells while keeping the overall utilization below 60%.

BY : Abhishek Mandole
LinkedIn : Abhishek Mandole
set_app_options -name place.coarse.congestion_driven_max_util -value 0.6
▪ -name place.coarse.congestion_driven_max_util -value 0.6 : You are instructing the placement
tool during the "coarse" placement stage to use a congestion-driven approach but limit the overall
cell utilization to a maximum of 60%.

analyze_lib_cell_placement -lib_cells *
▪ analyze_lib_cell_placement : This function or command initiates an analysis specifically focused
on the placement of standard library cells.
▪ -lib_cells * : This option specifies the target cells for analysis. The wildcard character “*” indicates
all standard library cells in the design.

create_placement –congestion
▪ Initiates the placement process with a focus on congestion management.
▪ create_placement : This command or function triggers the placement stage of the design flow,
where standard library cells are arranged on the chip layout.
▪ -congestion : This option instructs the placement tool to prioritize congestion management during
the placement process.

set_parasitic_parameters -early_spec best_para

▪ sets parasitic parameters for early design analysis.
▪ -early_spec : option in your code snippet likely refers to using an "early" or preliminary estimation
method for parasitic parameters. BY : Abhishek Mandole
LinkedIn : Abhishek Mandole
▪ best_para : option likely indicates using the "best" or most appropriate estimation method
available within the tool for this early design analysis stage.

set_parasitic_parameters -late_spec worst_para

▪ Sets parasitic parameters for a more critical analysis stage in the design.
▪ -late_spec : option in your code snippet likely refers to using a more precise or "late"
specification for parasitic parameters. This typically happens after the layout is more finalized.
▪ worst_para : option indicates using the most pessimistic or "worst-case" scenario for parasitic
extraction. This means the tool considers the parasitic effects that could have the most negative
impact on circuit performance.

check_legality –verbose
▪ check_legality : This command initiates a design rule check (DRC) on your design.
▪ –verbose : This option instructs the tool to provide a more detailed output compared to the
default behavior.

set_attribute [get_lib_cells */*LVT*] threshold_voltage_group LVT

▪ Modifies an attribute of standard library cells within your design.
▪ get_lib_cells : This function retrieves information about standard library cells from the design
library.
▪ */*LVT* : This wildcard expression likely selects all standard library cells whose names contain
the substring "LVT". This likely refers to cells optimized for Low Voltage Threshold (LVT)
processes.
BY : Abhishek Mandole
LinkedIn : Abhishek Mandole
▪ threshold_voltage_group LVT : This specifies the name of the attribute being modified. In this
case, it refers to an attribute likely related to the threshold voltage of the transistors within these
cells.

set_threshold_voltage_group_type -type low_vt LVT

▪ Defines a relationship between a voltage group name and its actual electrical properties.
▪ set_threshold_voltage_group_type : This command is likely specific to your design tool and
sets properties for threshold voltage groups.
▪ -type low_vt : This option defines the electrical characteristic associated with the group. In this
case, "low_vt" indicates a low threshold voltage.
▪ LVT : This argument assigns the name "LVT" to the voltage group with low threshold voltage
characteristics.

set_multi_vth_constraint -low_vt_percentage 5 -cost cell_count

▪ set_multi_vth_constraint : you are instructing the tool to consider Vt variations during
placement.
▪ -low_vt_percentage 5 : This option sets a target percentage for low Vt (LVT) cells in the
placement. In this case, it aims for 5% of the placed cells to be LVT cells.
▪ -cost cell_count : This option defines the cost metric used by the tool to optimize placement
while considering the Vt constraint. Here, "cell_count" indicates that the tool will try to
minimize the total number of cells used.

BY : Abhishek Mandole
LinkedIn : Abhishek Mandole
analyze_design_violations
▪ Initiates a process to examine your design for potential rule violations.

place_opt -to final_opt

▪ Initiates a final optimization stage after the placement process.
▪ After arranging standard library cells on the chip layout during the placement stage, there might still
be room for improvement.
▪ Placement optimization is an iterative process that refines the initial placement solution to achieve
better results according to specified goals.
▪ -to final_opt : option likely indicates that this is the final round of placement optimization in your
design flow.

report_qor –summary
▪ You instruct the tool to generate a concise report focusing on the essential QoR metrics. This
summary can help you quickly assess the overall health of your design layout.

report_timing
▪ The tool analyzes your design layout, including the placed and routed cells, and calculates the delays
for various signal paths.

BY : Abhishek Mandole
LinkedIn : Abhishek Mandole
report_utilization -config core_utilization
▪ report_utilization : command is likely a general command for generating utilization reports in
your EDA tool.
▪ -config core_utilization : option specifies that you want a report focused on the core area
utilization.

save_block –as placement_done

BY : Abhishek Mandole
LinkedIn : Abhishek Mandole
Thank You

BY : Abhishek Mandole
LinkedIn : Abhishek Mandole