4.

10 A Simple Program (1 of 3)

Consider the simple MARIE program given

below. We show a set of mnemonic
instructions stored at addresses 0x100
0x106 (hex):
 4.10 A Simple Program (2 of 3)

computer when our program runs.

This is the LOAD 104 instruction:
 4.10 A Simple Program (3 of 3)

Our second instruction is ADD 105:

4.11 A Discussion on Assemblers (1 of 4)

Mnemonic instructions, such as LOAD 104, are

easy for humans to write and understand.
They are impossible for computers to understand.
Assemblers translate instructions that are
comprehensible to humans into the machine
language that is comprehensible to computers
We note the distinction between an assembler and a
compiler: In assembly language, there is a one-to-one
correspondence between a mnemonic instruction and
its machine code. With compilers, this is not usually
the case.
4.11 A Discussion on Assemblers (2 of 4)

Assemblers create an object program file from

mnemonic source code in two passes.
During the first pass, the assembler assembles
as much of the program as it can, while it
builds a symbol table that contains memory
references for all symbols in the program.
During the second pass, the instructions are
completed using the values from the symbol
table.
4.11 A Discussion on Assemblers (3 of 4)

Consider our example

program at the right.
Note that we have
included two
directives HEX and
DEC that specify the
radix of the
constants.
The first pass, creates
a symbol table and
the partially-
assembled
instructions as shown.
4.11 A Discussion on Assemblers (4 of 4)

After the second pass, the assembly is

complete.
 4.12 Extending Our Instruction Set
(1 of 6)

So far, all of the MARIE instructions that we

have discussed use a direct addressing mode.
This means that the address of the operand is
explicitly stated in the instruction.
It is often useful to employ a indirect
addressing, where the address of the address
of the operand is given in the instruction.
If you have ever used pointers in a program, you
are already familiar with indirect addressing.
 4.12 Extending Our Instruction Set
(2 of 6)
We have included three indirect addressing mode instructions
in the MARIE instruction set.
The first two are LOADI X and STOREI X where specifies
the address of the operand to be loaded or stored.
In RTL :

LOADI X STOREI X
 4.12 Extending Our Instruction Set
(3 of 6)

The ADDI X where specifies the address of

the operand to be added.
In RTL:

ADDI X
 4.12 Extending Our Instruction Set
(4 of 6)
Another helpful programming tool is the use of subroutines.
The jump-and-store instruction, JNS, gives us limited
subroutine functionality. The details of the JNS instruction are
given by the following RTL:

Does JNS permit

recursive calls?
PC AC
 4.12 Extending Our Instruction Set
(5 of 6)
Our first new instruction is the CLEAR
instruction.
All it does is set the contents of the
accumulator to all zeroes.
This is the RTL for CLEAR:
AC 0

We put our new instructions to work in the

program on the following slide.
 4.12 Extending Our Instruction Set (6 of 6)
Example 4.2 on the textbook and Ex4_1.mas in the MARIE
simulator package: Using loop to add five numbers.

100 | LOAD Addr 10E | SKIPCOND 000

101 | STORE Next 10F | JUMP Loop
102 | LOAD Num 110 | HALT
103 | SUBT One 111 |Addr HEX 117
104 | STORE Ctr 112 |Next HEX 0
105 |Loop LOAD Sum 113 |Num DEC 5
106 | ADDI Next 114 |Sum DEC 0
107 | STORE Sum 115 |Ctr HEX 0
108 | LOAD Next 116 |One DEC 1
109 | ADD One 117 | DEC 10
10A | STORE Next 118 | DEC 15
10B | LOAD Ctr 119 | DEC 2
10C | SUBT One 11A | DEC 25
10D | STORE Ctr 11B | DEC 30
 MARIE Assembly Program: Example 4.3
Ex4_2.mas in the MARIE simulator package
If X = Y then
X=X 2
ORG 100 else
If, Load X /Load the first value Y=Y-X
Subt Y /Subtract the value of Y, store result in AC
Skipcond 400 /If AC=0, skip the next instruction
Jump Else /Jump to Else part if AC is not equal to 0
Then, Load X /Reload X so it can be doubled
Add X /Double X
Store X /Store the new value
Jump Endif /Skip over the false, or else, part to end of if
Else, Load Y /Start the else part by loading Y
Subt X /Subtract X from Y
Store Y /Store Y-X in Y
Endif, Halt /Terminate program (it doesn't do much!)
X, Dec 12 /Load the loop control variable
Y, Dec 20 /Subtract one from the loop control variable
END
 MARIE Assembly Program: Example 4.4
Ex4_3.mas in the MARIE simulator package

/ This program traverses a string and outputs each

/ character. The string is terminated with a null.
/ Note: By changing the output window control setting
/ to "no linefeeds" the text will print in a single
/ line, rather than in a column of single characters.
ORG 100
Getch, LoadI Chptr / Load the character found at address chptr.
Skipcond 400 / If the character is a null, we are done.
Jump Outp / Otherwise, proceed with operation.
Halt
 MARIE Assembly Program: Example 4.4
Outp, Output / Output the character.
Load Chptr / Move pointer to next character.
Add One
Store Chptr
Jump Getch
One, Hex 0001
Chptr, Hex 10B
String, Dec 072 /H
Dec 101 /e
Dec 108 /l
Dec 108 /l
Dec 111 /o
Dec 032 / [space]
Dec 119 /w
Dec 111 /o
Dec 114 /r
Dec 108 /l
Dec 100 /d
Dec 033 /!
Dec 000 / [null]
END
 MARIE Assembly Program: Example 4.5
Ex4_4.mas in the MARIE simulator package

/This example illustrates the use of a simple subroutine to double the value stored at X

ORG 100
Load X / Load the first number to be doubled.
Store Temp / Use Temp as a parameter to pass value to Subr.
JnS Subr / Store the return address, and jump to the procedure.
Store X / Store the first number, doubled
Load Y / Load the second number to be doubled.
Store Temp
JnS Subr / Store the return address and jump to the procedure.
Loop, Store Y / Store the second number doubled.
Halt / End program.
X, DEC 20
Y, DEC 48
Temp, DEC 0
 MARIE Assembly Program: Example 4.5

Subr, HEX 0 / Store return address here.

Load Temp / Actual subroutine to double numbers.
Add Temp / AC now holds double the value of Temp.
JumpI Subr / Return to calling code.
END
4.13 A Discussion on Decoding (1 of 21)

synchronized, making sure that bits flow to the

correct components as the components are
needed.
There are two general ways in which a control unit
can be implemented: hardwired control and
microprogrammed control.
With microprogrammed control, a small program is
placed into read-only memory in the microcontroller.
Hardwired controllers implement this program using
digital logic components.
4.13 A Discussion on Decoding (2 of 21)

Your text provides a complete list of the register

The microoperations given by each RTL define the

Each microoperation consists of a distinctive signal

pattern that is interpreted by the control unit and
results in the execution of an instruction.
Recall, the RTL for the Add instruction is:
MAR X
MBR M[MAR]
AC AC + MBR
4.13 A Discussion on Decoding (3 of 21)

registers and main

memory have a unique
address along the
datapath.
The addresses take the
form of signals issued
by the control unit.
4.13 A Discussion on Decoding (4 of 21)

Let us define two sets of

three signals.
One set, P2, P1, P0, controls
reading from memory or a
register, and the other set
consisting of P5, P4, P3,
controls writing to memory or
a register.
4.13 A Discussion on Decoding (5 of 21)

The register MBR is enabled for reading when P0 and P1

are high, and enabled for writing when P3 and P4 are high.
4.13 A Discussion on Decoding (6 of 21)

RTL reveals that the ALU has

only three operations: add,
subtract, and clear.
We will also define a fourth

signals consists of:

Register controls: P0 through P5,
MR , and MW.
ALU controls: A0 through A1 and
LALT
source.
Timing: T0 through T7 and counter
reset Cr
4.13 A Discussion on Decoding (7 of 21)

MAR X
MBR M[MAR]
AC AC + MBR
After an Add instruction is fetched, the address, X, is in
the rightmost 12 bits of the IR, which has a datapath
address of 7.
X is copied to the MAR, which has a datapath address of 1.
Thus we need to raise signals P0, P1, and P2 to read from
the IR, and signal P3 to write to the MAR.
4.13 A Discussion on Decoding (8 of 21)

instruction:
P3 P2 P1 P0 T3 : MAR X
P4 P3 T4 MR : MBR M[MAR]
Cr A0 P5 T5 LALT : AC AC + MBR
[Reset counter]
These signals are ANDed with combinational logic to
bring about the desired machine behavior.
The next slide shows the timing diagram for this
instruction.
 4.13 A Discussion on Decoding (9 of 21)
Notice the concurrent signal states
during each machine cycle: C3
through C5.

P3 P2 P1 P0 T3 : MAR X
P4 P3 T4 MR : MBR M[MAR]
Cr A0 P5 T5 LALT : AC AC + MBR
[Reset counter]
 4.13 A Discussion on Decoding
(10 of 21)
We note that the signal pattern just described is the
same whether our machine used hardwired or
microprogrammed control.
In hardwired control, the bit pattern of machine
instruction in the IR is decoded by combinational
logic.
The decoder output works with the control signals
of the current system state to produce a new set of
control signals.

A block diagram of a hardwired control unit is shown on

the following slide.
4.13 A Discussion on Decoding
(11 of 21)
 4.13 A Discussion on Decoding
(12 of 21)

MARIE's instruction decoder. (Partial.)

 4.13 A Discussion on Decoding
(13 of 21)
A ring counter that counts from 0 to 5
 4.13 A Discussion on Decoding
(14 of 21)

= 0011 instruction.
 4.13 A Discussion on Decoding
(15 of 21)

In microprogrammed control, instruction

microcode produces control signal changes.
Machine instructions are the input for a
microprogram that converts the 1s and 0s of
an instruction into control signals.
The microprogram is stored in firmware,
which is also called the control store.
A microcode instruction is retrieved during
each clock cycle.
 4.13 A Discussion on Decoding
(16 of 21)

This is how a generic microprogrammed

control unit might look.
 4.13 A Discussion on Decoding
(17 of 21)
If MARIE were microprogrammed, the
microinstruction format might look like this:

MicroOp1 and MicroOp2 contain binary codes for

each instruction. Jump is a single bit indicating that
the value in the Dest field is a valid address and
should be placed in the microsequencer.
 4.13 A Discussion on Decoding
(18 of 21)

microoperation codes along with the

corresponding RTL:
 4.13 A Discussion on Decoding
(19 of 21)

microprogram are given below (using RTL

for clarity):
 4.13 A Discussion on Decoding
(20 of 21)
The first four lines are the fetch-decode-
execute cycle.
The remaining lines are the beginning of a
jump table.
 4.13 A Discussion on Decoding
(21 of 21)

control unit works like a system-in-miniature.

Microinstructions are fetched, decoded, and executed
in the same manner as regular instructions.
This extra level of instruction interpretation is what
makes microprogrammed control slower than
hardwired control.
The advantages of microprogrammed control are that it
can support very complicated instructions and only the
microprogram needs to be changed if the instruction
set changes (or an error is found).
4.14 Real-World Architectures (1 of 7)

MARIE shares many features with modern

architectures but it is not an accurate depiction of
them.
In the following slides, we briefly examine two
machine architectures.
We will look at an Intel architecture, which is a CISC
machine and MIPS, which is a RISC machine.
CISC is an acronym for complex instruction set
computer.
RISC stands for reduced instruction set computer.
4.14 Real-World Architectures (2 of 7)

The classic Intel architecture, the 8086, was

born in 1979. It is a CISC architecture.
It was adopted by IBM for its famed PC, which
was released in 1981.
The 8086 operated on 16-bit data words and
supported 20-bit memory addresses.
Later, to lower costs, the 8-bit 8088 was
introduced. Like the 8086, it used 20-bit
memory addresses.
What was the largest memory that the 8086 could address?
4.14 Real-World Architectures (3 of 7)

The 8086 had four 16-bit general-purpose registers

that could be accessed by the half-word.
It also had a flags register, an instruction register,
and a stack accessed through the values in two
other registers, the base pointer and the stack
pointer.
The 8086 had no built in floating-point processing.
In 1980, Intel released the 8087 numeric
coprocessor, but few users elected to install them
because of their high cost.
4.14 Real-World Architectures (4 of 7)

In 1985, Intel introduced the 32-bit 80386.

It also had no built-in floating-point unit.
The 80486, introduced in 1989, was an 80386 that
had built-in floating-point processing and cache
memory.
The 80386 and 80486 offered downward
compatibility with the 8086 and 8088.
Software written for the smaller-word systems was
directed to use the lower 16 bits of the 32-bit
registers.
4.14 Real-World Architectures (5 of 7)

architecture.
Speed enhancing features include:
Hyperthreading
Hyperpipelining
Wider instruction pipeline
Execution trace cache (holds decoded instructions for
possible reuse) multilevel cache and instruction pipelining.
Intel, along with many others, is marrying many of the
ideas of RISC architectures with microprocessors that
are largely CISC.
4.14 Real-World Architectures (6 of 7)

The MIPS family of CPUs has been one of the most

successful in its class.
In 1986 the first MIPS CPU was announced.
It had a 32-bit word size and could address 4GB of
memory.
Over the years, MIPS processors have been used in
general purpose computers as well as in games.
The MIPS architecture now offers 32- and 64-bit
versions.
4.14 Real-World Architectures (7 of 7)

MIPS was one of the first RISC microprocessors.

The original MIPS architecture had only 55 different
instructions, as compared with the 8086 which had
over 100.
MIPS was designed with performance in mind: It is
a load/store architecture, meaning that only the
load and store instructions can access memory.
The large number of registers in the MIPS
architecture keeps bus traffic to a minimum.
How does this design affect performance?
 Conclusion (1 of 2)

The major components of a computer system

are its control unit, registers, memory, ALU,
and data path.
A built-in clock keeps everything synchronized.
Control units can be microprogrammed or
hardwired.
Hardwired control units give better
performance, while microprogrammed units
are more adaptable to changes.
 Conclusion (2 of 2)

Computers run programs through iterative

fetch-decode-execute cycles.
Computers can run programs that are in
machine language.
An assembler converts mnemonic code to
machine language.
The Intel architecture is an example of a CISC
architecture; MIPS is an example of a RISC
architecture.