Chapter 4

MARIE: An
Introduction
to a Simple Computer
 Objectives

Learn the components common to every

modern computer system.
Be able to explain how each component
contributes to program execution.
Understand a simple architecture invented to
illuminate these basic concepts, and how it
relates to some real architectures.
Know how the program assembly process
works.
 4.1 Introduction

Chapter 1 presented a general overview of

computer systems.
In Chapter 2, we discussed how data is stored and
manipulated by various computer system
components.
Chapter 3 described the fundamental components
of digital circuits.
Having this background, we can now understand
how computer components work, and how they fit
together to create useful computer systems.
 4.2 CPU Basics (1 of 2)

executes program instructions.

The two principal parts of the CPU are the
datapath and the control unit.
The datapath consists of an arithmetic-logic unit
and storage units (registers) that are
interconnected by a data bus that is also
connected to main memory.
Various CPU components perform sequenced
operations according to signals provided by its
control unit.
 4.2 CPU Basics (2 of 2)

Registers hold data that can be readily

accessed by the CPU.
They can be implemented using D flip-flops.
A 32-bit register requires 32 D flip-flops.
The arithmetic-logic unit (ALU) carries out
logical and arithmetic operations as directed
by the control unit.
The control unit determines which actions to
carry out according to the values in a program
counter register and a status register.
 4.3 The Bus (1 of 5)

The CPU shares data with other system

components by way of a data bus.
A bus is a set of wires that simultaneously convey
a single bit along each line.
Two types of buses are commonly found in
computer systems: point-to-point, and
multipoint buses.
These are
point-to-point buses:
 4.3 The Bus (2 of 5)

Buses consist of data lines, control lines,

and address lines.
While the data lines convey bits from one
device to another, control lines determine
the direction of data flow, and when each
device can access the bus.
Address lines determine the location of the
source or destination of the data.
The next slide shows a model bus configuration.
4.3 The Bus (3 of 5)
 4.3 The Bus (4 of 5)

A multipoint bus is shown below.

Because a multipoint bus is a shared
resource, access to it is controlled through
protocols, which are built into the
hardware.
 4.3 The Bus (5 of 5)

In a master-slave configuration, where more than one

device can be the bus master, concurrent bus master
requests must be arbitrated.
Four categories of bus arbitration are:
Daisy chain: Permissions are passed from the highest-priority
device to the lowest.
Centralized parallel: Each device is directly connected to an
arbitration circuit.
Distributed using self-detection: Devices decide which gets the
bus among themselves.
Distributed using collision-detection: Any device can try to use
the bus. If its data collides with the data of another device, it tries
again.
 4.4 Clocks (1 of 2)

Every computer contains at least one clock that

synchronizes the activities of its components.
A fixed number of clock cycles are required to carry
out each data movement or computational
operation.
The clock frequency, measured in megahertz or
gigahertz, determines the speed with which all
operations are carried out.
Clock cycle time is the reciprocal of clock frequency.
An 800 MHz clock has a cycle time of 1.25 ns.
 4.4 Clocks (2 of 2)

Clock speed should not be confused with CPU

performance.
The CPU time required to run a program is given by
the general performance equation:

We see that we can improve CPU throughput when we

reduce the number of instructions in a program,
reduce the number of cycles per instruction, or reduce
the number of nanoseconds per clock cycle.
We will return to this important equation in later chapters.
4.5 The Input/Output Subsystem

A computer communicates with the outside world

through its input/output (I/O) subsystem.
I/O devices connect to the CPU through various
interfaces.
I/O can be memory-mapped where the I/O device
view.
Or I/O can be instruction-based, where the CPU has
a specialized I/O instruction set.

We study I/O in detail in chapter 7.

4.6 Memory Organization (1 of 8)

Computer memory consists of a linear array of

addressable storage cells that are similar to
registers.
Memory can be byte-addressable, or word-
addressable, where a word typically consists of two
or more bytes.
Memory is constructed of RAM chips, often
referred to in terms of length width.
If the memory word size of the machine is 16 bits,
then a 4M 16 RAM chip gives us 4 mega 16-bit
memory locations.
4.6 Memory Organization (2 of 8)

How does the computer access a memory location

corresponds to a particular address?
We observe that 4M can be expressed as 22 220 =
222 words.
The memory locations for this memory are numbered
0 through 222 1.
Thus, the memory bus of this system requires at least
22 address lines.
22 1 in binary.

of the desired memory element.

4.6 Memory Organization (3 of 8)
Physical memory usually consists of more than one
RAM chip.
Access is more efficient when memory is organized
into banks of chips with the addresses interleaved
across the chips
With low-order interleaving, the low order bits of
the address specify which memory bank contains
the address of interest.
Accordingly, in high-order interleaving, the high
order address bits specify the memory bank.
The next two slides illustrate these two ideas.
4.6 Memory Organization (4 of 8)

Example: Suppose we have a

memory consisting of 16 2K x
8 bit chips.
Memory is 32K = 25 210 = 215
15 bits are needed for each
address.
We need 4 bits to select the
chip, and 11 bits for the offset
into the chip that selects the
byte.
4.6 Memory Organization (5 of 8)

In high-order interleaving the high-order 4

bits select the chip.
In low-order interleaving the low-order 4
bits select the chip.
4.6 Memory Organization (6 of 8)
4.6 Memory Organization (7 of 8)
4.6 Memory Organization (8 of 8)

EXAMPLE 4.1: Suppose we have a 128-word memory

that is 8-way low-order interleaved
which means it uses 8 memory banks; 8 = 23
So we use the low-order 3 bits to identify the bank.
Because we have 128 words, we need 7 bits for each
address (128 = 27).
 4.7 Interrupts

The normal execution of a program is altered when

an event of higher-priority occurs. The CPU is
alerted to such an event through an interrupt.
Interrupts can be triggered by I/O requests,
arithmetic errors (such as division by zero), or when
an invalid instruction is encountered.
Each interrupt is associated with a procedure that
directs the actions of the CPU when an interrupt
occurs.
Nonmaskable interrupts are high-priority interrupts
that cannot be ignored.
 4.8 MARIE (1 of 14)

We can now bring together many of the ideas that

we have discussed to this point using a very simple
model computer.
Our model computer, the Machine Architecture
that is Really Intuitive and Easy (MARIE) was
designed for the singular purpose of illustrating
basic computer system concepts.
While this system is too simple to do anything
useful in the real world, a deep understanding of its
functions will enable you to comprehend system
architectures that are much more complex.
 4.8 MARIE (2 of 14)

The MARIE architecture has the following

characteristics:
Binary, two's complement data representation.
Stored program, fixed word length data and
instructions.
4K words of word-addressable main memory.
16-bit data words.
16-bit instructions, 4 for the opcode and 12 for the
address.
A 16-bit arithmetic logic unit (ALU).
Seven registers for control and data movement.
 4.8 MARIE (3 of 14)

(1) Accumulator, AC, a 16-bit register that holds a

conditional operator (e.g., "less than") or one
operand of a two-operand instruction.
(2) Memory address register, MAR, a 12-bit
register that holds the memory address of an
instruction or the operand of an instruction.
(3) Memory buffer register, MBR, a 16-bit register
that holds the data after its retrieval from, or
before its placement in memory.
 4.8 MARIE (4 of 14)

(4) Program counter, PC, a 12-bit register that

holds the address of the next program instruction
to be executed.
(5) Instruction register, IR, which holds an
instruction immediately preceding its execution.
(6) Input register, InREG, an 8-bit register that
holds data read from an input device.
(7) Output register, OutREG, an 8-bit register, that
holds data that is ready for the output device.
 4.8 MARIE (5 of 14)

This is the MARIE architecture shown

graphically.
 4.8 MARIE (6 of 14)

The registers are interconnected, and connected

with main memory through a common data bus.
Each device on the bus is identified by a unique
number that is set on the control lines whenever
that device is required to carry out an operation.
Separate connections are also provided between
the accumulator and the memory buffer register,
and the ALU and the accumulator and memory
buffer register.
This permits data transfer between these devices
without use of the main data bus.
 4.8 MARIE (7 of 14)

This is the MARIE

data path shown
graphically.
 4.8 MARIE (8 of 14)

specifies the format of its instructions and the

primitive operations that the machine can
perform.

hardware and its software.

Some ISAs include hundreds of different
instructions for processing data and
controlling program execution.
The MARIE ISA consists of only 13 instructions.
 4.8 MARIE (9 of 14)

This is the format of a MARIE instruction:

The fundamental MARIE instructions are:

 4.8 MARIE (10 of 14)

This is a bit pattern for a LOAD instruction

as it would appear in the IR:

We see that the opcode is 1 and the

address from which to load the data is 3.
 4.8 MARIE (11 of 14)

This is a bit pattern for a SKIPCOND instruction as

it would appear in the IR:

We see that the opcode is 8 and bits 11 and 10 are

10, meaning that the next instruction will be
skipped if the value in the AC is greater than zero.
What is the hexadecimal representation of this instruction?
 4.8 MARIE (12 of 14)

Each of our instructions actually consists of a

sequence of smaller instructions called
microoperations.
The exact sequence of microoperations that are
carried out by an instruction can be specified using
register transfer language (RTL).
In the MARIE RTL, we use the notation M[X] to
indicate the actual data value stored in memory
location X, and to indicate the transfer of bytes
to a register or memory location.
 4.8 MARIE (13 of 14)

The RTL for the LOAD instruction is:

MAR X
MBR M[MAR]
AC MBR

Similarly, the RTL for the ADD instruction is:

MAR X
MBR M[MAR]
AC AC + MBR
 4.8 MARIE (14 of 14)

Recall that SKIPCOND skips the next

instruction according to the value of the AC.
The RTL for this instruction is the most
complex in our instruction set:
If IR[11 - 10] = 00 then
If AC < 0 then PC PC + 1
else If IR[11 - 10] = 01 then
If AC = 0 then PC PC + 1
else If IR[11 - 10] = 10 then
If AC > 0 then PC PC + 1
4.9 Instruction Processing (1 of 7)

The fetch-decode-execute cycle is the series of steps

that a computer carries out when it runs a program.
We first have to fetch an instruction from memory,
and place it into the IR.
Once in the IR, it is decoded to determine what
needs to be done next.
If a memory value (operand) is involved in the
operation, it is retrieved and placed into the MBR.
With everything in place, the instruction is
executed.
The next slide shows a flowchart of this process.
4.9 Instruction Processing (2 of 7)
4.9 Instruction Processing (3 of 7)

All computers provide a way of interrupting the

fetch-decode-execute cycle.
Interrupts are asynchronous and indicate some
type of service is required.
Interrupts occur when:
A user break (e.g., Control+C) is issued
I/O is requested by the user or a program
A critical error occurs
Interrupts can be caused by hardware or software.
Software interrupts are also called traps.
4.9 Instruction Processing (4 of 7)

Interrupt processing involves adding

another step to the fetch-decode-execute
cycle as shown below.
4.9 Instruction Processing (5 of 7)
4.9 Instruction Processing (6 of 7)

For general-purpose systems, it is common to

disable all interrupts during the time in which
an interrupt is being processed.
Typically, this is achieved by setting a bit in the
flags register.
Interrupts that are ignored in this case are
called maskable.
Nonmaskable interrupts are those interrupts
that must be processed in order to keep the
system in a stable condition.
 4.9 Instruction Processing (7 of 7)

Interrupts are very useful in processing I/O.

However, interrupt-driven I/O is complicated, and is
beyond the scope of our present discussion.
We will look into this idea in greater detail in Chapter 7.
MARIE, being the simplest of simple systems, uses a
modified form of programmed I/O.
All output is placed in an output register (OutREG)
and the CPU polls the input register (InREG) until
input is sensed, at which time the value is copied into
the accumulator.