Chapter 5

A Closer Look at
Instruction Set
Architectures
 Objectives

Understand the factors involved in

instruction set architecture design.
Gain familiarity with memory addressing
modes.
Understand the concepts of instruction-
level pipelining and its affect upon
execution performance.
 5.1 Introduction
This chapter builds upon the ideas in Chapter
4.
We present a detailed look at different
instruction formats, operand types, and
memory access methods.
We will see the interrelation between
machine organization and instruction formats.
This leads to a deeper understanding of
computer architecture in general.
5.2 Instruction Formats (1 of 31)
Instruction sets are differentiated by the
following:
Number of bits per instruction.
Stack-based or register-based.
Number of explicit operands per instruction.
Operand location.
Types of operations.
Type and size of operands.
5.2 Instruction Formats (2 of 31)

Instruction set architectures are measured

according to:
Main memory space occupied by a program.
Instruction complexity.
Instruction length (in bits).
Total number of instructions in the instruction
set.
5.2 Instruction Formats (3 of 31)
In designing an instruction set, consideration
is given to:
Instruction length.
Whether short, long, or variable.
Number of operands.
Number of addressable registers.
Memory organization.
Whether byte- or word addressable.
Addressing modes.
Choose any or all: direct, indirect or indexed.
5.2 Instruction Formats (4 of 31)
Byte ordering, or endianness, is another major
architectural consideration.
If we have a two-byte integer, the integer may
be stored so that the least significant byte is
followed by the most significant byte or vice
versa.
In little endian machines, the least significant byte
is followed by the most significant byte.
Big endian machines store the most significant
byte first (at the lower address).
5.2 Instruction Formats (5 of 31)

As an example, suppose we have the

hexadecimal number 0x12345678.
The big endian and small endian
arrangements of the bytes are shown
below.
5.2 Instruction Formats (6 of 31)
A larger example: A
computer uses 32-
bit integers. The
values 0xABCD1234,
0x00FE4321, and
0x10 would be
stored sequentially
in memory, starting
at address 0x200 as
here.
5.2 Instruction Formats (7 of 31)
Big endian:
Is more natural.
The sign of the number can be determined by looking
at the byte at address offset 0.
Strings and integers are stored in the same order.
Little endian:
Makes it easier to place values on non-word
boundaries.
Conversion from a 16-bit integer address to a 32-bit
integer address does not require any arithmetic.
5.2 Instruction Formats (8 of 31)
The next consideration for architecture design
concerns how the CPU will store data.
We have three choices:
1. A stack architecture
2. An accumulator architecture
3. A general purpose register architecture
In choosing one over the other, the tradeoffs
are simplicity (and cost) of hardware design
with execution speed and ease of use.
5.2 Instruction Formats (9 of 31)
In a stack architecture, instructions and operands
are implicitly taken from the stack.
A stack cannot be accessed randomly.
In an accumulator architecture, one operand of a
binary operation is implicitly in the accumulator.
One operand is in memory, creating lots of bus traffic.
In a general purpose register (GPR) architecture,
registers can be used instead of memory.
Faster than accumulator architecture.
Efficient implementation for compilers.
Results in longer instructions.
5.2 Instruction Formats (10 of 31)
Most systems today are GPR systems.
There are three types:
Memory-memory where two or three operands
may be in memory.
Register-memory where at least one operand
must be in a register.
Load-store where no operands may be in memory.
The number of operands and the number of
available registers has a direct affect on
instruction length.
5.2 Instruction Formats (11 of 31)
Stack machines use one - and zero-operand
instructions.
LOAD and STORE instructions require a single
memory address operand.
Other instructions use operands from the stack
implicitly.

top element.
Binary instructions (e.g., ADD, MULT) use the top
two items on the stack.
5.2 Instruction Formats (12 of 31)
Stack architectures require us to think about
arithmetic expressions a little differently.
We are accustomed to writing expressions
using infix notation, such as: Z = X + Y.
Stack arithmetic requires that we use postfix
notation: Z = XY+.
This is also called reverse Polish notation,
(somewhat) in honor of its Polish inventor, Jan
Lukasiewicz (1878 1956).
5.2 Instruction Formats (13 of 31)

The principal advantage of postfix notation

is that parentheses are not used.
For example, the infix expression,
Z = (X + Y) (W + U)
becomes:
Z = X Y + W U +
in postfix notation.
5.2 Instruction Formats (14 of 31)

Example: Convert the infix expression (2+3)

6/3 to postfix:
5.2 Instruction Formats (15 of 31)

Example: Convert the infix expression (2+3)

6/3 to postfix:
5.2 Instruction Formats (16 of 31)

Example: Convert the infix expression (2+3)

6/3 to postfix:
5.2 Instruction Formats (17 of 31)

Example: Use a stack to evaluate the

postfix expression 2 3 + 6 3 / - :
5.2 Instruction Formats (18 of 31)

Example: Use a stack to evaluate the

postfix expression 2 3 + 6 3 / - :
5.2 Instruction Formats (19 of 31)

Example: Use a stack to evaluate the

postfix expression 2 3 + 6 3 / - :
5.2 Instruction Formats (20 of 31)

Example: Use a stack to evaluate the

postfix expression 2 3 + 6 3 / - :
5.2 Instruction Formats (21 of 31)

Example: Use a stack to evaluate the

postfix expression 2 3 + 6 3 / - :
5.2 Instruction Formats (22 of 31)
Let's see how to evaluate an infix expression
using different instruction formats.
With a three-address ISA, (e.g., mainframes),
the infix expression,
Z = X Y + W U
might look like this:
MULT R1,X,Y
MULT R2,W,U
ADD Z,R1,R2
5.2 Instruction Formats (23 of 31)
In a two-address ISA, (e.g., Intel, Motorola), the
infix expression,
Z = X Y + W U
might look like this:
LOAD R1,X
MULT R1,Y
LOAD R2,W
MULT R2,U Note: One-address
ADD R1,R2 ISAs usually require
STORE Z,R1 one operand to be a
register.
5.2 Instruction Formats (24 of 31)
In a one-address ISA, like MARIE, the infix expression,
Z = X Y + W U
looks like this:
LOAD X
MULT Y
STORE TEMP
LOAD W
MULT U
ADD TEMP
STORE Z
5.2 Instruction Formats (25 of 31)
In a stack ISA, the postfix expression,
Z = X Y W U +
might look like this:
PUSH X
PUSH Y
MULT Would this program require
PUSH W more execution time than the
PUSH U corresponding (shorter)
MULT program that we saw in the
ADD 3-address ISA?
POP Z
5.2 Instruction Formats (26 of 31)
We have seen how instruction length is
affected by the number of operands
supported by the ISA.
In any instruction set, not all instructions
require the same number of operands.
Operations that require no operands, such as
HALT, necessarily waste some space when
fixed-length instructions are used.
One way to recover some of this space is to
use expanding opcodes.
5.2 Instruction Formats (27 of 31)
A system has 16 registers
and 4K of memory.
We need 4 bits to access
one of the registers. We
also need 12 bits for a
memory address.
If the system is to have
16-bit instructions, we
have two choices for our
instructions:
5.2 Instruction Formats (28 of 31)

If we allow the length of the opcode to

vary, we could create a very rich instruction
set:
5.2 Instruction Formats (29 of 31)
Example: Given 8-bit instructions, is it possible
to allow the following to be encoded?
3 instructions with two 3-bit operands
2 instructions with one 4-bit operand
4 instructions with one 3-bit operand
We need:
3 23 23 = 192 bits for the 3-bit operands
2 24 = 32 bits for the 4-bit operands
4 23 = 32 bits for the 3-bit operands
Total: 256 bits.
5.2 Instruction Formats (30 of 31)

With a total of 256 bits required, we can

exactly encode our instruction set in 8 bits!
We need:
3 23 23 = 192 bits for the 3-bit operands
2 24 = 32 bits for the 4-bit operands
4 23 = 32 bits for the 3-bit operands
Total: 256 bits.
One such encoding is shown on the next slide.
5.2 Instruction Formats (31 of 31)