ITC-CSCC2022 634

Optimizing Design Power Integrity

using IR-Aware Placement
2022 37th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC) | 978-1-6654-8559-3/22/$31.00 ©2022 IEEE | DOI: 10.1109/ITC-CSCC55581.2022.9894858

Johannah Mae Abestano Olga Joy Gerasta

Microelectronics Laboratory Microelectronics Laboratory
Mindanao State University-Iligan Institute of Technology Mindanao State University–Iligan Institute of Technology
Iligan City, Philippines Iligan City, Philippines
[email protected] [email protected]

Jefferson Hora Melvin Joey de Guzman

Microelectronics Laboratory Physical Design Team
Mindanao State University-Iligan Institute of Technology Lattice Semiconductor (PH) Corporation
Iligan City, Philippines Muntinlupa City, Philippines
[email protected] [email protected]

Abstract—As the IC technology advances, voltage drop aggressors technique, but only to a limited extent; such timing
becomes increasingly significant in circuit performance. issues are avoided [11-12]. During the dynamic IR drop
Although detecting this problem in earlier stages is helpful, only analysis, more current would flow in the instances because
few tools are available to fix this. In this paper, the IR-drop is inputs are switching continuously. In order to mitigate high
simulated and analyzed in 90nm technology. It utilizes the IR current demand, a cell padding could be added. Cell padding
drop centric technology integrated in cadence tools. The refers to placement clearance given to standard cells. The
experimental results shows that IR drop violations is reduce by reserved space can be used for routing or insertion of
40% and 13% improvement of worst-case voltage degradation decoupling capacitors.
after the last iteration.
The approach presented in this paper is spreading
Keywords—dynamic power, hotspots, ir-aware placement, aggressors to different locations in the design. This reduces
voltage drop current requirements in the hotspot regions. Then a refine
placement process is performed to reduce the worst IR drop of
I. INTRODUCTION the chip. The technique of adding cell padding to high-current
As we push through lower technology nodes in IC design, density instances has also been integrated, utilizing Cadence's
transistor size reduces with narrower metal lines. Thinner built-in IR-aware placement algorithm. IR-drop results
metal wires do not only increase wire resistance but also create generated from Voltus are utilized in Innovus during the refine
localized voltage drops within the power grid, leading to the placement to reduce the number of IR-drop violations in the
decreased power supply voltage at cells and transistors. These design.
localized drops in the power supply voltage lead to
functionality failure of the device [1]. The framework of this paper is organized as follows:
Section II discusses the flow of analysis. Section III elaborates
Excessive IR-drop may weaken CMOS devices' driving on the IR-aware placement methodology. Section IV is the
capability and leave a smaller noise margin for signal detailed results of this work. Finally, the conclusion is given
transition [2]. According to the reference [3], a 5% reduction in Section V.
in supply voltage can impede circuit performance by 15% or
more. There are two forms of IR drop: static and dynamic. The II. THE DESIGN FLOW
static IR drop is determined by the overall peak current of the The IR-aware placement flow is performed using the
device. On the other hand, dynamic IR Drop is caused by Innovus and Voltus tools. In the Innovus cockpit, a post-
localized currents in a local region. Even if the design meets routed database is loaded. The database is generated after
the static IR drop criteria, it may still exhibit the dynamic IR performing the following stages: synthesis, floor planning,
drop hotspots [4]. As a result, designers performed Engineer placement, clock tree synthesis, and routing. Fig. 1 highlights
Change Order (ECO) to relocate these hotspots during sign- the necessary inputs for each stage in the design flow.
off.
Groups of high-power drivers in the same power area that
switch synchronously drain power from the power rail and
generate transient IR drops in certain locations. One of the key
responsibilities of power integrity analysis is to identify IR
drops above a threshold. Several studies have been conducted
to analyze voltage drop-aware placement [5-9]. The
traditional technique in fixing IR-drop issues is adding
decoupling capacitors near the aggressor [10], but this can Fig. 1. Requirements for IR-aware Placement Flow
become less effective in advanced nodes. Another technique
is spreading aggressors to different locations. However, it may After ensuring that the needed files are available, it is
have routing issues if the displacement is very large. followed by setting up the environment for dynamic power
Cadence's digital IC design feature uses the spreading of and rail mode. Perform power and rail analysis, hotspot

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 ITC-CSCC2022 635

identification, and refine placement. Fig. 2 shows that after but it is slightly higher than the traditional IR-aware placement
checking for IR Drop violations if there are still some critical flow.
violations, another iteration of IR aware placement is
performed, which is followed by IR Drop analysis.

Fig. 3. Number of Violating Instances per Iterations

Fig. 2. Innovus Flow

III. VOLTAGE DEGRADATION AWARE PLACEMENT

Voltage Drop-aware analysis can be done base on the
dynamic power and rail analysis. It can be generated either by
logic simulation or by utilizing timing window information.
Dynamic analysis, unlike static analysis, uses peak currents as
the basis for analysis, allowing you to examine finer time
variations in currents across a clock cycle. The goal of IR Fig. 4. Comparison of Violating Instances
Aware Placement analysis is to disperse high IR drop
instances away from hotspots in order to reduce IR drop. This The hotspots highlighted in Fig. 5 show that after IR drop-
can be done at any stage of place-and-route flow after the aware placement, aggressors are displaced in nearby rows.
detail placement. It is a refinement of the existing placement,
which can be done with multiple iterations as needed.
The flow starts by running the dynamic power and rail
analysis. The Voltus tool divides the design into regions with
the hotspots and identifies the worst instances in those
hotspots. The number of regions and instances to report can
be specified by the designer. There are region-based reports
for each area that identify the instances with the worst IR
drops, as well as their layer-based and net-based IR drop
values. In the traditional flow, we set the IR-drop aware
placement effort to medium. This means that the tool moves
the IR violating instances in both vertical and horizontal
directions. The aggressor has higher priority than other
instances during legalization. A higher value of the worst
instance will result in more instance movement, whereas a
lower value will result in less instance movement.
For the new method, the IR drop aware placement effort is
still set to medium. An additional current density feature is
added to the algorithm. It restricts the number of padded
instances by using the Voltus debug report. IR critical
instances with the current density value higher than the
specified value get padded. In this study, the current density
threshold is 0, which means it enables padding on all hot Fig. 5. Comparison of the IR Map
instances.
In the first iteration below, the worst IR drop of the design
IV. RESULTS AND DISCUSSION with cell padding is slightly smaller than the traditional
Multiple iterations are needed to converge the results in method. Both methods show improvement in the second
the design. This study runs three iterations, as shown in Fig. iteration. However, in the third iteration, traditional IR-aware
3. As depicted in Fig. 4, the design initially has 2560 violating flow worsens while using the cell padding technique has much
instances. After performing IR-aware placement, it reduces to better results.
1534 instances. We can still observe a reduction of violating
instances from our original design by applying cell padding,

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 ITC-CSCC2022 636

TABLE I. WORST DYNAMIC IR DROP Conference on Computer Design: VLSI in Computers and Processors,
vol. 2005, pp. 437–443, October 2005.
Without
Iteration With padding [3] J.-S. Yim, S.-O. Bae, and C.-M. Kyung. A floorplan-based planning
padding
409 mV methodology for power and clock distribution. In ASICs. In Proc. of
First 408 mV
DAC, June 1999.
Second 388 mV 374 mV
507 mV [4] X. X. Huang, H. C. Chen, S.W. Wang, I. H.R. Jiang, Y. C. Chou, C. H.
Third 354 mV
Tsai, “Dynamic IR-drop ECO optimization by cell movement with
current waveform staggering and machine learning guidance,” In
IEEE/ACM International Conference on Computer-Aided Design,
The total power was measured to be 3.146mW, as shown Digest of Technical Papers, ICCAD (Institute of Electrical and
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In this paper, the use of cell padding with an IR-aware 2021.
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