Xyce™ Parallel Electronic Simulator

Version 7.7 Release Notes

Sandia National Laboratories

August 3, 2023

The Xyce™ Parallel Electronic Simulator has been written to support the simulation needs of Sandia
National Laboratories’ electrical designers. Xyce™ is a SPICE-compatible simulator with the ability to solve
extremely large circuit problems on large-scale parallel computing platforms, but also includes support for
most popular parallel and serial computers.
For up-to-date information not available at the time these notes were produced, please visit the Xyce™
web page at http://xyce.sandia.gov.

Contents
New Features and Enhancements 2

Defects Fixed in this Release 4

Supported Platforms 7

Xyce Release 7.7 Documentation 7

External User Resources 8

1
Highlights
• Xyce now handles local variation with the same netlist convention as HSPICE and other simulators.
This allows users to more easily simulate things like mismatch using commercial PDKs.

• The parser, expression library and device package have undergone various efficiency improvements
with respect to parameter handling. In the case of the parser, this speeds up parsing in many cases. For
the device package, it speeds up analysis. In the case of the expression library, it often speeds up both
parsing and analysis.

New Features and Enhancements

New Devices and Device Model Improvements
• The Xyce diode now supports sidewall effects supported by other simulators such as ngspice and
HSPICE.

• The open source version of Xyce now includes the published version of EKV MOSFET model version
2.6 as the level 260 MOSFET. Previously, this model was only available in our “non free” binaries.

Enhanced Solver Stability, Performance and Features

• The expression library TABLE and SPLINE operators now support a “downsampling” feature, in which
the user can request that a large data file can automatically have the number of points used by the
source reduced. For TABLE based sources, which are based on a PWL linear approximation, this can
dramatically speed up simulations, as the number of required breakpoints is reduced.

• The random operators in the expression library (such as AGAUSS and AUNIF) now support implicit
local and global variation, consistent with other simulators.

• Parameter handling in the parser has been refactored. As a result, the parsing and setup time for large
process design kits (PDKs) has been improved.

Interface Improvements
• Subcircuit multipliers (M=) previously had to have a fixed value. Now, they can be treated like any
other parameter, and can change during a simulation using commands such as .STEP.

• Formatting errors in unused subcircuit definitions (.SUBCKT) will no longer emit errors, only warn-
ings. This is limited to issues in the (.SUBCKT) line of the netlist. If additional parsing issues are found
within the subcircuit definition, they may still result in an error being emitted from the simulator.

• Xyce now has a diagnostic option, .options diagnostic to aid in debugging of user circuits. This
option can be used to output nodes with extreme solution values, voltages, currents and discontinuities
during a simulation. Additionally, it can provide information on continuation methods used during the
DC Operating point calculation. See the Reference Guide section 2.1.25.2 and chapter 10 the User’s
Guide for more details.

• The third argument (num sigma) to the random expression operators AGAUSS and GAUSS is now op-
tional.

2
 • The metrics tracking and reporting feature now has an option to include error messages. When en-
abled, the tracking data reported by Xyce is encoded as a JSON string. If certain error conditions
occur, the JSON string may now include a list of diagnostic messages. These error messages will
be encoded as an array under the tag name “ErrorMessages” next to the “audit” field (e.g. “au-
dit”:{. . . },”ErrorMessages”:[. . . ]).

• Expressions are now allowed on the following analysis lines: .TRAN, .DC and .AC.

• Data files read in via the expression library operators such as TABLE and TABLEFILE can now contain
comments.

• Data files read in via the expression library operators such as TABLE and TABLEFILE can now include
dashes in the filename.

• When running a frequency domain analysis such as .HB or .AC, complex-valued expressions on the
.PRINT line will now automatically output both the real and imaginary parts.

• .params can now be complex-valued. When used in a real-valued context, only the real part will be
used, but in complex (i.e. frequency domain) contexts, complex arithmetic is performed.

XDM
• Fixed bug where an instance of a SPECTRE device is not translated as an instance or a comment if it
appears after a definition of a SPECTRE device.

3
Defects Fixed in this Release

Table 1: Fixed Defects. The Xyce team has multiple issue trackers, and the table below indicates fixed issues by
indentifying both the tracker and the issue number. Further, some issues are reported by open source users on
GitHub and these issues may be tracked using multiple issue numbers.
Defect Description
Xyce Project Backlog/106: Xyce/ADMS would emit code that would not compile if a
Xyce/ADMS generates incorrect Verilog-A module tried to assign a probe-dependent expression
derivative code for integer variables into an integer variable.
The Xyce diode now supports an instance parameter for the
junction perimeter (PJ) and a number of model parameters
Xyce Project Backlog/157: Xyce
(JSW, NS, CJSW, PHP, MJSW, FCS) supporting the effects.
diode does not support sidewall
Default values are such that the feature is disabled. This brings
effects
the Xyce level 1 and 2 diodes into agreement with other
simulators when these parameters are specified.
This task was related to backlog isssue 494. In the initial
Xyce Project Backlog/492: implementation of subcircuit multipliers, they were
Subcircuit multiliplier parameters constrained to have fixed values. However, in some cases a
(M) need to be handled as an AST user may wish to change multiplier values during a simulation.
(enabling .STEP to be applied to To enable this feature, the subcircuit multiplier parameters had
subcircuit M) to be part of the same abstract syntax tree (AST) as other
parameters from the netlist. This has been fixed.
The subcircuit multiplier parameter, M, is treated as a special
Xyce Project Backlog/494: case in the Xyce parser. Due to its special treatment, the use
Remove parser error trap for using case of setting this parameter via a mutable parameter (i.e.
.global param on the implicit .global param ) did not work correctly. This has been fixed.
subcircuit multiplier parameter (M) This issue did not apply to device multipliers, just to subcircuit
multipliers.
When Xyce/ADMS was refactored to remove use of Sacado, a
bit of templated code was not rewritten because it appeared to
Xyce Project Backlog/527:
be good enough for the new implementation. But that version
Xyce/ADMS aborts on analog
had a restriction that all arguments of an analog function must
functions that have arguments of a
have the same type as the return value. This code has now been
type different from their return
rewritten. Analog functions can now return either reals or
types
integers, and may have arguments of either type irrespective of
their return type.
Due to the way Xyce/ADMS implements $strobe,
$bound step, and other statements that look like function calls
and how it implements analog functions themselves, these
Xyce Project Bugs/36:
“callfunctions” cannot be used inside analog functions. Until
Xyce/ADMS aborts when an analog
this release, trying to call $strobe from inside an analog
function calls $strobe, $bound step,
function would cause ADMS to abort with a fatal error about a
or other “callfunction”
missing template. Now it will emit a warning that the usage is
not implemented, but will simply ignore the callfunction and
generate otherwise functional code.
A mistake in the code for generating analog function
Xyce Project Bugs/35: derivatives caused any analog function that used ceil or floor to
Xyce/ADMS does not allow ceil abort processing of an entire Verilog-A model. This mistake
and floor in analog functions has been fixed and now ceil and floor can be used inside analog
functions

4
Table 1: Fixed Defects. Note that we have two multiple issue tracking systems for Sandia Users. SON and SRN refer to
our legacy open- and restricted-network Bugzilla system, and Gitlab refers to issues in our gitlab repositories.
Defect Description
Sensitivity analysis in Xyce can optionally scale sensitivity
Xyce Project Bugs/27: Transient values by p/100, where p is the original value of the sensitivity
adjoint sensitivity doesn’t correctly parameter. This particular capability was never implemented
handle scaling for transient adjoints, which was an oversight. This has been
fixed.
Xyce Project Backlog/534: Xyce
needs to remove deprecated
These features have been replaced with C++17 compliant
features in C++17, like
features.
std::binary function() and
std::unary function().
Xyce Project Backlog/565: Fix
Piecewise-linear sources were not instrumented to be updated
VPWL/IPWL independent sources
during .STEP loops. This has been fixed.
to work with .STEP
The breakpoint functions in the expression library were not
Xyce Project Backlog/566:
properly reset at the beginning of each .STEP iteration. This
Expression library breakpoint
was causing breakpoints to be overlooked early in the
handling has a problem with .STEP
transient. This has been fixed.
This issue was inspired by backlog issues 565 and 566. If a
PWL source is specified using a Bsrc and the TABLE operator
Xyce Project Backlog/575:
(instead of a PWL source), then it was very inefficient if the
Expression tables are inefficient
table was large and the entries of that table were based on
when they are large and contain
expressions rather than pure numbers. This was because the
expressions
subordinate expressions in the table were being updated too
frequently. This has been fixed.
When invoked from a Bsrc, the expression library has to
provide derivatives as well as function evaluations. In the Bsrc,
the needed derivatives are with respect to solution variables,
which are usually voltage nodes. When a Bsrc is inside of a
Xyce Project Bugs/41: Expression subcircuit, it is possible that the original expression contains
library inconsistently handles voltage node dependencies that will need to be replaced with
subcircuit nodes for derivatives the subcircuit instance nodes. When this happens, the new list
of nodes might include a duplicate or ground node, even if the
original version did not. The expression library wasn’t
handling this use case (new duplicates) correctly, and this
caused a memory error. This has been fixed.
There was a bug in the parser in the function that resolved
Xyce Project Bugs/54: subcircuit
subcircuit parameters. When subcircuit instance parameters
parameters incorrectly deleted
(from the X line) matched a parameter in the list of unresolved
when multiple subcircuit instances
parameters in the subcircuit definition, that parameter was
(X lines) refer to same subcircuit
incorrectly being erased from the definition container. This has
definition
been fixed.
When Xyce cannot take the first transient step out of a DC op,
it incorrectly reported that Xyce reaches the maximum local
Xyce Project Backlog/147: The
error test failures. Xyce does not check local truncation error
handling of the first failed step out
for the first step. This has been fixed. Xyce now handles this
of a DC op was incorrect
case correctly and it also reports the time when Xyce reaches
the maximum number of failures without convergence.

5
Table 1: Fixed Defects. Note that we have two multiple issue tracking systems for Sandia Users. SON and SRN refer to
our legacy open- and restricted-network Bugzilla system, and Gitlab refers to issues in our gitlab repositories.
Defect Description
Xyce Project Backlog/595: The expression library could not tokenize a device name such
Expression library does not as V B[0]. The use of brackets and other unusual characters
recognize device names that include was allowed in other tokens such as voltage nodes. For this bug
square brackets and a bunch of only device name tokens, used in the expression library, were
other unusual (but supported) affected. This was an oversight in the expression library lexer
characters code. This has been fixed.
In the resolution of parameters in subcircuits, expressions
Xyce Project Bugs/55: Null pointer could be deleted before they were stored in parameter objects
in expression resulting in a null pointer for the expression. This issue has
been fixed.
The Python interface to Xyce was incorrectly using an ADC
Xyce Project Bugs/59:
base name when trying to get DAC devices. This has been
Mixed-Signal Segmentation Fault
fixed.
Xyce Project Bugs/60: Error The bracket operator used in a block of debugging code was
building with incorrect for use on the std::unordered map object. This code
Xyce GRAPH DEBUG=ON was fixed to use the correct accessor function for the map.
The devConMap is a data structure provided by each device
model to enable the topology package to perform the ”no DC
Xyce Project Backlog/611: The
path to ground” diagnostic. The BSIMCMG devices did not
devConMap is not implemented in
have this set up, and so circuits using these devices would
any of the BSIM CMG devices
sometimes produce spurious warning messages. This has been
fixed.
Xyce would get a segmentation fault when the netlist specified
a Bsrc that depended on the current thru another Bsrc, that
happened to be a current-source style Bsrc. Behavioral sources
can either be current or voltage sources, depending on the
Xyce Project Bugs/61: Circuit
netlist specification. When specified as a voltage source, they
causes Segfault
have an internal current variable, which is accessible by other
behavioral sources. When specified as a current source, they do
not. Xyce was not catching this mistake early enough and this
was resulting in a memory error. This has been fixed.

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Supported Platforms
Certified Support
The following platforms have been subject to certification testing for the Xyce version 7.7 release.

• Red Hat Enterprise Linux® 7, x86-64 (serial and parallel)

• Microsoft Windows 10® , x86-64 (serial)

• Apple® macOS, x86-64 (serial and parallel)

Build Support
Though not certified platforms, Xyce has been known to run on the following systems.

• FreeBSD 12.X on Intel x86-64 and AMD64 architectures (serial and parallel)

• Distributions of Linux other than Red Hat Enterprise Linux 6

• Microsoft Windows under Cygwin and MinGW

Xyce Release 7.7 Documentation

The following Xyce documentation is available on the Xyce website in pdf form.

• Xyce Version 7.7 Release Notes (this document)

• Xyce Users’ Guide, Version 7.7

• Xyce Reference Guide, Version 7.7

• Xyce Mathematical Formulation

• Power Grid Modeling with Xyce

• Application Note: Coupled Simulation with the Xyce General External Interface

• Application Note: Mixed Signal Simulation with Xyce 7.2

Also included at the Xyce website as web pages are the following.

• Frequently Asked Questions

• Building Guide (instructions for building Xyce from the source code)

• Running the Xyce Regression Test Suite

• Xyce/ADMS Users’ Guide

• Tutorial: Adding a new compact model to Xyce

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External User Resources
• Website: http://xyce.sandia.gov

• Google Groups discussion forum: https://groups.google.com/forum/#!forum/xyce-users

• Email support: [email protected]

• Address:
Electrical Models and Simulation Dept.
Sandia National Laboratories
P.O. Box 5800, M.S. 1177
Albuquerque, NM 87185-1177

Sandia National Laboratories is a multimission laboratory managed and operated by National Technology
and Engineering Solutions of Sandia, LLC, a wholly owned subsidiary of Honeywell International, Inc., for
the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA0003525.

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