Unification of Partitioning, Placement and Floorplanning

Saurabh N. Adya Shubhyant Chaturvedi Jarrod A. Roy, David A.

Synplicity Inc. Advanced Micro Devices Papa, lgor L. Markov
600 W. California Ave. Austin, TX, 78741 University of Michigan
Sunnyvale, CA 95054 shubhyant.chaturvedi@~d.eom EECS Department
saurabhesynplicity.com Ann Arbor, MI 48109-2122
{royj,iamyou,imarkov) @umich.edu

ABSTRACT local and global wires.

Large macro blocks, pre-designed datapaths, embedded memories Automated placement of embedded memories, 1P blocks and data-
and analog blocks are increasingly used in ASIC designs. How- paths can improve time-to-market by quickly generating many high-
ever, robust algorithms for large-scale placement of such designs quality layout scenarios, from which experienced designers can se-
have only recently been considered in the literature, and improve- lect smaller candidate sets, using their domain knowledge. While
ments by over 10% per paper are still common. Large macros can there can be hundreds of large placeable circuit blocks, ideal block
be handled by traditional floorplanning, but are harder t o account fol locations can also be influenced by millions of small standard cells,
in min-cut and analytical placement. On the other hand, traditional Accounting for this effect is often beyond human capabilities and is
floorplanning techniques do not s c d e to large numbers of objects, difficult in classical methodologies for automatic layout where Roor-
especially in terms of solution quality. planning and placement are performed in separate steps. Tradition-
Wepropose to integrate min-cut placement with fixed-outline 8001 ally, a circuit is firs1 partitioned. and then floorplanned with rect-
planning to solve the more general placement problem, which in- angular shapes. The macro locations are fixed, and soft blocks are
cludes cell placement, Roorplanning, mixed-size placement and achi- shaped, followed by standard-cell placement. In the past partition-
eving routability. At every step of min-cut placement, either parti- ing and floorplanning have often been used to increase the capacity
tioning or wirelength-driven. fixed-outline floorplanning is invoked. of older placement algorithms which did not scale beyond half a mil-
If the latter fails, we undo an earlier paltitioning decision, merge ad- lion movable objects. However, modem placement algorithms, and
jacent placement regions and re-floorplan the larger region to find even some of academic tools used in this work, are routinely used on
a legal placement for the macros. Empirically, this framework im- flat netlists with over four million movable objects.
proves the scalability and quality of results for traditional wirelength- From an optimization point of view, floorplanning and placement
driven floorplanning. It has been validated on recent designs with are very similar problems - both seek non-overlapping placements to
embedded memories and accounts for routability. Additionally, we minimize wirelength. They are mostly distinguished by scale and the
propose that free-shape rectilinear floorplilnning can be used with need to account for shapes in floorplanning, which calls for different
rough module-area estimates before synthesis. optimization techniques (see Table 1). Notice, however, that netlist
partitioning is often used in placement algorithms, where geometric
1, INTRODUCTION shapes of partitions can be adjusted. This considerably blurs the sep-
The amount of embedded memory used on a chip is expected to aration between partitioning. placement and floorplanning, raising
grow dramatically in the next few years [24],from around 50% of the possibility that these three steps can be performed by one CAD
the die area today to 70% by 2005, and 90% by 201 1 . This growth is tool. In this work, we develop such a tool and term the unified layout
mostly fueled by chips for high-bandwidth communication, portable optimization poorplacemenl following Steve Teig's keynote speech
multi-media, interactive consumer electronics and indusuial embed- at ISPD 2002. We concentrate on fundamental algorithm develop-
ded systems. While memories and random logic have traditionally ment and present basic empirical validation. Clearly. industrial use
been manufactured using different semiconductor processes, today will also require additional support with new methodologies. e.g.. to
most foundries offer hybrid processes that can produce reasonably allocate repeaters and optimize timing.
dense memories embedded in random logic with fast gates and so- Our implementation Capo9.Ois derivedfrom an existing standard-
phisticated interconnect 124). The use of on-chip memories substan- cell placer and can also be used as a multi-way partitioner. Added
tially improves energy-efficiency and response latency. while reduc- functionalities include (I) completely integrated mixed-size place-
ing weight, form factor and assembly costs. ment competitive with best published results. (2) wirelength-driven
Physical design with large pre-designed circuit blocks is more fixed-outline floorplanning, that outpelforms existing floorplanners
challenging than conventional standard-cell layout. While commer- by far, and (3) free-shape floorplanning that simultaneously deter-
cia1 layout tools have considerably improved in the last two years, mines locations and shapes of modules so as to optimize intercon-
the locations of large blocks are still typically determined by manual nect. Empirically. most modules are shaped as rectangles, with a
floorplanning. Perhaps, the most obvious challenge is the minimiza- noticeable fraction of L-, T- and U-shapes. However, we observe
tion of wirelength, which also affects routability. The optimization significantly smaller wirelengths and runtimes compared to purely
of wirelength is the most prevalent approach to placement and Roor- rectangular floorplans.
planning, and it enables other optimizations through the use of net One of the benchmark sets used in our empirical evaluation is
weights and bounds 112, 141. Moreover, some form of wirelength completely new and is the first to incorporate embedded memories
optimization appears necessary - a recent study [23] from Intel with complete routing information. Embedded memories often use
shows that 5 I% of dynamic power in currently-shipped microproces- only two layers of metal (aside from power suipes) and do not block
sors is consumed when driving signals over interconnects, including routing tracks at other metal layers. Therefore. our benchmarks

02004 IEEE.
0-7803-8702-3/04/$20.00 550

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 Characetirrics

Scalable runtime
Scalrble wirclcngcb

Constrains

Can optimize
otisntadon of modules
svppDn for
non-rectangular bloc*r
SYppon for
soft rectangular blocks
Handling net Weigh13
PWlili0"US

YCS
:I" YSl
(a) Block-based (b) Mixed-size
Handling lcngth b u n d s Figure 1: Layout styles. Standard-ceUlayout is shown in Figure *a).

Table 1: A comparison of e o m o n algorithms for partitioning, Awr- optimal end-case placer. To allow the partitioners to find better cuts,
planning, and placement, contrasted with what can be achieved by a Capo often shifts the cutline to accommodate an excess of circuit
unifiedfloorplnew. Published Hoorplanning algorithm awnme a par- modules in one partition. This also allows Capo to distribute the
ticular shape for each block, e.g., rectangle, L.shape or T-shape, hut available whitespace uniformly [ I I] so as to facilitate easier routing.
floorplacers may be able to automatically chwse an acceptable shape. Non-uniform distribution can be easily achieved by pre-processing
[I]. Recent enhancements are based on the concept of placement
mainly emphasize the effect of embedded memories on the place- feedback [I91 in which a given collection of bins is partitioned N
ment of standard cells and can be viewed as a minimal sanity-check times, without requiring steady improvement, to achieve more con-
for mixed-size placement. In particular, we evaluate recent work sistent terminal propagation. This change improves both wirelength
on mixed-size placement 16, 221 which relies on greedy legalization and routability. Table 2 compares routability of placements pro-
of cell macro locations through left (or right) packing. Such strate- duced by three leading min-cut placers on the IBM-Dragon (v2)
gies typically produce unroutable standard-cell placements [29, 51, benchmarks. We run Dragon 3.01 [29] in a mode where it spreads
and careful re-distribution of whitespace shown in I291 to improve whitespace according to congestion. This significantly increases
routability may be less effective with large circuit blocks present, wirelength, but produces more routable placements. As of August
due to the fragmentation of layout. More generally, it seems that 2004, FengShui I221 does not have such a mode and shifts all cells
reliable incremental modification of mixed-size layouts is more dif- to the left (or right), typically yielding unroutable placements.
ficult than that of pure standard-cell layouts. Therefore. in this work
we attempt to minimize the need for such modification. 2.2 Fixed-outline Floorplanning
The rest of the paper is structured as follows. Section 2 describes A typical flwrplanning formulation deals with a set of circuit
relevant previous work. In Section 3 we integrate Hoorplanning into modules, each characterized by area and shape type. Rectangular
partitioning-based placement. The Appendix introduces new mixed-
modules (blocks) may have varying aspect ratios (sofrblocks). This
size placement benchmarks whch are used for empirical validation is common for IP blocks available in several shapes, and for hier-
in Section 4. Section 5 concludes our paper. archical parfitions where area can be estimated before synthesis. A
2. RELEVANT PREVIOUS WORK floorplan specifies module locations and shapes such that modules
do not overlap. Classical floorplanning minimizes a linear combi-
As pointed out in [IS, 9, 31, modem hierarchical ASIC design nation of floorplan area and total net length. However, in modem
Rows are typically based on fixed-die Roorplanning, placement and design flows the Rwrplan often has a fixed outline 1181, which ac-
routing, rather than the older variable-die style. In such a flow, each centuates the minimization of wirelength, reminding of placement.
top-down step may start with a Hoorplan of prescribed aspect ratio The Hoorplanner Parquet [3. IO] performs fixed-outline Hoorplan-
and with blocks of bounded. but not always fixed, aspect ratios. ning with rectangular modules by combining Simulated Annealing
with a new mechanism for move selection, based a n the notion of
2.1 Min-cut Placement poorplan slack 131. Slackrepresents the amount of horizontal or ver-
Top-down placement algorithms seek to decompose a given place- tical space next to each block and can be computed quickly. To im-
ment instance into smaller instances by sub-dividing the placement prove the width of a Hoorplan, one must necessarily relocate a block
region, assigning modules to subregions and cutting the netlist hy- with zero horizontal slack (similarly for height). Such moves are
pergraph [9]. In this context a placement bin represents (i) a place- performed at regular time intervals during conventional Simulated
ment region with allowed module locations (sites), (ii) a collection Annealing to bias the aspect ratio of current floorplan to that of the
of circuit modules to be placed in this region, (iii) all signal nets desired outline. When the temperature schedule runs out, the final
incident to the modules in the region, and (iv) fixed cells and pins
outside the region that are adjacent to modules in the region (termi-
Circuit Capo9.0-fccdback Dragon 3.01 -fd FcngShui 2.5
nals). The top-down placement process can be viewed as a sequence routed WL I Wol routed WL 1 Wol muted WL 1 Viol
of passes where each pass examines all bins and divides some of ibmOlc 839802 0 871052 53 time-out 1351
them into smaller bins. Most commonly the division step is accom- ibmOlh 860067 147. 832928 0 tims-0~1 1736
plished with balanced min-cut partitioning that minimizes the num- ibm02c 2239345 0 2198166 200 2202910
~ ~~~~ 0
ibmO2h 2i62938 0 2215716 -0 lime-out 1722
ber of signal nets connecting modules in multiple regions. These ibm07e 4620754 0 4249798 0 iimcinlt 85
techniques leverage well-understood and scalable algorithms for hy- ibm07h 4861456 25 4643654 0 iime-ou~ 649
pergraph partitioning and typically lead to routable placements. ibmone 4750574 o 4681110 o 46609964 o
ibmO8b 4882005 0 4530017 0 timc-0nt 133116
This work uses the top-down placer Capo [91, which implements
three min-cut partitioners - optimal (branch-and-bound), middle-
range (Fiduccia-Mattheyses) and large-scale (multi-level Fiduccia-
Mattheyses). Bins with seven cells or less are processed with an

55 1

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 floorplan may not satisfy the outline. Parquet empirically achieves the top-level floorplanning stage. It affects both runtime and the
high ratios of successes to failures on fixed-outline floorplanning in- quality of wirelength optimization.
stances with 15% whitespace [3]. Parquet also supports soft blocks. The multi-level placer mPG-MS [ 131 clusters the netlist bottom-
up to build a hierarchy. The top-level coarse netlist of approximately
2.3 Mixed-size Placement 500 clusters is placed using Simulated Annealing, after which the
For the reasons outlined in the introduction, mixed-size placement netlist is gradually unclustered so as to improve the placement of
is becoming increasingly important. Much progress has been made smaller clusters by incremental annealing. All intermediate cluster
recently [ I . 2. 13.22.281. and we survey relevant algorithms below. placements in mPG-MS are non-overlapping. which is enforced with
The force-directed algorithm Kraftwerk [I51 models interconnect specially-designed data structures and yet takes considerable com-
with attraction forces and introduces additional repulsion forces be- putational effort. This and the pervasive use of Simulated Annealing
tween overlapping modules. The new module locations achieved by make mPG very slow. While mPG finds better placements than those
applying those forces are estimated by solving the Poisson equation. reported in [I], even better placements have been produced recently
which is reduced to solving large sparse systems of linear equations. by the min-cut technique below, which is also much faster.
Forces are recomputed for each new placement, and the algorithm The work in [221 advocates a two-stage approach to mixed-size
is applied until convergence. Kraftwerk is fast and can success- placement. First, the min-cut placer FengShui [61 generates an ini-
fully handle large mixed-size placement instances wirh significant tial placement for the mixed-size netlist without trying to prevent
amounts of whitespace, but often fails to resolve overlaps between all overlaps between modules. The placer only tracks the global
large modules in realistic circumstances where blocks may be diffi- distribution of area during partitioning and uses the frnctiomI cut
cult to pack [2]. In a recent empirical comparison of standard-cell technique 161. which further relaxes hook-keeping by not requiring
placers [SI Kraftwerk was outperformed by several min-cut tools. placement bins to align to cell rows. While giving min-cut partition-
Another potential shortcoming of this analytical algorithm is hav- ers more freedom, these relaxations prevent cells from being placed
ing no provisions for optimizing orientations of large modules - a in rows easily and require additional repair during detail placement.
clearly discrete optimization problem. This may particularly complicate the optimization of module orien-
MMP 1281 attempts to solve the mixed-size placement problem tations, not considered in [221 (relevant benchmarks use only square
by a bottom-up clustering of standard cells and subsequent cluster blocks with all pins placed in the centers).
placement. The placement engine is a combination of quadratic and The second stage consists of removing overlaps by a fast legalizer
min-cut techniques. It balances partition areas by shifting the cut- designed to handle large modules along with standard cells. The le-
line after each min-cut optimization. As described, the algorithm galizer is essentially greedy and attempts to shift all modules towards
assumes pre-determined orientations of all circuit modules and does the left edge of the chip (or to the right edge, if that produces better
not attempt to optimize them. No empirical comparisons to other results). In our experience, the implementation reported in [22] leads
techniques or scalability data are available. It is especially unclear if to horizontal stacking of modules and sometimes yields out-of-core
this technique can handle large, fixed-size. difficult-to-pack blocks. placements, especially when several very large modules are present
The work in [21 proposes a methodology for mixed-size placement (the benchmarks used in [221 contain numerous modules of medium
that combines floorplanning and standard-cell techniques as follows. size). Another concern about packed placements is the harmful ef-
Step 1. During pre-processing, each large module is shredded fect of such a strategy on routahility, explicitly shown in [29]. Over-
into small fake cells connected by a grid of fake wires. Pins are all, the work in I221 demonstrates very good legal placements for
propagated to shredded cells to reflect pin offsets. Assigning common benchmarks. but questions remain about the robustness and
sufficiently high weights to fake wires ensures that fake cells generality of the proposed approach to mixed-size placement. We
belonging to the same large module are placed next to each address these questions with additional benchmarking in our work.
other if the placer minimizes linear wirelength. A black-box
standard-cell placer is applied to the shredded netlist.
Step 2. Initial locations of large modules are computed by aver- 3. INTEGRATION OF PARTITIONING,
aging the locations of respective fake cells. A module is rotated PLACEMENT AND PLOORPLANNING
according to the prevailing orientation in the grid that models it. In this section we introduce our correct-by-construction approach
To remove overlaps between large modules, small cells are clus- to floorplacement, which does not rely on post-placement legaliza-
tered (bottom up, based on locations) into soft blocks to create tion procedures for large modules.
a fixed-outline floorplanning instance with 100-200 blocks.
Step 3. Non-overlapping locations of large modules are gener- 3.1 Unified Placement and Floorplanning
ated by running a fixed-outline floorplanner, e.g., Parquet [3]. We first observe that min-cut placers scale well in terms of runtime
Initial locations can be discarded, or else can be re-used with and wirelength minimization, but cannot produce non-overlapping
low-temperature annealing during floorplanning. placements of modules with a wide variety of sizes. On the other
Step 4. Large modules are fixed, and remaining soft blocks hand, annealing-based floorplanners can handle vastly different mod-
are disintegrated into original standard cells. The black-box ule shapes and sizes, but only for relatively few (100-200) modules at
standard-cell placer is called again to re-place small cells. a time. Otherwise, either solutions will be poor or optimization will
Observe that the shredding process facilitates physical (location- take too long to be practical. As explained in Section 2.3, the loose
based) clustering of small cells and thus improves final locations integration of fixed-outline floorplanning and standard-cell place-
of large modules, even if their initial locations are discarded. A ment proposed in 121 suffers from a similar drawback because its
major advantage of this methodology is its robustness - it often single top-level floorplanning step may have to operate on numer-
produces legal placements when other approaches leave large over- ous modules. Bottom-up clustering can improve the scalability of
laps or place modules out of core. It also optimizes module orien- annealing, but not sufficiently to make it competitive with other ap-
tations. This fully-automated methodology successfully competed proaches. Therefore. in this work we apply min-cut placement as
with a major commercial tool in 2002 and has been recently im- much as possible and delay explicit floorplanning until it becomes
proved by more judicious handling of whitespace [I]. Yet. the main necessary. In particular, since min-cut placement generates a slic-
scalability bottleneck remains in the use of Simulated Annealing at ing floorplan, we view it as an implicit floorplanning step, resewing

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 ~

Variables: queue of placement bins ing. Backtracking does incur some overhead in failed Roo~Qlanruns,
Initialize queue with top-level placement b i n Ibut this overhead is tolerable because mereed bins take considerably
I

1 While (queue not empty)

longer to Roorplan. Funhermore, this overhead can be moderated
2 Dequeue a bin
3 Ji (bin has largdmany macms) somewhat by careful prediction, as will be described later.
4 Cluster std-cells into soft m a c m For a given bin, a floorplanning instance is constructed as fol-
4 use fixed-autline Euurplanner tu pack lows. All connections between modules in the bin and other mod-
d l macms (wft+hard) ules are propagated to frred terminals at the periphery of the bin.
6 U h e d - a u t h e floorplanning succeeds Similar terminal propagation schemes are commonly used in some
7 Fix m a e m and remove sites underneath the macros
analytical placers [26]. As the bin may contain numerous standard
R Else
9 Undo one partition decision. Merge bin with sibling cells, we reduce the number of movable objects by conglomerating
10 Floorplan new merged bin standard cells into soft placeable blocks. This is accomplished by a
11 ~ 1 s ei f ( b i n s m a l l enough) simple bottom-up connectivity-based clustering [ZO]. The existing
12 Process end case large modules in the bin are usually kept out of this clustering. To
13 Else
14 Bi-partition the bin into Smaller b i n s
h n h e r simnlifv Roomlannina,
. I - we artificiallv downsize soft blocks
15 Enqueue each child b i n
consisting of standard cells, as in [I], because standard cells will be
placed later anyway. The clustered netlist is then passed to the ran-
Figure 2: Our Boorplacement algorithm. Bold-faced l i e s 3-10 are domized fixed-outline floorplanner Parquet, which sizes soft blocks
different from traditional min-cut placement. and optimizes block orientations. We allow at most five attempts
..
to find a non-overlamine - rrlacement
. of modules within the bin. If
explicit floorplanning for "local" non-slicing block packing. the flwrplanner is successful, the locations of all large modules are
We start with a single placement bin representing the entire lay- returned to the top-down placer and considered fixed. The rows be-
out region with all the placeable objects initialized at the center of low those modules are fractured and their sites are removed. i.e.,
the placement bin. Using min-cut partitioning, the bin is split into the modules are treated as fixed obstacles. At this point, min-cut
two bins of similar sizes, and during this process the cut-line is ad- placement resumes with a bin that has no large modules in it, but
justed according to actial partition sizes. Applying this technique has somewhat non-uniform row structure. When min-cut placement
recursively to bins (with terminal propagation) produces a series of is finished, large modules do not overlap by conswction. but small
gradually refined slicing floorplans of the entire layout region, where cells sometimes overlap in few places (typically below 0.01% by
each room corresponds to a bin.' In very small bins, all cells can be area). Those overlaps are quickly detected and removed with lo-
placed by a branch-and-bound end-case placer (81. However, this cal changes using a row-based legalizer from the GSRC bookshelf
scheme breaks down on modules that are greater than their bins. [IO]. Detailed placement uses branch-and-bound placement in slid-
When such a module appears in a bin. recursive bisection cannot ing windows [SI, but does not move the macros. Figure I(b) shows
continue, or else will likely produce a placement with overlapping a sample placement produced by our tool.
modules. Indeed, the work in [22] continues bisection and resolves
resulting overlaps later. However, in this work we switch from re- 3.2 Practical Issues
cursive bisection to "local" floorplanning where the fixed outline is Empirical boundary between placement and Roorplanning. By
determined by the bin. This is done for two main reasons: (1) to identifying the characteristics of placement bins for which our al-
preserve wirelength, congestion and delay estimates that may have gorithm calls floorplanning, one can tabulate the empirical bound-
been performed early during top-down placement [71, and ( 2 ) avoid ary between placement and floorplanning. Formulating such ad hoc
the need to legalize a placement with overlapping macros. In par- thresholds in terms of dimensions of the largest module in the bin.
ticular, we are unconvinced that existing legalization algorithms are etc allows one to avoid unnecessary backtracking and decrease the
robust enough to handle a wide variety of module shapes and sizes in overhead of floorplanning calls that fail because they are issued too
realistic netlists (see Figure 5). We also anticipate difficulty ensuring late. In practice. issuing floorplanning calls too early (i.e., on larger
routability while shifting macros and standard cells at the same time. bins) increases final wirelength and sometimes runtime. To improve
While resomng to fixed-outline floorplanning is a naNral step, wirelength, our ad hoc tests for large blocks in bins (that trigger
successful fixed-outline floorplanners have appeared only recently floorplanning) are deliberately conservative.
131. Additionally, the floorplanner may fail to pack all modules At least one module does not fit into a potential child bin.
within the bin without overlaps. As with any constraint-satisfaction
problem. this can be for two reasons: either (i) the instance is unsat- The sum of the larger dimension of the largest module and the
isfiable, or (ii) the solver is unable to find any of existing solutions. smaller dimension of the second largest module exceeds the
In this case, we undo the previous partitioning step and merge the smaller dimension of a potential child bin.
failed bin with its sibling 6in. whether the sibling has been processed There are 5 30 large modules in the bin, but their total area
or not, then discard the two bins. The merged bin includes all mod- exceeds 80% of the total area of cells and modules in the bin.
ules contained in the two smaller bins, and its rectangular outline is In our experience, these tests are g w d enough to ensure that at
the union of the two rectangular outlines. This bin is Rwrplanncd, most one level of backtracking @lock-merging) . . is required to pre-
and in the case of failure can be merged with its sibling again. The vent o\erlap, hsiacen luge rnuduler
overall process is s u m m ~ z e din Figure 2. Side-effect: Narrow vertical slivers hetnccn larrc module% Ad-
I

It is typically easier to satisfy the outline of a merged bin because jacent large modules placed by the fixed-outline floorplanner may
circuit modules become relatively smaller. However. Simulated An- have tall, narrow columns of empty sites between them. Fitting small
nealing takes longer on larger bins and is less successful in mini- cells in such slivers may be non-trivial, e.g., consider a column with
mizing wirelength. Therefore, it is imponant to floorplan at just the four sites and a collection of cells that take two or three sites each.
right time, and our algorithm determines this point by backtrack- In this case, every three-site cell implies the loss of one site. but
this loss is difficult to estimate during balanced min-cut partition-
'If every cut-line is fixed apriori to the center of its bin, recursive ing. Therefore. a traditional min-cut placer that assigns cells to bins
bisection generates a grid-like Boorplan. based only on site area may create cell overlaps in such cases. When

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 wide cells get assigned to narrow columns, they may end up overlap-
ping with macros. Since such overlaps are relatively rare. they can
be resolved by simple legalization with minimal movement, e.g.. Ca-
dence Qplace in the ECO mode. One can also identify contiguous
site sequences (sub-rows) that are shorter than existing wide cells
and mark them as used when creating a new placement bin.

3.3 Wirelength-driven Floorplanning Figure 3: Figure on left shows a free-shape floorplan of the ami33
Pure block-based designs. Since our floorplacer includes a state- benchmark. Our RoOrplacer determines bath loeations and shapes
of-the-art floorplanner 131, it can natively handle pure block-based of individual modules to minimize wirelength. ltnditional rectangu-
designs. Unlike most algorithms designed for mixed-size place- lar floorplanning with Parquet is compamd to our free-shape non-
ment, it can pack blocks into a tight outline, optimize block orienta- rectangular floorplacementon the right.
tions and aspect ratios of soft blocks. Indeed, when the number of
blocks is very small, our algorithm applies floorplanning right away. produced by our floorplacer using fake-net weights of 500. An addi-
However, when given a larger design, it may start with partition- tional benefit of our approach is its scalability, e.g.. if no hard blocks
ing and then call fixed-outline floorplanning for separate bins. This are present, everything is accomplished without Simulated Anneal-
is demonstrated in Figure I(a) which shows the block-based design ing. Figure 3(b) reports the improvement in mntime and wirelength
n 3 0 0 placed using our Aoorplacer. The cuts made by the min-cut over traditional rectangular floorplanning with Parquet on a mix of
partitioner are clearly seen making the resulting floorplan globally MCNC and GSRC floorplanning benchmarks. For larger designs,
slicing, but locally non-slicing. Since recusrive bisection scales well wirelength is reduced by more than 50%. We expect that this new
and is more successful at minimizing wirelength than annealing- type of free-shape floorplanning can be useful before logic synthe-
based floorplanning, the proposed approach is scalable and effective sis to determine relative locations of large modules and enable early
at minimizing wirelength. This expectation is fully confirmed by estimates of signal delays in global interconnect.
empirical results in Section 4.
Free-shape rectilinear Roorplanning. Some circuit modules, such 4. EMPIRICAL VALIDATION
as embedded memories and pre-designed datapaths, have fixed rect- In earlier sections we demonstrate the effectiveness of our pro-
angular shapes. However, when only the area of a module is esti- posed Aoorplacer in large-scale congestion-driven standard cell place-
mated, but its shape is unknown, there is often no a priori reason ment and free-shape floorplacement. Below we validate our tool on
to limit its shape to rectangles. Such limitations may be justified by designs with hard blocks and on mixed-size placement instances.
added efficiency in handling rectangular blocks, but can handicap
interconnect optimization. Non-rectangular floorplanning has been 4.1 Results on Floorplanning Instances
popular in several design contexts, and existing work can be clas- Table 3 compares our proposed floorplacer with the annealing-
sified by whether the floorplanner is allowed to change the shape based tool Parquet using GSRC floorplanning benchmarks [IO]. Com-
type of modules. To this end, the work in (211 and 1271 repre- parisons of other floorplanners to Parquet can be found in recent
sents simple non-rectangular shapes with Sequence Pairs (SP) and literature on flwrplanning. We first convert the benchmarks to the
Bounded Slicing Grids (BSG) to pack such modules using the popu- GSRC bookshelf format for placement using an internal converter
lar annealing-based framework. In contrast, the work in (171 solves a and generate square fixed-die layouts with 20% whitespace. Since
specific floorplanning formulation proposed in [18], which assumes area minimization is not an objective as long as we fit within the
desired locations of given rectangular modules and seeks to re-shape fixed-outline constraints, we only report half-perimeter wirelength
the modules so as to avoid overlaps. The proposed algorithm is an (HPWL) and runtimes. For the smallest three benchmarks n10,
incremental detailed floorplanner that tends to generate fairly com- 1130and n50 the two approaches perform similarly, as the floor-
plicated shapes. but does not account for interconnect. Below we placer resorts to floorplanning. However, the larger the designs, the
extend our global free-shape floorplanner to generate both locations more partitioning calls are made by the floorplacer. This results in
and shapes of soft modules so as to minimize interconnect. Empir- faster and more powerful interconnect optimization compared to the
ically, most of the modules are shaped as rectangles, but L-,T- and annealing-based Parquet tool. The improvements should be even
U-shapes are sometimes created when this helps reducing intercon- more pronounced for larger block-based designs.
nect. Our algorithm is also capable of pin placement.
Below we rely on techniques proposed in (21, where each large 4.2 Validation in Mixed-size Placement
module is pre-processed into a grid of fake cells and heavy fake Faraday Benchmarks. To validate the routability of placements
nets. Signal pins of a module are propagated to respective fake produced by Capo 9.0, we use the new benchmarks introduced in
cells. However, in our context there is no need to shred fixed-shape the Appendix. We compare our approach with Cadence Qplace (part
blocks because they are already handled by our floorplacer. Thus, we
only shred soft blocks. As in 121. heavy weights on fake neb ensure
Circuit #Blocks Parqucl Capo (Mircd-sircl
that shreds of the same module stay together during min-wirelength HPWL Time HPWL nmc (tMin-cul
placement. However. since we now allow non-rectangular shapes, sec *cc Level*
there is no need to average locations of fake cells and determine the
prevailing orientation as in (21. We simply accept module shapes as-
sumed hy f&e grids during placement. Because of the relative rigid-
ity of fake grids and because we rely on min-cut placement, most
modules assume rectangular shapes, which is convenient from many
perspectives. Other shapes are generated only when this reduces
interconnect. and they remain relatively simple. This is demon- Table 3 Flwrplnnnning versus Awrplacement. The last column 'Zev-
strated in Figure 3(a) where modules are color-coded. The plot is els" lisls the number of min-mtlevels exemted before the fimt flwrplan.
ning step. All data are averaged aver 10 independent NN.
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 Cmuii ShUltra - Qplace(v5.4.126) CapoY.0 -feedback FengShui 2.6 06'17/04
Place Route Place Route Place Route
HPWL Time WL Time Viol HPWL Time WL Time Viol HPWL Time WL lime Viol
(e8) (min) (e8) (min) (e8) (min) (e8) (min) (e8) (min) (e8) (min)

RlSCl
"Dh PZd
16.72 7
fi3-A
21.69 11
:
3
'd.2
15.75
224
21
E 6
21.50 16
7
0
Pi%
19.98/0C
P4
30
E 7
OC
'8
OC OC
DSPZ 9.98 4 12.09 6 0 9.23 9 11.12 5 0 9.28 IO 11.64 6 0
RlSC2
~~~
15.63 8 20.74 30 333 16.30 19 21.38 11 5 209.8/0C 25 OC OC OC
a b l e 4 Routing results on Faraday benchmarks. Routed WL is in database units. OC mans that a lalge number of cells and macms were
placed outside the corn a m . Best mults are bold.faced. All muting BS well as Qplace mns are performed on B 750MHzSun Blade workstation
with 2GB RAM running Solaris. Capo and FengShui mm are on B somewhat faster 2.4GHz Linur workstation with 1GB RAM. Capo is used
in the -feedback mode,which is several limes slower than the default mode. Also note that Capo performs loeai "ding-based floorplanning.

of SEUltra) and FengShui 2.6, using Cadence WarpRoute for routing hardware platform for each tool. For SEUlua, we use the Cadence-
in all cases. The results are presented in Table 4. For SEUltra, we recommended flow for mixed-size designs, which produces com-
use the Cadence-recommended flow for placing mixed-size designs pletely legal placements, unlike those reported in [Z] for the 2002
as explained in the Appendix. The placements produced by Capo version of the same tool. Also note that the wirelengths achieved by
are generally mutable on all benchmarks, sometimes with a small the latest version of SEUltra are much better than those reported in
number of violations. For the Capo results in Table 5 legalization 121. Clearly, Cadence tools have greatly improved since 2002.
by Qplace ECO was not needed, but may be necessary rarely. Feng- On the older IBM-MS benchmarks, placements produced by our
Shui 2.6 produces legal placements of henchmarks DMA, DSPl and floorplacer Capo 9.0 (with option -feedback) are on average 12.09%
DSP2, but places many cells in RISCl and RISCZ outside the core better than Cadence SEUltra, 19.6I% bener than the C-P-C Row,
area as shown in Figure 5 . Only with considerable effort Qplace 14.56% better than Capo-Kraftwerk ECO flow. 13.99% better than
ECO legalized these placements. but WarpRoute did not complete. mPG-MS and 8.09% worse than FengShui 2.6. Using the best of
IBM Netlists. The IBM Mixed-Size (IBM-MS) placement bench- two N n S of Capo 9.0 improves solution quality by 1.66%. On the
marks released at ISPD 2002 121 are derived from the well-known newer IBM-MSwPins benchmarks. in terms of HPWL, on average,
netlists made public by IBM in 1998. These benchmarks have been the placements produced by our Boorplacer are 13.74% better than
consistently used in the recent literature on mixed-size placement, Cadence SEUltra, 19.59% bener than the Capo-Parquet-Capo flow,
but have two important drawbacks: (i) all large modules are square, 17.83% better than Capo-Kraftwerk ECO flow and 5.14% worse
(ii) all pins in such modules are in the center. Therefore these bench- than FengShui 2.6. Choosing the best of two Capo 9.0 runs results in
marks give no incentive to optimize block orientations and cannot a 1.55% improvement. Note that FengShui shifts all cells to the left
be extended with routing information. To this end, the majority of (or right) edge of the chip, thus lowering wirelength compared to a
published mixed-size placers do not attempt to optimize module ori- placement spread around the core area. However, according to Table
entations. While the IBM-MS benchmarks served well to compare 2, this strategy is not always successful in the presence of large mod-
enq-level mixed-size placers, we seek more realistic evaluation. ules. Comparing results of FengShui 2.6 on two sets of benchmarks
We derive a new set of benchmarks termed IBM-MSwPins from in Table 6, we conclude that the relative advantage of FengShui 2.6
the IBM-MS placement benchmarks. Aspect ratios of large modules decreases in the presence of rectangular blocks with non-trivial pin
are chosen randomly between 0.5 and 2.0. Pins of all cells and large offsets, as it does not optimize module orientations.
modules are distributed evenly through the periphery. To determine
pin locations for individual cells and large modules, we first perform
placement with all pins centered. For every net, we determine its 5. CONCLUSIONS
center by averaging the locations of incident cells. Then, for each Our work originates from the realization that min-cut placers im-
cell and large module, pins are ordered on the periphery by the cen- plicitly perform flwrplanning, in addition to partitioning. There-
ters of their incident nets. The new IBM-MSwPins benchmarks are fore. separate partitioning and floorplanning steps traditionally used
available in the public domain [4]. in VLSI design can be subsumed by a min-cut placer. Such a uni-
We compare our proposed floorplacement approach to Cadence fication can lead to simpler, more consistent, more controllable and
Qplace (part of SEUltra), a Capo-Parquet-Capo methodology [I]. more successful EDA tools and tool chains. For example, while the
Capo followed by an incremental run of Kraftwerk (data from [21), field of floorplanning has been very active in academia for twenty
mPG-MS 1131 and FengShui 2.6 1221 using the two sets of 1BM years, there are relatively few successful commercial floorplanners.
mixed-size benchmarks. Relative performance is reported in Table 6. While this is partly due to integration difficulties and to the fact
Detailed results for the newer IBM-MSwPins benchmarks are pre- that experienced designers perform floorplanning by hand, our re-
sented in Table 7. Given that some tools are only available on the Sun sults suggest that common floorplanners based purely on Simulated
Solaris platform and others only on Intel-compatible Linux worksta- Annealing tend to produce very sub-optimal solutions. To a large
tions. runtimes are not directly comparable. However, we list the extent this is not a matter of EDA tools' lacking intangible designer
intuition, but rather the poor quality of existing algorithms with re-
spect to closed-form optimization objectives. Interconnect optimiza-
tion is also handicapped by the populu limitation that all modules
be laid out as rectangles. To this end. our work shows that unify-
ing partitioning, Boorplanning and placement in a single algorithm
leads to better layouts and facilitates new layout optimizations, such
as free-shape floorplanning that simultaneously determines the lo-
'l'dble 5: Fsrada) hmchmnrkss)mhe\imd and laid ouI uilhsrtandard cations and shapes of modules so as to optimize interconnect. Em-
,\SIc'Rov using IBA1 ,\niran 0.13pm librarics. m,hIArea mprr>mtr the pirical validation uses a unifiedjoorplncer tool, that can be used as
nmn ulembrddcd memories in p r m n t d t h c tnUI rrU am=.

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 Benchmark Suite SEUlua SEUllra Capo+ Cap- mPG FengShui[221 Capo v9.0 Capo 8.0
"5.1.67 v5.4.l26 Parquet+ Kraftwerk 1131 "2.6 06/17/04 -feedback -feedback
(2002) (2004) Capo[21 ECOLZI best-of-2
IBM-MS (ISPD2002) 92.71% 12.09% 19.61% 14.56% 13.99% -8.09% 0% -1.66%
IBM-MS wPins (new) - 13.74% 19.59% 17.83% -5.14% 0% -1.55%

- GZr-
e
Circut Ca cncc
Blak-PlacetQPlacs
SEUltra
(Low-Temp.
Annealing1 7x4
FS,

Sun-BlsdelW03SOMHz Linuflentium,ZGOHz Linuflenlium.2GHn Li""XA um.2.4GHz

I n m J

ibmOl I
17%3.25
limc
(min)
12
HPWL
(-5)
3.21
Time
(mi")
I8
HPWL
(e61
2.96
Timc
(minl
5
%
Overlap
1.22
HPWL
(e61
256
~
Time
(mi")
3
HPWL
_o
-
2.67
ibmO21 7.17 31 7.91 12 6.84 13 0.25 6.05 5 5.54
ibmO3 9.06 28 10.08 51 9.45 13 0.18 8.77 6 8.67
ibmO4 10.28 31 11.01 I2 10.09 I5 0.74 8.38 7 9.79
ibmO5 11.55 24 11.03 5 11.46 5 0 9.94 8 10.82
ibm% 8.33 32 8.70 19 9.22 19 0.25 6.99 9 7.35
ibm07 13.79 41 14.34 22 14.34 57 0.24 11.37 I2 12.30
ibmO8 17.36 50 11.01 26 17.63 22 1.80 13.51 15 16.02
ibmO9 16.91 56 19.53 29 2I.M 32 0.35 14.12 14 15.51
ibmlO 43.71 53.34 119 49.52 72 4.34 41.96 22 34.98
ibmll 24.98 86
71 2551 43 25.48 42 0.76 21.19 21 22.31
ibml2 46.38 81 54.82 97 61.48 53 0.63 40.84 22 40.78 42
91 34.30 54 32.37 71 0.12 25.45 25 28.70
148 48.66 145 47.63 117 0.07 39.93 52 40.97
206 70.68 208 62.63 I24 0.09 51.96 67 59.19 116
248 75.27 154 78.47 166 2.03 62.71 70 67.M II 5
288 87.81 204 85.40 132 0.13 69.38 79 78.78 94

- -
-
--
190 54.66 II5 57.47 162 0.02 45.59 87 50.39
19.59% 17.83% -
-5.14% 0%

Tal ~~~ .~~~~

7: Mixed-size olacement results on L e new IBM-MSwPins mixed-si- benchmarks. A aositive ~ercentaeeIn the last row indicates ~ ~~~
~~ ~ ~ ~~~~~~~~

an appmach produces placements with that much greater HPWL than Capo 9.0 on average. Cadence SEUltra places designs i b m 0 and
ibml4 illegally wiL overlaps between macros or macms outside the core a m . FengSShui 2.6 returns core placements packed to cere edges.

a partitioner, a large-scale cell placer, a floorplanner and a mixed- ASICs. We apply to these benchmarks a standard ASIC design How
size placer. Our implementation scales well, is competitive with the to generate five mixed-size designs. Faraday benchmarks include
state of the art in all of its areas of applicability, and in some cases three commonly-used functional blocks: (I)a 16-bit DSP, (ID a
produces better wirelengths than any previously reponed methods. 32-bit RJSC CPU,and (In)a DMA controller - see Table 5 for
We show that for sufficiently large floorplanning and mixed-size statistics. Other details on these benchmarks, such as the EDA tools
placement instances, min-cut techniques are more successful in min- recommended by Faraday and tool settings, can be found in 1161. To
imizing wirelength than simulated annealing. However, for small minimize the impact of routing on the results of the accounted place-
layout instances with modules of different sizes, the use of anneal- ment approaches, we avoid clock-tree generation and power routing
ing seems required to pack modules well. In the process of tuning in our Rows. However, both clock-trees and power rails can be built
the performance of our implementation, we empirically tabulate the on our benchmarks. Below we describe our ASIC flow for generat-
boundary between placement and floorplanning by identifying more ing the mixed-size benchmarks from the original netlists.
successful optimizations in various cases. A representative thresh- Faraday benchmarks come with behavioral Verilog descriptions,
old for floorplanning is currently at 30 blocks, which means that the timing constraints and scripts for synthesis. We use Artisan's 0.13
use of flat annealing on larger instances is not justified. In the future, micron libraries in IBM technology for synthesizing these designs
as floorplanners improve at satisfying fixed-outline constraints while under worst-case process conditions, with the same timing constraints
minimizing wirelength, this boundary can be lowered even further. as specified in the Faraday design documents. Synopsys Design
A floorplacer of the type described in out work can place objects Compiler (~2003.03-2)is used for synthesis, and Artisan Memory
with very different semantics -standard cells, macros, datapaths, Generator IO instantiate embedded memories. Artisan limits the size
memories, etc. Extensions to free-shape floorplanning can he used of its SRAM memories to a minimum word-length of 128 for dual-
with unsynthesized modules to better estimate global interconnect port memories and to 256 for single-port memories. This requires a
delays before synthesis. However. t o fully exploit these novel ca. change in the behavioral descriptions of Faraday designs to account
pabilities, new VLSI methodologies are required. Our hope is that for larger word-lengths. In a variation of the original design. we built
such future methodologies and methodology studies will confirm the register files in place of memories for smaller word-lengths and thus
potential of Hoorplacement. came up with two flavors each for DSP and RISC - one uses only
memories and the other uses both memories and register files.
The gate-level netlists obtained after synthesis are taken through
Appendix: Embedded-Memory Benchmarks the automatic place and route (APR) flow using Cadence Silicon
The Faraday Corporation recently released three circuits (161, origi- Ensemble Ultra (v5.4.126). We follow the Cadence recommended
nally intended for comparisons between structured and conventional flow for placing mixed-size designs and first use the "Qplace No-

556

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 (e) RISC2

Figure 4 Faraday benchmarks placed by the Capo 9.0 floorplacer. Note that Capo tends to align large blocks, which may simplify the
routing in their vicinity, BS weU ss the routing of bus%%%
comecling those blocks. The discrepancies in wirelength versus Table 4 for the same
benchmarks represent variability in Capo mulls. To show block orientations, north-west corners of memories are marked with diagonal lines.

config Block" command to place embedded memories. Then the (181 A. E. Kahng, "Classical Floorplanning Harmful?", ISPD 2000, pp.
locations of embedded memories are fixed, the affected cell sites are 207-213.
removed, and the remaining standard cells are placed using the com- 1191 A. Kahng and S. Reda, "Placement Feedback A Concept and Method
. -
mand "Onlace Nocontie". To find good - locations of U 0 Dads, we
perform concurrent pin and cell placement in Qplace. This improves
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