G522-0289-00 MPC603EC/D

(IBM Order Number) (Motorola Order Number)

1/97
REV 3

C .
IN
O R,
U CT
O ND
IC
S EM
Advance Information L E
PowerPC 603 ™ RISCE S CA
Microprocessor
E
FR
Hardware Specifications
Y B
The PowerPC 603 microprocessor
V ED is an implementation of the PowerPC™ family of
C HI
reduced instruction set computing (RISC) microprocessors. In this document, the term
‘603’ is used as anRabbreviation for the phrase, ‘PowerPC 603 microprocessor’. The
A
PowerPC 603 microprocessors are available from Motorola as MPC603 and from IBM as
PPC603. This document contains pertinent physical characteristics of the 603. For
functional characteristics refer to the PowePC 603 RISC Microprocessor User’s Manual.
This document contains the following topics:
Topic Page
Section 1.1, “Overview” 2
Section 1.3, “General Parameters” 4

603 Hardware Specifications

Section 1.4, “Electrical and Thermal Characteristics” 4
Section 1.5, “PowerPC 603 Microprocessor Pin Assignments” 14
Section 1.6, “PowerPC 603 Microprocessor Pinout Listing” 15
Section 1.7, “PowerPC 603 Microprocessor Package Description” 17
Section 1.8, “System Design Information” 21
Section 1.9, “Ordering Information” 28
Appendix A, “General Handling Recommendations for the C4-CQFP Package” 29

To locate any published errata or updates for this document, refer to the website at
http://www.mot.com/powerpc/ or at http://www.chips.ibm.com/products/ppc.

The PowerPC name, the PowerPC logotype, and PowerPC 603 are trademarks of International Business Machines Corporation, used by
Motorola under license from International Business Machines Corporation. FLOTHERM is a registered trademark of Flomerics Ltd., UK.
This document contains information on a new product under development by Motorola and IBM. Motorola and IBM reserve the right to
change or discontinue this product without notice.
© Motorola Inc., 1997. All rights reserved.
Portions hereof © International Business Machines Corporation, 1991–1997. All rights reserved.
1.1 Overview
This section describes the features of the 603 and describes briefly how those units interact.
The 603 is the first low-power implementation of the PowerPC microprocessor family of RISC
microprocessors. The 603 implements the PowerPC architecture as it is specified for 32-bit addressing,
which provides 32-bit effective (logical) addresses, integer data types of 8, 16, and 32 bits, and floating-
point data types of 32 and 64 bits (single-precision and double-precision). For 64-bit PowerPC
implementations, the PowerPC architecture provides additional 64-bit integer data types, 64-bit addressing,
and related features.
The 603 provides four software controllable power-saving modes. Three of the modes (the
N C.doze, nap, and
I by the processor.
, units
sleep modes) are static in nature, and progressively reduce the amount of power dissipated
R
TO affecting operational
The fourth is a dynamic power management mode that causes the functional in the 603 to
automatically enter a low-power mode when the functional units are idleCwithout
performance, software execution, or any external hardware. DU
N
O
The 603 is a superscalar processor capable of issuing and retiringCas
I many as three instructions per clock.
Mhowever, the 603 makes completion appear
SE
Instructions can execute out of order for increased performance;

LE
sequential.
The 603 integrates five execution units—an integer A
C unit (IU), a floating-point unit (FPU), a branch
E S
E
processing unit (BPU), a load/store unit (LSU), and a system register unit (SRU). The ability to execute five
FR instructions with rapid execution times yield high efficiency
instructions in parallel and the use of simple
B
and throughput for 603-based systems. Y Most integer instructions execute in one clock cycle. The FPU is
ED
pipelined so a single-precision multiply-add instruction can be issued every clock cycle.
V
HI on-chip, 8-Kbyte, two-way set-associative, physically addressed caches for
The 603 provides independent
C
instructions and dataRand on-chip instruction and data memory management units (MMUs). The MMUs
A
contain 64-entry, two-way set-associative, data and instruction translation lookaside buffers (DTLB and
ITLB) that provide support for demand-paged virtual memory address translation and variable-sized block
translation. The TLBs and caches use a least recently used (LRU) replacement algorithm. The 603 also
supports block address translation through the use of two independent instruction and data block address
translation (IBAT and DBAT) arrays of four entries each. Effective addresses are compared simultaneously
with all four entries in the BAT array during block translation. In accordance with the PowerPC architecture,
if an effective address hits in both the TLB and BAT array, the BAT translation takes priority.
The 603 has a selectable 32- or 64-bit data bus and a 32-bit address bus. The 603 interface protocol allows
multiple masters to compete for system resources through a central external arbiter. The 603 provides a
three-state coherency protocol that supports the exclusive, modified, and invalid cache states. This protocol
is a compatible subset of the MESI (modified/exclusive/shared/invalid) four-state protocol and operates
coherently in systems that contain four-state caches. The 603 supports single-beat and burst data transfers
for memory accesses; it also supports both memory-mapped I/O and direct-store addressing.
The 603 uses an advanced, 3.3-V CMOS process technology and maintains full interface compatibility with
TTL devices.

2 603 Hardware Specifications

1.2 Features
This section summarizes features of the 603’s implementation of the PowerPC architecture. Major features
of the 603 are as follows:
• High-performance, superscalar microprocessor
— As many as three instructions issued and retired per clock
— As many as five instructions in execution per clock
— Single-cycle execution for most instructions
— Pipelined FPU for all single-precision and most double-precision operations
C .
• Five independent execution units and two register files IN
— BPU featuring static branch prediction O R,
— A 32-bit IU U CT
ND
CO
— Fully IEEE 754-compliant FPU for both single- and double-precision operations
I
M and FPRs
— LSU for data transfer between data cache and GPRs
E
— SRU that executes condition register (CR) andSspecial-purpose register (SPR) instructions
E
— Thirty-two GPRs for integer operands AL
E SC
R E
— Thirty-two FPRs for single- or double-precision operands
• F
High instruction and data throughput
B Y
D
— Zero-cycle branch capability (branch folding)
VE branch prediction on unresolved conditional branches
— ProgrammableIstatic
H
Cfetch
A R
— Instruction unit capable of fetching two instructions per clock from the instruction cache
— A six-entry instruction queue that provides lookahead capability
— Independent pipelines with feed-forwarding that reduces data dependencies in hardware
— 8-Kbyte data cache—two-way set-associative, physically addressed; LRU replacement
algorithm
— 8-Kbyte instruction cache—two-way set-associative, physically addressed; LRU replacement
algorithm
— Cache write-back or write-through operation programmable on a per page or per block basis
— BPU that performs CR lookahead operations
— Address translation facilities for 4-Kbyte page size, variable block size, and 256-Mbyte
segment size
— A 64-entry, two-way set-associative ITLB
— A 64-entry, two-way set-associative DTLB
— Four-entry data and instruction BAT arrays providing 128-Kbyte to 256-Mbyte blocks
— Software table search operations and updates supported through fast trap mechanism
— 52-bit virtual address; 32-bit physical address
• Facilities for enhanced system performance
— A 32- or 64-bit split-transaction external data bus with burst transfers
— Support for one-level address pipelining and out-of-order bus transactions
— Bus extensions for direct-store operations

603 Hardware Specifications 3

 • Integrated power management
— Low-power 3.3 volt design
— Internal processor/bus clock multiplier that provides 1/1, 2/1, 3/1 and 4/1 ratios
— Three power saving modes—doze, nap, and sleep
— Automatic dynamic power reduction when internal functional units are idle
• In-system testability and debugging features through JTAG boundary-scan capability

1.3 General Parameters .

C
The following list provides a summary of the general parameters of the 603. IN
O R,
CT
Technology 0.5 µ CMOS (four-layer metal)
U
ND
Die size 11.5 mm x 7.4 mm (85 mm2)
O
Transistor count 1.6 million
IC
Logic design Fully-static S EM
L E
Package A CQFP
Surface mount, 240-pin
C
Power supply
E ES
3.3 ± 5% V dc
FR
1.4 Electrical and BYThermal Characteristics
E D
H IVand DC electrical specifications and thermal characteristics for the 603.
This section provides the AC

A RC
1.4.1 DC Electrical Characteristics
The tables in this section describe the 603 DC electrical characteristics. Table 1 provides the absolute
maximum ratings.

Table 1. Absolute Maximum Ratings

Characteristic Symbol Value Unit

Core supply voltage Vdd –0.3 to 4.0 V

PLL supply voltage AVdd –0.3 to 4.0 V

Input voltage Vin –0.3 to 5.5 V

Storage temperature range Tstg –55 to 150 °C

Notes:
1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress
ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may
affect device reliability or cause permanent damage to the device.
2. Caution: Vin must not exceed Vdd by more than 2.5 V at anytime including during power-on reset.

4 603 Hardware Specifications

Table 2 provides the recommended operating conditions for the 603.

Table 2. Recommended Operating Conditions

Characteristic Symbol Value Unit

Core supply voltage Vdd 3.135 to 3.465 V

PLL supply voltage AVdd 3.135 to 3.465 V

Input voltage Vin –0.3 to 5.5 V

°C
C.
Die-junction temperature Tj 0 to 105

N
,I
Notes: These are the recommended and tested operating conditions. Proper device operation outside of these

OR
conditions is not guaranteed.
T
Table 3 provides the package thermal characteristics for the 603.
DUC
N
CO
I
Table 3. Package Thermal Characteristics
E M
Characteristic S Symbol Value Rating
L E
Motorola wire-bond CQFP package die junction-to-caseAthermal resistance (typical) θJC °C/W
S C 2.2

R
IBM C4-CQFP package die junction-to-heat sink EEbase thermal resistance (typical) θJS 1.1 °C/W
F
BY
Note: Refer to Section 1.8, “System Design Information,” for more details about thermal management.

V ED
HI
Table 4 provides the DC electrical characteristics for the 603.
C
AR Table 4. DC Electrical Specifications
Vdd = 3.3 ± 5% V dc, GND = 0 V dc, 0 ≤ Tj ≤ 105 °C

Characteristic Symbol Min Max Unit Notes

Input high voltage (all inputs except SYSCLK) VIH 2.2 5.5 V

Input low voltage (all inputs except SYSCLK) VIL GND 0.8 V

SYSCLK input high voltage CVIH 2.4 5.5 V

SYSCLK input low voltage CVIL GND 0.4 V

Input leakage current, Vin = 3.465 V Iin — 10 µA 1

Vin = 5.5 V Iin — TBD µA 1

Hi-Z (off-state) leakage current, Vin = 3.465 V ITSI — 10 µA 1

Vin = 5.5 V ITSI — TBD µA 1

Output high voltage, IOH = –9 mA VOH 2.4 — V

603 Hardware Specifications 5

 Table 4. DC Electrical Specifications (Continued)
Vdd = 3.3 ± 5% V dc, GND = 0 V dc, 0 ≤ Tj ≤ 105 °C

Characteristic Symbol Min Max Unit Notes

Output low voltage, IOL = 14 mA VOL — 0.4 V

Capacitance, Vin = 0 V, f = 1 MHz (excludes TS, ABB, DBB, and ARTRY) Cin — 10.0 pF 2

Capacitance, Vin = 0 V, f = 1 MHz (for TS, ABB, DBB, and ARTRY) Cin — 15.0 pF 2

Notes:
C .
IN
1. Excludes test signals (LSSD_MODE, L1_TSTCLK, L2_TSTCLK), and JTAG signals.
2. Capacitance is periodically sampled rather than 100% tested.
O R,
U CT
ND
Table 5 provides the power consumption for the 603.
O
IC
Table 5. Power Consumption
M
SE
Vdd = 3.3 ± 5% V dc, GND = 0 V dc, 0 ≤ Tj ≤ 105 °C

LE
A Processor Core Frequency
SC
CPU Clock:
Unit
EE
SYSCLK
66.67 MHz 80 MHz
F R
BY
Full-On Mode

VED Typical 1.8 2.0 W

I
RCH Maximum 2.5 2.9 W
AMode*
Doze

Typical 740 800 mW

Nap Mode*

Typical 160 160 mW

Sleep Mode*

Typical 125 130 mW

Sleep Mode—PLL Disabled*

Typical 70 40 mW

Sleep Mode—PLL and SYSCLK Disabled*

Typical 2 2 mW

Note: These values apply for all valid PLL_CFG[0–3] settings and do not include
output driver power (OVdd) or analog supply power (AVdd). OVdd power is
system dependent but is typically ≤ 10% of Vdd. Worst-case AVdd = 15 mW.

6 603 Hardware Specifications

1.4.2 AC Electrical Characteristics
This section provides the AC electrical characteristics for the 603. After fabrication, parts are sorted by
maximum processor core frequency as shown in Section 1.4.2.1, “Clock AC Specifications” and tested for
conformance to the AC specifications for that frequency. The processor core frequency is determined by the
bus (SYSCLK) frequency and the settings of the PLL_CFG[0–3] signals. PLL_CFG signals should be set
prior to power up and not altered afterwards. These specifications are for 66 MHz core frequency with
33 MHz bus (66C—2:1 bus mode), 66 MHz bus (66A—1:1 bus mode), and 80 MHz core frequency with
40 MHz bus (80C—2:1 bus mode). Parts are sold by maximum processor core frequency and bus mode; see
Section 1.9, “Ordering Information.”

1.4.2.1 Clock AC Specifications C .

IN
Table 6 provides the clock AC timing specifications as defined in Figure 1.
O R,
Table 6. Clock AC Timing Specifications C
T
U
Vdd = 3.3 ± 5% V dc, GND = 0 V dc, 0 ≤ Tj ≤ 105 °C
O ND
IC66A
66C
E M 80C
Num Characteristic S Unit Notes
Min LMaxE Min Max Min Max
A
Processor frequency
E SC 66.0 16.67 66.0 16.67 80.0
16.67 MHz 1
E
VCO frequency FR 120 240 120 240 120 240 MHz
B Y
SYSCLK (bus) frequency D 16.67 33.0 16.67 66.0 16.67 40.0 MHz
V E
1 SYSCLK cycle time
C HI 40.0 60.0 30.0 60.0 25.0 60.0 ns

2,3 SYSCLK rise ARand fall time — 2.0 — 2.0 — 2.0 ns 2

4 SYSCLK duty cycle measured at 1.4 V 40.0 60.0 40.0 60.0 40.0 60.0 % 3

SYSCLK jitter — ±150 — ±150 — ±150 ps 4

603 internal PLL-relock time — 100 — 100 — 100 µs 3, 5

Notes:
1. Caution: The SYSCLK frequency and PLL_CFG[0–3] settings must be chosen such that the resulting
SYSCLK (bus) frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective
maximum or minimum operating frequencies. Refer to the PLL_CFG[0–3] signal description in Section 1.8,
“System Design Information,” for valid PLL_CFG[0–3] settings, and to Section 1.9, “Ordering Information,” for
available frequencies and part numbers.
2. Rise and fall times for the SYSCLK input are measured from 0.4 V to 2.4 V.
3. Timing is guaranteed by design and characterization, and is not tested.
4. The total input jitter (short term and long term combined) must be under ±150 ps.
5. Relock timing is guaranteed by design and characterization, and is not tested. PLL-relock time is the
maximum amount of time required for PLL lock after a stable Vdd and SYSCLK are reached during the
power-on reset sequence. This specification also applies when the PLL has been disabled and
subsequently re-enabled during sleep mode. Also note that HRESET must be held asserted for a minimum
of 255 bus clocks after the PLL-relock time (100 µs) during the power-on reset sequence.

603 Hardware Specifications 7

 Figure 1 provides the SYSCLK input timing diagram.

4 4 2 3
CVih

VM
SYSCLK
CVil

C .
IN
VM = Midpoint Voltage (1.4 V)

O R,
CT
Figure 1. SYSCLK Input Timing Diagram
U
1.4.2.2 Input AC Specifications
O ND
ICdefined in Figure 2 and Figure 3.
Table 7 provides the input AC timing specifications for the 603 as
S EM
LE
Table 7. Input AC Timing Specifications
Vdd = 3.3 ± 5% V dc, GND = 0 V dc, 0 ≤ Tj ≤ 105 °C A
E SC
RE 66C 66A 80C
Num Characteristic F Unit Notes
BY Min Max Min Max Min Max
D
10a I VE inputs valid to 4.0
Address/data/transfer attribute — 2.5 — 3.5 — ns 2
H
RC
SYSCLK (input setup)

10b A
All other inputs valid to SYSCLK (input setup) 6.0 — 4.5 — 5.5 — ns 3

10c Mode select inputs valid to HRESET (input 8* — 8* — 8* — ns 4, 5, 6

setup) (for DRTRY, QACK and TLBISYNC) tsysclk tsysclk tsysclk

11a SYSCLK to address/data/transfer attribute 1.0 — 1.0 — 1.0 — ns 2

inputs invalid (input hold)

11b SYSCLK to all other inputs invalid (input hold) 1.0 — 1.0 — 1.0 — ns 3

11c HRESET to mode select inputs invalid (input 0 — 0 — 0 — ns 4, 6

hold) (for DRTRY, QACK, and TLBISYNC)

Notes:
1. All input specifications are measured from the TTL level (0.8 or 2.0 V) of the signal in question to the 1.4 V of the
rising edge of the input SYSCLK. Both input and output timings are measured at the pin (see Figure 2).
2. Address/data/transfer attribute input signals are composed of the following—A[0–31], AP[0–3], TT[0–4],
TC[0–1], TBST, TSIZ[0–2], GBL, DH[0–31], DL[0–31], DP[0–7].
3. All other input signals are composed of the following—TS, XATS, ABB, DBB, ARTRY, BG, AACK, DBG, DBWO,
TA, DRTRY, TEA, DBDIS, HRESET, SRESET, INT, SMI, MCP, TBEN, QACK, TLBISYNC.
4. The setup and hold time is with respect to the rising edge of HRESET (see Figure 3). This specification is for
configuration-mode only. Also note that HRESET must be held asserted for a minimum of 255 bus clocks after
the PLL-relock time (100 µs) during the power-on reset sequence.
5. tsysclk is the period of the external clock (SYSCLK) in nanoseconds.
6. These values are guaranteed by design, and are not tested.

8 603 Hardware Specifications

Figure 2 provides the input timing diagram for the 603.

VM
SYSCLK
10a

10b
11a

11b

ALL INPUTS
C .
IN
VM = Midpoint Voltage (1.4 V)
O R,
U CT
ND
Figure 2. Input Timing Diagram
O
IC
Figure 3 provides the mode select input timing diagram for the 603.
M
SE
E
HRESET
C AL VM
E ES
FR
10cY
B
E D 11c

H IV
MODE PINS RC
A
VM = Midpoint Voltage (1.4 V)

Figure 3. Mode Select Input Timing Diagram

603 Hardware Specifications 9

 1.4.2.3 Output AC Specifications
Table 8 provides the output AC timing specifications for the 603 as defined in Figure 4.

Table 8. Output AC Timing Specifications1

Vdd = 3.3 ± 5% V dc, GND = 0 V dc, CL = 50 pF, 0 ≤ Tj ≤ 105 °C

66C 66A 80C

Num Characteristic Unit Notes
Min Max Min Max Min Max

—.
C
12 SYSCLK to output driven (output enable time) 1.0 — 1.0 — 1.0 ns
N
I 12.0
R,
13a SYSCLK to output valid (5.5 V to 0.8 V— TS, — 13.0 — 10.0 — ns 4
O
CT —
ABB, ARTRY, DBB)

U
ND
13b SYSCLK to output valid (TS, ABB, ARTRY, DBB) — 12.0 — 9.0 11.0 ns 6

—O
IC
14a SYSCLK to output valid (5.5 V to 0.8 V— all — 15.0 12.0 — 14.0 ns 4

EM
except TS, ABB, ARTRY, DBB)
S13.0
LE
14b SYSCLK to output valid (all except TS, ABB, — — 10.0 — 12.0 ns 6
ARTRY, DBB) A
SC
15 SYSCLK to output invalid (output hold)
REE 1.5 — 1.5 — 1.5 — ns 3

16 SYSCLK to output high impedance Y

F
(all except — 11.5 — 8.5 — 10.5 ns
B
ED
ARTRY, ABB, DBB)

V
HI
17 SYSCLK to ABB, DBB, high impedance after — 1.0 — 1.2 — 1.0 tsysclk 5,7
precharge C
18
AR
SYSCLK to ARTRY high impedance before — 11.0 — 8.0 — 10.0 ns
precharge

19 SYSCLK to ARTRY precharge enable 0.2 * — 0.2 * — 0.2 * — ns 3,5,8

tsysclk tsysclk tsysclk
+ 1.0 + 1.0 + 1.0

20 Maximum delay to ARTRY precharge — 1.0 — 1.2 — 1.0 tsysclk 5,8

21 SYSCLK to ARTRY high impedance after — 2.0 — 2.25 — 2.0 tsysclk 5,8
precharge

Notes:
1. All output specifications are measured from the 1.4 V of the rising edge of SYSCLK to the TTL level (0.8 V or 2.0 V)
of the signal in question. Both input and output timings are measured at the pin
2. All maximum timing specifications assume CL = 50 pF.
3. This minimum parameter assumes CL = 0 pF.
4. SYSCLK to output valid (5.5 V to 0.8 V) includes the extra delay associated with discharging the external voltage
from 5.5 V to 0.8 V instead of from Vdd to 0.8 V (5 V CMOS levels instead of 3.3 V CMOS levels).
5. tsysclk is the period of the external bus clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be
multiplied by the period of SYSCLK to compute the actual time duration (in nanoseconds) of the parameter in
question.
6. Output signal transitions from GND to 2.0 V or Vdd to 0.8 V.
7. Nominal precharge width for ABB and DBB is 0.5 tsysclk.
8. Nominal precharge width for ARTRY is 1.0 tsysclk.

10 603 Hardware Specifications

Figure 4 provides the output timing diagram for the 603.

VM VM VM
SYSCLK
14
15

16
12
ALL OUTPUTS
(Except TS, ABB,
DBB, ARTRY
C .
13 15
IN
13 16
O R,
TS
U CT
O ND
17
IC
S EM
ABB, DBB
ALE
SC
REE 21

F
BY
20

ED
19

I V 18

CH
ARTRY

AR
VM = Midpoint Voltage (1.4 V)

Figure 4. Output Timing Diagram

1.4.3 JTAG AC Timing Specifications

Table 9 provides the JTAG AC timing specifications as defined in Figure 5 through Figure 8.

Table 9. JTAG AC Timing Specifications (Independent of SYSCLK)

Vdd = 3.3 ± 5% V dc, GND = 0 V dc, CL = 50 pF, 0 ≤ Tj ≤ 105 °C

Num Characteristic Min Max Unit Notes

TCK frequency of operation 0 16 MHz

1 TCK cycle time 62.5 — ns

2 TCK clock pulse width measured at 1.4 V 25 — ns

3 TCK rise and fall times 0 3 ns

4 TRST setup time to TCK rising edge 13 — ns 1

5 TRST assert time 40 — ns

6 Boundary-scan input data setup time 6 — ns 2

603 Hardware Specifications 11

 Table 9. JTAG AC Timing Specifications (Independent of SYSCLK) (Continued)
Vdd = 3.3 ± 5% V dc, GND = 0 V dc, CL = 50 pF, 0 ≤ Tj ≤ 105 °C

Num Characteristic Min Max Unit Notes

7 Boundary-scan input data hold time 27 — ns 2

8 TCK to output data valid 4 25 ns 3

9 TCK to output high impedance 3 24 ns 3

10 TMS, TDI data setup time 0 — ns

C .
ns IN
R,
11 TMS, TDI data hold time 25 —
O
CT
12 TCK to TDO data valid 4 24 ns

D U
13 TCK to TDO high impedance
O
3
N15 ns

IC
M
Notes:

SE purposes only.
1. TRST is an asynchronous signal. The setup time is for test
2. Non-test signal input timing with respect to TCK.LE
3. Non-test signal output timing with respect toC
A
S TCK.

R EE
Figure 5 provides the JTAG clock inputFtiming diagram.
BY
D
I VE
H
1

C
AR
2 2

VM VM VM
TCK
3 3

VM = Midpoint Voltage (1.4 V)

Figure 5. Clock Input Timing Diagram

Figure 6 provides the TRST timing diagram.

VM
TCK
4

TRST

Figure 6. TRST Timing Diagram

12 603 Hardware Specifications

Figure 7 provides the boundary-scan timing diagram.

VM
TCK VM

6 7

Data Inputs Input Data Valid

.
Data Outputs Output Data Valid

C
IN
R,
9

O
CT
Data Outputs
U
8
O ND
Data Outputs
IC Output Data Valid

S EM
E Timing Diagram
Figure 7. Boundary-Scan

C AL
ES
Figure 8 provides the test access port timing diagram.
E
FR
BYVM
D
VM
TCK

I VE
CH
10 11

A R
TDI, TMS Input Data Valid

12

TDO Output Data Valid

13

TDO

12

TDO Output Data Valid

Figure 8. Test Access Port Timing Diagram

603 Hardware Specifications 13

1.5 PowerPC 603 Microprocessor Pin Assignments
This section contains the pinout diagram for the 603 ceramic quad flat pack (CQFP) package as shown in
Figure 9.

LSSD_MODE
CKSTP_OUT

L2 _TSTCLK
L1_TSTCLK
PLL_CFG0

PLL_CFG1
PLL_CFG2

PLL_CFG3
TLBISYNC

CKSTP_IN
CLK_OUT

HRESET

SRESET
SYSCLK
OGND

OGND

OGND

OGND

OGND
OVDD

OVDD

OVDD

OVDD

OVDD
QACK

RSRV

TSIZ0
TSIZ1
TSIZ2
AVDD
TBEN

TRST

TBST
GND

GND

MCP

GND
VDD

TMS

TDO
CSE

DPE
APE

TCK
AP0
AP1

AP2
AP3

TC0
TC1

TT0
TT1

SMI

TT2
TT3
TDI

INT
WT

BR
CI

211
240
239
238
237
236
235
234
233
232
231
230
229
228
227
226
225
224
223
222
221
220
219
218
217
216
215
214
213
212

210
209
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
GBL 1
C . 180 TT4

IN
A1 2 179 A0

R,
A3 3 178 A2
VDD 4 1 177 VDD

O
A5 5 176 A4

CT
A7 6 175 A6
A9 7 174 A8

U
OGND 8 173 OVDD

ND
GND 9 172 GND
OVDD 10 171 OGND

O
A11 11 170 A10

IC
A13 12 169 A12
A15 13 168 A14

M
VDD 14 167 VDD

SE
A17 15 166 A16
A19 16 TOP VIEW 165 A18

LE
A21 17 164 A20
OGND 18 163 OVDD

A
GND 19 162 GND

SC
OVDD 20 161 OGND
A23 21 160 A22
A25 22
E 159 A24

RE
A27 23 158 A26
VDD 157 VDD
F
24
DBWO 25 156 DRTRY

BY
DBG 26 155 TA
BG 27 154 TEA

ED
AACK 28 153 DBDIS
GND 29 152 GND

V
A29 30 151 A28
QREQ 31
I 150 XATS

CH
ARTRY 32 149 TS
OGND 33 148 OVDD
VDD
OVDD
34
35
AR 147
146
VDD
OGND
ABB 36 145 DBB
A31 37 144 A30
DP0 38 143 DL0
GND 39 142 GND
DP1 40 141 DL1
DP2 41 140 DL2
DP3 42 139 DL3
OGND 43 138 OVDD
VDD 44 137 VDD
OVDD 45 136 OGND
DP4 46 135 DL4
DP5 47 134 DL5
DP6 48 133 DL6
GND 49 132 GND
DP7 50 131 DL7
DL23 51 130 DL8
DL24 52 129 DL9
OGND 53 128 OVDD
OVDD 54 127 OGND
DL25 55 126 DL10
DL26 56 125 DL11
DL27 57 124 DL12
DL28 58 123 DL13
VDD 59 122 VDD
OGND 60 121 OVDD
111
110

112
113
114
115
116
117
118
119
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109

120
OGND

OGND

OGND

OGND

OGND

OGND

OGND
OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD
DH31
DH30
DH29

DH28
DH27
DH26
DH25
DH24
DH23

DH22

DH21
DH20
DH19
DH18
DH17
DH16

DH15

DH14
DH13
DH12
DH11
DH10
DL29
DL30
DL31

DL22
DL21
DL20

DL19
DL18
DL17

DL16
DL15
DL14
GND

GND
DH9

DH8
DH7
DH6

DH5
DH4
DH3

DH2
DH1
DH0

Figure 9. Pinout Diagram of the CQFP Package

14 603 Hardware Specifications

1.6 PowerPC 603 Microprocessor Pinout Listing
Table 10 provides the pinout listing for the 603 CQFP package.

Table 10. PowerPC 603 Microprocessor Pinout Listing

Signal Name Pin Number Active I/O

A[0–31] 179, 2, 178, 3, 176, 5, 175, 6, 174, 7, 170, 11, 169, 12, 168, High I/O
13, 166, 15, 165, 16, 164, 17, 160, 21, 159, 22, 158, 23, 151,
30, 144, 37

C .
IN
AACK 28 Low Input

ABB 36
O R,Low I/O

AP[0–3] 231, 230, 227, 226

U CT High I/O

APE 218 O ND Low Output

IC
ARTRY 32
S EM Low I/O

AVDD 209
ALE High Input

SC
EE
BG 27 Low Input

BR 219 F R Low Output

BY
ED
CI 237 Low Output

I V
CLK_OUT
CH221 — Output

CKSTP_IN AR 215 Low Input

CKSTP_OUT 216 Low Output

CSE 225 High Output

DBB 145 Low I/O

DBDIS 153 Low Input

DBG 26 Low Input

DBWO 25 Low Input

DH[0–31] 115, 114, 113, 110, 109, 108, 99, 98, 97, 94, 93, 92, 91, 90, High I/O
89, 87, 85, 84, 83, 82, 81, 80, 78, 76, 75, 74, 73, 72, 71, 68,
67, 66

DL[0–31] 143, 141, 140, 139, 135, 134, 133, 131, 130, 129, 126, 125, High I/O
124, 123, 119, 118, 117, 107, 106, 105, 102, 101, 100, 51,
52, 55, 56, 57, 58, 62, 63, 64

DP[0–7] 38, 40, 41, 42, 46, 47, 48, 50 High I/O

DPE 217 Low Output

DRTRY 156 Low Input

GBL 1 Low I/O

603 Hardware Specifications 15

 Table 10. PowerPC 603 Microprocessor Pinout Listing (Continued)

Signal Name Pin Number Active I/O

GND 9, 19, 29, 39, 49, 65, 116, 132, 142, 152, 162, 172, 182, 206, Low Input
239

HRESET 214 Low Input

INT 188 Low Input

LSSD_MODE1 205 Low Input

—N C.
L1_TSTCLK1 204
, I Input

L2_TSTCLK1 R
O —
T
203 Input

MCP 186
DUC Low Input
N
CO120, 127, 136,
146, 161, 171, 181, 193, 220, 228, 238MI
OGND 8, 18, 33, 43, 53, 60, 69, 77, 86, 95, 103, 111, Low Input

SE
E 96, 104, 112, 121, 128,
AL222, 229, 240
OVDD 10, 20, 35, 45, 54, 61, 70, 79, 88, High Input

C
138, 148, 163, 173, 183, 194,

PLL_CFG[0–3] 213, 211, 210, 208EE

S High Input
FR
BY
QACK 235 Low Input

QREQ 31 E D Low Output

H IV
RSRV C 232 Low Output

SMI
AR 187 Low Input

SRESET 189 Low Input

SYSCLK 212 — Input

TA 155 Low Input

TBEN 234 High Input

TBST 192 Low I/O

TC[0–1] 224, 223 High Output

TCK 201 — Input

TDI 199 High Input

TDO 198 High Output

TEA 154 Low Input

TLBISYNC 233 Low Input

TMS 200 High Input

TRST 202 Low Input

TSIZ[0–2] 197, 196, 195 High I/O

16 603 Hardware Specifications

 Table 10. PowerPC 603 Microprocessor Pinout Listing (Continued)

Signal Name Pin Number Active I/O

TS 149 Low I/O

TT[0–4] 191, 190, 185, 184, 180 High I/O

VDD 4, 14, 24, 34, 44, 59, 122, 137, 147, 157, 167, 177, 207 High Input

WT 236 Low Output

XATS 150 Low

C . I/O
IN
R,
Notes:

T O machine operation.
1. These are test signals for factory use only and must be pulled up to Vdd for normal
2. OVdd inputs supply power to the I/O drivers and Vdd inputs supply powerUtoCthe processor core. Future
D for example, OVdd = 3.3 V or
ON
members of the 603 family may use different OVdd and Vdd input levels;

IC
5.0 V, with Vdd = 2.5 V.

E M
S
ALE
1.7 PowerPC 603 Microprocessor Package
C
Description ES E
FR parameters and the mechanical dimensions for the 603. Note
The following sections provide the package
Y types of CQFP packages—the Motorola wire-bond CQFP and the
that the 603 is currently offered inBtwo
D
VE
IBM C4-CQFP.

H I
R
1.7.1 MotorolaCWire-Bond CQFP Package Description
A
The following sections provide the package parameters and mechanical dimensions for the Motorola wire-
bond CQFP package.

1.7.1.1 Package Parameters

The package parameters for the Motorola wire-bond CQFP are as provided in the following list. The
package type is 32 mm x 32 mm, 240-pin ceramic quad flat pack.
Package outline 32 mm x 32 mm
Interconnects 240
Pitch 0.5 mm (20 mil)
Maximum module height 4.15 mm

603 Hardware Specifications 17

1.7.1.2 Mechanical Dimensions of the Motorola Wire-Bond CQFP Package
Figure 10 shows the mechanical dimensions for the Motorola wire-bond CQFP package.

AB

θI

–H–
θ2

C .
IRN
O R, H

CT AA
G

U
O ND
IC
F C

S EM
LE
A

A J

SC
EE
B

*Reduced pin count shown for clarity. 60 F

R
Y
pins per side

B
D
I VE Min. Max.

CH
A 30.86 31.75

A R B 34.6 BSC
C 3.75 4.15
D 0.5 BSC
E 0.18 0.30
F 3.10 3.90
G 0.13 0.175
H 0.45 0.55
J 0.25 –
AA 1.80 REF
AB 0.95 REF
θ1 2° 6°
θ2 1° 7°
R 0.15 REF

Pin 240
Notes:
Pin 1 1. BSC—Between Standard Centers.
2. All measurements in mm.

D E

Die Wire Bonds Ceramic Body

Alloy 42 Leads
*Not to scale

Figure 10. Mechanical Dimensions of the Motorola Wire-Bond CQFP Package

18 603 Hardware Specifications

1.7.2 IBM C4-CQFP Package Description
The following sections provide the package parameters and mechanical dimensions for the IBM C4-CQFP
package.

1.7.2.1 Package Parameters

The package parameters for the IBM C4-CQFP are as provided in the following list. The package type is
32 mm x 32 mm, 240-pin ceramic quad flat pack.
Package outline 32 mm x 32 mm
Interconnects 240
C .
IN
R,
Pitch 0.5 mm
O
Lead plating Ni Au
U CT
Solder joint Sn/PB (10/90)
O ND
IC
EM
Lead encapsulation Epoxy
S
Solder-bump encapsulation Epoxy
L E
Maximum module height 3.1 mm CA
E ES
FR
Co-planarity specification 0.08 mm

Note: No solvent can be used B Y the C4-CQFP package.

with See Appendix A, “General Handling
D
VE
Recommendations for the C4-CQFP Package,” for details.
I
R CH
A

603 Hardware Specifications 19

1.7.2.2 Mechanical Dimensions of the IBM C4-CQFP Package
Figure 11 shows the mechanical dimensions for the IBM C4-CQFP package.

Epoxy Dam Solder-Bump Encapsulant

Chip
F
Radius
Ang
G Jmin
N C.
,I
Urethane

R
Clip Leadframe Tape Cast Ceramic H

CTO
U
O ND
IC
C

S EM
ALE
SC
EE
-C- 0.08
A
F R
BY s
0.13 TOTAL A-B

E D
*Reduced pin count shown for clarity. 60 pins per side
V
HI
min max
C
AR
A 31.8 32.2
B 34.4 34.8
E C 2.33 2.93
D 0.45 0.55
E 0.18 0.28
F 0.585 0.685
G 0.12 0.20
H 0.40 0.60
Jmin 0.30 0.40
-B- Ang 0.0° 5.0°
Rad — 0.25

D
0.08 TOTAL M A-B

Pin 240

Pin 1
-A-
B
0.13 TOTAL s A-B * Not to scale
All measurements in mm

Figure 11. Mechanical Dimensions of the IBM C4-CQFP Package

20 603 Hardware Specifications

 1.8 System Design Information
This section provides electrical and thermal design recommendations for successful application of the 603.

1.8.1 PLL Configuration

The 603 PLL is configured by the PLL_CFG[0–3] signals. For a given SYSCLK (bus) frequency, the PLL
configuration signals set the internal CPU and VCO frequency of operation. The PLL configuration for the
603 is shown in Table 11 for nominal frequencies.

Table 11. PowerPC 603 Microprocessor PLL Configuration

CPU Frequency in MHz (VCO Frequency in MHz) IN

C.
O R,
BusCT Bus
PLL_CFG[0–3] Bus-to- Core-to-
Bus Bus Bus Bus Bus
33.3 U
Core VCO
ND
16.6 MHz 20 MHz 25 MHz MHz 40 MHz 50 MHz 66.6 MHz
Multiplier Multiplier
O
IC —
EM
0000 1x 2x — — — — — 66.6
S (133)

0001 1x 4x — —AL
E — 33.3 40 50 —
SC (133) (160) (200)

16.6R
EE
0010 1x 8x
F 20 25 — — — —

BY
(133) (160) (200)

0100 2x E2xD — — — 66.6 80 — —

I V (133) (160)

RCH
0101
A
2x 4x 33.3
(133)
40
(160)
50
(200)
— — — —

1000 3x 2x — 60 75 — — — —
(120) (150)

1001 3x 4x 50 60 — — — — —
(200) (240)

1100 4x 2x 66.6 80 — — — — —
(133) (160)

0011 PLL bypass

1111 Clock off

Notes:
1. The sample bus-to-core frequencies shown are for reference only.
2. Some PLL configurations may select bus, CPU, or PLL frequencies which are not supported by the 603; see
Section 1.4.2.2, “Input AC Specifications,” for valid SYSCLK frequencies.
3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the bus
mode is set for 1:1 mode operation. This mode is intended for factory use only. Note: The AC timing specifications
given in this document do not apply in PLL-bypass mode.
4. In clock-off mode, no clocking occurs inside the 603 regardless of the SYSCLK input.
5. PLL_CFG[0–1] signals select the CPU-to-bus ratio (1:1, 2:1, 3:1, 4:1), PLL_CFG[2–3] signals select the CPU-to-PLL
multiplier (x2, x4, x8).

603 Hardware Specifications 21

1.8.2 PLL Power Supply Filtering
The AVdd power signal is provided on the 603 to provide power to the clock generation phased-lock loop.
To ensure stability of the internal clock, the power supplied to the AVdd input signal should be filtered using
a circuit similar to the one shown in Figure 12. The circuit should be placed as close as possible to the AVdd
signal to ensure it filters out as much noise as possible.

10 Ω
Vdd AVdd
10 µF 0.1 µF

C .
IN
R,
GND
O
Figure 12. PLL Power Supply Filter CircuitCT

N DU
O
IC
1.8.3 Decoupling Recommendations
Due to the 603’s dynamic power management feature, large
S EMaddress and data buses, and high operating

LE noise must be prevented from reaching other

frequencies, the 603 can generate transient power surges and high frequency noise in its power supply,
especially while driving large capacitive loads. A This
E SC requires a clean, tightly regulated source of power.
components in the 603 system, and the 603 itself
E designer place at least one decoupling capacitor at each Vdd
FR
Therefore, it is recommended that the system

BYplanes in the PCB, utilizing short traces to minimize inductance.

and OVdd pin of the 603. It is also recommended that these decoupling capacitors receive their power from
separate Vdd, OVdd, and GND power
VED
HI as close as possible to their associated Vdd or OVdd pin. Suggested values
These capacitors should vary in value from 220 pF to 10 µF to provide both high- and low-frequency
filtering, and should beCplaced
for the Vdd pins—220AR pF (ceramic), 0.01 µF (ceramic), and 0.1 µF (ceramic). Suggested values for the
OVdd pins—0.01 µF (ceramic), 0.1 µF (ceramic), and 10 µF (tantalum). Only SMT (surface mount
technology) capacitors should be used to minimize lead inductance.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the Vdd and OVdd planes, to enable quick recharging of the smaller chip capacitors. These bulk
capacitors should also have a low ESR (equivalent series resistance) rating to ensure the quick response time
necessary. They should also be connected to the power and ground planes through two vias to minimize
inductance. Suggested bulk capacitors—100 µF (AVX TPS tantalum) or 330 µF (AVX TPS tantalum).

1.8.4 Connection Recommendations

To ensure reliable operation, it is recommended to connect unused inputs to an appropriate signal level.
Unused active low inputs should be connected to Vdd. Unused active high inputs should be connected to
GND.

1.8.5 Pull-up Resistor Requirements

The 603 requires high-resistive (weak: 10 KΩ) pull-up resistors on several control signals of the bus
interface to maintain the control signals in the negated state after they have been actively negated and
released by the 603 or other bus master. These signals are—TS, ABB, DBB, ARTRY.
In addition, the 603 has three open-drain style outputs that require pull-up resistors (weak or stronger:
4.7 KΩ–10 KΩ) if they are used by the system. These signals are—APE, DPE, and CKSTP_OUT.
During inactive periods on the bus, the address and transfer attributes on the bus are not driven by any master

22 603 Hardware Specifications

and may float in the high-impedance state for relatively long periods of time. Since the 603 must continually
monitor these signals for snooping, this float condition may cause excessive power draw by the input
receivers on the 603. It is recommended that these signals be pulled up through weak (10 KΩ) pull-up
resistors or restored in some manner by the system. The snooped address and transfer attribute inputs are—
A[0–31], AP[0–3], TT[0–4], TBST, TSIZ[0–2], and GBL.
The data bus input receivers are normally turned off when no read operation is in progress and do not require
pull-up resistors on the data bus.

1.8.6 Thermal Management Information

This section provides thermal management information for the ceramic quad-flat package
N C. for air-cooled
, I design—the heat
applications. Proper thermal control design is primarily dependent upon the system-level
R
T O
sink, airflow and thermal interface material. To reduce the die-junction temperature, heat sinks may be
attached to the package by several methods—adhesive or spring clip to holesC in the printed-circuit board;
see Figure 13. This spring force should not exceed 5.5 pounds of force. DU
O N
IC
WB/CQFP Package M
E Heat Sink
S
ALE
SC Heat Sink

EE
Clip

F R
BY Adhesive

ED
or
Thermal Interface Material
I V
RCH
A

Printed-Circuit Board

Figure 13. Package Exploded Cross-Sectional View with Several Heat Sink Options

The board designer can choose between several types of heat sinks to place on the 603. There are several
commercially-available heat sinks for the 603 provided by the following vendors:
Chip Coolers Inc. 800-227-0254 (USA/Canada)
333 Strawberry Field Rd. 401-739-7600
Warwick, RI 02887-6979

International Electronic Research Corporation (IERC) 818-842-7277

135 W. Magnolia Blvd.
Burbank, CA 91502

Thermalloy 214-243-4321
2021 W. Valley View Lane
P.O. Box 810839
Dallas, TX 75731

603 Hardware Specifications 23

 Wakefield Engineering 617-245-5900
60 Audubon Rd.
Wakefield, MA 01880

Aavid Engineering 603-528-3400

One Kool Path
Laconia, NH 03247-0440

Ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal
performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost.
C .
1.8.6.1 Internal Package Conduction Resistance , IN
T OR in Table 3) versus the
For this packaging technology the intrinsic thermal conduction resistance (shown
external thermal resistance paths are shown in Figure 14 for a package with C
DU
an attached heat sink mounted
to a printed-circuit board.
O N
IC
External Resistance Radiation
M
Convection

SE
ALE
E SC
E
Heat Sink
FR
Thermal Interface Material

Internal Resistance BY Die/Package

ED
Die Junction

I V Package/Leads

RCH Printed-Circuit Board

A

Radiation Convection
External Resistance
(Note the internal versus external package resistance)

Figure 14. Package with Heat Sink Mounted to a Printed-Circuit Board

1.8.6.2 Adhesives and Thermal Interface Materials

A thermal interface material is recommended at the package lid-to-heat sink interface to minimize the
thermal contact resistance. For those applications where the heat sink is attached by spring clip mechanism,
Figure 15 shows the thermal performance of three thin-sheet thermal-interface materials (silicone, graphite/
oil, floroether oil), a bare joint, and a joint with thermal grease as a function of contact pressure. As shown,
the performance of these thermal interface materials improves with increasing contact pressure. The use of
thermal grease significantly reduces the interface thermal resistance. That is, the bare joint results in a
thermal resistance approximately 7 times greater than the thermal grease joint.
Heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board (see
Figure 13). This spring force should not exceed 5.5 pounds of force. Therefore, the synthetic grease offers
the best thermal performance, considering the low interface pressure. Of course, the selection of any thermal
interface material depends on many factors—thermal performance requirements, manufacturability, service
temperature, dielectric properties, cost, etc.

24 603 Hardware Specifications

 Silicone Sheet (0.006 inch)
Bare Joint
2 Floroether Oil Sheet (0.007 inch)
Graphite/Oil Sheet (0.005 inch)
Synthetic Grease
Specific Thermal Resistance (Kin2 /W)
Specific Thermal Resistance (Kin2/W)

1.5

C .
IN
O R,
U CT
ND
1
O
IC
S EM
ALE
0.5
SC
REE
F
BY
VED
I
CH
0
0
AR 10 20 30 40 50 60 70 80
Contact Pressure
Contact Pressure (psi) (psi)

Figure 15. Thermal Performance of Select Thermal Interface Material

The board designer can choose between several types of thermal interface. Heat sink adhesive materials
should be selected based upon high conductivity, yet adequate mechanical strength to meet equipment
shock/vibration requirements. There are several commercially-available thermal interfaces and adhesive
materials provided by the following vendors:
Dow-Corning Corporation 517-496-4000
Dow-Corning Electronic Materials
P.O. Box 0997
Midland, MI 48686-0997
Chomerics, Inc. 617-935-4850
77 Dragon Court
Woburn, MA 01888-4850
Thermagon Inc. 216-741-7659
3256 West 25th Street
Cleveland, OH 44109-1668

603 Hardware Specifications 25

 Loctite Corporation 860-571-5100
1001 Trout Brook Crossing
Rocky Hill, CT 06067
AI Technology (e.g., EG7655) 609-882-2332
1425 Lower Ferry Rd
Trent, NJ 08618

The following section provides a heat sink selection example using one of the commercially available heat
sinks.
C .
1.8.6.3 Heat Sink Selection Example
, IN
asR
For preliminary heat sink sizing, the die-junction temperature can be expressed O follows:
Tj = Ta + Tr + (θjc + θint + θsa) * Pd U CT
ND
CO
Where:
I
Tj is the die-junction temperature M
Ta is the inlet cabinet ambient temperature SE
E
AL cabinet
Tr is the air temperature rise within the computer
C
ESthermal resistance
θjc is the die junction-to-case thermal resistance
E
θint is the adhesive or interface material
FR thermal resistance
θsa is the heat sink base-to-ambient
Pd is the power dissipated byBYthe device
D
I VE temperatures (Tj) should be maintained less than the value specified in
During operation the die-junction
Table 2. The temperature
R CH of the air cooling the component greatly depends upon the ambient inlet air
temperature and the A air temperature rise within the electronic cabinet. An electronic cabinet inlet-air
temperature (Ta) may range from 30 to 40 °C. The air temperature rise within a cabinet (Tr) may be in the
range of 5 to 10 °C. The thermal resistance of the thermal interface material (θint) is typically about
1 °C/W. Assuming a Ta of 30 °C, a Tr of 5 °C a CQFP package θjc = 2.2 °C/W, and a power consumption
(Pd ) of 3.0 W, the following expression for Tj is obtained:
Die-junction temperature: Tj = 30 °C + 5 °C + (2.2 °C/W + 1.0 °C/W + Rsa) * 3.0 W
For a Thermalloy heat sink #2328B, the heat sink-to-ambient thermal resistance (Rsa) versus airflow
velocity is shown in Figure 16.

26 603 Hardware Specifications

 8

(°C/W)
Heat Sink Thermal Resistance (°C/W)
7
Thermalloy #2328B Pin-fin Heat Sink
(25 x 28 x 15 mm)
Thermal Resistance 6

C .
IN
5

O R,
4
U CT
O ND
3 IC
EM
Heat Sink

S
2 ALE
SC
REE
1 F
0.5 Y
0
B 1 1.5 2 2.5 3 3.5

E D Approach Airflow Velocity

Approach Airflow Velocity (m/s) (m/s)
H IV
RC #2328B Heat Sink-to-Ambient Thermal Resistance Versus Airflow Velocity
Figure 16. Thermalloy
A
Assuming an air velocity of 0.5 m/s, we have an effective Rsa of 7 °C/W, thus
Tj = 30 °C + 5 °C + (2.2 °C/W +1.0 °C/W + 7 °C/W) * 3.0 W,
resulting in a die-junction temperature of approximately 66 °C which is well within the maximum operating
temperature of the component.
Other heat sinks offered by Chip Coolers, IERC, Thermalloy, Wakefield Engineering, and Aavid
Engineering offer different heat sink-to-ambient thermal resistances, and may or may not need air flow.
Though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a common figure-
of-merit used for comparing the thermal performance of various microelectronic packaging technologies,
one should exercise caution when only using this metric in determining thermal management because no
single parameter can adequately describe three-dimensional heat flow. The final die-junction operating
temperature, is not only a function of the component-level thermal resistance, but the system-level design
and its operating conditions. In addition to the component's power consumption, a number of factors affect
the final operating die-junction temperature—airflow, board population (local heat flux of adjacent
components), heat sink efficiency, heat sink attach, heat sink placement, next-level interconnect technology,
system air temperature rise, altitude, etc.
Due to the complexity and the many variations of system-level boundary conditions for today's
microelectronic equipment, the combined effects of the heat transfer mechanisms (radiation, convection and
conduction) may vary widely. For these reasons, we recommend using conjugate heat transfer models for
the board, as well as, system-level designs. To expedite system-level thermal analysis, several “compact”
thermal-package models are available within FLOTHERM®. These are available upon request.

603 Hardware Specifications 27

1.9 Ordering Information
This section provides the ordering information for the 603. Note that the individual part numbers correspond
to a specific combination of 603 internal/bus frequencies, which must be observed to ensure proper
operation of the device. For other frequency combinations, temperature ranges, power-supply tolerances
package types, etc., contact your local Motorola or IBM sales office.

Table 12. Ordering Information for the PowerPC 603 Microprocessor

Package Type Maximum Maximum Required Part Numbers

Internal Bus PLL_CFG[0–3]
Motorola IBM Frequency Frequency Setting Motorola C . IBM
IN
, PPC603-FX-080-2
Wire-bond C4-CQFP 80 MHz 40 MHz 0100
O R
MPC603AFE80CC

CT
CQFP
66.67 MHz 33.33 MHz 0100
U
MPC603AFE66CC
D
PPC603-FX-066-2

66.67 MHz 0000 O N

MPC603AFE66AC PPC603-FX-066-1
IC
S EM
1.9.1 Motorola Part Number Key E
CAL part number for the 603.
Figure 17 provides a detailed description of the Motorola
E ES
FR
MPC BY 603 A FE XX X C
D
I VE Revision Level

Product Code CH
(Contact Motorola Sales Office)

AR
Part Identifier
Application Modifier
(A = 1:1 Processor to Bus,
C = 2:1 Processor to Bus)
Part Modifier
(A = Alpha—Original Design) Processor Speed
Package
(FE = Wire-Bond CQFP)

Figure 17. Motorola Part Number Key

1.9.2 IBM Part Number Key

Figure 18 provides a detailed description of the IBM part number for the 603.

PPC 603 – F X– 0XX– X

Product Code Bus Speed
(1 = Internal Speed,
Part Identifier 2 = Half Internal)

Package
(F = C4-CQFP) Internal Speed
Revision Level
(Contact IBM Sales Office)

Figure 18. IBM Part Number Key

28 603 Hardware Specifications

 Appendix A
General Handling Recommendations for the
C4-CQFP Package
The following list provides a few guidelines for package handling:
• Handle the electrostatic discharge sensitive (ESD) package with care before, during, and after
processing.

C.
• Do not apply any load to exceed 3 Kg after assembly.
N
,I
• Components should not be hot-dip tinned.
• R
O (local exhaust) for all
The package encapsulation is an acrylated urethane. Use adequate ventilation
elevated temperature processes. C T
The package parameters are as follows: N DU
O
IC
EM
Heat sink adhesive AIEG-7655
S
IBM reference drawing 99F4869
L E
Yamaichi QFP-POA0.5-240P
SC
Test socket
Signal 165
E E
Power/ground 75 FR
BY
D
Total 240
E
IV
A.1 Package
RCHEnvironmental, Operation, Shipment,
A
and Storage Requirements
The environmental, operation, shipment, and storage requirements are as follows:
• Make sure that the package is suitable for continuous operation under business office environments.
— Operating environment: 10 °C to 40 °C, 8% to 80% relative humidity
— Storage environment: 1 °C to 60 °C, up to 80% relative humidity
— Shipping environment: 40 °C to 60 °C, 5% to 100% relative humidity
• This component is qualified to meet JEDEC moisture Class 2.
After expiration of shelf life, packages may be baked at 120 °C (+10/–5 °C) for 4 hours minimum
and then be used or repackaged. Shelf life is as specified by JEDEC for moisture Class 2
components.

A.2 Card Assembly Recommendations

This section provides recommendations for card assembly process. Follow these guidelines for card
assembly.
• This component is supported for aqueous, IR, convection reflow, and vapor phase card assembly
processes.
• The temperature of packages should not exceed 220 °C for longer than 5 minutes.
• The package entering a cleaning cycle must not be exposed to temperature greater than that
occurring during solder reflow or hot air exposure.
• It is not recommended to re-attach a package that is removed after card assembly.

603 Hardware Specifications 29

During the card assembly process, no solvent can be used with the C4FP, and no more than 3 Kg of force
must be applied normal to the top of the package prior to, during, or after card assembly. Other details of
the card assembly process follow:
Solder paste Either water soluble (for example, Alpha 1208) or no clean
Solder stencil thickness 0.152 mm
Solder stencil aperature Width reduced to 0.03 mm from the board pad width
Placement tool Panasonic MPA3 or equivalent
Solder reflow Infrared, convection, or vapor phase
C .
Solder reflow profile Infrared and/or convection
, IN
• Average ramp-up—0.48 to 1.8 °C/second OR
• Time above 183 °C—45 to 145 secondsC
T
D U
• Minimum lead temperature—200N°C
O
IC °C
• Maximum lead temperature—240
E M °C
S
• Maximum C4FP temperature—245
Vapor phase
ALE
SC
• Preheat (board)—60
E
°C to 150 °C
RE 183 °C—60 to 145 seconds
• Time above
F
• Minimum lead temperature—200 °C
B• Y
E D Maximum C4FP temperature—220 °C
H IV • Egress temperature—below 150 °C
RC
A
Clean after reflow De-ionized (D.I.) water if water-soluble paste is used
• Cleaner requirements—conveyorized, in-line
• Minimum of four washing chambers
— Pre-clean chamber: top and bottom sprays, minimum top-side
pressure of 25 psig, water temperature of 70 °C minimum, dwell
time of 24 seconds minimum, water is not re-used, water flow rate
of 30 liters/minute.
— Wash chamber #1: top and bottom sprays, minimum top-side
pressure of 48 psig, minimum bottom-side pressure of 44 psig,
water temperature of 62.5 °C (±2.5 °C), dwell time of 48 seconds
minimum, water flow rate of 350 liters/minute.
— Wash chamber #2: top and bottom sprays, minimum top-side
pressure of 32 psig, minimum bottom-side pressure of 28 psig,
water temperature of 72.5 °C (±2.5 °C), dwell time of 48 seconds
minimum, water flow rate of 325 liters/minute.
— Final rinse chamber: top and bottom sprays, minimum top-side
pressure of 25 psig, water temperature of 72.5 °C minimum, dwell
time of 24 seconds minimum, water flow rate of 30 liters/minute.
• No cleaning required if “no clean solder paste” is used
Touch-up and repair Water soluble (for example, Kester 450) or No Clean Flux
C4FP removal Hot air rework
C4FP replace Hand solder

30 603 Hardware Specifications

 C .
IN
O R,
U CT
D
NPowerPC
implied copyright or patent licenses granted hereunder by Motorola or IBM to design, modify theO
Information in this document is provided solely to enable system and software implementers to use microprocessors. There are no express or

IC
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M
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The PowerPC 603 microprocessor embodies the intellectual property of Motorola and SEof IBM. However, neither Motorola nor IBM assumes any responsibility
E
AL neither
or liability as to any aspects of the performance, operation, or other attributes of the microprocessor as marketed by the other party or by any third party. Neither
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FR and/or any of the products as described herein without further notice. NOTHING IN THIS
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CONVEYANCE BY MOTOROLA OR IBM OF AN D EXPRESS WARRANTY OF ANY KIND OR IMPLIED WARRANTY, REPRESENTATION, OR GUARANTEE

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FITNESS OF THE PRODUCTS FOR ANY PARTICULAR PURPOSE. Neither Motorola nor IBM assumes any

herein shall be undertaken solely byC Hmarketing party

liability or obligation for damages of any kind out of the application or use of these materials. Any warranty or other obligations as to the products described

absence of such an agreement, R

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