Puter Architecture
Puter Architecture
1
Computer System
• Number of interrelated components like
- Computer hardware - peripherals
- Data communication equipments
that work together with aim of converting
data into information.
• A computer system essentially has three
important components:
• CPU
• Input Unit
• Output Unit
Computer System
5
Component Interaction
The CPU controls all of the other resources within the system,
in order to accomplish a task.
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The CPU
Basic functions of CPU are:
7
• How do computers represent data?
CPU works with only binary data.
8
Interaction between functional
blocks
• CPU: Processor
Interprets and carries Registers
out basic instructions Control Arithmetic
Control Arithmetic
that operate a computer Unit Logic Unit (ALU)
Also called the processor
Instructions
Data
Control unit directs and Informatio
coordinates operations n
computer
in Input Output
Devices
Data Memory Information
Devices
Arithmetic logic unit
(ALU) performs Instructions
Data
arithmetic, comparison, Informatio
and logical operations n
Storage
Devices 9
Next
Interaction between functional blocks
TToouusseerr
(R(Reessuultl)t
Data
Data MEMORY UNIT
INPUT UNIT OUTPUT UNIT
(Registers)
ininsstrturucctitoionn re
reaadd wwrirtiete
ooppeeraranndd rresultlt
data flow
10
------Control flow
Interaction between functional
blocks
• The set of wires used for interconnection
is known as system bus.
• System bus is used to transmit data from
one unit to another.
• System bus is collection of wires through
which data is transmitted from one unit to
another (CPU, Memory and I/O devices)
• System bus has certain size or width
called data path which is measured in bits.
Interaction between functional
blocks
• System bus is further divided into three logical units: address bus,
data bus and control bus
• Data Bus: It transfers actual data or instructions between the
processor, memory and I/O devices.
• Address Bus: It informs the CPU about the location of the data
residing in the memory.
• Before data or instructions can be written into or read from memory
by cpu or I/O sections, address must be transmitted to memory over
the address bus.
• Processor and memory units holds a bidirectional relationship with the control and
data bus.
• In case of address bus, the communications with processors and memory is
unidirectional.
• The processor provides location of data (stored in memory), to be fetched from
memory, to the address bus and data bus carries the required data to processor.
What is a register?
Temporary high-speed storage area that holds
data and instructions
Stores location
from where instruction
was fetched
Stores Stores data
instruction while it is while ALU
being decoded computes it
Stores results
of calculation
p. 185
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Next
Registers
Register Name Function
Program Counter (PC) A Program counter keeps track of next
instructions to be executed.
Instruction Register (IR) An IR holds the instructions to be decoded
by the control unit.
Memory Address Register (MAR) MAR holds address of the next location in
memory to be accessed.
Memory Buffer Register (MBR) MBR is used for storing data either coming
to the CPU or data being transferred by the
CPU.
Accumulator (ACC) An accumulator is general purpose register
used for storing temporary results and
results produced by arithmetic logic unit.
Data Register (DR) A Data register is used for storing the
operands and other data.
Arithmetic / Logic Unit
ALU
+ Addition
-
Subtraction
Multiplication
Division
/ *
Logical Operations
Step 2.
Decode
Memory Translate
instruction
Step 4. Store into
Write result to commands
memory
Processor
ALU Step 3. Execute Control Unit
Carry out
command
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Next
Central Processing Unit (CPU)
Performs calculations
Arithmetic / Logic Unit
and decisions
Coordinates
Control Unit processing steps
Small, fast
Registers storage areas for
instructions and
data
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Communication between various Units of
a Computer System
• Processor to memory communication
• It also buffers the flow of data from the device to the processor and
vice versa.
Data
Interface Logic Bus
Unit Device
Processor Controller
Data Register Data
Bus
Register
Processor to I/O Devices Communication
• Steps to transfer of data between processor and I/O devices:
1. Processor sends the address of device from which data is to be read via
system bus.
3. The device interface logic acknowledge the signal and turns on a device
busy flip-flop (state 0).
4. I/O device reads data and places it in data register of the interface. It also
set data ready flip flop (state 1).
5. The processor continually interrogates the data ready flip flop and waits
until this flip-flop is set (state 0).
6. When data ready flip-flop is set, the processor reads data from interface
data register and places it in the appropriate processor register.
Processor Speed
• The processor is the main hardware that drives the computer, the
faster the processor, the better the performance.
• The overall speed of computer system is determined by several
factors, most notably:
– Clock speed
• The rate at which the processor process information and this
is measured in millions of cycles per second (Megahertz)
• E.g. 700 MHz
• The more the number of hertz, the faster is the processing
speed
– Speed and size of the data bus
• Larger the bus width and the faster the bus speed the grater
amount of data which can travel on it
Processor Speed
• While purchasing computer system, a perfect match
between the bus size, bus speed and the speed of clock
should be considered.
• For e.x. ,if computer can deliver data of 256 bits at a time
to the processor, the processor can only use 8 bits at a
time, and has slower clock speed
– Then it will not function optimally
– Data can be corrupted
– There will be a queue of data, waiting to get off the
bus
Processor Speed
• In a similar scenario, computer can deliver
data of 256 bits at a time to the processor,
the processor can use 64 bits at a time,
and has a faster clock speed
– Will function properly
– The processor will sit idle for data to be
received
– Hence, there is wastage of the precious
Multiprocessor systems
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Common pool of memory connected with high speed
bus