MJSAT 3 (1) 11-16

Malaysian Journal of Science

and
Advanced Technology

journal homepage: https://mjsat.com.my/

Design and Analysis of Full Adder Using 0.6 Micron CMOS Technology

Lee Chen Fei 1, Siti Husna Abdul Rahman1,2, Krishnan Subramaniam1, and Ahmad Anwar Zainuddin3,*

1
Department of Computer Engineering and Computer Science, School of Engineering and Computing, Manipal International
University, Negeri Sembilan, Malaysia
2
Faculty of Computing & Informatics (FCI) Multimedia University, Cyberjaya Malaysia
3
Kulliyyah of Information and Communication Technology, International Islamic University Malaysia

KEYWORDS ABSTRACT
Full Adder The design of a full adder involves the use of logic gates so that the design can convert 8
Multiplexer inputs to create a byte-wide adder and to force the carry bit to the other adder. However,
CMOS Technology the uses of multiplexers to replace the logic gates in the construction of the full adder is
Adder proven to be possible due to the function of the multiplexers to act as the digital switch in
the system that provides the flow of digital information from multiple inputs into an output.
This research aims to explore the possibility of implementing the multiplexers into the
ARTICLE HISTORY design of the full adder and to analyse the different possible full adder design using the
multiplexers. Using the multiplexers also allows for fewer logic gates to be used in the
Received 22 July 2022 design of the full adder, which reduces the overall area coverage of the full adder. However,
Received in revised form adding multiplexers does not make a complete adder more efficient and may slow it down.
5 February 2023 Thus, this article compares a conventional full adder with logic gates, a full adder with two
Accepted 5 February 2023 2:1 multiplexers, and a full adder with six 2:1 multiplexers in terms of power usage, time
Available online 6 February delay of the Sum and Carry outputs, and technology (0.6 μm).
2023

© 2023 The Authors. Published by Penteract Technology.

This is an open access article under the CC BY-NC 4.0 license (https://creativecommons.org/licenses/by-nc/4.0/).

1. INTRODUCTION
In a digital logic, a full adder is a adder which consists of three
and two outputs. Z.Zain recognized the full adder being one of the
most important digital blocks for a lot of systems [1]. This is mainly
due to the ability of the full adder to perform mathematical
operations such as addition or subtraction for the digital circuits. A
basic full adder design combines two binary digits (A, B) alongside
a carry-in digits (Cin) inputs and creates a sum (Sum) and a carry-
out (Carry or Cout) output.
Fig. 1 The design of a One-bit full adder cell [2]

*Corresponding author:
E-mail address: Ahmad Anwar Zainuddin <[email protected]>.
2785-8901/ © 2023 The Authors. Published by Penteract Technology.
This is an open access article under the CC BY-NC 4.0 license (https://creativecommons.org/licenses/by-nc/4.0/).
 Zainuddin et al./ Malaysian Journal of Science and Advanced Technology 12

Table 1 Truth table of a One-bit full adder cell.

Button State Output

A B Cin Carry Sum

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0
Fig. 3 shows the conventional full adder [3]
1 0 0 0 1
In a typical full adder, Sum is obtained through the XOR function
1 0 1 1 0 of the inputs, while the Carry is the same as the previous logic gate
when two of the inputs have the same state [3]. A multiplexer (MUX),
1 1 0 1 0 sometimes is being called as a data selector, is a component that choose
several analog or digital inputs and filter them into one output. [4]
1 1 1 1 1 further explains that the multiplexer is capable of altering parallel data
into serial data by redirecting such data from many inputs into one
output. The multiplexer comes in variety, with the different number of
inputs define each variation, such as 2 to 1 MUX, 4 to 1 MUX, 8 to 1
The truth table of a full adder is shown in Table 1. Through the MUX and 16 to 1 MUX. A multiplexer can be built using the logic
truth table, the Sum output can be summarized into a Boolean gates, in which the 4 to 1 Multiplexer is shown in the Fig. 4, with the
expression: Truth table of that multiplexer shown in Table 2.
Sum = A ⊕ B ⊕ Cin (1)

The carry-out (Cout or Carry) output meanwhile is summarized

into the Boolean expression as below
Carry = A. B + B.Cin + A.Cin (2)

[2] further explains the functionality of the full adder, in which that
any number of full adders can be linked together through the Carry-in
input and Carry-out outputs to form an n-bit addition, as illustrated on
Fig. 2:

Fig. 4. 4 to 1 Multiplexer built using Logic gates [4]

Table 2 Truth table of a 4 to 1 Multiplexer [4]

Inputs Output

A B Y

0 0 0

0 1 1

1 0 0

1 1 1

Fig. 2 4 Full adders being connected into a 4-bit adder. [4] also proposed that using multiplexers in a combinational
circuit can allow for a more cost-efficient and less complications, this
In a conventional full adder design, the circuit mainly consists of includes the use of multiplexers in a full adder. However, as more
two XOR gates, two AND gate and one OR gate. The design of the multiplexers is used, the delay of the full adder will increase as well
conventional full adder is shown in Fig. 3 below: due to the port-switching and extra I/O (Input/Output) signals that
increases as more multiplexers is added. Previous works have been
covered in [12] and [13] respectively.
 Zainuddin et al./ Malaysian Journal of Science and Advanced Technology 13

2. LITERATURE REVIEW the full adder to be more area efficient and low powered which uses
The variety of the design on a full adder is retrieved and compared Multiplexers into the design. [8] showcases their take on the full adder
from the other writers or authors that experiments with the same topics. design that uses six multiplexer gates, which will be then replaced with
[5] had designed a low power full adder high speed full adder that have two transistor Multiplexers that gives the MBA-T12 cell. Finally, [9]
better performance than the conventional full adder. [6] demonstrated also proposed another full adder design that also uses six Multiplexers
their quaternary full adder designs which also provides positive results gates with all of the internal gate nodes directly inputed with fresh
from the performance of their full adder design.[7] has their design on signal for faster transitions to output signals. The details on the design
of the full adders from the authors are mentioned further in table 3.

Table 3 Literature Review of Full Adder using CMOS Technology

No References Title Research Design Important Finding

1 [5] Design & Study Using six 2T multiplexers through the GDI The proposed full adder from the authors have
of a Low Power (Gate Diffusion Input), the authors design a low seen to have improvement in term of the full
High Speed power full adder circuit. The GDI technique adder delay, power and area coverage when
Full Adder provides with different types of logic function compared with the conventional full adder.
Using GDI using two transistor-based circuit arrangement.
Multiplexer A basic GDI will consist of 3 inputs and is made
up of one nMOS and one pMOS.

2 [6] A Novel The proposed full adder design uses quaternary The proposed full adder in the three-supply
Multiplexer- positive 2:1 multiplexer, quaternary 4:1 voltage case has low level of PDP, with the
Based multiplexer, quaternary successor, predecessor result being 1590 times lower than the
Quaternary Full and second level successor. In the full adder greatest recorded result. In a single supply
Adder design, the quaternary inverter is utilized as voltage case, the PDP is also reduced to about
in well. 3.04 of that of the best reported single supply
Nanoelectronics voltage design.

3 [7] Design of Area In the design of the full adder, the author uses The modified truncated multiplier improves
Efficient and the multiplexer based full adder into the much more in device utility through the
Low Power multiplier circuit which included the modified reduction of the area coverage when
Multipliers wallance and truncated multiplexers. The compared to modified Wallance multiplier,
using Wallance multiplier consists of partial product which offers up to 25% less area coverage as
Multiplexer by N2 AND gates, while the Truncated well as 10% less power and hence is
based Full multiplier uses constant correction method or considered an efficient in power dissipation
Adder variable correction procedure. reduction and maintaining less area coverage.

4 [8] A Novel Low The Authors introduce a 1-bit full adder design When comparing the proposed design to the
Power that uses six multiplexer gates. The multiplexer conventional design, the modified version is
Multiplexer- gates is replaced with 2-transistor Multiplexer shown to save more than 26% power when
Based Full that gives the MBA-T12 cell that in total use 12 testing under 6 different frequencies and
Adder Cell transistor to realize the 1-bit full adder design. loads using H-Spice.

5 [9] A Novel Low The proposed full adder design uses six Compared to the most power efficient 10-
Power identical Multiplexer gates which will be then transistor adders, the proposed design uses
Multiplexer- replace with 2 transistor circuit. All of the 23% less power and is 64% more faster than
Based Full internal gate nodes are directly inputted with the recorded fastest tested adders.
Adder fresh signals to create a faster transition into the
output signals.
 Zainuddin et al./ Malaysian Journal of Science and Advanced Technology 14

3. RESEARCH METHODOLOGY 3.3 Modified Full Adder version 2 (Using six 2:1 multiplexers).
Most of the research have discovered that when using
multiplexers in a full adder, the full adder improved in the power The proposed model for the Modified Full Adder version 2
usage, the speed of operation as well as the efficiency of the full using six multiplexers originated from the design of Fig. 6, where
adder. However, none of the research done suggest the optimum they use two 4 to 1 multiplexers. For the simulation, the design
design on the full adder when their research is completed and using two 4 to 1 Multiplexers is converted to six 2 to 1
provide the conclusion based on one design. Hence for research Multiplexers. The conversion from 4 to 1 multiplexer to 2 to 1
methodology in determine the optimum design of a full adder, three Multiplexers increases the area coverage of the overall circuit due
full adder design will be simulated using the DSCH Software which to the number of 2 to 1 multiplexer being triple the number of the
is followed up in the Microwind Software for simulation. 2 to 1 multiplexers on the Modified Full Adder version 1.

3.1 Conventional Full Adder

The design of the conventional full adder follows the default

full adder design, in which it uses Logic gates in the construction of
the full adder. Using 2 XOR gate, two AND gate and one OR gate,
the conventional full adder is built which contains three inputs (A,
B, Cin) and two output (Sum, Carry). The design of the
conventional full adder will follow Fig. 3 as a point of reference.
3.2 Modified Full Adder version 1 (Using two 2:1
multiplexers).

Using the proposed model from Maurya et al., the Modified

Full Adder version 1 will be constructed using two multiplexers.
Alongside the design, an XOR gate as well as a NOT gate is used
in this modified full adder. This work, according to Maurya et al.,
display the study on the Wallance tree multiplier and the truncated
multipliers in both this version of the full adder and the
conventional full adder, which suggests that the modified full adder Fig. 6 Design of the Modified Full Adder version 2.
occupies less area when compared to the conventional full adder.
Fig. 5 shows the design of the modified full adder version 1 that
uses 2 multiplexers [10].
4. RESULT AND DISCUSSIONS
The Schematics of the previously mentioned full adder
Designs were created in the DSCH Software and is then compiled
into the Microwind to check for the Power Usage and the Output
Delay for three full adder Design. The simulation results are
displayed from Fig. 7 until Fig. 15. Throughout the simulation,
the 0.6 Micron CMOS Technology is used to ensure that all three
full adder design are being tested in a similar environment and
that the comparison between the three designs can be made fair.
Additionally, 0.6 micron CMOS technology is used for the
purpose of electronics development which will acts as a signal
conditioning circuit in the three full adder designs, according to
[11].

Fig. 5 Modified Full Adder version 1 design.

Fig. 7. Schematic Circuit of the Conventional Full

Adder in DSCH.
 Zainuddin et al./ Malaysian Journal of Science and Advanced Technology 15

Fig. 11. Layout Circuit of the Modified Full Adder version 1

Fig. 8. Schematic Circuit of the Modified Full Adder version using two multiplexers in Microwind..
1 using two Multiplexer in DSCH.

Fig. 12. Layout Circuit of the Modified Full Adder version 2

using six multiplexers n Microwind.

Fig. 9. Schematic Circuit of the Modified Full Adder version 2

using Six Multiplexer in DSCH.

Fig. 13. Pulse Operation for the Conventional Full Adder.

Fig. 10. Layout Circuit of the Conventional Full Adder in

Microwind.

Fig. 14. Pulse Operation for the Modified Full Adder version 1
 Zainuddin et al./ Malaysian Journal of Science and Advanced Technology 16

ACKNOWLEDGEMENT
The research was supported by Manipal International
University's Department of Computer Science and Engineering
in Negeri Sembilan, Malaysia.

REFERENCES
[1] Z.Zain, ‘High Speed and Lowpower Gdi Based Full Adder’, J. VLSI
Circuits Syst., vol. 1, no. 1, Art. no. 1, Mar. 2019, doi:
10.31838/jvcs/01.01.02.
[2] I. Grout, ‘Introduction to Digital Logic Design’, in Digital Systems
Design with FPGAs and CPLDs, Elsevier, 2008, pp. 217–331. doi:
Fig. 15. Pulse Operation for the Modified Full Adder version 2 10.1016/B978-0-7506-8397-5.00005-2.
[3] R. Reddy R, ‘A Novel 1-Bit Full Adder Design Using DCVSL
In each of the Pulse Operation diagram from Fig. 13 to Fig 15, XOR/XNOR Gate and Pass Transistor Multiplexers’, Int. J. Innov.
the parameters of the I/O can be retrieved such as frequency, speed etc. Technol. Explor. Eng. IJITEE, vol. 2, pp. 142–146, Apr. 2013.
However, for the experiment, the value of the minimum time delay for [4] M. Bansal, H. Singh, and G. Sharma, ‘A Taxonomical Review of
both outputs (Sum and Carry) as well as the power usage is collected Multiplexer Designs for Electronic Circuits & Devices’, J. Electron.
and tabulated into a table format which is shown at Table 4. Inform., vol. 3, no. 2, pp. 77–88, Apr. 2021, doi: 10.36548/jei.2021.2.001.
[5] B. Mukherjee and A. Ghosal, ‘Design &amp; study of a low power high
speed full adder using GDI multiplexer’, in 2015 IEEE 2nd International
Table 4 Power Usage and Minimum Output Time Delay of each Full Conference on Recent Trends in Information Systems (ReTIS), Kolkata,
Adder Circuit India, Jul. 2015, pp. 465–470. doi: 10.1109/ReTIS.2015.7232924.
[6] E. Roosta and S. A. Hosseini, ‘A Novel Multiplexer-Based Quaternary
FULL ADDER VERSION MIN TIME MIN TIME POWER Full Adder in Nanoelectronics’, Circuits Syst. Signal Process., vol. 38, no.
DELAY IN DELAY IN USAGE 9, pp. 4056–4078, Sep. 2019, doi: 10.1007/s00034-019-01039-8.
CARRY SUM (PS) (MW)
[7] S. Murugeswari and S. K. Mohideen, ‘Design of area efficient and low
(PS)
power multipliers using multiplexer based full adder’, in Second
International Conference on Current Trends In Engineering and
Conventional Full Adder 159 162 2.393 Technology - ICCTET 2014, Coimbatore, India, Jul. 2014, pp. 388–392.
doi: 10.1109/ICCTET.2014.6966322.
Modified Full Adder Version 63 57 2.144
1 (Using 2 Multiplexer) [8] B. Alhalabi and A. Al-Sheraidah, ‘A novel low power multiplexer-based
full adder cell’, in ICECS 2001. 8th IEEE International Conference on
Modified Full Adder Version 117 1104 3.442 Electronics, Circuits and Systems (Cat. No.01EX483), Malta, 2001, pp.
2 (Using 2 Multiplexer) 1433–1436. doi: 10.1109/ICECS.2001.957484.
[9] Y. Jiang, A. Al-Sheraidah, Y. Wang, E. Sha, and J.-G. Chung, ‘A Novel
Multiplexer-Based Low-Power Full Adder’, Circuits Syst. II Express
Briefs IEEE Trans. On, vol. 51, pp. 345–348, Aug. 2004, doi:
Through the result gained from the simulation, the minimum time 10.1109/TCSII.2004.831429.
delay in the Version 1 of the full adder design is proven to be the [10] K. A. K. Maurya, Y. R. Lakshmanna, K. B. Sindhuri, and N. U. Kumar,
shortest for both the Carry output as well as the Sum output. When ‘Design and implementation of 32-bit adders using various full adders’,
compared to the conventional design, the time delay for the version 1 in 2017 Innovations in Power and Advanced Computing Technologies (i-
design for the Carry output is 60.38% less while for the Sum output is PACT), Vellore, Apr. 2017, pp. 1–6. doi: 10.1109/IPACT.2017.8245176.
64.81% less. In terms of power usage, the Version 1 design of the full [11] A. Solanki, K. Prasad, K. Nunan, and R. Oreilly, ‘Comparing process flow
adder is also shown to be the shortest as well, with 10% less power of monolithic CMOS-MEMS intergration on SOI wafers with monolithic
being used when compared with the conventional design. The BiMOS-MEMS integration on Silicon wafer’, in 2010 53rd IEEE
minimum time delay of the Carry output in the Version 2 design is also International Midwest Symposium on Circuits and Systems, Seattle, WA,
shorter when compared to the conventional design, with around USA, Aug. 2010, pp. 1189–1192. doi:
26.41% less time delay. However, when checking the minimum time 10.1109/MWSCAS.2010.5548876.
delay at the Sum output, the value is 10 times the time delay of that [12] Gamage, S. A., Subramaniam, K., & Zainuddin, A. A. (2022).
from the conventional design. The power usage for the Version 2 is Comparative Analysis of CMOS based Full Adders by Simulation in
higher than the conventional full adder as well, with 43.84% more DSCH and Microwind. Malaysian Journal of Science and Advanced
power being used. Technology, 183-187.
[13] Manokaran, P., & Zainuddin, A. A. (2022). Simulation of Low-Power
Shift Registers Using the MTCMOS Method with a Wide Selection of
5. CONCLUSION Transistors. Malaysian Journal of Science and Advanced Technology, 78-
83.
From the results, it is evident that the full adder that uses two
multiplexers is among the most optimal setup for a high efficiency full
adder construction since it uses less power but generate result with less
delay when compared to the other two design. The full adder also
occupies less area since it uses less components as well which
contributes to it using less power as well. Hence, when implementing
full adder for any system, it is recommended to use the modified full
adder design that uses the two multiplexers to improve the
performance of the systems, while producing the same logic as the
other two design which is based on the truth-table produced on the
result.