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Lab 3 - Inverter Layout Design

VLSI

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Ahmad Haziq
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35 views7 pages

Lab 3 - Inverter Layout Design

VLSI

Uploaded by

Ahmad Haziq
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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FAKULTI TEKNOLOGI DAN KEJURUTERAAN

ELEKTRONIK DAN KOMPUTER


UNIVERSITI TEKNIKAL MALAYSIA MELAKA

VLSI DESIGN & FABRICATION

BERC4804 SEMESTER 2 SESI 2023/2024

LAB 3: INVERTER LAYOUT DESIGN

NO. STUDENTS' NAME MATRIC. NO.

AHMAD HAZIQ BIN AHMAD LATFI B082110321


1.

MUHAMMAD HAIKAL BIN MOHD RIDZUAN B082110221


2.

3.

4.

PROGRAMME 3 BERC

SECTION / S1/1
GROUP
23/4/2024
DATE

1. DR MOHD SYAFIQ BIN MISPAN


NAME OF
INSTRUCTOR(S)
2.

EXAMINER’S COMMENT(S) TOTAL MARKS

1
5.0 RESULTS

1. Layout design

2
2. DRC

3
3. LVS

4
4. Parasitic netlist

5. Simulation waveform (with parasitics) with measured value of tpLH and tpHL.

5
6. Simulation waveform (without parasitics) with measured value of tpLH and tpHL.

6
7. Propagation delay comparison of pre-layout (without parasitics) and post-layout (with
parasitics) waveforms.
Table 5.1 : Propagation delay comparison.
Design tPLH (ns) tPHL (ns) tPD (ns)
Pre-layout (without parasitics) 0.0411 0.0251 0.0331

Post-layout (with parasitics) – PART A 1.9117 1.6565 1.7903


Post-layout (with parasitics) – PART D 2.0811 1.8227 1.9563

6.0 QUESTIONS AND DISCUSSION


Discuss the findings from the experiment.
 Explain your observation of propagation delay difference in Table 5.1.

From my observations the propagation delay tPLH and tPHL are larger for the post-layout
simulation compared to the pre-layout simulation. This is because the post-layout simulations
account for parasitic capacitances and resistances extracted from the actual layout, which slows
down the switching speeds of the transistors.

 Based on your learning experience in Lab 3, suggest the best layout practice(s) for designing
CMOS circuit for high speed application.

1) Use minimum size transistors to reduce parasitics

2) Make connections as short as possible to minimize wiring capacitance

3) Use higher metal layers(lower resistance)for critical signal paths

4) Follow design rules strictly to ensure manufacturing reliability

7.0 CONCLUSION
Conclude what you have learned in this lab session

In this lab, we learned how to design and simulate a basic CMOS inverter circuit using industry-standard VLSI
design tools. We created the layout adhering to design rules, performed verification checks like DRC and LVS,
extracted parasitic capacitances and resistances from the layout, and ran simulations accounting for these parasitic
effects. We observed how the layout parasitics significantly degraded the circuit speed compared to ideal pre-
layout simulations. We also saw how simply increasing the length of one metal connection further slowed down
the circuit timing. This lab gave insights into critical layout effects that must be considered for high-performance
integrated circuit design.

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