Digital Logic and Microprocessor Design Hwang

with Interfacing, 2E

Combinational
Circuits

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in part.
 Outline

 Analysis of Combinational Circuits

 Synthesis of Combinational Circuits
 Minimization, Boolean algebra and K-maps
 Timing Hazards and Glitches
 Example: BCD to 7-segment Decoder

2
 Analysis of Combinational
Circuit
 Analysis
 Given a circuit, we want to know its operation
 Describe operation using either
 Truth table x y z

 Boolean function
 Steps to create truth table
f

3
 Analysis of
Combinational Circuit
 Derive the truth table for this circuit:
A B C

4
 Analysis of
Combinational Circuit
 Derive the truth table for this circuit:
A B C
A B C P Q
0 0 0 0 1
0 0 1 1 1
P
0 1 0 0 0
0 1 1 0 1
1 0 0 0 0
Q
1 0 1 0 0
1 1 0 1 0
1 1 1 1 0

5
 Analysis of
Combinational Circuit
 Derive the Boolean function for this circuit:
x y z

x' y'
x'y'z

x'yz
x'y'z + x'yz + xy'z + xyz
f
xy'z

xyz

f = x'y'z + x'yz + xy'z + xyz

6
 Analysis of
Combinational Circuit
 Derive the Boolean function for this circuit:
x y z

f=?
g=?

7
 Analysis of
Combinational Circuit
 Using Boolean function
x y z

y' xy'

xy' + (y ⊕ z) x' (xy' + (y ⊕ z))

x' y⊕z
f

(x(y ⊕ z))'
g

f = x' (xy' + (y ⊕ z))

g = (x(y ⊕ z))'

8
 Synthesis of
Combinational Circuit
 Synthesis is the reverse of Analysis
 Given the operation of a circuit with either a
truth table or a Boolean equation
 Derive the circuit for it
 Example: construct a 3-bit unsigned
comparator circuit for the “greater than or
equal to 5” test

9
 Synthesis of
Combinational Circuit
 3-bit “greater than or equal to 5” comparator circuit
Decimal Binary number Output
number x2 x1 x0 f x2 x1 x0
0 0 0 0 0
1 0 0 1 0
2 0 1 0 0
3 0 1 1 0
4 1 0 0 0 f
5 1 0 1 1
6 1 1 0 1
7 1 1 1 1

f = x2x1'x0 + x2x1x0' + x2x1x0

10
 Synthesis of
Combinational Circuit
 Synthesize the circuit for this truth table
a b c x y
0 0 0 1 0
0 0 1 0 0
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 1
1 1 0 1 0
1 1 1 0 0

11
 Synthesis of
Combinational Circuit
 Synthesize the circuit for this truth table
a b c
a b c x y
0 0 0 1 0
0 0 1 0 0
0 1 0 1 1
x
0 1 1 1 0
1 0 0 0 1
1 0 1 1 1
1 1 0 1 0 y

1 1 1 0 0

12
 Synthesis of
Combinational Circuit
 Optimize this circuit
a b c a b c

x x

y y

13
 Minimization of
Combinational Circuits
 Optimize circuit size, speed, and power
 How to optimize? One to one map from Boolean
to Circuit
 From Canonical to Standard to Non-Standard
 Methods
 Boolean algebra – theoretical – difficult
 Karnaugh maps – easy, but only for few variables
 Tabulation method – best for computer

14
 Boolean Algebra
 Minimize a sum-of-minterms format,
reduce the number of product terms
 This is done by factoring out the
common variable(s).

F = xy'z' + xyz'
= xz' (y' + y)
= xz' 1
= xz'

15
 Boolean Algebra
 Reducing the number of product terms
 will reduce the number of inputs to the OR gate
 will reduce the number of AND gates
 Reducing the number of variables
 will reduce the number of inputs to the AND
gate

16
 Boolean Algebra
 Sometimes it is advantageous to duplicate a
product term one or more times in an equation
F = x'yz' + x'yz + xyz'
= x'yz' + x'yz + xyz' + x'yz' (duplicate x'yz')
= (x'yz' + x'yz) + (x'yz' + xyz')
= x'y(z' + z) + yz' (x' + x)
= x'y 1 + yz' 1
= x'y + yz'
= y(x' + z')

17
 Karnaugh Maps (K-Maps)
 A K-map provides a simple and
straightforward procedure for combining
product terms
 Minterms are grouped so that we can easily
see which of the minterms can be combined
 Adjacent squares differ in the value of only
one bit
 Use minterm numbers for easy reference

18
 Karnaugh Maps (K-Maps)
y yz
x 0 1 x 00 01 11 10
0 1 0 1 3 2
0 x'y' x'y 0 x'y'z' x'y'z x'yz x'yz'

2 3 4 5 7 6
1 xy' xy 1 xy'z' xy'z xyz xyz'

yz v=0 v=1
yz
wx 00 01 11 10 wx 00 01 11 10 00 01 11 10
0 1 3 2 0 1 3 2 16 17 19 18
00 w'x'y'z' w'x'y'z w'x'yz w'x'yz' 00 v'w'x'y'z' v'w'x'y'z v'w'x'yz v'w'x'yz' vw'x'y'z' vw'x'y'z vw'x'yz vw'x'yz'
4 5 7 6 4 5 7 6 20 21 23 22
01 w'xy'z' w'xy'z w'xyz w'xyz' 01 v'w'xy'z' v'w'xy'z v'w'xyz v'w'xyz' vw'xy'z' vw'xy'z vw'xyz vw'xyz'

12 13 15 14 12 13 15 14 28 29 31 30
11 wxy'z' wxy'z wxyz wxyz' 11 v'wxy'z' v'wxy'z v'wxyz v'wxyz' vwxy'z' vwxy'z vwxyz vwxyz'

8 9 11 10 8 9 11 10 24 25 27 26
10 wx'y'z' wx'y'z wx'yz wx'yz' 10 v'wx'y'z' v'wx'y'z v'wx'yz v'wx'yz' vwx'y'z' vwx'y'z vwx'yz vwx'yz'

19
 Equality of Boolean
equations and K-map
F= x'y' + x'y + xy
x'y' + x'y = x' (y' + y) = x' (1) = x'
F
y
x 0 1 x'y + xy = (x' + x) y = (1) y = y
0 1
0 1 1

2 3 F
1 1 y x'
x 0 1
0 1
0 1 1

2 3
1 1
y
20
 Subcube
 Subcube is a rectangle of adjacent 1-minterms:
 Must be rectangular in shape
 Number of 1-minterms enclosed must be a power of two

F F z
yz x' yz F
yz x'y' x'z
x 00 01 11 10 x 00 01 11 10 x 00 01 11 10
0 1 1 1 1 0 1 1 0 1 1 1
y'z
1 1 1 1 1 1

2-subcube F
yz
x'z' F
yz
y'z
wx 00 01 11 10 wx 00 01 11 10
00 1 1 00 1
F z'
yz
x 00 01 11 10 01 01 1

0 1 1 11 11 1

1 1 1 10 1 1 10 1

21
 Subcube
v'w'xz' w'xy'z'
F yz v=0 v=1
wx 00 01 11 10 00 01 11 10
0 1 3 2 16 17 19 18
00
4 5 7 6 20 21 23 22
01 1 1 1

12 13 15 14 28 29 31 30
11 1 1 1 1

8 9 11 10 24 25 27 26
10 1 1 1 1

wz

 Find as few subcubes as possible to cover all of the 1-

minterms
 The size of the subcube should be as big as possible

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Procedure of using K-map
FF
yz yz w'x'z'
 Draw k-map wxwx 00 0001 0111 11 10 10
0 1 3 2

Find prime implicant 00 1 0 1 13 2

 00
4
1
5 7 6
1

01 41 15 7 6x'yz'
 Find essential PI 01
11
12
121
13
1
15
1
13
1
1
15
14
14
11 wyz'
Create minimum cover
1 1 10 1
 10
8
8
9 11
9
1
11 10
10 1
 Get the list xz wxy
1-minterm Prime Implicant Essential PI
m0 w'x'z' w'x'z'
m2 w'x'z', x'yz'
F = w'x'z' + xz + wyz' m5 xz xz
m7 xz xz
m10 x'yz', wyz'
F = z' (w'x' + wy) + xz m13 xz xz
m14 wyz', wxy
m15 xz

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 Don’t Care items
 don’t-care: minterms we do not care whether their values
are a 0 or a 1
 A function can be reduced even further using don’t-cares
 Example:
 1-minterms: m0, m1, m2, m3, m4, m7, m8, and m9
 ×-minterms: m10, m11, m12, m13, m14, and m15
F
yz
wx 00 01 11 10
00 1
0
1
1
1
3
1
2
F = x' + yz + y'z'
4 5 7 6 x'
01 1 1
y'z' yz
12 13 15 14
11 × × × × F = x' + (y  z)
8 9 11 10
10 1 1 × ×

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 Tabulation Method
 K-map is only good for at most maybe 5 variables
 With more than 5 variables it becomes difficult to visualize
how the minterms should be combined into subcubes
 Other methods i.e., Tabulation Method also known as
Quine-McCluskey method for 6 and more variables is used,
which is suitable for computer programs (for reference see
Hwang, 2nd edition, pg.87)

25
 K-Map
Use the K-map method to simplify this equation:
F(w, x, y, z) = Σ(1, 2, 4, 5, 7, 13, 14)

F
yz
wx 00 01 11 10
00 1 1

01 1 1 1

11 1 1

10

26
Time Hazards and Glitches
 Functional analysis VS Timing analysis (Ideal circuit VS
actual implementation)
 Timing hazards are problems in a circuit as a result of
timing issues.
 A glitch is when a signal is expected to be stable (from a
functional analysis), but it changes value for a brief
moment and then goes back to what it is expected to be.
d0
d1
d0 s'd0 s

s s' y s'
s'd0
d1 sd1 sd1
y
t0 t1 t2 t3

27
Time Hazards and Glitches
 Glitches are caused by multiple sources having paths of
different delays
 A glitch can be eliminated by adding an extra prime
implicant
 Equivalent to adding an extra path between the source and
the destination
y dd s'd0 y dd s'd0 d0 s'd0
1 0 1 0
s 00 01 11 10 s 00 01 11 10 s
0
sd1
0 1 1 1 1
d1 y
1 1 1 1 1 1

sd1 d1d0 sd1 d 1d 0

28
 Using Glitch for One-shot
pulse
 A circuit that outputs a single, short pulse when given an
input of arbitrary time length is known as a one-shot.
Input Output
A

Delay through
the Inverters
Input
A
Output
Delay through
the AND gate

29
BCD to 7-Segment Decoder
 Converts a 4-bit binary coded decimal (BCD) input to
seven output signals for turning on the seven LEDs in a
7-segment LED display
 A typical combinational circuit synthesis problem

f g b

e c

30
BCD to 7-Segment Decoder

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BCD to 7-Segment Decoder

32
BCD to 7-Segment Decoder

33
BCD to 7-Segment Decoder

34
 Conclusions

 Analysis of Combinational Circuits

 Synthesis of Combinational Circuits
 Minimization, Boolean algebra and K-maps
 Time Hazards and Glitches
 Example: BCD to 7-segment Decoder

35