Department of Electrical Engineering – ITU

EE233L: Digital Logic Design Lab

Course Instructor: Hussnain Riaz Dated: 06 – 12 – 2023

Lab Engineer: Muhammad Kashif Semester: Fall 2023

Batch: BSEE 22

LAB 13 Open Ended Lab: Implementation of ALU

Checked on: __________________________

Signature: __________________________
 13.1. Introduction
This lab requires the students to use their knowledge of digital systems thereby performing the implementation key digital circuits
such as combinational circuits. The students specifically are required to implement Arithmetic Logic Unit (ALU) in Verilog.

13.2. Objectives
The aforementioned ALU should perform
• Addition
• Subtraction
• Bitwise and
• Bitwise or
• Bitwise XOR

13.3. Conduct of Lab

You can work and get evaluated in groups of two. However, manual submission has to be separate.
If there is difficulty in understanding any aspect of the lab, please seek help from the lab engineer or the TA.
If a lab task contains an instruction to show the work to lab engineer, make sure that the lab engineer evaluates and marks on
your manual for that task. If your manual is unmarked for this task, it can result in mark deduction.
All tasks must be evaluated within the lab time. Submit the lab manual before leaving the lab.

13.4. Design Requirements

Your ALU design should include the following components:
1. An adder
2. A subtractor.
3. 4-bit logic gates for AND, OR, and XOR operations.
4. A 3-to-8 decoder to select the appropriate operation based on the Opcode input.
5. Flip-flops to store intermediate and final results.

Report
"Verilog Implementation of a Comprehensive Arithmetic Logic Unit (ALU) with
Multi-Function Capabilities"
Introduction

ALU_Testbench Module:
This module serves as a testbench for the MAIN_ALU module. It provides inputs to the ALU and observes the results for different
operations. The specified operations include addition, subtraction, bitwise AND, bitwise OR, and bitwise XOR. The testbench
includes a clock (Clk), inputs (X, Y, ALUOp, Cin), and outputs (Output, Cout).
Adder Module:
This module implements a 4-bit adder. The sum output represents the sum of two inputs (x and y) along with a carry-in (cin). The
cout output indicates the carry-out from the most significant bit.
MAIN_ALU Module:
The main Arithmetic Logic Unit (ALU) module incorporates various components to perform different operations based on the given
ALUOp input. It includes an adder (Task1), a subtractor (Task2), logic to select operations based on ALUOp, and outputs (Output,
Cout). The ALU operates on the rising edge of the clock (Clk).
Decoder Module:
The decoder module takes a 3-bit input (A) and produces an 8-bit output (Y). The output represents a binary selection based on the
input. It is used to convert the 3-bit ALUOp into an 8-bit control signal for the ALU operations.
FlipFlop Module:
This module implements a simple D flip-flop. The output Q is updated on the rising edge of the clock (CLK) based on the input
data (D).
Subtractor Module:
Similar to the Adder module, this module implements a 4-bit subtractor. It calculates the difference (Diff) and the borrow-out
(Yout) based on the inputs (X, Y, Yin).
LogicGates Module:
This module performs basic logic operations on 4-bit inputs X and Y. It produces outputs for AND (AND_out), OR (OR_out), and
XOR (XOR_out) operations.
Summary:
The provided Verilog code collectively represents a comprehensive implementation of an Arithmetic Logic Unit (ALU) with the
capability to perform addition, subtraction, bitwise AND, OR, and XOR operations. The design is modular, with separate modules
for different components, enhancing readability and maintainability. The testbench (ALU_Testbench) allows for the validation of
the ALU functionality under various scenarios.

The importance of the problem addressed in this lab lies in its practical application and relevance to digital systems and computer
architecture. Here are some key points highlighting the significance of implementing an Arithmetic Logic Unit (ALU) with the
specified functionalities:
1. Core Component of CPUs:
• The ALU is a fundamental building block of central processing units (CPUs) in computers. It performs essential
arithmetic and logical operations required for the execution of programs and processing of data.
2. Versatile Operation:
• By incorporating addition, subtraction, bitwise AND, OR, and XOR operations, the designed ALU becomes a
versatile component capable of handling a wide range of computational tasks. This versatility is crucial for
supporting diverse applications and algorithms.
3. Digital System Design Understanding:
• The lab task requires students to apply their knowledge of digital systems and combinational circuits. Designing
an ALU involves understanding how different components work together to execute operations, contributing to a
deeper comprehension of digital system design principles.
4. Coding and Implementation Skills:
• Implementing the ALU in Verilog challenges students to translate theoretical knowledge into practical coding
skills. This hands-on experience is invaluable for future engineers and computer scientists, as it enhances their
ability to design and implement complex digital systems.
5. Problem-Solving Skills:
• Students need to address the challenge of integrating various components, including adders, subtractors, logic
gates, decoders, and flip-flops, to create a functional ALU. This problem-solving exercise enhances their
analytical and design skills.
6. Understanding Opcode-Based Operation:
• The inclusion of a 3-to-8 decoder to select operations based on Opcode input reflects real-world CPU design. This
aspect of the lab emphasizes the importance of understanding how control signals and decoders are used to execute
different instructions in a CPU.
7. Group Collaboration and Individual Accountability:
• Allowing group work encourages collaboration, simulating real-world scenarios where engineers often work in
teams. However, individual manual submissions promote accountability, ensuring that each student understands
and can independently demonstrate their knowledge.
8. Time Management:
 • The requirement to complete all tasks within the lab time emphasizes the importance of time management in
engineering projects. Meeting deadlines is a crucial skill in professional settings.
In summary, this lab tackles a fundamental problem in computer engineering, providing students with hands-on experience in
designing and implementing a crucial component of digital systems. The skills developed in this lab are directly applicable to real-
world scenarios in computer architecture and digital system design.

13.4.1. Material and Method

1. ALU_Testbench Module:
• Inputs:
• X and Y: 4-bit input operands.
• ALUOp: 3-bit ALU operation code.
• Cin: Carry input.
• Clk: Clock signal.
• Outputs:
• Output: 4-bit output result.
• Cout: Carry output.
• Behavior:
• Sequentially tests the ALU for different operations using a clock (Clk) and specified inputs.
• Tests include addition, subtraction, bitwise AND, OR, and XOR.
• Outputs results and carries are observed after a specified clock cycle.

2. Adder Module:
• Inputs:
• x and y: 4-bit input operands.
• cin: Carry input.
• Outputs:
• sum: 4-bit sum output.
• cout: Carry output.
• Behavior:
• Computes the sum and carry-out using bitwise XOR and AND operations.

3. MAIN_ALU Module:
• Inputs:
• X, ALUOp, Y: 4-bit input operands and 3-bit operation code.
• Cin: Carry input.
• Clk: Clock signal.
• Outputs:
• Output: 4-bit output result.
• Cout: Carry output.
• Behavior:
• Utilizes a decoder to choose the appropriate operation based on the ALUOp.
• Instantiates an adder (Task1) and a subtractor (Task2).
• Outputs the result and carry based on the selected operation.

4. Decoder Module:
• Inputs:
 • A: 3-bit input representing ALU operation code.
• Outputs:
• Y: 8-bit output representing the control signal for ALU operations.
• Behavior:
• Decodes the 3-bit input to an 8-bit output, where each bit corresponds to a specific ALU operation.

5. FlipFlop Module:
• Inputs:
• D: Data input.
• CLK: Clock signal.
• Outputs:
• Q: Flip-flop output.
• Behavior:
• Updates the output Q on the rising edge of the clock (CLK) based on the input data (D).

6. Subtractor Module:
• Inputs:
• X and Y: 4-bit input operands.
• Yin: Borrow input.
• Outputs:
• Diff: 4-bit difference output.
• Yout: Borrow output.
• Behavior:
• Computes the difference and borrow-out using bitwise XOR and AND operations.

7. LogicGates Module:
• Inputs:
• X and Y: 4-bit input operands.
• Outputs:
• AND_out, OR_out, XOR_out: Outputs of bitwise AND, OR, and XOR operations.
• Behavior:
• Performs basic logic operations on the input operands.
These modules collectively create a modular and functional ALU, with a testbench (ALU_Testbench) to validate its correct
behavior under various scenarios. Each module contributes to the overall functionality of the ALU, implementing specific
components and operations in a modular and organized manner.
CODES:
13.4.2. Results

13.4.3. Conclusion
In this lab, a comprehensive implementation of an Arithmetic Logic Unit (ALU) in Verilog has been achieved. The designed ALU
is capable of performing key operations such as addition, subtraction, bitwise AND, OR, and XOR. The modular approach to the
design, using separate modules for different components, enhances readability, maintainability, and overall understanding of the
digital system.
The key components of the ALU include adders, subtractors, logic gates, decoders, and flip-flops. These components work together
to execute operations based on the specified 3-bit ALU operation code (ALUOp). The design adheres to good coding practices,
incorporating meaningful names for modules, signals, and operations.
A testbench (ALU_Testbench) has been provided to verify the correct functionality of the ALU under different scenarios. The test
cases include addition, subtraction, bitwise AND, OR, and XOR operations, ensuring that the ALU operates as expected.
The use of a decoder (Decoder module) facilitates the interpretation of the 3-bit ALU operation code, converting it into an 8-bit
control signal for the ALU operations. This approach allows for extensibility, making it easier to add new operations in the future.
In summary, this lab provides students with valuable hands-on experience in designing a versatile ALU, a fundamental component
of digital systems and computer architecture. The modular design, thoughtful use of control signals, and the inclusion of a testbench
contribute to a well-rounded learning experience in digital system design and Verilog programming. Students are encouraged to
further explore and optimize the design, extending its capabilities or implementing additional features for a deeper understanding
of digital circuit design.
 Assessment Rubric
Method:
Lab report evaluation and instructor observation during lab sessions.

Able to complete the Able to complete the Tasks completion below

Performance CLO Marks
tasks over 80% (4-5) tasks 50 – 80% (2-3) 50% (0-1)
Incapable of understanding
Conceptually understands Needs guidance to
the purpose of the
1. Realization of the topic under study and understand the purpose of
1 experiment and
experiment develops the experimental the experiment and to
consequently fails to
setup accordingly develop the required setup
develop the required setup
Actively engages and
Cooperates with other group Distracts or discourages
cooperates with other group
2. Teamwork 1 members in a reasonable other group members from
members in an effective
manner conducting the experiments
manner
Sets up hardware/software
Unable to set up
properly according to the Makes minor errors in
3. Conducting experimental setup, and
3 requirement of experiment hardware/software setup and
experiment perform the procedure of
and examines the output observation of output
experiment
carefully
Observes lab safety rules;
4. Laboratory handles the development
Observes safety rules and
safety and board and other components Disregards lab safety and
1 disciplinary guidelines with
disciplinary with care and adheres to the disciplinary rules
minor deviations
rules lab disciplinary guidelines
aptly
Completes data collection
from the experiment setup Completes data collection Fails at collecting data by
by giving proper inputs and with minor errors and enters giving proper inputs and
5. Data
3 observing the outputs, data in lab report with slight observing output states of
collection
complies with the deviations from provided experiment setup, unable to
instructions regarding data guidelines fill the lab report properly
entry in manual
Analyzes the data obtained
Unable to establish the
from experiment thoroughly Analyzes data with minor
relationship between
and accurately verifies it error and correlates it with
practical and theoretical
with theoretical theoretical values
6. Data analysis 3 values and lacks the
understanding, accounts for reasonably. Attempts to
theoretical understanding to
any discrepancy in data from account for any discrepancy
explain any discrepancy in
theory with sound in data from theory
data
explanation, where asked

Successfully uses lab PC and Does not know how to use

Requires assistance in
internet to look for relevant computer to look up
looking for IC datasheets
7. Computer use 3 datasheets, carry out datasheets or carry out
and carrying out calculation
calculations, or verify results calculation and simulation
and simulation tasks
using simulation tasks

Total (out of 35)