Department of Electrical Engineering – ITU

EE233L: Digital Logic Design Lab

Course Instructor: Hussnain Riaz Dated: 22 – 11 – 2023

Lab Engineer: Muhammad Kashif Semester: Fall 2023

Batch: BSEE 22

LAB 11 Sequential Circuits: 4-bit Universal Shift Register with

Parallel Load and Left/Right Shift Operations

Name Roll Number Lab Marks

Checked on: __________________________

Signature: __________________________
 Sequential Circuits: 4-bit Universal Shift Register with Parallel
Load and Left/Right Shift Operations
11.1. Introduction
This lab exercise aims to develop an understanding of the working of a universal shift register and its different modes of
operation. In one task, pseudo-random number sequence is generated by use of shift register and XOR gate and in another a
Johnson counter is designed and tested using a shift register.

11.2. Objectives
This lab will enable the students to achieve the following:
• Understand the shift operation and the construction and working of a shift register
• Demonstrate parallel load, shift left and shift right operations in a universal shift register
• Generate pseudo-random numbers using shift registers
• Design and test the operation of a Johnson counter using shift register

11.3. Conduct of Lab

All tasks of this lab have to be performed using the logic trainer in Embedded Lab.
Bring printout of this lab manual when you come to perform the lab.
You can work and get evaluated in groups of two. However, manual submission has to be separate.
If there is difficulty in understanding any aspect of the lab, please seek help from the lab engineer or the TA.
If a lab task contains an instruction to show the work to lab engineer, make sure that the lab engineer evaluates and
marks on your manual for that task. If your manual is unmarked for this task, it can result in mark deduction.
All tasks must be evaluated within the lab time. Submit the lab manual before leaving the lab.

11.4. Theory and Background

11.4.1. Register
A register is a group of flip-flops that can store binary information. One flip-flop can store one bit. An n-bit register has n
flip-flops and stores n-bits of binary information.
11.4.1.1. Shift register
In addition to flip-flops, a register also has logic gates that determine how the data in the register is to be processed. A register
with combinational logic gates that has the ability to shift its data from right to left or left to right is called a shift register.
Depending on the combinational logic circuit used in the shift register, it may have operations of parallel load, serial input,
clear, right shift and left shift etc.

11.5. Lab Tasks

11.5.1. Task 1: Universal shift register [Marks: 4]

A universal shift register is a special type of shift register that is capable of performing the following four operations:
- Load parallel input
- Shift right with serial input from left
- Shift left with serial input from right
- Hold output
 To select one of the four modes, there are two select inputs S1 and S0. 74194 is a 4-bit bidirectional universal shift
register. Its pin configuration is as below:

Figure 11.1: Pin configuration of 74194

S0-S1: Mode selection inputs

Clear (Active-Low): Stores 0 in all bits of the register asynchronously
Shift right serial input (SIR): Serial input when right shift mode is selected
A, B, C, D: Parallel outputs
Shift left serial input (SIL): Serial input when left shift mode is selected
A, B, C, D: Parallel inputs; these will be loaded into the shift register when parallel input mode selected
QA-QD: Parallel outputs
Clock: Positive-edge of the clock triggers the register
Connect this circuit on breadboard according to the following figure, where all keys are to be connected to switches and
OA – OD are to be connected to the state monitor LEDs of your logic trainer.

Figure 11.2: Multisim circuit to test the operation of 74194 shift register

At every clock pulse, change inputs according to Table 11.1. Apply inputs in the same order as given in this table. Keep
the clock frequency very low so that you get time to observe current outputs of the register and also to change inputs in
between consecutive clock pulses. Enter your observed outputs under columns QA, QB, QC and QD. [4]
Table 11.1: Operation of shift register IC 74194

S1 S0 SIR SIL A B C D Clock QA QB QC QD Mode of operation

1 1 X X 1 1 0 1 ↑ 1 1 0 1 Parallel load
0 1 1 X X X X X ↑ 1 1 1 0
0 1 1 X X X X X ↑ 1 1 1 1
Right-shift
0 1 0 X X X X X ↑ 0 1 1 1
0 1 0 X X X X X ↑ 0 0 1 1
1 0 X 1 X X X X ↑ 0 1 1 1
1 0 X 1 X X X X ↑ 1 1 1 1
Left-shift
1 0 X 0 X X X X ↑ 1 1 1 0
1 0 X 0 X X X X ↑ 1 1 0 0
0 0 X X X X X X ↑ 1 1 0 0 Output-hold
 Give answer to question 1 of Analysis.

11.5.2. Task 2: Linear-feedback shift register (LFSR) [Marks: 7]

Figure 11.3 shows a circuit designed to work as a 4-bit Fibonacci linear-feedback shift register (LFSR). LFSR can
generate a pseudo-random sequence of binary numbers.

Figure 11.3: Linear Feedback Shift Register (LFSR)

Build this circuit on breadboard using the universal shift register IC 74194 and XOR gate IC 7486. [3]
When running the circuit, initially select parallel load mode of the shift register and load 0001 in the register.
Then, select the right-shift mode of the shift register. Note down the 4-bit output after each positive edge of the clock in
Table 11.2 and show working hardware to the lab engineer to obtain credit. [4]
Table 11.2: Random numbers generated using LSFR

Clock edge 4-bit output Clock edge 4-bit output

1 0001 17 1000
2 1000 18 0100
3 0100 19 0010
4 0010 20 1001
5 1001 21 1100
6 1100 22 0110
7 0110 23 1011
8 1011 24 0101
9 0101 25 1010
10 1010 26 1101
11 1101 27 1110
12 1110 28 1111
13 1111 29 0111
14 0111 30 0011
15 0011 31 0001
16 0001 32 1000
Give answer to question 2 of Analysis.

11.5.3. Task 3: Johnson counter using shift register [Marks: 9]

A Johnson counter is a special type of ring counter. A 3-bit Johnson counter outputs the following 3-bit sequence (Table
11.3) in 6 clock cycles and then repeats.
 Table 11.3: 3-bit Johnson counter

Clock edge O2 O1 O0
1 0 0 0
2 1 0 0
3 1 1 0
4 1 1 1
5 0 1 1
6 0 0 1
7 (Repeat) 0 0 0
Design a 4-bit Johnson counter using a shift register and additional combinational logic circuitry. Draw the logic diagram
of your design in the following box: [3]

Build circuit on breadboard according to your proposed design diagram. [2]

Power up the circuit and note down the output of your shift register at each clock edge starting with 0000 in Table 11.4.
Also, show working hardware to the lab engineer to obtain credit. [4]
Table 11.4: 4-bit Johnson counter

Clock edge O3 O2 O1 O0
1 0 0 0 0
2 1 0 0 0
3 1 1 0 0
4 1 1 1 0
5 1 1 1 1
6 0 1 1 1
7 0 0 1 1
8 0 0 0 1
9 0 0 0 0
10 1 0 0 0
Give answer to question 3 of Analysis.

11.5.4. Analysis [Marks: 5]

Does the output of your table indicate correct working according to the stated mode of operation in the last column?
[1]
This circuit generates a sequence of random numbers and repeats the sequence after a certain number of clock cycles.
State below your observations; specifically state the number of clock cycles after which the sequence repeats itself.
[2]

Looking at Table 11.3 and Table 11.4, can you suggest a formula for the number of clock cycles after which an n-bit
Johnson counter repeats itself? Please state below along with reasoning. [2]
 Assessment Rubric
Method:
Lab report evaluation and instructor observation during lab sessions.

Able to complete the Able to complete the Tasks completion

Performance CLO Marks
tasks over 80% (4-5) tasks 50 – 80% (2-3) below 50% (0-1)
Incapable of understanding
Conceptually understands Needs guidance to
the purpose of the
1. Realization the topic under study and understand the purpose of
1 experiment and
of experiment develops the experimental the experiment and to
consequently fails to
setup accordingly develop the required setup
develop the required setup
Actively engages and Distracts or discourages
Cooperates with other
cooperates with other other group members from
2. Teamwork 1 group members in a
group members in an conducting the
reasonable manner
effective manner experiments
Sets up hardware/software
Unable to set up
properly according to the Makes minor errors in
3. Conducting experimental setup, and
2 requirement of experiment hardware/software setup
experiment perform the procedure of
and examines the output and observation of output
experiment
carefully
Observes lab safety rules;
handles the development
4. Laboratory
board and other Observes safety rules and
safety and Disregards lab safety and
1 components with care and disciplinary guidelines
disciplinary disciplinary rules
adheres to the lab with minor deviations
rules
disciplinary guidelines
aptly
Completes data collection
Fails at collecting data by
from the experiment setup Completes data collection
giving proper inputs and
by giving proper inputs with minor errors and
5. Data observing output states of
2 and observing the outputs, enters data in lab report
collection experiment setup, unable
complies with the with slight deviations from
to fill the lab report
instructions regarding data provided guidelines
properly
entry in manual
Analyzes the data obtained
Analyzes data with minor Unable to establish the
from experiment
error and correlates it with relationship between
thoroughly and accurately
theoretical values practical and theoretical
6. Data verifies it with theoretical
2 reasonably. Attempts to values and lacks the
analysis understanding, accounts
account for any theoretical understanding
for any discrepancy in data
discrepancy in data from to explain any discrepancy
from theory with sound
theory in data
explanation, where asked

Successfully uses lab PC Requires assistance in Does not know how to use
and internet to look for looking for IC datasheets computer to look up
7. Computer
2 relevant datasheets, carry and carrying out datasheets or carry out
use
out calculations, or verify calculation and simulation calculation and simulation
results using simulation tasks tasks

Total (out of 35)