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Adder

notes from digital electronics about adder.

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Mohammad Rafi Hurriyet
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18 views17 pages

Adder

notes from digital electronics about adder.

Uploaded by

Mohammad Rafi Hurriyet
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Program: B.Tech.,EE.

, Semester III, Year II


ECL0306: Digital Electronics
Unit III
ADDERS
Lecture No. XIX
Abhishek Tripathi

Assistant Professor, SOET/EE


Outlines
• Prerequisites
• Real life examples
• Objectives
• Half Adder
• Full Adder
• Implementation
• Performance
• Ripple carry adder
• Exercise
• Learning Outcomes
• References
Prerequisites

• Knowledge of K-Map.
• Knowledge of Binary arithmetic.
•Knowledge of logic gates.
Real life examples
Adders & Subtractors are wildly used in in computer's ALU (Arithmetic
logic unit) to compute addition as well as CPU (Central Processing unit)
and GPU (Graphics Processing unit) for graphics applications to reduce
the circuit complexity.
Adders
◼ The most basic arithmetic operation in a digital computer is
addition.
◼ Half Adder is a combination circuit that performs addition of 2 bits.

Inputs Outputs
a b Carry Sum
0 0 0 0 Sum = ab + ab = a  b
0 1 0 1
Carry = ab
1 0 0 1
1 1 1 0

< SELO 5> <Reference.: R1,R2>


Half Adder

Sum = ab + ab = a  b
Carry = ab

◼ Half adders cannot accept a carry input and hence it is not possible
to cascade them to construct an n-bit binary adder.
< SELO 5> <Reference.: R1,R2>
Full Adder
◼ Full Adder is a combinational circuit that forms the arithmetic sum of
three input bits. It is described by the following truth table:

Inputs Outputs
c b a Cout Sum
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
Sum = abc + abc + abc + abc = a  b  c
Cout = ab + ac + bc =ab + c (a + b)

< SELO 5> <Reference.: R1,R2>


Full Adder Implementation - 1

Sum = abc + abc + abc + abc = a  b  c


C out = ab + ac + bc = ab + c (a + b)

ai bi
ai
si bi
Full
Adder
ci+1 (FA)
ci
ci+1 ci
si
Full Adder at bit i

< SELO 5> <Reference.: R1,R2>


Full Adder Implementation - 2
◼ A full adder can be implemented using 2 half adders and an OR gate

ai
si bi

ci+1 ci

ai bi

Full
Adder
ci+1 ci
(FA)

si
< SELO 5> <Reference.: R1,R2>
Performance of a Full Adder

◼ Use a 2-input NAND gate implementation of a 1-bit full adder.

< SELO 5> <Reference.: R1,R2>


Ripple Carry Adder
◼ 4-bit Binary Adder: ( Sum = A + B )
◼ A 4-bit binary adder can be implemented by cascading four 1-bit full
adders as follows:
◼ Inputs: A = (a3a2a1a0) Outputs: Sum = (s3s2s1s0)
B = (b3b2b1b0)
Cout = c4
Cin = cin = c0

< SELO 5> <Reference.: R1,R2>


Performance of an n-bit Ripple Carry
Adder

◼ Carry ripples from input co to output cn


◼ Worst case propagation delay for sum in terms of 2-input NAND gate

i=1 2 + 3 = 5 + 2(n − 2)+ 3 = 2n + 4


tsum = 5 +  n−2
delay (1 gd) is given by,
◼ Worst case propagation delay for carry output is given by,
tcarry = delay for cn−1 + 2 = 5 +  n−2
i=1 2 + 2 = 2n + 3

◼ Therefore, propagation delay for an n-bit Ripple Carry Adder is O(n).

< SELO 5> <Reference.: R1,R2>


Exercises

◼ Design a signed comparator for comparing two 4-bit 1’s


• complement numbers A and B
 If A > B, the circuit should produce 1 as output, otherwise 0

◼ Design a signed comparator for comparing two 4-bit 2’s


• complement numbers A and B
 If A > B, the circuit should produce 1 as output, otherwise 0

◼ Design an n-bit absolute (ABS) value generator for 2’s complement


represented numbers, i.e.,for an n-bit input, X, the output is |X|

< SELO 5>


Objectives

•To acquire the basic knowledge of digital logic levels and application of
knowledge to understand digital electronics circuit.
Learning Outcomes
Students will be able to learn and understand:
Concept of Adder in detail.
Concept of look ahead carry.
References

1. Digital Design (4th Edition) by M. Morris Mano, Michael D. Ciletti


2. An engineering approach to digital design Fletcher, William I.

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