Collision Free Scheduling

 To avoid collisions and to achieve maximum throughput, all the tasks that are waiting in the ready
queue for initiation, should be scheduled properly.
 When scheduling tasks in a non-linear pipeline, the main objective is to obtain the shortest average
latency between initiations without causing collisions.

 Following are the steps to obtain this:

1. Collision vector calculation (Determines from forbidden and permissible latencies)

2. State transition diagram

3. Simple cycles and Greedy cycles

4. MAL (Minimum Average Latency)

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 1. Collision Vector
 The collision vector is a method of analyzing how often we can initiate a new operation into the
pipeline and maintain synchronous flow without collision (means permissible state).
 It is a m-bit binary vector C =(Cm Cm-1 ….. C3 C2 C1) that can be obtained from the combined set of
forbidden latencies and permissible latencies. Value of m is the maximum value of forbidden latency.
So for the next example m will be 7
 Ci = 1 if latency i causes a collision, i.e. for forbidden latencies
Ci = 0 for permissible latencies
S1 X X X
For Example: S2 X X
Forbidden Latencies = {2,4,5,7} S3 X X X
Permissible latencies = {1,3,6, 8+ } Clk 1 2 3 4 5 6 7 8

So, Collision vector will be:

C7 C6 C5 C4 C3 C2 C1 [Latency positions]
C = (1 0 1 1 0 1 0 ) = (1011010)
[MSB of the collision vector will be the max value of forbidden latency] 29
 2. State Transition Diagram
 A state diagram is constructed from collision vector.
 A state diagram will specify the permissible state transitions among successive initiations based on the collision
vector.
 State diagram shows the all possible initial sequences (cycles) without causing a collision in the pipeline.
 State transition will be the permissible latencies of the initial collision vector.
Example: Initial Collision Vector (ICV) = (1011010)
 Method to draw state transition diagram:
 The permissible latencies = {1,3,6,8+ } (Permissible latencies are the positions of 0s in the collision vector),
so we have to find the next states of collision vector for the transitions (1,3,6,8+ )
 Permissible latencies are the transitions that are used to generate the new states.
 To find the collision vector of next state, the collision vector of present state is shifted right for each
transition (1,3,6,8+ ).
 The shifted vector of Present State (PS) is then bitwise OR with Initial Collision Vector (ICV), which is
initial state of the state transition diagram.
 We can again generate some new states from the next state, based on the permissible latencies of the next
state. This process will continue until we do not get any new state.
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 2. State Transition Diagram
 Step 1: Calculating next state with Present State (PS) = 1011010
For the 1st step, present state and initial collision vector will be same.
• Present state = Initial state = 1011010
• Permissible latencies = {1,3,6,8+ }
 With latency 1:  With latency 6:
1 0 1 1 0 1 0 ICV 1 0 1 1 0 1 0 ICV
+ 0 1 0 1 1 0 1 After right shift of PS by 1 + 0 0 0 0 0 0 1 After right shift of PS by 6
------------------------------------------------------- -------------------------------------------------------
1 1 1 1 1 1 1 Next state 1 0 1 1 0 1 1 Next state
• So, the new state 1111111 with latency 1 • So, same next state 1011011 with latency 3 and 6

 With latency 3:  With latency 𝟖+ :

1 0 1 1 0 1 0 ICV 1 0 1 1 0 1 0 ICV
+ 0 0 0 1 0 1 1 After right shift of PS by 3 + 0 0 0 0 0 0 0 After right shift of PS by 8
------------------------------------------------------- -------------------------------------------------------
1 0 1 1 0 1 1 Next state 1 0 1 1 0 1 0 Next state
• So, the new state 1011011 with latency 3 • So, the next state 1011010 with latency 8, which
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returns to the initial state.
 2. State Transition Diagram
8+
 With latency 1, the next state will be 1111111 1011010
 With latency 3 & 6, the next state will be 1011011 3 6 1
 With latency 8+ the next state will be 1011010 1011011 1111111

Fig: Initial State Diagram

 Now again, we have to find the transitions of the two new states so that we can go to other new
states: 1011011 and 1111111

 Find the permissible latencies of the new states, i.e. the position of 0s in the new states.
 For the new state 1011011, the permissible latencies will be : {3,6, 8+ }

 For the new state 1111111, the permissible latencies will be : {8+ }

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 2. State Transition Diagram
 Step 2: Calculating next state with Present State (PS) = 1011011
• Initial state = 1011010
• Permissible latencies will be : {3,6, 8+ }  With latency 𝟖+ :
 With latency 3: 1 0 1 1 0 1 0 ICV
+ 0 0 0 0 0 0 0 After right shift of PS by 8
1 0 1 1 0 1 0 ICV
-------------------------------------------------------
+ 0 0 0 1 0 1 1 After right shift of PS by 3
1 0 1 1 0 1 0 Next state
-------------------------------------------------------
1 0 1 1 0 1 1 Next state • So, the next state 1011010 with latency 8, which
returns to the initial state.
• So, the next state 1011011 with latency 3
is the same present state.
8+
 With latency 6:
1011010
1 0 1 1 0 1 0 ICV 3
+ 0 0 0 0 0 0 1 After right shift of PS by 6 6 8+ 1
------------------------------------------------------- 3
1 0 1 1 0 1 1 Next state 1011011 1111111
• So, the next state 1011011 with latency 6 6
is the same present state. 33
 So, no new state generated from the present state 1011011
 2. State Transition Diagram
 Step 3: Calculating next state with Present State (PS) = 1111111
• Initial state = 1011010
• Permissible latencies will be : {8+ } 8+
 With latency 𝟖+ : 1011010
1 0 1 1 0 1 0 ICV 3 8+
6 8+ 1
+ 0 0 0 0 0 0 0 After right shift of PS by 8 3
------------------------------------------------------- 1011011 1111111
1 0 1 1 0 1 0 Next state 6
• So, the next state 1011010 with latency 8, which returns to the
initial state. Fig: Final State Diagram
• No new state generated from the present state 1011011
 Note: The bitwise OR of the shifted version of the present state with the initial collision vector is meant to
prevent collision from future initiations.
 When the number of shifts is greater than the maximum forbidden latency of the initial collision vector, all
transitions are always redirected back to the initial state. For example: in the state diagram, after 8 or more
shifts, the next 8+ state must be the initial state, regardless of which state the transition starts from.
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 3. Simple and Greedy Cycles
 Cycles can be find out from the state transition Latency Cycle types Average
Cycles Latency
diagram.
(3) Simple and 3
 Simple Cycles: A simple cycle is a latency cycle Constant cycle
in which each state appears only once.
(6) Simple and 6
 Greedy Cycles: A greedy cycle is a simple cycle constant cycle
where the average latency is minimum. (8) Simple and 8
constant cycle
8+ (1,8) Simple cycle 4.5
1011010 (3,8) Simple cycle 5.5
3 8+ (6,8) Simple cycle 7
6 8+ 1
3
1011011 1111111 • As the avg latency of (3) is minimum, so, Greedy
6 Cycle = (3)

Fig: Final State Diagram

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 4. MAL (Minimum Average Latency)
Latency Cycles Cycle types Average
Latency
 MAL is the minimum average latency obtained
(3) Simple (Greedy 3 (MAL)
from the greedy cycle. Cycle)
 Atleast one of the greedy cycles will lead to the (6) Simple 6
MAL (8) Simple 8
(1,8) Simple 4.5
(3,8) Simple cycle 5.5
8+
(6,8) Simple cycle 7
1011010
3 8+
6 8+ 1
3
1011011 1111111  The greedy cycle (3) leads to MAL = 3
6

Fig: Final State Diagram

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Overall Summery to Find The Collision Free Scheduling
Reservation Table

Find issue latencies

Find forbidden and permissible latencies

Generate collision vector

Draw state diagram

Determine greedy cycles

Determine MAL 37
 Numerical Problem Based on Reservation Table
 Consider the following reservation table:
Clk 1 2 3 4 5 6 7
S1 X X
S2 X X
S3 X X
S4 X X

a) Determine latencies in forbidden list F, and the collision vector C

b) Draw the state transition diagram
c) List all simple and greedy cycles
d) Find optimal constant latency cycle. / What will be the minimum allowed constant cycle?
e) Determine MAL
f) If clock period, T = 20ns, determine the maximum throughput of the pipeline.

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 Solution
a) Forbidden latencies in each stage: Clk 1 2 3 4 5 6 7
S1 = {5}, S2 = {4}, S3 = {2}, S4 = {2} S1 X X
Forbidden latencies = {2, 4, 5}, Permissible latencies = {1,3,6+ } S2 X X
Collision Vector = (1 1 0 1 0) S3 X X
b) Step 1 : PS = Initial Collision Vector = 11010, Permissible latencies = {1,3,6+ } S4 X X
 With latency 1:  With latency 𝟔+ :
1 1 0 1 0 ICV 1 1 0 1 0 ICV
+ 0 1 1 0 1 After right shift of PS by 1 + 0 0 0 0 0 After right shift of PS by 6
------------------------------------------------------- -------------------------------------------------------
1 1 1 1 1 Next state 1 1 0 1 0 Next state
• So, the new state 11111 with latency 1 • So, the next state 11010 with latency 6, which
 With latency 3: returns to the initial state.
1 1 0 1 0 ICV
6+
+ 0 0 0 1 1 After right shift of PS by 3
11010
------------------------------------------------------- 3 1
1 1 0 1 1 Next state
• So, the new state 11011 with latency 3 11011 11111
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Initial State Diagram
 Solution (continue)
b) Step 2: PS =11011 Initial Collision Vector = 11010, Permissible latencies = {3,6+ }

 With latency 3:  With latency 𝟔+ :

1 1 0 1 0 ICV 1 1 0 1 0 ICV
+ 0 0 0 1 1 After right shift of PS by 3 + 0 0 0 0 0 After right shift of PS by 6
------------------------------------------------------- -------------------------------------------------------
1 1 0 1 1 Next state 1 1 0 1 0 Next state
• So, the next state 11011 with latency 3 • So, the next state 11010 with latency 6, which
is the same present state. returns to the initial state.

Step 3: PS =11111 Initial Collision Vector = 11010, Permissible latencies = {6+ }

 With latency 𝟔+ :
6+
1 1 0 1 0 ICV
+ 0 0 0 0 0 After right shift of PS by 6 11010
3 1
------------------------------------------------------- 6+ 6+
1 1 0 1 0 Next state 11011 11111
• So, the next state 11010 with latency 6, which 3
returns to the initial state.
Final State Diagram 40
 Solution (continue)
c) Simple Cycles : (3), (6), (3,6), (1,6)
Greedy Cycles : (3) [as the avg latency is minimum for 3]

d) Optimal Constant Latency Cycle: (3) [as the avg latency of 3 is min between 3 and 6]
6+
e) MAL (Minimum Average Latency) = 3
11010
3 1
f) Throughput, 6+ 6+
W = (η / τ) × (1 / MAL) 11011 11111
Assuming efficiency = 1 3
τ = 20ns
1 1 106
Throughput (W) = × = = 16.67 × 106 instructions / sec
20×10−9 3 20×3×10−3
= 16.67 MIPS

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 Numerical Problem (2) Based on Reservation Table
 Consider the following reservation table:
Clk 1 2 3 4 5 6
S1 X X
S2 X X
S3 X
S4 X
S5 X X

a) Determine latencies in forbidden list F, and the collision vector C

b) Draw the state transition diagram
c) List all simple and greedy cycles
d) Find optimal constant latency cycle. / What will be the minimum allowed constant cycle?
e) Determine MAL
f) If clock period, T = 10ns, determine the maximum throughput of the pipeline.
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 Solution
a) Forbidden latencies in each stage: Clk 1 2 3 4 5 6
S1 = {5}, S2 = {3}, S3 = {0}, S4 = {0}, S5 = {4} S1 X X
Forbidden latencies = {3, 4, 5}, Permissible latencies = {1,2,6+ } S2 X X
S3 X
Collision Vector = (1 1 1 0 0)
S4 X
b) Step 1 : PS = Initial Collision Vector = 11100, Permissible latencies = {1,2,6+ } S5 X X
 With latency 1:  With latency 𝟔+ :
1 1 1 0 0 ICV 1 1 1 0 0 ICV
+ 0 1 1 1 0 After right shift of PS by 1 + 0 0 0 0 0 After right shift of PS by 6
------------------------------------------------------- -------------------------------------------------------
1 1 1 1 0 Next state 1 1 1 0 0 Next state
• So, the new state 11110 with latency 1 • So, the next state 11100 with latency 6, which
 With latency 2: returns to the initial state.
1 1 1 0 0 ICV
6+
+ 0 0 1 1 1 After right shift of PS by 2
11100
------------------------------------------------------- 1 2
1 1 1 1 1 Next state
• So, the new state 11111 with latency 2 11110 11111
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Initial State Diagram
 Solution (continue)
b) Step 2: PS =11110 Initial Collision Vector = 11100, Permissible latencies = {1,6+ }

 With latency 1:  With latency 𝟔+ :

1 1 1 0 0 ICV 1 1 1 0 0 ICV
+ 0 1 1 1 1 After right shift of PS by 1 + 0 0 0 0 0 After right shift of PS by 6
------------------------------------------------------- -------------------------------------------------------
1 1 1 1 1 Next state 1 1 1 0 0 Next state
• So, the next state 11111 with latency 1 • So, the next state 11100 with latency 6, which
is a previous state. returns to the initial state.

Step 3: PS =11111 Initial Collision Vector = 11100, Permissible latencies = {6+ }

 With latency 𝟔+ :
6+
1 1 1 0 0 ICV
+ 0 0 0 0 0 After right shift of PS by 6 11100
1 2
------------------------------------------------------- 6 + 6+
1 1 1 0 0 Next state 11110
1
11111
• So, the next state 11100 with latency 6, which
returns to the initial state.
Final State Diagram 44
 Solution (continue)
c) Simple Cycles : (6), (1,6) ,(2,6), (1,1,6)
Greedy Cycles : (1,1,6) [as the avg latency is minimum for (1,1,6) ]

d) Optimal Constant Latency Cycle: (6) [As 6 is the only constant latency cycle]

e) MAL (Minimum Average Latency) = 2.67 6+

f) Throughput, 11100
1 2
W = (η / τ) × (1 / MAL) 6+ 6+
11110 11111
Assuming efficiency = 1 1

τ = 10ns
1 1 106
Throughput (W) = × = = 37.45 × 106 instructions / sec
10×10−9 2.67 10×2.67×10−3
= 37.45 MIPS

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