Crystal Growth and Wafer

Fabrication
Dr. Kalyan Biswas
Assistant Professor, ECE Department
MCKV Institute of Engineering

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 Types of Chips
• Dynamic Random Access Memory chips (DRAMs)
- serve as the primary memory for computers
• Microprocessors (MPUs) - act as the brains of
computers.
• Application Specific Integrated Circuits (ASICs) -
are custom semiconductors designed for very specific
functions
• Digital Signal Processors (DSPs) - process signals,
such as image and sound signals or radar pulses.
• Programmable memory chips (EPROMs, EEPROMs,
and Flash) - are used to perform functions that require
programming on the chip.

2
Semiconductor Fabrication Processes

• Front-End Processing (Wafer

fabrication)
• Back-End Processing (Assembly
and Testing)

3
Simplified View of MOSFET

4
Fabrication Process Flow for VLSI Devices

5
Semiconductor Manufacturing
Process

6
Basic processes involved in fabricating
Monolithic ICs
1. Silicon wafer (substrate) preparation
2. Epitaxial growth
3. Oxidation
4. Photolithography
5. Diffusion
6. Ion implantation
7. Isolation technique
8. Metallization
9. Assembly processing & packaging

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8
Wafer Prcoessing

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Fab Cost

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 Clean Room
• A clean environment designed to reduce the contamination of
processes and materials. This is accomplished by removing or
reducing contamination sources.
• Artificial environment with low particle counts
• Started in medical application for post surgery infection
prevention
• Particles kills yield
• IC fabrication must in a clean room
• Adopted in semiconductor industry in 1950
• Smaller device needs higher grade clean room
• Less particle, more expensive to build

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 Clean Room Definitions
• Use HEPA filters that are 99.97% effective of removing
particles that are 0.5microns or larger.
• High-efficiency particulate air or HEPA is a type of air filter.
• Class X clean rooms means that there are less than X particles
per cubic foot with diameter greater than 0.5 micron
• Typical clean room facilities have various class levels

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 Clean Room Class

• Class 10 is defined as less than 10 particles

with diameter larger than 0.5 um per cubic
foot.
• Class 1 is defined as less than 1 such particles
per cubic foot.
• 0.18 mm device require higher than Class 1
grade clean room.

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 Types of Contamination
• Particulate
Dust, skin, hair, makeup…
• Chemical
Oil, grease, metal ions, perfume…
• Biological
Bacteria, fungi, rodents???
• Radiation
Ultraviolet light…

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Effect of Particles on Masks

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Effect of Particle Contamination

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 Gowning
• Proper gowning order
– Hair cover
– Hood
– Shoe covers
– Coverall
– Gloves
– Face mask
– Safety Glasses

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 Why silicon?
• Higher Bandgap of Silicon (1.1 eV), comparison to Ge (.6 eV)
• Si devices can operate upto 150C versus 100C for Ge.
• The raw material is very cheap
• The intrinsic (undoped) resistivity of Germanium is about 47
Ohm-cm, which would have precluded the fabrication of
rectifying devices with high break-down voltages.
• In contrast, the intrinsic resistivity of silicon is about 230000
ohm-cm. thus high voltage rectifying devices and certain
infrared sensing devices are practical with silicon.

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 Raw Material and Purification
• The raw material for silicon manufacture is sand- often obtained from
beaches,
• The sand is heated in a furnace containing a source of carbon,
• 2C + SiO2 (MGS) Si + 2CO,
• where MGS = metallurgical grade silicon.
• Although MGS is of relatively high purity (98%), it still contains a number
of contaminants (such as iron, carbon and aluminum).
• The MGS is further purified to obtain electronic grade silicon (EGS)
• EGS, a polycrystalline material of high purity, is the raw material for
preparation of single crystal silicon.
• Pure EGS requires that doping elements be in parts per billion (ppb) range,
and carbon be less than 2 parts per million (ppm).

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 Raw Material and Purification (Cont.)
• The MGS silicon is purified to EGS silicon (Electronic Grade Silicon) using a
distillation process,
• First, the MGS is reacted with HCl to form SiHCl3, (trichlorosilane) which is
in liquid form at room temperature,
Si (Solid)+3HCl (Gas) SiHCl3 +H2 (gas)+Heat
• Fractional distillation results in impurity segregation, and extremely pure
SiHCl3.
• To convert the SiHCl3 back into purified Si a CVD (Chemical Vapor
Deposition) process is used (in a hydrogen atmosphere),
SiHCl3 (gas)+H2 (gas) 2Si (solid)+ 6HCl (gas),
• The nucleation surface is thin poly-Si rod, with a final thickness of many
inches in diameter,
• All that is specified is impurity level, so fast deposition is possible .

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 Wafer Fabrication
• A high-purity, single-crystal silicon called "99.999999999%
(eleven-nine)" is grown from a seed to an ingot.
• The wafers are generally available in diameters of 150 mm,
200 mm, or 300 mm, and are mirror-polished and rinsed
before shipment from the wafer manufacturer.

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 Wafer Fabrication
• A wafer is a thin slice of
semiconducting material,
such as a silicon crystal,
upon which microcircuits
are constructed by doping
(for example, diffusion or
ion implantation, etching,
and deposition of various
materials.
• Wafers are cut out of silicon
boules

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Crystal Grower Schematic

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Czochralski Growing System

A crystal is pulled from a feedstock of

molten material by slowly withdrawing
it from the melt. Czochralski pullers
often possess provisions for adding to
the melt during a single pull so that
crystals larger than what can be
obtained in a single charge of the
crucible may be produced.

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 Wafer growth – Czochralski Method (Cz)
-From the high purity poly-Si, single crystal silicon is required,
-The Cz process is the most common for large wafer diameter production.

-The EGS is broken into small pieces

and placed in an SiO2 crucible,

-In an argon ambient, the crucible is

heated to just above 1417oC,

-A single crystal seed is then lowered

into the melt (crystal orientation and
wafer diameter determined by seed
orientation and pull rate),

-Dopant is added to the melt to

intentionally dope the resulting crystal,

-The oxygen and carbon (from graphite

furnace components), contribute about
1017-1018cm-3 contaminants.

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Main components:
a furnace, which includes a fused-silica crucible, a graphite susceptor, a rotation
mechanism (clockwise as shown), a heating element, and a power supply;
a crystal-pulling mechanism, which includes a seed holder and a rotation mechanism
(counter-Clockwise); and
an ambient control, which includes a gas source (such as argon), a flow control and an
exhaust system
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• Practical Integrated Circuits
Can Only be Fabricated from
Single-Crystal Material
• Czochralski Process is a
Technique in Making Single-
Crystal Silicon
• A Solid Seed Crystal is Rotated
and Slowly Extracted from a
Pool of Molten Si
• Requires Careful Control to
Give Crystals Desired Purity
and Dimensions

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 Wafer growth – Float Zone (FZ)
-The Float Zone (FZ) growth method is far less common, and is reserved for
situations where oxygen and carbon impurities cannot be tolerated,

-The entire poly-Si rod is extracted from the EGS process as a whole.

Poly-
Si

c-Si

RF
coil

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 The float zone method
The float Zone (FZ) method is based on the zone-melting principle
and was invented by Theuerer in 1962.
The production takes place under vacuum or in an inert gaseous
atmosphere.
The process starts with a high-purity polycrystalline rod and a
mono-crystalline seed crystal that are held face to face in a vertical
position and are rotated.
With a radio frequency field both are partially melted.
 The seed is brought up from below to make contact with the drop
of melt formed at the tip of the poly rod.
A necking process is carried out to establish a dislocation free
crystal before the neck is allowed to increase in diameter to form a
taper and reach the desired diameter for steady-state growth.
As the molten zone is moved along the polysilicon rod, the molten
silicon solidifies into a single Crystal and, simultaneously, the
material is purified.
Unlike CZ growth, the silicon molten Zone is not in contact with
any substances except ambient gas, which may only contain doping
gas.
 Therefore FZ silicon can easily achieve much higher purity and
higher resistivity.
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 Float Zone Crystal Growth
Gas inlet (inert)

Chuck

Polycrystalline
rod (silicon) Molten zone

Traveling
RF RF coil

Seed crystal
Chuck
Inert gas out

30
12” (30 cm) Boule

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Experimentally determined temperature gradient

Temp

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Variation of pull rate with diameter

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 Specification
• Temperature:Above 950 deg C
• Pull-rate:2.7 mm/min
• Rotation:20-30 rpm.

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 Wafer growth-Wafer Finishing
-The roughed ingot is turned into a uniform diameter using a diamond tip,
-A flat(s) is added to the ingot to indicate crystal orientation and doping type,
-Inside diameter saw is used to slice off individual wafers,
-Finally the wafers undergo a lapping and polishing stage which removes damage caused
by the saw, and creates a smooth polished surface,
-Before use in the cleanroom, the wafers are subjected to a chemical clean to remove
impurities on the surface.

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 Wafer Lapping, Etching & Polishing
• Wafer lapping: Sliced wafers are mechanically lapped using a counter-
rotating lapping machine and an aluminum oxide slurry. This flattens the
wafer surfaces makes them parallel and reduces mechanical defects like
saw markings.
• Wafer Etching: After lapping wafers are etched in a solution of nitric acid,
acetic acid, or sodium hydroxides to remove microscopic cracks or surface
damage created by the lapping process.
• Wafer Polishing: The wafers are polished in a series of a combination of
chemical and mechanical polishing processes called CMP. The wafers are
held on a hard ceramic chuck using either wax bonding or vacuum and
buffed with a slurry of silica powder, RO/DI water and sodium hydroxide.
The polishing process involves two or three polishing steps with
progressively finer slurry and intermediate cleaning using RO/DI water.

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 Wafer growth-Wafer Finishing (Cont.)

In defining substrates we need to

specify:

(111), p-type (111), n-type (100), p-type (100), n-type 1. Doping type/level,
2. Crystal orientation,
3. Impurity levels, (oxygen and carbon),
4. Defect levels.

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Final Wafer

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 Wafer Dimensions & Attributes

Diameter Thickness Area Weight Weight/25

(mm) (m) (cm2) (grams/lbs) Wafers (lbs)
150 675  20 176.71 28 / 0.06 1.5
200 725  20 314.16 53.08 / 0.12 3
300 775  20 706.86 127.64 / 0.28 7
400 825  20 1256.64 241.56 / 0.53 13

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 Processing Considerations
• In the IC processing of silicon wafers it is
usually necessary to maintain purity and
perfection of the material.
– Chemical Cleaning
– Gettering Treatment
– Thermal stress factors

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 Chemical Cleaning
• Prior to use, silicon wafers are usually cleaned chemically.
• Commonly used are aqueous mixtures of NH4OH-H2O2, HCl-
H2O2 and H2SO4-H2O2
• All solutions are efficient in removing metallic impurities but
HCl-H2O2 is the best
• The ammonium hydroxide and sulfuric acid based mixtures
will also remove organic contaminants but the later is better
in this regard.
• Since the chemically grown oxide can contain impurities from
the chemicals, it is usually removed by a short immersion in
dilute hydrofluoric acid dip.

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 Gettering Treatments
• To remove metallic impurities from devices, a variety of processing
techniques termed "gettering" treatments are available.
• Gettering is a general term taken to mean a process that removes harmful
impurities or defects from the regions in a wafer where devices are
fabricated.
• Pregettering means to pre-treat silicon wafers prior to IC processing. It
provides a wafer with sinks that can absorb impurities as they are
introduced during device processing.

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 Extrinsic Gettering Procedures
• Mechanical damage by abrasion, grooving, or sand blasting have all been
used to create stress fields at the backside of wafers. During subsequent
annealing steps, dislocations, which relieve these stresses, are generated.
The dislocations in turn serve as gettering sites.
• A layer of polysilicon deposited on the wafer backside (1.2-1.5 microns
thick) has grain boundaries, and high degree of lattice disorder, which acts
as sinks for mobile impurities

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 Intrinsic Gettering Procedure
• Intrinsic gettering is based on the principle that under proper conditions,
supersaturated oxygen in silicon wafers will precipitate out of solution, and
form clusters within the wafer during thermal processing.
• Punching out dislocation loops can relieve the stresses that result as these
clusters grow into larger precipitates.
• These dislocations become sites at which unwanted impurities can be
trapped and localized. In an effectively designed intrinsic gettering process,
these precipitates are only allowed to form in the bulk regions of the wafer.
• They are prevented from forming in the active device regions by reducing
the oxygen concentration to levels below the threshold required for
precipitation (denuded zone formation). In this manner, unwanted
impurities are localized (gettered) only in regions not containing active
devices.

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 Thermal stress Factors
• When the wafer is removed from furnace, a temperature gradient in wafer
remains.
• The temperature gradient creates a thermal stress S=ET where =CTE
of wafer, E- Young’s modulus, T –temperature difference across the
wafer.
• If these stresses exceed the yield strength of the material, dislocations will
form.
• Stresses are kept acceptable level by withdrawing the wafer slowly or by
lowering the furnace temperature (prior to removing the wafer)
• Material parameters must also be considered. Oxygen precipitates (useful
for gettering) can reduce the yield strength up to five folds.

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 Summary of Key Ideas
• Raw materials (SiO2) are refined to produce electronic grade silicon with a purity
unmatched by any other commonly available material on earth.
• CZ crystal growth produces structurally perfect Si single crystals which can then
be cut into wafers and polished as the starting material for IC manufacturing.
• Starting wafers contain only dopants, O, and C in measurable quantities.
• Dopant incorporation during crystal growth is straightforward except for
segregation effects which cause spatial variations in the dopant concentrations.
• Point, line, and volume (1D, 2D, and 3D) defects can be present in crystals,
particularly after high temperature processing.
• Point defects are "fundamental" and their concentration depends on
temperature (exponentially), on doping level and on other processes like ion
implantation which can create non-equilibrium transient concentrations of these
defects.

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 Crystal Defects in Silicon
A crystal defect (microdefect) is any interruption in the
repetitive nature of the unit cell crystal structure.

Three general types of crystal defects in silicon:

1. Point defects - Localized crystal defect at
the atomic level
2. Dislocations - Displaced unit cells
3. Gross defects - Defects in crystal structure

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 Point Defects
Any nonsilicon atom incorporated into the lattice at either a substitutional
(i.e. replacing a host silicon atom) or interstitial (i.e. between silicon atoms)
site is considered a point defect.

(a) Vacancy defect

(b) Interstitial defect (c) Frenkel defect

Redrawn from Sorab K. Ghandi, VLSI Fabrication Principles: Silicon
and Gallium Arsenide, 2nd edition, New York, Wiley, 1994, page 23

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 Frenkel defect

A Frenkel defect is a type of defect in crystalline solids wherein an atom

is displaced from its lattice position to an interstitial site, creating a
vacancy at the original site and an interstitial defect at the new location
within the same element without any changes in chemical properties.

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 Dislocations in Unit Cells

Dislocations form the second class of defects.

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 Crystal Slip
(Gross Defects)

(a) (b) (c)

Redrawn from Sorab K. Ghandi, VLSI Fabrication Principles: Silicon

and Gallium Arsenide, 2nd edition, New York, Wiley, 1994, page 49

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 Summary: Basic Process Steps for Wafer
Preparation

Wafer Lapping
Crystal Growth and Edge Grind Cleaning

Shaping Etching Inspection

Wafer Slicing Polishing Packaging

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53
 Yield of a Wafer
Fabrication Yield

Y =(NG/NT)x100%
NG = Number of good working die
NT = Total number of die sites
Yield enhancement is complex and
time consuming!!

66 good die
Yield = = 75%
88 total die

Reduction in defect density is a critical aspect for increasing wafer yield.

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55
IC device

drain

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Silicon chip High lead solder die attach

Tin/lead plated copper

leadframe

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