TMS320F2837xD Dual-Core Real-Time

Microcontrollers

Technical Reference Manual

Literature Number: SPRUHM8K

DECEMBER 2013 – REVISED MAY 2024
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Table of Contents

Read This First.........................................................................................................................................................................73

About This Manual................................................................................................................................................................. 73
Notational Conventions.......................................................................................................................................................... 73
Glossary................................................................................................................................................................................. 73
Related Documentation From Texas Instruments.................................................................................................................. 73
Support Resources................................................................................................................................................................ 73
Trademarks............................................................................................................................................................................ 74
1 C2000™ Microcontrollers Software Support......................................................................................................................75
1.1 Introduction...................................................................................................................................................................... 76
1.2 C2000Ware Structure.......................................................................................................................................................76
1.3 Documentation................................................................................................................................................................. 76
1.4 Devices............................................................................................................................................................................ 76
1.5 Libraries........................................................................................................................................................................... 76
1.6 Code Composer Studio™ Integrated Development Environment (IDE).......................................................................... 76
1.7 SysConfig and PinMUX Tool............................................................................................................................................ 77
2 C28x Processor.....................................................................................................................................................................78
2.1 Introduction...................................................................................................................................................................... 79
2.2 C28X Related Collateral...................................................................................................................................................79
2.3 Features........................................................................................................................................................................... 79
2.4 Floating-Point Unit............................................................................................................................................................80
2.5 Trigonometric Math Unit (TMU)........................................................................................................................................80
2.6 Viterbi, Complex Math, and CRC Unit II (VCU-II).............................................................................................................81
3 System Control and Interrupt.............................................................................................................................................. 82
3.1 Introduction...................................................................................................................................................................... 83
3.2 System Control Functional Description............................................................................................................................ 83
3.2.1 Device Identification.................................................................................................................................................. 83
3.2.2 Device Configuration Registers................................................................................................................................. 84
3.3 Resets.............................................................................................................................................................................. 84
3.3.1 Reset Sources........................................................................................................................................................... 84
3.3.2 External Reset (XRS)................................................................................................................................................ 85
3.3.3 Power-On Reset (POR).............................................................................................................................................85
3.3.4 Debugger Reset (SYSRS).........................................................................................................................................85
3.3.5 Watchdog Reset (WDRS)..........................................................................................................................................86
3.3.6 NMI Watchdog Reset (NMIWDRS)............................................................................................................................86
3.3.7 DCSM Safe Code Copy Reset (SCCRESET)........................................................................................................... 86
3.3.8 Hibernate Reset (HIBRESET)................................................................................................................................... 86
3.3.9 Hardware BIST Reset (HWBISTRS)......................................................................................................................... 86
3.3.10 Test Reset (TRST)...................................................................................................................................................86
3.4 Peripheral Interrupts.........................................................................................................................................................87
3.4.1 Interrupt Concepts..................................................................................................................................................... 87
3.4.2 Interrupt Architecture................................................................................................................................................. 87
3.4.3 Interrupt Entry Sequence...........................................................................................................................................89
3.4.4 Configuring and Using Interrupts...............................................................................................................................90
3.4.5 PIE Channel Mapping................................................................................................................................................92
3.4.6 Vector Tables............................................................................................................................................................. 94
3.5 Exceptions and Non-Maskable Interrupts........................................................................................................................ 99
3.5.1 Configuring and Using NMIs......................................................................................................................................99
3.5.2 Emulation Considerations........................................................................................................................................100
3.5.3 NMI Sources............................................................................................................................................................100

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3.5.4 Illegal Instruction Trap (ITRAP)............................................................................................................................... 100

3.6 Safety Features..............................................................................................................................................................101
3.6.1 Write Protection on Registers.................................................................................................................................. 101
3.6.2 Missing Clock Detection Logic.................................................................................................................................101
3.6.3 PLLSLIP Detection.................................................................................................................................................. 102
3.6.4 CPU1 and CPU2 PIE Vector Address Validity Check..............................................................................................103
3.6.5 NMIWDs.................................................................................................................................................................. 103
3.6.6 ECC and Parity Enabled RAMs, Shared RAMs Protection..................................................................................... 103
3.6.7 ECC Enabled Flash Memory................................................................................................................................... 103
3.6.8 ERRORSTS Pin...................................................................................................................................................... 104
3.7 Clocking......................................................................................................................................................................... 104
3.7.1 Clock Sources......................................................................................................................................................... 106
3.7.2 Derived Clocks........................................................................................................................................................ 107
3.7.3 Device Clock Domains............................................................................................................................................ 108
3.7.4 XCLKOUT................................................................................................................................................................109
3.7.5 Clock Connectivity................................................................................................................................................... 110
3.7.6 Clock Source and PLL Setup................................................................................................................................... 111
3.7.7 Clock (OSCCLK) Failure Detection..........................................................................................................................114
3.8 32-Bit CPU Timers 0/1/2.................................................................................................................................................116
3.9 Watchdog Timers............................................................................................................................................................118
3.9.1 Servicing the Watchdog Timer................................................................................................................................. 119
3.9.2 Minimum Window Check......................................................................................................................................... 119
3.9.3 Watchdog Reset or Watchdog Interrupt Mode.........................................................................................................120
3.9.4 Watchdog Operation in Low-Power Modes............................................................................................................. 120
3.9.5 Emulation Considerations........................................................................................................................................120
3.10 Low-Power Modes....................................................................................................................................................... 121
3.10.1 IDLE.......................................................................................................................................................................121
3.10.2 STANDBY.............................................................................................................................................................. 121
3.10.3 HALT......................................................................................................................................................................122
3.10.4 Hibernate (HIB)......................................................................................................................................................124
3.11 Memory Controller Module........................................................................................................................................... 125
3.11.1 Functional Description........................................................................................................................................... 125
3.12 Flash and OTP Memory............................................................................................................................................... 133
3.12.1 Features................................................................................................................................................................ 133
3.12.2 Flash Tools............................................................................................................................................................ 133
3.12.3 Default Flash Configuration................................................................................................................................... 134
3.12.4 Flash Bank, One-Time Programmable (OTP) Memory, and Flash Pump............................................................. 134
3.12.5 Flash Module Controller (FMC)............................................................................................................................. 135
3.12.6 Flash and OTP Memory Power-Down Modes and Wakeup.................................................................................. 135
3.12.7 Flash and OTP Memory Performance...................................................................................................................137
3.12.8 Flash Read Interface............................................................................................................................................. 137
3.12.9 Erase/Program Flash.............................................................................................................................................139
3.12.10 Error Correction Code (ECC) Protection............................................................................................................. 140
3.12.11 Reserved Locations Within Flash and OTP Memory........................................................................................... 144
3.12.12 Procedure to Change the Flash Control Registers..............................................................................................144
3.12.13 Simple Procedure to Modify an Application from RAM Configuration to Flash Configuration............................. 144
3.12.14 Flash Pump Ownership Semaphore....................................................................................................................145
3.13 Dual Code Security Module (DCSM)........................................................................................................................... 147
3.13.1 Functional Description........................................................................................................................................... 147
3.13.2 CSM Impact on Other On-Chip Resources........................................................................................................... 154
3.13.3 Incorporating Code Security in User Applications................................................................................................. 155
3.14 JTAG............................................................................................................................................................................ 160
3.15 System Control Register Configuration Restrictions.................................................................................................... 160
3.16 Software....................................................................................................................................................................... 161
3.16.1 SYSCTL Examples................................................................................................................................................161
3.16.2 TIMER Examples...................................................................................................................................................161
3.16.3 MEMCFG Examples..............................................................................................................................................162
3.16.4 INTERRUPT Examples......................................................................................................................................... 162
3.16.5 LPM Examples...................................................................................................................................................... 165
3.16.6 WATCHDOG Examples.........................................................................................................................................165
3.17 System Control Registers............................................................................................................................................ 166

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3.17.1 System Control Base Addresses...........................................................................................................................166

3.17.2 CPUTIMER_REGS Registers............................................................................................................................... 167
3.17.3 PIE_CTRL_REGS Registers................................................................................................................................. 174
3.17.4 WD_REGS Registers............................................................................................................................................ 226
3.17.5 NMI_INTRUPT_REGS Registers.......................................................................................................................... 232
3.17.6 XINT_REGS Registers.......................................................................................................................................... 245
3.17.7 SYNC_SOC_REGS Registers.............................................................................................................................. 254
3.17.8 DMA_CLA_SRC_SEL_REGS Registers...............................................................................................................261
3.17.9 FLASH_PUMP_SEMAPHORE_REGS Registers................................................................................................. 268
3.17.10 DEV_CFG_REGS Registers............................................................................................................................... 270
3.17.11 CLK_CFG_REGS Registers................................................................................................................................ 337
3.17.12 CPU_SYS_REGS Registers............................................................................................................................... 360
3.17.13 ROM_PREFETCH_REGS Registers.................................................................................................................. 399
3.17.14 DCSM_Z1_REGS Registers............................................................................................................................... 401
3.17.15 DCSM_Z2_REGS Registers............................................................................................................................... 421
3.17.16 DCSM_COMMON_REGS Registers...................................................................................................................441
3.17.17 MEM_CFG_REGS Registers.............................................................................................................................. 448
3.17.18 ACCESS_PROTECTION_REGS Registers........................................................................................................495
3.17.19 MEMORY_ERROR_REGS Registers................................................................................................................. 518
3.17.20 ROM_WAIT_STATE_REGS Registers................................................................................................................ 535
3.17.21 FLASH_CTRL_REGS Registers......................................................................................................................... 537
3.17.22 FLASH_ECC_REGS Registers........................................................................................................................... 546
3.17.23 CPU_ID_REGS Registers................................................................................................................................... 569
3.17.24 UID_REGS Registers.......................................................................................................................................... 571
3.17.25 DCSM_Z1_OTP Registers.................................................................................................................................. 580
3.17.26 DCSM_Z2_OTP Registers.................................................................................................................................. 588
3.17.27 Register to Driverlib Function Mapping............................................................................................................... 596
4 ROM Code and Peripheral Booting...................................................................................................................................614
4.1 Introduction.................................................................................................................................................................... 615
4.2 Boot ROM Registers...................................................................................................................................................... 615
4.3 Device Boot Sequence...................................................................................................................................................615
4.4 Device Boot Modes........................................................................................................................................................ 616
4.5 Configuring Boot Mode Pins.......................................................................................................................................... 617
4.6 Configuring Get Boot Options........................................................................................................................................ 619
4.7 Configuring Emulation Boot Options.............................................................................................................................. 620
4.8 Device Boot Flow Diagrams...........................................................................................................................................621
4.8.1 Emulation Boot Flow Diagrams............................................................................................................................... 623
4.8.2 Standalone and Hibernate Boot Flow Diagrams..................................................................................................... 625
4.9 Device Reset and Exception Handling...........................................................................................................................627
4.9.1 Reset Causes and Handling....................................................................................................................................627
4.9.2 Exceptions and Interrupts Handling.........................................................................................................................628
4.10 Boot ROM Description................................................................................................................................................. 629
4.10.1 Entry Points........................................................................................................................................................... 629
4.10.2 Wait Points.............................................................................................................................................................629
4.10.3 Memory Maps........................................................................................................................................................630
4.10.4 Boot Modes........................................................................................................................................................... 633
4.10.5 Boot Data Stream Structure.................................................................................................................................. 648
4.10.6 GPIO Assignments................................................................................................................................................ 650
4.10.7 Secure ROM Function APIs.................................................................................................................................. 652
4.10.8 Boot IPC................................................................................................................................................................ 653
4.10.9 Clock Initializations................................................................................................................................................ 658
4.10.10 Wait State Configuration......................................................................................................................................659
4.10.11 Boot Status information........................................................................................................................................659
4.10.12 ROM Version....................................................................................................................................................... 662
5 Direct Memory Access (DMA)............................................................................................................................................663
5.1 Introduction.................................................................................................................................................................... 664
5.1.1 Features.................................................................................................................................................................. 664
5.1.2 Block Diagram......................................................................................................................................................... 665
5.2 Architecture.................................................................................................................................................................... 666
5.2.1 Common Peripheral Architecture............................................................................................................................ 666
5.2.2 Peripheral Interrupt Event Trigger Sources............................................................................................................. 667

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5.2.3 DMA Bus................................................................................................................................................................. 671

5.3 Address Pointer and Transfer Control............................................................................................................................671
5.4 Pipeline Timing and Throughput.................................................................................................................................... 677
5.5 CPU and CLA Arbitration............................................................................................................................................... 678
5.6 Channel Priority..............................................................................................................................................................679
5.6.1 Round-Robin Mode................................................................................................................................................. 679
5.6.2 Channel 1 High-Priority Mode................................................................................................................................. 680
5.7 Overrun Detection Feature.............................................................................................................................................680
5.8 Software......................................................................................................................................................................... 681
5.8.1 DMA Examples........................................................................................................................................................681
5.9 DMA Registers............................................................................................................................................................... 682
5.9.1 DMA Base Addresses............................................................................................................................................. 682
5.9.2 DMA_REGS Registers............................................................................................................................................ 683
5.9.3 DMA_CH_REGS Registers..................................................................................................................................... 688
5.9.4 DMA Registers to Driverlib Functions......................................................................................................................714
6 Control Law Accelerator (CLA)..........................................................................................................................................717
6.1 Introduction.................................................................................................................................................................... 718
6.1.1 Features.................................................................................................................................................................. 718
6.1.2 CLA Related Collateral............................................................................................................................................ 718
6.1.3 Block Diagram......................................................................................................................................................... 719
6.2 CLA Interface................................................................................................................................................................. 720
6.2.1 CLA Memory............................................................................................................................................................720
6.2.2 CLA Memory Bus.................................................................................................................................................... 721
6.2.3 Shared Peripherals and EALLOW Protection..........................................................................................................722
6.2.4 CLA Tasks and Interrupt Vectors............................................................................................................................. 722
6.2.5 CLA Software Interrupt to CPU............................................................................................................................... 725
6.3 CLA and CPU Arbitration............................................................................................................................................... 726
6.3.1 CLA Message RAM................................................................................................................................................. 726
6.3.2 CLA Program Memory.............................................................................................................................................727
6.3.3 CLA Data Memory................................................................................................................................................... 728
6.3.4 Peripheral Registers (ePWM, HRPWM, Comparator).............................................................................................728
6.4 CLA Configuration and Debug....................................................................................................................................... 729
6.4.1 Building a CLA Application...................................................................................................................................... 729
6.4.2 Typical CLA Initialization Sequence........................................................................................................................ 729
6.4.3 Debugging CLA Code..............................................................................................................................................730
6.4.4 CLA Illegal Opcode Behavior.................................................................................................................................. 731
6.4.5 Resetting the CLA................................................................................................................................................... 732
6.5 Pipeline.......................................................................................................................................................................... 732
6.5.1 Pipeline Overview....................................................................................................................................................732
6.5.2 CLA Pipeline Alignment...........................................................................................................................................733
6.5.3 Parallel Instructions................................................................................................................................................. 737
6.5.4 CLA Task Execution Latency...................................................................................................................................737
6.6 Software......................................................................................................................................................................... 738
6.6.1 CLA Examples.........................................................................................................................................................738
6.7 Instruction Set................................................................................................................................................................ 739
6.7.1 Instruction Descriptions........................................................................................................................................... 739
6.7.2 Addressing Modes and Encoding............................................................................................................................740
6.7.3 Instructions.............................................................................................................................................................. 743
6.8 CLA Registers................................................................................................................................................................ 870
6.8.1 CLA Base Addresses.............................................................................................................................................. 870
6.8.2 CLA_REGS Registers............................................................................................................................................. 871
6.8.3 CLA_SOFTINT_REGS Registers............................................................................................................................910
6.8.4 CLA Registers to Driverlib Functions.......................................................................................................................914
7 Interprocessor Communication (IPC)............................................................................................................................... 916
7.1 Introduction.................................................................................................................................................................... 917
7.2 Message RAMs..............................................................................................................................................................918
7.3 IPC Flags and Interrupts................................................................................................................................................ 918
7.4 IPC Command Registers............................................................................................................................................... 918
7.5 Free-Running Counter................................................................................................................................................... 918
7.6 IPC Communication Protocol......................................................................................................................................... 919
7.7 IPC Registers................................................................................................................................................................. 920

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7.7.1 IPC Base Addresses............................................................................................................................................... 920

7.7.2 IPC_REGS_CPU1 Registers...................................................................................................................................921
7.7.3 IPC_REGS_CPU2 Registers...................................................................................................................................953
7.7.4 IPC Registers to Driverlib Functions........................................................................................................................984
8 General-Purpose Input/Output (GPIO)..............................................................................................................................986
8.1 Introduction.................................................................................................................................................................... 987
8.1.1 GPIO Related Collateral.......................................................................................................................................... 988
8.2 Configuration Overview..................................................................................................................................................989
8.3 Digital General-Purpose I/O Control.............................................................................................................................. 990
8.4 Input Qualification.......................................................................................................................................................... 991
8.4.1 No Synchronization (Asynchronous Input).............................................................................................................. 991
8.4.2 Synchronization to SYSCLKOUT Only....................................................................................................................991
8.4.3 Qualification Using a Sampling Window..................................................................................................................992
8.5 USB Signals................................................................................................................................................................... 995
8.6 SPI Signals.....................................................................................................................................................................995
8.7 GPIO and Peripheral Muxing......................................................................................................................................... 996
8.7.1 GPIO Muxing........................................................................................................................................................... 996
8.7.2 Peripheral Muxing..................................................................................................................................................1002
8.8 Internal Pullup Configuration Requirements................................................................................................................ 1004
8.9 Software....................................................................................................................................................................... 1005
8.9.1 GPIO Examples.....................................................................................................................................................1005
8.9.2 LED Examples.......................................................................................................................................................1005
8.10 GPIO Registers.......................................................................................................................................................... 1006
8.10.1 GPIO Base Addresses........................................................................................................................................ 1006
8.10.2 GPIO_CTRL_REGS Registers............................................................................................................................1007
8.10.3 GPIO_DATA_REGS Registers............................................................................................................................ 1173
8.10.4 GPIO Registers to Driverlib Functions.................................................................................................................1222
9 Crossbar (X-BAR)............................................................................................................................................................. 1229
9.1 Input X-BAR ................................................................................................................................................................ 1230
9.2 ePWM, CLB, and GPIO Output X-BAR........................................................................................................................1233
9.2.1 ePWM X-BAR........................................................................................................................................................1233
9.2.2 CLB X-BAR............................................................................................................................................................1235
9.2.3 GPIO Output X-BAR..............................................................................................................................................1238
9.2.4 X-BAR Flags..........................................................................................................................................................1240
9.3 XBAR Registers........................................................................................................................................................... 1241
9.3.1 XBAR Base Addresses..........................................................................................................................................1241
9.3.2 INPUT_XBAR_REGS Registers............................................................................................................................1242
9.3.3 XBAR_REGS Registers........................................................................................................................................ 1259
9.3.4 EPWM_XBAR_REGS Registers........................................................................................................................... 1272
9.3.5 CLB_XBAR_REGS Registers............................................................................................................................... 1365
9.3.6 OUTPUT_XBAR_REGS Registers........................................................................................................................1458
9.3.7 Register to Driverlib Function Mapping................................................................................................................. 1559
10 Analog Subsystem......................................................................................................................................................... 1565
10.1 Introduction................................................................................................................................................................ 1566
10.1.1 Features.............................................................................................................................................................. 1566
10.1.2 Block Diagram..................................................................................................................................................... 1566
10.2 Optimizing Power-Up Time........................................................................................................................................ 1570
10.3 Analog Subsystem Registers..................................................................................................................................... 1571
10.3.1 Analog Subsystem Base Addresses................................................................................................................... 1571
10.3.2 ANALOG_SUBSYS_REGS Registers.................................................................................................................1572
11 Analog-to-Digital Converter (ADC)................................................................................................................................1582
11.1 Introduction.................................................................................................................................................................1583
11.1.1 ADC Related Collateral........................................................................................................................................1583
11.1.2 Features...............................................................................................................................................................1584
11.1.3 Block Diagram......................................................................................................................................................1585
11.2 ADC Configurability.................................................................................................................................................... 1586
11.2.1 Clock Configuration..............................................................................................................................................1586
11.2.2 Resolution............................................................................................................................................................1586
11.2.3 Voltage Reference............................................................................................................................................... 1587
11.2.4 Signal Mode.........................................................................................................................................................1587
11.2.5 Expected Conversion Results..............................................................................................................................1588

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11.2.6 Interpreting Conversion Results...........................................................................................................................1589

11.3 SOC Principle of Operation........................................................................................................................................ 1590
11.3.1 SOC Configuration...............................................................................................................................................1591
11.3.2 Trigger Operation.................................................................................................................................................1591
11.3.3 ADC Acquisition (Sample and Hold) Window...................................................................................................... 1591
11.3.4 ADC Input Models................................................................................................................................................1592
11.3.5 Channel Selection................................................................................................................................................1593
11.4 SOC Configuration Examples.....................................................................................................................................1594
11.4.1 Single Conversion from ePWM Trigger............................................................................................................... 1594
11.4.2 Oversampled Conversion from ePWM Trigger.................................................................................................... 1594
11.4.3 Multiple Conversions from CPU Timer Trigger.................................................................................................... 1595
11.4.4 Software Triggering of SOCs............................................................................................................................... 1596
11.5 ADC Conversion Priority.............................................................................................................................................1596
11.6 Burst Mode................................................................................................................................................................. 1599
11.6.1 Burst Mode Example............................................................................................................................................1599
11.6.2 Burst Mode Priority Example............................................................................................................................... 1600
11.7 EOC and Interrupt Operation......................................................................................................................................1601
11.7.1 Interrupt Overflow................................................................................................................................................ 1602
11.7.2 Continue to Interrupt Mode.................................................................................................................................. 1602
11.7.3 Early Interrupt Configuration Mode...................................................................................................................... 1602
11.8 Post-Processing Blocks..............................................................................................................................................1603
11.8.1 PPB Offset Correction..........................................................................................................................................1604
11.8.2 PPB Error Calculation.......................................................................................................................................... 1604
11.8.3 PPB Limit Detection and Zero-Crossing Detection.............................................................................................. 1604
11.8.4 PPB Sample Delay Capture.................................................................................................................................1606
11.9 Opens/Shorts Detection Circuit (OSDETECT)........................................................................................................... 1607
11.9.1 Implementation.................................................................................................................................................... 1608
11.9.2 Detecting an Open Input Pin................................................................................................................................1608
11.9.3 Detecting a Shorted Input Pin.............................................................................................................................. 1608
11.10 Power-Up Sequence................................................................................................................................................ 1609
11.11 ADC Calibration........................................................................................................................................................ 1609
11.11.1 ADC Zero Offset Calibration.............................................................................................................................. 1610
11.11.2 ADC Calibration Routines in OTP Memory........................................................................................................ 1611
11.12 ADC Timings............................................................................................................................................................ 1612
11.12.1 ADC Timing Diagrams....................................................................................................................................... 1612
11.13 Additional Information...............................................................................................................................................1618
11.13.1 Ensuring Synchronous Operation...................................................................................................................... 1618
11.13.2 Choosing an Acquisition Window Duration........................................................................................................ 1622
11.13.3 Achieving Simultaneous Sampling.....................................................................................................................1624
11.13.4 Result Register Mapping....................................................................................................................................1624
11.13.5 Internal Temperature Sensor............................................................................................................................. 1624
11.13.6 Designing an External Reference Circuit........................................................................................................... 1625
11.14 Software................................................................................................................................................................... 1627
11.14.1 ADC Examples...................................................................................................................................................1627
11.15 ADC Registers..........................................................................................................................................................1630
11.15.1 ADC Base Addresses........................................................................................................................................ 1630
11.15.2 ADC_RESULT_REGS Registers....................................................................................................................... 1631
11.15.3 ADC_REGS Registers....................................................................................................................................... 1652
11.15.4 ADC Registers to Driverlib Functions................................................................................................................ 1784
12 Buffered Digital-to-Analog Converter (DAC)................................................................................................................1789
12.1 Introduction................................................................................................................................................................ 1790
12.1.1 DAC Related Collateral....................................................................................................................................... 1790
12.1.2 Features.............................................................................................................................................................. 1790
12.1.3 Block Diagram..................................................................................................................................................... 1790
12.2 Using the DAC........................................................................................................................................................... 1791
12.2.1 Initialization Sequence.........................................................................................................................................1791
12.2.2 DAC Offset Adjustment........................................................................................................................................1792
12.2.3 EPWMSYNCPER Signal..................................................................................................................................... 1792
12.3 Lock Registers........................................................................................................................................................... 1792
12.4 Software..................................................................................................................................................................... 1793
12.4.1 DAC Examples.................................................................................................................................................... 1793

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12.5 DAC Registers........................................................................................................................................................... 1793

12.5.1 DAC Base Addresses..........................................................................................................................................1793
12.5.2 DAC_REGS Registers.........................................................................................................................................1794
12.5.3 DAC Registers to Driverlib Functions.................................................................................................................. 1801
13 Comparator Subsystem (CMPSS)................................................................................................................................. 1803
13.1 Introduction................................................................................................................................................................ 1804
13.1.1 CMPSS Related Collateral.................................................................................................................................. 1804
13.1.2 Features.............................................................................................................................................................. 1804
13.1.3 Block Diagram..................................................................................................................................................... 1805
13.2 Comparator................................................................................................................................................................ 1805
13.3 Reference DAC.......................................................................................................................................................... 1806
13.4 Ramp Generator........................................................................................................................................................ 1807
13.4.1 Ramp Generator Overview..................................................................................................................................1807
13.4.2 Ramp Generator Behavior...................................................................................................................................1808
13.4.3 Ramp Generator Behavior at Corner Cases....................................................................................................... 1809
13.5 Digital Filter................................................................................................................................................................ 1810
13.5.1 Filter Initialization Sequence................................................................................................................................ 1811
13.6 Using the CMPSS.......................................................................................................................................................1811
13.6.1 LATCHCLR and EPWMSYNCPER Signals ........................................................................................................1811
13.6.2 Synchronizer, Digital Filter, and Latch Delays......................................................................................................1811
13.6.3 Calibrating the CMPSS .......................................................................................................................................1812
13.6.4 Enabling and Disabling the CMPSS Clock.......................................................................................................... 1812
13.7 Software..................................................................................................................................................................... 1813
13.7.1 CMPSS Examples............................................................................................................................................... 1813
13.8 CMPSS Registers...................................................................................................................................................... 1814
13.8.1 CMPSS Base Addresses.....................................................................................................................................1814
13.8.2 CMPSS_REGS Registers................................................................................................................................... 1815
13.8.3 CMPSS Registers to Driverlib Functions.............................................................................................................1838
14 Sigma Delta Filter Module (SDFM)................................................................................................................................ 1841
14.1 Introduction................................................................................................................................................................ 1842
14.1.1 SDFM Related Collateral.....................................................................................................................................1842
14.1.2 Features.............................................................................................................................................................. 1843
14.1.3 Block Diagram..................................................................................................................................................... 1844
14.2 Configuring Device Pins.............................................................................................................................................1846
14.3 Input Control Unit....................................................................................................................................................... 1847
14.4 Sinc Filter................................................................................................................................................................... 1848
14.4.1 Data Rate and Latency of the Sinc Filter.............................................................................................................1850
14.5 Data (Primary) Filter Unit........................................................................................................................................... 1851
14.5.1 32-bit or 16-bit Data Filter Output Representation...............................................................................................1852
14.5.2 SDSYNC Event................................................................................................................................................... 1853
14.6 Comparator (Secondary) Filter Unit........................................................................................................................... 1854
14.6.1 Higher Threshold (HLT) Comparator .................................................................................................................. 1855
14.6.2 Lower Threshold (LLT) Comparator ....................................................................................................................1855
14.7 Theoretical SDFM Filter Output................................................................................................................................. 1856
14.8 Interrupt Unit.............................................................................................................................................................. 1858
14.8.1 SDFM (SDINT) Interrupt Sources .......................................................................................................................1858
14.9 Register Descriptions................................................................................................................................................. 1860
14.10 Software................................................................................................................................................................... 1862
14.10.1 SDFM Examples................................................................................................................................................1862
14.11 SDFM Registers....................................................................................................................................................... 1862
14.11.1 SDFM Base Addresses......................................................................................................................................1862
14.11.2 SDFM_REGS Registers.................................................................................................................................... 1863
14.11.3 SDFM Registers to Driverlib Functions..............................................................................................................1899
15 Enhanced Pulse Width Modulator (ePWM)...................................................................................................................1901
15.1 Introduction................................................................................................................................................................ 1902
15.1.1 EPWM Related Collateral....................................................................................................................................1903
15.1.2 Submodule Overview.......................................................................................................................................... 1904
15.2 Configuring Device Pins.............................................................................................................................................1909
15.3 ePWM Modules Overview..........................................................................................................................................1909
15.4 Time-Base (TB) Submodule....................................................................................................................................... 1911
15.4.1 Purpose of the Time-Base Submodule................................................................................................................ 1911

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15.4.2 Controlling and Monitoring the Time-Base Submodule....................................................................................... 1912

15.4.3 Calculating PWM Period and Frequency.............................................................................................................1914
15.4.4 Phase Locking the Time-Base Clocks of Multiple ePWM Modules..................................................................... 1917
15.4.5 Simultaneous Writes to TBPRD and CMPx Registers Between ePWM Modules............................................... 1917
15.4.6 Time-Base Counter Modes and Timing Waveforms............................................................................................ 1918
15.4.7 Global Load......................................................................................................................................................... 1922
15.5 Counter-Compare (CC) Submodule...........................................................................................................................1924
15.5.1 Purpose of the Counter-Compare Submodule.................................................................................................... 1924
15.5.2 Controlling and Monitoring the Counter-Compare Submodule............................................................................1925
15.5.3 Operational Highlights for the Counter-Compare Submodule............................................................................. 1926
15.5.4 Count Mode Timing Waveforms.......................................................................................................................... 1927
15.6 Action-Qualifier (AQ) Submodule...............................................................................................................................1930
15.6.1 Purpose of the Action-Qualifier Submodule........................................................................................................ 1930
15.6.2 Action-Qualifier Submodule Control and Status Register Definitions..................................................................1931
15.6.3 Action-Qualifier Event Priority..............................................................................................................................1933
15.6.4 AQCTLA and AQCTLB Shadow Mode Operations............................................................................................. 1934
15.6.5 Configuration Requirements for Common Waveforms........................................................................................ 1936
15.7 Dead-Band Generator (DB) Submodule.................................................................................................................... 1943
15.7.1 Purpose of the Dead-Band Submodule...............................................................................................................1943
15.7.2 Dead-band Submodule Additional Operating Modes.......................................................................................... 1944
15.7.3 Operational Highlights for the Dead-Band Submodule........................................................................................1946
15.8 PWM Chopper (PC) Submodule................................................................................................................................ 1950
15.8.1 Purpose of the PWM Chopper Submodule......................................................................................................... 1950
15.8.2 Operational Highlights for the PWM Chopper Submodule.................................................................................. 1950
15.8.3 Waveforms...........................................................................................................................................................1951
15.9 Trip-Zone (TZ) Submodule.........................................................................................................................................1954
15.9.1 Purpose of the Trip-Zone Submodule..................................................................................................................1954
15.9.2 Operational Highlights for the Trip-Zone Submodule.......................................................................................... 1955
15.9.3 Generating Trip Event Interrupts......................................................................................................................... 1957
15.10 Event-Trigger (ET) Submodule................................................................................................................................ 1960
15.10.1 Operational Overview of the ePWM Event-Trigger Submodule........................................................................ 1961
15.11 Digital Compare (DC) Submodule............................................................................................................................ 1965
15.11.1 Purpose of the Digital Compare Submodule......................................................................................................1967
15.11.2 Enhanced Trip Action Using CMPSS.................................................................................................................1967
15.11.3 Using CMPSS to Trip the ePWM on a Cycle-by-Cycle Basis............................................................................ 1967
15.11.4 Operation Highlights of the Digital Compare Submodule.................................................................................. 1968
15.12 ePWM Crossbar (X-BAR)........................................................................................................................................ 1975
15.13 Applications to Power Topologies............................................................................................................................ 1976
15.13.1 Overview of Multiple Modules............................................................................................................................1976
15.13.2 Key Configuration Capabilities.......................................................................................................................... 1977
15.13.3 Controlling Multiple Buck Converters With Independent Frequencies.............................................................. 1978
15.13.4 Controlling Multiple Buck Converters With Same Frequencies......................................................................... 1980
15.13.5 Controlling Multiple Half H-Bridge (HHB) Converters........................................................................................1982
15.13.6 Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM)...................................................................... 1984
15.13.7 Practical Applications Using Phase Control Between PWM Modules............................................................... 1986
15.13.8 Controlling a 3-Phase Interleaved DC/DC Converter........................................................................................ 1987
15.13.9 Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter.................................................................. 1990
15.13.10 Controlling a Peak Current Mode Controlled Buck Module............................................................................. 1992
15.13.11 Controlling H-Bridge LLC Resonant Converter................................................................................................1993
15.14 High-Resolution Pulse Width Modulator (HRPWM)................................................................................................. 1994
15.14.1 Operational Description of HRPWM.................................................................................................................. 1996
15.14.2 SFO Library Software - SFO_TI_Build_V8.lib................................................................................................... 2017
15.15 ePWM Registers...................................................................................................................................................... 2020
15.15.1 ePWM Base Addresses.....................................................................................................................................2020
15.15.2 EPWM_REGS Registers................................................................................................................................... 2021
15.15.3 Register to Driverlib Function Mapping............................................................................................................. 2141
16 Enhanced Capture (eCAP)............................................................................................................................................. 2153
16.1 Introduction................................................................................................................................................................ 2154
16.1.1 Features.............................................................................................................................................................. 2154
16.1.2 ECAP Related Collateral..................................................................................................................................... 2154
16.2 Description................................................................................................................................................................. 2154

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16.3 Configuring Device Pins for the eCAP....................................................................................................................... 2155

16.4 Capture and APWM Operating Mode........................................................................................................................ 2156
16.5 Capture Mode Description......................................................................................................................................... 2158
16.5.1 Event Prescaler................................................................................................................................................... 2159
16.5.2 Edge Polarity Select and Qualifier.......................................................................................................................2159
16.5.3 Continuous/One-Shot Control............................................................................................................................. 2160
16.5.4 32-Bit Counter and Phase Control.......................................................................................................................2161
16.5.5 CAP1-CAP4 Registers........................................................................................................................................ 2161
16.5.6 eCAP Synchronization.........................................................................................................................................2161
16.5.7 Interrupt Control...................................................................................................................................................2163
16.5.8 DMA Interrupt...................................................................................................................................................... 2165
16.5.9 Shadow Load and Lockout Control..................................................................................................................... 2165
16.5.10 APWM Mode Operation.....................................................................................................................................2165
16.6 Application of the eCAP Module................................................................................................................................ 2167
16.6.1 Example 1 - Absolute Time-Stamp Operation Rising-Edge Trigger.................................................................... 2167
16.6.2 Example 2 - Absolute Time-Stamp Operation Rising- and Falling-Edge Trigger.................................................2168
16.6.3 Example 3 - Time Difference (Delta) Operation Rising-Edge Trigger..................................................................2169
16.6.4 Example 4 - Time Difference (Delta) Operation Rising- and Falling-Edge Trigger.............................................. 2170
16.7 Application of the APWM Mode................................................................................................................................. 2171
16.7.1 Example 1 - Simple PWM Generation (Independent Channels)......................................................................... 2171
16.8 Software..................................................................................................................................................................... 2172
16.8.1 ECAP Examples.................................................................................................................................................. 2172
16.9 eCAP Registers..........................................................................................................................................................2173
16.9.1 eCAP Base Addresses........................................................................................................................................ 2173
16.9.2 ECAP_REGS Registers...................................................................................................................................... 2174
16.9.3 ECAP Registers to Driverlib Functions................................................................................................................2189
17 Enhanced Quadrature Encoder Pulse (eQEP)............................................................................................................. 2192
17.1 Introduction................................................................................................................................................................ 2193
17.1.1 EQEP Related Collateral..................................................................................................................................... 2195
17.2 Configuring Device Pins.............................................................................................................................................2195
17.3 Description................................................................................................................................................................. 2196
17.3.1 EQEP Inputs........................................................................................................................................................2196
17.3.2 Functional Description......................................................................................................................................... 2197
17.3.3 eQEP Memory Map............................................................................................................................................. 2198
17.4 Quadrature Decoder Unit (QDU)................................................................................................................................2199
17.4.1 Position Counter Input Modes............................................................................................................................. 2199
17.4.2 eQEP Input Polarity Selection............................................................................................................................. 2202
17.4.3 Position-Compare Sync Output........................................................................................................................... 2202
17.5 Position Counter and Control Unit (PCCU)................................................................................................................ 2202
17.5.1 Position Counter Operating Modes..................................................................................................................... 2202
17.5.2 Position Counter Latch........................................................................................................................................ 2205
17.5.3 Position Counter Initialization.............................................................................................................................. 2207
17.5.4 eQEP Position-compare Unit...............................................................................................................................2208
17.6 eQEP Edge Capture Unit........................................................................................................................................... 2210
17.7 eQEP Watchdog.........................................................................................................................................................2214
17.8 eQEP Unit Timer Base............................................................................................................................................... 2214
17.9 eQEP Interrupt Structure............................................................................................................................................2215
17.10 eQEP Registers....................................................................................................................................................... 2215
17.10.1 eQEP Base Addresses......................................................................................................................................2215
17.10.2 EQEP_REGS Registers.................................................................................................................................... 2216
17.10.3 EQEP Registers to Driverlib Functions..............................................................................................................2247
18 Serial Peripheral Interface (SPI).................................................................................................................................... 2250
18.1 Introduction................................................................................................................................................................ 2251
18.1.1 Features.............................................................................................................................................................. 2251
18.1.2 SPI Related Collateral......................................................................................................................................... 2251
18.1.3 Block Diagram..................................................................................................................................................... 2252
18.2 System-Level Integration........................................................................................................................................... 2253
18.2.1 SPI Module Signals............................................................................................................................................. 2253
18.2.2 Configuring Device Pins...................................................................................................................................... 2254
18.2.3 SPI Interrupts.......................................................................................................................................................2254
18.2.4 DMA Support....................................................................................................................................................... 2256

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18.3 SPI Operation.............................................................................................................................................................2257

18.3.1 Introduction to Operation..................................................................................................................................... 2257
18.3.2 Master Mode........................................................................................................................................................2258
18.3.3 Slave Mode..........................................................................................................................................................2259
18.3.4 Data Format.........................................................................................................................................................2261
18.3.5 Baud Rate Selection............................................................................................................................................2262
18.3.6 SPI Clocking Schemes........................................................................................................................................ 2263
18.3.7 SPI FIFO Description...........................................................................................................................................2264
18.3.8 SPI DMA Transfers..............................................................................................................................................2265
18.3.9 SPI High-Speed Mode.........................................................................................................................................2266
18.3.10 SPI 3-Wire Mode Description............................................................................................................................ 2266
18.4 Programming Procedure............................................................................................................................................ 2268
18.4.1 Initialization Upon Reset......................................................................................................................................2268
18.4.2 Configuring the SPI............................................................................................................................................. 2268
18.4.3 Configuring the SPI for High-Speed Mode.......................................................................................................... 2269
18.4.4 Data Transfer Example........................................................................................................................................2270
18.4.5 SPI 3-Wire Mode Code Examples.......................................................................................................................2271
18.4.6 SPI STEINV Bit in Digital Audio Transfers...........................................................................................................2273
18.5 Software..................................................................................................................................................................... 2274
18.5.1 SPI Examples...................................................................................................................................................... 2274
18.6 SPI Registers............................................................................................................................................................. 2277
18.6.1 SPI Base Addresses............................................................................................................................................2277
18.6.2 SPI_REGS Registers.......................................................................................................................................... 2278
18.6.3 SPI Registers to Driverlib Functions....................................................................................................................2296
19 Serial Communications Interface (SCI)........................................................................................................................ 2298
19.1 Introduction................................................................................................................................................................ 2299
19.1.1 Features.............................................................................................................................................................. 2299
19.1.2 SCI Related Collateral......................................................................................................................................... 2300
19.1.3 Block Diagram..................................................................................................................................................... 2300
19.2 Architecture................................................................................................................................................................ 2300
19.3 SCI Module Signal Summary..................................................................................................................................... 2300
19.4 Configuring Device Pins.............................................................................................................................................2302
19.5 Multiprocessor and Asynchronous Communication Modes....................................................................................... 2302
19.6 SCI Programmable Data Format................................................................................................................................2303
19.7 SCI Multiprocessor Communication...........................................................................................................................2304
19.7.1 Recognizing the Address Byte............................................................................................................................ 2304
19.7.2 Controlling the SCI TX and RX Features.............................................................................................................2304
19.7.3 Receipt Sequence............................................................................................................................................... 2304
19.8 Idle-Line Multiprocessor Mode................................................................................................................................... 2305
19.8.1 Idle-Line Mode Steps...........................................................................................................................................2305
19.8.2 Block Start Signal................................................................................................................................................ 2306
19.8.3 Wake-Up Temporary (WUT) Flag........................................................................................................................ 2306
19.8.4 Receiver Operation..............................................................................................................................................2306
19.9 Address-Bit Multiprocessor Mode.............................................................................................................................. 2307
19.9.1 Sending an Address............................................................................................................................................ 2307
19.10 SCI Communication Format.....................................................................................................................................2308
19.10.1 Receiver Signals in Communication Modes...................................................................................................... 2309
19.10.2 Transmitter Signals in Communication Modes.................................................................................................. 2310
19.11 SCI Port Interrupts.................................................................................................................................................... 2311
19.11.1 Break Detect...................................................................................................................................................... 2312
19.12 SCI Baud Rate Calculations.....................................................................................................................................2312
19.13 SCI Enhanced Features...........................................................................................................................................2313
19.13.1 SCI FIFO Description........................................................................................................................................ 2313
19.13.2 SCI Auto-Baud...................................................................................................................................................2315
19.13.3 Autobaud-Detect Sequence.............................................................................................................................. 2315
19.14 Software................................................................................................................................................................... 2316
19.14.1 SCI Examples....................................................................................................................................................2316
19.15 SCI Registers........................................................................................................................................................... 2316
19.15.1 SCI Base Addresses......................................................................................................................................... 2316
19.15.2 SCI_REGS Registers........................................................................................................................................ 2317
19.15.3 SCI Registers to Driverlib Functions..................................................................................................................2338

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20 Inter-Integrated Circuit Module (I2C).............................................................................................................................2341

20.1 Introduction................................................................................................................................................................ 2342
20.1.1 I2C Related Collateral......................................................................................................................................... 2342
20.1.2 Features.............................................................................................................................................................. 2343
20.1.3 Features Not Supported...................................................................................................................................... 2343
20.1.4 Functional Overview............................................................................................................................................ 2344
20.1.5 Clock Generation.................................................................................................................................................2345
20.1.6 I2C Clock Divider Registers (I2CCLKL and I2CCLKH)....................................................................................... 2346
20.2 Configuring Device Pins.............................................................................................................................................2347
20.3 I2C Module Operational Details................................................................................................................................. 2347
20.3.1 Input and Output Voltage Levels......................................................................................................................... 2347
20.3.2 Selecting Pullup Resistors...................................................................................................................................2347
20.3.3 Data Validity.........................................................................................................................................................2347
20.3.4 Operating Modes................................................................................................................................................. 2347
20.3.5 I2C Module START and STOP Conditions.......................................................................................................... 2351
20.3.6 Non-repeat Mode versus Repeat Mode.............................................................................................................. 2352
20.3.7 Serial Data Formats.............................................................................................................................................2352
20.3.8 Clock Synchronization......................................................................................................................................... 2355
20.3.9 Arbitration............................................................................................................................................................ 2356
20.3.10 Digital Loopback Mode...................................................................................................................................... 2357
20.3.11 NACK Bit Generation......................................................................................................................................... 2358
20.4 Interrupt Requests Generated by the I2C Module..................................................................................................... 2358
20.4.1 Basic I2C Interrupt Requests...............................................................................................................................2359
20.4.2 I2C FIFO Interrupts..............................................................................................................................................2362
20.5 Resetting or Disabling the I2C Module.......................................................................................................................2362
20.6 Software..................................................................................................................................................................... 2363
20.6.1 I2C Examples...................................................................................................................................................... 2363
20.7 I2C Registers............................................................................................................................................................. 2365
20.7.1 I2C Base Addresses............................................................................................................................................2365
20.7.2 I2C_REGS Registers...........................................................................................................................................2366
20.7.3 I2C Registers to Driverlib Functions.................................................................................................................... 2389
21 Multichannel Buffered Serial Port (McBSP)................................................................................................................. 2391
21.1 Introduction................................................................................................................................................................ 2392
21.1.1 MCBSP Related Collateral.................................................................................................................................. 2392
21.1.2 Features of the McBSPs......................................................................................................................................2392
21.1.3 McBSP Pins/Signals............................................................................................................................................2393
21.2 Configuring Device Pins.............................................................................................................................................2393
21.3 McBSP Operation...................................................................................................................................................... 2394
21.3.1 Data Transfer Process of McBSPs...................................................................................................................... 2395
21.3.2 Companding (Compressing and Expanding) Data.............................................................................................. 2395
21.3.3 Clocking and Framing Data................................................................................................................................. 2397
21.3.4 Frame Phases..................................................................................................................................................... 2399
21.3.5 McBSP Reception............................................................................................................................................... 2402
21.3.6 McBSP Transmission.......................................................................................................................................... 2403
21.3.7 Interrupts and DMA Events Generated by a McBSP...........................................................................................2404
21.4 McBSP Sample Rate Generator................................................................................................................................ 2404
21.4.1 Block Diagram..................................................................................................................................................... 2405
21.4.2 Frame Synchronization Generation in the Sample Rate Generator.................................................................... 2408
21.4.3 Synchronizing Sample Rate Generator Outputs to an External Clock................................................................ 2408
21.4.4 Reset and Initialization Procedure for the Sample Rate Generator.....................................................................2410
21.5 McBSP Exception/Error Conditions............................................................................................................................2411
21.5.1 Types of Errors.....................................................................................................................................................2411
21.5.2 Overrun in the Receiver.......................................................................................................................................2412
21.5.3 Unexpected Receive Frame-Synchronization Pulse........................................................................................... 2413
21.5.4 Overwrite in the Transmitter................................................................................................................................ 2415
21.5.5 Underflow in the Transmitter................................................................................................................................2416
21.5.6 Unexpected Transmit Frame-Synchronization Pulse.......................................................................................... 2417
21.6 Multichannel Selection Modes................................................................................................................................... 2420
21.6.1 Channels, Blocks, and Partitions.........................................................................................................................2420
21.6.2 Multichannel Selection.........................................................................................................................................2421
21.6.3 Configuring a Frame for Multichannel Selection..................................................................................................2421

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21.6.4 Using Two Partitions............................................................................................................................................2421

21.6.5 Using Eight Partitions.......................................................................................................................................... 2423
21.6.6 Receive Multichannel Selection Mode.................................................................................................................2424
21.6.7 Transmit Multichannel Selection Modes.............................................................................................................. 2425
21.6.8 Using Interrupts Between Block Transfers.......................................................................................................... 2426
21.7 SPI Operation Using the Clock Stop Mode................................................................................................................ 2428
21.7.1 SPI Protocol.........................................................................................................................................................2428
21.7.2 Clock Stop Mode................................................................................................................................................. 2428
21.7.3 Enable and Configure the Clock Stop Mode....................................................................................................... 2429
21.7.4 Clock Stop Mode Timing Diagrams..................................................................................................................... 2430
21.7.5 Procedure for Configuring a McBSP for SPI Operation.......................................................................................2432
21.7.6 McBSP as the SPI Master .................................................................................................................................. 2432
21.7.7 McBSP as an SPI Slave ..................................................................................................................................... 2434
21.8 Receiver Configuration...............................................................................................................................................2435
21.8.1 Programming the McBSP Registers for the Desired Receiver Operation........................................................... 2435
21.8.2 Resetting and Enabling the Receiver.................................................................................................................. 2436
21.8.3 Set the Receiver Pins to Operate as McBSP Pins.............................................................................................. 2437
21.8.4 Digital Loopback Mode........................................................................................................................................ 2437
21.8.5 Clock Stop Mode................................................................................................................................................. 2437
21.8.6 Receive Multichannel Selection Mode.................................................................................................................2438
21.8.7 Receive Frame Phases....................................................................................................................................... 2438
21.8.8 Receive Word Lengths........................................................................................................................................ 2439
21.8.9 Receive Frame Length........................................................................................................................................ 2440
21.8.10 Receive Frame-Synchronization Ignore Function............................................................................................. 2441
21.8.11 Receive Companding Mode...............................................................................................................................2442
21.8.12 Receive Data Delay...........................................................................................................................................2444
21.8.13 Receive Sign-Extension and Justification Mode................................................................................................2446
21.8.14 Receive Interrupt Mode..................................................................................................................................... 2447
21.8.15 Receive Frame-Synchronization Mode............................................................................................................. 2447
21.8.16 Receive Frame-Synchronization Polarity.......................................................................................................... 2449
21.8.17 Receive Clock Mode..........................................................................................................................................2452
21.8.18 Receive Clock Polarity.......................................................................................................................................2453
21.8.19 SRG Clock Divide-Down Value..........................................................................................................................2455
21.8.20 SRG Clock Synchronization Mode.................................................................................................................... 2455
21.8.21 SRG Clock Mode (Choose an Input Clock)....................................................................................................... 2456
21.8.22 SRG Input Clock Polarity...................................................................................................................................2456
21.9 Transmitter Configuration...........................................................................................................................................2457
21.9.1 Programming the McBSP Registers for the Desired Transmitter Operation....................................................... 2457
21.9.2 Resetting and Enabling the Transmitter.............................................................................................................. 2458
21.9.3 Set the Transmitter Pins to Operate as McBSP Pins.......................................................................................... 2458
21.9.4 Digital Loopback Mode........................................................................................................................................ 2459
21.9.5 Clock Stop Mode................................................................................................................................................. 2459
21.9.6 Transmit Multichannel Selection Mode................................................................................................................2460
21.9.7 XCERs Used in the Transmit Multichannel Selection Mode................................................................................2461
21.9.8 Transmit Frame Phases...................................................................................................................................... 2463
21.9.9 Transmit Word Lengths....................................................................................................................................... 2463
21.9.10 Transmit Frame Length..................................................................................................................................... 2464
21.9.11 Enable/Disable the Transmit Frame-Synchronization Ignore Function..............................................................2465
21.9.12 Transmit Companding Mode............................................................................................................................. 2466
21.9.13 Transmit Data Delay.......................................................................................................................................... 2467
21.9.14 Transmit DXENA Mode..................................................................................................................................... 2469
21.9.15 Transmit Interrupt Mode.................................................................................................................................... 2469
21.9.16 Transmit Frame-Synchronization Mode.............................................................................................................2470
21.9.17 Transmit Frame-Synchronization Polarity..........................................................................................................2471
21.9.18 SRG Frame-Synchronization Period and Pulse Width...................................................................................... 2472
21.9.19 Transmit Clock Mode.........................................................................................................................................2473
21.9.20 Transmit Clock Polarity......................................................................................................................................2473
21.10 Emulation and Reset Considerations.......................................................................................................................2475
21.10.1 McBSP Emulation Mode....................................................................................................................................2475
21.10.2 Resetting and Initializing McBSPs.....................................................................................................................2475
21.11 Data Packing Examples........................................................................................................................................... 2478

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21.11.1 Data Packing Using Frame Length and Word Length....................................................................................... 2478
21.11.2 Data Packing Using Word Length and the Frame-Synchronization Ignore Function.........................................2480
21.12 Interrupt Generation................................................................................................................................................. 2481
21.12.1 McBSP Receive Interrupt Generation............................................................................................................... 2481
21.12.2 McBSP Transmit Interrupt Generation...............................................................................................................2482
21.12.3 Error Flags.........................................................................................................................................................2482
21.13 McBSP Modes......................................................................................................................................................... 2483
21.14 Special Case: External Device is the Transmit Frame Master ................................................................................ 2483
21.15 Software................................................................................................................................................................... 2485
21.15.1 MCBSP Examples............................................................................................................................................. 2485
21.16 McBSP Registers..................................................................................................................................................... 2485
21.16.1 McBSP Base Addresses................................................................................................................................... 2485
21.16.2 McBSP_REGS Registers.................................................................................................................................. 2486
21.16.3 MCBSP Registers to Driverlib Functions...........................................................................................................2530
22 Controller Area Network (CAN)..................................................................................................................................... 2534
22.1 Introduction................................................................................................................................................................ 2535
22.1.1 DCAN Related Collateral.....................................................................................................................................2535
22.1.2 Features.............................................................................................................................................................. 2535
22.1.3 Block Diagram..................................................................................................................................................... 2536
22.2 Functional Description................................................................................................................................................2538
22.2.1 Configuring Device Pins...................................................................................................................................... 2538
22.2.2 Address/Data Bus Bridge.................................................................................................................................... 2538
22.3 Operating Modes........................................................................................................................................................2540
22.3.1 Initialization..........................................................................................................................................................2540
22.3.2 CAN Message Transfer (Normal Operation)....................................................................................................... 2541
22.3.3 Test Modes.......................................................................................................................................................... 2542
22.4 Multiple Clock Source................................................................................................................................................ 2546
22.5 Interrupt Functionality.................................................................................................................................................2547
22.5.1 Message Object Interrupts.................................................................................................................................. 2547
22.5.2 Status Change Interrupts.....................................................................................................................................2547
22.5.3 Error Interrupts.................................................................................................................................................... 2547
22.5.4 Peripheral Interrupt Expansion (PIE) Module Nomenclature for DCAN Interrupts.............................................. 2547
22.5.5 Interrupt Topologies............................................................................................................................................. 2548
22.6 Parity Check Mechanism........................................................................................................................................... 2549
22.6.1 Behavior on Parity Error...................................................................................................................................... 2549
22.7 Debug Mode...............................................................................................................................................................2550
22.8 Module Initialization....................................................................................................................................................2550
22.9 Configuration of Message Objects............................................................................................................................. 2551
22.9.1 Configuration of a Transmit Object for Data Frames........................................................................................... 2551
22.9.2 Configuration of a Transmit Object for Remote Frames...................................................................................... 2551
22.9.3 Configuration of a Single Receive Object for Data Frames.................................................................................2551
22.9.4 Configuration of a Single Receive Object for Remote Frames............................................................................2552
22.9.5 Configuration of a FIFO Buffer.............................................................................................................................2552
22.10 Message Handling................................................................................................................................................... 2552
22.10.1 Message Handler Overview.............................................................................................................................. 2553
22.10.2 Receive/Transmit Priority...................................................................................................................................2553
22.10.3 Transmission of Messages in Event Driven CAN Communication.................................................................... 2553
22.10.4 Updating a Transmit Object............................................................................................................................... 2554
22.10.5 Changing a Transmit Object.............................................................................................................................. 2554
22.10.6 Acceptance Filtering of Received Messages.....................................................................................................2555
22.10.7 Reception of Data Frames.................................................................................................................................2555
22.10.8 Reception of Remote Frames............................................................................................................................2555
22.10.9 Reading Received Messages............................................................................................................................2555
22.10.10 Requesting New Data for a Receive Object.................................................................................................... 2556
22.10.11 Storing Received Messages in FIFO Buffers...................................................................................................2556
22.10.12 Reading from a FIFO Buffer............................................................................................................................ 2556
22.11 CAN Bit Timing......................................................................................................................................................... 2558
22.11.1 Bit Time and Bit Rate......................................................................................................................................... 2558
22.11.2 Configuration of the CAN Bit Timing.................................................................................................................. 2563
22.12 Message Interface Register Sets............................................................................................................................. 2567
22.12.1 Message Interface Register Sets 1 and 2 (IF1 and IF2)....................................................................................2567

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22.12.2 Message Interface Register Set 3 (IF3).............................................................................................................2568

22.13 Message RAM..........................................................................................................................................................2569
22.13.1 Structure of Message Objects........................................................................................................................... 2569
22.13.2 Addressing Message Objects in RAM............................................................................................................... 2572
22.13.3 Message RAM Representation in Debug Mode................................................................................................ 2573
22.14 Software................................................................................................................................................................... 2574
22.14.1 CAN Examples.................................................................................................................................................. 2574
22.15 CAN Registers......................................................................................................................................................... 2574
22.15.1 CAN Base Addresses........................................................................................................................................2574
22.15.2 CAN_REGS Registers.......................................................................................................................................2575
22.15.3 CAN Registers to Driverlib Functions................................................................................................................ 2631
23 Universal Serial Bus (USB) Controller..........................................................................................................................2635
23.1 Introduction................................................................................................................................................................ 2636
23.1.1 Features.............................................................................................................................................................. 2636
23.1.2 USB Related Collateral........................................................................................................................................2636
23.1.3 Block Diagram..................................................................................................................................................... 2637
23.2 Functional Description................................................................................................................................................2639
23.2.1 Operation as a Device......................................................................................................................................... 2639
23.2.2 Operation as a Host.............................................................................................................................................2644
23.2.3 DMA Operation....................................................................................................................................................2648
23.2.4 Address/Data Bus Bridge.................................................................................................................................... 2648
23.3 Initialization and Configuration................................................................................................................................... 2650
23.3.1 Pin Configuration................................................................................................................................................. 2650
23.3.2 Endpoint Configuration........................................................................................................................................ 2651
23.4 USB Global Interrupts................................................................................................................................................ 2651
23.5 Software..................................................................................................................................................................... 2652
23.5.1 USB Examples.................................................................................................................................................... 2652
23.6 USB Registers............................................................................................................................................................2652
23.6.1 USB Base Address..............................................................................................................................................2652
23.6.2 USB Register Map...............................................................................................................................................2652
23.6.3 Register Descriptions.......................................................................................................................................... 2660
23.6.4 USB Registers to Driverlib Functions.................................................................................................................. 2731
24 Universal Parallel Port (uPP)......................................................................................................................................... 2748
24.1 Introduction................................................................................................................................................................ 2749
24.1.1 Features Supported.............................................................................................................................................2749
24.2 Configuring Device Pins.............................................................................................................................................2750
24.3 Functional Description................................................................................................................................................2750
24.3.1 Functional Block Diagram....................................................................................................................................2750
24.3.2 Data Flow............................................................................................................................................................ 2751
24.3.3 Clock Generation and Control............................................................................................................................. 2752
24.4 IO Interface and System Requirements..................................................................................................................... 2753
24.4.1 Pin Multiplexing................................................................................................................................................... 2753
24.4.2 Internal DMA Controller Description.................................................................................................................... 2753
24.4.3 Protocol Description............................................................................................................................................ 2755
24.4.4 Data Format.........................................................................................................................................................2758
24.4.5 Reset Considerations.......................................................................................................................................... 2759
24.4.6 Interrupt Support..................................................................................................................................................2759
24.4.7 Emulation Considerations....................................................................................................................................2760
24.4.8 Transmit and Receive FIFOs...............................................................................................................................2760
24.4.9 Transmit and Receive Data (MSG) RAM.............................................................................................................2761
24.4.10 Initialization and Operation................................................................................................................................ 2762
24.5 UPP Registers............................................................................................................................................................2763
24.5.1 UPP Base Addresses.......................................................................................................................................... 2763
24.5.2 UPP_REGS Registers.........................................................................................................................................2764
24.5.3 UPP Registers to Driverlib Functions.................................................................................................................. 2798
25 External Memory Interface (EMIF).................................................................................................................................2801
25.1 Introduction................................................................................................................................................................ 2802
25.1.1 Purpose of the Peripheral....................................................................................................................................2803
25.1.2 EMIF Related Collateral...................................................................................................................................... 2803
25.1.3 Features.............................................................................................................................................................. 2804
25.1.4 Functional Block Diagram....................................................................................................................................2805

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25.1.5 Configuring Device Pins...................................................................................................................................... 2805

25.2 EMIF Module Architecture..........................................................................................................................................2806
25.2.1 EMIF Clock Control............................................................................................................................................. 2806
25.2.2 EMIF Requests....................................................................................................................................................2806
25.2.3 EMIF Signal Descriptions.................................................................................................................................... 2807
25.2.4 EMIF Signal Multiplexing Control........................................................................................................................ 2808
25.2.5 SDRAM Controller and Interface......................................................................................................................... 2808
25.2.6 Asynchronous Controller and Interface............................................................................................................... 2821
25.2.7 Data Bus Parking.................................................................................................................................................2833
25.2.8 Reset and Initialization Considerations............................................................................................................... 2833
25.2.9 Interrupt Support..................................................................................................................................................2833
25.2.10 DMA Event Support...........................................................................................................................................2834
25.2.11 EMIF Signal Multiplexing................................................................................................................................... 2834
25.2.12 Memory Map......................................................................................................................................................2834
25.2.13 Priority and Arbitration....................................................................................................................................... 2835
25.2.14 System Considerations......................................................................................................................................2835
25.2.15 Power Management.......................................................................................................................................... 2836
25.2.16 Emulation Considerations..................................................................................................................................2836
25.3 Example Configuration...............................................................................................................................................2836
25.3.1 Hardware Interface.............................................................................................................................................. 2836
25.3.2 Software Configuration........................................................................................................................................ 2837
25.4 EMIF Registers.......................................................................................................................................................... 2844
25.4.1 EMIF Base Addresses.........................................................................................................................................2844
25.4.2 EMIF_REGS Registers........................................................................................................................................2845
25.4.3 EMIF1_CONFIG_REGS Registers......................................................................................................................2865
25.4.4 EMIF2_CONFIG_REGS Registers......................................................................................................................2870
25.4.5 EMIF Registers to Driverlib Functions................................................................................................................. 2873
26 Configurable Logic Block (CLB)....................................................................................................................................2875
26.1 Introduction................................................................................................................................................................ 2876
26.1.1 CLB Related Collateral........................................................................................................................................ 2876
26.2 Description................................................................................................................................................................. 2876
26.2.1 CLB Clock............................................................................................................................................................2878
26.3 CLB Input/Output Connection.................................................................................................................................... 2879
26.3.1 Overview..............................................................................................................................................................2879
26.3.2 CLB Input Selection.............................................................................................................................................2879
26.3.3 CLB Output Selection.......................................................................................................................................... 2885
26.3.4 CLB Output Signal Multiplexer............................................................................................................................ 2886
26.4 CLB Tile......................................................................................................................................................................2887
26.4.1 Static Switch Block.............................................................................................................................................. 2888
26.4.2 Counter Block...................................................................................................................................................... 2890
26.4.3 FSM Block........................................................................................................................................................... 2893
26.4.4 LUT4 Block.......................................................................................................................................................... 2895
26.4.5 Output LUT Block................................................................................................................................................ 2895
26.4.6 High Level Controller (HLC)................................................................................................................................ 2896
26.5 CPU Interface.............................................................................................................................................................2900
26.5.1 Register Description............................................................................................................................................ 2900
26.5.2 Non-Memory Mapped Registers..........................................................................................................................2901
26.6 DMA Access...............................................................................................................................................................2901
26.7 Software..................................................................................................................................................................... 2902
26.7.1 CLB Examples.....................................................................................................................................................2902
26.8 CLB Registers............................................................................................................................................................ 2905
26.8.1 CLB Base Addresses.......................................................................................................................................... 2905
26.8.2 CLB_LOGIC_CONFIG_REGS Registers............................................................................................................ 2906
26.8.3 CLB_LOGIC_CONTROL_REGS Registers........................................................................................................ 2938
26.8.4 CLB_DATA_EXCHANGE_REGS Registers........................................................................................................ 2965
26.8.5 CLB Registers to Driverlib Functions...................................................................................................................2967
27 Revision History............................................................................................................................................................. 2970

List of Figures
Figure 3-1. Device Interrupt Architecture...................................................................................................................................88

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Figure 3-2. Interrupt Propagation Path...................................................................................................................................... 89

Figure 3-3. Missing Clock Detection Logic.............................................................................................................................. 102
Figure 3-4. ERRORSTS Pin Diagram......................................................................................................................................104
Figure 3-5. Clocking System....................................................................................................................................................105
Figure 3-6. Single-ended 3.3V External Clock.........................................................................................................................106
Figure 3-7. External Crystal..................................................................................................................................................... 106
Figure 3-8. External Resonator................................................................................................................................................107
Figure 3-9. AUXCLKIN............................................................................................................................................................ 107
Figure 3-10. Missing Clock Detection Logic.............................................................................................................................115
Figure 3-11. CPU-Timers......................................................................................................................................................... 116
Figure 3-12. CPU-Timer Interrupts Signals and Output Signal................................................................................................ 117
Figure 3-13. CPU Watchdog Timer Module............................................................................................................................. 118
Figure 3-14. Memory Architecture........................................................................................................................................... 125
Figure 3-15. Arbitration Scheme on Global Shared Memories................................................................................................ 127
Figure 3-16. Arbitration Scheme on Local Shared Memories..................................................................................................128
Figure 3-17. FMC Interface with Core, Bank, and Pump.........................................................................................................135
Figure 3-18. Flash Prefetch Mode........................................................................................................................................... 138
Figure 3-19. ECC Logic Inputs and Outputs............................................................................................................................141
Figure 3-20. Flash Pump Semaphore (PUMPREQUEST) States and State Transitions........................................................ 145
Figure 3-21. Clock Configuration Semaphore (CLKSEM) State Transitions........................................................................... 146
Figure 3-22. Storage of Zone-Select Bits in OTP Memory...................................................................................................... 151
Figure 3-23. Location of Zone-Select Block Based on Link-Pointer........................................................................................ 152
Figure 3-24. CSM Password Match Flow (PMF)..................................................................................................................... 156
Figure 3-25. ECSL Password Match Flow (PMF)....................................................................................................................158
Figure 3-26. TIM Register........................................................................................................................................................168
Figure 3-27. PRD Register...................................................................................................................................................... 169
Figure 3-28. TCR Register.......................................................................................................................................................170
Figure 3-29. TPR Register.......................................................................................................................................................172
Figure 3-30. TPRH Register.................................................................................................................................................... 173
Figure 3-31. PIECTRL Register...............................................................................................................................................176
Figure 3-32. PIEACK Register.................................................................................................................................................177
Figure 3-33. PIEIER1 Register................................................................................................................................................ 178
Figure 3-34. PIEIFR1 Register................................................................................................................................................ 180
Figure 3-35. PIEIER2 Register................................................................................................................................................ 182
Figure 3-36. PIEIFR2 Register................................................................................................................................................ 184
Figure 3-37. PIEIER3 Register................................................................................................................................................ 186
Figure 3-38. PIEIFR3 Register................................................................................................................................................ 188
Figure 3-39. PIEIER4 Register................................................................................................................................................ 190
Figure 3-40. PIEIFR4 Register................................................................................................................................................ 192
Figure 3-41. PIEIER5 Register................................................................................................................................................ 194
Figure 3-42. PIEIFR5 Register................................................................................................................................................ 196
Figure 3-43. PIEIER6 Register................................................................................................................................................ 198
Figure 3-44. PIEIFR6 Register................................................................................................................................................ 200
Figure 3-45. PIEIER7 Register................................................................................................................................................ 202
Figure 3-46. PIEIFR7 Register................................................................................................................................................ 204
Figure 3-47. PIEIER8 Register................................................................................................................................................ 206
Figure 3-48. PIEIFR8 Register................................................................................................................................................ 208
Figure 3-49. PIEIER9 Register................................................................................................................................................ 210
Figure 3-50. PIEIFR9 Register................................................................................................................................................ 212
Figure 3-51. PIEIER10 Register.............................................................................................................................................. 214
Figure 3-52. PIEIFR10 Register.............................................................................................................................................. 216
Figure 3-53. PIEIER11 Register...............................................................................................................................................218
Figure 3-54. PIEIFR11 Register...............................................................................................................................................220
Figure 3-55. PIEIER12 Register.............................................................................................................................................. 222
Figure 3-56. PIEIFR12 Register.............................................................................................................................................. 224
Figure 3-57. SCSR Register.................................................................................................................................................... 227
Figure 3-58. WDCNTR Register.............................................................................................................................................. 228
Figure 3-59. WDKEY Register.................................................................................................................................................229
Figure 3-60. WDCR Register...................................................................................................................................................230
Figure 3-61. WDWCR Register................................................................................................................................................231
Figure 3-62. NMICFG Register................................................................................................................................................233

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Figure 3-63. NMIFLG Register................................................................................................................................................ 234

Figure 3-64. NMIFLGCLR Register......................................................................................................................................... 236
Figure 3-65. NMIFLGFRC Register......................................................................................................................................... 239
Figure 3-66. NMIWDCNT Register.......................................................................................................................................... 241
Figure 3-67. NMIWDPRD Register..........................................................................................................................................242
Figure 3-68. NMISHDFLG Register.........................................................................................................................................243
Figure 3-69. XINT1CR Register...............................................................................................................................................246
Figure 3-70. XINT2CR Register...............................................................................................................................................247
Figure 3-71. XINT3CR Register...............................................................................................................................................248
Figure 3-72. XINT4CR Register...............................................................................................................................................249
Figure 3-73. XINT5CR Register...............................................................................................................................................250
Figure 3-74. XINT1CTR Register............................................................................................................................................ 251
Figure 3-75. XINT2CTR Register............................................................................................................................................ 252
Figure 3-76. XINT3CTR Register............................................................................................................................................ 253
Figure 3-77. SYNCSELECT Register...................................................................................................................................... 255
Figure 3-78. ADCSOCOUTSELECT Register......................................................................................................................... 257
Figure 3-79. SYNCSOCLOCK Register.................................................................................................................................. 260
Figure 3-80. CLA1TASKSRCSELLOCK Register....................................................................................................................262
Figure 3-81. DMACHSRCSELLOCK Register.........................................................................................................................263
Figure 3-82. CLA1TASKSRCSEL1 Register............................................................................................................................264
Figure 3-83. CLA1TASKSRCSEL2 Register............................................................................................................................265
Figure 3-84. DMACHSRCSEL1 Register................................................................................................................................ 266
Figure 3-85. DMACHSRCSEL2 Register................................................................................................................................ 267
Figure 3-86. PUMPREQUEST Register.................................................................................................................................. 269
Figure 3-87. DEVCFGLOCK1 Register................................................................................................................................... 272
Figure 3-88. PARTIDL Register............................................................................................................................................... 274
Figure 3-89. PARTIDH Register...............................................................................................................................................276
Figure 3-90. REVID Register................................................................................................................................................... 277
Figure 3-91. DC0 Register.......................................................................................................................................................278
Figure 3-92. DC1 Register.......................................................................................................................................................279
Figure 3-93. DC2 Register.......................................................................................................................................................280
Figure 3-94. DC3 Register.......................................................................................................................................................281
Figure 3-95. DC4 Register.......................................................................................................................................................283
Figure 3-96. DC5 Register.......................................................................................................................................................284
Figure 3-97. DC6 Register.......................................................................................................................................................285
Figure 3-98. DC7 Register.......................................................................................................................................................286
Figure 3-99. DC8 Register.......................................................................................................................................................287
Figure 3-100. DC9 Register.....................................................................................................................................................288
Figure 3-101. DC10 Register...................................................................................................................................................289
Figure 3-102. DC11 Register................................................................................................................................................... 290
Figure 3-103. DC12 Register...................................................................................................................................................291
Figure 3-104. DC13 Register...................................................................................................................................................292
Figure 3-105. DC14 Register...................................................................................................................................................293
Figure 3-106. DC15 Register...................................................................................................................................................294
Figure 3-107. DC17 Register...................................................................................................................................................296
Figure 3-108. DC18 Register...................................................................................................................................................297
Figure 3-109. DC19 Register...................................................................................................................................................298
Figure 3-110. DC20 Register................................................................................................................................................... 299
Figure 3-111. PERCNF1 Register............................................................................................................................................301
Figure 3-112. FUSEERR Register........................................................................................................................................... 302
Figure 3-113. SOFTPRES0 Register....................................................................................................................................... 303
Figure 3-114. SOFTPRES1 Register....................................................................................................................................... 304
Figure 3-115. SOFTPRES2 Register....................................................................................................................................... 305
Figure 3-116. SOFTPRES3 Register....................................................................................................................................... 307
Figure 3-117. SOFTPRES4 Register....................................................................................................................................... 308
Figure 3-118. SOFTPRES6 Register....................................................................................................................................... 309
Figure 3-119. SOFTPRES7 Register....................................................................................................................................... 310
Figure 3-120. SOFTPRES8 Register....................................................................................................................................... 311
Figure 3-121. SOFTPRES9 Register.......................................................................................................................................312
Figure 3-122. SOFTPRES11 Register..................................................................................................................................... 313
Figure 3-123. SOFTPRES13 Register.....................................................................................................................................314

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Figure 3-124. SOFTPRES14 Register.....................................................................................................................................315

Figure 3-125. SOFTPRES16 Register.....................................................................................................................................316
Figure 3-126. CPUSEL0 Register............................................................................................................................................317
Figure 3-127. CPUSEL1 Register............................................................................................................................................319
Figure 3-128. CPUSEL2 Register............................................................................................................................................320
Figure 3-129. CPUSEL3 Register............................................................................................................................................321
Figure 3-130. CPUSEL4 Register............................................................................................................................................322
Figure 3-131. CPUSEL5 Register............................................................................................................................................323
Figure 3-132. CPUSEL6 Register............................................................................................................................................324
Figure 3-133. CPUSEL7 Register............................................................................................................................................325
Figure 3-134. CPUSEL8 Register............................................................................................................................................326
Figure 3-135. CPUSEL9 Register............................................................................................................................................327
Figure 3-136. CPUSEL11 Register.......................................................................................................................................... 328
Figure 3-137. CPUSEL12 Register..........................................................................................................................................330
Figure 3-138. CPUSEL14 Register..........................................................................................................................................332
Figure 3-139. CPU2RESCTL Register.................................................................................................................................... 333
Figure 3-140. RSTSTAT Register............................................................................................................................................ 334
Figure 3-141. LPMSTAT Register............................................................................................................................................ 335
Figure 3-142. SYSDBGCTL Register...................................................................................................................................... 336
Figure 3-143. CLKSEM Register............................................................................................................................................. 339
Figure 3-144. CLKCFGLOCK1 Register..................................................................................................................................340
Figure 3-145. CLKSRCCTL1 Register.....................................................................................................................................342
Figure 3-146. CLKSRCCTL2 Register.....................................................................................................................................344
Figure 3-147. CLKSRCCTL3 Register.....................................................................................................................................346
Figure 3-148. SYSPLLCTL1 Register......................................................................................................................................347
Figure 3-149. SYSPLLMULT Register..................................................................................................................................... 348
Figure 3-150. SYSPLLSTS Register....................................................................................................................................... 349
Figure 3-151. AUXPLLCTL1 Register..................................................................................................................................... 350
Figure 3-152. AUXPLLMULT Register.....................................................................................................................................351
Figure 3-153. AUXPLLSTS Register....................................................................................................................................... 352
Figure 3-154. SYSCLKDIVSEL Register................................................................................................................................. 353
Figure 3-155. AUXCLKDIVSEL Register.................................................................................................................................354
Figure 3-156. PERCLKDIVSEL Register.................................................................................................................................355
Figure 3-157. XCLKOUTDIVSEL Register.............................................................................................................................. 356
Figure 3-158. LOSPCP Register............................................................................................................................................. 357
Figure 3-159. MCDCR Register...............................................................................................................................................358
Figure 3-160. X1CNT Register................................................................................................................................................ 359
Figure 3-161. CPUSYSLOCK1 Register................................................................................................................................. 362
Figure 3-162. HIBBOOTMODE Register................................................................................................................................. 365
Figure 3-163. IORESTOREADDR Register.............................................................................................................................366
Figure 3-164. PIEVERRADDR Register.................................................................................................................................. 367
Figure 3-165. PCLKCR0 Register........................................................................................................................................... 368
Figure 3-166. PCLKCR1 Register........................................................................................................................................... 370
Figure 3-167. PCLKCR2 Register........................................................................................................................................... 371
Figure 3-168. PCLKCR3 Register........................................................................................................................................... 373
Figure 3-169. PCLKCR4 Register........................................................................................................................................... 374
Figure 3-170. PCLKCR6 Register........................................................................................................................................... 375
Figure 3-171. PCLKCR7 Register........................................................................................................................................... 376
Figure 3-172. PCLKCR8 Register........................................................................................................................................... 377
Figure 3-173. PCLKCR9 Register........................................................................................................................................... 378
Figure 3-174. PCLKCR10 Register......................................................................................................................................... 379
Figure 3-175. PCLKCR11 Register..........................................................................................................................................380
Figure 3-176. PCLKCR12 Register......................................................................................................................................... 381
Figure 3-177. PCLKCR13 Register......................................................................................................................................... 382
Figure 3-178. PCLKCR14 Register......................................................................................................................................... 383
Figure 3-179. PCLKCR16 Register......................................................................................................................................... 385
Figure 3-180. SECMSEL Register...........................................................................................................................................386
Figure 3-181. LPMCR Register............................................................................................................................................... 387
Figure 3-182. GPIOLPMSEL0 Register...................................................................................................................................389
Figure 3-183. GPIOLPMSEL1 Register...................................................................................................................................392
Figure 3-184. TMR2CLKCTL Register.................................................................................................................................... 395

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Figure 3-185. RESC Register.................................................................................................................................................. 397

Figure 3-186. ROMPREFETCH Register................................................................................................................................ 400
Figure 3-187. Z1_LINKPOINTER Register..............................................................................................................................402
Figure 3-188. Z1_OTPSECLOCK Register............................................................................................................................. 403
Figure 3-189. Z1_BOOTCTRL Register.................................................................................................................................. 404
Figure 3-190. Z1_LINKPOINTERERR Register...................................................................................................................... 405
Figure 3-191. Z1_CSMKEY0 Register.....................................................................................................................................406
Figure 3-192. Z1_CSMKEY1 Register.....................................................................................................................................407
Figure 3-193. Z1_CSMKEY2 Register.....................................................................................................................................408
Figure 3-194. Z1_CSMKEY3 Register.....................................................................................................................................409
Figure 3-195. Z1_CR Register.................................................................................................................................................410
Figure 3-196. Z1_GRABSECTR Register................................................................................................................................411
Figure 3-197. Z1_GRABRAMR Register................................................................................................................................. 414
Figure 3-198. Z1_EXEONLYSECTR Register......................................................................................................................... 416
Figure 3-199. Z1_EXEONLYRAMR Register...........................................................................................................................419
Figure 3-200. Z2_LINKPOINTER Register..............................................................................................................................422
Figure 3-201. Z2_OTPSECLOCK Register............................................................................................................................. 423
Figure 3-202. Z2_BOOTCTRL Register.................................................................................................................................. 424
Figure 3-203. Z2_LINKPOINTERERR Register...................................................................................................................... 425
Figure 3-204. Z2_CSMKEY0 Register.....................................................................................................................................426
Figure 3-205. Z2_CSMKEY1 Register.....................................................................................................................................427
Figure 3-206. Z2_CSMKEY2 Register.....................................................................................................................................428
Figure 3-207. Z2_CSMKEY3 Register.....................................................................................................................................429
Figure 3-208. Z2_CR Register.................................................................................................................................................430
Figure 3-209. Z2_GRABSECTR Register............................................................................................................................... 431
Figure 3-210. Z2_GRABRAMR Register................................................................................................................................. 434
Figure 3-211. Z2_EXEONLYSECTR Register......................................................................................................................... 436
Figure 3-212. Z2_EXEONLYRAMR Register...........................................................................................................................439
Figure 3-213. FLSEM Register................................................................................................................................................ 442
Figure 3-214. SECTSTAT Register..........................................................................................................................................443
Figure 3-215. RAMSTAT Register........................................................................................................................................... 446
Figure 3-216. DxLOCK Register..............................................................................................................................................450
Figure 3-217. DxCOMMIT Register......................................................................................................................................... 451
Figure 3-218. DxACCPROT0 Register.................................................................................................................................... 452
Figure 3-219. DxTEST Register.............................................................................................................................................. 453
Figure 3-220. DxINIT Register.................................................................................................................................................454
Figure 3-221. DxINITDONE Register...................................................................................................................................... 455
Figure 3-222. LSxLOCK Register............................................................................................................................................ 456
Figure 3-223. LSxCOMMIT Register....................................................................................................................................... 458
Figure 3-224. LSxMSEL Register............................................................................................................................................ 460
Figure 3-225. LSxCLAPGM Register.......................................................................................................................................462
Figure 3-226. LSxACCPROT0 Register.................................................................................................................................. 463
Figure 3-227. LSxACCPROT1 Register.................................................................................................................................. 465
Figure 3-228. LSxTEST Register.............................................................................................................................................466
Figure 3-229. LSxINIT Register............................................................................................................................................... 468
Figure 3-230. LSxINITDONE Register.....................................................................................................................................469
Figure 3-231. GSxLOCK Register........................................................................................................................................... 470
Figure 3-232. GSxCOMMIT Register...................................................................................................................................... 472
Figure 3-233. GSxMSEL Register........................................................................................................................................... 475
Figure 3-234. GSxACCPROT0 Register................................................................................................................................. 477
Figure 3-235. GSxACCPROT1 Register................................................................................................................................. 479
Figure 3-236. GSxACCPROT2 Register................................................................................................................................. 481
Figure 3-237. GSxACCPROT3 Register................................................................................................................................. 483
Figure 3-238. GSxTEST Register............................................................................................................................................485
Figure 3-239. GSxINIT Register.............................................................................................................................................. 488
Figure 3-240. GSxINITDONE Register....................................................................................................................................490
Figure 3-241. MSGxTEST Register.........................................................................................................................................492
Figure 3-242. MSGxINIT Register........................................................................................................................................... 493
Figure 3-243. MSGxINITDONE Register.................................................................................................................................494
Figure 3-244. NMAVFLG Register........................................................................................................................................... 497
Figure 3-245. NMAVSET Register........................................................................................................................................... 499

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Figure 3-246. NMAVCLR Register...........................................................................................................................................501

Figure 3-247. NMAVINTEN Register....................................................................................................................................... 503
Figure 3-248. NMCPURDAVADDR Register........................................................................................................................... 504
Figure 3-249. NMCPUWRAVADDR Register.......................................................................................................................... 505
Figure 3-250. NMCPUFAVADDR Register.............................................................................................................................. 506
Figure 3-251. NMDMAWRAVADDR Register.......................................................................................................................... 507
Figure 3-252. NMCLA1RDAVADDR Register..........................................................................................................................508
Figure 3-253. NMCLA1WRAVADDR Register......................................................................................................................... 509
Figure 3-254. NMCLA1FAVADDR Register............................................................................................................................. 510
Figure 3-255. MAVFLG Register..............................................................................................................................................511
Figure 3-256. MAVSET Register..............................................................................................................................................512
Figure 3-257. MAVCLR Register............................................................................................................................................. 513
Figure 3-258. MAVINTEN Register..........................................................................................................................................514
Figure 3-259. MCPUFAVADDR Register................................................................................................................................. 515
Figure 3-260. MCPUWRAVADDR Register............................................................................................................................. 516
Figure 3-261. MDMAWRAVADDR Register.............................................................................................................................517
Figure 3-262. UCERRFLG Register........................................................................................................................................ 519
Figure 3-263. UCERRSET Register........................................................................................................................................ 520
Figure 3-264. UCERRCLR Register........................................................................................................................................ 521
Figure 3-265. UCCPUREADDR Register................................................................................................................................ 522
Figure 3-266. UCDMAREADDR Register................................................................................................................................523
Figure 3-267. UCCLA1READDR Register...............................................................................................................................524
Figure 3-268. CERRFLG Register...........................................................................................................................................525
Figure 3-269. CERRSET Register...........................................................................................................................................526
Figure 3-270. CERRCLR Register...........................................................................................................................................527
Figure 3-271. CCPUREADDR Register...................................................................................................................................528
Figure 3-272. CERRCNT Register.......................................................................................................................................... 529
Figure 3-273. CERRTHRES Register......................................................................................................................................530
Figure 3-274. CEINTFLG Register.......................................................................................................................................... 531
Figure 3-275. CEINTCLR Register.......................................................................................................................................... 532
Figure 3-276. CEINTSET Register.......................................................................................................................................... 533
Figure 3-277. CEINTEN Register............................................................................................................................................ 534
Figure 3-278. ROMWAITSTATE Register................................................................................................................................536
Figure 3-279. FRDCNTL Register........................................................................................................................................... 538
Figure 3-280. FBAC Register.................................................................................................................................................. 539
Figure 3-281. FBFALLBACK Register..................................................................................................................................... 540
Figure 3-282. FBPRDY Register............................................................................................................................................. 541
Figure 3-283. FPAC1 Register.................................................................................................................................................542
Figure 3-284. FMSTAT Register.............................................................................................................................................. 543
Figure 3-285. FRD_INTF_CTRL Register............................................................................................................................... 545
Figure 3-286. ECC_ENABLE Register.................................................................................................................................... 548
Figure 3-287. SINGLE_ERR_ADDR_LOW Register...............................................................................................................549
Figure 3-288. SINGLE_ERR_ADDR_HIGH Register.............................................................................................................. 550
Figure 3-289. UNC_ERR_ADDR_LOW Register.................................................................................................................... 551
Figure 3-290. UNC_ERR_ADDR_HIGH Register................................................................................................................... 552
Figure 3-291. ERR_STATUS Register.....................................................................................................................................553
Figure 3-292. ERR_POS Register...........................................................................................................................................555
Figure 3-293. ERR_STATUS_CLR Register............................................................................................................................556
Figure 3-294. ERR_CNT Register........................................................................................................................................... 557
Figure 3-295. ERR_THRESHOLD Register............................................................................................................................ 558
Figure 3-296. ERR_INTFLG Register......................................................................................................................................559
Figure 3-297. ERR_INTCLR Register..................................................................................................................................... 560
Figure 3-298. FDATAH_TEST Register................................................................................................................................... 561
Figure 3-299. FDATAL_TEST Register....................................................................................................................................562
Figure 3-300. FADDR_TEST Register.....................................................................................................................................563
Figure 3-301. FECC_TEST Register....................................................................................................................................... 564
Figure 3-302. FECC_CTRL Register.......................................................................................................................................565
Figure 3-303. FOUTH_TEST Register.................................................................................................................................... 566
Figure 3-304. FOUTL_TEST Register..................................................................................................................................... 567
Figure 3-305. FECC_STATUS Register...................................................................................................................................568
Figure 3-306. CPUID Register.................................................................................................................................................570

22 TMS320F2837xD Dual-Core Real-Time Microcontrollers SPRUHM8K – DECEMBER 2013 – REVISED MAY 2024
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Figure 3-307. UID_PSRAND0 Register...................................................................................................................................572

Figure 3-308. UID_PSRAND1 Register...................................................................................................................................573
Figure 3-309. UID_PSRAND2 Register...................................................................................................................................574
Figure 3-310. UID_PSRAND3 Register...................................................................................................................................575
Figure 3-311. UID_PSRAND4 Register................................................................................................................................... 576
Figure 3-312. UID_PSRAND5 Register...................................................................................................................................577
Figure 3-313. UID_UNIQUE Register......................................................................................................................................578
Figure 3-314. UID_CHECKSUM Register............................................................................................................................... 579
Figure 3-315. Z1OTP_LINKPOINTER1 Register.................................................................................................................... 581
Figure 3-316. Z1OTP_LINKPOINTER2 Register.................................................................................................................... 582
Figure 3-317. Z1OTP_LINKPOINTER3 Register.................................................................................................................... 583
Figure 3-318. Z1OTP_PSWDLOCK Register..........................................................................................................................584
Figure 3-319. Z1OTP_CRCLOCK Register.............................................................................................................................585
Figure 3-320. Z1OTP_JTAGLOCK Register............................................................................................................................586
Figure 3-321. Z1OTP_BOOTCTRL Register...........................................................................................................................587
Figure 3-322. Z2OTP_LINKPOINTER1 Register.................................................................................................................... 589
Figure 3-323. Z2OTP_LINKPOINTER2 Register.................................................................................................................... 590
Figure 3-324. Z2OTP_LINKPOINTER3 Register.................................................................................................................... 591
Figure 3-325. Z2OTP_PSWDLOCK Register..........................................................................................................................592
Figure 3-326. Z2OTP_CRCLOCK Register.............................................................................................................................593
Figure 3-327. Z2OTP_JTAGLOCK Register............................................................................................................................594
Figure 3-328. Z2OTP_BOOTCTRL Register...........................................................................................................................595
Figure 4-1. Z1 and Z2 BOOTCTRL Selection..........................................................................................................................618
Figure 4-2. CPU1 Device Boot Flow........................................................................................................................................621
Figure 4-3. CPU2 Device Boot Flow........................................................................................................................................622
Figure 4-4. CPU1 Emulation Boot Flow...................................................................................................................................623
Figure 4-5. CPU2 Emulation Boot Flow...................................................................................................................................624
Figure 4-6. CPU1 Standalone and Hibernate Boot Flow......................................................................................................... 625
Figure 4-7. CPU2 Standalone and Hibernate Boot Flow......................................................................................................... 626
Figure 4-8. Overview of SCI Bootloader Operation................................................................................................................. 634
Figure 4-9. Overview of SCI Boot Function............................................................................................................................. 635
Figure 4-10. SPI Loader.......................................................................................................................................................... 636
Figure 4-11. Data Transfer From EEPROM Flow.................................................................................................................... 637
Figure 4-12. EEPROM Device at Address 0x50......................................................................................................................638
Figure 4-13. Overview of I2C Boot Function............................................................................................................................639
Figure 4-14. Random Read..................................................................................................................................................... 640
Figure 4-15. Sequential Read..................................................................................................................................................640
Figure 4-16. Overview of Parallel GPIO Bootloader Operation............................................................................................... 641
Figure 4-17. Parallel GPIO Bootloader Handshake Protocol...................................................................................................642
Figure 4-18. Parallel GPIO Mode Overview............................................................................................................................ 642
Figure 4-19. Parallel GPIO Mode - Host Transfer Flow........................................................................................................... 643
Figure 4-20. 8-Bit Parallel GetWord Function.......................................................................................................................... 644
Figure 4-21. Overview of CAN-A Bootloader Operation.......................................................................................................... 645
Figure 4-22. USB Boot Flow.................................................................................................................................................... 647
Figure 5-1. DMA Block Diagram.............................................................................................................................................. 665
Figure 5-2. Common Peripheral Architecture.......................................................................................................................... 666
Figure 5-3. DMA Trigger Architecture...................................................................................................................................... 668
Figure 5-4. Peripheral Interrupt Trigger Input Diagram............................................................................................................669
Figure 5-5. DMA State Diagram.............................................................................................................................................. 676
Figure 5-6. 3-Stage Pipeline DMA Transfer.............................................................................................................................677
Figure 5-7. 3-stage Pipeline with One Read Stall....................................................................................................................677
Figure 5-8. Overrun Detection Logic........................................................................................................................................680
Figure 5-9. DMACTRL Register...............................................................................................................................................684
Figure 5-10. DEBUGCTRL Register........................................................................................................................................685
Figure 5-11. PRIORITYCTRL1 Register.................................................................................................................................. 686
Figure 5-12. PRIORITYSTAT Register.................................................................................................................................... 687
Figure 5-13. MODE Register................................................................................................................................................... 689
Figure 5-14. CONTROL Register............................................................................................................................................ 691
Figure 5-15. BURST_SIZE Register........................................................................................................................................693
Figure 5-16. BURST_COUNT Register................................................................................................................................... 694
Figure 5-17. SRC_BURST_STEP Register.............................................................................................................................695

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Figure 5-18. DST_BURST_STEP Register............................................................................................................................. 696

Figure 5-19. TRANSFER_SIZE Register.................................................................................................................................697
Figure 5-20. TRANSFER_COUNT Register............................................................................................................................698
Figure 5-21. SRC_TRANSFER_STEP Register......................................................................................................................699
Figure 5-22. DST_TRANSFER_STEP Register...................................................................................................................... 700
Figure 5-23. SRC_WRAP_SIZE Register................................................................................................................................701
Figure 5-24. SRC_WRAP_COUNT Register...........................................................................................................................702
Figure 5-25. SRC_WRAP_STEP Register.............................................................................................................................. 703
Figure 5-26. DST_WRAP_SIZE Register................................................................................................................................ 704
Figure 5-27. DST_WRAP_COUNT Register........................................................................................................................... 705
Figure 5-28. DST_WRAP_STEP Register...............................................................................................................................706
Figure 5-29. SRC_BEG_ADDR_SHADOW Register.............................................................................................................. 707
Figure 5-30. SRC_ADDR_SHADOW Register........................................................................................................................ 708
Figure 5-31. SRC_BEG_ADDR_ACTIVE Register..................................................................................................................709
Figure 5-32. SRC_ADDR_ACTIVE Register........................................................................................................................... 710
Figure 5-33. DST_BEG_ADDR_SHADOW Register............................................................................................................... 711
Figure 5-34. DST_ADDR_SHADOW Register........................................................................................................................ 712
Figure 5-35. DST_BEG_ADDR_ACTIVE Register.................................................................................................................. 713
Figure 5-36. DST_ADDR_ACTIVE Register............................................................................................................................714
Figure 6-1. CLA Block Diagram............................................................................................................................................... 719
Figure 6-2. MVECT1 Register................................................................................................................................................. 873
Figure 6-3. MVECT2 Register................................................................................................................................................. 874
Figure 6-4. MVECT3 Register................................................................................................................................................. 875
Figure 6-5. MVECT4 Register................................................................................................................................................. 876
Figure 6-6. MVECT5 Register................................................................................................................................................. 877
Figure 6-7. MVECT6 Register................................................................................................................................................. 878
Figure 6-8. MVECT7 Register................................................................................................................................................. 879
Figure 6-9. MVECT8 Register................................................................................................................................................. 880
Figure 6-10. MCTL Register.................................................................................................................................................... 881
Figure 6-11. MIFR Register......................................................................................................................................................882
Figure 6-12. MIOVF Register...................................................................................................................................................886
Figure 6-13. MIFRC Register...................................................................................................................................................889
Figure 6-14. MICLR Register...................................................................................................................................................891
Figure 6-15. MICLROVF Register........................................................................................................................................... 893
Figure 6-16. MIER Register..................................................................................................................................................... 895
Figure 6-17. MIRUN Register.................................................................................................................................................. 898
Figure 6-18. _MPC Register.................................................................................................................................................... 900
Figure 6-19. _MAR0 Register.................................................................................................................................................. 901
Figure 6-20. _MAR1 Register.................................................................................................................................................. 902
Figure 6-21. _MSTF Register.................................................................................................................................................. 903
Figure 6-22. _MR0 Register.................................................................................................................................................... 906
Figure 6-23. _MR1 Register.................................................................................................................................................... 907
Figure 6-24. _MR2 Register.................................................................................................................................................... 908
Figure 6-25. _MR3 Register.................................................................................................................................................... 909
Figure 6-26. SOFTINTEN Register.......................................................................................................................................... 911
Figure 6-27. SOFTINTFRC Register....................................................................................................................................... 913
Figure 7-1. IPC Module Architecture....................................................................................................................................... 917
Figure 7-2. IPCACK Register...................................................................................................................................................922
Figure 7-3. IPCSTS Register................................................................................................................................................... 925
Figure 7-4. IPCSET Register................................................................................................................................................... 929
Figure 7-5. IPCCLR Register...................................................................................................................................................932
Figure 7-6. IPCFLG Register................................................................................................................................................... 937
Figure 7-7. IPCCOUNTERL Register...................................................................................................................................... 941
Figure 7-8. IPCCOUNTERH Register......................................................................................................................................942
Figure 7-9. IPCSENDCOM Register........................................................................................................................................943
Figure 7-10. IPCSENDADDR Register....................................................................................................................................944
Figure 7-11. IPCSENDDATA Register..................................................................................................................................... 945
Figure 7-12. IPCREMOTEREPLY Register............................................................................................................................. 946
Figure 7-13. IPCRECVCOM Register......................................................................................................................................947
Figure 7-14. IPCRECVADDR Register.................................................................................................................................... 948
Figure 7-15. IPCRECVDATA Register..................................................................................................................................... 949

24 TMS320F2837xD Dual-Core Real-Time Microcontrollers SPRUHM8K – DECEMBER 2013 – REVISED MAY 2024
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Figure 7-16. IPCLOCALREPLY Register.................................................................................................................................950

Figure 7-17. IPCBOOTSTS Register.......................................................................................................................................951
Figure 7-18. IPCBOOTMODE Register................................................................................................................................... 952
Figure 7-19. IPCACK Register.................................................................................................................................................954
Figure 7-20. IPCSTS Register................................................................................................................................................. 957
Figure 7-21. IPCSET Register................................................................................................................................................. 961
Figure 7-22. IPCCLR Register.................................................................................................................................................964
Figure 7-23. IPCFLG Register................................................................................................................................................. 969
Figure 7-24. IPCCOUNTERL Register.................................................................................................................................... 973
Figure 7-25. IPCCOUNTERH Register....................................................................................................................................974
Figure 7-26. IPCRECVCOM Register......................................................................................................................................975
Figure 7-27. IPCRECVADDR Register.................................................................................................................................... 976
Figure 7-28. IPCRECVDATA Register..................................................................................................................................... 977
Figure 7-29. IPCLOCALREPLY Register.................................................................................................................................978
Figure 7-30. IPCSENDCOM Register......................................................................................................................................979
Figure 7-31. IPCSENDADDR Register....................................................................................................................................980
Figure 7-32. IPCSENDDATA Register..................................................................................................................................... 981
Figure 7-33. IPCREMOTEREPLY Register............................................................................................................................. 982
Figure 7-34. IPCBOOTSTS Register.......................................................................................................................................983
Figure 7-35. IPCBOOTMODE Register................................................................................................................................... 984
Figure 8-1. GPIO Logic for a Single Pin.................................................................................................................................. 988
Figure 8-2. Input Qualification Using a Sampling Window.......................................................................................................992
Figure 8-3. Input Qualifier Clock Cycles.................................................................................................................................. 994
Figure 8-4. GPACTRL Register..............................................................................................................................................1011
Figure 8-5. GPAQSEL1 Register........................................................................................................................................... 1012
Figure 8-6. GPAQSEL2 Register........................................................................................................................................... 1014
Figure 8-7. GPAMUX1 Register.............................................................................................................................................1016
Figure 8-8. GPAMUX2 Register.............................................................................................................................................1018
Figure 8-9. GPADIR Register.................................................................................................................................................1020
Figure 8-10. GPAPUD Register............................................................................................................................................. 1022
Figure 8-11. GPAINV Register............................................................................................................................................... 1024
Figure 8-12. GPAODR Register.............................................................................................................................................1026
Figure 8-13. GPAGMUX1 Register........................................................................................................................................ 1028
Figure 8-14. GPAGMUX2 Register........................................................................................................................................ 1029
Figure 8-15. GPACSEL1 Register......................................................................................................................................... 1030
Figure 8-16. GPACSEL2 Register......................................................................................................................................... 1031
Figure 8-17. GPACSEL3 Register......................................................................................................................................... 1032
Figure 8-18. GPACSEL4 Register......................................................................................................................................... 1033
Figure 8-19. GPALOCK Register........................................................................................................................................... 1034
Figure 8-20. GPACR Register................................................................................................................................................1036
Figure 8-21. GPBCTRL Register........................................................................................................................................... 1038
Figure 8-22. GPBQSEL1 Register.........................................................................................................................................1039
Figure 8-23. GPBQSEL2 Register.........................................................................................................................................1041
Figure 8-24. GPBMUX1 Register.......................................................................................................................................... 1043
Figure 8-25. GPBMUX2 Register.......................................................................................................................................... 1045
Figure 8-26. GPBDIR Register.............................................................................................................................................. 1047
Figure 8-27. GPBPUD Register.............................................................................................................................................1049
Figure 8-28. GPBINV Register.............................................................................................................................................. 1051
Figure 8-29. GPBODR Register............................................................................................................................................ 1053
Figure 8-30. GPBAMSEL Register........................................................................................................................................ 1055
Figure 8-31. GPBGMUX1 Register........................................................................................................................................1057
Figure 8-32. GPBGMUX2 Register........................................................................................................................................1058
Figure 8-33. GPBCSEL1 Register......................................................................................................................................... 1059
Figure 8-34. GPBCSEL2 Register......................................................................................................................................... 1060
Figure 8-35. GPBCSEL3 Register......................................................................................................................................... 1061
Figure 8-36. GPBCSEL4 Register......................................................................................................................................... 1062
Figure 8-37. GPBLOCK Register...........................................................................................................................................1063
Figure 8-38. GPBCR Register............................................................................................................................................... 1065
Figure 8-39. GPCCTRL Register...........................................................................................................................................1067
Figure 8-40. GPCQSEL1 Register.........................................................................................................................................1068
Figure 8-41. GPCQSEL2 Register.........................................................................................................................................1070

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Figure 8-42. GPCMUX1 Register.......................................................................................................................................... 1072

Figure 8-43. GPCMUX2 Register.......................................................................................................................................... 1074
Figure 8-44. GPCDIR Register.............................................................................................................................................. 1076
Figure 8-45. GPCPUD Register.............................................................................................................................................1078
Figure 8-46. GPCINV Register.............................................................................................................................................. 1080
Figure 8-47. GPCODR Register............................................................................................................................................ 1082
Figure 8-48. GPCGMUX1 Register....................................................................................................................................... 1084
Figure 8-49. GPCGMUX2 Register....................................................................................................................................... 1085
Figure 8-50. GPCCSEL1 Register.........................................................................................................................................1086
Figure 8-51. GPCCSEL2 Register.........................................................................................................................................1087
Figure 8-52. GPCCSEL3 Register.........................................................................................................................................1088
Figure 8-53. GPCCSEL4 Register.........................................................................................................................................1089
Figure 8-54. GPCLOCK Register.......................................................................................................................................... 1090
Figure 8-55. GPCCR Register............................................................................................................................................... 1092
Figure 8-56. GPDCTRL Register...........................................................................................................................................1094
Figure 8-57. GPDQSEL1 Register.........................................................................................................................................1095
Figure 8-58. GPDQSEL2 Register.........................................................................................................................................1097
Figure 8-59. GPDMUX1 Register.......................................................................................................................................... 1099
Figure 8-60. GPDMUX2 Register...........................................................................................................................................1101
Figure 8-61. GPDDIR Register.............................................................................................................................................. 1103
Figure 8-62. GPDPUD Register............................................................................................................................................. 1105
Figure 8-63. GPDINV Register...............................................................................................................................................1107
Figure 8-64. GPDODR Register.............................................................................................................................................1109
Figure 8-65. GPDGMUX1 Register........................................................................................................................................ 1111
Figure 8-66. GPDGMUX2 Register........................................................................................................................................ 1113
Figure 8-67. GPDCSEL1 Register......................................................................................................................................... 1115
Figure 8-68. GPDCSEL2 Register......................................................................................................................................... 1116
Figure 8-69. GPDCSEL3 Register......................................................................................................................................... 1117
Figure 8-70. GPDCSEL4 Register......................................................................................................................................... 1118
Figure 8-71. GPDLOCK Register........................................................................................................................................... 1119
Figure 8-72. GPDCR Register............................................................................................................................................... 1121
Figure 8-73. GPECTRL Register........................................................................................................................................... 1123
Figure 8-74. GPEQSEL1 Register......................................................................................................................................... 1124
Figure 8-75. GPEQSEL2 Register......................................................................................................................................... 1126
Figure 8-76. GPEMUX1 Register...........................................................................................................................................1128
Figure 8-77. GPEMUX2 Register...........................................................................................................................................1130
Figure 8-78. GPEDIR Register...............................................................................................................................................1132
Figure 8-79. GPEPUD Register............................................................................................................................................. 1134
Figure 8-80. GPEINV Register...............................................................................................................................................1136
Figure 8-81. GPEODR Register.............................................................................................................................................1138
Figure 8-82. GPEGMUX1 Register........................................................................................................................................ 1140
Figure 8-83. GPEGMUX2 Register........................................................................................................................................ 1142
Figure 8-84. GPECSEL1 Register......................................................................................................................................... 1144
Figure 8-85. GPECSEL2 Register......................................................................................................................................... 1145
Figure 8-86. GPECSEL3 Register......................................................................................................................................... 1146
Figure 8-87. GPECSEL4 Register......................................................................................................................................... 1147
Figure 8-88. GPELOCK Register........................................................................................................................................... 1148
Figure 8-89. GPECR Register................................................................................................................................................1150
Figure 8-90. GPFCTRL Register............................................................................................................................................1152
Figure 8-91. GPFQSEL1 Register......................................................................................................................................... 1153
Figure 8-92. GPFMUX1 Register........................................................................................................................................... 1155
Figure 8-93. GPFDIR Register...............................................................................................................................................1157
Figure 8-94. GPFPUD Register............................................................................................................................................. 1159
Figure 8-95. GPFINV Register............................................................................................................................................... 1161
Figure 8-96. GPFODR Register............................................................................................................................................. 1163
Figure 8-97. GPFGMUX1 Register........................................................................................................................................ 1165
Figure 8-98. GPFCSEL1 Register..........................................................................................................................................1167
Figure 8-99. GPFCSEL2 Register..........................................................................................................................................1168
Figure 8-100. GPFLOCK Register......................................................................................................................................... 1169
Figure 8-101. GPFCR Register..............................................................................................................................................1171
Figure 8-102. GPADAT Register............................................................................................................................................ 1175

26 TMS320F2837xD Dual-Core Real-Time Microcontrollers SPRUHM8K – DECEMBER 2013 – REVISED MAY 2024
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Figure 8-103. GPASET Register............................................................................................................................................ 1177

Figure 8-104. GPACLEAR Register....................................................................................................................................... 1179
Figure 8-105. GPATOGGLE Register.................................................................................................................................... 1181
Figure 8-106. GPBDAT Register............................................................................................................................................1183
Figure 8-107. GPBSET Register............................................................................................................................................1185
Figure 8-108. GPBCLEAR Register.......................................................................................................................................1187
Figure 8-109. GPBTOGGLE Register....................................................................................................................................1189
Figure 8-110. GPCDAT Register............................................................................................................................................1191
Figure 8-111. GPCSET Register............................................................................................................................................ 1193
Figure 8-112. GPCCLEAR Register.......................................................................................................................................1195
Figure 8-113. GPCTOGGLE Register....................................................................................................................................1197
Figure 8-114. GPDDAT Register............................................................................................................................................1199
Figure 8-115. GPDSET Register............................................................................................................................................1201
Figure 8-116. GPDCLEAR Register.......................................................................................................................................1203
Figure 8-117. GPDTOGGLE Register....................................................................................................................................1205
Figure 8-118. GPEDAT Register............................................................................................................................................1207
Figure 8-119. GPESET Register............................................................................................................................................1209
Figure 8-120. GPECLEAR Register.......................................................................................................................................1211
Figure 8-121. GPETOGGLE Register....................................................................................................................................1213
Figure 8-122. GPFDAT Register............................................................................................................................................1215
Figure 8-123. GPFSET Register............................................................................................................................................1217
Figure 8-124. GPFCLEAR Register.......................................................................................................................................1219
Figure 8-125. GPFTOGGLE Register....................................................................................................................................1221
Figure 9-1. Input X-BAR........................................................................................................................................................ 1231
Figure 9-2. ePWM X-BAR Architecture - Single Output........................................................................................................ 1233
Figure 9-3. CLB X-BAR Architecture - Single Output............................................................................................................ 1235
Figure 9-4. GPIO to CLB Tile Connections............................................................................................................................1236
Figure 9-5. GPIO Output X-BAR Architecture....................................................................................................................... 1238
Figure 9-6. X-BAR Input Sources.......................................................................................................................................... 1240
Figure 9-7. INPUT1SELECT Register................................................................................................................................... 1243
Figure 9-8. INPUT2SELECT Register................................................................................................................................... 1244
Figure 9-9. INPUT3SELECT Register................................................................................................................................... 1245
Figure 9-10. INPUT4SELECT Register................................................................................................................................. 1246
Figure 9-11. INPUT5SELECT Register..................................................................................................................................1247
Figure 9-12. INPUT6SELECT Register................................................................................................................................. 1248
Figure 9-13. INPUT7SELECT Register................................................................................................................................. 1249
Figure 9-14. INPUT8SELECT Register................................................................................................................................. 1250
Figure 9-15. INPUT9SELECT Register................................................................................................................................. 1251
Figure 9-16. INPUT10SELECT Register............................................................................................................................... 1252
Figure 9-17. INPUT11SELECT Register................................................................................................................................1253
Figure 9-18. INPUT12SELECT Register............................................................................................................................... 1254
Figure 9-19. INPUT13SELECT Register............................................................................................................................... 1255
Figure 9-20. INPUT14SELECT Register............................................................................................................................... 1256
Figure 9-21. INPUTSELECTLOCK Register......................................................................................................................... 1257
Figure 9-22. XBARFLG1 Register......................................................................................................................................... 1260
Figure 9-23. XBARFLG2 Register......................................................................................................................................... 1262
Figure 9-24. XBARFLG3 Register......................................................................................................................................... 1264
Figure 9-25. XBARCLR1 Register......................................................................................................................................... 1266
Figure 9-26. XBARCLR2 Register......................................................................................................................................... 1268
Figure 9-27. XBARCLR3 Register......................................................................................................................................... 1270
Figure 9-28. TRIP4MUX0TO15CFG Register....................................................................................................................... 1274
Figure 9-29. TRIP4MUX16TO31CFG Register..................................................................................................................... 1277
Figure 9-30. TRIP5MUX0TO15CFG Register....................................................................................................................... 1280
Figure 9-31. TRIP5MUX16TO31CFG Register..................................................................................................................... 1283
Figure 9-32. TRIP7MUX0TO15CFG Register....................................................................................................................... 1286
Figure 9-33. TRIP7MUX16TO31CFG Register..................................................................................................................... 1289
Figure 9-34. TRIP8MUX0TO15CFG Register....................................................................................................................... 1292
Figure 9-35. TRIP8MUX16TO31CFG Register..................................................................................................................... 1295
Figure 9-36. TRIP9MUX0TO15CFG Register....................................................................................................................... 1298
Figure 9-37. TRIP9MUX16TO31CFG Register..................................................................................................................... 1301
Figure 9-38. TRIP10MUX0TO15CFG Register..................................................................................................................... 1304

SPRUHM8K – DECEMBER 2013 – REVISED MAY 2024 TMS320F2837xD Dual-Core Real-Time Microcontrollers 27
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Figure 9-39. TRIP10MUX16TO31CFG Register................................................................................................................... 1307

Figure 9-40. TRIP11MUX0TO15CFG Register......................................................................................................................1310
Figure 9-41. TRIP11MUX16TO31CFG Register....................................................................................................................1313
Figure 9-42. TRIP12MUX0TO15CFG Register..................................................................................................................... 1316
Figure 9-43. TRIP12MUX16TO31CFG Register................................................................................................................... 1319
Figure 9-44. TRIP4MUXENABLE Register............................................................................................................................1322
Figure 9-45. TRIP5MUXENABLE Register............................................................................................................................1327
Figure 9-46. TRIP7MUXENABLE Register............................................................................................................................1332
Figure 9-47. TRIP8MUXENABLE Register............................................................................................................................1337
Figure 9-48. TRIP9MUXENABLE Register............................................................................................................................1342
Figure 9-49. TRIP10MUXENABLE Register..........................................................................................................................1347
Figure 9-50. TRIP11MUXENABLE Register.......................................................................................................................... 1352
Figure 9-51. TRIP12MUXENABLE Register..........................................................................................................................1357
Figure 9-52. TRIPOUTINV Register...................................................................................................................................... 1362
Figure 9-53. TRIPLOCK Register.......................................................................................................................................... 1364
Figure 9-54. AUXSIG0MUX0TO15CFG Register.................................................................................................................. 1367
Figure 9-55. AUXSIG0MUX16TO31CFG Register................................................................................................................ 1370
Figure 9-56. AUXSIG1MUX0TO15CFG Register.................................................................................................................. 1373
Figure 9-57. AUXSIG1MUX16TO31CFG Register................................................................................................................ 1376
Figure 9-58. AUXSIG2MUX0TO15CFG Register.................................................................................................................. 1379
Figure 9-59. AUXSIG2MUX16TO31CFG Register................................................................................................................ 1382
Figure 9-60. AUXSIG3MUX0TO15CFG Register.................................................................................................................. 1385
Figure 9-61. AUXSIG3MUX16TO31CFG Register................................................................................................................ 1388
Figure 9-62. AUXSIG4MUX0TO15CFG Register.................................................................................................................. 1391
Figure 9-63. AUXSIG4MUX16TO31CFG Register................................................................................................................ 1394
Figure 9-64. AUXSIG5MUX0TO15CFG Register.................................................................................................................. 1397
Figure 9-65. AUXSIG5MUX16TO31CFG Register................................................................................................................ 1400
Figure 9-66. AUXSIG6MUX0TO15CFG Register.................................................................................................................. 1403
Figure 9-67. AUXSIG6MUX16TO31CFG Register................................................................................................................ 1406
Figure 9-68. AUXSIG7MUX0TO15CFG Register.................................................................................................................. 1409
Figure 9-69. AUXSIG7MUX16TO31CFG Register................................................................................................................ 1412
Figure 9-70. AUXSIG0MUXENABLE Register...................................................................................................................... 1415
Figure 9-71. AUXSIG1MUXENABLE Register...................................................................................................................... 1420
Figure 9-72. AUXSIG2MUXENABLE Register...................................................................................................................... 1425
Figure 9-73. AUXSIG3MUXENABLE Register...................................................................................................................... 1430
Figure 9-74. AUXSIG4MUXENABLE Register...................................................................................................................... 1435
Figure 9-75. AUXSIG5MUXENABLE Register...................................................................................................................... 1440
Figure 9-76. AUXSIG6MUXENABLE Register...................................................................................................................... 1445
Figure 9-77. AUXSIG7MUXENABLE Register...................................................................................................................... 1450
Figure 9-78. AUXSIGOUTINV Register.................................................................................................................................1455
Figure 9-79. AUXSIGLOCK Register.....................................................................................................................................1457
Figure 9-80. OUTPUT1MUX0TO15CFG Register.................................................................................................................1460
Figure 9-81. OUTPUT1MUX16TO31CFG Register...............................................................................................................1463
Figure 9-82. OUTPUT2MUX0TO15CFG Register.................................................................................................................1466
Figure 9-83. OUTPUT2MUX16TO31CFG Register...............................................................................................................1469
Figure 9-84. OUTPUT3MUX0TO15CFG Register.................................................................................................................1472
Figure 9-85. OUTPUT3MUX16TO31CFG Register...............................................................................................................1475
Figure 9-86. OUTPUT4MUX0TO15CFG Register.................................................................................................................1478
Figure 9-87. OUTPUT4MUX16TO31CFG Register...............................................................................................................1481
Figure 9-88. OUTPUT5MUX0TO15CFG Register.................................................................................................................1484
Figure 9-89. OUTPUT5MUX16TO31CFG Register...............................................................................................................1487
Figure 9-90. OUTPUT6MUX0TO15CFG Register.................................................................................................................1490
Figure 9-91. OUTPUT6MUX16TO31CFG Register...............................................................................................................1493
Figure 9-92. OUTPUT7MUX0TO15CFG Register.................................................................................................................1496
Figure 9-93. OUTPUT7MUX16TO31CFG Register...............................................................................................................1499
Figure 9-94. OUTPUT8MUX0TO15CFG Register.................................................................................................................1502
Figure 9-95. OUTPUT8MUX16TO31CFG Register...............................................................................................................1505
Figure 9-96. OUTPUT1MUXENABLE Register..................................................................................................................... 1508
Figure 9-97. OUTPUT2MUXENABLE Register..................................................................................................................... 1513
Figure 9-98. OUTPUT3MUXENABLE Register..................................................................................................................... 1518
Figure 9-99. OUTPUT4MUXENABLE Register..................................................................................................................... 1523

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Figure 9-100. OUTPUT5MUXENABLE Register................................................................................................................... 1528

Figure 9-101. OUTPUT6MUXENABLE Register................................................................................................................... 1533
Figure 9-102. OUTPUT7MUXENABLE Register................................................................................................................... 1538
Figure 9-103. OUTPUT8MUXENABLE Register................................................................................................................... 1543
Figure 9-104. OUTPUTLATCH Register................................................................................................................................1548
Figure 9-105. OUTPUTLATCHCLR Register.........................................................................................................................1550
Figure 9-106. OUTPUTLATCHFRC Register........................................................................................................................ 1552
Figure 9-107. OUTPUTLATCHENABLE Register..................................................................................................................1554
Figure 9-108. OUTPUTINV Register..................................................................................................................................... 1556
Figure 9-109. OUTPUTLOCK Register................................................................................................................................. 1558
Figure 10-1. Analog Subsystem Block Diagram (337-Ball ZWT)...........................................................................................1567
Figure 10-2. Analog Subsystem Block Diagram (176-Pin PTP)............................................................................................ 1568
Figure 10-3. Analog Subsystem Block Diagram (100-Pin PZP)............................................................................................ 1569
Figure 10-4. INTOSC1TRIM Register....................................................................................................................................1573
Figure 10-5. INTOSC2TRIM Register....................................................................................................................................1574
Figure 10-6. TSNSCTL Register............................................................................................................................................1575
Figure 10-7. LOCK Register.................................................................................................................................................. 1576
Figure 10-8. ANAREFTRIMA Register.................................................................................................................................. 1578
Figure 10-9. ANAREFTRIMB Register.................................................................................................................................. 1579
Figure 10-10. ANAREFTRIMC Register................................................................................................................................ 1580
Figure 10-11. ANAREFTRIMD Register................................................................................................................................ 1581
Figure 11-1. ADC Module Block Diagram.............................................................................................................................. 1585
Figure 11-2. SOC Block Diagram...........................................................................................................................................1590
Figure 11-3. Single-Ended Input Model................................................................................................................................. 1592
Figure 11-4. Differential Input Model......................................................................................................................................1592
Figure 11-5. Round Robin Priority Example...........................................................................................................................1597
Figure 11-6. High Priority Example........................................................................................................................................ 1598
Figure 11-7. Burst Priority Example....................................................................................................................................... 1600
Figure 11-8. ADC EOC Interrupts.......................................................................................................................................... 1601
Figure 11-9. ADC PPB Block Diagram...................................................................................................................................1603
Figure 11-10. ADC PPB Interrupt Event................................................................................................................................ 1605
Figure 11-11. Opens/Shorts Detection Circuit........................................................................................................................1607
Figure 11-12. Input Circuit Equivalent with OSDETECT Enabled..........................................................................................1608
Figure 11-13. ADC Timings for 12-bit Mode in Early Interrupt Mode..................................................................................... 1613
Figure 11-14. ADC Timings for 12-bit Mode in Late Interrupt Mode...................................................................................... 1614
Figure 11-15. ADC Timings for 16-bit Mode in Early Interrupt Mode..................................................................................... 1615
Figure 11-16. ADC Timings for 16-bit Mode in Late Interrupt Mode (SYSCLK Cycles).........................................................1616
Figure 11-17. Example: Basic Synchronous Operation......................................................................................................... 1618
Figure 11-18. Example: Synchronous Operation with Multiple Trigger Sources....................................................................1619
Figure 11-19. Example: Synchronous Operation with Uneven SOC Numbers......................................................................1620
Figure 11-20. Example: Asynchronous Operation with Uneven SOC Numbers – Trigger Overflow..................................... 1620
Figure 11-21. Example: Asynchronous Operation with Different Resolutions....................................................................... 1621
Figure 11-22. Example: Synchronous Operation with Different Resolutions......................................................................... 1621
Figure 11-23. Example: Synchronous Equivalent Operation with Non-Overlapping Conversions.........................................1622
Figure 11-24. ADC Reference System...................................................................................................................................1625
Figure 11-25. ADC Shared Reference System...................................................................................................................... 1626
Figure 11-26. ADCRESULT0 Register...................................................................................................................................1632
Figure 11-27. ADCRESULT1 Register...................................................................................................................................1633
Figure 11-28. ADCRESULT2 Register...................................................................................................................................1634
Figure 11-29. ADCRESULT3 Register...................................................................................................................................1635
Figure 11-30. ADCRESULT4 Register...................................................................................................................................1636
Figure 11-31. ADCRESULT5 Register...................................................................................................................................1637
Figure 11-32. ADCRESULT6 Register...................................................................................................................................1638
Figure 11-33. ADCRESULT7 Register...................................................................................................................................1639
Figure 11-34. ADCRESULT8 Register...................................................................................................................................1640
Figure 11-35. ADCRESULT9 Register...................................................................................................................................1641
Figure 11-36. ADCRESULT10 Register.................................................................................................................................1642
Figure 11-37. ADCRESULT11 Register................................................................................................................................. 1643
Figure 11-38. ADCRESULT12 Register.................................................................................................................................1644
Figure 11-39. ADCRESULT13 Register.................................................................................................................................1645
Figure 11-40. ADCRESULT14 Register.................................................................................................................................1646

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Figure 11-41. ADCRESULT15 Register.................................................................................................................................1647

Figure 11-42. ADCPPB1RESULT Register............................................................................................................................1648
Figure 11-43. ADCPPB2RESULT Register............................................................................................................................1649
Figure 11-44. ADCPPB3RESULT Register............................................................................................................................1650
Figure 11-45. ADCPPB4RESULT Register............................................................................................................................1651
Figure 11-46. ADCCTL1 Register.......................................................................................................................................... 1655
Figure 11-47. ADCCTL2 Register.......................................................................................................................................... 1657
Figure 11-48. ADCBURSTCTL Register................................................................................................................................1658
Figure 11-49. ADCINTFLG Register...................................................................................................................................... 1660
Figure 11-50. ADCINTFLGCLR Register...............................................................................................................................1662
Figure 11-51. ADCINTOVF Register......................................................................................................................................1663
Figure 11-52. ADCINTOVFCLR Register.............................................................................................................................. 1664
Figure 11-53. ADCINTSEL1N2 Register................................................................................................................................1665
Figure 11-54. ADCINTSEL3N4 Register................................................................................................................................1667
Figure 11-55. ADCSOCPRICTL Register.............................................................................................................................. 1669
Figure 11-56. ADCINTSOCSEL1 Register............................................................................................................................ 1671
Figure 11-57. ADCINTSOCSEL2 Register............................................................................................................................ 1673
Figure 11-58. ADCSOCFLG1 Register.................................................................................................................................. 1675
Figure 11-59. ADCSOCFRC1 Register..................................................................................................................................1679
Figure 11-60. ADCSOCOVF1 Register..................................................................................................................................1684
Figure 11-61. ADCSOCOVFCLR1 Register.......................................................................................................................... 1687
Figure 11-62. ADCSOC0CTL Register.................................................................................................................................. 1690
Figure 11-63. ADCSOC1CTL Register.................................................................................................................................. 1693
Figure 11-64. ADCSOC2CTL Register.................................................................................................................................. 1696
Figure 11-65. ADCSOC3CTL Register.................................................................................................................................. 1699
Figure 11-66. ADCSOC4CTL Register.................................................................................................................................. 1702
Figure 11-67. ADCSOC5CTL Register.................................................................................................................................. 1705
Figure 11-68. ADCSOC6CTL Register.................................................................................................................................. 1708
Figure 11-69. ADCSOC7CTL Register.................................................................................................................................. 1711
Figure 11-70. ADCSOC8CTL Register.................................................................................................................................. 1714
Figure 11-71. ADCSOC9CTL Register.................................................................................................................................. 1717
Figure 11-72. ADCSOC10CTL Register................................................................................................................................ 1720
Figure 11-73. ADCSOC11CTL Register................................................................................................................................ 1723
Figure 11-74. ADCSOC12CTL Register................................................................................................................................ 1726
Figure 11-75. ADCSOC13CTL Register................................................................................................................................ 1729
Figure 11-76. ADCSOC14CTL Register................................................................................................................................ 1732
Figure 11-77. ADCSOC15CTL Register................................................................................................................................ 1735
Figure 11-78. ADCEVTSTAT Register................................................................................................................................... 1738
Figure 11-79. ADCEVTCLR Register.....................................................................................................................................1741
Figure 11-80. ADCEVTSEL Register..................................................................................................................................... 1743
Figure 11-81. ADCEVTINTSEL Register............................................................................................................................... 1745
Figure 11-82. ADCOSDETECT Register............................................................................................................................... 1747
Figure 11-83. ADCCOUNTER Register................................................................................................................................. 1748
Figure 11-84. ADCREV Register........................................................................................................................................... 1749
Figure 11-85. ADCOFFTRIM Register...................................................................................................................................1750
Figure 11-86. ADCPPB1CONFIG Register............................................................................................................................1751
Figure 11-87. ADCPPB1STAMP Register............................................................................................................................. 1753
Figure 11-88. ADCPPB1OFFCAL Register........................................................................................................................... 1754
Figure 11-89. ADCPPB1OFFREF Register........................................................................................................................... 1755
Figure 11-90. ADCPPB1TRIPHI Register..............................................................................................................................1756
Figure 11-91. ADCPPB1TRIPLO Register.............................................................................................................................1757
Figure 11-92. ADCPPB2CONFIG Register............................................................................................................................1758
Figure 11-93. ADCPPB2STAMP Register............................................................................................................................. 1760
Figure 11-94. ADCPPB2OFFCAL Register........................................................................................................................... 1761
Figure 11-95. ADCPPB2OFFREF Register........................................................................................................................... 1762
Figure 11-96. ADCPPB2TRIPHI Register..............................................................................................................................1763
Figure 11-97. ADCPPB2TRIPLO Register.............................................................................................................................1764
Figure 11-98. ADCPPB3CONFIG Register............................................................................................................................1765
Figure 11-99. ADCPPB3STAMP Register............................................................................................................................. 1767
Figure 11-100. ADCPPB3OFFCAL Register......................................................................................................................... 1768
Figure 11-101. ADCPPB3OFFREF Register......................................................................................................................... 1769

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Figure 11-102. ADCPPB3TRIPHI Register............................................................................................................................1770

Figure 11-103. ADCPPB3TRIPLO Register...........................................................................................................................1771
Figure 11-104. ADCPPB4CONFIG Register..........................................................................................................................1772
Figure 11-105. ADCPPB4STAMP Register........................................................................................................................... 1774
Figure 11-106. ADCPPB4OFFCAL Register......................................................................................................................... 1775
Figure 11-107. ADCPPB4OFFREF Register......................................................................................................................... 1776
Figure 11-108. ADCPPB4TRIPHI Register............................................................................................................................1777
Figure 11-109. ADCPPB4TRIPLO Register...........................................................................................................................1778
Figure 11-110. ADCINLTRIM1 Register.................................................................................................................................1779
Figure 11-111. ADCINLTRIM2 Register................................................................................................................................. 1780
Figure 11-112. ADCINLTRIM3 Register.................................................................................................................................1781
Figure 11-113. ADCINLTRIM4 Register.................................................................................................................................1782
Figure 11-114. ADCINLTRIM5 Register.................................................................................................................................1783
Figure 11-115. ADCINLTRIM6 Register.................................................................................................................................1784
Figure 12-1. DAC Module Block Diagram..............................................................................................................................1791
Figure 12-2. DACREV Register............................................................................................................................................. 1795
Figure 12-3. DACCTL Register..............................................................................................................................................1796
Figure 12-4. DACVALA Register............................................................................................................................................1797
Figure 12-5. DACVALS Register............................................................................................................................................1798
Figure 12-6. DACOUTEN Register........................................................................................................................................1799
Figure 12-7. DACLOCK Register...........................................................................................................................................1800
Figure 12-8. DACTRIM Register............................................................................................................................................1801
Figure 13-1. CMPSS Module Block Diagram........................................................................................................................ 1805
Figure 13-2. Comparator Block Diagram............................................................................................................................... 1805
Figure 13-3. Reference DAC Block Diagram.........................................................................................................................1806
Figure 13-4. Ramp Generator Block Diagram....................................................................................................................... 1808
Figure 13-5. Ramp Generator Behavior................................................................................................................................ 1809
Figure 13-6. Digital Filter Behavior........................................................................................................................................ 1810
Figure 13-7. COMPCTL Register.......................................................................................................................................... 1817
Figure 13-8. COMPHYSCTL Register................................................................................................................................... 1819
Figure 13-9. COMPSTS Register.......................................................................................................................................... 1820
Figure 13-10. COMPSTSCLR Register................................................................................................................................. 1821
Figure 13-11. COMPDACCTL Register................................................................................................................................. 1822
Figure 13-12. DACHVALS Register....................................................................................................................................... 1823
Figure 13-13. DACHVALA Register....................................................................................................................................... 1824
Figure 13-14. RAMPMAXREFA Register.............................................................................................................................. 1825
Figure 13-15. RAMPMAXREFS Register.............................................................................................................................. 1826
Figure 13-16. RAMPDECVALA Register............................................................................................................................... 1827
Figure 13-17. RAMPDECVALS Register............................................................................................................................... 1828
Figure 13-18. RAMPSTS Register.........................................................................................................................................1829
Figure 13-19. DACLVALS Register........................................................................................................................................1830
Figure 13-20. DACLVALA Register........................................................................................................................................1831
Figure 13-21. RAMPDLYA Register.......................................................................................................................................1832
Figure 13-22. RAMPDLYS Register.......................................................................................................................................1833
Figure 13-23. CTRIPLFILCTL Register................................................................................................................................. 1834
Figure 13-24. CTRIPLFILCLKCTL Register.......................................................................................................................... 1835
Figure 13-25. CTRIPHFILCTL Register.................................................................................................................................1836
Figure 13-26. CTRIPHFILCLKCTL Register..........................................................................................................................1837
Figure 13-27. COMPLOCK Register..................................................................................................................................... 1838
Figure 14-1. Sigma Delta Filter Module (SDFM) CPU Interface............................................................................................1842
Figure 14-2. Sigma Delta Filter Module (SDFM) Block Diagram........................................................................................... 1844
Figure 14-3. Block Diagram of One Filter Module................................................................................................................. 1845
Figure 14-4. Different Modulator Modes Supported...............................................................................................................1848
Figure 14-5. Simplified Sinc Filter Architecture......................................................................................................................1849
Figure 14-6. Z-Transform of Sinc Filter of Order N................................................................................................................ 1849
Figure 14-7. Frequency Response of Different Sinc Filters................................................................................................... 1849
Figure 14-8. SDSYNC Event................................................................................................................................................. 1853
Figure 14-9. Comparator Unit Structure................................................................................................................................ 1854
Figure 14-10. SDFM Error (SD_ERR) Interrupt Sources.......................................................................................................1858
Figure 14-11. SDIFLG Register............................................................................................................................................. 1865
Figure 14-12. SDIFLGCLR Register......................................................................................................................................1867

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Figure 14-13. SDCTL Register.............................................................................................................................................. 1869

Figure 14-14. SDMFILEN Register........................................................................................................................................1870
Figure 14-15. SDCTLPARM1 Register.................................................................................................................................. 1871
Figure 14-16. SDDFPARM1 Register.................................................................................................................................... 1872
Figure 14-17. SDDPARM1 Register...................................................................................................................................... 1873
Figure 14-18. SDCMPH1 Register........................................................................................................................................ 1874
Figure 14-19. SDCMPL1 Register......................................................................................................................................... 1875
Figure 14-20. SDCPARM1 Register...................................................................................................................................... 1876
Figure 14-21. SDDATA1 Register.......................................................................................................................................... 1877
Figure 14-22. SDCTLPARM2 Register.................................................................................................................................. 1878
Figure 14-23. SDDFPARM2 Register.................................................................................................................................... 1879
Figure 14-24. SDDPARM2 Register...................................................................................................................................... 1880
Figure 14-25. SDCMPH2 Register........................................................................................................................................ 1881
Figure 14-26. SDCMPL2 Register......................................................................................................................................... 1882
Figure 14-27. SDCPARM2 Register...................................................................................................................................... 1883
Figure 14-28. SDDATA2 Register.......................................................................................................................................... 1884
Figure 14-29. SDCTLPARM3 Register.................................................................................................................................. 1885
Figure 14-30. SDDFPARM3 Register.................................................................................................................................... 1886
Figure 14-31. SDDPARM3 Register...................................................................................................................................... 1887
Figure 14-32. SDCMPH3 Register........................................................................................................................................ 1888
Figure 14-33. SDCMPL3 Register......................................................................................................................................... 1889
Figure 14-34. SDCPARM3 Register...................................................................................................................................... 1890
Figure 14-35. SDDATA3 Register.......................................................................................................................................... 1891
Figure 14-36. SDCTLPARM4 Register.................................................................................................................................. 1892
Figure 14-37. SDDFPARM4 Register.................................................................................................................................... 1893
Figure 14-38. SDDPARM4 Register...................................................................................................................................... 1894
Figure 14-39. SDCMPH4 Register........................................................................................................................................ 1895
Figure 14-40. SDCMPL4 Register......................................................................................................................................... 1896
Figure 14-41. SDCPARM4 Register...................................................................................................................................... 1897
Figure 14-42. SDDATA4 Register.......................................................................................................................................... 1898
Figure 15-1. Multiple ePWM Modules....................................................................................................................................1905
Figure 15-2. Submodules and Signal Connections for an ePWM Module.............................................................................1906
Figure 15-3. ePWM Modules and Critical Internal Signal Interconnects............................................................................... 1908
Figure 15-4. Time-Base Submodule...................................................................................................................................... 1911
Figure 15-5. Time-Base Submodule Signals and Registers.................................................................................................. 1912
Figure 15-6. Time-Base Frequency and Period.....................................................................................................................1914
Figure 15-7. Time-Base Counter Synchronization Scheme...................................................................................................1916
Figure 15-8. Time-Base Up-Count Mode Waveforms............................................................................................................1918
Figure 15-9. Time-Base Down-Count Mode Waveforms....................................................................................................... 1919
Figure 15-10. Time-Base Up-Down-Count Waveforms, TBCTL[PHSDIR = 0] Count Down On Synchronization Event.......1920
Figure 15-11. Time-Base Up-Down Count Waveforms, TBCTL[PHSDIR = 1] Count Up On Synchronization Event............ 1921
Figure 15-12. Global Load: Signals and Registers................................................................................................................ 1922
Figure 15-13. One-Shot Sync Mode...................................................................................................................................... 1923
Figure 15-14. Counter-Compare Submodule........................................................................................................................ 1924
Figure 15-15. Detailed View of the Counter-Compare Submodule........................................................................................1925
Figure 15-16. Counter-Compare Event Waveforms in Up-Count Mode................................................................................ 1928
Figure 15-17. Counter-Compare Events in Down-Count Mode.............................................................................................1928
Figure 15-18. Counter-Compare Events In Up-Down-Count Mode, TBCTL[PHSDIR = 0] Count Down On
Synchronization Event....................................................................................................................................................... 1929
Figure 15-19. Counter-Compare Events In Up-Down-Count Mode, TBCTL[PHSDIR = 1] Count Up On Synchronization
Event.................................................................................................................................................................................. 1929
Figure 15-20. Action-Qualifier Submodule.............................................................................................................................1930
Figure 15-21. Action-Qualifier Submodule Inputs and Outputs............................................................................................. 1931
Figure 15-22. Possible Action-Qualifier Actions for EPWMxA and EPWMxB Outputs..........................................................1932
Figure 15-23. AQCTL[SHDWAQAMODE]............................................................................................................................. 1935
Figure 15-24. AQCTL[SHDWAQBMODE]............................................................................................................................. 1935
Figure 15-25. Up-Down Count Mode Symmetrical Waveform...............................................................................................1937
Figure 15-26. Up, Single Edge Asymmetric Waveform, with Independent Modulation on EPWMxA and EPWMxB—
Active High......................................................................................................................................................................... 1938
Figure 15-27. Up, Single Edge Asymmetric Waveform with Independent Modulation on EPWMxA and EPWMxB—
Active Low..........................................................................................................................................................................1939

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Figure 15-28. Up-Count, Pulse Placement Asymmetric Waveform With Independent Modulation on EPWMxA..................1940
Figure 15-29. Up-Down Count, Dual-Edge Symmetric Waveform, with Independent Modulation on EPWMxA and
EPWMxB — Active Low.....................................................................................................................................................1940
Figure 15-30. Up-Down Count, Dual-Edge Symmetric Waveform, with Independent Modulation on EPWMxA and
EPWMxB — Complementary.............................................................................................................................................1941
Figure 15-31. Up-Down Count, Dual-Edge Asymmetric Waveform, with Independent Modulation on EPWMxA—Active
Low.....................................................................................................................................................................................1941
Figure 15-32. Up-Down Count, PWM Waveform Generation Utilizing T1 and T2 Events..................................................... 1942
Figure 15-33. Dead_Band Submodule.................................................................................................................................. 1943
Figure 15-34. Configuration Options for the Dead-Band Submodule.................................................................................... 1946
Figure 15-35. Dead-Band Waveforms for Typical Cases (0% < Duty < 100%)..................................................................... 1948
Figure 15-36. PWM Chopper Submodule..............................................................................................................................1950
Figure 15-37. PWM Chopper Submodule Operational Details.............................................................................................. 1951
Figure 15-38. Simple PWM Chopper Submodule Waveforms Showing Chopping Action Only............................................ 1951
Figure 15-39. PWM Chopper Submodule Waveforms Showing the First Pulse and Subsequent Sustaining Pulses........... 1952
Figure 15-40. PWM Chopper Submodule Waveforms Showing the Pulse Width (Duty Cycle) Control of Sustaining Pulses 1953
Figure 15-41. Trip-Zone Submodule......................................................................................................................................1954
Figure 15-42. Trip-Zone Submodule Mode Control Logic......................................................................................................1958
Figure 15-43. Trip-Zone Submodule Interrupt Logic..............................................................................................................1959
Figure 15-44. Event-Trigger Submodule................................................................................................................................1960
Figure 15-45. Event-Trigger Submodule Showing Event Inputs and Prescaled Outputs...................................................... 1961
Figure 15-46. Event-Trigger Interrupt Generator................................................................................................................... 1963
Figure 15-47. Event-Trigger SOCA Pulse Generator............................................................................................................ 1964
Figure 15-48. Event-Trigger SOCB Pulse Generator............................................................................................................ 1964
Figure 15-49. Digital-Compare Submodule High-Level Block Diagram.................................................................................1965
Figure 15-50. GPIO MUX-to-Trip Input Connectivity............................................................................................................. 1966
Figure 15-51. DCAEVT1 Event Triggering.............................................................................................................................1969
Figure 15-52. DCAEVT2 Event Triggering.............................................................................................................................1969
Figure 15-53. DCBEVT1 Event Triggering.............................................................................................................................1970
Figure 15-54. DCBEVT2 Event Triggering.............................................................................................................................1970
Figure 15-55. Event Filtering................................................................................................................................................. 1971
Figure 15-56. Blanking Window Timing Diagram...................................................................................................................1972
Figure 15-57. Valley Switching...............................................................................................................................................1974
Figure 15-58. ePWM X-BAR..................................................................................................................................................1975
Figure 15-59. Simplified ePWM Module................................................................................................................................ 1976
Figure 15-60. EPWM1 Configured as a Typical Master, EPWM2 Configured as a Slave .................................................... 1977
Figure 15-61. Control of Four Buck Stages. Here FPWM1≠ FPWM2≠ FPWM3≠ FPWM4 ............................................................. 1978
Figure 15-62. Buck Waveforms for Control of Four Buck Stages (Note: Only three bucks shown here).............................. 1979
Figure 15-63. Control of Four Buck Stages. (Note: FPWM2 = N x FPWM1).............................................................................. 1980
Figure 15-64. Buck Waveforms for Control of Four Buck Stages (Note: FPWM2 = FPWM1).................................................... 1981
Figure 15-65. Control of Two Half-H Bridge Stages (FPWM2 = N x FPWM1)............................................................................ 1982
Figure 15-66. Half-H Bridge Waveforms for Control of Two Half-H Bridge Stages (Note: Here FPWM2 = FPWM1)................. 1983
Figure 15-67. Control of Dual 3-Phase Inverter Stages as Is Commonly Used in Motor Control..........................................1984
Figure 15-68. 3-Phase Inverter Waveforms for Control of Dual 3-Phase Inverter Stages (Only One Inverter Shown)......... 1985
Figure 15-69. Configuring Two PWM Modules for Phase Control......................................................................................... 1986
Figure 15-70. Timing Waveforms Associated with Phase Control Between Two Modules....................................................1987
Figure 15-71. Control of 3-Phase Interleaved DC/DC Converter.......................................................................................... 1988
Figure 15-72. 3-Phase Interleaved DC/DC Converter Waveforms for Control of 3-Phase Interleaved DC/DC Converter....1989
Figure 15-73. Control of Full-H Bridge Stage (FPWM2 = FPWM1)............................................................................................ 1990
Figure 15-74. ZVS Full-H Bridge Waveforms........................................................................................................................ 1991
Figure 15-75. Peak Current Mode Control of Buck Converter...............................................................................................1992
Figure 15-76. Peak Current Mode Control Waveforms for Control of Buck Converter.......................................................... 1992
Figure 15-77. Control of Two Resonant Converter Stages....................................................................................................1993
Figure 15-78. H-Bridge LLC Resonant Converter PWM Waveforms.....................................................................................1993
Figure 15-79. HRPWM Block Diagram.................................................................................................................................. 1994
Figure 15-80. Resolution Calculations for Conventionally Generated PWM......................................................................... 1995
Figure 15-81. Operating Logic Using MEP............................................................................................................................ 1996
Figure 15-82. HRPWM Extension Registers and Memory Configuration.............................................................................. 1997
Figure 15-83. HRPWM System Interface.............................................................................................................................. 1998
Figure 15-84. HRPWM and HRCAL Source Clock................................................................................................................1999
Figure 15-85. Required PWM Waveform for a Requested Duty = 40.5%..............................................................................2002

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Figure 15-86. Low % Duty Cycle Range Limitation Example (HRPCTL[HRPE] = 0)............................................................ 2005
Figure 15-87. High % Duty Cycle Range Limitation Example (HRPCTL[HRPE] = 0)............................................................2006
Figure 15-88. Up-Count Duty Cycle Range Limitation Example (HRPCTL[HRPE] = 1)........................................................2006
Figure 15-89. Up-Down Count Duty Cycle Range Limitation Example (HRPCTL[HRPE] = 1)..............................................2006
Figure 15-90. Simple Buck Controlled Converter Using a Single PWM................................................................................ 2013
Figure 15-91. PWM Waveform Generated for Simple Buck Controlled Converter................................................................ 2013
Figure 15-92. Simple Reconstruction Filter for a PWM-based DAC......................................................................................2015
Figure 15-93. PWM Waveform Generated for the PWM DAC Function................................................................................ 2015
Figure 15-94. TBCTL Register...............................................................................................................................................2024
Figure 15-95. TBCTL2 Register.............................................................................................................................................2026
Figure 15-96. TBCTR Register.............................................................................................................................................. 2027
Figure 15-97. TBSTS Register.............................................................................................................................................. 2028
Figure 15-98. CMPCTL Register........................................................................................................................................... 2029
Figure 15-99. CMPCTL2 Register......................................................................................................................................... 2031
Figure 15-100. DBCTL Register............................................................................................................................................ 2033
Figure 15-101. DBCTL2 Register.......................................................................................................................................... 2036
Figure 15-102. AQCTL Register............................................................................................................................................ 2037
Figure 15-103. AQTSRCSEL Register.................................................................................................................................. 2039
Figure 15-104. PCCTL Register............................................................................................................................................ 2040
Figure 15-105. VCAPCTL Register....................................................................................................................................... 2042
Figure 15-106. VCNTCFG Register.......................................................................................................................................2044
Figure 15-107. HRCNFG Register.........................................................................................................................................2046
Figure 15-108. HRPWR Register.......................................................................................................................................... 2048
Figure 15-109. HRMSTEP Register...................................................................................................................................... 2049
Figure 15-110. HRCNFG2 Register....................................................................................................................................... 2050
Figure 15-111. HRPCTL Register.......................................................................................................................................... 2051
Figure 15-112. TRREM Register............................................................................................................................................2053
Figure 15-113. GLDCTL Register.......................................................................................................................................... 2054
Figure 15-114. GLDCFG Register......................................................................................................................................... 2056
Figure 15-115. EPWMXLINK Register...................................................................................................................................2058
Figure 15-116. AQCTLA Register.......................................................................................................................................... 2060
Figure 15-117. AQCTLA2 Register........................................................................................................................................ 2062
Figure 15-118. AQCTLB Register.......................................................................................................................................... 2063
Figure 15-119. AQCTLB2 Register........................................................................................................................................ 2065
Figure 15-120. AQSFRC Register......................................................................................................................................... 2066
Figure 15-121. AQCSFRC Register...................................................................................................................................... 2067
Figure 15-122. DBREDHR Register...................................................................................................................................... 2068
Figure 15-123. DBRED Register........................................................................................................................................... 2069
Figure 15-124. DBFEDHR Register.......................................................................................................................................2070
Figure 15-125. DBFED Register............................................................................................................................................2071
Figure 15-126. TBPHS Register............................................................................................................................................ 2072
Figure 15-127. TBPRDHR Register.......................................................................................................................................2073
Figure 15-128. TBPRD Register............................................................................................................................................2074
Figure 15-129. CMPA Register.............................................................................................................................................. 2075
Figure 15-130. CMPB Register..............................................................................................................................................2076
Figure 15-131. CMPC Register............................................................................................................................................. 2077
Figure 15-132. CMPD Register............................................................................................................................................. 2078
Figure 15-133. GLDCTL2 Register........................................................................................................................................2079
Figure 15-134. SWVDELVAL Register...................................................................................................................................2080
Figure 15-135. TZSEL Register.............................................................................................................................................2081
Figure 15-136. TZDCSEL Register........................................................................................................................................2083
Figure 15-137. TZCTL Register.............................................................................................................................................2084
Figure 15-138. TZCTL2 Register...........................................................................................................................................2086
Figure 15-139. TZCTLDCA Register..................................................................................................................................... 2088
Figure 15-140. TZCTLDCB Register..................................................................................................................................... 2090
Figure 15-141. TZEINT Register........................................................................................................................................... 2092
Figure 15-142. TZFLG Register.............................................................................................................................................2093
Figure 15-143. TZCBCFLG Register..................................................................................................................................... 2095
Figure 15-144. TZOSTFLG Register..................................................................................................................................... 2097
Figure 15-145. TZCLR Register............................................................................................................................................ 2099
Figure 15-146. TZCBCCLR Register.....................................................................................................................................2101

34 TMS320F2837xD Dual-Core Real-Time Microcontrollers SPRUHM8K – DECEMBER 2013 – REVISED MAY 2024
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Figure 15-147. TZOSTCLR Register..................................................................................................................................... 2102

Figure 15-148. TZFRC Register............................................................................................................................................ 2103
Figure 15-149. ETSEL Register.............................................................................................................................................2104
Figure 15-150. ETPS Register...............................................................................................................................................2107
Figure 15-151. ETFLG Register.............................................................................................................................................2110
Figure 15-152. ETCLR Register.............................................................................................................................................2111
Figure 15-153. ETFRC Register............................................................................................................................................ 2112
Figure 15-154. ETINTPS Register......................................................................................................................................... 2113
Figure 15-155. ETSOCPS Register....................................................................................................................................... 2114
Figure 15-156. ETCNTINITCTL Register...............................................................................................................................2116
Figure 15-157. ETCNTINIT Register......................................................................................................................................2117
Figure 15-158. DCTRIPSEL Register.................................................................................................................................... 2118
Figure 15-159. DCACTL Register..........................................................................................................................................2120
Figure 15-160. DCBCTL Register..........................................................................................................................................2121
Figure 15-161. DCFCTL Register..........................................................................................................................................2122
Figure 15-162. DCCAPCTL Register.....................................................................................................................................2124
Figure 15-163. DCFOFFSET Register.................................................................................................................................. 2126
Figure 15-164. DCFOFFSETCNT Register........................................................................................................................... 2127
Figure 15-165. DCFWINDOW Register.................................................................................................................................2128
Figure 15-166. DCFWINDOWCNT Register..........................................................................................................................2129
Figure 15-167. DCCAP Register........................................................................................................................................... 2130
Figure 15-168. DCAHTRIPSEL Register...............................................................................................................................2131
Figure 15-169. DCALTRIPSEL Register................................................................................................................................2133
Figure 15-170. DCBHTRIPSEL Register...............................................................................................................................2135
Figure 15-171. DCBLTRIPSEL Register................................................................................................................................2137
Figure 15-172. HWVDELVAL Register.................................................................................................................................. 2139
Figure 15-173. VCNTVAL Register........................................................................................................................................2140
Figure 16-1. Capture and APWM Modes of Operation..........................................................................................................2156
Figure 16-2. Counter Compare and PRD Effects on the eCAP Output in APWM Mode....................................................... 2157
Figure 16-3. eCAP Block Diagram.........................................................................................................................................2158
Figure 16-4. Event Prescale Control......................................................................................................................................2159
Figure 16-5. Prescale Function Waveforms...........................................................................................................................2159
Figure 16-6. Details of the Continuous/One-shot Block.........................................................................................................2160
Figure 16-7. Details of the Counter and Synchronization Block............................................................................................ 2162
Figure 16-8. Time-Base Counter Synchronization Scheme...................................................................................................2163
Figure 16-9. Interrupts in eCAP Module................................................................................................................................ 2164
Figure 16-10. PWM Waveform Details Of APWM Mode Operation.......................................................................................2165
Figure 16-11. Time-Base Frequency and Period Calculation................................................................................................ 2166
Figure 16-12. Capture Sequence for Absolute Time-stamp and Rising-Edge Detect........................................................... 2167
Figure 16-13. Capture Sequence for Absolute Time-stamp with Rising- and Falling-Edge Detect....................................... 2168
Figure 16-14. Capture Sequence for Delta Mode Time-stamp and Rising Edge Detect....................................................... 2169
Figure 16-15. Capture Sequence for Delta Mode Time-stamp with Rising- and Falling-Edge Detect...................................2170
Figure 16-16. PWM Waveform Details of APWM Mode Operation....................................................................................... 2171
Figure 16-17. TSCTR Register.............................................................................................................................................. 2175
Figure 16-18. CTRPHS Register........................................................................................................................................... 2176
Figure 16-19. CAP1 Register.................................................................................................................................................2177
Figure 16-20. CAP2 Register.................................................................................................................................................2178
Figure 16-21. CAP3 Register.................................................................................................................................................2179
Figure 16-22. CAP4 Register.................................................................................................................................................2180
Figure 16-23. ECCTL1 Register............................................................................................................................................ 2181
Figure 16-24. ECCTL2 Register............................................................................................................................................ 2183
Figure 16-25. ECEINT Register.............................................................................................................................................2185
Figure 16-26. ECFLG Register.............................................................................................................................................. 2187
Figure 16-27. ECCLR Register..............................................................................................................................................2188
Figure 16-28. ECFRC Register..............................................................................................................................................2189
Figure 17-1. Optical Encoder Disk.........................................................................................................................................2193
Figure 17-2. QEP Encoder Output Signal for Forward/Reverse Movement.......................................................................... 2193
Figure 17-3. Index Pulse Example.........................................................................................................................................2194
Figure 17-4. Functional Block Diagram of the eQEP Peripheral........................................................................................... 2197
Figure 17-5. Functional Block Diagram of Decoder Unit....................................................................................................... 2199
Figure 17-6. Quadrature Decoder State Machine..................................................................................................................2200

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Figure 17-7. Quadrature-clock and Direction Decoding........................................................................................................ 2201

Figure 17-8. Position Counter Reset by Index Pulse for 1000-Line Encoder (QPOSMAX = 3999 or 0xF9F)....................... 2203
Figure 17-9. Position Counter Underflow/Overflow (QPOSMAX = 4)....................................................................................2204
Figure 17-10. Software Index Marker for 1000-line Encoder (QEPCTL[IEL] = 1)..................................................................2206
Figure 17-11. Strobe Event Latch (QEPCTL[SEL] = 1)......................................................................................................... 2206
Figure 17-12. eQEP Position-compare Unit.......................................................................................................................... 2208
Figure 17-13. eQEP Position-compare Event Generation Points..........................................................................................2209
Figure 17-14. eQEP Position-compare Sync Output Pulse Stretcher................................................................................... 2209
Figure 17-15. eQEP Edge Capture Unit.................................................................................................................................2211
Figure 17-16. Unit Position Event for Low Speed Measurement (QCAPCTL[UPPS] = 0010)...............................................2212
Figure 17-17. eQEP Edge Capture Unit - Timing Details...................................................................................................... 2212
Figure 17-18. eQEP Watchdog Timer....................................................................................................................................2214
Figure 17-19. eQEP Unit Timer Base.................................................................................................................................... 2214
Figure 17-20. eQEP Interrupt Generation..............................................................................................................................2215
Figure 17-21. QPOSCNT Register........................................................................................................................................ 2217
Figure 17-22. QPOSINIT Register.........................................................................................................................................2218
Figure 17-23. QPOSMAX Register........................................................................................................................................2219
Figure 17-24. QPOSCMP Register........................................................................................................................................2220
Figure 17-25. QPOSILAT Register........................................................................................................................................ 2221
Figure 17-26. QPOSSLAT Register....................................................................................................................................... 2222
Figure 17-27. QPOSLAT Register......................................................................................................................................... 2223
Figure 17-28. QUTMR Register.............................................................................................................................................2224
Figure 17-29. QUPRD Register............................................................................................................................................. 2225
Figure 17-30. QWDTMR Register......................................................................................................................................... 2226
Figure 17-31. QWDPRD Register..........................................................................................................................................2227
Figure 17-32. QDECCTL Register.........................................................................................................................................2228
Figure 17-33. QEPCTL Register............................................................................................................................................2230
Figure 17-34. QCAPCTL Register......................................................................................................................................... 2232
Figure 17-35. QPOSCTL Register.........................................................................................................................................2233
Figure 17-36. QEINT Register............................................................................................................................................... 2234
Figure 17-37. QFLG Register................................................................................................................................................ 2236
Figure 17-38. QCLR Register................................................................................................................................................ 2238
Figure 17-39. QFRC Register................................................................................................................................................2240
Figure 17-40. QEPSTS Register........................................................................................................................................... 2242
Figure 17-41. QCTMR Register.............................................................................................................................................2244
Figure 17-42. QCPRD Register............................................................................................................................................. 2245
Figure 17-43. QCTMRLAT Register.......................................................................................................................................2246
Figure 17-44. QCPRDLAT Register.......................................................................................................................................2247
Figure 18-1. SPI CPU Interface............................................................................................................................................. 2252
Figure 18-2. SPI Interrupt Flags and Enable Logic Generation.............................................................................................2255
Figure 18-3. SPI DMA Trigger Diagram.................................................................................................................................2256
Figure 18-4. SPI Master/Slave Connection........................................................................................................................... 2257
Figure 18-5. SPI Module Master Configuration..................................................................................................................... 2259
Figure 18-6. SPI Module Slave Configuration....................................................................................................................... 2260
Figure 18-7. SPICLK Signal Options..................................................................................................................................... 2263
Figure 18-8. SPI: SPICLK-LSPCLK Characteristic when (BRR + 1) is Odd, BRR > 3, and CLKPOLARITY = 1.................. 2264
Figure 18-9. SPI 3-wire Master Mode....................................................................................................................................2266
Figure 18-10. SPI 3-wire Slave Mode....................................................................................................................................2267
Figure 18-11. Five Bits per Character.................................................................................................................................... 2270
Figure 18-12. SPI Digital Audio Receiver Configuration Using Two SPIs............................................................................. 2273
Figure 18-13. Standard Right-Justified Digital Audio Data Format........................................................................................2273
Figure 18-14. SPICCR Register............................................................................................................................................ 2279
Figure 18-15. SPICTL Register............................................................................................................................................. 2281
Figure 18-16. SPISTS Register............................................................................................................................................. 2283
Figure 18-17. SPIBRR Register.............................................................................................................................................2285
Figure 18-18. SPIRXEMU Register....................................................................................................................................... 2286
Figure 18-19. SPIRXBUF Register........................................................................................................................................ 2287
Figure 18-20. SPITXBUF Register........................................................................................................................................ 2288
Figure 18-21. SPIDAT Register............................................................................................................................................. 2289
Figure 18-22. SPIFFTX Register........................................................................................................................................... 2290
Figure 18-23. SPIFFRX Register...........................................................................................................................................2292

36 TMS320F2837xD Dual-Core Real-Time Microcontrollers SPRUHM8K – DECEMBER 2013 – REVISED MAY 2024
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Figure 18-24. SPIFFCT Register........................................................................................................................................... 2294

Figure 18-25. SPIPRI Register.............................................................................................................................................. 2295
Figure 19-1. SCI CPU Interface.............................................................................................................................................2299
Figure 19-2. Serial Communications Interface (SCI) Module Block Diagram........................................................................2301
Figure 19-3. Typical SCI Data Frame Formats...................................................................................................................... 2303
Figure 19-4. Idle-Line Multiprocessor Communication Format..............................................................................................2305
Figure 19-5. Double-Buffered WUT and TXSHF................................................................................................................... 2306
Figure 19-6. Address-Bit Multiprocessor Communication Format......................................................................................... 2307
Figure 19-7. SCI Asynchronous Communications Format.................................................................................................... 2308
Figure 19-8. SCI RX Signals in Communication Modes........................................................................................................ 2309
Figure 19-9. SCI TX Signals in Communications Mode........................................................................................................ 2310
Figure 19-10. SCI FIFO Interrupt Flags and Enable Logic.................................................................................................... 2314
Figure 19-11. SCICCR Register.............................................................................................................................................2318
Figure 19-12. SCICTL1 Register........................................................................................................................................... 2320
Figure 19-13. SCIHBAUD Register....................................................................................................................................... 2322
Figure 19-14. SCILBAUD Register........................................................................................................................................ 2323
Figure 19-15. SCICTL2 Register........................................................................................................................................... 2324
Figure 19-16. SCIRXST Register.......................................................................................................................................... 2326
Figure 19-17. SCIRXEMU Register....................................................................................................................................... 2329
Figure 19-18. SCIRXBUF Register........................................................................................................................................2330
Figure 19-19. SCITXBUF Register........................................................................................................................................ 2332
Figure 19-20. SCIFFTX Register........................................................................................................................................... 2333
Figure 19-21. SCIFFRX Register...........................................................................................................................................2335
Figure 19-22. SCIFFCT Register...........................................................................................................................................2337
Figure 19-23. SCIPRI Register.............................................................................................................................................. 2338
Figure 20-1. Multiple I2C Modules Connected...................................................................................................................... 2342
Figure 20-2. I2C Module Conceptual Block Diagram............................................................................................................ 2345
Figure 20-3. Clocking Diagram for the I2C Module............................................................................................................... 2345
Figure 20-4. Roles of the Clock Divide-Down Values (ICCL and ICCH)................................................................................2346
Figure 20-5. Bit Transfer on the I2C bus................................................................................................................................2347
Figure 20-6. I2C Slave TX / RX Flowchart.............................................................................................................................2349
Figure 20-7. I2C Master TX / RX Flowchart...........................................................................................................................2350
Figure 20-8. I2C Module START and STOP Conditions........................................................................................................2351
Figure 20-9. I2C Module Data Transfer (7-Bit Addressing with 8-bit Data Configuration Shown)......................................... 2352
Figure 20-10. I2C Module 7-Bit Addressing Format (FDF = 0, XA = 0 in I2CMDR).............................................................. 2353
Figure 20-11. I2C Module 10-Bit Addressing Format (FDF = 0, XA = 1 in I2CMDR).............................................................2353
Figure 20-12. I2C Module Free Data Format (FDF = 1 in I2CMDR)......................................................................................2354
Figure 20-13. Repeated START Condition (in This Case, 7-Bit Addressing Format)............................................................ 2354
Figure 20-14. Synchronization of Two I2C Clock Generators During Arbitration...................................................................2355
Figure 20-15. Arbitration Procedure Between Two Master-Transmitters...............................................................................2356
Figure 20-16. Pin Diagram Showing the Effects of the Digital Loopback Mode (DLB) Bit.....................................................2357
Figure 20-17. Enable Paths of the I2C Interrupt Requests....................................................................................................2360
Figure 20-18. Backwards Compatibility Mode and Forward Compatibility Bit, Slave Transmitter......................................... 2361
Figure 20-19. I2C FIFO Interrupt........................................................................................................................................... 2362
Figure 20-20. I2COAR Register.............................................................................................................................................2367
Figure 20-21. I2CIER Register.............................................................................................................................................. 2368
Figure 20-22. I2CSTR Register............................................................................................................................................. 2369
Figure 20-23. I2CCLKL Register........................................................................................................................................... 2373
Figure 20-24. I2CCLKH Register...........................................................................................................................................2374
Figure 20-25. I2CCNT Register............................................................................................................................................. 2375
Figure 20-26. I2CDRR Register.............................................................................................................................................2376
Figure 20-27. I2CSAR Register............................................................................................................................................. 2377
Figure 20-28. I2CDXR Register.............................................................................................................................................2378
Figure 20-29. I2CMDR Register............................................................................................................................................ 2379
Figure 20-30. I2CISRC Register............................................................................................................................................2383
Figure 20-31. I2CEMDR Register..........................................................................................................................................2384
Figure 20-32. I2CPSC Register............................................................................................................................................. 2385
Figure 20-33. I2CFFTX Register........................................................................................................................................... 2386
Figure 20-34. I2CFFRX Register........................................................................................................................................... 2388
Figure 21-1. Conceptual Block Diagram of the McBSP.........................................................................................................2394
Figure 21-2. McBSP Data Transfer Paths............................................................................................................................. 2395

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Figure 21-3. Companding Processes.................................................................................................................................... 2396

Figure 21-4. μ-Law Transmit Data Companding Format....................................................................................................... 2396
Figure 21-5. A-Law Transmit Data Companding Format....................................................................................................... 2396
Figure 21-6. Two Methods by Which the McBSP Can Compand Internal Data.................................................................... 2397
Figure 21-7. Example - Clock Signal Control of Bit Transfer Timing......................................................................................2397
Figure 21-8. McBSP Operating at Maximum Packet Frequency........................................................................................... 2399
Figure 21-9. Single-Phase Frame for a McBSP Data Transfer..............................................................................................2400
Figure 21-10. Dual-Phase Frame for a McBSP Data Transfer.............................................................................................. 2400
Figure 21-11. Implementing the AC97 Standard With a Dual-Phase Frame......................................................................... 2401
Figure 21-12. Timing of an AC97-Standard Data Transfer Near Frame Synchronization..................................................... 2401
Figure 21-13. McBSP Reception Physical Data Path............................................................................................................2402
Figure 21-14. McBSP Reception Signal Activity....................................................................................................................2402
Figure 21-15. McBSP Transmission Physical Data Path.......................................................................................................2403
Figure 21-16. McBSP Transmission Signal Activity...............................................................................................................2403
Figure 21-17. Conceptual Block Diagram of the Sample Rate Generator.............................................................................2405
Figure 21-18. Possible Inputs to the Sample Rate Generator and the Polarity Bits.............................................................. 2407
Figure 21-19. CLKG Synchronization and FSG Generation When GSYNC = 1 and CLKGDV = 1.......................................2409
Figure 21-20. CLKG Synchronization and FSG Generation When GSYNC = 1 and CLKGDV = 3.......................................2410
Figure 21-21. Overrun in the McBSP Receiver..................................................................................................................... 2412
Figure 21-22. Overrun Prevented in the McBSP Receiver.................................................................................................... 2413
Figure 21-23. Possible Responses to Receive Frame-Synchronization Pulses....................................................................2413
Figure 21-24. An Unexpected Frame-Synchronization Pulse During a McBSP Reception...................................................2414
Figure 21-25. Proper Positioning of Frame-Synchronization Pulses..................................................................................... 2415
Figure 21-26. Data in the McBSP Transmitter Overwritten and Thus Not Transmitted......................................................... 2415
Figure 21-27. Underflow During McBSP Transmission......................................................................................................... 2416
Figure 21-28. Underflow Prevented in the McBSP Transmitter............................................................................................. 2417
Figure 21-29. Possible Responses to Transmit Frame-Synchronization Pulses................................................................... 2417
Figure 21-30. An Unexpected Frame-Synchronization Pulse During a McBSP Transmission..............................................2418
Figure 21-31. Proper Positioning of Frame-Synchronization Pulses..................................................................................... 2419
Figure 21-32. Alternating Between the Channels of Partition A and the Channels of Partition B..........................................2422
Figure 21-33. Reassigning Channel Blocks Throughout a McBSP Data Transfer................................................................ 2422
Figure 21-34. McBSP Data Transfer in the 8-Partition Mode................................................................................................ 2423
Figure 21-35. Activity on McBSP Pins for the Possible Values of XMCM..............................................................................2427
Figure 21-36. Typical SPI Interface....................................................................................................................................... 2428
Figure 21-37. SPI Transfer with CLKSTP = 10b (No Clock Delay), CLKXP = 0, and CLKRP = 0.........................................2430
Figure 21-38. SPI Transfer with CLKSTP = 11b (Clock Delay), CLKXP = 0, CLKRP = 1......................................................2430
Figure 21-39. SPI Transfer with CLKSTP = 10b (No Clock Delay), CLKXP = 1, and CLKRP = 0.........................................2431
Figure 21-40. SPI Transfer with CLKSTP = 11b (Clock Delay), CLKXP = 1, CLKRP = 1......................................................2431
Figure 21-41. SPI Interface with McBSP Used as Master .................................................................................................... 2433
Figure 21-42. SPI Interface With McBSP Used as Slave ..................................................................................................... 2434
Figure 21-43. Unexpected Frame-Synchronization Pulse With (R/X)FIG = 0....................................................................... 2442
Figure 21-44. Unexpected Frame-Synchronization Pulse With (R/X)FIG = 1....................................................................... 2442
Figure 21-45. Companding Processes for Reception and for Transmission......................................................................... 2443
Figure 21-46. Range of Programmable Data Delay.............................................................................................................. 2444
Figure 21-47. 2-Bit Data Delay Used to Skip a Framing Bit.................................................................................................. 2445
Figure 21-48. Data Clocked Externally Using a Rising Edge and Sampled by the McBSP Receiver on a Falling Edge...... 2450
Figure 21-49. Frame of Period 16 CLKG Periods and Active Width of 2 CLKG Periods.......................................................2451
Figure 21-50. Data Clocked Externally Using a Rising Edge and Sampled by the McBSP Receiver on a Falling Edge...... 2454
Figure 21-51. Unexpected Frame-Synchronization Pulse With (R/X) FIG = 0...................................................................... 2465
Figure 21-52. Unexpected Frame-Synchronization Pulse With (R/X) FIG = 1...................................................................... 2465
Figure 21-53. Companding Processes for Reception and for Transmission......................................................................... 2466
Figure 21-54. μ-Law Transmit Data Companding Format..................................................................................................... 2467
Figure 21-55. A-Law Transmit Data Companding Format..................................................................................................... 2467
Figure 21-56. Range of Programmable Data Delay.............................................................................................................. 2468
Figure 21-57. 2-Bit Data Delay Used to Skip a Framing Bit.................................................................................................. 2468
Figure 21-58. Data Clocked Externally Using a Rising Edge and Sampled by the McBSP Receiver on a Falling Edge...... 2472
Figure 21-59. Frame of Period 16 CLKG Periods and Active Width of 2 CLKG Periods.......................................................2472
Figure 21-60. Data Clocked Externally Using a Rising Edge and Sampled by the McBSP Receiver on a Falling Edge...... 2474
Figure 21-61. Four 8-Bit Data Words Transferred To/From the McBSP................................................................................ 2478
Figure 21-62. One 32-Bit Data Word Transferred To/From the McBSP................................................................................ 2479
Figure 21-63. 8-Bit Data Words Transferred at Maximum Packet Frequency....................................................................... 2480

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Figure 21-64. Configuring the Data Stream of Figure 21-63 as a Continuous 32-Bit Word...................................................2480
Figure 21-65. Receive Interrupt Generation.......................................................................................................................... 2481
Figure 21-66. Transmit Interrupt Generation......................................................................................................................... 2482
Figure 21-67. DRR2 Register................................................................................................................................................ 2488
Figure 21-68. DRR1 Register................................................................................................................................................ 2489
Figure 21-69. DXR2 Register................................................................................................................................................ 2490
Figure 21-70. DXR1 Register................................................................................................................................................ 2491
Figure 21-71. SPCR2 Register.............................................................................................................................................. 2492
Figure 21-72. SPCR1 Register.............................................................................................................................................. 2495
Figure 21-73. RCR2 Register................................................................................................................................................ 2498
Figure 21-74. RCR1 Register................................................................................................................................................ 2500
Figure 21-75. XCR2 Register................................................................................................................................................ 2501
Figure 21-76. XCR1 Register................................................................................................................................................ 2503
Figure 21-77. SRGR2 Register..............................................................................................................................................2504
Figure 21-78. SRGR1 Register..............................................................................................................................................2506
Figure 21-79. MCR2 Register................................................................................................................................................2507
Figure 21-80. MCR1 Register................................................................................................................................................2509
Figure 21-81. RCERA Register..............................................................................................................................................2511
Figure 21-82. RCERB Register............................................................................................................................................. 2512
Figure 21-83. XCERA Register..............................................................................................................................................2513
Figure 21-84. XCERB Register..............................................................................................................................................2514
Figure 21-85. PCR Register.................................................................................................................................................. 2515
Figure 21-86. RCERC Register............................................................................................................................................. 2518
Figure 21-87. RCERD Register............................................................................................................................................. 2519
Figure 21-88. XCERC Register............................................................................................................................................. 2520
Figure 21-89. XCERD Register............................................................................................................................................. 2521
Figure 21-90. RCERE Register............................................................................................................................................. 2522
Figure 21-91. RCERF Register..............................................................................................................................................2523
Figure 21-92. XCERE Register..............................................................................................................................................2524
Figure 21-93. XCERF Register..............................................................................................................................................2525
Figure 21-94. RCERG Register............................................................................................................................................. 2526
Figure 21-95. RCERH Register............................................................................................................................................. 2527
Figure 21-96. XCERG Register............................................................................................................................................. 2528
Figure 21-97. XCERH Register............................................................................................................................................. 2529
Figure 21-98. MFFINT Register.............................................................................................................................................2530
Figure 22-1. CAN Block Diagram.......................................................................................................................................... 2536
Figure 22-2. Accessing Message Objects Through IFx Registers.........................................................................................2537
Figure 22-3. CAN_MUX.........................................................................................................................................................2542
Figure 22-4. CAN Core in Silent Mode.................................................................................................................................. 2543
Figure 22-5. CAN Core in Loopback Mode............................................................................................................................2544
Figure 22-6. CAN Core in External Loopback Mode............................................................................................................. 2545
Figure 22-7. CAN Core in Loopback Combined with Silent Mode.........................................................................................2546
Figure 22-8. CAN Interrupt Topology 1.................................................................................................................................. 2548
Figure 22-9. CAN Interrupt Topology 2.................................................................................................................................. 2548
Figure 22-10. Initialization of a Transmit Object.................................................................................................................... 2551
Figure 22-11. Initialization of a Single Receive Object for Data Frames................................................................................2551
Figure 22-12. Initialization of a Single Receive Object for Remote Frames.......................................................................... 2552
Figure 22-13. CPU Handling of a FIFO Buffer (Interrupt Driven)...........................................................................................2557
Figure 22-14. Bit Timing.........................................................................................................................................................2558
Figure 22-15. Propagation Time Segment.............................................................................................................................2559
Figure 22-16. Synchronization on Late and Early Edges...................................................................................................... 2561
Figure 22-17. Filtering of Short Dominant Spikes..................................................................................................................2562
Figure 22-18. Structure of the CAN Core's CAN Protocol Controller.....................................................................................2564
Figure 22-19. Data Transfer Between IF1 / IF2 Registers and Message RAM..................................................................... 2568
Figure 22-20. Structure of a Message Object........................................................................................................................2569
Figure 22-21. Message RAM Representation in Debug Mode.............................................................................................. 2573
Figure 22-22. CAN_CTL Register..........................................................................................................................................2577
Figure 22-23. CAN_ES Register............................................................................................................................................2580
Figure 22-24. CAN_ERRC Register...................................................................................................................................... 2582
Figure 22-25. CAN_BTR Register......................................................................................................................................... 2583
Figure 22-26. CAN_INT Register...........................................................................................................................................2585

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Figure 22-27. CAN_TEST Register....................................................................................................................................... 2586

Figure 22-28. CAN_PERR Register...................................................................................................................................... 2588
Figure 22-29. CAN_RAM_INIT Register................................................................................................................................2589
Figure 22-30. CAN_GLB_INT_EN Register.......................................................................................................................... 2590
Figure 22-31. CAN_GLB_INT_FLG Register........................................................................................................................ 2591
Figure 22-32. CAN_GLB_INT_CLR Register........................................................................................................................ 2592
Figure 22-33. CAN_ABOTR Register.................................................................................................................................... 2593
Figure 22-34. CAN_TXRQ_X Register.................................................................................................................................. 2594
Figure 22-35. CAN_TXRQ_21 Register................................................................................................................................ 2595
Figure 22-36. CAN_NDAT_X Register...................................................................................................................................2596
Figure 22-37. CAN_NDAT_21 Register................................................................................................................................. 2597
Figure 22-38. CAN_IPEN_X Register....................................................................................................................................2598
Figure 22-39. CAN_IPEN_21 Register.................................................................................................................................. 2599
Figure 22-40. CAN_MVAL_X Register...................................................................................................................................2600
Figure 22-41. CAN_MVAL_21 Register................................................................................................................................. 2601
Figure 22-42. CAN_IP_MUX21 Register............................................................................................................................... 2602
Figure 22-43. CAN_IF1CMD Register................................................................................................................................... 2603
Figure 22-44. CAN_IF1MSK Register................................................................................................................................... 2606
Figure 22-45. CAN_IF1ARB Register....................................................................................................................................2607
Figure 22-46. CAN_IF1MCTL Register................................................................................................................................. 2609
Figure 22-47. CAN_IF1DATA Register.................................................................................................................................. 2611
Figure 22-48. CAN_IF1DATB Register.................................................................................................................................. 2612
Figure 22-49. CAN_IF2CMD Register................................................................................................................................... 2613
Figure 22-50. CAN_IF2MSK Register................................................................................................................................... 2616
Figure 22-51. CAN_IF2ARB Register....................................................................................................................................2617
Figure 22-52. CAN_IF2MCTL Register................................................................................................................................. 2619
Figure 22-53. CAN_IF2DATA Register.................................................................................................................................. 2621
Figure 22-54. CAN_IF2DATB Register.................................................................................................................................. 2622
Figure 22-55. CAN_IF3OBS Register....................................................................................................................................2623
Figure 22-56. CAN_IF3MSK Register................................................................................................................................... 2625
Figure 22-57. CAN_IF3ARB Register....................................................................................................................................2626
Figure 22-58. CAN_IF3MCTL Register................................................................................................................................. 2627
Figure 22-59. CAN_IF3DATA Register.................................................................................................................................. 2629
Figure 22-60. CAN_IF3DATB Register.................................................................................................................................. 2630
Figure 22-61. CAN_IF3UPD Register....................................................................................................................................2631
Figure 23-1. USB Block Diagram...........................................................................................................................................2637
Figure 23-2. USB Scheme.....................................................................................................................................................2638
Figure 23-3. USB Device Functional Address Register (USBFADDR)..................................................................................2660
Figure 23-4. USB Power Management Register (USBPOWER) in Host Mode.....................................................................2661
Figure 23-5. USB Power Management Register (USBPOWER) in Device Mode................................................................. 2662
Figure 23-6. USB Transmit Interrupt Status Register (USBTXIS)......................................................................................... 2663
Figure 23-7. USB Transmit Interrupt Status Register (USBRXIS)......................................................................................... 2665
Figure 23-8. USB Transmit Interrupt Status Enable Register (USBTXIE)............................................................................. 2667
Figure 23-9. USB Transmit Interrupt Status Enable Register (USBRXIE).............................................................................2669
Figure 23-10. USB General Interrupt Status Register (USBIS) in Host Mode.......................................................................2671
Figure 23-11. USB General Interrupt Status Register (USBIS) in Device Mode....................................................................2672
Figure 23-12. USB Interrupt Enable Register (USBIE) in Host Mode....................................................................................2673
Figure 23-13. USB Interrupt Enable Register (USBIE) in Device Mode................................................................................ 2674
Figure 23-14. USB Frame Value Register (USBFRAME)...................................................................................................... 2675
Figure 23-15. USB Endpoint Index Register (USBEPIDX).................................................................................................... 2675
Figure 23-16. USB Test Mode Register (USBTEST) in Host Mode.......................................................................................2676
Figure 23-17. USB Test Mode Register (USBTEST) in Device Mode................................................................................... 2677
Figure 23-18. USB FIFO Endpoint n Register (USBFIFO[n])................................................................................................ 2678
Figure 23-19. USB Device Control Register (USBDEVCTL)................................................................................................. 2679
Figure 23-20. USB Transmit Dynamic FIFO Sizing Register (USBTXFIFOSZ).....................................................................2681
Figure 23-21. USB Receive Dynamic FIFO Sizing Register (USBRXFIFOSZ)..................................................................... 2682
Figure 23-22. USB Transmit FIFO Start Address Register (USBTXFIFOADDR])................................................................. 2683
Figure 23-23. USB Receive FIFO Start Address Register (USBRXFIFOADDR).................................................................. 2684
Figure 23-24. USB Connect Timing Register (USBCONTIM)................................................................................................2685
Figure 23-25. USB Full-Speed Last Transaction to End of Frame Timing Register (USBFSEOF)........................................2686
Figure 23-26. USB Low-Speed Last Transaction to End of Frame Timing Register (USBLSEOF)....................................... 2686

40 TMS320F2837xD Dual-Core Real-Time Microcontrollers SPRUHM8K – DECEMBER 2013 – REVISED MAY 2024
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Figure 23-27. USB Transmit Functional Address Endpoint n Registers (USBTXFUNCADDR[n])........................................ 2687
Figure 23-28. USB Transmit Hub Address Endpoint n Registers (USBTXHUBADDR[n]).....................................................2688
Figure 23-29. USB Transmit Hub Port Endpoint n Registers (USBTXHUBPORT[n])............................................................2689
Figure 23-30. USB Receive Functional Address Endpoint n Registers (USBFIFO[n])..........................................................2690
Figure 23-31. USB Receive Hub Address Endpoint n Registers (USBRXHUBADDR[n])..................................................... 2691
Figure 23-32. USB Receive Hub Port Endpoint n Register (USBRXHUBPORT[n]).............................................................. 2692
Figure 23-33. USB Control and Status Endpoint 0 Low Register (USBCSRL0) in Host Mode............................................. 2693
Figure 23-34. USB Control and Status Endpoint 0 Low Register (USBCSRL0) in Device Mode..........................................2694
Figure 23-35. USB Control and Status Endpoint 0 High Register (USBCSRH0) in Host Mode............................................ 2696
Figure 23-36. USB Control and Status Endpoint 0 High Register (USBCSRH0) in Device Mode........................................ 2697
Figure 23-37. USB Receive Byte Count Endpoint 0 Register (USBCOUNT0)...................................................................... 2698
Figure 23-38. USB Type Endpoint 0 Register (USBTYPE0)................................................................................................. 2698
Figure 23-39. USB NAK Limit Register (USBNAKLMT)........................................................................................................ 2699
Figure 23-40. USB Maximum Transmit Data Endpoint n Registers (USBTXMAXP[n])......................................................... 2700
Figure 23-41. USB Transmit Control and Status Endpoint n Low Register (USBTXCSRL[n]) in Host Mode........................ 2701
Figure 23-42. USB Transmit Control and Status Endpoint n Low Register (USBTXCSRL[n]) in Device Mode.................... 2702
Figure 23-43. USB Transmit Control and Status Endpoint n High Register (USBTXCSRH[n]) in Host Mode.......................2704
Figure 23-44. USB Transmit Control and Status Endpoint n High Register (USBTXCSRH[n]) in Device Mode................... 2705
Figure 23-45. USB Maximum Receive Data Endpoint n Registers (USBRXMAXP[n])......................................................... 2706
Figure 23-46. USB Receive Control and Status Endpoint n Low Register (USBRXCSRL[n]) in Host Mode........................ 2707
Figure 23-47. USB Receive Control and Status Endpoint n Low Register (USBRXCSRL[n]) in Device Mode.....................2708
Figure 23-48. USB Receive Control and Status Endpoint n High Register (USBRXCSRH[n]) in Host Mode....................... 2710
Figure 23-49. USB Receive Control and Status Endpoint n High Register (USBRXCSRH[n]) in Device Mode....................2711
Figure 23-50. USB Receive Byte Count Endpoint n Register (USBRXCOUNT[n])............................................................... 2712
Figure 23-51. USB Host Transmit Configure Type Endpoint n Registers (USBTXTYPE[n])................................................. 2713
Figure 23-52. USB Host Transmit Interval Endpoint n Registers (USBTXINTERVAL[n])...................................................... 2714
Figure 23-53. USB Host Configure Receive Type Endpoint n Register (USBRXTYPE[n])................................................... 2715
Figure 23-54. USB Host Receive Polling Interval Endpoint n Registers (USBRXINTERVAL[n])...........................................2716
Figure 23-55. USB Request Packet Count in Block Transfer Endpoint n Registers (USBRQPKTCOUNT[n])......................2717
Figure 23-56. USB Receive Double Packet Buffer Disable Register (USBRXDPKTBUFDIS).............................................. 2718
Figure 23-57. USB Transmit Double Packet Buffer Disable Register (USBTXDPKTBUFDIS)..............................................2719
Figure 23-58. USB External Power Control Register (USBEPC).......................................................................................... 2720
Figure 23-59. USB External Power Control Raw Interrupt Status Register (USBEPCRIS)...................................................2722
Figure 23-60. USB External Power Control Interrupt Mask Register (USBEPCIM).............................................................. 2723
Figure 23-61. USB External Power Control Interrupt Status and Clear Register (USBEPCISC).......................................... 2724
Figure 23-62. USB Device RESUME Raw Interrupt Status Register (USBDRRIS).............................................................. 2725
Figure 23-63. USB Device RESUME Raw Interrupt Status Register (USBDRRIS).............................................................. 2726
Figure 23-64. USB Device RESUME Interrupt Status and Clear Register (USBDRISC)...................................................... 2727
Figure 23-65. USB General-Purpose Control and Status Register (USBGPCS).................................................................. 2728
Figure 23-66. USB DMA Select Register (USBDMASEL)..................................................................................................... 2729
Figure 24-1. uPP Integration..................................................................................................................................................2749
Figure 24-2. Functional Block Diagram................................................................................................................................. 2750
Figure 24-3. RX in SDR or DDR (Non-Demux) Mode........................................................................................................... 2751
Figure 24-4. RX in DDR (Demux) Mode................................................................................................................................ 2751
Figure 24-5. TX in SDR (Non-Interleave) or DDR (Non-Demux) Mode.................................................................................2751
Figure 24-6. TX in SDR (Interleave) or DDR (Demux) Mode................................................................................................ 2751
Figure 24-7. IO Output Clock Generation for TX Mode......................................................................................................... 2752
Figure 24-8. IO Input Clock for RX Mode.............................................................................................................................. 2752
Figure 24-9. Structure of DMA Window and Lines in Memory...............................................................................................2754
Figure 24-10. uPP Receive in SDR Mode............................................................................................................................. 2756
Figure 24-11. uPP Transmit in SDR Mode.............................................................................................................................2756
Figure 24-12. uPP Transmit in SDR Mode – Interleaving......................................................................................................2757
Figure 24-13. uPP Receive DDR Case................................................................................................................................. 2757
Figure 24-14. uPP Transmit DDR Case.................................................................................................................................2757
Figure 24-15. uPP Tx Data Pattern in Non-Interleaved Mode............................................................................................... 2758
Figure 24-16. uPP Rx Data Pattern in Non-Interleaved Mode...............................................................................................2758
Figure 24-17. PID Register.................................................................................................................................................... 2766
Figure 24-18. PERCTL Register............................................................................................................................................2767
Figure 24-19. CHCTL Register.............................................................................................................................................. 2769
Figure 24-20. IFCFG Register............................................................................................................................................... 2770
Figure 24-21. IFIVAL Register............................................................................................................................................... 2772

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Figure 24-22. THCFG Register..............................................................................................................................................2773

Figure 24-23. RAWINTST Register....................................................................................................................................... 2775
Figure 24-24. ENINTST Register...........................................................................................................................................2777
Figure 24-25. INTENSET Register........................................................................................................................................ 2779
Figure 24-26. INTENCLR Register........................................................................................................................................ 2781
Figure 24-27. CHIDESC0 Register........................................................................................................................................2783
Figure 24-28. CHIDESC1 Register........................................................................................................................................2784
Figure 24-29. CHIDESC2 Register........................................................................................................................................2785
Figure 24-30. CHIST0 Register............................................................................................................................................. 2786
Figure 24-31. CHIST1 Register............................................................................................................................................. 2787
Figure 24-32. CHIST2 Register............................................................................................................................................. 2788
Figure 24-33. CHQDESC0 Register...................................................................................................................................... 2789
Figure 24-34. CHQDESC1 Register...................................................................................................................................... 2790
Figure 24-35. CHQDESC2 Register...................................................................................................................................... 2791
Figure 24-36. CHQST0 Register........................................................................................................................................... 2792
Figure 24-37. CHQST1 Register........................................................................................................................................... 2793
Figure 24-38. CHQST2 Register........................................................................................................................................... 2794
Figure 24-39. GINTEN Register............................................................................................................................................ 2795
Figure 24-40. GINTFLG Register.......................................................................................................................................... 2796
Figure 24-41. GINTCLR Register.......................................................................................................................................... 2797
Figure 24-42. DLYCTL Register.............................................................................................................................................2798
Figure 25-1. EMIF Module Overview..................................................................................................................................... 2802
Figure 25-2. EMIF Functional Block Diagram........................................................................................................................2805
Figure 25-3. Timing Waveform of SDRAM PRE Command...................................................................................................2809
Figure 25-4. EMIF to 2M × 16 × 4 Bank SDRAM Interface................................................................................................... 2810
Figure 25-5. EMIF to 512K × 16 × 2 Bank SDRAM Interface................................................................................................ 2810
Figure 25-6. Timing Waveform for Basic SDRAM Read Operation....................................................................................... 2818
Figure 25-7. Timing Waveform for Basic SDRAM Write Operation....................................................................................... 2819
Figure 25-8. EMIF Asynchronous Interface........................................................................................................................... 2821
Figure 25-9. EMIF to 8-bit/16-bit Memory Interface...............................................................................................................2822
Figure 25-10. Common Asynchronous Interface................................................................................................................... 2822
Figure 25-11. Timing Waveform of an Asynchronous Read Cycle in Normal Mode.............................................................. 2826
Figure 25-12. Timing Waveform of an Asynchronous Write Cycle in Normal Mode.............................................................. 2828
Figure 25-13. Timing Waveform of an Asynchronous Read Cycle in Select Strobe Mode....................................................2830
Figure 25-14. Timing Waveform of an Asynchronous Write Cycle in Select Strobe Mode.................................................... 2832
Figure 25-15. Example Configuration Interface..................................................................................................................... 2837
Figure 25-16. SDRAM Timing Register (SDRAM_TR).......................................................................................................... 2838
Figure 25-17. SDRAM Self Refresh Exit Timing Register (SDR_EXT_TMNG)..................................................................... 2839
Figure 25-18. SDRAM Refresh Control Register (SDRAM_RCR).........................................................................................2839
Figure 25-19. SDRAM Configuration Register (SDRAM_CR)............................................................................................... 2840
Figure 25-20. LH28F800BJE-PTTL90 to EMIF Read Timing Waveforms............................................................................. 2841
Figure 25-21. LH28F800BJE-PTTL90 to EMIF Write Timing Waveforms............................................................................. 2842
Figure 25-22. Asynchronous m Configuration Register (m = 1, 2) (ASYNC_CSn_CR(n = 2, 3))..........................................2844
Figure 25-23. RCSR Register................................................................................................................................................2846
Figure 25-24. ASYNC_WCCR Register................................................................................................................................ 2847
Figure 25-25. SDRAM_CR Register......................................................................................................................................2848
Figure 25-26. SDRAM_RCR Register................................................................................................................................... 2850
Figure 25-27. ASYNC_CS2_CR Register............................................................................................................................. 2851
Figure 25-28. ASYNC_CS3_CR Register............................................................................................................................. 2853
Figure 25-29. ASYNC_CS4_CR Register............................................................................................................................. 2855
Figure 25-30. SDRAM_TR Register...................................................................................................................................... 2857
Figure 25-31. TOTAL_SDRAM_AR Register.........................................................................................................................2858
Figure 25-32. TOTAL_SDRAM_ACTR Register.................................................................................................................... 2859
Figure 25-33. SDR_EXT_TMNG Register.............................................................................................................................2860
Figure 25-34. INT_RAW Register.......................................................................................................................................... 2861
Figure 25-35. INT_MSK Register.......................................................................................................................................... 2862
Figure 25-36. INT_MSK_SET Register................................................................................................................................. 2863
Figure 25-37. INT_MSK_CLR Register................................................................................................................................. 2864
Figure 25-38. EMIF1LOCK Register......................................................................................................................................2866
Figure 25-39. EMIF1COMMIT Register.................................................................................................................................2867
Figure 25-40. EMIF1MSEL Register......................................................................................................................................2868

42 TMS320F2837xD Dual-Core Real-Time Microcontrollers SPRUHM8K – DECEMBER 2013 – REVISED MAY 2024
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Figure 25-41. EMIF1ACCPROT0 Register............................................................................................................................2869

Figure 25-42. EMIF2LOCK Register......................................................................................................................................2871
Figure 25-43. EMIF2COMMIT Register.................................................................................................................................2872
Figure 25-44. EMIF2ACCPROT0 Register............................................................................................................................2873
Figure 26-1. Block Diagram of the CLB Subsystem in the Device........................................................................................ 2877
Figure 26-2. Block Diagram of a CLB Tile and CPU Interface...............................................................................................2877
Figure 26-3. CLB Clocking.....................................................................................................................................................2878
Figure 26-4. GPIO to CLB Tile Connections..........................................................................................................................2879
Figure 26-5. CLB Input Mux and Filter...................................................................................................................................2880
Figure 26-6. CLB Input Synchronization Example.................................................................................................................2880
Figure 26-7. CLB Outputs......................................................................................................................................................2885
Figure 26-8. CLB Output Signal Multiplexer.......................................................................................................................... 2886
Figure 26-9. CLB Tile Submodules........................................................................................................................................2887
Figure 26-10. Counter Block..................................................................................................................................................2890
Figure 26-11. FSM Block....................................................................................................................................................... 2893
Figure 26-12. FSM LUT Block............................................................................................................................................... 2894
Figure 26-13. LUT4 Block......................................................................................................................................................2895
Figure 26-14. Output LUT Block............................................................................................................................................ 2895
Figure 26-15. High Level Controller Block............................................................................................................................. 2896
Figure 26-16. CLB_COUNT_RESET Register...................................................................................................................... 2908
Figure 26-17. CLB_COUNT_MODE_1 Register................................................................................................................... 2909
Figure 26-18. CLB_COUNT_MODE_0 Register................................................................................................................... 2910
Figure 26-19. CLB_COUNT_EVENT Register.......................................................................................................................2911
Figure 26-20. CLB_FSM_EXTRA_IN0 Register....................................................................................................................2912
Figure 26-21. CLB_FSM_EXTERNAL_IN0 Register.............................................................................................................2913
Figure 26-22. CLB_FSM_EXTERNAL_IN1 Register.............................................................................................................2914
Figure 26-23. CLB_FSM_EXTRA_IN1 Register....................................................................................................................2915
Figure 26-24. CLB_LUT4_IN0 Register.................................................................................................................................2916
Figure 26-25. CLB_LUT4_IN1 Register.................................................................................................................................2917
Figure 26-26. CLB_LUT4_IN2 Register.................................................................................................................................2918
Figure 26-27. CLB_LUT4_IN3 Register.................................................................................................................................2919
Figure 26-28. CLB_FSM_LUT_FN1_0 Register....................................................................................................................2920
Figure 26-29. CLB_FSM_LUT_FN2 Register........................................................................................................................2921
Figure 26-30. CLB_LUT4_FN1_0 Register........................................................................................................................... 2922
Figure 26-31. CLB_LUT4_FN2 Register............................................................................................................................... 2923
Figure 26-32. CLB_FSM_NEXT_STATE_0 Register.............................................................................................................2924
Figure 26-33. CLB_FSM_NEXT_STATE_1 Register.............................................................................................................2925
Figure 26-34. CLB_FSM_NEXT_STATE_2 Register.............................................................................................................2926
Figure 26-35. CLB_MISC_CONTROL Register.................................................................................................................... 2927
Figure 26-36. CLB_OUTPUT_LUT_0 Register..................................................................................................................... 2929
Figure 26-37. CLB_OUTPUT_LUT_1 Register..................................................................................................................... 2930
Figure 26-38. CLB_OUTPUT_LUT_2 Register..................................................................................................................... 2931
Figure 26-39. CLB_OUTPUT_LUT_3 Register..................................................................................................................... 2932
Figure 26-40. CLB_OUTPUT_LUT_4 Register..................................................................................................................... 2933
Figure 26-41. CLB_OUTPUT_LUT_5 Register..................................................................................................................... 2934
Figure 26-42. CLB_OUTPUT_LUT_6 Register..................................................................................................................... 2935
Figure 26-43. CLB_OUTPUT_LUT_7 Register..................................................................................................................... 2936
Figure 26-44. CLB_HLC_EVENT_SEL Register................................................................................................................... 2937
Figure 26-45. CLB_LOAD_EN Register................................................................................................................................ 2940
Figure 26-46. CLB_LOAD_ADDR Register........................................................................................................................... 2941
Figure 26-47. CLB_LOAD_DATA Register............................................................................................................................ 2942
Figure 26-48. CLB_INPUT_FILTER Register........................................................................................................................ 2943
Figure 26-49. CLB_IN_MUX_SEL_0 Register.......................................................................................................................2945
Figure 26-50. CLB_LCL_MUX_SEL_1 Register....................................................................................................................2947
Figure 26-51. CLB_LCL_MUX_SEL_2 Register....................................................................................................................2948
Figure 26-52. CLB_BUF_PTR Register.................................................................................................................................2949
Figure 26-53. CLB_GP_REG Register.................................................................................................................................. 2950
Figure 26-54. CLB_OUT_EN Register.................................................................................................................................. 2951
Figure 26-55. CLB_GLBL_MUX_SEL_1 Register................................................................................................................. 2952
Figure 26-56. CLB_GLBL_MUX_SEL_2 Register................................................................................................................. 2953
Figure 26-57. CLB_INTR_TAG_REG Register......................................................................................................................2954

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Figure 26-58. CLB_LOCK Register....................................................................................................................................... 2955

Figure 26-59. CLB_DBG_R0 Register...................................................................................................................................2956
Figure 26-60. CLB_DBG_R1 Register...................................................................................................................................2957
Figure 26-61. CLB_DBG_R2 Register...................................................................................................................................2958
Figure 26-62. CLB_DBG_R3 Register...................................................................................................................................2959
Figure 26-63. CLB_DBG_C0 Register...................................................................................................................................2960
Figure 26-64. CLB_DBG_C1 Register...................................................................................................................................2961
Figure 26-65. CLB_DBG_C2 Register...................................................................................................................................2962
Figure 26-66. CLB_DBG_OUT Register................................................................................................................................2963
Figure 26-67. CLB_PUSH_y Register................................................................................................................................... 2966
Figure 26-68. CLB_PULL_y Register.................................................................................................................................... 2967

List of Tables
Table 1-1. C2000Ware Root Directories.................................................................................................................................... 76
Table 2-1. TMU Supported Instructions..................................................................................................................................... 80
Table 2-2. Viterbi Decode Performance..................................................................................................................................... 81
Table 2-3. Complex Math Performance..................................................................................................................................... 81
Table 3-1. Reset Signals............................................................................................................................................................84
Table 3-2. PIE Channel Mapping............................................................................................................................................... 92
Table 3-3. CPU Interrupt Vectors............................................................................................................................................... 94
Table 3-4. PIE Interrupt Vectors.................................................................................................................................................95
Table 3-5. Access to EALLOW-Protected Registers................................................................................................................101
Table 3-6. Clock Connections Sorted by Clock Domain...........................................................................................................110
Table 3-7. Clock Connections Sorted by Module Name...........................................................................................................111
Table 3-8. Clock Source (OSCCLK) Failure Detection.............................................................................................................114
Table 3-9. Example Watchdog Key Sequences....................................................................................................................... 119
Table 3-10. LPM Entry and Exit Criteria...................................................................................................................................123
Table 3-11. Local Shared RAM................................................................................................................................................ 126
Table 3-12. Global Shared RAM.............................................................................................................................................. 126
Table 3-13. Error Handling in Different Scenarios....................................................................................................................131
Table 3-14. Mapping of ECC Bits in Read Data from ECC/Parity Address Map..................................................................... 132
Table 3-15. Mapping of Parity Bits in Read Data from ECC/Parity Address Map....................................................................132
Table 3-16. CLA Access Filter................................................................................................................................................. 147
Table 3-17. RAM Status...........................................................................................................................................................148
Table 3-18. Security Levels......................................................................................................................................................148
Table 3-19. System Control Registers Impacted..................................................................................................................... 160
Table 3-20. System Control Base Address Table.................................................................................................................... 166
Table 3-21. CPUTIMER_REGS Registers...............................................................................................................................167
Table 3-22. CPUTIMER_REGS Access Type Codes.............................................................................................................. 167
Table 3-23. TIM Register Field Descriptions............................................................................................................................168
Table 3-24. PRD Register Field Descriptions.......................................................................................................................... 169
Table 3-25. TCR Register Field Descriptions...........................................................................................................................170
Table 3-26. TPR Register Field Descriptions...........................................................................................................................172
Table 3-27. TPRH Register Field Descriptions........................................................................................................................ 173
Table 3-28. PIE_CTRL_REGS Registers................................................................................................................................ 174
Table 3-29. PIE_CTRL_REGS Access Type Codes................................................................................................................174
Table 3-30. PIECTRL Register Field Descriptions...................................................................................................................176
Table 3-31. PIEACK Register Field Descriptions.....................................................................................................................177
Table 3-32. PIEIER1 Register Field Descriptions.................................................................................................................... 178
Table 3-33. PIEIFR1 Register Field Descriptions.................................................................................................................... 180
Table 3-34. PIEIER2 Register Field Descriptions.................................................................................................................... 182
Table 3-35. PIEIFR2 Register Field Descriptions.................................................................................................................... 184
Table 3-36. PIEIER3 Register Field Descriptions.................................................................................................................... 186
Table 3-37. PIEIFR3 Register Field Descriptions.................................................................................................................... 188
Table 3-38. PIEIER4 Register Field Descriptions.................................................................................................................... 190
Table 3-39. PIEIFR4 Register Field Descriptions.................................................................................................................... 192
Table 3-40. PIEIER5 Register Field Descriptions.................................................................................................................... 194
Table 3-41. PIEIFR5 Register Field Descriptions.................................................................................................................... 196
Table 3-42. PIEIER6 Register Field Descriptions.................................................................................................................... 198
Table 3-43. PIEIFR6 Register Field Descriptions.................................................................................................................... 200

44 TMS320F2837xD Dual-Core Real-Time Microcontrollers SPRUHM8K – DECEMBER 2013 – REVISED MAY 2024
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Table 3-44. PIEIER7 Register Field Descriptions.................................................................................................................... 202

Table 3-45. PIEIFR7 Register Field Descriptions.................................................................................................................... 204
Table 3-46. PIEIER8 Register Field Descriptions.................................................................................................................... 206
Table 3-47. PIEIFR8 Register Field Descriptions.................................................................................................................... 208
Table 3-48. PIEIER9 Register Field Descriptions.................................................................................................................... 210
Table 3-49. PIEIFR9 Register Field Descriptions.................................................................................................................... 212
Table 3-50. PIEIER10 Register Field Descriptions.................................................................................................................. 214
Table 3-51. PIEIFR10 Register Field Descriptions.................................................................................................................. 216
Table 3-52. PIEIER11 Register Field Descriptions...................................................................................................................218
Table 3-53. PIEIFR11 Register Field Descriptions...................................................................................................................220
Table 3-54. PIEIER12 Register Field Descriptions.................................................................................................................. 222
Table 3-55. PIEIFR12 Register Field Descriptions.................................................................................................................. 224
Table 3-56. WD_REGS Registers............................................................................................................................................226
Table 3-57. WD_REGS Access Type Codes........................................................................................................................... 226
Table 3-58. SCSR Register Field Descriptions........................................................................................................................ 227
Table 3-59. WDCNTR Register Field Descriptions.................................................................................................................. 228
Table 3-60. WDKEY Register Field Descriptions.....................................................................................................................229
Table 3-61. WDCR Register Field Descriptions.......................................................................................................................230
Table 3-62. WDWCR Register Field Descriptions................................................................................................................... 231
Table 3-63. NMI_INTRUPT_REGS Registers......................................................................................................................... 232
Table 3-64. NMI_INTRUPT_REGS Access Type Codes.........................................................................................................232
Table 3-65. NMICFG Register Field Descriptions....................................................................................................................233
Table 3-66. NMIFLG Register Field Descriptions.................................................................................................................... 234
Table 3-67. NMIFLGCLR Register Field Descriptions............................................................................................................. 236
Table 3-68. NMIFLGFRC Register Field Descriptions............................................................................................................. 239
Table 3-69. NMIWDCNT Register Field Descriptions.............................................................................................................. 241
Table 3-70. NMIWDPRD Register Field Descriptions..............................................................................................................242
Table 3-71. NMISHDFLG Register Field Descriptions.............................................................................................................243
Table 3-72. XINT_REGS Registers......................................................................................................................................... 245
Table 3-73. XINT_REGS Access Type Codes.........................................................................................................................245
Table 3-74. XINT1CR Register Field Descriptions...................................................................................................................246
Table 3-75. XINT2CR Register Field Descriptions...................................................................................................................247
Table 3-76. XINT3CR Register Field Descriptions...................................................................................................................248
Table 3-77. XINT4CR Register Field Descriptions...................................................................................................................249
Table 3-78. XINT5CR Register Field Descriptions...................................................................................................................250
Table 3-79. XINT1CTR Register Field Descriptions................................................................................................................ 251
Table 3-80. XINT2CTR Register Field Descriptions................................................................................................................ 252
Table 3-81. XINT3CTR Register Field Descriptions................................................................................................................ 253
Table 3-82. SYNC_SOC_REGS Registers..............................................................................................................................254
Table 3-83. SYNC_SOC_REGS Access Type Codes............................................................................................................. 254
Table 3-84. SYNCSELECT Register Field Descriptions.......................................................................................................... 255
Table 3-85. ADCSOCOUTSELECT Register Field Descriptions............................................................................................. 257
Table 3-86. SYNCSOCLOCK Register Field Descriptions...................................................................................................... 260
Table 3-87. DMA_CLA_SRC_SEL_REGS Registers.............................................................................................................. 261
Table 3-88. DMA_CLA_SRC_SEL_REGS Access Type Codes..............................................................................................261
Table 3-89. CLA1TASKSRCSELLOCK Register Field Descriptions........................................................................................262
Table 3-90. DMACHSRCSELLOCK Register Field Descriptions.............................................................................................263
Table 3-91. CLA1TASKSRCSEL1 Register Field Descriptions................................................................................................264
Table 3-92. CLA1TASKSRCSEL2 Register Field Descriptions................................................................................................265
Table 3-93. DMACHSRCSEL1 Register Field Descriptions.................................................................................................... 266
Table 3-94. DMACHSRCSEL2 Register Field Descriptions.................................................................................................... 267
Table 3-95. FLASH_PUMP_SEMAPHORE_REGS Registers.................................................................................................268
Table 3-96. FLASH_PUMP_SEMAPHORE_REGS Access Type Codes................................................................................ 268
Table 3-97. PUMPREQUEST Register Field Descriptions...................................................................................................... 269
Table 3-98. DEV_CFG_REGS Registers.................................................................................................................................270
Table 3-99. DEV_CFG_REGS Access Type Codes................................................................................................................ 271
Table 3-100. DEVCFGLOCK1 Register Field Descriptions..................................................................................................... 272
Table 3-101. PARTIDL Register Field Descriptions................................................................................................................. 274
Table 3-102. PARTIDH Register Field Descriptions.................................................................................................................276
Table 3-103. REVID Register Field Descriptions..................................................................................................................... 277
Table 3-104. DC0 Register Field Descriptions.........................................................................................................................278

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Table 3-105. DC1 Register Field Descriptions.........................................................................................................................279

Table 3-106. DC2 Register Field Descriptions.........................................................................................................................280
Table 3-107. DC3 Register Field Descriptions.........................................................................................................................281
Table 3-108. DC4 Register Field Descriptions.........................................................................................................................283
Table 3-109. DC5 Register Field Descriptions.........................................................................................................................284
Table 3-110. DC6 Register Field Descriptions......................................................................................................................... 285
Table 3-111. DC7 Register Field Descriptions......................................................................................................................... 286
Table 3-112. DC8 Register Field Descriptions......................................................................................................................... 287
Table 3-113. DC9 Register Field Descriptions......................................................................................................................... 288
Table 3-114. DC10 Register Field Descriptions....................................................................................................................... 289
Table 3-115. DC11 Register Field Descriptions....................................................................................................................... 290
Table 3-116. DC12 Register Field Descriptions....................................................................................................................... 291
Table 3-117. DC13 Register Field Descriptions....................................................................................................................... 292
Table 3-118. DC14 Register Field Descriptions....................................................................................................................... 293
Table 3-119. DC15 Register Field Descriptions....................................................................................................................... 294
Table 3-120. DC17 Register Field Descriptions.......................................................................................................................296
Table 3-121. DC18 Register Field Descriptions.......................................................................................................................297
Table 3-122. DC19 Register Field Descriptions.......................................................................................................................298
Table 3-123. DC20 Register Field Descriptions.......................................................................................................................299
Table 3-124. PERCNF1 Register Field Descriptions............................................................................................................... 301
Table 3-125. FUSEERR Register Field Descriptions...............................................................................................................302
Table 3-126. SOFTPRES0 Register Field Descriptions...........................................................................................................303
Table 3-127. SOFTPRES1 Register Field Descriptions...........................................................................................................304
Table 3-128. SOFTPRES2 Register Field Descriptions...........................................................................................................305
Table 3-129. SOFTPRES3 Register Field Descriptions...........................................................................................................307
Table 3-130. SOFTPRES4 Register Field Descriptions...........................................................................................................308
Table 3-131. SOFTPRES6 Register Field Descriptions...........................................................................................................309
Table 3-132. SOFTPRES7 Register Field Descriptions...........................................................................................................310
Table 3-133. SOFTPRES8 Register Field Descriptions........................................................................................................... 311
Table 3-134. SOFTPRES9 Register Field Descriptions...........................................................................................................312
Table 3-135. SOFTPRES11 Register Field Descriptions......................................................................................................... 313
Table 3-136. SOFTPRES13 Register Field Descriptions.........................................................................................................314
Table 3-137. SOFTPRES14 Register Field Descriptions.........................................................................................................315
Table 3-138. SOFTPRES16 Register Field Descriptions.........................................................................................................316
Table 3-139. CPUSEL0 Register Field Descriptions................................................................................................................317
Table 3-140. CPUSEL1 Register Field Descriptions................................................................................................................319
Table 3-141. CPUSEL2 Register Field Descriptions................................................................................................................320
Table 3-142. CPUSEL3 Register Field Descriptions................................................................................................................321
Table 3-143. CPUSEL4 Register Field Descriptions................................................................................................................322
Table 3-144. CPUSEL5 Register Field Descriptions................................................................................................................323
Table 3-145. CPUSEL6 Register Field Descriptions................................................................................................................324
Table 3-146. CPUSEL7 Register Field Descriptions................................................................................................................325
Table 3-147. CPUSEL8 Register Field Descriptions................................................................................................................326
Table 3-148. CPUSEL9 Register Field Descriptions................................................................................................................327
Table 3-149. CPUSEL11 Register Field Descriptions.............................................................................................................. 328
Table 3-150. CPUSEL12 Register Field Descriptions..............................................................................................................330
Table 3-151. CPUSEL14 Register Field Descriptions..............................................................................................................332
Table 3-152. CPU2RESCTL Register Field Descriptions........................................................................................................ 333
Table 3-153. RSTSTAT Register Field Descriptions................................................................................................................ 334
Table 3-154. LPMSTAT Register Field Descriptions................................................................................................................ 335
Table 3-155. SYSDBGCTL Register Field Descriptions.......................................................................................................... 336
Table 3-156. CLK_CFG_REGS Registers............................................................................................................................... 337
Table 3-157. CLK_CFG_REGS Access Type Codes.............................................................................................................. 337
Table 3-158. CLKSEM Register Field Descriptions................................................................................................................. 339
Table 3-159. CLKCFGLOCK1 Register Field Descriptions......................................................................................................340
Table 3-160. CLKSRCCTL1 Register Field Descriptions.........................................................................................................342
Table 3-161. CLKSRCCTL2 Register Field Descriptions.........................................................................................................344
Table 3-162. CLKSRCCTL3 Register Field Descriptions.........................................................................................................346
Table 3-163. SYSPLLCTL1 Register Field Descriptions..........................................................................................................347
Table 3-164. SYSPLLMULT Register Field Descriptions......................................................................................................... 348
Table 3-165. SYSPLLSTS Register Field Descriptions........................................................................................................... 349

46 TMS320F2837xD Dual-Core Real-Time Microcontrollers SPRUHM8K – DECEMBER 2013 – REVISED MAY 2024
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Table 3-166. AUXPLLCTL1 Register Field Descriptions......................................................................................................... 350

Table 3-167. AUXPLLMULT Register Field Descriptions.........................................................................................................351
Table 3-168. AUXPLLSTS Register Field Descriptions........................................................................................................... 352
Table 3-169. SYSCLKDIVSEL Register Field Descriptions..................................................................................................... 353
Table 3-170. AUXCLKDIVSEL Register Field Descriptions.....................................................................................................354
Table 3-171. PERCLKDIVSEL Register Field Descriptions.....................................................................................................355
Table 3-172. XCLKOUTDIVSEL Register Field Descriptions.................................................................................................. 356
Table 3-173. LOSPCP Register Field Descriptions................................................................................................................. 357
Table 3-174. MCDCR Register Field Descriptions...................................................................................................................358
Table 3-175. X1CNT Register Field Descriptions.................................................................................................................... 359
Table 3-176. CPU_SYS_REGS Registers...............................................................................................................................360
Table 3-177. CPU_SYS_REGS Access Type Codes.............................................................................................................. 360
Table 3-178. CPUSYSLOCK1 Register Field Descriptions..................................................................................................... 362
Table 3-179. HIBBOOTMODE Register Field Descriptions..................................................................................................... 365
Table 3-180. IORESTOREADDR Register Field Descriptions.................................................................................................366
Table 3-181. PIEVERRADDR Register Field Descriptions...................................................................................................... 367
Table 3-182. PCLKCR0 Register Field Descriptions............................................................................................................... 368
Table 3-183. PCLKCR1 Register Field Descriptions............................................................................................................... 370
Table 3-184. PCLKCR2 Register Field Descriptions............................................................................................................... 371
Table 3-185. PCLKCR3 Register Field Descriptions............................................................................................................... 373
Table 3-186. PCLKCR4 Register Field Descriptions............................................................................................................... 374
Table 3-187. PCLKCR6 Register Field Descriptions............................................................................................................... 375
Table 3-188. PCLKCR7 Register Field Descriptions............................................................................................................... 376
Table 3-189. PCLKCR8 Register Field Descriptions............................................................................................................... 377
Table 3-190. PCLKCR9 Register Field Descriptions............................................................................................................... 378
Table 3-191. PCLKCR10 Register Field Descriptions............................................................................................................. 379
Table 3-192. PCLKCR11 Register Field Descriptions..............................................................................................................380
Table 3-193. PCLKCR12 Register Field Descriptions............................................................................................................. 381
Table 3-194. PCLKCR13 Register Field Descriptions............................................................................................................. 382
Table 3-195. PCLKCR14 Register Field Descriptions............................................................................................................. 383
Table 3-196. PCLKCR16 Register Field Descriptions............................................................................................................. 385
Table 3-197. SECMSEL Register Field Descriptions...............................................................................................................386
Table 3-198. LPMCR Register Field Descriptions................................................................................................................... 387
Table 3-199. GPIOLPMSEL0 Register Field Descriptions.......................................................................................................389
Table 3-200. GPIOLPMSEL1 Register Field Descriptions.......................................................................................................392
Table 3-201. TMR2CLKCTL Register Field Descriptions........................................................................................................ 395
Table 3-202. RESC Register Field Descriptions...................................................................................................................... 397
Table 3-203. ROM_PREFETCH_REGS Registers..................................................................................................................399
Table 3-204. ROM_PREFETCH_REGS Access Type Codes................................................................................................. 399
Table 3-205. ROMPREFETCH Register Field Descriptions.................................................................................................... 400
Table 3-206. DCSM_Z1_REGS Registers...............................................................................................................................401
Table 3-207. DCSM_Z1_REGS Access Type Codes.............................................................................................................. 401
Table 3-208. Z1_LINKPOINTER Register Field Descriptions..................................................................................................402
Table 3-209. Z1_OTPSECLOCK Register Field Descriptions................................................................................................. 403
Table 3-210. Z1_BOOTCTRL Register Field Descriptions...................................................................................................... 404
Table 3-211. Z1_LINKPOINTERERR Register Field Descriptions...........................................................................................405
Table 3-212. Z1_CSMKEY0 Register Field Descriptions.........................................................................................................406
Table 3-213. Z1_CSMKEY1 Register Field Descriptions.........................................................................................................407
Table 3-214. Z1_CSMKEY2 Register Field Descriptions.........................................................................................................408
Table 3-215. Z1_CSMKEY3 Register Field Descriptions.........................................................................................................409
Table 3-216. Z1_CR Register Field Descriptions.....................................................................................................................410
Table 3-217. Z1_GRABSECTR Register Field Descriptions....................................................................................................411
Table 3-218. Z1_GRABRAMR Register Field Descriptions..................................................................................................... 414
Table 3-219. Z1_EXEONLYSECTR Register Field Descriptions............................................................................................. 416
Table 3-220. Z1_EXEONLYRAMR Register Field Descriptions...............................................................................................419
Table 3-221. DCSM_Z2_REGS Registers...............................................................................................................................421
Table 3-222. DCSM_Z2_REGS Access Type Codes.............................................................................................................. 421
Table 3-223. Z2_LINKPOINTER Register Field Descriptions..................................................................................................422
Table 3-224. Z2_OTPSECLOCK Register Field Descriptions................................................................................................. 423
Table 3-225. Z2_BOOTCTRL Register Field Descriptions...................................................................................................... 424
Table 3-226. Z2_LINKPOINTERERR Register Field Descriptions.......................................................................................... 425

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Table 3-227. Z2_CSMKEY0 Register Field Descriptions.........................................................................................................426

Table 3-228. Z2_CSMKEY1 Register Field Descriptions.........................................................................................................427
Table 3-229. Z2_CSMKEY2 Register Field Descriptions.........................................................................................................428
Table 3-230. Z2_CSMKEY3 Register Field Descriptions.........................................................................................................429
Table 3-231. Z2_CR Register Field Descriptions.....................................................................................................................430
Table 3-232. Z2_GRABSECTR Register Field Descriptions................................................................................................... 431
Table 3-233. Z2_GRABRAMR Register Field Descriptions..................................................................................................... 434
Table 3-234. Z2_EXEONLYSECTR Register Field Descriptions............................................................................................. 436
Table 3-235. Z2_EXEONLYRAMR Register Field Descriptions...............................................................................................439
Table 3-236. DCSM_COMMON_REGS Registers.................................................................................................................. 441
Table 3-237. DCSM_COMMON_REGS Access Type Codes..................................................................................................441
Table 3-238. FLSEM Register Field Descriptions.................................................................................................................... 442
Table 3-239. SECTSTAT Register Field Descriptions..............................................................................................................443
Table 3-240. RAMSTAT Register Field Descriptions............................................................................................................... 446
Table 3-241. MEM_CFG_REGS Registers..............................................................................................................................448
Table 3-242. MEM_CFG_REGS Access Type Codes............................................................................................................. 448
Table 3-243. DxLOCK Register Field Descriptions..................................................................................................................450
Table 3-244. DxCOMMIT Register Field Descriptions............................................................................................................. 451
Table 3-245. DxACCPROT0 Register Field Descriptions........................................................................................................ 452
Table 3-246. DxTEST Register Field Descriptions.................................................................................................................. 453
Table 3-247. DxINIT Register Field Descriptions.....................................................................................................................454
Table 3-248. DxINITDONE Register Field Descriptions.......................................................................................................... 455
Table 3-249. LSxLOCK Register Field Descriptions................................................................................................................ 456
Table 3-250. LSxCOMMIT Register Field Descriptions........................................................................................................... 458
Table 3-251. LSxMSEL Register Field Descriptions................................................................................................................ 460
Table 3-252. LSxCLAPGM Register Field Descriptions...........................................................................................................462
Table 3-253. LSxACCPROT0 Register Field Descriptions...................................................................................................... 463
Table 3-254. LSxACCPROT1 Register Field Descriptions...................................................................................................... 465
Table 3-255. LSxTEST Register Field Descriptions.................................................................................................................466
Table 3-256. LSxINIT Register Field Descriptions................................................................................................................... 468
Table 3-257. LSxINITDONE Register Field Descriptions.........................................................................................................469
Table 3-258. GSxLOCK Register Field Descriptions............................................................................................................... 470
Table 3-259. GSxCOMMIT Register Field Descriptions.......................................................................................................... 472
Table 3-260. GSxMSEL Register Field Descriptions............................................................................................................... 475
Table 3-261. GSxACCPROT0 Register Field Descriptions..................................................................................................... 477
Table 3-262. GSxACCPROT1 Register Field Descriptions..................................................................................................... 479
Table 3-263. GSxACCPROT2 Register Field Descriptions..................................................................................................... 481
Table 3-264. GSxACCPROT3 Register Field Descriptions..................................................................................................... 483
Table 3-265. GSxTEST Register Field Descriptions................................................................................................................485
Table 3-266. GSxINIT Register Field Descriptions.................................................................................................................. 488
Table 3-267. GSxINITDONE Register Field Descriptions........................................................................................................490
Table 3-268. MSGxTEST Register Field Descriptions.............................................................................................................492
Table 3-269. MSGxINIT Register Field Descriptions............................................................................................................... 493
Table 3-270. MSGxINITDONE Register Field Descriptions.....................................................................................................494
Table 3-271. ACCESS_PROTECTION_REGS Registers....................................................................................................... 495
Table 3-272. ACCESS_PROTECTION_REGS Access Type Codes.......................................................................................495
Table 3-273. NMAVFLG Register Field Descriptions............................................................................................................... 497
Table 3-274. NMAVSET Register Field Descriptions............................................................................................................... 499
Table 3-275. NMAVCLR Register Field Descriptions...............................................................................................................501
Table 3-276. NMAVINTEN Register Field Descriptions........................................................................................................... 503
Table 3-277. NMCPURDAVADDR Register Field Descriptions............................................................................................... 504
Table 3-278. NMCPUWRAVADDR Register Field Descriptions.............................................................................................. 505
Table 3-279. NMCPUFAVADDR Register Field Descriptions.................................................................................................. 506
Table 3-280. NMDMAWRAVADDR Register Field Descriptions.............................................................................................. 507
Table 3-281. NMCLA1RDAVADDR Register Field Descriptions..............................................................................................508
Table 3-282. NMCLA1WRAVADDR Register Field Descriptions............................................................................................. 509
Table 3-283. NMCLA1FAVADDR Register Field Descriptions................................................................................................. 510
Table 3-284. MAVFLG Register Field Descriptions..................................................................................................................511
Table 3-285. MAVSET Register Field Descriptions..................................................................................................................512
Table 3-286. MAVCLR Register Field Descriptions................................................................................................................. 513
Table 3-287. MAVINTEN Register Field Descriptions..............................................................................................................514

48 TMS320F2837xD Dual-Core Real-Time Microcontrollers SPRUHM8K – DECEMBER 2013 – REVISED MAY 2024
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Table 3-288. MCPUFAVADDR Register Field Descriptions..................................................................................................... 515

Table 3-289. MCPUWRAVADDR Register Field Descriptions................................................................................................. 516
Table 3-290. MDMAWRAVADDR Register Field Descriptions.................................................................................................517
Table 3-291. MEMORY_ERROR_REGS Registers.................................................................................................................518
Table 3-292. MEMORY_ERROR_REGS Access Type Codes................................................................................................ 518
Table 3-293. UCERRFLG Register Field Descriptions............................................................................................................ 519
Table 3-294. UCERRSET Register Field Descriptions............................................................................................................ 520
Table 3-295. UCERRCLR Register Field Descriptions............................................................................................................ 521
Table 3-296. UCCPUREADDR Register Field Descriptions.................................................................................................... 522
Table 3-297. UCDMAREADDR Register Field Descriptions....................................................................................................523
Table 3-298. UCCLA1READDR Register Field Descriptions...................................................................................................524
Table 3-299. CERRFLG Register Field Descriptions...............................................................................................................525
Table 3-300. CERRSET Register Field Descriptions...............................................................................................................526
Table 3-301. CERRCLR Register Field Descriptions...............................................................................................................527
Table 3-302. CCPUREADDR Register Field Descriptions.......................................................................................................528
Table 3-303. CERRCNT Register Field Descriptions.............................................................................................................. 529
Table 3-304. CERRTHRES Register Field Descriptions..........................................................................................................530
Table 3-305. CEINTFLG Register Field Descriptions.............................................................................................................. 531
Table 3-306. CEINTCLR Register Field Descriptions.............................................................................................................. 532
Table 3-307. CEINTSET Register Field Descriptions.............................................................................................................. 533
Table 3-308. CEINTEN Register Field Descriptions................................................................................................................ 534
Table 3-309. ROM_WAIT_STATE_REGS Registers............................................................................................................... 535
Table 3-310. ROM_WAIT_STATE_REGS Access Type Codes...............................................................................................535
Table 3-311. ROMWAITSTATE Register Field Descriptions.................................................................................................... 536
Table 3-312. FLASH_CTRL_REGS Registers.........................................................................................................................537
Table 3-313. FLASH_CTRL_REGS Access Type Codes........................................................................................................ 537
Table 3-314. FRDCNTL Register Field Descriptions............................................................................................................... 538
Table 3-315. FBAC Register Field Descriptions...................................................................................................................... 539
Table 3-316. FBFALLBACK Register Field Descriptions......................................................................................................... 540
Table 3-317. FBPRDY Register Field Descriptions................................................................................................................. 541
Table 3-318. FPAC1 Register Field Descriptions.....................................................................................................................542
Table 3-319. FMSTAT Register Field Descriptions.................................................................................................................. 543
Table 3-320. FRD_INTF_CTRL Register Field Descriptions................................................................................................... 545
Table 3-321. FLASH_ECC_REGS Registers.......................................................................................................................... 546
Table 3-322. FLASH_ECC_REGS Access Type Codes..........................................................................................................546
Table 3-323. ECC_ENABLE Register Field Descriptions........................................................................................................ 548
Table 3-324. SINGLE_ERR_ADDR_LOW Register Field Descriptions...................................................................................549
Table 3-325. SINGLE_ERR_ADDR_HIGH Register Field Descriptions.................................................................................. 550
Table 3-326. UNC_ERR_ADDR_LOW Register Field Descriptions........................................................................................ 551
Table 3-327. UNC_ERR_ADDR_HIGH Register Field Descriptions....................................................................................... 552
Table 3-328. ERR_STATUS Register Field Descriptions.........................................................................................................553
Table 3-329. ERR_POS Register Field Descriptions...............................................................................................................555
Table 3-330. ERR_STATUS_CLR Register Field Descriptions................................................................................................556
Table 3-331. ERR_CNT Register Field Descriptions............................................................................................................... 557
Table 3-332. ERR_THRESHOLD Register Field Descriptions................................................................................................ 558
Table 3-333. ERR_INTFLG Register Field Descriptions..........................................................................................................559
Table 3-334. ERR_INTCLR Register Field Descriptions......................................................................................................... 560
Table 3-335. FDATAH_TEST Register Field Descriptions....................................................................................................... 561
Table 3-336. FDATAL_TEST Register Field Descriptions........................................................................................................562
Table 3-337. FADDR_TEST Register Field Descriptions.........................................................................................................563
Table 3-338. FECC_TEST Register Field Descriptions........................................................................................................... 564
Table 3-339. FECC_CTRL Register Field Descriptions...........................................................................................................565
Table 3-340. FOUTH_TEST Register Field Descriptions........................................................................................................ 566
Table 3-341. FOUTL_TEST Register Field Descriptions......................................................................................................... 567
Table 3-342. FECC_STATUS Register Field Descriptions.......................................................................................................568
Table 3-343. CPU_ID_REGS Registers.................................................................................................................................. 569
Table 3-344. CPU_ID_REGS Access Type Codes..................................................................................................................569
Table 3-345. CPUID Register Field Descriptions.....................................................................................................................570
Table 3-346. UID_REGS Registers......................................................................................................................................... 571
Table 3-347. UID_REGS Access Type Codes.........................................................................................................................571
Table 3-348. UID_PSRAND0 Register Field Descriptions.......................................................................................................572

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Table 3-349. UID_PSRAND1 Register Field Descriptions.......................................................................................................573

Table 3-350. UID_PSRAND2 Register Field Descriptions.......................................................................................................574
Table 3-351. UID_PSRAND3 Register Field Descriptions.......................................................................................................575
Table 3-352. UID_PSRAND4 Register Field Descriptions.......................................................................................................576
Table 3-353. UID_PSRAND5 Register Field Descriptions.......................................................................................................577
Table 3-354. UID_UNIQUE Register Field Descriptions..........................................................................................................578
Table 3-355. UID_CHECKSUM Register Field Descriptions................................................................................................... 579
Table 3-356. DCSM_Z1_OTP Registers..................................................................................................................................580
Table 3-357. DCSM_Z1_OTP Access Type Codes................................................................................................................. 580
Table 3-358. Z1OTP_LINKPOINTER1 Register Field Descriptions........................................................................................ 581
Table 3-359. Z1OTP_LINKPOINTER2 Register Field Descriptions........................................................................................ 582
Table 3-360. Z1OTP_LINKPOINTER3 Register Field Descriptions........................................................................................ 583
Table 3-361. Z1OTP_PSWDLOCK Register Field Descriptions..............................................................................................584
Table 3-362. Z1OTP_CRCLOCK Register Field Descriptions.................................................................................................585
Table 3-363. Z1OTP_JTAGLOCK Register Field Descriptions................................................................................................586
Table 3-364. Z1OTP_BOOTCTRL Register Field Descriptions...............................................................................................587
Table 3-365. DCSM_Z2_OTP Registers..................................................................................................................................588
Table 3-366. DCSM_Z2_OTP Access Type Codes................................................................................................................. 588
Table 3-367. Z2OTP_LINKPOINTER1 Register Field Descriptions........................................................................................ 589
Table 3-368. Z2OTP_LINKPOINTER2 Register Field Descriptions........................................................................................ 590
Table 3-369. Z2OTP_LINKPOINTER3 Register Field Descriptions........................................................................................ 591
Table 3-370. Z2OTP_PSWDLOCK Register Field Descriptions..............................................................................................592
Table 3-371. Z2OTP_CRCLOCK Register Field Descriptions.................................................................................................593
Table 3-372. Z2OTP_JTAGLOCK Register Field Descriptions................................................................................................594
Table 3-373. Z2OTP_BOOTCTRL Register Field Descriptions...............................................................................................595
Table 3-374. CPUTIMER Registers to Driverlib Functions...................................................................................................... 596
Table 3-375. ASYSCTL Registers to Driverlib Functions.........................................................................................................596
Table 3-376. PIE Registers to Driverlib Functions................................................................................................................... 597
Table 3-377. SYSCTL Registers to Driverlib Functions........................................................................................................... 598
Table 3-378. NMI Registers to Driverlib Functions.................................................................................................................. 605
Table 3-379. XINT Registers to Driverlib Functions.................................................................................................................605
Table 3-380. DCSM Registers to Driverlib Functions.............................................................................................................. 606
Table 3-381. MEMCFG Registers to Driverlib Functions......................................................................................................... 608
Table 3-382. FLASH Registers to Driverlib Functions..............................................................................................................611
Table 4-1. ROM Memory..........................................................................................................................................................615
Table 4-2. Boot ROM Registers............................................................................................................................................... 615
Table 4-3. Boot ROM Sequence.............................................................................................................................................. 615
Table 4-4. Device Default Boot Modes for CPU1 ....................................................................................................................616
Table 4-5. All Available Boot Modes........................................................................................................................................ 616
Table 4-6. BOOTCTRL Register Bit Fields for CPU1 ............................................................................................................. 617
Table 4-7. BOOTCTRL Register Bit Fields for CPU2.............................................................................................................. 617
Table 4-8. Get Mode Decoding on CPU1 ............................................................................................................................... 619
Table 4-9. Get Mode Decoding on CPU2................................................................................................................................ 619
Table 4-10. Emulation Boot Options........................................................................................................................................ 620
Table 4-11. Boot ROM Reset Causes and Actions.................................................................................................................. 627
Table 4-12. Boot ROM Exceptions and Actions.......................................................................................................................628
Table 4-13. Entry Point Addresses for CPU1 and CPU2 ........................................................................................................ 629
Table 4-14. Wait Point Addresses for CPU1 ........................................................................................................................... 629
Table 4-15. Wait Point Addresses for CPU2............................................................................................................................ 629
Table 4-16. CPU1 Boot ROM Memory Map.............................................................................................................................630
Table 4-17. CPU2 Boot ROM Memory Map.............................................................................................................................630
Table 4-18. CLA Data ROM Memory Map............................................................................................................................... 630
Table 4-19. Reserved RAM and Flash Memory-Map for CPU1 ..............................................................................................631
Table 4-20. Reserved RAM and Flash Memory-Map for CPU2...............................................................................................631
Table 4-21. CLA Data ROM Tables..........................................................................................................................................632
Table 4-22. SPI 8-Bit Data Stream...........................................................................................................................................636
Table 4-23. I2C 8-Bit Data Stream...........................................................................................................................................640
Table 4-24. Parallel GPIO Boot 8-Bit Data Stream.................................................................................................................. 641
Table 4-25. Bit-Rate Value for Internal Oscillators................................................................................................................... 645
Table 4-26. CAN 8-Bit Data Stream.........................................................................................................................................646
Table 4-27. USB 8-Bit Data Stream......................................................................................................................................... 648

50 TMS320F2837xD Dual-Core Real-Time Microcontrollers SPRUHM8K – DECEMBER 2013 – REVISED MAY 2024
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Table 4-28. LSB/MSB Loading Sequence in 8-Bit Data Stream.............................................................................................. 649

Table 4-29. SCI Boot Options.................................................................................................................................................. 650
Table 4-30. CAN Boot Options.................................................................................................................................................650
Table 4-31. I2C Boot Options...................................................................................................................................................650
Table 4-32. USB Boot Options.................................................................................................................................................651
Table 4-33. RAM Boot Options................................................................................................................................................ 651
Table 4-34. Flash Boot Options............................................................................................................................................... 651
Table 4-35. Wait Boot Options................................................................................................................................................. 651
Table 4-36. SPI Boot Options.................................................................................................................................................. 651
Table 4-37. Parallel Boot Options............................................................................................................................................ 651
Table 4-38. Safe Copy Code Function.....................................................................................................................................652
Table 4-39. Safe CRC Calculation Function............................................................................................................................ 652
Table 4-40. C2TOC1IPC Commands Table............................................................................................................................. 653
Table 4-41. C1TOC2IPC Commands Table............................................................................................................................. 655
Table 4-42. CPU2 Error Command Values.............................................................................................................................. 658
Table 4-43. Boot Clock Sources.............................................................................................................................................. 658
Table 4-44. Clock State After Boot ROM................................................................................................................................. 658
Table 4-45. ROM Wait States.................................................................................................................................................. 659
Table 4-46. CPU1 Boot Status Address...................................................................................................................................659
Table 4-47. CPU1 Boot Status Bit Fields................................................................................................................................. 659
Table 4-48. CPU1 Boot Mode Status Address.........................................................................................................................660
Table 4-49. CPU1 Boot Mode Status Values........................................................................................................................... 660
Table 4-50. CPU2 Boot Status Address...................................................................................................................................661
Table 4-51. CPU2 Boot Status Bit Fields................................................................................................................................. 661
Table 4-52. CPU1 IPC NAK Status Bit Fields.......................................................................................................................... 661
Table 4-53. CPU2 IPC NAK Status Bit Fields.......................................................................................................................... 662
Table 4-54. Boot ROM Version Information for CPU1 and CPU2 ...........................................................................................662
Table 5-1. DMA Trigger Source Options.................................................................................................................................. 669
Table 5-2. BURSTSIZE versus DATASIZE Behavior............................................................................................................... 673
Table 5-3. DMA Base Address Table....................................................................................................................................... 682
Table 5-4. DMA_REGS Registers............................................................................................................................................683
Table 5-5. DMA_REGS Access Type Codes........................................................................................................................... 683
Table 5-6. DMACTRL Register Field Descriptions...................................................................................................................684
Table 5-7. DEBUGCTRL Register Field Descriptions..............................................................................................................685
Table 5-8. PRIORITYCTRL1 Register Field Descriptions........................................................................................................686
Table 5-9. PRIORITYSTAT Register Field Descriptions.......................................................................................................... 687
Table 5-10. DMA_CH_REGS Registers.................................................................................................................................. 688
Table 5-11. DMA_CH_REGS Access Type Codes.................................................................................................................. 688
Table 5-12. MODE Register Field Descriptions....................................................................................................................... 689
Table 5-13. CONTROL Register Field Descriptions................................................................................................................ 691
Table 5-14. BURST_SIZE Register Field Descriptions............................................................................................................693
Table 5-15. BURST_COUNT Register Field Descriptions....................................................................................................... 694
Table 5-16. SRC_BURST_STEP Register Field Descriptions.................................................................................................695
Table 5-17. DST_BURST_STEP Register Field Descriptions................................................................................................. 696
Table 5-18. TRANSFER_SIZE Register Field Descriptions.....................................................................................................697
Table 5-19. TRANSFER_COUNT Register Field Descriptions................................................................................................698
Table 5-20. SRC_TRANSFER_STEP Register Field Descriptions..........................................................................................699
Table 5-21. DST_TRANSFER_STEP Register Field Descriptions.......................................................................................... 700
Table 5-22. SRC_WRAP_SIZE Register Field Descriptions....................................................................................................701
Table 5-23. SRC_WRAP_COUNT Register Field Descriptions...............................................................................................702
Table 5-24. SRC_WRAP_STEP Register Field Descriptions.................................................................................................. 703
Table 5-25. DST_WRAP_SIZE Register Field Descriptions.................................................................................................... 704
Table 5-26. DST_WRAP_COUNT Register Field Descriptions............................................................................................... 705
Table 5-27. DST_WRAP_STEP Register Field Descriptions...................................................................................................706
Table 5-28. SRC_BEG_ADDR_SHADOW Register Field Descriptions.................................................................................. 707
Table 5-29. SRC_ADDR_SHADOW Register Field Descriptions............................................................................................ 708
Table 5-30. SRC_BEG_ADDR_ACTIVE Register Field Descriptions......................................................................................709
Table 5-31. SRC_ADDR_ACTIVE Register Field Descriptions............................................................................................... 710
Table 5-32. DST_BEG_ADDR_SHADOW Register Field Descriptions................................................................................... 711
Table 5-33. DST_ADDR_SHADOW Register Field Descriptions............................................................................................ 712
Table 5-34. DST_BEG_ADDR_ACTIVE Register Field Descriptions...................................................................................... 713

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Table 5-35. DST_ADDR_ACTIVE Register Field Descriptions................................................................................................714

Table 5-36. DMA Registers to Driverlib Functions................................................................................................................... 714
Table 6-1. Configuration Options............................................................................................................................................. 723
Table 6-2. Write Followed by Read - Read Occurs First..........................................................................................................733
Table 6-3. Write Followed by Read - Write Occurs First.......................................................................................................... 733
Table 6-4. ADC to CLA Early Interrupt Response....................................................................................................................736
Table 6-5. Operand Nomenclature...........................................................................................................................................739
Table 6-6. INSTRUCTION dest, source1, source2 Short Description..................................................................................... 740
Table 6-7. Addressing Modes.................................................................................................................................................. 741
Table 6-8. Shift Field Encoding................................................................................................................................................ 741
Table 6-9. Operand Encoding.................................................................................................................................................. 742
Table 6-10. Condition Field Encoding...................................................................................................................................... 742
Table 6-11. Pipeline Activity for MBCNDD, Branch Not Taken.................................................................................................760
Table 6-12. Pipeline Activity for MBCNDD, Branch Taken.......................................................................................................760
Table 6-13. Pipeline Activity for MCCNDD, Call Not Taken..................................................................................................... 765
Table 6-14. Pipeline Activity for MCCNDD, Call Taken............................................................................................................766
Table 6-15. Pipeline Activity for MMOV16 MARx, MRa , #16I................................................................................................. 806
Table 6-16. Pipeline Activity for MMOV16 MAR0/MAR1, mem16........................................................................................... 809
Table 6-17. Pipeline Activity for MMOVI16 MAR0/MAR1, #16I............................................................................................... 827
Table 6-18. Pipeline Activity for MRCNDD, Return Not Taken.................................................................................................851
Table 6-19. Pipeline Activity for MRCNDD, Return Taken....................................................................................................... 851
Table 6-20. Pipeline Activity for MSTOP.................................................................................................................................. 854
Table 6-21. CLA Base Address Table...................................................................................................................................... 870
Table 6-22. CLA_REGS Registers...........................................................................................................................................871
Table 6-23. CLA_REGS Access Type Codes.......................................................................................................................... 871
Table 6-24. MVECT1 Register Field Descriptions................................................................................................................... 873
Table 6-25. MVECT2 Register Field Descriptions................................................................................................................... 874
Table 6-26. MVECT3 Register Field Descriptions................................................................................................................... 875
Table 6-27. MVECT4 Register Field Descriptions................................................................................................................... 876
Table 6-28. MVECT5 Register Field Descriptions................................................................................................................... 877
Table 6-29. MVECT6 Register Field Descriptions................................................................................................................... 878
Table 6-30. MVECT7 Register Field Descriptions................................................................................................................... 879
Table 6-31. MVECT8 Register Field Descriptions................................................................................................................... 880
Table 6-32. MCTL Register Field Descriptions........................................................................................................................ 881
Table 6-33. MIFR Register Field Descriptions......................................................................................................................... 882
Table 6-34. MIOVF Register Field Descriptions.......................................................................................................................886
Table 6-35. MIFRC Register Field Descriptions.......................................................................................................................889
Table 6-36. MICLR Register Field Descriptions.......................................................................................................................891
Table 6-37. MICLROVF Register Field Descriptions............................................................................................................... 893
Table 6-38. MIER Register Field Descriptions......................................................................................................................... 895
Table 6-39. MIRUN Register Field Descriptions...................................................................................................................... 898
Table 6-40. _MPC Register Field Descriptions........................................................................................................................ 900
Table 6-41. _MAR0 Register Field Descriptions...................................................................................................................... 901
Table 6-42. _MAR1 Register Field Descriptions...................................................................................................................... 902
Table 6-43. _MSTF Register Field Descriptions...................................................................................................................... 903
Table 6-44. _MR0 Register Field Descriptions........................................................................................................................ 906
Table 6-45. _MR1 Register Field Descriptions........................................................................................................................ 907
Table 6-46. _MR2 Register Field Descriptions........................................................................................................................ 908
Table 6-47. _MR3 Register Field Descriptions........................................................................................................................ 909
Table 6-48. CLA_SOFTINT_REGS Registers......................................................................................................................... 910
Table 6-49. CLA_SOFTINT_REGS Access Type Codes.........................................................................................................910
Table 6-50. SOFTINTEN Register Field Descriptions.............................................................................................................. 911
Table 6-51. SOFTINTFRC Register Field Descriptions........................................................................................................... 913
Table 6-52. CLA Registers to Driverlib Functions.................................................................................................................... 914
Table 7-1. IPC Message RAM Read/Write Access.................................................................................................................. 918
Table 7-2. IPC Command Registers........................................................................................................................................ 918
Table 7-3. IPC Base Addresses...............................................................................................................................................920
Table 7-4. IPC_REGS_CPU1 Registers.................................................................................................................................. 921
Table 7-5. IPC_REGS_CPU1 Access Type Codes................................................................................................................. 921
Table 7-6. IPCACK Register Field Descriptions.......................................................................................................................922
Table 7-7. IPCSTS Register Field Descriptions....................................................................................................................... 925

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Table 7-8. IPCSET Register Field Descriptions....................................................................................................................... 929

Table 7-9. IPCCLR Register Field Descriptions.......................................................................................................................932
Table 7-10. IPCFLG Register Field Descriptions..................................................................................................................... 937
Table 7-11. IPCCOUNTERL Register Field Descriptions.........................................................................................................941
Table 7-12. IPCCOUNTERH Register Field Descriptions........................................................................................................942
Table 7-13. IPCSENDCOM Register Field Descriptions..........................................................................................................943
Table 7-14. IPCSENDADDR Register Field Descriptions........................................................................................................944
Table 7-15. IPCSENDDATA Register Field Descriptions......................................................................................................... 945
Table 7-16. IPCREMOTEREPLY Register Field Descriptions................................................................................................. 946
Table 7-17. IPCRECVCOM Register Field Descriptions..........................................................................................................947
Table 7-18. IPCRECVADDR Register Field Descriptions........................................................................................................ 948
Table 7-19. IPCRECVDATA Register Field Descriptions......................................................................................................... 949
Table 7-20. IPCLOCALREPLY Register Field Descriptions.....................................................................................................950
Table 7-21. IPCBOOTSTS Register Field Descriptions...........................................................................................................951
Table 7-22. IPCBOOTMODE Register Field Descriptions....................................................................................................... 952
Table 7-23. IPC_REGS_CPU2 Registers................................................................................................................................ 953
Table 7-24. IPC_REGS_CPU2 Access Type Codes............................................................................................................... 953
Table 7-25. IPCACK Register Field Descriptions.....................................................................................................................954
Table 7-26. IPCSTS Register Field Descriptions..................................................................................................................... 957
Table 7-27. IPCSET Register Field Descriptions..................................................................................................................... 961
Table 7-28. IPCCLR Register Field Descriptions.....................................................................................................................964
Table 7-29. IPCFLG Register Field Descriptions..................................................................................................................... 969
Table 7-30. IPCCOUNTERL Register Field Descriptions........................................................................................................ 973
Table 7-31. IPCCOUNTERH Register Field Descriptions........................................................................................................974
Table 7-32. IPCRECVCOM Register Field Descriptions..........................................................................................................975
Table 7-33. IPCRECVADDR Register Field Descriptions........................................................................................................ 976
Table 7-34. IPCRECVDATA Register Field Descriptions......................................................................................................... 977
Table 7-35. IPCLOCALREPLY Register Field Descriptions.....................................................................................................978
Table 7-36. IPCSENDCOM Register Field Descriptions..........................................................................................................979
Table 7-37. IPCSENDADDR Register Field Descriptions........................................................................................................980
Table 7-38. IPCSENDDATA Register Field Descriptions......................................................................................................... 981
Table 7-39. IPCREMOTEREPLY Register Field Descriptions................................................................................................. 982
Table 7-40. IPCBOOTSTS Register Field Descriptions...........................................................................................................983
Table 7-41. IPCBOOTMODE Register Field Descriptions....................................................................................................... 984
Table 7-42. IPC Registers to Driverlib Functions..................................................................................................................... 984
Table 8-1. Sampling Period......................................................................................................................................................992
Table 8-2. Sampling Frequency............................................................................................................................................... 992
Table 8-3. Case 1: Three-Sample Sampling-Window Width....................................................................................................993
Table 8-4. Case 2: Six-Sample Sampling-Window Width........................................................................................................ 993
Table 8-5. USB I/O Signal Muxing........................................................................................................................................... 995
Table 8-6. GPIO Configuration for High-Speed SPI.................................................................................................................995
Table 8-7. GPIO Muxed Pins................................................................................................................................................... 996
Table 8-8. GPIO and Peripheral Muxing................................................................................................................................ 1002
Table 8-9. Peripheral Muxing (Multiple Pins Assigned)......................................................................................................... 1003
Table 8-10. Specific versus Generic Terminology for Registers............................................................................................ 1006
Table 8-11. GPIO Base Address Table.................................................................................................................................. 1006
Table 8-12. GPIO_CTRL_REGS Registers........................................................................................................................... 1007
Table 8-13. GPIO_CTRL_REGS Access Type Codes...........................................................................................................1009
Table 8-14. GPACTRL Register Field Descriptions................................................................................................................1011
Table 8-15. GPAQSEL1 Register Field Descriptions............................................................................................................. 1012
Table 8-16. GPAQSEL2 Register Field Descriptions............................................................................................................. 1014
Table 8-17. GPAMUX1 Register Field Descriptions...............................................................................................................1016
Table 8-18. GPAMUX2 Register Field Descriptions...............................................................................................................1018
Table 8-19. GPADIR Register Field Descriptions...................................................................................................................1020
Table 8-20. GPAPUD Register Field Descriptions................................................................................................................. 1022
Table 8-21. GPAINV Register Field Descriptions...................................................................................................................1024
Table 8-22. GPAODR Register Field Descriptions.................................................................................................................1026
Table 8-23. GPAGMUX1 Register Field Descriptions............................................................................................................ 1028
Table 8-24. GPAGMUX2 Register Field Descriptions............................................................................................................ 1029
Table 8-25. GPACSEL1 Register Field Descriptions............................................................................................................. 1030
Table 8-26. GPACSEL2 Register Field Descriptions............................................................................................................. 1031

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Table 8-27. GPACSEL3 Register Field Descriptions............................................................................................................. 1032

Table 8-28. GPACSEL4 Register Field Descriptions............................................................................................................. 1033
Table 8-29. GPALOCK Register Field Descriptions............................................................................................................... 1034
Table 8-30. GPACR Register Field Descriptions....................................................................................................................1036
Table 8-31. GPBCTRL Register Field Descriptions............................................................................................................... 1038
Table 8-32. GPBQSEL1 Register Field Descriptions.............................................................................................................1039
Table 8-33. GPBQSEL2 Register Field Descriptions.............................................................................................................1041
Table 8-34. GPBMUX1 Register Field Descriptions.............................................................................................................. 1043
Table 8-35. GPBMUX2 Register Field Descriptions.............................................................................................................. 1045
Table 8-36. GPBDIR Register Field Descriptions.................................................................................................................. 1047
Table 8-37. GPBPUD Register Field Descriptions.................................................................................................................1049
Table 8-38. GPBINV Register Field Descriptions.................................................................................................................. 1051
Table 8-39. GPBODR Register Field Descriptions................................................................................................................ 1053
Table 8-40. GPBAMSEL Register Field Descriptions............................................................................................................ 1055
Table 8-41. GPBGMUX1 Register Field Descriptions............................................................................................................1057
Table 8-42. GPBGMUX2 Register Field Descriptions............................................................................................................1058
Table 8-43. GPBCSEL1 Register Field Descriptions............................................................................................................. 1059
Table 8-44. GPBCSEL2 Register Field Descriptions............................................................................................................. 1060
Table 8-45. GPBCSEL3 Register Field Descriptions............................................................................................................. 1061
Table 8-46. GPBCSEL4 Register Field Descriptions............................................................................................................. 1062
Table 8-47. GPBLOCK Register Field Descriptions...............................................................................................................1063
Table 8-48. GPBCR Register Field Descriptions................................................................................................................... 1065
Table 8-49. GPCCTRL Register Field Descriptions...............................................................................................................1067
Table 8-50. GPCQSEL1 Register Field Descriptions.............................................................................................................1068
Table 8-51. GPCQSEL2 Register Field Descriptions.............................................................................................................1070
Table 8-52. GPCMUX1 Register Field Descriptions.............................................................................................................. 1072
Table 8-53. GPCMUX2 Register Field Descriptions.............................................................................................................. 1074
Table 8-54. GPCDIR Register Field Descriptions.................................................................................................................. 1076
Table 8-55. GPCPUD Register Field Descriptions.................................................................................................................1078
Table 8-56. GPCINV Register Field Descriptions.................................................................................................................. 1080
Table 8-57. GPCODR Register Field Descriptions................................................................................................................ 1082
Table 8-58. GPCGMUX1 Register Field Descriptions........................................................................................................... 1084
Table 8-59. GPCGMUX2 Register Field Descriptions........................................................................................................... 1085
Table 8-60. GPCCSEL1 Register Field Descriptions.............................................................................................................1086
Table 8-61. GPCCSEL2 Register Field Descriptions.............................................................................................................1087
Table 8-62. GPCCSEL3 Register Field Descriptions.............................................................................................................1088
Table 8-63. GPCCSEL4 Register Field Descriptions.............................................................................................................1089
Table 8-64. GPCLOCK Register Field Descriptions.............................................................................................................. 1090
Table 8-65. GPCCR Register Field Descriptions................................................................................................................... 1092
Table 8-66. GPDCTRL Register Field Descriptions...............................................................................................................1094
Table 8-67. GPDQSEL1 Register Field Descriptions.............................................................................................................1095
Table 8-68. GPDQSEL2 Register Field Descriptions.............................................................................................................1097
Table 8-69. GPDMUX1 Register Field Descriptions.............................................................................................................. 1099
Table 8-70. GPDMUX2 Register Field Descriptions...............................................................................................................1101
Table 8-71. GPDDIR Register Field Descriptions.................................................................................................................. 1103
Table 8-72. GPDPUD Register Field Descriptions................................................................................................................. 1105
Table 8-73. GPDINV Register Field Descriptions...................................................................................................................1107
Table 8-74. GPDODR Register Field Descriptions.................................................................................................................1109
Table 8-75. GPDGMUX1 Register Field Descriptions............................................................................................................ 1111
Table 8-76. GPDGMUX2 Register Field Descriptions............................................................................................................ 1113
Table 8-77. GPDCSEL1 Register Field Descriptions............................................................................................................. 1115
Table 8-78. GPDCSEL2 Register Field Descriptions............................................................................................................. 1116
Table 8-79. GPDCSEL3 Register Field Descriptions............................................................................................................. 1117
Table 8-80. GPDCSEL4 Register Field Descriptions............................................................................................................. 1118
Table 8-81. GPDLOCK Register Field Descriptions............................................................................................................... 1119
Table 8-82. GPDCR Register Field Descriptions................................................................................................................... 1121
Table 8-83. GPECTRL Register Field Descriptions............................................................................................................... 1123
Table 8-84. GPEQSEL1 Register Field Descriptions............................................................................................................. 1124
Table 8-85. GPEQSEL2 Register Field Descriptions............................................................................................................. 1126
Table 8-86. GPEMUX1 Register Field Descriptions...............................................................................................................1128
Table 8-87. GPEMUX2 Register Field Descriptions...............................................................................................................1130

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Table 8-88. GPEDIR Register Field Descriptions...................................................................................................................1132

Table 8-89. GPEPUD Register Field Descriptions................................................................................................................. 1134
Table 8-90. GPEINV Register Field Descriptions...................................................................................................................1136
Table 8-91. GPEODR Register Field Descriptions.................................................................................................................1138
Table 8-92. GPEGMUX1 Register Field Descriptions............................................................................................................ 1140
Table 8-93. GPEGMUX2 Register Field Descriptions............................................................................................................ 1142
Table 8-94. GPECSEL1 Register Field Descriptions............................................................................................................. 1144
Table 8-95. GPECSEL2 Register Field Descriptions............................................................................................................. 1145
Table 8-96. GPECSEL3 Register Field Descriptions............................................................................................................. 1146
Table 8-97. GPECSEL4 Register Field Descriptions............................................................................................................. 1147
Table 8-98. GPELOCK Register Field Descriptions............................................................................................................... 1148
Table 8-99. GPECR Register Field Descriptions....................................................................................................................1150
Table 8-100. GPFCTRL Register Field Descriptions..............................................................................................................1152
Table 8-101. GPFQSEL1 Register Field Descriptions........................................................................................................... 1153
Table 8-102. GPFMUX1 Register Field Descriptions............................................................................................................. 1155
Table 8-103. GPFDIR Register Field Descriptions.................................................................................................................1157
Table 8-104. GPFPUD Register Field Descriptions............................................................................................................... 1159
Table 8-105. GPFINV Register Field Descriptions................................................................................................................. 1161
Table 8-106. GPFODR Register Field Descriptions............................................................................................................... 1163
Table 8-107. GPFGMUX1 Register Field Descriptions.......................................................................................................... 1165
Table 8-108. GPFCSEL1 Register Field Descriptions............................................................................................................1167
Table 8-109. GPFCSEL2 Register Field Descriptions............................................................................................................1168
Table 8-110. GPFLOCK Register Field Descriptions............................................................................................................. 1169
Table 8-111. GPFCR Register Field Descriptions.................................................................................................................. 1171
Table 8-112. GPIO_DATA_REGS Registers.......................................................................................................................... 1173
Table 8-113. GPIO_DATA_REGS Access Type Codes..........................................................................................................1173
Table 8-114. GPADAT Register Field Descriptions................................................................................................................ 1175
Table 8-115. GPASET Register Field Descriptions................................................................................................................ 1177
Table 8-116. GPACLEAR Register Field Descriptions........................................................................................................... 1179
Table 8-117. GPATOGGLE Register Field Descriptions.........................................................................................................1181
Table 8-118. GPBDAT Register Field Descriptions................................................................................................................ 1183
Table 8-119. GPBSET Register Field Descriptions................................................................................................................ 1185
Table 8-120. GPBCLEAR Register Field Descriptions...........................................................................................................1187
Table 8-121. GPBTOGGLE Register Field Descriptions........................................................................................................1189
Table 8-122. GPCDAT Register Field Descriptions................................................................................................................1191
Table 8-123. GPCSET Register Field Descriptions................................................................................................................1193
Table 8-124. GPCCLEAR Register Field Descriptions...........................................................................................................1195
Table 8-125. GPCTOGGLE Register Field Descriptions........................................................................................................1197
Table 8-126. GPDDAT Register Field Descriptions................................................................................................................1199
Table 8-127. GPDSET Register Field Descriptions............................................................................................................... 1201
Table 8-128. GPDCLEAR Register Field Descriptions.......................................................................................................... 1203
Table 8-129. GPDTOGGLE Register Field Descriptions....................................................................................................... 1205
Table 8-130. GPEDAT Register Field Descriptions................................................................................................................1207
Table 8-131. GPESET Register Field Descriptions............................................................................................................... 1209
Table 8-132. GPECLEAR Register Field Descriptions...........................................................................................................1211
Table 8-133. GPETOGGLE Register Field Descriptions........................................................................................................1213
Table 8-134. GPFDAT Register Field Descriptions................................................................................................................1215
Table 8-135. GPFSET Register Field Descriptions................................................................................................................1217
Table 8-136. GPFCLEAR Register Field Descriptions...........................................................................................................1219
Table 8-137. GPFTOGGLE Register Field Descriptions........................................................................................................1221
Table 8-138. GPIO Registers to Driverlib Functions.............................................................................................................. 1222
Table 9-1. Input X-BAR Destinations..................................................................................................................................... 1232
Table 9-2. EPWM X-BAR Mux Configuration Table............................................................................................................... 1234
Table 9-3. CLB X-BAR Mux Configuration Table................................................................................................................... 1237
Table 9-4. Output X-BAR Mux Configuration Table............................................................................................................... 1239
Table 9-5. XBAR Base Address Table................................................................................................................................... 1241
Table 9-6. INPUT_XBAR_REGS Registers........................................................................................................................... 1242
Table 9-7. INPUT_XBAR_REGS Access Type Codes.......................................................................................................... 1242
Table 9-8. INPUT1SELECT Register Field Descriptions....................................................................................................... 1243
Table 9-9. INPUT2SELECT Register Field Descriptions....................................................................................................... 1244
Table 9-10. INPUT3SELECT Register Field Descriptions..................................................................................................... 1245

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Table 9-11. INPUT4SELECT Register Field Descriptions......................................................................................................1246

Table 9-12. INPUT5SELECT Register Field Descriptions..................................................................................................... 1247
Table 9-13. INPUT6SELECT Register Field Descriptions..................................................................................................... 1248
Table 9-14. INPUT7SELECT Register Field Descriptions..................................................................................................... 1249
Table 9-15. INPUT8SELECT Register Field Descriptions..................................................................................................... 1250
Table 9-16. INPUT9SELECT Register Field Descriptions..................................................................................................... 1251
Table 9-17. INPUT10SELECT Register Field Descriptions................................................................................................... 1252
Table 9-18. INPUT11SELECT Register Field Descriptions....................................................................................................1253
Table 9-19. INPUT12SELECT Register Field Descriptions................................................................................................... 1254
Table 9-20. INPUT13SELECT Register Field Descriptions................................................................................................... 1255
Table 9-21. INPUT14SELECT Register Field Descriptions................................................................................................... 1256
Table 9-22. INPUTSELECTLOCK Register Field Descriptions............................................................................................. 1257
Table 9-23. XBAR_REGS Registers......................................................................................................................................1259
Table 9-24. XBAR_REGS Access Type Codes..................................................................................................................... 1259
Table 9-25. XBARFLG1 Register Field Descriptions............................................................................................................. 1260
Table 9-26. XBARFLG2 Register Field Descriptions............................................................................................................. 1262
Table 9-27. XBARFLG3 Register Field Descriptions............................................................................................................. 1264
Table 9-28. XBARCLR1 Register Field Descriptions............................................................................................................. 1266
Table 9-29. XBARCLR2 Register Field Descriptions............................................................................................................. 1268
Table 9-30. XBARCLR3 Register Field Descriptions............................................................................................................. 1270
Table 9-31. EPWM_XBAR_REGS Registers.........................................................................................................................1272
Table 9-32. EPWM_XBAR_REGS Access Type Codes........................................................................................................ 1272
Table 9-33. TRIP4MUX0TO15CFG Register Field Descriptions........................................................................................... 1274
Table 9-34. TRIP4MUX16TO31CFG Register Field Descriptions......................................................................................... 1277
Table 9-35. TRIP5MUX0TO15CFG Register Field Descriptions........................................................................................... 1280
Table 9-36. TRIP5MUX16TO31CFG Register Field Descriptions......................................................................................... 1283
Table 9-37. TRIP7MUX0TO15CFG Register Field Descriptions........................................................................................... 1286
Table 9-38. TRIP7MUX16TO31CFG Register Field Descriptions......................................................................................... 1289
Table 9-39. TRIP8MUX0TO15CFG Register Field Descriptions........................................................................................... 1292
Table 9-40. TRIP8MUX16TO31CFG Register Field Descriptions......................................................................................... 1295
Table 9-41. TRIP9MUX0TO15CFG Register Field Descriptions........................................................................................... 1298
Table 9-42. TRIP9MUX16TO31CFG Register Field Descriptions......................................................................................... 1301
Table 9-43. TRIP10MUX0TO15CFG Register Field Descriptions......................................................................................... 1304
Table 9-44. TRIP10MUX16TO31CFG Register Field Descriptions....................................................................................... 1307
Table 9-45. TRIP11MUX0TO15CFG Register Field Descriptions..........................................................................................1310
Table 9-46. TRIP11MUX16TO31CFG Register Field Descriptions........................................................................................1313
Table 9-47. TRIP12MUX0TO15CFG Register Field Descriptions......................................................................................... 1316
Table 9-48. TRIP12MUX16TO31CFG Register Field Descriptions....................................................................................... 1319
Table 9-49. TRIP4MUXENABLE Register Field Descriptions................................................................................................1322
Table 9-50. TRIP5MUXENABLE Register Field Descriptions................................................................................................1327
Table 9-51. TRIP7MUXENABLE Register Field Descriptions................................................................................................1332
Table 9-52. TRIP8MUXENABLE Register Field Descriptions................................................................................................1337
Table 9-53. TRIP9MUXENABLE Register Field Descriptions................................................................................................1342
Table 9-54. TRIP10MUXENABLE Register Field Descriptions..............................................................................................1347
Table 9-55. TRIP11MUXENABLE Register Field Descriptions.............................................................................................. 1352
Table 9-56. TRIP12MUXENABLE Register Field Descriptions..............................................................................................1357
Table 9-57. TRIPOUTINV Register Field Descriptions.......................................................................................................... 1362
Table 9-58. TRIPLOCK Register Field Descriptions.............................................................................................................. 1364
Table 9-59. CLB_XBAR_REGS Registers.............................................................................................................................1365
Table 9-60. CLB_XBAR_REGS Access Type Codes............................................................................................................ 1365
Table 9-61. AUXSIG0MUX0TO15CFG Register Field Descriptions...................................................................................... 1367
Table 9-62. AUXSIG0MUX16TO31CFG Register Field Descriptions.................................................................................... 1370
Table 9-63. AUXSIG1MUX0TO15CFG Register Field Descriptions...................................................................................... 1373
Table 9-64. AUXSIG1MUX16TO31CFG Register Field Descriptions.................................................................................... 1376
Table 9-65. AUXSIG2MUX0TO15CFG Register Field Descriptions...................................................................................... 1379
Table 9-66. AUXSIG2MUX16TO31CFG Register Field Descriptions.................................................................................... 1382
Table 9-67. AUXSIG3MUX0TO15CFG Register Field Descriptions...................................................................................... 1385
Table 9-68. AUXSIG3MUX16TO31CFG Register Field Descriptions.................................................................................... 1388
Table 9-69. AUXSIG4MUX0TO15CFG Register Field Descriptions...................................................................................... 1391
Table 9-70. AUXSIG4MUX16TO31CFG Register Field Descriptions.................................................................................... 1394
Table 9-71. AUXSIG5MUX0TO15CFG Register Field Descriptions...................................................................................... 1397

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Table 9-72. AUXSIG5MUX16TO31CFG Register Field Descriptions.................................................................................... 1400

Table 9-73. AUXSIG6MUX0TO15CFG Register Field Descriptions...................................................................................... 1403
Table 9-74. AUXSIG6MUX16TO31CFG Register Field Descriptions.................................................................................... 1406
Table 9-75. AUXSIG7MUX0TO15CFG Register Field Descriptions...................................................................................... 1409
Table 9-76. AUXSIG7MUX16TO31CFG Register Field Descriptions.................................................................................... 1412
Table 9-77. AUXSIG0MUXENABLE Register Field Descriptions.......................................................................................... 1415
Table 9-78. AUXSIG1MUXENABLE Register Field Descriptions.......................................................................................... 1420
Table 9-79. AUXSIG2MUXENABLE Register Field Descriptions.......................................................................................... 1425
Table 9-80. AUXSIG3MUXENABLE Register Field Descriptions.......................................................................................... 1430
Table 9-81. AUXSIG4MUXENABLE Register Field Descriptions.......................................................................................... 1435
Table 9-82. AUXSIG5MUXENABLE Register Field Descriptions.......................................................................................... 1440
Table 9-83. AUXSIG6MUXENABLE Register Field Descriptions.......................................................................................... 1445
Table 9-84. AUXSIG7MUXENABLE Register Field Descriptions.......................................................................................... 1450
Table 9-85. AUXSIGOUTINV Register Field Descriptions.....................................................................................................1455
Table 9-86. AUXSIGLOCK Register Field Descriptions.........................................................................................................1457
Table 9-87. OUTPUT_XBAR_REGS Registers..................................................................................................................... 1458
Table 9-88. OUTPUT_XBAR_REGS Access Type Codes.................................................................................................... 1458
Table 9-89. OUTPUT1MUX0TO15CFG Register Field Descriptions.....................................................................................1460
Table 9-90. OUTPUT1MUX16TO31CFG Register Field Descriptions...................................................................................1463
Table 9-91. OUTPUT2MUX0TO15CFG Register Field Descriptions.....................................................................................1466
Table 9-92. OUTPUT2MUX16TO31CFG Register Field Descriptions...................................................................................1469
Table 9-93. OUTPUT3MUX0TO15CFG Register Field Descriptions.....................................................................................1472
Table 9-94. OUTPUT3MUX16TO31CFG Register Field Descriptions...................................................................................1475
Table 9-95. OUTPUT4MUX0TO15CFG Register Field Descriptions.....................................................................................1478
Table 9-96. OUTPUT4MUX16TO31CFG Register Field Descriptions...................................................................................1481
Table 9-97. OUTPUT5MUX0TO15CFG Register Field Descriptions.....................................................................................1484
Table 9-98. OUTPUT5MUX16TO31CFG Register Field Descriptions...................................................................................1487
Table 9-99. OUTPUT6MUX0TO15CFG Register Field Descriptions.....................................................................................1490
Table 9-100. OUTPUT6MUX16TO31CFG Register Field Descriptions.................................................................................1493
Table 9-101. OUTPUT7MUX0TO15CFG Register Field Descriptions...................................................................................1496
Table 9-102. OUTPUT7MUX16TO31CFG Register Field Descriptions.................................................................................1499
Table 9-103. OUTPUT8MUX0TO15CFG Register Field Descriptions...................................................................................1502
Table 9-104. OUTPUT8MUX16TO31CFG Register Field Descriptions.................................................................................1505
Table 9-105. OUTPUT1MUXENABLE Register Field Descriptions....................................................................................... 1508
Table 9-106. OUTPUT2MUXENABLE Register Field Descriptions....................................................................................... 1513
Table 9-107. OUTPUT3MUXENABLE Register Field Descriptions....................................................................................... 1518
Table 9-108. OUTPUT4MUXENABLE Register Field Descriptions....................................................................................... 1523
Table 9-109. OUTPUT5MUXENABLE Register Field Descriptions....................................................................................... 1528
Table 9-110. OUTPUT6MUXENABLE Register Field Descriptions....................................................................................... 1533
Table 9-111. OUTPUT7MUXENABLE Register Field Descriptions........................................................................................1538
Table 9-112. OUTPUT8MUXENABLE Register Field Descriptions....................................................................................... 1543
Table 9-113. OUTPUTLATCH Register Field Descriptions.................................................................................................... 1548
Table 9-114. OUTPUTLATCHCLR Register Field Descriptions.............................................................................................1550
Table 9-115. OUTPUTLATCHFRC Register Field Descriptions.............................................................................................1552
Table 9-116. OUTPUTLATCHENABLE Register Field Descriptions......................................................................................1554
Table 9-117. OUTPUTINV Register Field Descriptions..........................................................................................................1556
Table 9-118. OUTPUTLOCK Register Field Descriptions......................................................................................................1558
Table 9-119. INPUTXBAR Registers to Driverlib Functions...................................................................................................1559
Table 9-120. XBAR Registers to Driverlib Functions............................................................................................................. 1559
Table 9-121. EPWMXBAR Registers to Driverlib Functions.................................................................................................. 1560
Table 9-122. CLBXBAR Registers to Driverlib Functions...................................................................................................... 1561
Table 9-123. OUTPUTXBAR Registers to Driverlib Functions.............................................................................................. 1562
Table 10-1. Analog Signal Descriptions................................................................................................................................. 1570
Table 10-2. Reference Summary........................................................................................................................................... 1570
Table 10-3. Analog Subsystem Base Address Table............................................................................................................. 1571
Table 10-4. ANALOG_SUBSYS_REGS Registers................................................................................................................ 1572
Table 10-5. ANALOG_SUBSYS_REGS Access Type Codes............................................................................................... 1572
Table 10-6. INTOSC1TRIM Register Field Descriptions........................................................................................................1573
Table 10-7. INTOSC2TRIM Register Field Descriptions........................................................................................................1574
Table 10-8. TSNSCTL Register Field Descriptions................................................................................................................1575
Table 10-9. LOCK Register Field Descriptions...................................................................................................................... 1576

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Table 10-10. ANAREFTRIMA Register Field Descriptions.................................................................................................... 1578

Table 10-11. ANAREFTRIMB Register Field Descriptions.....................................................................................................1579
Table 10-12. ANAREFTRIMC Register Field Descriptions.................................................................................................... 1580
Table 10-13. ANAREFTRIMD Register Field Descriptions.................................................................................................... 1581
Table 11-1. ADC Options and Configuration Levels...............................................................................................................1586
Table 11-2. Analog to 12-bit Digital Formulas........................................................................................................................ 1588
Table 11-3. Analog to 16-bit Digital Formulas........................................................................................................................ 1588
Table 11-4. 12-Bit Digital-to-Analog Formulas....................................................................................................................... 1589
Table 11-5. 16-Bit Digital-to-Analog Formulas....................................................................................................................... 1589
Table 11-6. Channel Selection of Input Pins.......................................................................................................................... 1593
Table 11-7. Example Requirements for Multiple Signal Sampling......................................................................................... 1595
Table 11-8. Example Connections for Multiple Signal Sampling............................................................................................1595
Table 11-9. DETECTCFG Settings........................................................................................................................................ 1607
Table 11-10. ADC Calibration Functions in OTP.................................................................................................................... 1611
Table 11-11. ADC Timing Parameter Descriptions.................................................................................................................1612
Table 11-12. ADC Timings in 12-bit Mode............................................................................................................................. 1617
Table 11-13. ADC Timings in 16-bit Mode............................................................................................................................. 1617
Table 11-14. ADC Base Address Table..................................................................................................................................1630
Table 11-15. ADC_RESULT_REGS Registers...................................................................................................................... 1631
Table 11-16. ADC_RESULT_REGS Access Type Codes......................................................................................................1631
Table 11-17. ADCRESULT0 Register Field Descriptions.......................................................................................................1632
Table 11-18. ADCRESULT1 Register Field Descriptions.......................................................................................................1633
Table 11-19. ADCRESULT2 Register Field Descriptions.......................................................................................................1634
Table 11-20. ADCRESULT3 Register Field Descriptions.......................................................................................................1635
Table 11-21. ADCRESULT4 Register Field Descriptions.......................................................................................................1636
Table 11-22. ADCRESULT5 Register Field Descriptions.......................................................................................................1637
Table 11-23. ADCRESULT6 Register Field Descriptions.......................................................................................................1638
Table 11-24. ADCRESULT7 Register Field Descriptions.......................................................................................................1639
Table 11-25. ADCRESULT8 Register Field Descriptions.......................................................................................................1640
Table 11-26. ADCRESULT9 Register Field Descriptions.......................................................................................................1641
Table 11-27. ADCRESULT10 Register Field Descriptions.....................................................................................................1642
Table 11-28. ADCRESULT11 Register Field Descriptions..................................................................................................... 1643
Table 11-29. ADCRESULT12 Register Field Descriptions.....................................................................................................1644
Table 11-30. ADCRESULT13 Register Field Descriptions.....................................................................................................1645
Table 11-31. ADCRESULT14 Register Field Descriptions.....................................................................................................1646
Table 11-32. ADCRESULT15 Register Field Descriptions.....................................................................................................1647
Table 11-33. ADCPPB1RESULT Register Field Descriptions................................................................................................1648
Table 11-34. ADCPPB2RESULT Register Field Descriptions................................................................................................1649
Table 11-35. ADCPPB3RESULT Register Field Descriptions................................................................................................1650
Table 11-36. ADCPPB4RESULT Register Field Descriptions................................................................................................1651
Table 11-37. ADC_REGS Registers...................................................................................................................................... 1652
Table 11-38. ADC_REGS Access Type Codes......................................................................................................................1653
Table 11-39. ADCCTL1 Register Field Descriptions.............................................................................................................. 1655
Table 11-40. ADCCTL2 Register Field Descriptions.............................................................................................................. 1657
Table 11-41. ADCBURSTCTL Register Field Descriptions....................................................................................................1658
Table 11-42. ADCINTFLG Register Field Descriptions.......................................................................................................... 1660
Table 11-43. ADCINTFLGCLR Register Field Descriptions...................................................................................................1662
Table 11-44. ADCINTOVF Register Field Descriptions..........................................................................................................1663
Table 11-45. ADCINTOVFCLR Register Field Descriptions.................................................................................................. 1664
Table 11-46. ADCINTSEL1N2 Register Field Descriptions....................................................................................................1665
Table 11-47. ADCINTSEL3N4 Register Field Descriptions....................................................................................................1667
Table 11-48. ADCSOCPRICTL Register Field Descriptions.................................................................................................. 1669
Table 11-49. ADCINTSOCSEL1 Register Field Descriptions................................................................................................ 1671
Table 11-50. ADCINTSOCSEL2 Register Field Descriptions................................................................................................ 1673
Table 11-51. ADCSOCFLG1 Register Field Descriptions...................................................................................................... 1675
Table 11-52. ADCSOCFRC1 Register Field Descriptions......................................................................................................1679
Table 11-53. ADCSOCOVF1 Register Field Descriptions......................................................................................................1684
Table 11-54. ADCSOCOVFCLR1 Register Field Descriptions.............................................................................................. 1687
Table 11-55. ADCSOC0CTL Register Field Descriptions...................................................................................................... 1690
Table 11-56. ADCSOC1CTL Register Field Descriptions...................................................................................................... 1693
Table 11-57. ADCSOC2CTL Register Field Descriptions...................................................................................................... 1696

58 TMS320F2837xD Dual-Core Real-Time Microcontrollers SPRUHM8K – DECEMBER 2013 – REVISED MAY 2024
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Table 11-58. ADCSOC3CTL Register Field Descriptions...................................................................................................... 1699

Table 11-59. ADCSOC4CTL Register Field Descriptions...................................................................................................... 1702
Table 11-60. ADCSOC5CTL Register Field Descriptions...................................................................................................... 1705
Table 11-61. ADCSOC6CTL Register Field Descriptions...................................................................................................... 1708
Table 11-62. ADCSOC7CTL Register Field Descriptions...................................................................................................... 1711
Table 11-63. ADCSOC8CTL Register Field Descriptions...................................................................................................... 1714
Table 11-64. ADCSOC9CTL Register Field Descriptions...................................................................................................... 1717
Table 11-65. ADCSOC10CTL Register Field Descriptions.................................................................................................... 1720
Table 11-66. ADCSOC11CTL Register Field Descriptions.................................................................................................... 1723
Table 11-67. ADCSOC12CTL Register Field Descriptions.................................................................................................... 1726
Table 11-68. ADCSOC13CTL Register Field Descriptions.................................................................................................... 1729
Table 11-69. ADCSOC14CTL Register Field Descriptions.................................................................................................... 1732
Table 11-70. ADCSOC15CTL Register Field Descriptions.................................................................................................... 1735
Table 11-71. ADCEVTSTAT Register Field Descriptions....................................................................................................... 1738
Table 11-72. ADCEVTCLR Register Field Descriptions.........................................................................................................1741
Table 11-73. ADCEVTSEL Register Field Descriptions......................................................................................................... 1743
Table 11-74. ADCEVTINTSEL Register Field Descriptions................................................................................................... 1745
Table 11-75. ADCOSDETECT Register Field Descriptions................................................................................................... 1747
Table 11-76. ADCCOUNTER Register Field Descriptions..................................................................................................... 1748
Table 11-77. ADCREV Register Field Descriptions............................................................................................................... 1749
Table 11-78. ADCOFFTRIM Register Field Descriptions.......................................................................................................1750
Table 11-79. ADCPPB1CONFIG Register Field Descriptions................................................................................................1751
Table 11-80. ADCPPB1STAMP Register Field Descriptions................................................................................................. 1753
Table 11-81. ADCPPB1OFFCAL Register Field Descriptions............................................................................................... 1754
Table 11-82. ADCPPB1OFFREF Register Field Descriptions............................................................................................... 1755
Table 11-83. ADCPPB1TRIPHI Register Field Descriptions..................................................................................................1756
Table 11-84. ADCPPB1TRIPLO Register Field Descriptions.................................................................................................1757
Table 11-85. ADCPPB2CONFIG Register Field Descriptions................................................................................................1758
Table 11-86. ADCPPB2STAMP Register Field Descriptions................................................................................................. 1760
Table 11-87. ADCPPB2OFFCAL Register Field Descriptions............................................................................................... 1761
Table 11-88. ADCPPB2OFFREF Register Field Descriptions............................................................................................... 1762
Table 11-89. ADCPPB2TRIPHI Register Field Descriptions..................................................................................................1763
Table 11-90. ADCPPB2TRIPLO Register Field Descriptions.................................................................................................1764
Table 11-91. ADCPPB3CONFIG Register Field Descriptions................................................................................................1765
Table 11-92. ADCPPB3STAMP Register Field Descriptions................................................................................................. 1767
Table 11-93. ADCPPB3OFFCAL Register Field Descriptions............................................................................................... 1768
Table 11-94. ADCPPB3OFFREF Register Field Descriptions............................................................................................... 1769
Table 11-95. ADCPPB3TRIPHI Register Field Descriptions..................................................................................................1770
Table 11-96. ADCPPB3TRIPLO Register Field Descriptions.................................................................................................1771
Table 11-97. ADCPPB4CONFIG Register Field Descriptions................................................................................................1772
Table 11-98. ADCPPB4STAMP Register Field Descriptions................................................................................................. 1774
Table 11-99. ADCPPB4OFFCAL Register Field Descriptions............................................................................................... 1775
Table 11-100. ADCPPB4OFFREF Register Field Descriptions............................................................................................. 1776
Table 11-101. ADCPPB4TRIPHI Register Field Descriptions................................................................................................1777
Table 11-102. ADCPPB4TRIPLO Register Field Descriptions...............................................................................................1778
Table 11-103. ADCINLTRIM1 Register Field Descriptions.....................................................................................................1779
Table 11-104. ADCINLTRIM2 Register Field Descriptions.....................................................................................................1780
Table 11-105. ADCINLTRIM3 Register Field Descriptions.....................................................................................................1781
Table 11-106. ADCINLTRIM4 Register Field Descriptions.....................................................................................................1782
Table 11-107. ADCINLTRIM5 Register Field Descriptions.....................................................................................................1783
Table 11-108. ADCINLTRIM6 Register Field Descriptions.....................................................................................................1784
Table 11-109. ADC Registers to Driverlib Functions..............................................................................................................1784
Table 12-1. DAC Base Address Table................................................................................................................................... 1793
Table 12-2. DAC_REGS Registers........................................................................................................................................ 1794
Table 12-3. DAC_REGS Access Type Codes....................................................................................................................... 1794
Table 12-4. DACREV Register Field Descriptions................................................................................................................. 1795
Table 12-5. DACCTL Register Field Descriptions..................................................................................................................1796
Table 12-6. DACVALA Register Field Descriptions................................................................................................................1797
Table 12-7. DACVALS Register Field Descriptions................................................................................................................1798
Table 12-8. DACOUTEN Register Field Descriptions............................................................................................................1799
Table 12-9. DACLOCK Register Field Descriptions...............................................................................................................1800

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Table 12-10. DACTRIM Register Field Descriptions..............................................................................................................1801

Table 12-11. DAC Registers to Driverlib Functions................................................................................................................1801
Table 13-1. CMPSS Base Address Table.............................................................................................................................. 1814
Table 13-2. CMPSS_REGS Registers...................................................................................................................................1815
Table 13-3. CMPSS_REGS Access Type Codes.................................................................................................................. 1815
Table 13-4. COMPCTL Register Field Descriptions.............................................................................................................. 1817
Table 13-5. COMPHYSCTL Register Field Descriptions....................................................................................................... 1819
Table 13-6. COMPSTS Register Field Descriptions.............................................................................................................. 1820
Table 13-7. COMPSTSCLR Register Field Descriptions....................................................................................................... 1821
Table 13-8. COMPDACCTL Register Field Descriptions.......................................................................................................1822
Table 13-9. DACHVALS Register Field Descriptions............................................................................................................. 1823
Table 13-10. DACHVALA Register Field Descriptions........................................................................................................... 1824
Table 13-11. RAMPMAXREFA Register Field Descriptions...................................................................................................1825
Table 13-12. RAMPMAXREFS Register Field Descriptions.................................................................................................. 1826
Table 13-13. RAMPDECVALA Register Field Descriptions................................................................................................... 1827
Table 13-14. RAMPDECVALS Register Field Descriptions................................................................................................... 1828
Table 13-15. RAMPSTS Register Field Descriptions.............................................................................................................1829
Table 13-16. DACLVALS Register Field Descriptions............................................................................................................1830
Table 13-17. DACLVALA Register Field Descriptions............................................................................................................1831
Table 13-18. RAMPDLYA Register Field Descriptions...........................................................................................................1832
Table 13-19. RAMPDLYS Register Field Descriptions...........................................................................................................1833
Table 13-20. CTRIPLFILCTL Register Field Descriptions..................................................................................................... 1834
Table 13-21. CTRIPLFILCLKCTL Register Field Descriptions.............................................................................................. 1835
Table 13-22. CTRIPHFILCTL Register Field Descriptions.....................................................................................................1836
Table 13-23. CTRIPHFILCLKCTL Register Field Descriptions..............................................................................................1837
Table 13-24. COMPLOCK Register Field Descriptions......................................................................................................... 1838
Table 13-25. CMPSS Registers to Driverlib Functions.......................................................................................................... 1838
Table 14-1. Modulator Clock Modes...................................................................................................................................... 1847
Table 14-2. Order of Sinc Filter..............................................................................................................................................1850
Table 14-3. Peak Data Values for Different DOSR/Filter Combinations................................................................................ 1851
Table 14-4. Shift Control Bit Configuration Settings...............................................................................................................1852
Table 14-5. Number of Incorrect Samples Tabulated.............................................................................................................1853
Table 14-6. Peak Data Values for Different OSR/Filter Combinations................................................................................... 1854
Table 14-7. General Registers............................................................................................................................................... 1860
Table 14-8. Filter 1 Registers.................................................................................................................................................1860
Table 14-9. Filter 2 Registers.................................................................................................................................................1860
Table 14-10. Filter 3 Registers...............................................................................................................................................1861
Table 14-11. Filter 4 Registers............................................................................................................................................... 1861
Table 14-12. SDFM Base Address Table...............................................................................................................................1862
Table 14-13. SDFM_REGS Registers................................................................................................................................... 1863
Table 14-14. SDFM_REGS Access Type Codes...................................................................................................................1863
Table 14-15. SDIFLG Register Field Descriptions................................................................................................................. 1865
Table 14-16. SDIFLGCLR Register Field Descriptions..........................................................................................................1867
Table 14-17. SDCTL Register Field Descriptions.................................................................................................................. 1869
Table 14-18. SDMFILEN Register Field Descriptions............................................................................................................1870
Table 14-19. SDCTLPARM1 Register Field Descriptions...................................................................................................... 1871
Table 14-20. SDDFPARM1 Register Field Descriptions........................................................................................................ 1872
Table 14-21. SDDPARM1 Register Field Descriptions.......................................................................................................... 1873
Table 14-22. SDCMPH1 Register Field Descriptions............................................................................................................ 1874
Table 14-23. SDCMPL1 Register Field Descriptions............................................................................................................. 1875
Table 14-24. SDCPARM1 Register Field Descriptions.......................................................................................................... 1876
Table 14-25. SDDATA1 Register Field Descriptions.............................................................................................................. 1877
Table 14-26. SDCTLPARM2 Register Field Descriptions...................................................................................................... 1878
Table 14-27. SDDFPARM2 Register Field Descriptions........................................................................................................ 1879
Table 14-28. SDDPARM2 Register Field Descriptions.......................................................................................................... 1880
Table 14-29. SDCMPH2 Register Field Descriptions............................................................................................................ 1881
Table 14-30. SDCMPL2 Register Field Descriptions............................................................................................................. 1882
Table 14-31. SDCPARM2 Register Field Descriptions.......................................................................................................... 1883
Table 14-32. SDDATA2 Register Field Descriptions.............................................................................................................. 1884
Table 14-33. SDCTLPARM3 Register Field Descriptions...................................................................................................... 1885
Table 14-34. SDDFPARM3 Register Field Descriptions........................................................................................................ 1886

60 TMS320F2837xD Dual-Core Real-Time Microcontrollers SPRUHM8K – DECEMBER 2013 – REVISED MAY 2024
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Table 14-35. SDDPARM3 Register Field Descriptions.......................................................................................................... 1887

Table 14-36. SDCMPH3 Register Field Descriptions............................................................................................................ 1888
Table 14-37. SDCMPL3 Register Field Descriptions............................................................................................................. 1889
Table 14-38. SDCPARM3 Register Field Descriptions.......................................................................................................... 1890
Table 14-39. SDDATA3 Register Field Descriptions.............................................................................................................. 1891
Table 14-40. SDCTLPARM4 Register Field Descriptions...................................................................................................... 1892
Table 14-41. SDDFPARM4 Register Field Descriptions........................................................................................................ 1893
Table 14-42. SDDPARM4 Register Field Descriptions.......................................................................................................... 1894
Table 14-43. SDCMPH4 Register Field Descriptions............................................................................................................ 1895
Table 14-44. SDCMPL4 Register Field Descriptions............................................................................................................. 1896
Table 14-45. SDCPARM4 Register Field Descriptions.......................................................................................................... 1897
Table 14-46. SDDATA4 Register Field Descriptions.............................................................................................................. 1898
Table 14-47. SDFM Registers to Driverlib Functions.............................................................................................................1899
Table 15-1. Submodule Configuration Parameters................................................................................................................1909
Table 15-2. Key Time-Base Signals.......................................................................................................................................1913
Table 15-3. Action-Qualifier Submodule Possible Input Events.............................................................................................1931
Table 15-4. Action-Qualifier Event Priority for Up-Down-Count Mode................................................................................... 1933
Table 15-5. Action-Qualifier Event Priority for Up-Count Mode............................................................................................. 1933
Table 15-6. Action-Qualifier Event Priority for Down-Count Mode.........................................................................................1933
Table 15-7. Behavior if CMPA/CMPB is Greater than the Period.......................................................................................... 1934
Table 15-8. Classical Dead-Band Operating Modes..............................................................................................................1947
Table 15-9. Additional Dead-Band Operating Modes............................................................................................................ 1947
Table 15-10. Dead-Band Delay Values in μs as a Function of DBFED and DBRED.............................................................1949
Table 15-11. Possible Pulse Width Values for EPWMCLK = 80MHz.....................................................................................1952
Table 15-12. Possible Actions On a Trip Event......................................................................................................................1956
Table 15-13. Resolution for PWM and HRPWM.................................................................................................................... 1995
Table 15-14. Relationship Between MEP Steps, PWM Frequency, and Resolution..............................................................2001
Table 15-15. CMPA versus Duty (left), and [CMPA:CMPAHR] versus Duty (right)................................................................2002
Table 15-16. Duty Cycle Range Limitation for Three EPWMCLK/TBCLK Cycles................................................................. 2005
Table 15-17. SFO Library Features....................................................................................................................................... 2017
Table 15-18. Factor Values.................................................................................................................................................... 2018
Table 15-19. ePWM Base Address Table.............................................................................................................................. 2020
Table 15-20. EPWM_REGS Registers.................................................................................................................................. 2021
Table 15-21. EPWM_REGS Access Type Codes..................................................................................................................2023
Table 15-22. TBCTL Register Field Descriptions...................................................................................................................2024
Table 15-23. TBCTL2 Register Field Descriptions.................................................................................................................2026
Table 15-24. TBCTR Register Field Descriptions.................................................................................................................. 2027
Table 15-25. TBSTS Register Field Descriptions.................................................................................................................. 2028
Table 15-26. CMPCTL Register Field Descriptions............................................................................................................... 2029
Table 15-27. CMPCTL2 Register Field Descriptions............................................................................................................. 2031
Table 15-28. DBCTL Register Field Descriptions.................................................................................................................. 2033
Table 15-29. DBCTL2 Register Field Descriptions................................................................................................................ 2036
Table 15-30. AQCTL Register Field Descriptions.................................................................................................................. 2037
Table 15-31. AQTSRCSEL Register Field Descriptions........................................................................................................ 2039
Table 15-32. PCCTL Register Field Descriptions.................................................................................................................. 2040
Table 15-33. VCAPCTL Register Field Descriptions............................................................................................................. 2042
Table 15-34. VCNTCFG Register Field Descriptions.............................................................................................................2044
Table 15-35. HRCNFG Register Field Descriptions...............................................................................................................2046
Table 15-36. HRPWR Register Field Descriptions................................................................................................................ 2048
Table 15-37. HRMSTEP Register Field Descriptions............................................................................................................ 2049
Table 15-38. HRCNFG2 Register Field Descriptions.............................................................................................................2050
Table 15-39. HRPCTL Register Field Descriptions................................................................................................................2051
Table 15-40. TRREM Register Field Descriptions................................................................................................................. 2053
Table 15-41. GLDCTL Register Field Descriptions................................................................................................................2054
Table 15-42. GLDCFG Register Field Descriptions............................................................................................................... 2056
Table 15-43. EPWMXLINK Register Field Descriptions........................................................................................................ 2058
Table 15-44. AQCTLA Register Field Descriptions................................................................................................................2060
Table 15-45. AQCTLA2 Register Field Descriptions..............................................................................................................2062
Table 15-46. AQCTLB Register Field Descriptions................................................................................................................2063
Table 15-47. AQCTLB2 Register Field Descriptions..............................................................................................................2065
Table 15-48. AQSFRC Register Field Descriptions............................................................................................................... 2066

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Table 15-49. AQCSFRC Register Field Descriptions............................................................................................................ 2067

Table 15-50. DBREDHR Register Field Descriptions............................................................................................................ 2068
Table 15-51. DBRED Register Field Descriptions................................................................................................................. 2069
Table 15-52. DBFEDHR Register Field Descriptions.............................................................................................................2070
Table 15-53. DBFED Register Field Descriptions..................................................................................................................2071
Table 15-54. TBPHS Register Field Descriptions.................................................................................................................. 2072
Table 15-55. TBPRDHR Register Field Descriptions.............................................................................................................2073
Table 15-56. TBPRD Register Field Descriptions..................................................................................................................2074
Table 15-57. CMPA Register Field Descriptions.................................................................................................................... 2075
Table 15-58. CMPB Register Field Descriptions....................................................................................................................2076
Table 15-59. CMPC Register Field Descriptions................................................................................................................... 2077
Table 15-60. CMPD Register Field Descriptions................................................................................................................... 2078
Table 15-61. GLDCTL2 Register Field Descriptions..............................................................................................................2079
Table 15-62. SWVDELVAL Register Field Descriptions.........................................................................................................2080
Table 15-63. TZSEL Register Field Descriptions...................................................................................................................2081
Table 15-64. TZDCSEL Register Field Descriptions..............................................................................................................2083
Table 15-65. TZCTL Register Field Descriptions...................................................................................................................2084
Table 15-66. TZCTL2 Register Field Descriptions.................................................................................................................2086
Table 15-67. TZCTLDCA Register Field Descriptions........................................................................................................... 2088
Table 15-68. TZCTLDCB Register Field Descriptions........................................................................................................... 2090
Table 15-69. TZEINT Register Field Descriptions................................................................................................................. 2092
Table 15-70. TZFLG Register Field Descriptions...................................................................................................................2093
Table 15-71. TZCBCFLG Register Field Descriptions........................................................................................................... 2095
Table 15-72. TZOSTFLG Register Field Descriptions........................................................................................................... 2097
Table 15-73. TZCLR Register Field Descriptions.................................................................................................................. 2099
Table 15-74. TZCBCCLR Register Field Descriptions...........................................................................................................2101
Table 15-75. TZOSTCLR Register Field Descriptions........................................................................................................... 2102
Table 15-76. TZFRC Register Field Descriptions.................................................................................................................. 2103
Table 15-77. ETSEL Register Field Descriptions...................................................................................................................2104
Table 15-78. ETPS Register Field Descriptions.....................................................................................................................2107
Table 15-79. ETFLG Register Field Descriptions...................................................................................................................2110
Table 15-80. ETCLR Register Field Descriptions...................................................................................................................2111
Table 15-81. ETFRC Register Field Descriptions.................................................................................................................. 2112
Table 15-82. ETINTPS Register Field Descriptions............................................................................................................... 2113
Table 15-83. ETSOCPS Register Field Descriptions............................................................................................................. 2114
Table 15-84. ETCNTINITCTL Register Field Descriptions.....................................................................................................2116
Table 15-85. ETCNTINIT Register Field Descriptions............................................................................................................2117
Table 15-86. DCTRIPSEL Register Field Descriptions.......................................................................................................... 2118
Table 15-87. DCACTL Register Field Descriptions................................................................................................................2120
Table 15-88. DCBCTL Register Field Descriptions................................................................................................................2121
Table 15-89. DCFCTL Register Field Descriptions................................................................................................................2122
Table 15-90. DCCAPCTL Register Field Descriptions...........................................................................................................2124
Table 15-91. DCFOFFSET Register Field Descriptions........................................................................................................ 2126
Table 15-92. DCFOFFSETCNT Register Field Descriptions................................................................................................. 2127
Table 15-93. DCFWINDOW Register Field Descriptions.......................................................................................................2128
Table 15-94. DCFWINDOWCNT Register Field Descriptions............................................................................................... 2129
Table 15-95. DCCAP Register Field Descriptions................................................................................................................. 2130
Table 15-96. DCAHTRIPSEL Register Field Descriptions.....................................................................................................2131
Table 15-97. DCALTRIPSEL Register Field Descriptions......................................................................................................2133
Table 15-98. DCBHTRIPSEL Register Field Descriptions.....................................................................................................2135
Table 15-99. DCBLTRIPSEL Register Field Descriptions......................................................................................................2137
Table 15-100. HWVDELVAL Register Field Descriptions...................................................................................................... 2139
Table 15-101. VCNTVAL Register Field Descriptions............................................................................................................2140
Table 15-102. EPWM Registers to Driverlib Functions..........................................................................................................2141
Table 15-103. HRPWM Registers to Driverlib Functions....................................................................................................... 2147
Table 16-1. eCAP Base Address Table..................................................................................................................................2173
Table 16-2. ECAP_REGS Registers......................................................................................................................................2174
Table 16-3. ECAP_REGS Access Type Codes..................................................................................................................... 2174
Table 16-4. TSCTR Register Field Descriptions.................................................................................................................... 2175
Table 16-5. CTRPHS Register Field Descriptions................................................................................................................. 2176
Table 16-6. CAP1 Register Field Descriptions.......................................................................................................................2177

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Table 16-7. CAP2 Register Field Descriptions.......................................................................................................................2178

Table 16-8. CAP3 Register Field Descriptions.......................................................................................................................2179
Table 16-9. CAP4 Register Field Descriptions.......................................................................................................................2180
Table 16-10. ECCTL1 Register Field Descriptions................................................................................................................ 2181
Table 16-11. ECCTL2 Register Field Descriptions.................................................................................................................2183
Table 16-12. ECEINT Register Field Descriptions.................................................................................................................2185
Table 16-13. ECFLG Register Field Descriptions.................................................................................................................. 2187
Table 16-14. ECCLR Register Field Descriptions..................................................................................................................2188
Table 16-15. ECFRC Register Field Descriptions..................................................................................................................2189
Table 16-16. ECAP Registers to Driverlib Functions............................................................................................................. 2189
Table 17-1. EQEP Memory Map............................................................................................................................................ 2198
Table 17-2. Quadrature Decoder Truth Table........................................................................................................................ 2200
Table 17-3. eQEP Base Address Table................................................................................................................................. 2215
Table 17-4. EQEP_REGS Registers......................................................................................................................................2216
Table 17-5. EQEP_REGS Access Type Codes..................................................................................................................... 2216
Table 17-6. QPOSCNT Register Field Descriptions.............................................................................................................. 2217
Table 17-7. QPOSINIT Register Field Descriptions...............................................................................................................2218
Table 17-8. QPOSMAX Register Field Descriptions..............................................................................................................2219
Table 17-9. QPOSCMP Register Field Descriptions..............................................................................................................2220
Table 17-10. QPOSILAT Register Field Descriptions............................................................................................................ 2221
Table 17-11. QPOSSLAT Register Field Descriptions........................................................................................................... 2222
Table 17-12. QPOSLAT Register Field Descriptions............................................................................................................. 2223
Table 17-13. QUTMR Register Field Descriptions.................................................................................................................2224
Table 17-14. QUPRD Register Field Descriptions................................................................................................................. 2225
Table 17-15. QWDTMR Register Field Descriptions............................................................................................................. 2226
Table 17-16. QWDPRD Register Field Descriptions..............................................................................................................2227
Table 17-17. QDECCTL Register Field Descriptions.............................................................................................................2228
Table 17-18. QEPCTL Register Field Descriptions................................................................................................................2230
Table 17-19. QCAPCTL Register Field Descriptions............................................................................................................. 2232
Table 17-20. QPOSCTL Register Field Descriptions.............................................................................................................2233
Table 17-21. QEINT Register Field Descriptions................................................................................................................... 2234
Table 17-22. QFLG Register Field Descriptions.................................................................................................................... 2236
Table 17-23. QCLR Register Field Descriptions.................................................................................................................... 2238
Table 17-24. QFRC Register Field Descriptions....................................................................................................................2240
Table 17-25. QEPSTS Register Field Descriptions............................................................................................................... 2242
Table 17-26. QCTMR Register Field Descriptions.................................................................................................................2244
Table 17-27. QCPRD Register Field Descriptions................................................................................................................. 2245
Table 17-28. QCTMRLAT Register Field Descriptions...........................................................................................................2246
Table 17-29. QCPRDLAT Register Field Descriptions...........................................................................................................2247
Table 17-30. EQEP Registers to Driverlib Functions............................................................................................................. 2247
Table 18-1. SPI Module Signal Summary.............................................................................................................................. 2253
Table 18-2. SPI Interrupt Flag Modes.................................................................................................................................... 2255
Table 18-3. SPI Clocking Scheme Selection Guide...............................................................................................................2263
Table 18-4. 4-wire versus 3-wire SPI Pin Functions.............................................................................................................. 2266
Table 18-5. 3-Wire SPI Pin Configuration.............................................................................................................................. 2267
Table 18-6. SPI Base Address Table..................................................................................................................................... 2277
Table 18-7. SPI_REGS Registers..........................................................................................................................................2278
Table 18-8. SPI_REGS Access Type Codes......................................................................................................................... 2278
Table 18-9. SPICCR Register Field Descriptions.................................................................................................................. 2279
Table 18-10. SPICTL Register Field Descriptions................................................................................................................. 2281
Table 18-11. SPISTS Register Field Descriptions..................................................................................................................2283
Table 18-12. SPIBRR Register Field Descriptions.................................................................................................................2285
Table 18-13. SPIRXEMU Register Field Descriptions........................................................................................................... 2286
Table 18-14. SPIRXBUF Register Field Descriptions............................................................................................................ 2287
Table 18-15. SPITXBUF Register Field Descriptions............................................................................................................ 2288
Table 18-16. SPIDAT Register Field Descriptions................................................................................................................. 2289
Table 18-17. SPIFFTX Register Field Descriptions............................................................................................................... 2290
Table 18-18. SPIFFRX Register Field Descriptions...............................................................................................................2292
Table 18-19. SPIFFCT Register Field Descriptions............................................................................................................... 2294
Table 18-20. SPIPRI Register Field Descriptions.................................................................................................................. 2295
Table 18-21. SPI Registers to Driverlib Functions................................................................................................................. 2296

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Table 19-1. SCI Module Signal Summary..............................................................................................................................2300

Table 19-2. Programming the Data Format Using SCICCR.................................................................................................. 2303
Table 19-3. Asynchronous Baud Register Values for Common SCI Bit Rates...................................................................... 2312
Table 19-4. SCI Interrupt Flags..............................................................................................................................................2314
Table 19-5. SCI Base Address Table..................................................................................................................................... 2316
Table 19-6. SCI_REGS Registers..........................................................................................................................................2317
Table 19-7. SCI_REGS Access Type Codes......................................................................................................................... 2317
Table 19-8. SCICCR Register Field Descriptions.................................................................................................................. 2318
Table 19-9. SCICTL1 Register Field Descriptions................................................................................................................. 2320
Table 19-10. SCIHBAUD Register Field Descriptions........................................................................................................... 2322
Table 19-11. SCILBAUD Register Field Descriptions............................................................................................................ 2323
Table 19-12. SCICTL2 Register Field Descriptions............................................................................................................... 2324
Table 19-13. SCIRXST Register Field Descriptions.............................................................................................................. 2326
Table 19-14. SCIRXEMU Register Field Descriptions........................................................................................................... 2329
Table 19-15. SCIRXBUF Register Field Descriptions............................................................................................................2330
Table 19-16. SCITXBUF Register Field Descriptions............................................................................................................ 2332
Table 19-17. SCIFFTX Register Field Descriptions............................................................................................................... 2333
Table 19-18. SCIFFRX Register Field Descriptions...............................................................................................................2335
Table 19-19. SCIFFCT Register Field Descriptions...............................................................................................................2337
Table 19-20. SCIPRI Register Field Descriptions.................................................................................................................. 2338
Table 19-21. SCI Registers to Driverlib Functions................................................................................................................. 2338
Table 20-1. Dependency of Delay d on the Divide-Down Value IPSC................................................................................... 2346
Table 20-2. Operating Modes of the I2C Module................................................................................................................... 2348
Table 20-3. Master-Transmitter/Receiver Bus Activity Defined by the RM, STT, and STP Bits of I2CMDR.......................... 2348
Table 20-4. How the MST and FDF Bits of I2CMDR Affect the Role of the TRX Bit of I2CMDR...........................................2354
Table 20-5. Ways to Generate a NACK Bit............................................................................................................................ 2358
Table 20-6. Descriptions of the Basic I2C Interrupt Requests............................................................................................... 2359
Table 20-7. I2C Base Address Table (C28)........................................................................................................................... 2365
Table 20-8. I2C_REGS Registers.......................................................................................................................................... 2366
Table 20-9. I2C_REGS Access Type Codes......................................................................................................................... 2366
Table 20-10. I2COAR Register Field Descriptions.................................................................................................................2367
Table 20-11. I2CIER Register Field Descriptions...................................................................................................................2368
Table 20-12. I2CSTR Register Field Descriptions................................................................................................................. 2369
Table 20-13. I2CCLKL Register Field Descriptions............................................................................................................... 2373
Table 20-14. I2CCLKH Register Field Descriptions...............................................................................................................2374
Table 20-15. I2CCNT Register Field Descriptions................................................................................................................. 2375
Table 20-16. I2CDRR Register Field Descriptions.................................................................................................................2376
Table 20-17. I2CSAR Register Field Descriptions................................................................................................................. 2377
Table 20-18. I2CDXR Register Field Descriptions.................................................................................................................2378
Table 20-19. I2CMDR Register Field Descriptions................................................................................................................ 2379
Table 20-20. I2CISRC Register Field Descriptions................................................................................................................2383
Table 20-21. I2CEMDR Register Field Descriptions..............................................................................................................2384
Table 20-22. I2CPSC Register Field Descriptions................................................................................................................. 2385
Table 20-23. I2CFFTX Register Field Descriptions............................................................................................................... 2386
Table 20-24. I2CFFRX Register Field Descriptions............................................................................................................... 2388
Table 20-25. I2C Registers to Driverlib Functions................................................................................................................. 2389
Table 21-1. McBSP Interface Pins/Signals............................................................................................................................ 2393
Table 21-2. Register Bits That Determine the Number of Phases, Words, and Bits..............................................................2400
Table 21-3. Interrupts and DMA Events Generated by a McBSP.......................................................................................... 2404
Table 21-4. Effects of DLB and CLKSTP on Clock Modes.................................................................................................... 2406
Table 21-5. Choosing an Input Clock for the Sample Rate Generator with the SCLKME and CLKSM Bits.......................... 2406
Table 21-6. Polarity Options for the Input to the Sample Rate Generator............................................................................. 2407
Table 21-7. Input Clock Selection for Sample Rate Generator.............................................................................................. 2411
Table 21-8. Block - Channel Assignment...............................................................................................................................2420
Table 21-9. 2-Partition Mode..................................................................................................................................................2420
Table 21-10. 8-Partition Mode................................................................................................................................................2420
Table 21-11. Receive Channel Assignment and Control With Eight Receive Partitions........................................................ 2423
Table 21-12. Transmit Channel Assignment and Control When Eight Transmit Partitions Are Used.................................... 2423
Table 21-13. Selecting a Transmit Multichannel Selection Mode With the XMCM Bits......................................................... 2425
Table 21-14. Bits Used to Enable and Configure the Clock Stop Mode................................................................................ 2429
Table 21-15. Effects of CLKSTP, CLKXP, and CLKRP on the Clock Scheme....................................................................... 2429

64 TMS320F2837xD Dual-Core Real-Time Microcontrollers SPRUHM8K – DECEMBER 2013 – REVISED MAY 2024
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Table 21-16. Bit Values Required to Configure the McBSP as an SPI Master ..................................................................... 2433
Table 21-17. Bit Values Required to Configure the McBSP as an SPI Slave ....................................................................... 2434
Table 21-18. Register Bits Used to Reset or Enable the McBSP Receiver Field Descriptions..............................................2436
Table 21-19. Reset State of Each McBSP Pin.......................................................................................................................2436
Table 21-20. Register Bit Used to Enable/Disable the Digital Loopback Mode..................................................................... 2437
Table 21-21. Receive Signals Connected to Transmit Signals in Digital Loopback Mode.....................................................2437
Table 21-22. Register Bits Used to Enable/Disable the Clock Stop Mode.............................................................................2437
Table 21-23. Effects of CLKSTP, CLKXP, and CLKRP on the Clock Scheme....................................................................... 2438
Table 21-24. Register Bit Used to Enable/Disable the Receive Multichannel Selection Mode..............................................2438
Table 21-25. Register Bit Used to Choose One or Two Phases for the Receive Frame....................................................... 2438
Table 21-26. Register Bits Used to Set the Receive Word Lengths.......................................................................................2439
Table 21-27. Register Bits Used to Set the Receive Frame Length...................................................................................... 2440
Table 21-28. How to Calculate the Length of the Receive Frame......................................................................................... 2440
Table 21-29. Register Bit Used to Enable/Disable the Receive Frame-Synchronization Ignore Function.............................2441
Table 21-30. Register Bits Used to Set the Receive Companding Mode.............................................................................. 2442
Table 21-31. Register Bits Used to Set the Receive Data Delay........................................................................................... 2444
Table 21-32. Register Bits Used to Set the Receive Sign-Extension and Justification Mode................................................2446
Table 21-33. Example: Use of RJUST Field With 12-Bit Data Value ABCh...........................................................................2446
Table 21-34. Example: Use of RJUST Field With 20-Bit Data Value ABCDEh......................................................................2446
Table 21-35. Register Bits Used to Set the Receive Interrupt Mode..................................................................................... 2447
Table 21-36. Register Bits Used to Set the Receive Frame Synchronization Mode..............................................................2448
Table 21-37. Select Sources to Provide the Receive Frame-Synchronization Signal and the Effect on the FSR Pin........... 2449
Table 21-38. Register Bit Used to Set Receive Frame-Synchronization Polarity.................................................................. 2449
Table 21-39. Register Bits Used to Set the SRG Frame-Synchronization Period and Pulse Width...................................... 2451
Table 21-40. Register Bits Used to Set the Receive Clock Mode..........................................................................................2452
Table 21-41. Receive Clock Signal Source Selection............................................................................................................2453
Table 21-42. Register Bit Used to Set Receive Clock Polarity...............................................................................................2453
Table 21-43. Register Bits Used to Set the Sample Rate Generator (SRG) Clock Divide-Down Value................................ 2455
Table 21-44. Register Bit Used to Set the SRG Clock Synchronization Mode...................................................................... 2455
Table 21-45. Register Bits Used to Set the SRG Clock Mode (Choose an Input Clock)....................................................... 2456
Table 21-46. Register Bits Used to Set the SRG Input Clock Polarity................................................................................... 2456
Table 21-47. Register Bits Used to Place Transmitter in Reset Field Descriptions............................................................... 2458
Table 21-48. Register Bit Used to Enable/Disable the Digital Loopback Mode..................................................................... 2459
Table 21-49. Receive Signals Connected to Transmit Signals in Digital Loopback Mode.....................................................2459
Table 21-50. Register Bits Used to Enable/Disable the Clock Stop Mode.............................................................................2459
Table 21-51. Effects of CLKSTP, CLKXP, and CLKRP on the Clock Scheme....................................................................... 2460
Table 21-52. Register Bits Used to Enable/Disable Transmit Multichannel Selection........................................................... 2460
Table 21-53. Use of the Transmit Channel Enable Registers................................................................................................ 2461
Table 21-54. Register Bit Used to Choose 1 or 2 Phases for the Transmit Frame................................................................ 2463
Table 21-55. Register Bits Used to Set the Transmit Word Lengths......................................................................................2463
Table 21-56. Register Bits Used to Set the Transmit Frame Length......................................................................................2464
Table 21-57. How to Calculate Frame Length....................................................................................................................... 2464
Table 21-58. Register Bit Used to Enable/Disable the Transmit Frame-Synchronization Ignore Function............................2465
Table 21-59. Register Bits Used to Set the Transmit Companding Mode..............................................................................2466
Table 21-60. Register Bits Used to Set the Transmit Data Delay.......................................................................................... 2467
Table 21-61. Register Bit Used to Set the Transmit DXENA (DX Delay Enabler) Mode....................................................... 2469
Table 21-62. Register Bits Used to Set the Transmit Interrupt Mode.....................................................................................2469
Table 21-63. Register Bits Used to Set the Transmit Frame-Synchronization Mode.............................................................2470
Table 21-64. How FSXM and FSGM Select the Source of Transmit Frame-Synchronization Pulses................................... 2470
Table 21-65. Register Bit Used to Set Transmit Frame-Synchronization Polarity..................................................................2471
Table 21-66. Register Bits Used to Set SRG Frame-Synchronization Period and Pulse Width............................................ 2472
Table 21-67. Register Bit Used to Set the Transmit Clock Mode...........................................................................................2473
Table 21-68. How the CLKXM Bit Selects the Transmit Clock and the Corresponding Status of the MCLKX pin.................2473
Table 21-69. Register Bit Used to Set Transmit Clock Polarity..............................................................................................2473
Table 21-70. McBSP Emulation Modes Selectable with FREE and SOFT Bits of SPCR2....................................................2475
Table 21-71. Reset State of Each McBSP Pin.......................................................................................................................2475
Table 21-72. Receive Interrupt Sources and Signals.............................................................................................................2481
Table 21-73. Transmit Interrupt Sources and Signals............................................................................................................2482
Table 21-74. Error Flags........................................................................................................................................................ 2482
Table 21-75. McBSP Mode Selection.................................................................................................................................... 2483
Table 21-76. McBSP Base Address Table............................................................................................................................. 2485

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Table 21-77. MCBSP_REGS Registers.................................................................................................................................2486

Table 21-78. McBSP_REGS Access Type Codes................................................................................................................. 2486
Table 21-79. DRR2 Register Field Descriptions.................................................................................................................... 2488
Table 21-80. DRR1 Register Field Descriptions.................................................................................................................... 2489
Table 21-81. DXR2 Register Field Descriptions.................................................................................................................... 2490
Table 21-82. DXR1 Register Field Descriptions.................................................................................................................... 2491
Table 21-83. SPCR2 Register Field Descriptions.................................................................................................................. 2492
Table 21-84. SPCR1 Register Field Descriptions.................................................................................................................. 2495
Table 21-85. RCR2 Register Field Descriptions.................................................................................................................... 2498
Table 21-86. RCR1 Register Field Descriptions.................................................................................................................... 2500
Table 21-87. XCR2 Register Field Descriptions.................................................................................................................... 2501
Table 21-88. XCR1 Register Field Descriptions.................................................................................................................... 2503
Table 21-89. SRGR2 Register Field Descriptions..................................................................................................................2504
Table 21-90. SRGR1 Register Field Descriptions..................................................................................................................2506
Table 21-91. MCR2 Register Field Descriptions....................................................................................................................2507
Table 21-92. MCR1 Register Field Descriptions....................................................................................................................2509
Table 21-93. RCERA Register Field Descriptions..................................................................................................................2511
Table 21-94. RCERB Register Field Descriptions................................................................................................................. 2512
Table 21-95. XCERA Register Field Descriptions..................................................................................................................2513
Table 21-96. XCERB Register Field Descriptions..................................................................................................................2514
Table 21-97. PCR Register Field Descriptions...................................................................................................................... 2515
Table 21-98. RCERC Register Field Descriptions................................................................................................................. 2518
Table 21-99. RCERD Register Field Descriptions................................................................................................................. 2519
Table 21-100. XCERC Register Field Descriptions............................................................................................................... 2520
Table 21-101. XCERD Register Field Descriptions............................................................................................................... 2521
Table 21-102. RCERE Register Field Descriptions............................................................................................................... 2522
Table 21-103. RCERF Register Field Descriptions................................................................................................................2523
Table 21-104. XCERE Register Field Descriptions................................................................................................................2524
Table 21-105. XCERF Register Field Descriptions................................................................................................................2525
Table 21-106. RCERG Register Field Descriptions............................................................................................................... 2526
Table 21-107. RCERH Register Field Descriptions............................................................................................................... 2527
Table 21-108. XCERG Register Field Descriptions............................................................................................................... 2528
Table 21-109. XCERH Register Field Descriptions............................................................................................................... 2529
Table 21-110. MFFINT Register Field Descriptions............................................................................................................... 2530
Table 21-111. MCBSP Registers to Driverlib Functions.........................................................................................................2530
Table 22-1. CAN Register Access from Software.................................................................................................................. 2539
Table 22-2. CAN Register Access from Code Composer Studio™ IDE................................................................................ 2539
Table 22-3. PIE Module Nomenclature for Interrupts.............................................................................................................2547
Table 22-4. Programmable Ranges Required by CAN Protocol............................................................................................2559
Table 22-5. Message Object Field Descriptions.................................................................................................................... 2569
Table 22-6. Message RAM Addressing in Debug Mode........................................................................................................ 2572
Table 22-7. CAN Base Address Table................................................................................................................................... 2574
Table 22-8. CAN_REGS Registers........................................................................................................................................ 2575
Table 22-9. CAN_REGS Access Type Codes....................................................................................................................... 2576
Table 22-10. CAN_CTL Register Field Descriptions..............................................................................................................2577
Table 22-11. CAN_ES Register Field Descriptions................................................................................................................ 2580
Table 22-12. CAN_ERRC Register Field Descriptions.......................................................................................................... 2582
Table 22-13. CAN_BTR Register Field Descriptions............................................................................................................. 2583
Table 22-14. CAN_INT Register Field Descriptions...............................................................................................................2585
Table 22-15. CAN_TEST Register Field Descriptions........................................................................................................... 2586
Table 22-16. CAN_PERR Register Field Descriptions.......................................................................................................... 2588
Table 22-17. CAN_RAM_INIT Register Field Descriptions....................................................................................................2589
Table 22-18. CAN_GLB_INT_EN Register Field Descriptions.............................................................................................. 2590
Table 22-19. CAN_GLB_INT_FLG Register Field Descriptions............................................................................................ 2591
Table 22-20. CAN_GLB_INT_CLR Register Field Descriptions............................................................................................ 2592
Table 22-21. CAN_ABOTR Register Field Descriptions........................................................................................................ 2593
Table 22-22. CAN_TXRQ_X Register Field Descriptions...................................................................................................... 2594
Table 22-23. CAN_TXRQ_21 Register Field Descriptions.................................................................................................... 2595
Table 22-24. CAN_NDAT_X Register Field Descriptions.......................................................................................................2596
Table 22-25. CAN_NDAT_21 Register Field Descriptions..................................................................................................... 2597
Table 22-26. CAN_IPEN_X Register Field Descriptions........................................................................................................2598

66 TMS320F2837xD Dual-Core Real-Time Microcontrollers SPRUHM8K – DECEMBER 2013 – REVISED MAY 2024
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Table 22-27. CAN_IPEN_21 Register Field Descriptions...................................................................................................... 2599

Table 22-28. CAN_MVAL_X Register Field Descriptions.......................................................................................................2600
Table 22-29. CAN_MVAL_21 Register Field Descriptions..................................................................................................... 2601
Table 22-30. CAN_IP_MUX21 Register Field Descriptions................................................................................................... 2602
Table 22-31. CAN_IF1CMD Register Field Descriptions....................................................................................................... 2603
Table 22-32. CAN_IF1MSK Register Field Descriptions....................................................................................................... 2606
Table 22-33. CAN_IF1ARB Register Field Descriptions........................................................................................................2607
Table 22-34. CAN_IF1MCTL Register Field Descriptions..................................................................................................... 2609
Table 22-35. CAN_IF1DATA Register Field Descriptions...................................................................................................... 2611
Table 22-36. CAN_IF1DATB Register Field Descriptions...................................................................................................... 2612
Table 22-37. CAN_IF2CMD Register Field Descriptions....................................................................................................... 2613
Table 22-38. CAN_IF2MSK Register Field Descriptions....................................................................................................... 2616
Table 22-39. CAN_IF2ARB Register Field Descriptions........................................................................................................2617
Table 22-40. CAN_IF2MCTL Register Field Descriptions..................................................................................................... 2619
Table 22-41. CAN_IF2DATA Register Field Descriptions...................................................................................................... 2621
Table 22-42. CAN_IF2DATB Register Field Descriptions...................................................................................................... 2622
Table 22-43. CAN_IF3OBS Register Field Descriptions........................................................................................................2623
Table 22-44. CAN_IF3MSK Register Field Descriptions....................................................................................................... 2625
Table 22-45. CAN_IF3ARB Register Field Descriptions........................................................................................................2626
Table 22-46. CAN_IF3MCTL Register Field Descriptions..................................................................................................... 2627
Table 22-47. CAN_IF3DATA Register Field Descriptions...................................................................................................... 2629
Table 22-48. CAN_IF3DATB Register Field Descriptions...................................................................................................... 2630
Table 22-49. CAN_IF3UPD Register Field Descriptions........................................................................................................2631
Table 22-50. CAN Registers to Driverlib Functions............................................................................................................... 2631
Table 23-1. USB Memory Access from Software...................................................................................................................2649
Table 23-2. USB Memory Access from CCS IDE.................................................................................................................. 2650
Table 23-3. USB Base Address Table (C28)..........................................................................................................................2652
Table 23-4. Universal Serial Bus (USB) Controller Register Map..........................................................................................2652
Table 23-5. USB Device Functional Address Register (USBFADDR) Field Descriptions......................................................2660
Table 23-6. USB Power Management Register (USBPOWER) in Host Mode Field Descriptions.........................................2661
Table 23-7. USB Power Management Register (USBPOWER) in Device Mode Field Descriptions..................................... 2662
Table 23-8. USB Transmit Interrupt Status Register (USBTXIS) Field Descriptions............................................................. 2663
Table 23-9. USB Transmit Interrupt Status Register (USBRXIS) Field Descriptions............................................................. 2665
Table 23-10. USB Transmit Interrupt Status Register (USBTXIE) Field Descriptions........................................................... 2667
Table 23-11. USB Transmit Interrupt Status Register (USBRXIE) Field Descriptions........................................................... 2669
Table 23-12. USB General Interrupt Status Register (USBIS) in Host Mode Field Descriptions...........................................2671
Table 23-13. USB General Interrupt Status Register (USBIS) in Device Mode Field Descriptions....................................... 2672
Table 23-14. USB Interrupt Enable Register (USBIE) in Host Mode Field Descriptions........................................................2673
Table 23-15. USB Interrupt Enable Register (USBIE) in Device Mode Field Descriptions.................................................... 2674
Table 23-16. USB Frame Value Register (USBFRAME) Field Descriptions.......................................................................... 2675
Table 23-17. USB Endpoint Index Register (USBEPIDX) Field Descriptions........................................................................ 2675
Table 23-18. USB Test Mode Register (USBTEST) in Host Mode Field Descriptions...........................................................2676
Table 23-19. USB Test Mode Register (USBTEST) in Device Mode Field Descriptions....................................................... 2677
Table 23-20. USB FIFO Endpoint n Register (USBFIFO[n]) Field Descriptions.................................................................... 2678
Table 23-21. USB Device Control Register (USBDEVCTL) Field Descriptions..................................................................... 2679
Table 23-22. USB Transmit Dynamic FIFO Sizing Register (USBTXFIFOSZ) Field Descriptions.........................................2681
Table 23-23. USB Receive Dynamic FIFO Sizing Register (USBRXFIFOSZ) Field Descriptions......................................... 2682
Table 23-24. USB Transmit FIFO Start Address Register (USBTXFIFOADDR) Field Descriptions...................................... 2683
Table 23-25. USB Receive FIFO Start Address Register (USBRXFIFOADDR) Field Descriptions...................................... 2684
Table 23-26. USB Connect Timing Register (USBCONTIM) Field Descriptions....................................................................2685
Table 23-27. USB Full-Speed Last Transaction to End of Frame Timing Register (USBFSEOF) Field Descriptions............2686
Table 23-28. USB Low-Speed Last Transaction to End of Frame Timing Register (USBLSEOF) Field Descriptions........... 2686
Table 23-29. USB Transmit Functional Address Endpoint n Registers (USBTXFUNCADDR[n]) Field Descriptions............ 2687
Table 23-30. USB Transmit Hub Address Endpoint n Registers(USBTXHUBADDR[n]) Field Descriptions..........................2688
Table 23-31. USB Transmit Hub Port Endpoint n Registers(USBTXHUBPORT[n]) Field Descriptions.................................2689
Table 23-32. USB Receive Functional Address Endpoint n Registers(USBFIFO[n]) Field Descriptions...............................2690
Table 23-33. USB Receive Hub Address Endpoint n Registers (USBRXHUBADDR[n]) Field Descriptions......................... 2691
Table 23-34. USB Receive Hub Port Endpoint n Register (USBRXHUBPORT[n]) Field Descriptions.................................. 2692
Table 23-35. USB Control and Status Endpoint 0 Low Register (USBCSRL0) in Host Mode Field Descriptions................. 2693
Table 23-36. USB Control and Status Endpoint 0 Low Register (USBCSRL0) in Device Mode Field Descriptions..............2694
Table 23-37. USB Control and Status Endpoint 0 High Register (USBCSRH0) in Host Mode Field Descriptions................ 2696

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Table 23-38. USB Control and Status Endpoint 0 High Register (USBCSRH0) in Device Mode Field Descriptions............ 2697
Table 23-39. USB Receive Byte Count Endpoint 0 Register (USBCOUNT0) Field Descriptions.......................................... 2698
Table 23-40. USB Type Endpoint 0 Register (USBTYPE0) Field Descriptions..................................................................... 2698
Table 23-41. USB NAK Limit Register (USBNAKLMT) Field Descriptions............................................................................ 2699
Table 23-42. USB Maximum Transmit Data Endpoint n Registers (USBTXMAXP[n]) Field Descriptions............................. 2700
Table 23-43. USB Transmit Control and Status Endpoint n Low Register (USBTXCSRL[n]) in Host Mode Field
Descriptions....................................................................................................................................................................... 2701
Table 23-44. USB Transmit Control and Status Endpoint n Low Register (USBTXCSRL[n]) in Device Mode Field
Descriptions....................................................................................................................................................................... 2702
Table 23-45. USB Transmit Control and Status Endpoint n High Register (USBTXCSRH[n]) in Host Mode Field
Descriptions....................................................................................................................................................................... 2704
Table 23-46. USB Transmit Control and Status Endpoint n High Register (USBTXCSRH[n]) in Device Mode Field
Descriptions....................................................................................................................................................................... 2705
Table 23-47. USB Maximum Receive Data Endpoint n Registers (USBRXMAXP[n]) Field Descriptions............................. 2706
Table 23-48. USB Receive Control and Status Endpoint n Low Register (USBRXCSRL[n]) in Host Mode Field
Descriptions....................................................................................................................................................................... 2707
Table 23-49. USB Receive Control and Status Endpoint n Low Register (USBRX CSRL[n]) in Device Mode Field
Descriptions....................................................................................................................................................................... 2708
Table 23-50. USB Receive Control and Status Endpoint n High Register (USBRXCSRH[n]) in Host Mode Field
Descriptions....................................................................................................................................................................... 2710
Table 23-51. USB Receive Control and Status Endpoint n High Register (USBRXCSRH[n]) in Device Mode Field
Descriptions........................................................................................................................................................................2711
Table 23-52. USB Receive Byte Count Endpoint n Register (USBRXCOUNT[n]) Field Descriptions................................... 2712
Table 23-53. USB Host Transmit Configure Type Endpoint n Registers (USBTXTYPE[n]) Field Descriptions..................... 2713
Table 23-54. USB Host Transmit Interval Endpoint n Registers (USBTXINTERVAL[n]) Frame Numbers.............................2714
Table 23-55. USB Host Transmit Interval Endpoint n Registers (USBTXINTERVAL[n]) Field Descriptions.......................... 2714
Table 23-56. USB Host Configure Receive Type Endpoint n Register (USBRXTYPE[n]) Field Descriptions....................... 2715
Table 23-57. USB Host Receive Polling Interval Endpoint n Registers (USBRXINTERVAL[n]) Frame Numbers................. 2716
Table 23-58. USB Host Receive Polling Interval Endpoint n Registers (USBRXINTERVAL[n]) Field Descriptions...............2716
Table 23-59. USB Request Packet Count in Block Transfer Endpoint n Registers (USBRQPKTCOUNT[n]) Field
Descriptions....................................................................................................................................................................... 2717
Table 23-60. USB Receive Double Packet Buffer Disable Register (USBRXDPKTBUFDIS) Field Descriptions.................. 2718
Table 23-61. USB Transmit Double Packet Buffer Disable Register (USBTXDPKTBUFDIS) Field Descriptions..................2719
Table 23-62. USB External Power Control Register (USBEPC) Field Descriptions.............................................................. 2720
Table 23-63. USB External Power Control Raw Interrupt Status Register (USBEPCRIS) Field Descriptions.......................2722
Table 23-64. USB External Power Control Interrupt Mask Register (USBEPCIM) Field Descriptions.................................. 2723
Table 23-65. USB External Power Control Interrupt Status and Clear Register (USBEPCISC) Field Descriptions.............. 2724
Table 23-66. USB Device RESUME Raw Interrupt Status Register (USBDRRIS) Field Descriptions.................................. 2725
Table 23-67. USB Device RESUME Raw Interrupt Status Register (USBDRRIS) Field Descriptions.................................. 2726
Table 23-68. USB Device RESUME Interrupt Status and Clear Register (USBDRISC) Field Descriptions.......................... 2727
Table 23-69. USB General-Purpose Control and Status Register (USBGPCS) Field Descriptions...................................... 2728
Table 23-70. USB DMA Select Register (USBDMASEL) Field Descriptions......................................................................... 2729
Table 23-71. USB Registers to Driverlib Functions................................................................................................................2731
Table 24-1. uPP Signal Description....................................................................................................................................... 2753
Table 24-2. CPU/CLA/uPP-DMA Address Map..................................................................................................................... 2761
Table 24-3. CPU/CLA/uPP-DMA Address Map..................................................................................................................... 2761
Table 24-4. uPP Parameters Useful for System Tuning........................................................................................................ 2763
Table 24-5. UPP Base Address Table....................................................................................................................................2763
Table 24-6. UPP_REGS Registers........................................................................................................................................ 2764
Table 24-7. UPP_REGS Access Type Codes........................................................................................................................2764
Table 24-8. PID Register Field Descriptions.......................................................................................................................... 2766
Table 24-9. PERCTL Register Field Descriptions..................................................................................................................2767
Table 24-10. CHCTL Register Field Descriptions.................................................................................................................. 2769
Table 24-11. IFCFG Register Field Descriptions....................................................................................................................2770
Table 24-12. IFIVAL Register Field Descriptions................................................................................................................... 2772
Table 24-13. THCFG Register Field Descriptions..................................................................................................................2773
Table 24-14. RAWINTST Register Field Descriptions........................................................................................................... 2775
Table 24-15. ENINTST Register Field Descriptions...............................................................................................................2777
Table 24-16. INTENSET Register Field Descriptions............................................................................................................ 2779
Table 24-17. INTENCLR Register Field Descriptions............................................................................................................ 2781
Table 24-18. CHIDESC0 Register Field Descriptions............................................................................................................2783

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Table 24-19. CHIDESC1 Register Field Descriptions............................................................................................................2784

Table 24-20. CHIDESC2 Register Field Descriptions............................................................................................................2785
Table 24-21. CHIST0 Register Field Descriptions................................................................................................................. 2786
Table 24-22. CHIST1 Register Field Descriptions................................................................................................................. 2787
Table 24-23. CHIST2 Register Field Descriptions................................................................................................................. 2788
Table 24-24. CHQDESC0 Register Field Descriptions.......................................................................................................... 2789
Table 24-25. CHQDESC1 Register Field Descriptions.......................................................................................................... 2790
Table 24-26. CHQDESC2 Register Field Descriptions.......................................................................................................... 2791
Table 24-27. CHQST0 Register Field Descriptions............................................................................................................... 2792
Table 24-28. CHQST1 Register Field Descriptions............................................................................................................... 2793
Table 24-29. CHQST2 Register Field Descriptions............................................................................................................... 2794
Table 24-30. GINTEN Register Field Descriptions................................................................................................................ 2795
Table 24-31. GINTFLG Register Field Descriptions.............................................................................................................. 2796
Table 24-32. GINTCLR Register Field Descriptions.............................................................................................................. 2797
Table 24-33. DLYCTL Register Field Descriptions.................................................................................................................2798
Table 24-34. UPP Registers to Driverlib Functions................................................................................................................2798
Table 25-1. Configuration for EMIF1 and EMIF2 Modules.....................................................................................................2802
Table 25-2. EMIF Pins Used to Access Both SDRAM and Asynchronous Memories........................................................... 2807
Table 25-3. EMIF Pins Specific to SDRAM............................................................................................................................2807
Table 25-4. EMIF Pins Specific to Asynchronous Memory.................................................................................................... 2808
Table 25-5. EMIF SDRAM Commands.................................................................................................................................. 2808
Table 25-6. Truth Table for SDRAM Commands....................................................................................................................2809
Table 25-7. 16-bit EMIF Address Pin Connections................................................................................................................ 2811
Table 25-8. Description of the SDRAM Configuration Register (SDRAM_CR)......................................................................2812
Table 25-9. Description of the SDRAM Refresh Control Register (SDRAM_RCR)............................................................... 2812
Table 25-10. Description of the SDRAM Timing Register (SDRAM_TR)...............................................................................2812
Table 25-11. Description of the SDRAM Self Refresh Exit Timing Register (SDR_EXT_TMNG)..........................................2813
Table 25-12. SDRAM LOAD MODE REGISTER Command................................................................................................. 2813
Table 25-13. Refresh Urgency Levels....................................................................................................................................2815
Table 25-14. Mapping from Logical Address to EMIF Pins for 32-bit SDRAM.......................................................................2820
Table 25-15. Mapping from Logical Address to EMIF Pins for 16-bit SDRAM.......................................................................2820
Table 25-16. Normal Mode vs. Select Strobe Mode.............................................................................................................. 2821
Table 25-17. Description of the Asynchronous m Configuration Register (ASYNC_CSn_CR)............................................. 2823
Table 25-18. Description of the Asynchronous Wait Cycle Configuration Register (ASYNC_WCCR).................................. 2824
Table 25-19. Description of EMIF Interrupt Mask Set Register (INT_MSK_SET)..................................................................2824
Table 25-20. Description of EMIF Interrupt Mast Clear Register (INT_MSK_CLR)............................................................... 2825
Table 25-21. Asynchronous Read Operation in Normal Mode.............................................................................................. 2825
Table 25-22. Asynchronous Write Operation in Normal Mode...............................................................................................2827
Table 25-23. Asynchronous Read Operation in Select Strobe Mode.................................................................................... 2829
Table 25-24. Asynchronous Write Operation in Select Strobe Mode.....................................................................................2831
Table 25-25. Interrupt Monitor and Control Bit Fields............................................................................................................ 2834
Table 25-26. SR Field Value For EMIF to K4S641632H-TC(L)70 Interface...........................................................................2837
Table 25-27. SDRAM_TR Field Calculations for EMIF to K4S641632H-TC(L)70 Interface.................................................. 2838
Table 25-28. RR Calculation for EMIF to K4S641632H-TC(L)70 Interface........................................................................... 2839
Table 25-29. RR Calculation for EMIF to K4S641632H-TC(L)70 Interface........................................................................... 2839
Table 25-30. SDRAM_CR Field Values For EMIF to K4S641632H-TC(L)70 Interface..........................................................2840
Table 25-31. AC Characteristics for a Read Access..............................................................................................................2841
Table 25-32. AC Characteristics for a Write Access.............................................................................................................. 2841
Table 25-33. EMIF Base Address Table................................................................................................................................ 2844
Table 25-34. EMIF_REGS Registers..................................................................................................................................... 2845
Table 25-35. EMIF_REGS Access Type Codes.................................................................................................................... 2845
Table 25-36. RCSR Register Field Descriptions....................................................................................................................2846
Table 25-37. ASYNC_WCCR Register Field Descriptions.................................................................................................... 2847
Table 25-38. SDRAM_CR Register Field Descriptions..........................................................................................................2848
Table 25-39. SDRAM_RCR Register Field Descriptions....................................................................................................... 2850
Table 25-40. ASYNC_CS2_CR Register Field Descriptions................................................................................................. 2851
Table 25-41. ASYNC_CS3_CR Register Field Descriptions................................................................................................. 2853
Table 25-42. ASYNC_CS4_CR Register Field Descriptions................................................................................................. 2855
Table 25-43. SDRAM_TR Register Field Descriptions.......................................................................................................... 2857
Table 25-44. TOTAL_SDRAM_AR Register Field Descriptions.............................................................................................2858
Table 25-45. TOTAL_SDRAM_ACTR Register Field Descriptions........................................................................................ 2859

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Table 25-46. SDR_EXT_TMNG Register Field Descriptions.................................................................................................2860

Table 25-47. INT_RAW Register Field Descriptions.............................................................................................................. 2861
Table 25-48. INT_MSK Register Field Descriptions.............................................................................................................. 2862
Table 25-49. INT_MSK_SET Register Field Descriptions..................................................................................................... 2863
Table 25-50. INT_MSK_CLR Register Field Descriptions..................................................................................................... 2864
Table 25-51. EMIF1_CONFIG_REGS Registers................................................................................................................... 2865
Table 25-52. EMIF1_CONFIG_REGS Access Type Codes.................................................................................................. 2865
Table 25-53. EMIF1LOCK Register Field Descriptions..........................................................................................................2866
Table 25-54. EMIF1COMMIT Register Field Descriptions.....................................................................................................2867
Table 25-55. EMIF1MSEL Register Field Descriptions..........................................................................................................2868
Table 25-56. EMIF1ACCPROT0 Register Field Descriptions................................................................................................2869
Table 25-57. EMIF2_CONFIG_REGS Registers................................................................................................................... 2870
Table 25-58. EMIF2_CONFIG_REGS Access Type Codes.................................................................................................. 2870
Table 25-59. EMIF2LOCK Register Field Descriptions..........................................................................................................2871
Table 25-60. EMIF2COMMIT Register Field Descriptions.....................................................................................................2872
Table 25-61. EMIF2ACCPROT0 Register Field Descriptions................................................................................................2873
Table 25-62. EMIF Registers to Driverlib Functions.............................................................................................................. 2873
Table 26-1. Global Signals and Mux Selection...................................................................................................................... 2881
Table 26-2. Local Signals and Mux Selection........................................................................................................................ 2883
Table 26-3. CLB Output Signal Multiplexer Table.................................................................................................................. 2886
Table 26-4. Output Table........................................................................................................................................................2888
Table 26-5. Input Table.......................................................................................................................................................... 2889
Table 26-6. Ports Tied Off to Prevent Combinatorial Loops...................................................................................................2889
Table 26-7. Counter Block Operating Modes.........................................................................................................................2892
Table 26-8. HLC Event List.................................................................................................................................................... 2897
Table 26-9. HLC Instruction Address Ranges........................................................................................................................2898
Table 26-10. HLC Instruction Format.....................................................................................................................................2898
Table 26-11. HLC Instruction Description...............................................................................................................................2898
Table 26-12. HLC Register Encoding.................................................................................................................................... 2899
Table 26-13. Non-Memory Mapped Register Addresses.......................................................................................................2901
Table 26-14. CLB Base Address Table (C28)........................................................................................................................ 2905
Table 26-15. CLB_LOGIC_CONFIG_REGS Registers......................................................................................................... 2906
Table 26-16. CLB_LOGIC_CONFIG_REGS Access Type Codes.........................................................................................2906
Table 26-17. CLB_COUNT_RESET Register Field Descriptions.......................................................................................... 2908
Table 26-18. CLB_COUNT_MODE_1 Register Field Descriptions....................................................................................... 2909
Table 26-19. CLB_COUNT_MODE_0 Register Field Descriptions....................................................................................... 2910
Table 26-20. CLB_COUNT_EVENT Register Field Descriptions...........................................................................................2911
Table 26-21. CLB_FSM_EXTRA_IN0 Register Field Descriptions........................................................................................2912
Table 26-22. CLB_FSM_EXTERNAL_IN0 Register Field Descriptions.................................................................................2913
Table 26-23. CLB_FSM_EXTERNAL_IN1 Register Field Descriptions.................................................................................2914
Table 26-24. CLB_FSM_EXTRA_IN1 Register Field Descriptions........................................................................................2915
Table 26-25. CLB_LUT4_IN0 Register Field Descriptions.....................................................................................................2916
Table 26-26. CLB_LUT4_IN1 Register Field Descriptions.....................................................................................................2917
Table 26-27. CLB_LUT4_IN2 Register Field Descriptions.....................................................................................................2918
Table 26-28. CLB_LUT4_IN3 Register Field Descriptions.....................................................................................................2919
Table 26-29. CLB_FSM_LUT_FN1_0 Register Field Descriptions........................................................................................2920
Table 26-30. CLB_FSM_LUT_FN2 Register Field Descriptions............................................................................................2921
Table 26-31. CLB_LUT4_FN1_0 Register Field Descriptions............................................................................................... 2922
Table 26-32. CLB_LUT4_FN2 Register Field Descriptions................................................................................................... 2923
Table 26-33. CLB_FSM_NEXT_STATE_0 Register Field Descriptions.................................................................................2924
Table 26-34. CLB_FSM_NEXT_STATE_1 Register Field Descriptions.................................................................................2925
Table 26-35. CLB_FSM_NEXT_STATE_2 Register Field Descriptions.................................................................................2926
Table 26-36. CLB_MISC_CONTROL Register Field Descriptions........................................................................................ 2927
Table 26-37. CLB_OUTPUT_LUT_0 Register Field Descriptions......................................................................................... 2929
Table 26-38. CLB_OUTPUT_LUT_1 Register Field Descriptions......................................................................................... 2930
Table 26-39. CLB_OUTPUT_LUT_2 Register Field Descriptions......................................................................................... 2931
Table 26-40. CLB_OUTPUT_LUT_3 Register Field Descriptions......................................................................................... 2932
Table 26-41. CLB_OUTPUT_LUT_4 Register Field Descriptions......................................................................................... 2933
Table 26-42. CLB_OUTPUT_LUT_5 Register Field Descriptions......................................................................................... 2934
Table 26-43. CLB_OUTPUT_LUT_6 Register Field Descriptions......................................................................................... 2935
Table 26-44. CLB_OUTPUT_LUT_7 Register Field Descriptions......................................................................................... 2936

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Table 26-45. CLB_HLC_EVENT_SEL Register Field Descriptions....................................................................................... 2937

Table 26-46. CLB_LOGIC_CONTROL_REGS Registers......................................................................................................2938
Table 26-47. CLB_LOGIC_CONTROL_REGS Access Type Codes..................................................................................... 2938
Table 26-48. CLB_LOAD_EN Register Field Descriptions.................................................................................................... 2940
Table 26-49. CLB_LOAD_ADDR Register Field Descriptions............................................................................................... 2941
Table 26-50. CLB_LOAD_DATA Register Field Descriptions................................................................................................ 2942
Table 26-51. CLB_INPUT_FILTER Register Field Descriptions............................................................................................ 2943
Table 26-52. CLB_IN_MUX_SEL_0 Register Field Descriptions...........................................................................................2945
Table 26-53. CLB_LCL_MUX_SEL_1 Register Field Descriptions........................................................................................2947
Table 26-54. CLB_LCL_MUX_SEL_2 Register Field Descriptions........................................................................................2948
Table 26-55. CLB_BUF_PTR Register Field Descriptions.....................................................................................................2949
Table 26-56. CLB_GP_REG Register Field Descriptions...................................................................................................... 2950
Table 26-57. CLB_OUT_EN Register Field Descriptions...................................................................................................... 2951
Table 26-58. CLB_GLBL_MUX_SEL_1 Register Field Descriptions..................................................................................... 2952
Table 26-59. CLB_GLBL_MUX_SEL_2 Register Field Descriptions..................................................................................... 2953
Table 26-60. CLB_INTR_TAG_REG Register Field Descriptions..........................................................................................2954
Table 26-61. CLB_LOCK Register Field Descriptions........................................................................................................... 2955
Table 26-62. CLB_DBG_R0 Register Field Descriptions.......................................................................................................2956
Table 26-63. CLB_DBG_R1 Register Field Descriptions.......................................................................................................2957
Table 26-64. CLB_DBG_R2 Register Field Descriptions.......................................................................................................2958
Table 26-65. CLB_DBG_R3 Register Field Descriptions.......................................................................................................2959
Table 26-66. CLB_DBG_C0 Register Field Descriptions.......................................................................................................2960
Table 26-67. CLB_DBG_C1 Register Field Descriptions.......................................................................................................2961
Table 26-68. CLB_DBG_C2 Register Field Descriptions.......................................................................................................2962
Table 26-69. CLB_DBG_OUT Register Field Descriptions....................................................................................................2963
Table 26-70. CLB_DATA_EXCHANGE_REGS Registers..................................................................................................... 2965
Table 26-71. CLB_DATA_EXCHANGE_REGS Access Type Codes.....................................................................................2965
Table 26-72. CLB_PUSH_y Register Field Descriptions....................................................................................................... 2966
Table 26-73. CLB_PULL_y Register Field Descriptions........................................................................................................ 2967
Table 26-74. CLB Registers to Driverlib Functions................................................................................................................ 2967

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www.ti.com Read This First

Preface
Read This First

About This Manual

This Technical Reference Manual (TRM) details the integration, the environment, the functional description, and
the programming models for each peripheral and subsystem in the device.
The TRM should not be considered a substitute for the data sheet, rather a companion guide that should be
used alongside the device-specific data sheet to understand the details to program the device. The primary
purpose of the TRM is to abstract the programming details of the device from the data sheet. This allows
the data sheet to outline the high-level features of the device without unnecessary information about register
descriptions or programming models.

Note
Texas Instruments is transitioning to use more inclusive terminology. Some language may be different
than what you expect to see for certain technology areas.

Notational Conventions
This document uses the following conventions.
• Hexadecimal numbers can be shown with the suffix h or the prefix 0x. For example, the following number is
40 hexadecimal (decimal 64): 40h or 0x40.
• Registers in this document are shown in figures and described in tables.
– Each register figure shows a rectangle divided into fields that represent the fields of the register. Each field
is labeled with its bit name, its beginning and ending bit numbers above, and its read/write properties with
default reset value below. A legend explains the notation used for the properties.
– Reserved bits in a register figure can have one of multiple meanings:
• Not implemented on the device
• Reserved for future device expansion
• Reserved for TI testing
• Reserved configurations of the device that are not supported
– Writing nondefault values to the Reserved bits could cause unexpected behavior and should be avoided.
Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
Related Documentation From Texas Instruments
For a complete listing of related documentation and development-support tools for these devices, visit the
Texas Instruments website at http://www.ti.com. Additionally, the TMS320C28x DSP CPU and Instruction Set
Reference Guide and the TMS320C28x Floating Point Unit and Instruction Set Reference Guide must be used in
conjunction with this TRM.
Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.

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Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
Trademarks
TI E2E™, C2000™, Code Composer Studio™, Texas Instruments™, and controlSUITE™ are trademarks of Texas
Instruments.
USB Specification Revision 2.0™ is a trademark of Compaq Computer Corp.
All trademarks are the property of their respective owners.

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www.ti.com C2000™ Microcontrollers Software Support

Chapter 1
C2000™ Microcontrollers Software Support

This chapter discusses the C2000Ware for the C2000™ microcontrollers. The C2000Ware can be downloaded
from: www.ti.com/tool/C2000WARE

1.1 Introduction.................................................................................................................................................................76
1.2 C2000Ware Structure................................................................................................................................................. 76
1.3 Documentation............................................................................................................................................................76
1.4 Devices........................................................................................................................................................................ 76
1.5 Libraries...................................................................................................................................................................... 76
1.6 Code Composer Studio™ Integrated Development Environment (IDE)................................................................76
1.7 SysConfig and PinMUX Tool......................................................................................................................................77

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1.1 Introduction
C2000Ware for the C2000™ microcontrollers is a cohesive set of development software and documentation
designed to minimize software development time. From device-specific drivers and libraries to device peripheral
examples, C2000Ware provides a solid foundation to begin development and evaluation of your product.
C2000Ware can be downloaded from: www.ti.com/tool/C2000WARE
1.2 C2000Ware Structure
The C2000Ware software package is organized into the following directory structure as shown in Table 1-1.
Table 1-1. C2000Ware Root Directories
Directory Name Description
boards Contains the hardware design schematics, BOM, Gerber files, and documentation for C2000 controlCARDS.
device_support Contains all device-specific support files, bit field headers and device development user's guides.
docs Contains the C2000Ware package user's guides and the HTML index page of all package documentation.
driverlib Contains the device-specific driver library and driver-based peripheral examples.
libraries Contains the device-specific and core libraries.

1.3 Documentation
Within C2000Ware, there is an extensive amount of development documentation ranging from board design
documentation, to library user's guides, to driver API documentation. The "boards" directory contains all the
hardware design, BOM, Gerber files, and more for controlCARDs. To assist with locating the necessary
documentation, an HTML page is provided that contains a full list of all the documents in the C2000Ware
package. Locate this page in the "docs" directory.
1.4 Devices
C2000Ware contains the necessary software and documentation to jumpstart development for C2000™
microcontrollers. Each device includes device-specific common source files, peripheral example projects, bit
field headers, and if available, a device peripheral driver library. Additionally, documentation is provided for each
device on how to set up a CCS project, as well as give an overview of all the included example projects and
assist with troubleshooting. For devices with a driver library, documentation is also included that details all the
peripheral APIs available.
To learn more about C2000™ microcontrollers, visit: www.ti.com/c2000.
1.5 Libraries
The libraries included in C2000Ware range from fixed-point and floating-point math libraries, to specialized DSP
libraries, as well as calibration libraries. Each library includes documentation and examples, where applicable.
Additionally, the Flash API files and boot ROM source code are located in the "libraries" directory.
1.6 Code Composer Studio™ Integrated Development Environment (IDE)
Code Composer Studio™ is an integrated development environment (IDE) that supports TI's microcontroller and
embedded processors portfolio. The Code Composer Studio™ IDE comprises a suite of tools used to develop
and debug embedded applications. The latest version of Code Composer Studio™ IDE can be obtained at:
www.ti.com/ccstudio
All projects and examples in C2000Ware are built for and tested with the Code Composer Studio™ IDE.
Although the Code Composer Studio™ IDE is not included with the C2000Ware installer, Code Composer
Studio™ IDE is easily obtainable in a variety of versions.

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1.7 SysConfig and PinMUX Tool

To help simplify configuration challenges and accelerate software development, Texas Instruments™ created
SysConfig, an intuitive and comprehensive collection of graphical utilities for configuring pins, peripherals,
subsystems, and other components. SysConfig helps you manage, expose, and resolve conflicts visually so that
you have more time to create differentiated applications.
The tool's output includes C header and code files that can be used with C2000Ware examples or used to
configure custom software.
The SysConfig tool automatically selects the pinmux settings that satisfy the entered requirements. The
SysConfig tool is delivered integrated in the Code Composer Studio™ IDE, in the C2000Ware GPIO example,
as a standalone installer, or can be used by way of the cloud tools portal at: dev.ti.com

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C28x Processor www.ti.com

Chapter 2
C28x Processor

This chapter contains a short description of the C28x processor and extended instruction sets.
Further information can be found in the following documents:
• TMS320C28x CPU and Instruction Set Reference Guide
• TMS320C28x Extended Instruction Sets Technical Reference Manual
• Accelerators: Enhancing the Capabilities of the C2000 MCU Family Technical Brief
• TMS320C28x FPU Primer Application Report

2.1 Introduction.................................................................................................................................................................79
2.2 C28X Related Collateral............................................................................................................................................. 79
2.3 Features.......................................................................................................................................................................79
2.4 Floating-Point Unit......................................................................................................................................................80
2.5 Trigonometric Math Unit (TMU)................................................................................................................................. 80
2.6 Viterbi, Complex Math, and CRC Unit II (VCU-II)......................................................................................................81

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2.1 Introduction
The C28x CPU is a 32-bit fixed-point processor. This device draws from the best features of digital signal
processing, reduced instruction set computing (RISC), microcontroller architectures, firmware, and tool sets.
For more information on CPU architecture and instruction set, see the TMS320C28x CPU and Instruction Set
Reference Guide.
2.2 C28X Related Collateral

Foundational Materials
• C2000 Academy - C28x
• C2000 C28x Migration from COFF to EABI
• C2000 C28x Optimization Guide
• C2000 Performance Tips and Tricks
• C2000 Software Guide
• CGT Data Blocking C2000
• Enhancing the Computational Performance of the C2000™ Microcontroller Family Application Report
• How fast is your 32-bit MCU?

Getting Started Materials

• C2000 Multicore Development User Guide
• C2000 VCU, Viterbi, Complex Math, and CRC (Video)
• C2000Ware - CLAMath
• C2000Ware - FPU Fast RTS
• C2000Ware - FPU Library
• C2000Ware - Fast Integer Division
• C2000Ware - Fixed Point Library
• C2000Ware - IQMath
• C2000Ware - VCU Library
• C28x Context Save and Restore
• CRC Engines in C2000 Devices Application Report
• Migrating Software From 8-Bit (Byte) Addressable CPU's to C28x CPU Application Report
• TMS320C28x Extended Instruction Sets Application Report
• TMS320C28x FPU Primer Application Report
• Texas Instruments F2837xD Peripheral Driver Library
2.3 Features
The CPU features include a modified Harvard architecture and circular addressing. The RISC features
are single-cycle instruction execution, register-to-register operations, and modified Harvard architecture. The
microcontroller features include ease of use through an intuitive instruction set, byte packing and unpacking,
and bit manipulation. The modified Harvard architecture of the CPU enables instruction and data fetches to be
performed in parallel. The CPU can read instructions and data while it writes data simultaneously to maintain the
single-cycle instruction operation across the pipeline.

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2.4 Floating-Point Unit

The C28x plus floating-point (C28x+FPU) processor extends the capabilities of the C28x fixed-point CPU by
adding registers and instructions to support IEEE single-precision floating point operations.
Devices with the C28x+FPU include the standard C28x register set plus an additional set of floating-point unit
registers. The additional floating-point unit registers are the following:
• Eight floating-point result registers, RnH (where n = 0–7)
• Floating-point Status Register (STF)
• Repeat Block Register (RB)
All of the floating-point registers, except the repeat block register, are shadowed. This shadowing can be used in
high-priority interrupts for fast context save and restore of the floating-point registers.
For more information, see the TMS320C28x Extended Instruction Sets Technical Reference Manual.
2.5 Trigonometric Math Unit (TMU)
The trigonometric math unit (TMU) extends the capabilities of a C28x+FPU by adding instructions and
leveraging existing FPU instructions to speed up the execution of common trigonometric and arithmetic
operations listed in Table 2-1.
Table 2-1. TMU Supported Instructions
Instructions C Equivalent Operation Pipeline Cycles
MPY2PIF32 RaH,RbH a = b * 2pi 2/3
DIV2PIF32 RaH,RbH a = b / 2pi 2/3
DIVF32 RaH,RbH,RcH a = b/c 5
SQRTF32 RaH,RbH a = sqrt(b) 5
SINPUF32 RaH,RbH a = sin(b*2pi) 4
COSPUF32 RaH,RbH a = cos(b*2pi) 4
ATANPUF32 RaH,RbH a = atan(b)/2pi 4
QUADF32 RaH,RbH,RcH,RdH Operation to assist in calculating ATANPU2 5

No changes have been made to existing instructions, pipeline, or memory bus architecture. All TMU instructions
use the existing FPU register set (R0H to R7H) to carry out the operations.
For more information, see the TMS320C28x Extended Instruction Sets Technical Reference Manual.

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2.6 Viterbi, Complex Math, and CRC Unit II (VCU-II)

The VCU-II is the second-generation Viterbi, Complex Math, and CRC extension to the C28x CPU. The VCU-II
extends the capabilities of the C28x CPU by adding registers and instructions to accelerate the performance of
FFTs and communications-based algorithms. The C28x+VCU-II supports the following algorithm types:
• Viterbi Decoding: Viterbi decoding is commonly used in baseband communications applications. The
Viterbi decode algorithm consists of three main parts: branch metric calculations, compare-select (Viterbi
butterfly), and a traceback operation. Table 2-2 shows a summary of the VCU performance for each of these
operations.
Table 2-2. Viterbi Decode Performance
Viterbi Operation VCU Cycles

Branch Metric Calculation (code rate = 1/2) 1

Branch Metric Calculation (code rate = 1/3) 2p

Viterbi Butterfly (add-compare-select) 2(1)

Traceback per Stage 3(2)

(1) C28x CPU takes 15 cycles per butterfly.

(2) C28x CPU takes 22 cycles per stage.

• Cyclic Redundancy Check: Cyclic redundancy check (CRC) algorithms provide a straightforward method
for verifying data integrity over large data blocks, communication packets, or code sections. The C28x+VCU
can perform 8-bit, 16-bit, 24-bit, and 32-bit CRCs. For example, the VCU can compute the CRC for a block
length of 10 bytes in 10 cycles. A CRC result register contains the current CRC, which is updated whenever a
CRC instruction is executed.
• Complex Math: Complex math is used in many applications, a few are:
– Fast Fourier Transform (FFT): The complex FFT is used in spread spectrum communications, as well as
in many signal processing algorithms.
– Complex filters: Complex filters improve data reliability, transmission distance, and power efficiency. The
C28x+VCU can perform a complex I and Q multiply with coefficients (four multiplies) in a single cycle. In
addition, the C28x+VCU can read/write the real and imaginary parts of 16-bit complex data to memory in a
single cycle.

Table 2-3 shows a summary of a few complex math operations enabled by the VCU-II.
Table 2-3. Complex Math Performance
Complex Math Operation VCU Cycles Notes

Add or Subtract 1 32 +/- 32 = 32-bit (Useful for filters)

Add or Subtract 1 16 +/- 32 = 15-bit (Useful for FFT)

Multiply 2p 16 x 16 = 32-bit

Multiply and Accumulate (MAC) 2p 32 + 32 = 32-bit, 16 x 16 = 32-bit

RPT MAC 2p+N Repeat MAC. Single cycle after the first operation.

Note
Only the CRC-related VCU instructions are supported in future devices. FFT algorithms are available
for the C28x+FPU.

For more information, see the TMS320C28x Extended Instruction Sets Technical Reference Manual.

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Chapter 3
System Control and Interrupt

This chapter explains system control and interrupts found on the MCU. The system control module configures
and manages the overall operation of the device and provides information about the device status. Configurable
features in system control include reset control, NMI operation, power control, clock control, and low-power
modes.

3.1 Introduction.................................................................................................................................................................83
3.2 System Control Functional Description................................................................................................................... 83
3.3 Resets..........................................................................................................................................................................84
3.4 Peripheral Interrupts.................................................................................................................................................. 87
3.5 Exceptions and Non-Maskable Interrupts................................................................................................................99
3.6 Safety Features.........................................................................................................................................................101
3.7 Clocking.....................................................................................................................................................................104
3.8 32-Bit CPU Timers 0/1/2............................................................................................................................................116
3.9 Watchdog Timers...................................................................................................................................................... 118
3.10 Low-Power Modes.................................................................................................................................................. 121
3.11 Memory Controller Module.................................................................................................................................... 125
3.12 Flash and OTP Memory..........................................................................................................................................133
3.13 Dual Code Security Module (DCSM)..................................................................................................................... 147
3.14 JTAG........................................................................................................................................................................ 160
3.15 System Control Register Configuration Restrictions......................................................................................... 160
3.16 Software.................................................................................................................................................................. 161
3.17 System Control Registers......................................................................................................................................166

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3.1 Introduction
On this device, the CPU1 subsystem acts as a master, and by default (upon reset) owns all the configuration
and control. Through software running on CPU1, peripherals and I/Os can be configured to be accessible by the
CPU2 subsystem and the configuration chosen can be locked. All peripherals are available on CPU1, but not all
peripherals are available on CPU2. To see what peripherals can be configured for CPU2, consult the CPUSELn
registers in the DEV_CFG_REGS section.
The PLL clock configuration is also owned by the CPU1 subsystem by default, but a clock control semaphore is
provided by which CPU2 can grab access to the clock configuration registers.
Each CPU has an NMI module to handle different exceptions during run time. If the NMI was on CPU1, any NMI
exception that is unhandled before the NMI Watchdog (NMIWD) timer expiration resets the entire device. If the
NMI was on the CPU2 subsystem, then the CPU2 subsystem alone is reset, in which case the CPU1 subsystem
is informed by another NMI that the CPU2 subsystem was reset because of NMIWD timer expiration.
Each CPU subsystem a watchdog timer module for software to use. Watchdog timer expiration on CPU2 resets
the CPU2 subsystem alone when configured to generate a reset, but watchdog timer expiration on CPU1 resets
the entire device.
Except for a CPU2 standalone internal reset such as CPU2.NMIWD or CPU2.WD each time the device is reset,
the CPU2 subsystem is held under reset until the CPU1 subsystem brings the CPU2 subsystem out of reset.
This is done by the boot ROM software running on the CPU1 core.
This chapter explains the register space of the device system control module that is divided into three
categories:
1. System Control Device Configuration Registers (DEV_CFG_REGS). These registers are mapped to CPU1
only. The base address of these registers on the CPU1 address space begins at 0x5D000.
2. System Control Clock Configuration Registers (CLK_CFG_REGS). These registers are mapped to both
CPU1 and CPU2 address space but access control is based on a Clock Control Semaphore register. The
base address of these registers on both the CPU subsystems begins at 0x5D200.
3. System control CPU Subsystem Registers (CPU_SYS_REGS). These registers are mapped to both the
CPU subsystems. The base address of these registers on both the CPU subsystems begins at 0x5D300.
This chapter explains the system control module on both the CPU subsystems.
3.2 System Control Functional Description
The system control module provides the following capabilities:
• Device identification and configuration registers
• Reset control
• Exceptions and Interrupt control
• Safety and error handling features of the device
• Power control
• Clock control
• Low Power modes
• Security module
• Inter-Processor Communication (IPC)
3.2.1 Device Identification
Device identification registers provide information on device class, device family, revision, part number, pin
count, operating temperature range, package type, and device qualification status.
All of the device information is part of the DEV_CFG_REGS space and is accessible only by the software
running on the CPU1 subsystem.
The control subsystem device identification registers are: PARTIDL, PARTIDH, and REVID.

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A 256-bit Unique ID (UID) is available in UID_REGS. The 256 bits are separated into these registers:
• UID_PSRAND0-5: 192 bits of pseudo-random data
• UID_UNIQUE: 32-bit unique data, the value in this register is unique across all devices with the same
PARTIDH
• UID_CHECKSUM: 32-bit Fletcher checksum of UID_PSRAND0-5 and UID_UNIQUE
• CPU ID: 16-bit location in OTP memory. The value at this location provides the information about the CPU
(CPU1 or CPU2). Refer to the device data sheet for more detail.

3.2.2 Device Configuration Registers

Several registers provide users with configuration information for debug and identification purposes on this MCU.
This information includes the features of the peripheral and how much RAM and FLASH memory is available on
this part.
These registers are part of DEV_CFG_REGS space and are accessible only by the software running on the
CPU1 subsystem.
• DC0 – DC20: Device Configuration or Capabilities registers.
If a particular bit in these registers is set to ‘1’ then the associated/feature or module is available in the
device.
• PERCNF: Peripheral configuration register.
This register configures ADC capabilities, and enables or disables the USB internal PHY.
• CPUID: CPU identification register
This register is available for software to identify on which CPU it is executing.
3.3 Resets
This section explains the types and effects of the different resets on this device.
3.3.1 Reset Sources
Table 3-1 summarizes the various reset signals and their effect on the device.
Table 3-1. Reset Signals
Reset Source CPU1 Core CPU1 CPU2 Core CPU2 CPU2 Held JTAG / IOs XRS Output
Reset Peripherals Reset Peripherals In Reset Debug
(C28x, Reset (C28x, Reset Logic Reset
TMU, FPU, TMU, FPU,
VCU) VCU)
POR Yes Yes Yes Yes Yes Yes Hi-Z Yes
XRS Pin Yes Yes Yes Yes Yes No Hi-Z -
CPU1.WDRS Yes Yes Yes Yes Yes No Hi-Z Yes
CPU1.NMIWDRS Yes Yes Yes Yes Yes No Hi-Z Yes
CPU1.SYSRS Yes Yes Yes Yes Yes No Hi-Z No
(Debugger Reset)
CPU1.SCCRESET Yes Yes Yes Yes Yes No Hi-Z No
CPU2.SYSRS No No Yes Yes No No - No
(Debugger Reset)
CPU2.WDRS No No Yes Yes No No - No
CPU2.NMIWDRS No No Yes Yes No No - No
CPU2.SCCRESET No No Yes Yes No No - No
HIBRESET Yes Yes Yes Yes Yes Yes Isolated No
CPU1.HWBISTRS Yes No No No No No - No
CPU2.HWBISTRS No No Yes No No No - No
TRST No No No No No Yes - No

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The resets can be divided into a few groups:

• Chip-level resets (XRS, POR, CPU1. WDRS, and CPU1. NMIWDRS), which reset all or almost all of the
device.
• System resets (CPU1. SYSRS and CPU1.SCCRESET), which reset a large subset of the device but maintain
some system-level configuration.
• CPU2 subsystem resets (CPU2.SYSRS, CPU2.WDRS, CPU2.NMIWDRS, and CPU2.SCCRESET), which
reset only CPU2 and the peripherals.
• Special resets (HIBRESET, CPU1. HWBISTRS, CPU2.HWBISTRS, and TRST), which enable specific device
functions.
Whenever the CPU1 subsystem is reset, CPU2 and the peripherals are also reset, and CPU2 is held in reset.
CPU1 brings CPU2 out of reset by writing to the CPU2RESCTL register. This is normally done by the boot ROM.
For more details on the boot process, refer to Chapter 4.
After a reset, the reset cause register (RESC) is updated with the reset cause. The bits in this register maintain
their state across multiple resets. The bits can only be cleared by a power-on reset (POR) or by writing ones to
the register. Each CPU has their own RESC register, referred to as CPU1.RESC and CPU2.RESC.
Many peripheral modules have individual resets accessible through the system control registers. For information
about a module's reset state, refer to the appropriate chapter for that module.

Note
After a POR, XRS, CPU1.WDRS, CPU1.NMIWDRS, or HIBRESET, the boot ROMs clear all of the
system and message RAMs on both CPUs. After a CPU2.WDRS or CPU2.NMIWDRS, the CPU2 boot
ROM clears all of the CPU2 system and message RAMs.

3.3.2 External Reset (XRS)

The external reset (XRS) is the main chip-level reset for the device and resets both CPUs, all peripherals and I/O
pin configurations, and most of the system control registers.XRS also holds CPU2 in reset. There is a dedicated
open-drain pin for XRS. This pin can be used to drive reset pins for other ICs in the application, and can
be driven by an external source. The XRS is driven internally during watchdog, NMI, and power-on resets. In
hibernate mode, toggling XRS produces a HIBRESET.
The XRSn bit in the RESC register is set whenever XRS is driven low for any reason. This bit is then cleared by
the boot ROM.
3.3.3 Power-On Reset (POR)
The power-on reset (POR) circuit creates a clean reset throughout the device during power-up, suppressing
glitches on the GPIOs. The XRS pin is held low for the duration of the POR. In most applications, XRS is
held low long enough to reset other system ICs, but some applications can require a longer pulse. In these
cases, XRS can be driven low externally to provide the correct reset duration. A POR resets everything
that XRS does, along with a few other registers – the reset cause register (RESC), the NMI shadow flag
register (NMISHDFLG), the X1 clock counter register (X1CNT), and the hibernate configuration registers
(HIBBOOTMODE, IORESTOREADDR, and LPMCR.M0M1MODE).
After a POR, the POR and XRSn bits in RESC are set. These bits are then cleared by the boot ROM.
3.3.4 Debugger Reset (SYSRS)
During development, it is sometimes necessary to reset the CPU and the peripherals without disconnecting
the debugger or disrupting the system-level configuration. To facilitate this, each CPU has a subsystem reset,
which can be triggered by a debugger using Code Composer Studio™ IDE. The CPU2 subsystem reset
(CPU2.SYSRS) resets only CPU2, the peripherals, and the clock gating and LPM configuration. It does not
hold CPU2 in reset. The CPU1 subsystem reset (CPU1.SYSRS) resets CPU1, the peripherals, many system
control registers (including the clock gating and LPM configuration and the peripherals CPU ownership), and all
I/O pin configurations. It also produces a CPU2.SYSRS and holds CPU2 in reset.

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Neither SYSRS resets the ICEPick debug module, the device capability registers, the clock source and PLL
configurations, the missing clock detection state, the PIE vector fetch error handler address, the NMI flags, the
analog trims, or anything reset only by a POR (see Section 3.3.3).
3.3.5 Watchdog Reset (WDRS)
Each CPU has a watchdog timer that can optionally trigger a reset that lasts for 512 INTOSC1 cycles.
CPU1's watchdog reset (CPU1.WDRS) produces an XRS. CPU2 watchdog reset (CPU2.WDRS) produces a
CPU2.SYSRS and triggers an NMI on CPU1.
After a watchdog reset, the WDRSn bit in RESC is set.
3.3.6 NMI Watchdog Reset (NMIWDRS)
Each CPU has a non-maskable interrupt (NMI) module that detects hardware errors in the system. Each
NMI module has a watchdog timer that triggers a reset, if the CPU does not respond to an error within a
user-specified amount of time. The CPU1 NMI watchdog reset (CPU1.NMIWDRS) produces an XRS. The CPU2
NMI watchdog reset (CPU2.NMIWDRS) produces a CPU2.SYSRS and triggers an NMI on CPU1.
After an NMI watchdog reset, the NMIWDRSn bit in RESC is set.
3.3.7 DCSM Safe Code Copy Reset (SCCRESET)
Each CPU has a dual-zone code security module (DCSM) that blocks read access to certain areas of the Flash
memory. To facilitate CRC checks and copying of CLA code, TI provides ROM functions to securely access
those memory areas. To prevent security breaches, interrupts must be disabled before calling these functions.
If a vector fetch occurs in a safe copy or CRC function, the DCSM triggers a reset. The CPU1 security reset
(CPU1.SCCRESET) is similar to a CPU1.SYSRS, and the CPU2 security reset (CPU2.SCCRESET) is similar to
a CPU2.SYSRS. However, the security reset also resets the debug logic to deny access to a potential attacker.
After a security reset, the SCCRESETn bit in RESC is set.
3.3.8 Hibernate Reset (HIBRESET)
Hibernate is a chip-level low-power mode that gates power to large portions of the device. Waking up from
hibernate involves a special reset (HIBRESET). This reset is similar to a POR except that the I/O pins remain
isolated and the XRS pin is not toggled. (An external XRS toggle during hibernate triggers a HIBRESET). I/O
isolation is disabled in software as part of a special boot ROM flow. For more information on hibernate, refer to
Section 3.10.
After a hibernate reset, the HIBRESETn bit in RESC is set. This bit is then cleared by the boot ROM.
3.3.9 Hardware BIST Reset (HWBISTRS)
Each CPU has a Hardware Built-In Self Test (HWBIST) module that tests the functionality of the CPU. At the end
of the test, it resets the CPU to return it to a working state. This reset (HWBISTRS) only affects the CPU itself.
The peripherals and system control remain as previously configured. The CPU state is restored in software as
part of a special boot ROM flow. For more information on the HWBIST flow, contact your local TI representative.
After a HWBIST reset, the HWBISTn bit in RESC is set. This bit is then cleared by the boot ROM.
3.3.10 Test Reset (TRST)
The ICEPick debug module and associated JTAG logic has a reset (TRST) that is controlled by a dedicated pin.
This reset is normally active unless the user connects a debugger to the device. For more information on the
debug module, see the TI Processors Wiki page on ICEPick: http://processors.wiki.ti.com/index.php/ICEPICK.
The TRST does not have a normal RESC bit, but the TRSTn_pin_status bit indicates the state of the pin.

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3.4 Peripheral Interrupts

This section explains the peripheral interrupt handling on the device. Non-maskable interrupts are covered in
Section 3.5. Software interrupts and emulation interrupts are not covered in this document. For information on
those, see the TMS320C28x CPU and Instruction Set Reference Guide.
3.4.1 Interrupt Concepts
An interrupt is a signal that causes the CPU to pause its current execution and branch to a different piece of
code known as an interrupt service routine (ISR). This is a useful mechanism for handling peripheral events,
and involves less CPU overhead or program complexity than register polling. However, because interrupts are
asynchronous to the program flow, care must be taken to avoid conflicts over resources that are accessed both
in interrupts and in the main program code.
Interrupts propagate to the CPU through a series of flag and enable registers. The flag registers store the
interrupt until it is processed. The enable registers block the propagation of the interrupt. When an interrupt
signal reaches the CPU, the CPU fetches the appropriate ISR address from a list called the vector table.
3.4.2 Interrupt Architecture
The C28x CPU has 14 peripheral interrupt lines. Two of them (INT13 and INT14) are connected directly to
CPU timers 1 and 2, respectively. The remaining 12 are connected to peripheral interrupt signals through the
enhanced Peripheral Interrupt Expansion module (ePIE, or PIE as a shortened version). The PIE multiplexes up
to 16 peripheral interrupts into each CPU interrupt line and also expands the vector table to allow each interrupt
to have an ISR. This allows the CPU to support a large number of peripherals.
An interrupt path is divided into three stages – the peripheral, the PIE, and the CPU. Each stage has enable
and flag registers. This system allows the CPU to handle one interrupt while others are pending, implement and
prioritize nested interrupts in software, and disable interrupts during certain critical tasks.
Figure 3-1 shows the interrupt architecture for this device.
3.4.2.1 Peripheral Stage
Each peripheral has a unique interrupt configuration, which is described in that peripheral's chapter. Some
peripherals allow multiple events to trigger the same interrupt signal. For example, a communications peripheral
can use the same interrupt to indicate that data has been received or that there has been a transmission error.
The cause of the interrupt can be determined by reading the peripheral's status register. Often, the bits in the
status register must be cleared manually before another interrupt is generated.
3.4.2.2 PIE Stage
The PIE provides individual flag and enable register bits for each of the peripheral interrupt signals, which are
sometimes called PIE channels. These channels are grouped according to the associated CPU interrupt. Each
PIE group has one 16-bit enable register (PIEIERx), one 16-bit flag register (PIEIFRx), and one bit in the PIE
acknowledge register (PIEACK). The PIEACK register bit acts as a common interrupt mask for the entire PIE
group.
When the CPU receives an interrupt, the CPU fetches the address of the ISR from the PIE. The PIE returns
the vector for the lowest-numbered channel in the group that is both flagged and enabled. This gives lower-
numbered interrupts a higher priority when multiple interrupts are pending.
If no interrupt is both flagged and enabled, the PIE returns the vector for channel 1. This condition does not
happen unless software changes the state of the PIE while an interrupt is propagating. Section 3.4.4 contains
procedures for safely modifying the PIE configuration once interrupts have been enabled.

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CPU1.TINT0
CPU1.TIMER0
CPU1.LPMINT
LPM Logic CPU1.WAKEINT
CPU1.WD CPU1.NMIWD NMI
CPU1.TINT0 CPU1

INPUTXBAR4 CPU1.XINT1 Control CPU1 INT1

GPIO0
INPUTXBAR5 CPU1.XINT2 Control ePIE To
GPIO1 Input INT12
... INPUTXBAR6 CPU1.XINT3 Control
X-Bar
... INPUTXBAR13 CPU1.XINT4 Control
GPIOx
INPUTXBAR14 CPU1.XINT5 Control
CPU1.TINT1
CPU1.TIMER1 INT13
CPU1.TINT2
CPU1.TIMER2 INT14
IPC
4 Interrupts

Peripherals

CPU1.NMIWD NMI

CPU2
CPU2.XINT1 Control
CPU2.XINT2 Control INT1
To
CPU2.XINT3 Control CPU2
INT12
ePIE
CPU2.XINT4 Control
CPU2.XINT5 Control
CPU2.TINT1
CPU2.LPMINT CPU2.TIMER1 INT13
LPM Logic CPU2.WAKEINT
CPU2.TINT0 CPU2.TINT2
CPU2.WD CPU2.TIMER2 INT14
CPU2.TINT0
CPU2.TIMER0

Figure 3-1. Device Interrupt Architecture

3.4.2.3 CPU Stage

Like the PIE, the CPU provides flag and enable register bits for each of its interrupts. There is one enable
register (IER) and one flag register (IFR), both of which are internal CPU registers. There is also a global
interrupt mask, which is controlled by the INTM bit in the ST1 register. This mask can be set and cleared using
the CPU's SETC instruction. In C code, controlSUITE's DINT and EINT macros can be used for this purpose.
Writes to IER and INTM are atomic operations. In particular, if INTM is cleared, the next instruction in the
pipeline runs with interrupts disabled. No software delays are needed.
3.4.2.4 Dual-CPU Interrupt Handling
Each CPU has a PIE. Both PIEs must be configured independently.
Some interrupts come from shared peripherals that can be owned by either CPU, such as the ADCs and SPIs.
These interrupts are sent to both PIEs regardless of the peripheral's ownership. Thus, a peripheral owned by
one CPU can cause an interrupt on the other CPU if that interrupt is enabled in the other CPU's PIE.

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3.4.3 Interrupt Entry Sequence

Figure 3-2 shows how peripheral interrupts propagate to the CPU.
PIEIERx.1
0
Peripheral
PIEIFRx.1 1
Interrupt
Latch
A

PIEIERx.2
Peripheral 0 Set
PIEIFRx.2 1 PIEACK.x IER.x ST1.INTM
Interrupt
Latch 1 0 1
CPU
B 0 IFR.x 1 0
Interrupt
Latch
Logic

PIEIERx.16
0
Peripheral
PIEIFRx.16 1
Interrupt
Latch
P

Figure 3-2. Interrupt Propagation Path

When a peripheral generates an interrupt (on PIE group x, channel y), the following sequence of events is
triggered:
1. The interrupt is latched in PIEIFRx.y.
2. If PIEIERx.y is set, the interrupt propagates.
3. If PIEACK.x is clear, the interrupt propagates and PIEACK.x is set.
4. The interrupt is latched in IFR.x.
5. If IER.x is set, the interrupt propagates.
6. If INTM is clear, the CPU receives the interrupt.
7. Any instructions in the D2 or later stage of the pipeline are run to completion. Instructions in earlier stages
are flushed.
8. The CPU saves the context on the stack.
9. IFR.x and IER.x are cleared. INTM is set. EALLOW is cleared.
10. The CPU fetches the ISR vector from the PIE. PIEIFRx.y is cleared.
11. The CPU branches to the ISR.

The interrupt latency is the time between PIEIFRx.y latching the interrupt and the first ISR instruction entering
the execution stage of the CPU pipeline. The minimum interrupt latency is 14 SYSCLK cycles. Wait states on the
ISR or stack memories add to the latency. External interrupts add a minimum of two SYSCLK cycles for GPIO
synchronization plus extra time for input qualification (if used). Loops created using the RPT instruction cannot
be interrupted.

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3.4.4 Configuring and Using Interrupts

At power-up, no interrupts are enabled by default. The PIEIER and IER registers are cleared and INTM is set.
The application code is responsible for configuring and enabling all peripheral interrupts.
3.4.4.1 Enabling Interrupts
To enable a peripheral interrupt, perform the following steps:
1. Disable interrupts globally (DINT or SETC INTM).
2. Enable the PIE by setting the ENPIE bit of the PIECTRL register.
3. Write the ISR vector for each interrupt to the appropriate location in the PIE vector table, which can be found
in Section 3.4.6.
4. Set the appropriate PIEIERx bit for each interrupt. The PIE group and channel assignments can be found in
Section 3.4.6.
5. Set the CPU IER bit for any PIE group containing enabled interrupts.
6. Enable the interrupt in the peripheral.
7. Enable interrupts globally (EINT or CLRC INTM).
Step 4 does not apply to the Timer1 and Timer2 interrupts, which connect directly to the CPU.
3.4.4.2 Handling Interrupts
ISRs are similar to normal functions, but must do the following:
1. Save and restore the state of certain CPU registers (if used).
2. Clear the PIEACK bit for the interrupt group.
3. Return using the IRET instruction.
Requirements 1 and 3 are handled automatically by the TMS320C28x C compiler if the function is defined
using the __interrupt keyword. For information on this keyword, see the Keywords section of the TMS320C28x
Optimizing C/C++ Compiler v6.2.4 User's Guide. For information on writing assembly code to handle interrupts,
see the Standard Operation for Maskable Interrupts section of the TMS320C28x CPU and Instruction Set
Reference Guide.
The PIEACK bit for the interrupt group must be cleared manually in user code. This is normally done at the end
of the ISR. If the PIEACK bit is not cleared, the CPU does not receive any further interrupts from that group. This
does not apply to the Timer1 and Timer2 interrupts, which do not go through the PIE.

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3.4.4.3 Disabling Interrupts

To disable all interrupts, set the CPU's global interrupt mask using a DINT or SETC INTM. It is not necessary to
add NOPs after setting INTM or modifying IER – the next instruction executes with interrupts disabled.
Individual interrupts can be disabled using the PIEIERx registers, but care must be taken to avoid race
conditions. If an interrupt signal is already propagating when the PIEIER write completes, it may reach the
CPU and trigger a spurious interrupt condition. To avoid this, use the following procedure:
1. Disable interrupts globally (DINT or SETC INTM).
2. Clear the PIEIER bit for the interrupt.
3. Wait 5 cycles to make sure that any propagating interrupt has reached the CPU IFR register.
4. Clear the CPU IFR bit for the interrupt's PIE group.
5. Clear the PIEACK bit for the interrupt's PIE group.
6. Enable interrupts globally (EINT or CLRC INTM).
Interrupt groups can be disabled using the CPU IER register. This cannot cause a race condition, so no special
procedure is needed.
PIEIFR bits must never be cleared in software since the read/modify/write operation may cause incoming
interrupts to be lost. The only safe way to clear a PIEIFR bit is to have the CPU take the interrupt. The following
procedure can be used to bypass the normal ISR:
1. Disable interrupts globally (DINT or SETC INTM).
2. Modify the PIE vector table to map the PIEIFR bit interrupt vector to an empty ISR. This ISR only contains a
return from interrupt instruction (IRET).
3. Disable the interrupt in the peripheral registers.
4. Enable interrupts globally (EINT or CLRC INTM).
5. Wait for the pending interrupt to be serviced by the empty ISR.
6. Disable interrupts globally.
7. Modify the PIE vector table to map the interrupt vector back to the original ISR.
8. Clear the PIEACK bit for the interrupt's PIE group.
9. Enable interrupts globally.

3.4.4.4 Nesting Interrupts

By default, interrupts do not nest. It is possible to nest and prioritize interrupts via software control of the IER and
PIEIERx registers. Documentation and example code can be found in controlSUITE and on the TI Processors
wiki:
http://processors.wiki.ti.com/index.php/Interrupt_Nesting_on_C28x

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3.4.5 PIE Channel Mapping

Table 3-2 shows the PIE group and channel assignments for each peripheral interrupt. Each row is a group, and each column is a channel within that
group. When multiple interrupts are pending, the lowest-numbered channel is the lowest-numbered group is serviced first. Thus, the interrupts at the top
of the table have the highest priority, and the interrupts at the bottom have the lowest priority.

Note
Cells marked "-" are Reserved

Table 3-2. PIE Channel Mapping

INTx.1 INTx.2 INTx.3 INTx.4 INTx.5 INTx.6 INTx.7 INTx.8 INTx.9 INTx.10 INTx.11 INTx.12 INTx.13 INTx.14 INTx.15 INTx.16
INT1.y ADCA1 ADCB1 ADCC1 XINT1 XINT2 ADCD1 TIMER0 WAKE - - - - IPC1 IPC2 IPC3 IPC4
EPWM1 EPWM2_ EPWM3 EPWM4 EPWM5 EPWM6 EPWM7 EPWM8 EPWM9 EPWM10_ EPWM11_ EPWM12_
INT2.y - - - -
_TZ TZ _TZ _TZ _TZ _TZ _TZ _TZ _TZ TZ TZ TZ
INT3.y EPWM1 EPWM2 EPWM3 EPWM4 EPWM5 EPWM6 EPWM7 EPWM8 EPWM9 EPWM10 EPWM11 EPWM12 - - - -
INT4.y ECAP1 ECAP2 ECAP3 ECAP4 ECAP5 ECAP6 - - - - - - - - - -
INT5.y EQEP1 EQEP2 EQEP3 - CLB1 CLB2 CLB3 CLB4 SDFM1 SDFM2 - - - - - -
SPIA_R SPIB_R MCBSPA MCBSPA MCBSP MCBSP SPIC_R
INT6.y SPIA_TX SPIB_TX SPIC_TX - - - - - -
X X _RX _TX B_RX B_TX X
DMA_C DMA_CH DMA_C DMA_C DMA_C DMA_C
INT7.y - - - - - - - - - -
H1 2 H3 H4 H5 H6
I2CA_FI I2CB_FI SCIC_R SCIC_T SCID_R SCID_T
INT8.y I2CA I2CB - - - - - - UPPA -
FO FO X X X X
SCIA_R SCIB_R
INT9.y SCIA_TX SCIB_TX CANA_0 CANA_1 CANB_0 CANB_1 - - - - - - USBA -
X X
ADCA_E ADCB_E ADCC_E ADCD_EV
INT10.y ADCA2 ADCA3 ADCA4 ADCB2 ADCB3 ADCB4 ADCC2 ADCC3 ADCC4 ADCD2 ADCD3 ADCD4
VT VT VT T
INT11.y CLA1_1 CLA1_2 CLA1_3 CLA1_4 CLA1_5 CLA1_6 CLA1_7 CLA1_8 - - - - - - - -
RAM_CO FLASH_C RAM_AC
FPU FPU CLA CLA
EMIF_ RRECT ORRECT CESS SYS_PLL AUX_PLL
INT12.y XINT3 XINT4 XINT5 - FMC VCU OVER UNDER OVER UNDER
ERROR ABLE_ER ABLE_ER _VIOLATI _SLIP _SLIP
FLOW FLOW FLOW FLOW
ROR ROR ON

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3.4.5.1 PIE Interrupt Priority

3.4.5.1.1 Channel Priority
For every PIE group, the low number channels in the group have the highest priority. For instance in PIE group
1, channel 1.1 has priority over channel 1.3. If those two enabled interrupts occurred simultaneously, channel 1.1
is serviced first with channel 1.3 left pending. Once the ISR for channel 1.1 completes and provided there are no
other enabled and pending interrupts for PIE group 1, channel 1.3 is serviced. However, for the CPU to service
any more interrupts from a PIE group, PIEACK for the group must be cleared. For this specific example, in order
for channel 1.3 to be serviced, channel 1.1’s ISR has to clear PIEACK for group 1.
The following example describes an alternative scenario: channel 1.1 is currently being serviced by the CPU,
channel 1.3 is pending and before channel 1.1’s ISR completes, channel 1.2 which is enabled also comes in.
Since channel 1.2 has a higher priority than channel 1.3, the CPU services channel 1.2 and channel 1.3 is still
remains pending. Using the steps from the Interrupt Entry Sequence (Section 3.4.3), channel 1.2 interrupt can
happen as late as step 10 (The CPU fetches the ISR vector from the PIE. PIEIFRx.y is cleared) and channel 1.2
is still serviced ahead of channel 1.3.
3.4.5.1.2 Group Priority
Generally, the lowest channel in the lowest PIE group has the highest priority. An example of this is channels 1.1
and 2.1. Those two channels have the highest priority in their respective groups. If the interrupts for those two
enabled channels happened simultaneously and provided there are no other enabled and pending interrupts,
channel 1.1 is serviced first by the CPU with channel 2.1 left pending.
However, there are cases where channel priority supersedes group priority. This special case happens
depending on which step the CPU is currently at in the Interrupt Entry Sequence (Section 3.4.3).
The following describes an example of this special case.
The CPU is about to service channel 2.3 and is currently going through the steps in the Interrupt Entry Sequence
(Section 3.4.3).
1. As the CPU reaches step 10 (The CPU fetches the ISR vector from the PIE. PIEIFRx.y is cleared), two
enabled interrupts: channel 1.1 and channel 2.1 come in.
2. Due to channel priority, channel 2.1 is serviced ahead of channel 2.3. However, group priority dictates that
channel 1.1 be serviced ahead of channels 2.1 and 2.3.
3. Channel priority supersedes here and channel 2.1 is serviced ahead of 1.1 and 2.3.
4. After channel 2.1 completes, channel 1.1 is serviced followed by channel 2.3.
Group priority is only guaranteed if no interrupts are currently being serviced, that is, the Interrupt Entry
Sequence (Section 3.4.3) is not executing.

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3.4.6 Vector Tables

Table 3-3 shows the CPU interrupt vector table. The vectors for INT1 – INT12 are not used in this device. The
reset vector is fetched from the boot ROM instead of from this table.
Table 3-4 shows the PIE vector table.
Table 3-3. CPU Interrupt Vectors
Name Vector ID Address Size (x16) Description Core priority ePIE group
Priority
Reset 0 0x0000 0D00 2 Reset is always fetched from location 1 (Highest) -
0x003F_FFC0 in Boot ROM
INT1 1 0x0000 0D02 2 Not used. See PIE Group 1 5 -
INT2 2 0x0000 0D04 2 Not used. See PIE Group 2 6 -
INT3 3 0x0000 0D06 2 Not used. See PIE Group 3 7 -
INT4 4 0x0000 0D08 2 Not used. See PIE Group 4 8 -
INT5 5 0x0000 0D0A 2 Not used. See PIE Group 5 9 -
INT6 6 0x0000 0D0C 2 Not used. See PIE Group 6 10 -
INT7 7 0x0000 0D0E 2 Not used. See PIE Group 7 11 -
INT8 8 0x0000 0D10 2 Not used. See PIE Group 8 12 -
INT9 9 0x0000 0D12 2 Not used. See PIE Group 9 13 -
INT10 10 0x0000 0D14 2 Not used. See PIE Group 10 14 -
INT11 11 0x0000 0D16 2 Not used. See PIE Group 11 15 -
INT12 12 0x0000 0D18 2 Not used. See PIE Group 12 16 -
INT13 13 0x0000 0D1A 2 CPU TIMER1 Interrupt 17 -
INT14 14 0x0000 0D1C 2 CPU TIMER2 Interrupt 18 -
(for TI/RTOS use)
DATALOG 15 0x0000 0D1E 2 CPU Data Logging Interrupt 19 (lowest) -
RTOSINT 16 0x0000 0D20 2 CPU Real-Time OS Interrupt 4 -
RSVD 17 0x0000 0D22 2 Reserved 2 -
NMI 18 0x0000 0D24 2 Non-Maskable Interrupt 3 -
ILLEGAL 19 0x0000 0D26 2 Illegal Instruction (ITRAP) - -
USER 1 20 0x0000 0D28 2 User-Defined Trap - -
USER 2 21 0x0000 0D2A 2 User-Defined Trap - -
USER 3 22 0x0000 0D2C 2 User-Defined Trap - -
USER 4 23 0x0000 0D2E 2 User-Defined Trap - -
USER 5 24 0x0000 0D30 2 User-Defined Trap - -
USER 6 25 0x0000 0D32 2 User-Defined Trap - -
USER 7 26 0x0000 0D34 2 User-Defined Trap - -
USER 8 27 0x0000 0D36 2 User-Defined Trap - -
USER 9 28 0x0000 0D38 2 User-Defined Trap - -
USER 10 29 0x0000 0D3A 2 User-Defined Trap - -
USER 11 30 0x0000 0D3C 2 User-Defined Trap - -
USER 12 31 0x0000 0D3E 2 User-Defined Trap - -

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Table 3-4. PIE Interrupt Vectors

Name Vector ID Address Size (x16) Description Core Priority ePIE Group
Priority
PIE Group 1 Vectors - Muxed into CPU INT1
INT1.1 32 0x0000 0D40 2 ADCA1 interrupt 5 1 (Highest)
INT1.2 33 0x0000 0D42 2 ADCB1 interrupt 5 2
INT1.3 34 0x0000 0D44 2 ADCC1 interrupt 5 3
INT1.4 35 0x0000 0D46 2 XINT1 interrupt 5 4
INT1.5 36 0x0000 0D48 2 XINT2 interrupt 5 5
INT1.6 37 0x0000 0D4A 2 ADCD1 interrupt 5 6
INT1.7 38 0x0000 0D4C 2 TIMER0 interrupt 5 7
INT1.8 39 0x0000 0D4E 2 WAKE interrupt 5 8
INT1.9 128 0x0000 0E00 2 Reserved 5 9
INT1.10 129 0x0000 0E02 2 Reserved 5 10
INT1.11 130 0x0000 0E04 2 Reserved 5 11
INT1.12 131 0x0000 0E06 2 Reserved 5 12
INT1.13 132 0x0000 0E08 2 IPC1 interrupt 5 13
INT1.14 133 0x0000 0E0A 2 IPC2 interrupt 5 14
INT1.15 134 0x0000 0E0C 2 IPC3 interrupt 5 15
INT1.16 135 0x0000 0E0E 2 IPC4 interrupt 5 16 (Lowest)
PIE Group 2 Vectors - Muxed into CPU INT2
INT2.1 40 0x0000 0D50 2 EPWM1_TZ interrupt 6 1 (Highest)
INT2.2 41 0x0000 0D52 2 EPWM2_TZ interrupt 6 2
INT2.3 42 0x0000 0D54 2 EPWM3_TZ interrupt 6 3
INT2.4 43 0x0000 0D56 2 EPWM4_TZ interrupt 6 4
INT2.5 44 0x0000 0D58 2 EPWM5_TZ interrupt 6 5
INT2.6 45 0x0000 0D5A 2 EPWM6_TZ interrupt 6 6
INT2.7 46 0x0000 0D5C 2 EPWM7_TZ interrupt 6 7
INT2.8 47 0x0000 0D5E 2 EPWM8_TZ interrupt 6 8
INT2.9 136 0x0000 0E10 2 EPWM9_TZ interrupt 6 9
INT2.10 137 0x0000 0E12 2 EPWM10_TZ interrupt 6 10
INT2.11 138 0x0000 0E14 2 EPWM11_TZ interrupt 6 11
INT2.12 139 0x0000 0E16 2 EPWM12_TZ interrupt 6 12
INT2.13 140 0x0000 0E18 2 Reserved 6 13
INT2.14 141 0x0000 0E1A 2 Reserved 6 14
INT2.15 142 0x0000 0E1C 2 Reserved 6 15
INT2.16 143 0x0000 0E1E 2 Reserved 6 16 (Lowest)
PIE Group 3 Vectors - Muxed into CPU INT3
INT3.1 48 0x0000 0D60 2 EPWM1 interrupt 7 1 (Highest)
INT3.2 49 0x0000 0D62 2 EPWM2 interrupt 7 2
INT3.3 50 0x0000 0D64 2 EPWM3 interrupt 7 3
INT3.4 51 0x0000 0D66 2 EPWM4 interrupt 7 4
INT3.5 52 0x0000 0D68 2 EPWM5 interrupt 7 5
INT3.6 53 0x0000 0D6A 2 EPWM6 interrupt 7 6
INT3.7 54 0x0000 0D6C 2 EPWM7 interrupt 7 7
INT3.8 55 0x0000 0D6E 2 EPWM8 interrupt 7 8
INT3.9 144 0x0000 0E20 2 EPWM9 interrupt 7 9

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Table 3-4. PIE Interrupt Vectors (continued)

Name Vector ID Address Size (x16) Description Core Priority ePIE Group
Priority
INT3.10 145 0x0000 0E22 2 EPWM10 interrupt 7 10
INT3.11 146 0x0000 0E24 2 EPWM11 interrupt 7 11
INT3.12 147 0x0000 0E26 2 EPWM12 interrupt 7 12
INT3.13 148 0x0000 0E28 2 Reserved 7 13
INT3.14 149 0x0000 0E2A 2 Reserved 7 14
INT3.15 150 0x0000 0E2C 2 Reserved 7 15
INT3.16 151 0x0000 0E2E 2 Reserved 7 16 (Lowest)
PIE Group 4 Vectors - Muxed into CPU INT4
INT4.1 56 0x0000 0D70 2 ECAP1 interrupt 8 1 (Highest)
INT4.2 57 0x0000 0D72 2 ECAP2 interrupt 8 2
INT4.3 58 0x0000 0D74 2 ECAP3 interrupt 8 3
INT4.4 59 0x0000 0D76 2 ECAP4 interrupt 8 4
INT4.5 60 0x0000 0D78 2 ECAP5 interrupt 8 5
INT4.6 61 0x0000 0D7A 2 ECAP6 interrupt 8 6
INT4.7 62 0x0000 0D7C 2 Reserved 8 7
INT4.8 63 0x0000 0D7E 2 Reserved 8 8
INT4.9 152 0x0000 0E30 2 Reserved 8 9
INT4.10 153 0x0000 0E32 2 Reserved 8 10
INT4.11 154 0x0000 0E34 2 Reserved 8 11
INT4.12 155 0x0000 0E36 2 Reserved 8 12
INT4.13 156 0x0000 0E38 2 Reserved 8 13
INT4.14 157 0x0000 0E3A 2 Reserved 8 14
INT4.15 158 0x0000 0E3C 2 Reserved 8 15
INT4.16 159 0x0000 0E3E 2 Reserved 8 16 (Lowest)
PIE Group 5 Vectors - Muxed into CPU INT5
INT5.1 64 0x0000 0D80 2 EQEP1 interrupt 9 1 (Highest)
INT5.2 65 0x0000 0D82 2 EQEP2 interrupt 9 2
INT5.3 66 0x0000 0D84 2 EQEP3 interrupt 9 3
INT5.4 67 0x0000 0D86 2 Reserved 9 4
INT5.5 68 0x0000 0D88 2 CLB1 Interrupt 9 5
INT5.6 69 0x0000 0D8A 2 CLB2 Interrupt 9 6
INT5.7 70 0x0000 0D8C 2 CLB3 Interrupt 9 7
INT5.8 71 0x0000 0D8E 2 CLB4 Interrupt 9 8
INT5.9 160 0x0000 0E40 2 SD1 interrupt 9 9
INT5.10 161 0x0000 0E42 2 SD2 interrupt 9 10
INT5.11 162 0x0000 0E44 2 Reserved 9 11
INT5.12 163 0x0000 0E46 2 Reserved 9 12
INT5.13 164 0x0000 0E48 2 Reserved 9 13
INT5.14 165 0x0000 0E4A 2 Reserved 9 14
INT5.15 166 0x0000 0E4C 2 Reserved 9 15
INT5.16 167 0x0000 0E4E 2 Reserved 9 16 (Lowest)
PIE Group 6 Vectors - Muxed into CPU INT6
INT6.1 72 0x0000 0D90 2 SPIA_RX interrupt 10 1 (Highest)
INT6.2 73 0x0000 0D92 2 SPIA_TX interrupt 10 2

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Table 3-4. PIE Interrupt Vectors (continued)

Name Vector ID Address Size (x16) Description Core Priority ePIE Group
Priority
INT6.3 74 0x0000 0D94 2 SPIB_RX interrupt 10 3
INT6.4 75 0x0000 0D96 2 SPIB_TX interrupt 10 4
INT6.5 76 0x0000 0D98 2 MCBSPA_RX interrupt 10 5
INT6.6 77 0x0000 0D9A 2 MCBSPA_TX interrupt 10 6
INT6.7 78 0x0000 0D9C 2 MCBSPB_RX interrupt 10 7
INT6.8 79 0x0000 0D9E 2 MCBSPB_TX interrupt 10 8
INT6.9 168 0x0000 0E50 2 SPIC_RX interrupt 10 9
INT6.10 169 0x0000 0E52 2 SPIC_TX interrupt 10 10
INT6.11 170 0x0000 0E54 2 Reserved 10 11
INT6.12 171 0x0000 0E56 2 Reserved 10 12
INT6.13 172 0x0000 0E58 2 Reserved 10 13
INT6.14 173 0x0000 0E5A 2 Reserved 10 14
INT6.15 174 0x0000 0E5C 2 Reserved 10 15
INT6.16 175 0x0000 0E5E 2 Reserved 10 16 (Lowest)
PIE Group 7 Vectors - Muxed into CPU INT7
INT7.1 80 0x0000 0DA0 2 DMA_CH1 interrupt 11 1 (Highest)
INT7.2 81 0x0000 0DA2 2 DMA_CH2 interrupt 11 2
INT7.3 82 0x0000 0DA4 2 DMA_CH3 interrupt 11 3
INT7.4 83 0x0000 0DA6 2 DMA_CH4 interrupt 11 4
INT7.5 84 0x0000 0DA8 2 DMA_CH5 interrupt 11 5
INT7.6 85 0x0000 0DAA 2 DMA_CH6 interrupt 11 6
INT7.7 86 0x0000 0DAC 2 Reserved 11 7
INT7.8 87 0x0000 0DAE 2 Reserved 11 8
INT7.9 176 0x0000 0E60 2 Reserved 11 9
INT7.10 177 0x0000 0E62 2 Reserved 11 10
INT7.11 178 0x0000 0E64 2 Reserved 11 11
INT7.12 179 0x0000 0E66 2 Reserved 11 12
INT7.13 180 0x0000 0E68 2 Reserved 11 13
INT7.14 181 0x0000 0E6A 2 Reserved 11 14
INT7.15 182 0x0000 0E6C 2 Reserved 11 15
INT7.16 183 0x0000 0E6E 2 Reserved 11 16 (Lowest)
PIE Group 8 Vectors - Muxed into CPU INT8
INT8.1 88 0x0000 0DB0 2 I2CA interrupt 12 1 (Highest)
INT8.2 89 0x0000 0DB2 2 I2CA_FIFO interrupt 12 2
INT8.3 90 0x0000 0DB4 2 I2CB interrupt 12 3
INT8.4 91 0x0000 0DB6 2 I2CB_FIFO interrupt 12 4
INT8.5 92 0x0000 0DB8 2 SCIC_RX interrupt 12 5
INT8.6 93 0x0000 0DBA 2 SCIC_TX interrupt 12 6
INT8.7 94 0x0000 0DBC 2 SCID_RX interrupt 12 7
INT8.8 95 0x0000 0DBE 2 SCID_TX interrupt 12 8
INT8.9 184 0x0000 0E70 2 Reserved 12 9
INT8.10 185 0x0000 0E72 2 Reserved 12 10
INT8.11 186 0x0000 0E74 2 Reserved 12 11
INT8.12 187 0x0000 0E76 2 Reserved 12 12

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Table 3-4. PIE Interrupt Vectors (continued)

Name Vector ID Address Size (x16) Description Core Priority ePIE Group
Priority
INT8.13 188 0x0000 0E78 2 Reserved 12 13
INT8.14 189 0x0000 0E7A 2 Reserved 12 14
INT8.15 190 0x0000 0E7C 2 UPPA interrupt (CPU1 only) 12 15
INT8.16 191 0x0000 0E7E 2 Reserved 12 16 (Lowest)
PIE Group 9 Vectors - Muxed into CPU INT9
INT9.1 96 0x0000 0DC0 2 SCIA_RX interrupt 13 1 (Highest)
INT9.2 97 0x0000 0DC2 2 SCIA_TX interrupt 13 2
INT9.3 98 0x0000 0DC4 2 SCIB_RX interrupt 13 3
INT9.4 99 0x0000 0DC6 2 SCIB_TX interrupt 13 4
INT9.5 100 0x0000 0DC8 2 CANA interrupt 0 13 5
INT9.6 101 0x0000 0DCA 2 CANA interrupt 1 13 6
INT9.7 102 0x0000 0DCC 2 CANB interrupt 0 13 7
INT9.8 103 0x0000 0DCE 2 CANB interrupt 1 13 8
INT9.9 192 0x0000 0E80 2 Reserved 13 9
INT9.10 193 0x0000 0E82 2 Reserved 13 10
INT9.11 194 0x0000 0E84 2 Reserved 13 11
INT9.12 195 0x0000 0E86 2 Reserved 13 12
INT9.13 196 0x0000 0E88 2 Reserved 13 13
INT9.14 197 0x0000 0E8A 2 Reserved 13 14
INT9.15 198 0x0000 0E8C 2 USBA interrupt (CPU1 only) 13 15
INT9.16 199 0x0000 0E8E 2 Reserved 13 16 (Lowest)
PIE Group 10 Vectors - Muxed into CPU INT10
INT10.1 104 0x0000 0DD0 2 ADCA_EVT interrupt 14 1 (Highest)
INT10.2 105 0x0000 0DD2 2 ADCA2 interrupt 14 2
INT10.3 106 0x0000 0DD4 2 ADCA3 interrupt 14 3
INT10.4 107 0x0000 0DD6 2 ADCA4 interrupt 14 4
INT10.5 108 0x0000 0DD8 2 ADCB_EVT interrupt 14 5
INT10.6 109 0x0000 0DDA 2 ADCB2 interrupt 14 6
INT10.7 110 0x0000 0DDC 2 ADCB3 interrupt 14 7
INT10.8 111 0x0000 0DDE 2 ADCB4 interrupt 14 8
INT10.9 200 0x0000 0E90 2 ADCC_EVT interrupt 14 9
INT10.10 201 0x0000 0E92 2 ADCC2 interrupt 14 10
INT10.11 202 0x0000 0E94 2 ADCC3 interrupt 14 11
INT10.12 203 0x0000 0E96 2 ADCC4 interrupt 14 12
INT10.13 204 0x0000 0E98 2 ADCD_EVT interrupt 14 13
INT10.14 205 0x0000 0E9A 2 ADCD2 interrupt 14 14
INT10.15 206 0x0000 0E9C 2 ADCD3 interrupt 14 15
INT10.16 207 0x0000 0E9E 2 ADCD4 interrupt 14 16 (Lowest)
PIE Group 11 Vectors - Muxed into CPU INT11
INT11.1 112 0x0000 0DE0 2 CLA1_1 interrupt 15 1 (Highest)
INT11.2 113 0x0000 0DE2 2 CLA1_2 interrupt 15 2
INT11.3 114 0x0000 0DE4 2 CLA1_3 interrupt 15 3
INT11.4 115 0x0000 0DE6 2 CLA1_4 interrupt 15 4
INT11.5 116 0x0000 0DE8 2 CLA1_5 interrupt 15 5

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Table 3-4. PIE Interrupt Vectors (continued)

Name Vector ID Address Size (x16) Description Core Priority ePIE Group
Priority
INT11.6 117 0x0000 0DEA 2 CLA1_6 interrupt 15 6
INT11.7 118 0x0000 0DEC 2 CLA1_7 interrupt 15 7
INT11.8 119 0x0000 0DEE 2 CLA1_8 interrupt 15 8
INT11.9 208 0x0000 0EA0 2 Reserved 15 9
INT11.10 209 0x0000 0EA2 2 Reserved 15 10
INT11.11 210 0x0000 0EA4 2 Reserved 15 11
INT11.12 211 0x0000 0EA6 2 Reserved 15 12
INT11.13 212 0x0000 0EA8 2 Reserved 15 13
INT11.14 213 0x0000 0EAA 2 Reserved 15 14
INT11.15 214 0x0000 0EAC 2 Reserved 15 15
INT11.16 215 0x0000 0EAE 2 Reserved 15 16 (Lowest)
PIE Group 12 Vectors - Muxed into CPU INT12
INT12.1 120 0x0000 0DF0 2 XINT3 interrupt 16 1 (Highest)
INT12.2 121 0x0000 0DF2 2 XINT4 interrupt 16 2
INT12.3 122 0x0000 0DF4 2 XINT5 interrupt 16 3
INT12.4 123 0x0000 0DF6 2 Reserved 16 4
INT12.5 124 0x0000 0DF8 2 Reserved 16 5
INT12.6 125 0x0000 0DFA 2 VCU interrupt 16 6
INT12.7 126 0x0000 0DFC 2 FPU_OVERFLOW interrupt 16 7
INT12.8 127 0x0000 0DFE 2 FPU_UNDERFLOW interrupt 16 8
INT12.9 216 0x0000 0EB0 2 EMIF_ERROR interrupt 16 9
INT12.10 217 0x0000 0EB2 2 RAM_CORRECTABLE_ERROR 16 10
interrupt
INT12.11 218 0x0000 0EB4 2 FLASH_CORRECTABLE_ERROR 16 11
interrupt
INT12.12 219 0x0000 0EB6 2 RAM_ACCESS_VIOLATION 16 12
interrupt
INT12.13 220 0x0000 0EB8 2 SYS_PLL_SLIP interrupt 16 13
INT12.14 221 0x0000 0EBA 2 AUX_PLL_SLIP interrupt 16 14
INT12.15 222 0x0000 0EBC 2 CLA_OVERFLOW interrupt 16 15
INT12.16 223 0x0000 0EBE 2 CLA_UNDERFLOW interrupt 16 16 (Lowest)

3.5 Exceptions and Non-Maskable Interrupts

This section describes system-level error conditions that can trigger a non-maskable interrupt (NMI). The
interrupt allows the application to respond to the error.
3.5.1 Configuring and Using NMIs
Each CPU has its own NMI module. An incoming NMI sets a status bit in the NMIFLG register and starts the
NMI watchdog counter. This counter is clocked by the SYSCLK, and if it reaches the value in the NMIWDPRD
register, it triggers an NMI watchdog reset (NMIWDRS). To prevent this, the NMI handler must clear the flag bit
using the NMIFLGCLR register. Once all flag bits are clear, the NMIINT bit in the NMIFLG register may also be
cleared to allow future NMIs to be taken.
The NMI module is enabled by the boot ROM during the startup process. To respond to NMIs, an NMI handler
vector must be written to the PIE vector table.

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3.5.2 Emulation Considerations

The NMI watchdog counter behaves as follows under debug conditions:

CPU Suspended When the CPU is suspended, the NMI watchdog counter is suspended.
Run-Free Mode When the CPU is placed in run-free mode, the NMI watchdog counter
resumes operation as normal.
Real-Time Single-Step Mode When the CPU is in real-time single-step mode, the NMI watchdog
counter is suspended. The counter remains suspended even within real-
time interrupts.
Real-Time Run-Free Mode When the CPU is in real-time run-free mode, the NMI watchdog counter
operates as normal.

3.5.3 NMI Sources

There are several types of hardware errors that can trigger an NMI. Additional information about the error is
usually available from the module that detects it.
3.5.3.1 Missing Clock Detection
The missing clock detection logic monitors OSCCLK for failure. If the OSCCLK source stops, the PLL is
bypassed, OSCCLK is connected to INTOSC1, and NMIs are fired to both CPUs . For more information on
missing clock detection, see Section 3.6.2.
3.5.3.2 RAM Uncorrectable ECC Error
A single-bit parity error, double-bit ECC data error, or single-bit ECC address error in a RAM read triggers
an NMI. This applies to CPU, CLA, and DMA reads. Single-bit ECC data errors do not trigger an NMI, but
can optionally trigger a normal peripheral interrupt. For more information on RAM error detection, see Section
3.11.1.8.
3.5.3.3 Flash Uncorrectable ECC Error
A double-bit ECC data error or single-bit ECC address error in a Flash read triggers an NMI. Single-bit ECC data
errors do not trigger an NMI, but can optionally trigger a normal peripheral interrupt. For more information on
Flash error detection, see Section 3.12.10.
3.5.3.4 NMI Vector Fetch Mismatch
Each CPU's Peripheral Interrupt Expansion module (PIE) has redundant vector tables. If a mismatch in these
tables is detected during a vector fetch, a user-specified error handler is run instead of the ISR. If the vector
fetch was caused by an NMI, a second NMI is fired to the other CPU. Mismatches for other interrupts do not
trigger an NMI. For more information about the vector address check, see Section 3.6.4.
3.5.3.5 CPU2 Watchdog or NMI Watchdog Reset
A watchdog reset or NMI watchdog reset on CPU2 triggers an NMI on CPU1. Since a CPU1 reset also resets
CPU2, this NMI source is not available on CPU2.
Watchdog interrupts do not trigger an NMI.
3.5.4 Illegal Instruction Trap (ITRAP)
If the CPU tries to execute an illegal instruction, the CPU generates a special interrupt called an illegal
instruction trap (ITRAP). This interrupt is non-maskable and has a vector in the PIE vector table. For more
information about ITRAPs, see the Illegal-Instruction Trap in the TMS320C28x DSP CPU and Instruction Set
Reference Guide.

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Note
A RAM fetch access violation triggers an ITRAP in addition to the normal peripheral interrupt for RAM
access violations. The CPU handles the ITRAP first.

3.6 Safety Features

This section gives details on features that monitor device operation during run-time to detect any error in
operation.
3.6.1 Write Protection on Registers
3.6.1.1 LOCK Protection on System Configuration Registers
Several system configuration registers are protected from spurious CPU writes by “LOCK” registers. Once these
associated LOCK register bits are set the respective locked registers can no longer be modified by software. See
specific register descriptions for details.
3.6.1.2 EALLOW Protection
Several control registers are protected from spurious CPU writes by the EALLOW protection mechanism. The
EALLOW bit in status register 1 (ST1) indicates the state of protection as shown in Table 3-5.
Table 3-5. Access to EALLOW-Protected Registers
EALLOW Bit CPU Writes CPU Reads JTAG Writes JTAG Reads
0 Ignored Allowed Allowed(1) Allowed
1 Allowed Allowed Allowed Allowed

(1) The EALLOW bit is overridden via the JTAG port, allowing full access of protected registers during debug from the Code Composer
Studio™ IDE interface.

At reset, the EALLOW bit is cleared, enabling EALLOW protection. While protected, all writes to protected
registers by the CPU are ignored and only CPU reads, JTAG reads, and JTAG writes are allowed. If this bit
is set, by executing the EALLOW instruction, the CPU is allowed to write freely to protected registers. After
modifying registers, the registers can once again be protected by executing the EDIS instruction to clear the
EALLOW bit.
3.6.2 Missing Clock Detection Logic
The missing clock detect (MCD) logic detects OSCCLK failure, using INTOSC1 as the reference clock source.
This circuit only detects complete loss of OSCCLK and doesn’t do any detection of frequency drift on the
OSCCLK.
This circuit monitors the OSCLK (primary clock) using the 10 MHz clock provided by the INTOSC1 (secondary
clock) as a backup clock. This circuit functions as following.
1. The primary clock (OSCCLK) clock keeps ticking a 7-bit counter (named as MCDPCNT). This counter is
asynchronously reset with XRS.
2. The secondary clock (INTOSC1) clock keeps ticking a 13-bit counter (named as MCDSCNT). This counter is
asynchronously reset with XRS.
3. Each time MCDPCNT overflows, the MCDSCNT counter is reset. Thus, if OSCCLK is present or is not
slower than INTOSC1 by a factor of 64, MCDSCNT never overflows.
4. If OSCCLK stops for some reason or is slower than INTOSC1 by at least a factor of 64, the MCDSCNT
overflows and a missing clock condition is detected on OSCCLK.
5. The above check is continuously active, unless the MCD is disabled using MCDCR register (by making the
MCLKOFF bit 1)
6. If the circuit ever detects a missing OSCCLK, the following occurs:
• The MCLKSTS flag is set.
• The MCDSCNT counter is frozen to prevent further missing clock detection.
• The CLOCKFAIL signal goes high, which generates TRIP events to PWM modules and fires NMIs to
CPU1.NMIWD and CPU2.NMIWD.

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• PLL is forcefully bypassed and OSCCLK is switched to INTOSC1 (after the PLLSYSCLK divider).
PLLMULT is zeroed out automatically in this case.
• While the MCLKSTS bit is set, the OSCCLKSRCSEL bits have no effect and OSCCLK is forcefully
connected to INTOSC1.
• PLLRAWCLK going to the system is switched to INTOSC1 automatically.
7. If the MCLKCLR bit is written (W = 1 bit), MCLKSTS bit are cleared and OSCCLK source is decided by the
OSCCLKSRCSEL bits. Writing to MCLKCLR also clears the MCDPCNT and MCDSCNT counters to allow
the circuit re-evaluate missing clock detection. To lock the PLL after a missing clock detection, switch the
clock source to INTOSC1 (using OSCCLKSRCSEL register), do a MCLKCLR, and re-lock the PLL.
8. The MCD is enabled at power up. There is no support for a missing clock detection, if INTOSC2 is failed
from the device power-up.
Figure 3-3 shows the missing clock logic functional flow.

Secondary Clock CLOCKFAIL

INTOSC1 Missing
Clock INTOSC1
Detect
Primary Clock (MCD)
Logic
Low
OSCCLK Power
INTOSC2 Source Mode
Select OSCCLK Ckt
Ckt
X1/X2

CLKSRCCTL1.OSCCLRSRCSEL /1,
Switch
SYSPLL /2,
Ckt
/4
Mux
PLLRAWCLK ..
(glitch- PLLSYSCLK
/124
PLL Locking free)
/126
Registers Control
Ckt

Clock Dividers

Clock Sources SYSPLLCTL1/2/3,

SYSPLLMULT,
SYSPLLSTS

Figure 3-3. Missing Clock Detection Logic

Note
On a complete clock failure when OSCCLK is dead, it can take a maximum time of 8192 INTOSC1
cycles (that is, 0.8192 ms) before the CLOCKFAIL signal goes high, after which:
• NMI is generated
• OSCCLK is switched to INTOSC1
• PWM trip happens

3.6.3 PLLSLIP Detection

The PLL SLIP detection on this device can detect if the PLL reference clock goes too high or too slow while PLL
is locked. An interrupt to both the CPUs is triggered as shown in the ePIE table in Section 3.4. Apart from the
interrupt to both the CPUs, the PLLSTS.SLIP bit is set for user software to check the error.
The SLIP detection is available on both SYSPLL and AUXPLL.

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3.6.4 CPU1 and CPU2 PIE Vector Address Validity Check

The ePIE vector table on each CPU is duplicated into these two parts:
• Main ePIE Vector Table mapped from 0xD00 to 0xEFF in the C28x memory space
• Redundant ePIE Vector Table mapped from 0x1000D00 to 0x1000EFF in the C28x memory space
Following is the behavior of accesses to the ePIE memories:
• Data Writes to Main Vector Table: Writes to both memories
• Data Writes to Redundant Vector Table: Writes only to the Redundant Vector Table
• Vector Fetch: Data from both the vector tables are compared
• Data Read: Can read the Main and Redundant vector table separately
On every vector fetch from the ePIE, a hardware comparison (no cycle penalty is incurred to do the comparison)
of both the vector table outputs is performed and if there is a mismatch between the two vector table outputs, the
following occurs:
1. If the PIEVERRADDR register (default value 0x3F FFFF) is not initialized, the default error handler at
address 0x3FFFBE gets executed. But, when the PIEVERRADDR register is initialized to the address of the
user-defined routine, the user-defined routine is executed instead of the default error handler.
Note: Each CPU has a copy of the PIE Vector Fetch Error Handler register (CPU1.PIEVERRADDR and
CPU2.PIEVERRADDR).
2. Hardware also generates EPWM Trip signals that trips the PWM outputs using TRIPIN15.
3. An NMI to the other CPU is sent, if the current mismatch is during a vector fetch. For example, on an NMI
vector fetch error for CPU2 an NMI is also fired to CPU1.NMIWD.
If there is no mismatch, the correct vector is jammed onto the C28x program control.
3.6.5 NMIWDs
Each CPU has user-programmable NMIWD period registers, in which users can set a limit on how much time
they want to allocate for the device to acknowledge the NMI. If the NMI is not acknowledged, the NMI causes a
device reset.
3.6.6 ECC and Parity Enabled RAMs, Shared RAMs Protection
Each CPU subsystem has different RAM blocks. Few RAM blocks are ECC-enabled and others are parity-
enabled. All single-bit errors in ECC RAM are auto-corrected and an error counter is incremented every time
a single bit error is detected. If the error counter reaches a predefined user configured limit, an interrupt is
generated to the corresponding CPU. A typical threshold setting to avoid triggering on transient errors which are
corrected, but identify persistent faults is 10. Refer to Section 3.11 for more details on RAM errors.
All uncorrectable double-bit errors end up triggering an NMI to corresponding CPUs.
3.6.7 ECC Enabled Flash Memory
When ECC is programmed and enabled, Flash single-bit errors are corrected automatically by ECC logic before
giving data to the CPU, but the errors are not corrected in Flash memory. Flash memory still contains wrong data
until another erase/program operation happens to correct the Flash contents. Irrespective of whether the error
interrupt is enabled or disabled, single-bit errors are always corrected before giving data to the CPU. When the
interrupt is disabled, users can check the single-bit error counter register for any single-bit error occurrences.
The error counter stops incrementing once the value is equal to the threshold+1. It is always suggested to set
the threshold register to a non-zero value so that the error counter can increment. It is up to the user to decide
the threshold value at which to reprogram the Flash with the correct data. A typical threshold setting to avoid
triggering on transient errors that are corrected, but identify persistent faults is 10. When ECC is programmed
and enabled, Flash uncorrectable errors end up triggering an NMI to the respective CPU. Please refer to Section
3.11 for more details on Flash error correction and error catching mechanisms.

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3.6.8 ERRORSTS Pin

The ERRORSTS pin is an ‘always output’ pin and remains low until an error is detected inside the chip. On
an error, the ERRORSTS pin goes high until the corresponding internal error status flag for that error source is
cleared. Figure 3-4 shows the functionality of the ERRORSTS pin.
The ERRORSTS pin is tri-stated until the chip power rails ramp up to the lower operational limit. As the
ERRORSTS pin is an active-high pin, users who care about the state of this pin during power-up must connect
an external pull-down on this pin.
CPU1's NMIWD Shadow flags

CPU1.NMIWD.NMISHDFLG.Bit-0

CPU1.NMIWD.NMISHDFLG.Bit-1

CPU1.NMIWD.NMISHDFLG.Bit-15

CPU2's NMIWD Shadow flags

ERROR

CPU2.NMIWD.NMISHDFLG.Bit-0

CPU2.NMIWD.NMISHDFLG.Bit-1

CPU2.NMIWD.NMISHDFLG.Bit-15

Figure 3-4. ERRORSTS Pin Diagram

3.7 Clocking
This section explains the clock sources and clock domains on this device, and how to configure them for
application use. Figure 3-5 provides an overview of the device clocking system.

Note
While the CLK_CFG_REGS registers are mapped to both CPU1 and CPU2, there are not unique
settings per CPU, and the impact of these registers is global. Only one CPU can read/write to these
registers at a time; this is controlled by the Clock Control Semaphore Register (CLKSEM) in the
CLK_CFG_REGs. This register is unique in that either CPU can read and write to the register.
The default/2 divider for ePWMs and EMIFs is not shown in Figure 3-5.

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INTOSC1 To watchdog timers

CLKSRCCTL1 SYSPLLCTL1 SYSCLKDIVSEL

INTOSC2

SYSCLK To GS RAMs, GPIOs,

OSCCLK PLLSYSCLK
Divider NMIWDs, and IPC
X1 (XTAL) System PLL PLLRAWCLK

CPU1.SYSCLK CPU1 CPU1.CPUCLK To local memories

CPU2.SYSCLK CPU2 CPU2.CPUCLK To local memories

CPU1.SYSCLK To ePIEs, LS RAMs,

CLA message RAMs,
CPU2.SYSCLK and DCSMs

One per SYSCLK peripheral

CPU1.PCLKCRx CPUSELx

PERx.SYSCLK To peripherals

CPU2.PCLKCRx

One per LSPCLK peripheral

LOSPCP
CPU1.PCLKCRx CPUSELx

LSP To SCIs, SPIs, and

PERx.LSPCLK
Divider McBSPs

CPU2.PCLKCRx

One per ePWM

EPWMCLKDIV CPUSELx
CPU1.PCLKCRx

PLLSYSCLK /1
EPWMCLK To ePWMs
/2

CPU2.PCLKCRx
To CLBs

HRPWM

CPU1.PCLKCRx

HRPWMCLK To HRPWM Registers

One per CAN module

CPUSELx

CLKSRCCTL2

CAN Bit Clock To CANs

AUXCLKIN

CLKSRCCTL2 AUXPLLCTL1 AUXCLKDIVSEL

AUXOSCCLK AUXCLK AUXPLLCLK To USB bit clock

Divider
Auxiliary PLL AUXPLLRAWCLK

Figure 3-5. Clocking System

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3.7.1 Clock Sources

All of the clocks in the device are derived from one of four clock sources.
3.7.1.1 Primary Internal Oscillator (INTOSC2)
At power-up, the device is clocked from an on-chip 10 MHz oscillator (INTOSC2). INTOSC2 is the primary
internal clock source, and is the default system clock at reset. It is used to run the boot ROM and can be used
as the system clock source for the application. Note that INTOSC2's frequency tolerance is too loose to meet the
timing requirements for CAN and USB, so an external clock must be used to support those features.
3.7.1.2 Backup Internal Oscillator (INTOSC1)
The device also includes a redundant on-chip 10 MHz oscillator (INTOSC1). INTOSC1 is a backup clock source
that normally only clocks the watchdog timers and missing clock detection circuit (MCD). If MCD is enabled
and a missing system clock is detected, the system PLL is bypassed and all system clocks are connected to
INTOSC1 automatically. INTOSC1 may also be manually selected as the system and auxiliary clock source for
debug purposes.
3.7.1.3 External Oscillator (XTAL)
The dedicated X1 and X2 pins support an external clock source (XTAL), which can be used as the main system
and auxiliary clock source. Frequency limits and timing requirements can be found in the device data sheet.
Three types of external clock sources are supported:
• A single-ended 3.3V external clock. The clock signal must be connected to X1 while X2 is left unconnected,
as shown in Figure 3-6.

VDDOSC X1 VSSOSC X2

3.3V NC
3.3V
Clk

VDD OUT

GND
3.3V Oscillator

Figure 3-6. Single-ended 3.3V External Clock

• An external crystal. The crystal must be connected across X1 and X2 with the load capacitors connected to
VSSOSC as shown in Figure 3-7.

VDDOSC X1 VSSOSC X2

3.3V
Crystal

RD CL2 CL1

Figure 3-7. External Crystal

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• An external resonator. The resonator must be connected across X1 and X2 with the ground connected to
VSSOSC as shown in Figure 3-8.

VDDOSC X1 VSSOSC X2

3.3V

Resonator

Figure 3-8. External Resonator

Note
All 3 external clocking modes require the XTALOFF bit in CLKSRCCTL1 register to be set to 0. This
enables the path and circuitry required for the clock to propagate to the device.

3.7.1.4 Auxiliary Clock Input (AUXCLKIN)

An additional external clock source is supported on GPIO133 (AUXCLKIN). This must be a single-ended 3.3V
external clock and can be used as the source for the USB and CAN bit clocks. Frequency limits and timing
requirements can be found in the device data sheet. The external clock must be connected directly to the
GPIO133 pin, as shown in Figure 3-9.

Figure 3-9. AUXCLKIN

3.7.2 Derived Clocks

The clock sources discussed in the previous section can be multiplied (via PLL) and divided down to produce the
desired clock frequencies for the application. This process produces a set of derived clocks, which are described
in this section.
3.7.2.1 Oscillator Clock (OSCCLK)
One of INTOSC2, XTAL, or INTOSC1 must be chosen to be the master reference clock (OSCCLK) for the CPU
and most of the peripherals. OSCCLK may be used directly or fed through the system PLL to reach a higher
frequency. At reset, OSCCLK is the default system clock, and is connected to INTOSC2.

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3.7.2.2 System PLL Output Clock (PLLRAWCLK)

The system PLL allows the device to run at its maximum rated operating frequency, and in most applications
generates the main system clock. This PLL uses OSCCLK as a reference, and features a fractional multiplier
and slip detection. For configuration instructions, see Section 3.7.6.
3.7.2.3 Auxiliary Oscillator Clock (AUXOSCCLK)
One of INTOSC2, XTAL, or AUXCLKIN may be chosen to be the auxiliary reference clock (AUXOSCCLK) for the
USB module. (This selection does not affect the CAN bit clock, which uses AUXCLKIN directly). AUXOSCCLK
may be used directly or fed through the auxiliary PLL to reach a higher frequency. At reset, AUXOSCCLK is
connected to INTOSC2, but only an external oscillator can meet the USB timing requirements.
3.7.2.4 Auxiliary PLL Output Clock (AUXPLLRAWCLK)
The auxiliary PLL is used to generate a 60 MHz clock for the USB module. This PLL uses AUXOSCCLK as a
reference, and features a fractional multiplier and slip detection. For configuration instructions, see Section 3.7.6.
3.7.3 Device Clock Domains
The device clock domains feed the clock inputs of the various modules in the device. They are connected to the
derived clocks, either directly or through an additional divider.
3.7.3.1 System Clock (PLLSYSCLK)
The system control registers, GS RAMs, IPC module, GPIO qualification, and NMI watchdog timers have
their own clock domain (PLLSYSCLK). Despite the name, PLLSYSCLK may be connected to the system PLL
(PLLRAWCLK) or to OSCCLK. The chosen clock source is run through a frequency divider, which is configured
via the SYSCLKDIVSEL register. PLLSYSCLK is gated in HALT mode.
3.7.3.2 CPU Clock (CPUCLK)
Each CPU has a clock (CPU1.CPUCLK and CPU2.CPUCLK) that is used to clock the CPU, the coprocessors,
the private RAMs (M0, M1, D0, and D1), and the boot ROM and Flash wrapper. This clock is identical to
PLLSYSCLK, but is gated when the CPU enters IDLE, STANDBY, or HALT mode.
3.7.3.3 CPU Subsystem Clock (SYSCLK and PERx.SYSCLK)
Each CPU provides a clock (CPU1.SYSCLK and CPU2.SYSCLK) to its CLA, DMA, and most owned peripherals.
This clock is identical to PLLSYSCLK, but is gated when the CPU enters STANDBY or HALT mode.
Each peripheral clock can be connected to either CPU1.SYSCLK or CPU2.SYSCLK. This selection is made by
CPU1 using the CPUSELx registers. Each peripheral clock also has its own independent clock gating that is
controlled by the CPU's PCLKCRx registers. By default, the ePWM, EMIF1, and EMIF2 clocks each have an
additional /2 divider, which is required to support CPU frequencies over 100 MHz. At slower CPU frequencies,
these dividers can be disabled using the PERCLKDIVSEL register.
A peripheral may be assigned to either CPU. That is, code for a peripheral can be executed from either CPU1 or
CPU2. CPUSELx register is used assign a peripheral to either CPU1 or CPU2. This register must be configured
prior to enabling the clock for the chosen peripheral since the clock for each peripheral is derived from the
selected CPU subsystem. The clock multiplexer controlled by the CPUSELx register is not glitch-free. Therefore
the CPUSELx register must be configured before the PCLKCRx register. Note that the reset for each peripheral
is also driven from the selected CPU.
3.7.3.4 Low-Speed Peripheral Clock (LSPCLK and PERx.LSPCLK)
The SCI, SPI, and McBSP modules can communicate at bit rates that are much slower than the CPU
frequency. These modules are connected to a shared clock divider, which generates a low-speed peripheral
clock (LSPCLK) derived from SYSCLK. LSPCLK uses a /4 divider by default, but the ratio can be changed via
the LOSPCP register. Each SCI, SPI, and McBSP module's clock (PERx.LSPCLK) can be gated independently
via the PCLKCRx registers.

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3.7.3.5 USB Auxiliary Clock (AUXPLLCLK)

The USB module requires a fixed 60-MHz clock for bit sampling. Since the main system clock is usually not a
multiple of 60 MHz, the correct frequency cannot be achieved with a simple divider. Instead, the USB clock is
provided through an auxiliary clock path (AUXPLLCLK), which can use an independent clock source and PLL to
generate the correct frequency.
USB clock tolerances are very tight. As stated in section 7.1.11 of the USB 2.0 specification, low-speed
devices (1.50 Mb/s) have a tolerance of ±1.5%, while high-speed devices (12.000 Mb/s) have a tolerance of
±0.25%. Typically these tolerances are achieved by using an external crystal or resonator as the source for
AUXOSCCLK.
3.7.3.6 CAN Bit Clock
The required frequency tolerance for the CAN bit clock depends on the bit timing setup and network
configuration, and can be as tight as 0.1%. Since the main system clock (in the form of PERx.SYSCLK) may not
be precise enough, the bit clock can also be connected to XTAL or AUXCLKIN via the CLKSRCCTL2 register.
There is an independent selection for each CAN module.
3.7.3.7 CPU Timer2 Clock (TIMER2CLK)
CPU timers 0 and 1 are connected to PERx.SYSCLK. Timer 2 is connected to PERx.SYSCLK by default, but
may also be connected to INTOSC1, INTOSC2, XTAL, or AUXPLLCLK via the TMR2CLKCTL register. This
register also provides a separate prescale divider for timer 2. If a source other than SYSCLK is used, the
SYSCLK frequency must be at least twice the source frequency to ensure correct sampling. Each CPU has its
own independent CPU timers and TMR2CLKCTL register.
The main reason to use a non-SYSCLK source would be for internal frequency measurement. In most
applications, timer 2 runs off of the SYSCLK.
3.7.4 XCLKOUT
It is sometimes necessary to observe a clock directly for debug and testing purposes. The external clock output
(XCLKOUT) feature supports this by connecting a clock to an external pin, GPIO73. The available clock sources
are PLLSYSCLK, PLLRAWCLK, CPU1.SYSCLK, CPU2.SYSCLK, AUXPLLRAWCLK, INTOSC1, and INTOSC2.
To use XCLKOUT, first select the clock source via the CLKSRCCTL3 register. Next, select the desired
output divider via the XCLKOUTDIVSEL register. Finally, connect GPIO73 to mux channel 3 using the GPIO
configuration registers.

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3.7.5 Clock Connectivity

The following tables provide details on the clock connections of every module present in the device.
Table 3-6. Clock Connections Sorted by Clock Domain
Clock Domain CPU1 Subsystem CPU2 Subsystem Shared Modules
CPUx.CPUCLK CPU1 CPU2
CPU1.VCU CPU2.VCU
CPU1.FPU CPU2.FPU
CPU1.TMU CPU2.TMU
CPU1.M0 - M1 RAMs CPU2.M0 - M1 RAMs
CPU1.D0 - D1 RAMs CPU2.D0 - D1 RAMs
CPU1.BootROM CPU2.BootROM
CPU1.Flash CPU2.Flash
CPUx.SYSCLK CPU1.ePIE CPU2.ePIE
CPU1.LS0 - LS5 RAMs CPU2.LS0 - LS5 RAMs
CPU1.CLA1 Message RAMs CPU2.CLA1 Message RAMs
CPU1.DCSM CPU2.DCSM
PLLSYSCLK CPU1.NMIWD CPU2.NMIWD GS0 - GS15 RAMs
EMIF1 GPIO Input Sync and Qual
IPC
PERx.SYSCLK CPU1.CLA1 CPU2.CLA1 ADCA - D
CPU1.DMA CPU2.DMA CLB1 - 4
CPU1.Timer0 - 2 CPU2.Timer0 - 2 CMPSS1 - 8
EMIF2 DACA - C
uPP A ePWM1 - 12
eCAP1 - 6
eQEP1 - 3
I2CA - B
McBSPA - B
SDFM1 - 8
PERx.LSPCLK McBSPA - B
SCIA - D
SPIA - C
CAN Bit Clock CANA - B
AUXPLLCLK USB
WDCLK (INTOSC1) CPU1.Watchdog CPU2.Watchdog

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Table 3-7. Clock Connections Sorted by Module Name

Module Name Clock Domain
ADCA - D PERx.SYSCLK
Boot ROM CPUx.CPUCLK
CANA - B CAN Bit Clock
CLA PERx.SYSCLK
CLA Message RAMs CPUx.SYSCLK
CLB1 - 4 PERx.SYSCLK
CMPSS1 - 8 PERx.SYSCLK
CPU CPUx.CPUCLK
CPU Timers PERx.SYSCLK
D0 - D1 RAMs CPUx.CPUCLK
DACA - C PERx.SYSCLK
DCSM CPUx.SYSCLK
DMA PERx.SYSCLK
eCAP1 - 6 PERx.SYSCLK
EMIF1 PLLSYSCLK
EMIF2 PERx.SYSCLK
ePIE CPUx.SYSCLK
ePWM PERx.SYSCLK
eQEP1 - 3 PERx.SYSCLK
Flash CPUx.CPUCLK
FPU CPUx.CPUCLK
GS0 - GS15 RAMs PLLSYSCLK
I2CA - B PERx.SYSCLK
IPC PLLSYSCLK
LS0 - LS5 RAMs CPUx.SYSCLK
M0 - M1 RAMs CPUx.CPUCLK
McBSPA - B PERx.LSPCLK
NMIWD PLLSYSCLK
SCIA - D PERx.LSPCLK
SDFM1 - 8 PERx.SYSCLK
SPIA - C PERx.LSPCLK
TMU CPUx.CPUCLK
uPP PERx.SYSCLK
USB AUXPLLCLK
VCU CPUx.CPUCLK
Watchdog Timer WDCLK (INTOSC1)

3.7.6 Clock Source and PLL Setup

The needs of the application are what ultimately determine the clock configuration. Specific concerns such
as application performance, power consumption, total system cost, and EMC are beyond the scope of this
document. The concerns must provide answers to the following questions:
1. What is the desired CPU frequency?
2. Is CAN required?
3. Is USB required?
4. What types of external oscillators or clock sources are available?

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If CAN or USB is required, an external clock source with a precise frequency must be used as a reference clock.
Otherwise, it can be possible to use only INTOSC2 and avoid the need for more external components.
3.7.6.1 Choosing PLL Settings
There are two settings to configure for each PLL – a multiplier and a divider. They obey the formulas:
fPLLSYSCLK = fOSCCLK * (SYSPLLMULT.IMULT + SYSPLLMULT.FMULT) / SYSCLKDIVSEL.PLLSYSCLKDIV
fAUXPLLCLK = fAUXOSCCLK * (AUXPLLMULT.IMULT + AUXPLLMULT.FMULT) / AUXCLKDIVSEL.AUXPLLDIV
where fOSCCLK is the system oscillator clock frequency, fAUXOSCCLK is the auxiliary oscillator clock frequency,
IMULT and FMULT are the integral and fractional parts of the multipliers, PLLSYSCLKDIV is the system clock
divider, and AUXPLLDIV is the auxiliary clock divider. For the permissible values of the multipliers and dividers,
see the documentation for their respective registers.
Many combinations of multiplier and divider can produce the same output frequency. However, the product of the
reference clock frequency and the multiplier (known as the VCO frequency) must be in the range specified in the
data sheet.

Note
The system clock frequency (PLLSYSCLK) may not exceed the limit specified in the datasheet. This
limit does not allow for oscillator tolerance.

The clock source and PLL configuration registers are shared between the two CPUs. Register access is
controlled via a semaphore, which is described in the Inter-Processor Communication chapter.
3.7.6.2 System Clock Setup
Once the application requirements are understood, a specific clock configuration can be determined. The default
configuration is for INTOSC2 to be used as the system clock (PLLSYSCLK) with a divider of 1. The following
procedure must be used to set up the desired application configuration:
1. Select the reference clock source (OSCCLK) by writing to CLKSRCCTL1.OSCCLKSRCSEL.
2. Set up the system PLL: (see the InitSysPll() function in your devices controlSUITE installation for an
example):
a. Bypass the PLL by clearing SYSPLLCTL1[PLLCLKEN].
b. Set the system clock divider to /1 to make sure of the fastest PLL configuration by clearing
SYSCLKDIVSEL[ PLLSYSCLKDIV].
c. Set the integral and fractional multipliers by simultaneously writing them both to SYSPLLMULT. This
automatically enables the PLL. Be sure that the product of OSCCLK and the multiplier is in the range
specified in the data sheet.
d. Lock the PLL five times (see your device errata for details). This number can be increased depending on
application requirements. A higher number of lock attempts helps to make sure of a successful PLL start.
e. Set the system clock divider one setting higher than the final desired value. For example
ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = divsel + 1. This limits the current increase when
switching to the PLL.
f. Set up the watchdog to reset the device. Note that the SCRS[WDOVERRIDE] bit must not be cleared
prior to locking the PLL.
g. Set the SYSDBGCTL[BIT_0] bit. This bit is only reset by a POR reset. If the watchdog has to reset
the device due to an issue with switching to the PLL, this bit can be checked in the reset handler to
determine the reset was caused by a PLL error.
h. Switch to the PLL as the system clock by setting SYSPLLCTL1[PLLCLKEN].
i. Clear the SYSDBGCTL[BIT_0] bit.
j. Change the divider to the appropriate value.
k. Reconfigure the watchdog as needed for the application.

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Note
If the CPU2 changes the OSCCLK source, CPU2 does not automatically bypass the PLL. The CPU2
must manually bypass the PLL first by writing a 0 to SYSPLLCTL1.PLLCLKEN.

3.7.6.3 USB Auxiliary Clock Setup

See the InitAuxPll() function in your device’s controlSUITE installation for an example.
If USB functionality is needed, the auxiliary clock (AUXPLLCLK) must be configured to produce 60 MHz. The
procedure is similar to the system clock setup:
1. Select the reference clock source (AUXOSCCLK) by writing to CLKSRCCTL2.AUXOSCCLKSRCSEL.
2. Wait two AUXOSCCLK cycles.
3. Set up the auxiliary PLL. If the PLL is not needed, bypass the PLL and power the PLL down by writing a 0 to
AUXPLLCTL1.PLLEN. To use the PLL:
a. Set the desired auxiliary clock divider by writing to AUXCLKDIVSEL.AUXPLLDIV.
b. ) Configure CPU Timer 2 to be clocked from AUXPLL. Keep the counter frozen.
c. ) Power down the AUXPLL by clearing AUXPLLCTL1[PLLEN].
d. Set the integral and fractional multipliers simultaneously. This automatically enables the PLL. Be sure
that the product of AUXOSCCLK and the multiplier is in the range specified in the data sheet.
e. Wait for the PLL to lock by polling the AUXPLLSTS.LOCKS bit. This takes 16 µs plus 1024
AUXOSCCLK cycles.
f. Connect the auxiliary PLL output clock (AUXPLLRAWCLK) to AUXPLLCLK by writing a 1 to
AUXPLLCTL1.PLLCLKEN.
g. Start CPU Timer 2. In a large for() loop, continue polling the TCR[TIF] overflow flag. If the flag is set, the
AUXPLL started correctly. If not set, repeat steps (c) through (g). The auxiliary clock configuration can be
changed at run time. Changing the AUXOSCCLK source automatically bypasses the PLL and sets the
multiplier to zero. Changing the multiplier from one non-zero value to another temporarily bypasses the
PLL until the PLL re-locks.
The auxiliary clock configuration can be changed at run time. Changing the AUXOSCCLK source automatically
bypasses the PLL and sets the multiplier to zero. Changing the multiplier from one non-zero value to another
temporarily bypasses the PLL until the PLL re-locks.

Note
If the AUXOSCCLK source is changed on the same AUXOSCCLK cycle as the multiplier, the PLL is
disabled but the AUXPLLMULT register shows the written value. This can happen when the system
PLL is enabled before configuring the auxiliary PLL (CPUCLK >> AUXOSCCLK). To avoid this issue,
wait 2 AUXOSCCLK cycles between changing the clock source and writing to AUXPLLMULT.

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3.7.6.4 Clock Configuration Examples

Example 1: Using a crystal (15 MHz) as a reference, generates a CPU frequency of 100 MHz and a USB clock
of 60 MHz:
CLKSRCCTL1.OSCCLKSRCSEL = 0x1

SYSPLLMULT.IMULT = 26 (0x1A)

SYSPLLMULT.FMULT = .50 (0x2)

SYSCLKDIVSEL.PLLSYSCLKDIV = 4 (0x2)

SYSPLLCTL1.PLLCLKEN = 1

PERCLKDIVSEL.EPWMCLKDIV = 1 (0x0)

PERCLKDIVSEL.EMIF1CLKDIV = 1 (0x0)

PERCLKDIVSEL.EMIF2CLKDIV = 1 (0x0)

CLKSRCCTL2.AUXOSCCLKSRCSEL = 0x1

AUXPLLMULT.IMULT = 8 (0x08)

AUXPLLMULT.FMULT = .00 (0x0)

AUXCLKDIVSEL.AUXPLLDIV = 2 (0x1)

AUXPLLCTL1.PLLCLKEN = 1

This gives a PLLRAWCLK of 397.5 MHz and an AUXPLLRAWCLK of 120 MHz, both of which are in the
acceptable range. The CPU frequency is 99.375 MHz. Crystals have tight frequency tolerances, which can keep
the system clock from exceeding 100 MHz. The USB frequency is exactly 60 MHz. Since the CPU frequency is
less than 100 MHz, the ePWM and EMIF clock dividers can be set to /1.
Example 2: Using INTOSC2 (10 MHz) as a reference, generates a CPU frequency of 200 MHz - 3%:
CLKSRCCTL1.OSCCLKSRCSEL = 0x0
SYSPLLMULT.IMULT = 38 (0x26)
SYSPLLMULT.FMULT = .75 (0x3)
SYSCLKDIVSEL.PLLSYSCLKDIV = 2 (0x1)
SYSPLLCTL1.PLLCLKEN = 1

3.7.7 Clock (OSCCLK) Failure Detection

To achieve safety diagnostic, Missing Clock Detection (MCD) can be used. Table 3-8 lists the details.
Table 3-8. Clock Source (OSCCLK) Failure Detection
Clock Failure Time for Detection
Clocks Detected Limitations
Detection Circuitry (in Cycles)
Missing Clock Detection (MCD) INTOSC2, XTAL/X1 8192 INTOSC1 cycles Cannot detect INTOSC1 clock failure.

3.7.7.1 Missing Clock Detection Logic

The missing clock detect (MCD) logic detects OSCCLK failure, using INTOSC1 as the reference clock source.
This circuit only detects complete loss of OSCCLK and doesn’t do any detection of frequency drift on the
OSCCLK.
This circuit monitors the OSCLK (primary clock) using the 10 MHz clock provided by the INTOSC1 (secondary
clock) as a backup clock. This circuit functions as following.

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1. The primary clock (OSCCLK) clock keeps ticking a 7-bit counter (named as MCDPCNT). This counter is
asynchronously reset with XRS.
2. The secondary clock (INTOSC1) clock keeps ticking a 13-bit counter (named as MCDSCNT). This counter is
asynchronously reset with XRS.
3. Each time MCDPCNT overflows, the MCDSCNT counter is reset. Thus, if OSCCLK is present or is not
slower than INTOSC1 by a factor of 64, MCDSCNT never overflows.
4. If OSCCLK stops for some reason or is slower than INTOSC1 by at least a factor of 64, the MCDSCNT
overflows and a missing clock condition is detected on OSCCLK.
5. The above check is continuously active, unless the MCD is disabled using MCDCR register (by making the
MCLKOFF bit 1)
6. If the circuit ever detects a missing OSCCLK, the following occurs:
• The MCLKSTS flag is set.
• The MCDSCNT counter is frozen to prevent further missing clock detection.
• The CLOCKFAIL signal goes high, which generates TRIP events to PWM modules and fires NMIs to
CPU1.NMIWD and CPU2.NMIWD.
• PLL is forcefully bypassed and OSCCLK is switched to INTOSC1 (after the PLLSYSCLK divider).
PLLMULT is zeroed out automatically in this case.
• While the MCLKSTS bit is set, the OSCCLKSRCSEL bits have no effect and OSCCLK is forcefully
connected to INTOSC1.
• PLLRAWCLK going to the system is switched to INTOSC1 automatically.
7. If the MCLKCLR bit is written (W = 1 bit), MCLKSTS bit are cleared and OSCCLK source is decided by the
OSCCLKSRCSEL bits. Writing to MCLKCLR also clears the MCDPCNT and MCDSCNT counters to allow
the circuit re-evaluate missing clock detection. To lock the PLL after a missing clock detection, switch the
clock source to INTOSC1 (using OSCCLKSRCSEL register), do a MCLKCLR, and re-lock the PLL.
8. The MCD is enabled at power up. There is no support for a missing clock detection, if INTOSC2 is failed
from the device power-up.
Figure 3-10 shows the missing clock logic functional flow.

Secondary Clock CLOCKFAIL

INTOSC1 Missing
Clock INTOSC1
Detect
Primary Clock (MCD)
Logic
Low
OSCCLK Power
INTOSC2 Source Mode
Select OSCCLK Ckt
Ckt
X1/X2

CLKSRCCTL1.OSCCLRSRCSEL /1,
Switch
SYSPLL /2,
Ckt
/4
Mux
PLLRAWCLK ..
(glitch- PLLSYSCLK
/124
PLL Locking free)
/126
Registers Control
Ckt

Clock Dividers

Clock Sources SYSPLLCTL1/2/3,

SYSPLLMULT,
SYSPLLSTS

Figure 3-10. Missing Clock Detection Logic

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Note
On a complete clock failure when OSCCLK is dead, it can take a maximum time of 8192 INTOSC1
cycles (that is, 0.8192 ms) before the CLOCKFAIL signal goes high, after which:
• NMI is generated
• OSCCLK is switched to INTOSC1
• PWM trip happens

3.8 32-Bit CPU Timers 0/1/2

This section describes the three 32-bit CPU-Timers (TIMER0/1/2) shown in Figure 3-11.
CPU-Timer0 and CPU-Timer1 can be used in user applications. CPU-Timer2 is reserved for real-time operating
system uses (for example, TI-RTOS). If the application is not using an operating system that utilizes this timer,
then CPU-Timer2 can be used in the application. CPU-Timer0 and CPU-Timer1 run off of SYSCLK. CPU-Timer2
normally runs off of SYSCLK, but can also use INTOSC1, INTOSC2, XTAL, and AUXPLLCLK. The CPU-Timer
interrupt signals (TINT0, TINT1, TINT2) are connected as shown in Figure 3-12.

Note
If a source other than SYSCLK is used for CPU-Timer2, the SYSCLK frequency must be at least twice
the source frequency to make sure of correct sampling.
The CPU-Timer2 pre-scaler is implemented as a post-scale of the results

Reset
Timer reload

16-bit timer divide-down

32-bit timer period
TDDRH:TDDR
PRDH:PRD

16-bit prescale counter

SYSCLKOUT
PSCH:PSC
TCR.4 32-bit counter
(Timer start status) Borrow TIMH:TIM

Borrow

TINT

Figure 3-11. CPU-Timers

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INT1 TINT0
to PIE TIMER0
INT12

28x
CPU
TINT1
INT13 TIMER1

TINT2
INT14 TIMER2

A. The timer registers are connected to the memory bus of the C28x processor.
B. The CPU Timers are synchronized to SYSCLKOUT.

Figure 3-12. CPU-Timer Interrupts Signals and Output Signal

The general operation of the CPU-Timer is as follows:

• The 32-bit counter register, TIMH:TIM, is loaded with the value in the period register PRDH:PRD
• The counter decrements once every (TPR[TDDRH:TDDR]+1) SYSCLKOUT cycles, where TDDRH:TDDR is
the timer divider.
• When the counter reaches 0, a timer interrupt output signal generates an interrupt pulse.
The registers listed in Section 3.17 are used to configure the timers.

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3.9 Watchdog Timers

The watchdog module generates an output pulse 512 watchdog clocks (WDCLKs) wide whenever the 8-bit
watchdog up counter has reached the maximum value. The watchdog clock source is INTOSC1. Software must
periodically write a 0x55 + 0xAA sequence into the watchdog key register to reset the watchdog counter. The
counter can also be disabled. Figure 3-13 shows the various functional blocks within the watchdog module.

WDCR(WDPS(2:0)) WDCR(WDDIS)

WDCNTR(7:0)

WDCLK Watchdog 8-bit 1-count

(INTOSC1)
/512 Overflow
Prescaler Watchdog delay
Counter
SYSRSn
Clear
Count

WDWCR(MIN(7:0))
WDKEY(7:0) Watchdog
In Window
Watchdog Window
Good Key Out of Window
Key Detector Detector
Bad Key
55 + AA

WDRSTn
Generate
512-WDCLK
WDINTn Watchdog Timeout
Output Pulse

SCSR(WDENINT)

Figure 3-13. CPU Watchdog Timer Module

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3.9.1 Servicing the Watchdog Timer

The watchdog counter (WDCNTR) is reset when the proper sequence is written to the WDKEY register before
the 8-bit watchdog counter overflows. The WDCNTR is reset-enabled when a value of 0x55 is written to the
WDKEY. When the next value written to the WDKEY register is 0xAA, then the WDCNTR is reset. Any value
written to the WDKEY other than 0x55 or 0xAA causes no action. Any sequence of 0x55 and 0xAA values can
be written to the WDKEY without causing a system reset; only a write of 0x55 followed by a write of 0xAA to the
WDKEY resets the WDCNTR.
Table 3-9. Example Watchdog Key Sequences
Step Value Written to WDKEY Result
1 0xAA No action
2 0xAA No action
3 0x55 WDCNTR is enabled to be reset if next value is 0xAA.
4 0x55 WDCNTR is enabled to be reset if next value is 0xAA.
5 0x55 WDCNTR is enabled to be reset if next value is 0xAA.
6 0xAA WDCNTR is reset.
7 0xAA No action
8 0x55 WDCNTR is enabled to be reset if next value is 0xAA.
9 0xAA WDCNTR is reset.
10 0x55 WDCNTR is enabled to be reset if next value is 0xAA.
11 0x32 Improper value written to WDKEY.
No action, WDCNTR no longer enabled to be reset by next 0xAA.
12 0xAA No action due to previous invalid value.
13 0x55 WDCNTR is enabled to be reset if next value is 0xAA.
14 0xAA WDCNTR is reset.

Step 3 in Table 3-9 is the first action that enables the WDCNTR to be reset. The WDCNTR is not actually reset
until step 6. Step 8 again re-enables the WDCNTR to be reset and step 9 resets the WDCNTR. Step 10 again
re-enables the WDCNTR to be reset. Writing the wrong key value to the WDKEY in step 11 causes no action,
however the WDCNTR is no longer enabled to be reset and the 0xAA in step 12 now has no effect.
If the watchdog is configured to reset the device, then a WDCR overflow or writing the incorrect value to the
WDCR[WDCHK] bits resets the device and set the watchdog flag (WDRSn) in the reset cause register (RESC).
After a reset, the program can read the state of this flag to determine whether the reset was caused by the
watchdog. After doing this, the program must clear WDRSn to allow subsequent watchdog resets to be detected.
Watchdog resets are not prevented when the flag is set.
3.9.2 Minimum Window Check
To complement the timeout mechanism, the watchdog also contains an optional "windowing" feature that
requires a minimum delay between counter resets. This can help protect against error conditions that bypass
large parts of the normal program flow but still include watchdog handling.
To set the window minimum, write the desired minimum watchdog count to the WDWCR register. This value
takes effect after the next WDKEY sequence. From then on, any attempt to service the watchdog when
WDCNTR is less than WDWCR triggers a watchdog interrupt or reset. When WDCNTR is greater than or equal
to WDWCR, the watchdog can be serviced normally.
At reset, the window minimum is zero, which disables the windowing feature.

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3.9.3 Watchdog Reset or Watchdog Interrupt Mode

The watchdog can be configured in the SCSR register to either reset the device (WDRST) or assert an interrupt
(WDINT) if the watchdog counter reaches the maximum value. The behavior of each condition is described
below:
• Reset mode:
If the watchdog is configured to reset the device, then the WDRST signal pulls the device reset (XRS) pin low
for 512 INTOSC1 cycles when the watchdog counter reaches the maximum value.
Note: After a CPU1 watchdog reset, the boot ROMs clears all of the system and message RAMs on both
CPUs. After a CPU2 watchdog reset, CPU2's boot ROM clears all of the CPU2 system and message RAMs.
• Interrupt mode:
When the watchdog counter expires, the watchdog asserts an interrupt by driving the WDINT signal low for
512 INTOSC1 cycles. The falling edge of WDINT triggers a WAKEINT interrupt in the PIE, if the interrupt
is enabled. Because the PIE is edge-triggered, re-enabling the WAKEINT while WDINT is active does not
produce a duplicate interrupt.
To avoid unexpected behavior, software must not change the configuration of the watchdog while WDINT is
active. For example, changing from interrupt mode to reset mode while WDINT is active, immediately resets
the device. Disabling the watchdog while WDINT is active, causes a duplicate interrupt if the watchdog is
later re-enabled. If a debug reset is issued while WDINT is active, the reset cause register (RESC) shows a
watchdog reset. The WDINTS bit in the SCSR register can be read to determine the current state of WDINT.
3.9.4 Watchdog Operation in Low-Power Modes
In IDLE mode, the watchdog interrupt (WDINT) signal can generate an interrupt to the CPU to take the CPU
out of IDLE mode. As with any other peripheral, the watchdog interrupt triggers a WAKEINT interrupt in the PIE
during IDLE mode. User software must determine which peripheral caused the interrupt.
In STANDBY mode, all of the clocks to the peripherals are turned off within the CPU subsystem. The only
peripheral that remains functional is the watchdog since the watchdog module runs off the oscillator clock
(OSCCLK). The WDINT signal is applied to the Low Power Modes (LPM) block so that the signal can be used
to wake the CPU from STANDBY low-power mode. This feature is enabled by setting LPMCR.WDINTE = 1. See
Section 3.10 for details.
Note: If the watchdog interrupt is used to wake-up from an IDLE or STANDBY low-power mode condition,
software must make sure that the WDINT signal goes back high before attempting to reenter the IDLE
or STANDBY mode. The WDINT signal is held low for 512 INTOSC1 cycles when the watchdog interrupt
is generated. The current state of WDINT can be determined by reading the watchdog interrupt status bit
(WDINTS) bit in the SCSR register. WDINTS follows the state of WDINT by two SYSCLKOUT cycles.
In HALT mode, the internal oscillators and CPU1 watchdog are kept active if the user sets
CLKSRCCTL1.WDHALTI = 1. A watchdog reset can wake the system from HALT mode, but a watchdog
interrupt cannot.
3.9.5 Emulation Considerations
The watchdog module behaves as follows under various debug conditions:

CPU Suspended: When the CPU is suspended, the watchdog clock (WDCLK) is suspended
Run-Free Mode: When the CPU is placed in run-free mode, then the watchdog module
resumes operation as normal.
Real-Time Single-Step Mode: When the CPU is in real-time single-step mode, the watchdog clock
(WDCLK) is suspended. The watchdog remains suspended even within
real-time interrupts.
Real-Time Run-Free Mode: When the CPU is in real-time run-free mode, the watchdog operates as
normal.

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3.10 Low-Power Modes

This device has three clock-gating, low-power modes, and a special power-gating mode. All low-power modes
are entered by setting the LPMCR register and executing the IDLE instruction. More information about the IDLE
instruction can be found in the TMS320C28x CPU and Instruction Set Reference Guide. Note that each CPU
has an LPMCR register.
Low-power modes must not be entered into while a Flash program or erase is ongoing.
The application can verify the following before entering STANDBY or HALT mode:
1. Check the value of the GPIODAT register of the pin selected for STANDBY or HALT wake-up
(GPIOLPMSEL0/1) prior to entering the low-power mode to make sure that the wake event has not already
been asserted.
2. The LPMCR.QUALSTDBY register must be set to a value greater than the ratio of INTOSC1/PLLSYSCLK to
make sure of proper wake up. This is applicable to STANDBY only.

3.10.1 IDLE
IDLE is a standard feature of the C28x CPU. In this mode, the CPU clock is gated while all peripheral clocks are
left running. IDLE can thus be used to conserve power while a CPU is waiting for peripheral events. When one
CPU is in IDLE, there is no effect on the other CPU subsystem.
Any enabled interrupt wakes up the CPU from IDLE mode.
To enter IDLE mode, set LPMCR.LPM to 0x0 and execute the IDLE instruction.
3.10.2 STANDBY
STANDBY is a more aggressive low-power mode that gates both the CPU clock and any peripheral clocks
derived from the CPU's SYSCLK. The watchdog however, is left active. Like IDLE, this mode affects only one
CPU subsystem. The other CPU subsystem and all of the peripherals are unaffected. STANDBY is best for an
application where the wake-up signal is from an external system (or CPU subsystem) rather than a peripheral
input.
IPC interrupt 1 (flag 0), an NMI fired to the other CPU, or (optionally) a watchdog interrupt, wakes up the CPU
subsystem from STANDBY mode. Any of GPIO0-63 can also be configured to wake up the subsystem when the
GPIOs are driven active low. Upon wakeup, the CPU receives a WAKEINT interrupt, even if the CPU was woken
by an IPCINT1 signal.
To enter STANDBY mode:
1. Set LPMCR.LPM to 0x1.
2. Enable the WAKEINT interrupt in the PIE.
3. For watchdog interrupt wakeup, set LPMCR.WDINTE to 1 and configure the watchdog to generate
interrupts.
4. For GPIO wakeup, set GPIOLPMSEL0 and GPIOLPMSEL1 to connect the chosen GPIOs to the LPM
module, and set LPMCR.QUALSTDBY to select the number of OSCCLK cycles for input qualification.
5. Execute the IDLE instruction to enter STANDBY.
To wake up from Standby mode:
1. Configure the desired GPIO to trigger the wakeup.
2. Drive the selected GPIO signal low; the signal must remain low for the number of OSCCLK cycles specified
in the QUALSTDBY bits in the LPMCR register. If the signal is sampled high during this period, the count
restarts.
At the end of the qualification period, the PLL enables the CLKIN to the CPU and the WAKEINT interrupt is
latched in the PIE block. The WAKEINT interrupt can also triggered by IPCINT1 sent from the other CPU and a
watchdog interrupt.
The CPU is now out of STANDBY mode and can resume normal execution.

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If CPU2 is in STANDBY mode, writing a 1 to the RESET bit of the CPU2RESCTL register has no effect.
CPU2 can be reset by any chip-level reset (POR, XRSn, CPU1.WDRSn, or CPU1.NMIWDRSn) or HIBRESETn.
Alternately, CPU2 can be woken up by any configured wake-up event.
If CPU2 is in STANDBY mode and the debugger is connected, executing a debug reset on CPU2 has no effect.
To wake up the CPU2 with the debugger, Click Run, Single Step, or Step over in the Debug toolbar. CCS IDE
prompts the user requesting to bring the CPU out of the low-power mode. Click Yes. This wakes up CPU2 from
STANDBY and continues execution.
3.10.3 HALT
HALT is a global low-power mode that gates almost all system clocks and allows for power-down of oscillators
and analog blocks. This mode affects both CPU subsystems. HALT can be used for additional power savings
over putting both CPU subsystems in STANDBY, although the options for wakeup are more limited.
Similar to STANDBY, any of GPIO0-63 can be configured to wake up the system from HALT. No other wakeup
option is available. However, CPU1's watchdog can still be clocked, and can be configured to produce a
watchdog reset if a timeout mechanism is needed. On wakeup, both CPUs receive a WAKEINT interrupt.
To enter HALT mode:
1. Disable all interrupts with the exception of the WAKEINT interrupt on both CPUs. The other interrupts can be
reenabled after the device is brought out of HALT mode.
2. Put CPU2 into IDLE mode. (Using STANDBY causes a duplicate WAKEINT on CPU2). CPU1 must verify
this by checking the LPMSTAT register.
3. Set LPMCR.LPM to 0x2. Set GPIOLPMSEL0 and GPIOLPMSEL1 to connect the chosen GPIOs to the LPM
module.
4. Set CLKSRCCTL1.WDHALTI to 1 to keep the CPU1 watchdog active and INTOSC1 and INTOSC2 powered
up in HALT.
5. Set CLKSRCCTL1.WDHALTI to 0 to disable the CPU1 watchdog and power down INTOSC1 and INTOSC2
in HALT.
6. Execute the IDLE instruction on CPU1 to enter HALT.
If an interrupt or NMI is received while the IDLE instruction is in the pipeline, the system begins executing the
WAKEINT ISR. After HALT wakeup, ISR execution resumes where the execution left off.

Note
Before entering HALT mode, if the system PLL is locked (SYSPLL.LOCKS = 1), the system PLL must
also be connected to the system clock (PLLCTL1.PLLCLKEN = 1). Otherwise, the device never wakes
up.

To wake up from HALT mode:

1. Drive the selected GPIO low for a minimum 5 µs. This activates the CPU1.WAKEINT and CPU2.WAKEINT
PIE interrupts.
2. Drive the wake-up GPIO high again to initiate the powering up of the SYSPLL and AUXPLL
3. Wait 16 µs plus 1024 OSCLK cycles to allow the PLLs to lock and the WAKEINT ISR to be latched.
4. Execute the WAKEINT ISR.
The device is now out of HALT mode and can resume normal execution.

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Table 3-10. LPM Entry and Exit Criteria

LPM Mode Entry Sequence Exit Criteria
CPU1 IDLE 1. CPU1 configures CPU1.LPMCR.LPM to 00b 1. POR/BOR
2. CPU1 Executes IDLE instruction 2. IORSn
3. Any enabled CPU1 interrupt
4. CPU1 NMI

CPU1 STANDBY 1. CPU1 configures CPU1.LPMCR.LPM bits to 01b 1. POR/BOR

2. CPU1 programs CPU1.LPMCR.QUAL bits to 2. IORSn
configure appropriate OSCCLK qualification for 3. CPU1.WDINTn
GPIO wakeup pin 4. NMI fired to CPU2
3. CPU1 programs CPU1.GPIOLPMSEL0/1 register 5. GPIO0.async to GPIO63.async selected
to select GPIO0 to GPIO63 pin for wake using CPU1.GPIOLPMSEL0/1 (after OSCCLK
4. CPU1 Executes IDLE instruction qualification)
6. CPU2toCPU1IPCINT1
7. CPU1.POWERABORT

CPU2 IDLE 1. CPU2 configures CPU2.LPMCR.LPM to 00b 1. POR/BOR

2. CPU2 Executes IDLE instruction 2. IORSn
3. Any enabled CPU2 interrupt
4. CPU2 NMI

CPU2 STANDBY 1. CPU2 configures CPU2.LPMCR.LPM bits to 01b 1. POR/BOR

2. CPU2 programs CPU2.LPMCR.QUAL bits to 2. IORSn
configure appropriate OSCCLK qualification for 3. CPU2.WDINTn
GPIO wakeup pin 4. NMI Fired to CPU1
3. CPU2 programs CPU2.GPIOLPMSEL0/1 5. GPIO0.async to GPIO63.async selected
registers to select GPIO0 to GPIO63 pin for wake using CPU2.GPIOLPMSEL0/1 (after OSCCLK
4. CPU2 Executes IDLE instruction qualification)
6. CPU1toCPU2IPCINT1
7. CPU2.POWERABORT

HALT 1. CPU1 configures CPU1.LPMCR.LPM bits to 10b 1. POR/BOR

2. CPU1 programs CPU1.GPIOLPMSEL0/1 2. IORSn
registers to select GPIO0 to GPIO63 pin for wake 3. CPU1.WDRSn
3. CPU1 software confirms whether CPU2 has gone 4. GPIO0.async to GPIO63.async selected using
to IDLE or not using LPMSTAT register CPU1.GPIOLPMSEL0/1 (kept low until XTAL,
4. CPU1 Executes IDLE instruction INTOSCx, and PLL powers up)
5. CPU1.POWERABORT
6. CPU2.POWERABORT

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3.10.4 Hibernate (HIB)

Hibernate (HIB) is a global low-power mode that gates the supply voltages to most of the system. This mode
affects both CPU subsystems. HIB is essentially a controlled power-down with remote wakeup capability, and
can be used to save power during long periods of inactivity. Because gating the supply voltage corrupts the state
of the logic, a reset is required to exit HIB. To prevent external systems from being affected by the reset, HIB
provides isolation of the I/O pin states as well as low-power data retention via the M0 and M1 memories.
Unlike the clock-gating modes, HIB does not have a true wakeup. Instead, GPIO41 becomes HIBWAKE, an
asynchronous reset signal. When the boot ROM detects a HIB wakeup, the boot ROM avoids clearing M0 and
M1 and calls a user-specified I/O restore function. To prevent glitches on internal and external signals, XRS also
generates a HIBWAKE signal during HIB. The I/O restore function must set up the GPIO control registers to
match their pre-HIB state, then write a 1 to LPMCR.IOISODIS to deactivate I/O isolation. If the restore function
does not disable isolation, the boot ROM disables isolation.
To enter HIB mode:
1. Save any necessary state to the M0 and M1 memories of both CPUs.
2. Put all I/Os in the desired state for isolation and deactivate any analog modules in use.
3. Write the address of the I/O restore function for each CPU to the IORESTOREADDR register.
4. Put CPU2 in reset, IDLE, or STANDBY.
5. Bypass the PLL by setting PLLCLKEN to 0.
6. Set CPU1's LPMCR.LPM to 0x3 and execute the IDLE instruction.
Any debugger connection is lost on HIB entry since the JTAG logic is powered down.
Due to the loss of system state on HIB entry, it is possible for error information to be lost if an NMI is triggered
while the IDLE instruction is in the pipeline. The ERRORSTS pin is set and remains set until I/O isolation is
disabled, but there is no way to determine what caused the error.
To wake the device from HIB mode:
1. Assert the dedicated GPIOHIBWAKE pin (GPIO41) low to enable the power-up of the device clock sources.
2. Assert GPIOHIBWAKE pin high again. This triggers the power-up of the rest of the device.
3. Boot ROM code executes on HIB wake-up. Boot ROM reads CPU1.RESC.HIBRESTn bit to determine this is
a wakeup from HIB.
4. Boot ROM calls the I/O context restore routine. This I/O restore function must reconfigure the I/O
configuration and do any other necessary application setup.
Since waking up from HIB mode is a type of reset, the device enters the main function. The device is now out of
HIB mode and can normal execution.

Note
The bootROM uses locations 0x02-0x122 on CPU1 M0 RAM and locations 0x02-0x80 on CPU2 M0
RAM. To prevent losing any data during HIB wake-up, avoid saving any critical data to these locations.
The application must bypass the PLL before executing the IDLE instruction to enter HIB. If the PLL is
not bypassed when entering HIB, there is a brief current spike on the Vdd supply that can cause the
device to reset.

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3.11 Memory Controller Module

Note
All RAMs on these devices are SRAMs.

For these devices, the RAMs have different characteristics. Some are:
• dedicated to each CPU (M0, M1, and Dx RAMs),
• shared between the CPU and its own CLA (LSx RAM),
• shared between the CPU and DMA of both subsystems (GSx RAM), and
• used to send and receive messages between processors (MSGRAM).
All these RAMs are highly configurable to achieve control for write access and fetch access from different
masters. There are also RAMs - called IPC MSGRAMs - that are used for interprocessor communication. All
dedicated RAMs are enabled with the ECC feature (both data and address) and shared RAMs, as well as IPC
MSGRAMs, are enabled with the PARITY (both data and address) feature. Some of the dedicated memories are
secure memory as well. Refer to Section 3.13 for more details. Each RAM has its own controller that takes care
of the access protection/security related checks and ECC/Parity features for that RAM. Figure 3-14 shows the
configuration of these RAMs.
CPU1.LSx RAM CPU2.LSx RAM
GSx RAM

CPU1 TO CPU2 TO CPU2.CLA1

CPU1.CLA1 CPU1.CLA1 CPU2.CLA1
MSGRAM MSGRAM

CPU1.CLA1 TO CPU2.CLA1 TO
CPU1 MSGRAM CPU2 MSGRAM
CPU1.DMA CPU2.DMA

CPU1 CPU2
CPU1.M0 RAM CPU2.M0 RAM

CPU2 TO CPU1
MSGRAM
CPU1.M1 RAM CPU2.M1 RAM

CPU1 TO CPU2
CPU1.Dx RAM MSGRAM CPU2.Dx RAM

Figure 3-14. Memory Architecture

3.11.1 Functional Description

This section further defines and discusses the dedicated RAMs, shared RAMs, and MSG RAMs on this device.
3.11.1.1 Dedicated RAM (Dx RAM)
Each CPU subsystem has four dedicated RAM blocks: M0, M1, D0, and D1. M0/M1 memories are small blocks
of memory which are tightly coupled with the CPU. Only the CPU has access to these memories. No other
masters (including DMA) have any access to these memories.
All dedicated RAMs have the ECC feature. All dedicated memories (except for M0/M1) are secure memory
and also have the access protection (CPU write protection/CPU fetch protection) feature. Each type of access
protection for each RAM block can be enabled/disabled by configuring the specific bit in the access protection
register, allocated to each subsystem (DxACCPROT).
3.11.1.2 Local Shared RAM (LSx RAM)
RAM blocks that are dedicated to each subsystem and are accessible to the CPU and CLA only, are called local
shared RAMs (LSx RAMs). All such memories are secure memory and have the parity feature. By default, these
memories are dedicated to the CPU only, and the user can choose to share these memories with the CLA by
appropriately configuring the MSEL_LSx bit field in the LSxMSEL register. Further, when these memories are
shared between the CPU and CLA, the user can choose to use these memories as CLA program memory by

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configuring the CLAPGM_LSx bit field in the LSxCLAPGM registers. CPU access to all memory blocks, which
are programmed as CLA program memory, are blocked.
All these RAMs have the access protection (CPU write/CPU fetch) feature. Each type of access protection for
each RAM block can be enabled or disabled by configuring the specific bit in the local shared RAM access
protection registers, mapped to each CPU subsystem. Table 3-11 shows the LSx RAM features.
Table 3-11. Local Shared RAM
MSEL_LSx CLAPGM_LSx CPUx CPUx.CLA1 Comment
Allowed Access Allowed Access
00 X All - LSx memory is configured as CPU dedicated RAM
01 0 All Data Read LSx memory is shared between CPU and CLA1
Data Write
01 1 Emulation Read Fetch Only LSx memory is CLA1 program memory
Emulation Write

3.11.1.3 Global Shared RAM (GSx RAM)

RAM blocks that are accessible from both the CPU and their respective DMA are called global shared RAMs
(GSx RAMs). Each shared RAM can be owned by either CPU subsystem based on the configuration of their
respective bits (one bit for each GSx memory) in the GSxMSEL register. When a particular GSx RAM block is
owned by the CPU1 subsystem, CPU1 and CPU1.DMA have full access to that RAM block, whereas CPU2 and
CPU2.DMA have only read access (no fetch/write access). Similarly, when a particular GSx RAM block is owned
by the CPU2 subsystem, CPU1 and CPU1.DMA has only read access (no fetch/write access) to that RAM block,
whereas CPU2 and CPU2.DMA has full access.
Table 3-12 shows the features of the GSx RAM.
Table 3-12. Global Shared RAM
GSxMSEL CPU1 CPU1 CPU1 CPU1.DMA CPU1.DMA CPU2 CPU2 CPU2 CPU2.DMA CPU2.DMA
Fetch Read Write Read Write Fetch Read Write Read Write
0 Yes Yes Yes Yes Yes No Yes No Yes No
1 No Yes No Yes No Yes Yes Yes Yes Yes

Note
Emulation/Debugger access is allowed from both CPUs, irrespective of the GSxMSEL setting.

Like other shared RAM, these RAMs also have a different levels of access protection which can be enabled or
disabled by configuring specific bits in the GSxACCPROT registersmapped in each subsystem.
Master select and access protection configuration for each GSx RAM block can be individually locked by the
user to prevent further update to these bit fields. The user can also choose to permanently lock the configuration
to individual bit fields by setting the specific bit fields in the GSxCOMMIT register (refer to the register description
for more details). Once configuration is committed for a particular GSx RAM block, the configuration cannot
be changed further until CPUx. SYSRS is issued. Only the CPU1 software can change the master select
configuration by writing into the GSxMSEL register, mapped on the CPU1. The GSxMSEL register, which is
mapped to the CPU2 subsystem, is a status register that can only be used by CPU2 software to know the
master ownership for each GSx RAM block.
3.11.1.4 CPU Message RAM (CPU MSG RAM)
These RAM blocks can be used to share data between CPU1 and CPU2. Since these RAMs are used for
interprocessor communication, they are also called IPC RAMs. The CPU MSGRAMs have CPU/DMA read/write
access from its own CPU subsystem, and CPU/DMA read only access from the other subsystem.
This RAM has parity.

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3.11.1.5 CLA Message RAM (CLA MSGRAM)

These RAM blocks are be used to share data between the CPU and CLA. The CLA has read and write access to
the "CLA to CPU MSGRAM." The CPU has read and write access to the "CPU to CLA MSGRAM." The CPU and
CLA both have read access to both MSGRAMs.
This RAM has parity.
3.11.1.6 Access Arbitration
For a shared RAM, multiple accesses can happen at a given time. The maximum number of accesses to any
shared RAM at any given time depends on the type of shared RAM. On this device, a combination of a fixed and
round robin scheme is followed to arbitrate multiple access at any given time. Accesses from the same masters
are arbitrated in a fixed priority manner, but the accesses from different masters are arbitrated using the round
robin scheme.
The following is the order of fixed priority for CPU accesses:
1. Data Write/Program Write
2. Data Read
3. Program Read/Program Fetch
The following is the order of fixed priority for CLA accesses:
1. Data Write
2. Data Read/Program Fetch
Figure 3-15 represents the arbitration scheme on global shared memories:

Round Robin Arbitration

CPU1-DWRITE CPU1
Fixed Granted CPU1 Access
CPU1-DREAD Priority RR-CPU1
CPU1-PREAD/FETCH Arbiter

CPU1.DMA READ/WRITE

RR-CPU2.DMA RR-CPU1.DMA

CPU2-DWRITE
CPU2
CPU2-DREAD Fixed Granted CPU2 Access
Priority
CPU2-PREAD/FETCH Arbiter

RR-CPU2

CPU2.DMA READ/WRITE

Figure 3-15. Arbitration Scheme on Global Shared Memories

Figure 3-16 represents the arbitration scheme on local shared memories.

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Round Robin Arbitration

CPU-DWRITE CPU
Fixed Granted CPU1 Access
CPU-DREAD
Priority
Arbiter RR-CPU
CPU-PREAD/FETCH

CLA-DWRITE CLA RR-CPU.CLA

Fixed
Priority Granted CLA Access
CLA-DREAD
Arbiter

Figure 3-16. Arbitration Scheme on Local Shared Memories

3.11.1.7 Access Protection

All RAM blocks except for M0/M1 on both subsystems have different levels of protection. This feature allows
the user to enable or disable specific access to individual RAM blocks from individual masters. There is no
protection for read accesses, hence reads are always allowed from all the masters which have access to that
RAM block.
The following sections describe the different kinds of protection available for RAM blocks on this device.
Note: For debug accesses, all the protections are disabled.
3.11.1.7.1 CPU Fetch Protection
A CPU has execution permission from a memory, only if that memory is dedicated to that CPU or its respective
subsystem is master for that memory (in case of GSx memory). When fetch accesses are allowed based on
the mastership, it can be further protected by setting the FETCHPROTx bit of the specific register to ‘1.’ If fetch
access is done by the CPU to a memory where CPU fetch protection is enabled, a fetch protection violation
occurs.
There are two types of fetch protection violations:
• Non-master CPU fetch protection violation
• Master CPU fetch protection violation
If a fetch access is made to a memory by a non-master CPU, it is called a non-master fetch protection violation.
If a fetch access is made to a dedicated or shared memory by the master CPU, and FETCHPROTx is set to ‘1’
for that memory, the violation is called a master CPU fetch protection violation.
If a fetch protection violation occurs, it results in an ITRAP for CPU. A flag gets set into the appropriate access
violation flag register, and the memory address for which the access violation occurred, get latched into the
appropriate CPU fetch access violation address register.
3.11.1.7.2 CPU Write Protection
A CPU has write permission to a memory only if that memory is dedicated to that CPU, or if the respective
subsystem is the master for that memory (in case of GSx memory). When write accesses are allowed based on
the mastership, write accesses can be further protected by setting the CPUWRPROTx bit of the specific register
to 1. If write access is done by a CPU to memory where the write is protected, a write protection violation occurs.
There are two types of CPU write protection violations:
• Non-master CPU write protection violation
• Master CPU write protection violation
If a write access is made to a dedicated or shared memory by the master CPU and CPUWRPROTx is set to
1 for that memory, the write access is called a master CPU write protection violation.

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If a write protection violation occurs, write gets ignored, a flag gets set into the appropriate access violation flag
register, and the memory address for which the access violation occurred, gets latched into the appropriate CPU
write access violation address register. Also, an access violation interrupt is generated if enabled in the interrupt
enable register.
3.11.1.7.3 CPU Read Protection
For local shared RAM, if memory is shared between the CPU and the CLA, the CPU only has access if the
memory is configured as data RAM for the CLA. If the memory is programmed as program RAM, all the access
from the CPU, including a read, is blocked and the violation is considered as a non-master access violation.
If a read protection violation occurs, a flag gets set into the appropriate access violation flag register, and the
memory address for which the access violation occurred, gets latched into the appropriate CPU read access
violation address register. Also, an access violation interrupt is generated, if enabled in the interrupt enable
register.
3.11.1.7.4 CLA Fetch Protection
If local shared RAM is configured as dedicated RAM for the CPU, or if it is configured as data RAM for the CLA,
any fetch access from the CLA to that particular LSx RAM results in a CLA fetch protection violation, which is a
non-master access violation.
If a CLA fetch protection violation occurs, it results in a MSTOP, a flag gets set into the appropriate access
violation flag register, and the memory address for which the access violation occurred, gets latched into the
appropriate CLA fetch access violation address register. Also, an access violation interrupt is generated to the
master CPU if enabled in the interrupt enable register.
3.11.1.7.5 CLA Write Protection
If local shared RAM is configured as dedicated RAM for the CPU, or if it is configured as program RAM for the
CLA, any data write access from the CLA to that particular LSx RAM results in a CLA write protection violation,
which is a non-master access violation.
If a CLA write protection violation occurs, write gets ignored, a flag gets set into the appropriate access violation
flag register, and the memory address for which the access violation occurred, gets latched into the appropriate
CLA write access violation address register. Also, an access violation interrupt is generated to the master CPU if
enabled in the interrupt enable register.
3.11.1.7.6 CLA Read Protection
If local shared RAM is configured as dedicated RAM for the CPU, or if it is configured as program RAM for the
CLA, any data read access from the CLA to that particular LSx RAM results in a CLA read protection violation,
which is a non-master access violation.
If a CLA read protection violation occurs, a flag gets set into the appropriate access violation flag register, and
the memory address for which the access violation occurred, gets latched into the appropriate CLA read access
violation address register. Also, an access violation interrupt is generated to the master CPU if enabled in the
interrupt enable register.
3.11.1.7.7 DMA Write Protection
The CPU1 or CPU2 DMA has write permission to a GSx memory only if the respective subsystem is master for
that memory. When write accesses from a DMA are allowed based on the mastership, write accesses can be
further protected by setting the DMAWRPROTx bit of a specific register to 1’ If write access is done by the DMA
to protected memory, a write protection violation occurs.
There are two types of DMA write protection violations:
• Non-master DMA write protection violation (only applicable to Sx memories)
• Master DMA write protection violation

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If a write access is made to GSx memory by a non-master DMA, the write access is called a non-master
write protection violation. If a write access is made to a dedicated or shared memory by a master DMA, and
DMAWRPROTx is set to 1 for that memory, the write access is called a master DMA write protection violation.
If a write protection violation occurs on CPU1, write is ignored and a DMAERR interrupt gets generated, whereas
in the case of CPU2, a write is ignored and an access violation interrupt is generated if enabled in the interrupt
enable register. A flag gets set in the DMA access violation flag register, and the memory address where
the violation happened gets latched in the DMA fetch access violation address register. These are dedicated
registers for each subsystem.

Note 1: All access protections are ignored during debug accesses. Write access to a protected memory
goes through when the write is done using the debugger, irrespective of the write protection
configuration for that memory.
Note 2: Access protection is not implemented for M0 and M1 memories.
Note 3: In the case of local shared RAM, if memory is shared between the CPU and the CLA, the CPU only
has access if the memory is configured as data RAM for the CLA. If the memory is programmed
as program RAM, all the access from the CPU (including read) and data access from the CLA
is blocked, and the violation is considered as a non-master access violation. If the memory is
configured as dedicated to the CPU, all access from the CLA is blocked and the violation is
considered a non-master access violation.

3.11.1.8 Memory Error Detection, Correction and Error Handling

These devices have memory error detection and correction features to satisfy safety standards requirements.
These requirements warrant the addition of detection mechanisms for finite dangerous failures.
In this device, all dedicated RAMs support error correction code (ECC) protection and the shared RAMs have
parity protection. The ECC scheme used is Single Error Correction Double Error Detection (SECDED). The
parity scheme used is even parity. ECC/Parity covers the data bits stored in memory as well as address.
ECC/Parity calculation is done inside the memory controller module and then calculated. ECC/Parity is written
into the memory along with the data. ECC/Parity is computed for 16-bit data; hence, for each 32-bit data, there
are three 7-bit ECC codes (or 3-bit parity), two of which are for data and a third one for the address.
3.11.1.8.1 Error Detection and Correction
Error detection is done while reading the data from memory. The error detection is performed for data as well as
address. For parity memory, only a single-bit error gets detected, whereas in case of ECC memory, along with a
single-bit error, a double-bit error also gets detected. These errors are called correctable error and uncorrectable
errors. The following are characteristics of these errors:
• Parity errors are always uncorrectable errors
• Single-bit ECC errors are correctable errors
• Double-bit ECC errors are uncorrectable errors
• Address ECC errors are also uncorrectable errors
Correctable errors get corrected by the memory controller module and then correct data is given back as read
data to the master. It is also written back into the memory to prevent double-bit error due to another single-bit
error at the same memory address.

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Note
ECC/Parity for address is calculated for address offset only (based on RAM block size) of
corresponding 32-bit aligned address. For example, in case of LSx RAM that are 4-KB RAM block,
only 11 LSBs of 32-bit aligned address are used. So if address is 0x8F8F, address ECC (or Parity)is
calculated for address 0x78E (11-bit offset of 32-bit aligned address). Similarly for 8-KB RAM block,
12-bit address offset is used.

3.11.1.8.2 Error Handling

For each correctable error, the count in the correctable error count register increments by one. When the value
in this count register becomes equal to the value configured into the correctable error threshold register, an
interrupt is generated to the respective CPU, that is, if the interrupt is enabled in the correctable interrupt enable
register. The user needs to configure the correctable error threshold register based on the system requirements.
Also, the address for which the error occurred, gets latched into the master-specific status register and a flag
gets set. Each of these registers are dedicated for each CPU subsystem.
If there are uncorrectable errors, an NMI gets generated for the respective CPU. In this case, the address for
which the error occurred, also gets latched into the master-specific address status register, and a flag gets set.
Table 3-13 summarizes different error situations that can arise. These need to be handled appropriately in the
software, using the status and interrupt indications provided.
Table 3-13. Error Handling in Different Scenarios
Access Type Error Found In Error Type Status Indication Error Notification
Reads Data read from Uncorrectable Yes -CPUx/CPUx.DMA/CPUx.CLA1 NMI for CPUx access
memory Error CPU/DMA/CLA Read Error Address NMI for CPUx.DMA access
(Single-bit error for Register Data returned to CPUx/ NMI to CPU for CPUx.CLA1 access
Parity RAMs OR CPUx.DMA/CPUx.CLA1 is incorrect
Double bit Error for
ECC RAMs)
Reads Data read from Single-bit error for Yes - CPUx/CPUx.DMA CPU/DMA Interrupt when error counter reaches the
memory ECC RAMs Read Error Address Register Increment user programmable threshold for single
single error counter errors
Reads Address Address error Yes - CPUx/CPUx.DMA/CPUx.CLA1 NMI to CPU for CPUx access
CPU/DMA/CLA Read Address Error NMI to CPU for CPUx.DMA access
Register Data returned to CPUx/ NMI to CPU for CPUx.CLA1 access
CPUx.DMA/CPUx.CLA1 is incorrect

Note
In the case of an uncorrectable error during fetch on the CPU, there is the possibility of getting an
ITRAP before an NMI exception, since garbage instructions enter into the CPU pipeline before the
NMI gets generated.
During debug accesses, correctable as well as uncorrectable errors are masked.

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3.11.1.9 Application Test Hooks for Error Detection and Correction

Since error detection and correction logic is part of safety critical logic, safety applications need to make sure
that the logic is always working fine (during run time also). To enable this, a test mode is provided, in which
a user can modify the data bits (without modifying the ECC/Parity bits) or ECC/Parity bits directly. Using this
feature, an ECC/Parity error can be injected into data.

Note
The memory map for ECC/Parity bits and data bits are the same. The user must choose a different
test mode to access ECC/Parity bits.

Table 3-14 shows the bit mapping for the ECC bits when the bits are read in RAMTEST mode using their
respective addresses. Table 3-15 shows the bit mapping for the Parity bits when the bits are read in RAMTEST
mode using their respective addresses.
Table 3-14. Mapping of ECC Bits in Read Data from ECC/Parity Address Map
Data Bits Location in Read Data Content (ECC Memory)
6:0 ECC Code for lower 16 bits of data
7 Not Used
14:8 ECC Code for upper 16 bits of data
15 Not Used
22:16 ECC Code for address
31:23 Not Used

Table 3-15. Mapping of Parity Bits in Read Data from ECC/Parity Address Map
Data Bits Location in Read Data Content (Parity Memory)
0 Parity for lower 16 bits of data
7:1 Not Used
8 Parity for upper 16 bits of data
15:9 Not Used
16 Parity for address
31:17 Not Used

3.11.1.10 RAM Initialization

To make sure that read/fetch from uninitialized RAM locations do not cause ECC or parity errors, the RAM_INIT
feature is provided for each memory block. Using this feature, any RAM block can be initialized with 0x0 data
and respective ECC/Parity bits accordingly. This can be initiated by setting the INIT bit to 1 for the specific RAM
block in INIT registers. To check the status of RAM initialization, the software must poll for the INITDONE bit for
that RAM block in the INITDONE register to be set. Unless this bit gets set, no access must be made to that
RAM memory block.
In the case of GSx memory, only the CPU of the subsystem that is configured as the master for the particular
GSx RAM block can initiate the RAM initialization.

Note
None of the masters must access the memory while initialization is taking place. If memory is
accessed before RAMINITDONE is set, the memory read/write as well as initialization does not
happen correctly.

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3.12 Flash and OTP Memory

Flash is an electrically erasable/programmable nonvolatile memory that can be programmed and erased many
times to ease code development. Flash memory can be used primarily as a program memory for the core, and
secondarily as static data memory.
This section describes the proper sequence to configure the wait states and operating mode of Flash. This
section also includes information on Flash and OTP memory power modes, how to improve Flash performance
by enabling the Flash prefetch/cache mode, and the SECDED safety feature.
3.12.1 Features
Features of Flash memory include:
• Dedicated Flash bank in the CPU1 subsystem (refer to the device data sheet for the size of Flash bank)
• Dedicated Flash bank in the CPU2 subsystem (refer to the device data sheet for the size of Flash bank)
• Dedicated Flash module controller (FMC) in the CPU1 and CPU2 subsystems for each bank
• 128 bits (bank width) can be programmed at a time along with ECC
• Multiple sectors providing the option of leaving some sectors programmed and only erasing specific sectors
• User-programmable OTP memory locations for configuring security, OTP boot-mode and boot-mode select
pins (if the user is unable to use the factory-default boot-mode select pins)
• Single-Flash pump shared by the CPU1 and CPU2 subsystems
• Hardware Flash pump semaphore to control ownership of the pump between the two FMCs.
• Enhanced performance using the code-prefetch mechanism and data cache in CPU1-FMC and CPU2-FMC
• Configurable wait states to give the best performance for a given execution speed
• Safety Features
– SECDED-single error correction and double error detection is supported in both FMCs
– Address bits are included in ECC
– Test mode to check the health of ECC logic
• Supports low-power modes for Flash bank and pump for power savings
• Built-in power mode control logic
• Integrated Flash program/erase state machine (FSM) in both FMCs
– Simple Flash API algorithms
– Fast erase and program times (refer to the device data sheet for details)
• Code Security Module (CSM) to prevent access to the Flash by unauthorized persons (refer to Section 3.13
for details)

3.12.2 Flash Tools

Texas Instruments provides the following tools for Flash:
• Code Composer Studio (CCS) IDE - the development environment with integrated Flash plugin
• F021 Flash API Library - a set of software peripheral functions to erase/program Flash
• UniFlash - standalone tool to erase/program/verify the Flash content through JTAG. No CCS IDE is required.
• CCS On-Chip Flash Plugin and UniFlash tools developed for these devices support AutoEccGeneration (see
TMS320F2837xD Flash API Version 1.54 Reference Guide). But the tools do not support the program of ECC
generated by the linker -ecc options.
Users must check and install available updates for CCS On-Chip Flash Plugin and UniFlash tools.

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3.12.3 Default Flash Configuration

The following are Flash module configuration settings at power-up in both CPU1 and CPU2 subsystems:
• Dedicated Flash banks are in sleep power mode
• Shared pump is in sleep mode
• ECC is enabled
• Wait-states are set to the maximum (0xF)
• Code-prefetch mechanism and data cache are disabled in both FMCs
During the boot process, the boot ROM performs a dummy read of the Code Security Module (CSM) password
locations in the OTP memory. This read is performed to unlock a new (or erased) device that has no password
stored in the device, so that Flash programming or loading of code into CSM-protected SARAM can be
performed. On devices with a password, this read has no effect and the device remains locked. One effect
of this read is that the Flash transitions from the sleep (reset) state to the active state.
User application software must initialize wait-states using the FRDCNTL register, and configure cache/prefetch
features using the RD_INTF_CTRL register, to achieve optimum system performance. Software that configures
Flash settings like wait-states, cache/prefetch features, and so on, must be executed only from RAM memory,
not from Flash memory.

Note
Before initializing wait-states, turn off the pre-fetch and data caching in the FRD_INTF_CTRL register.

3.12.4 Flash Bank, One-Time Programmable (OTP) Memory, and Flash Pump
There is a dedicated Flash bank in the CPU1 subsystem called the CPU1 Flash bank and a dedicated Flash
bank in the CPU2 subsystem called the CPU2 Flash bank. Also, there is a one-time programmable (OTP)
memory on the CPU1 subsystem called USER OTP, which the user can program only once and cannot erase.
Flash and OTP memory are uniformly mapped in both program and data memory space.
Both the CPU1 subsystem and CPU2 subsystem have a TI-OTP that contains manufacturing information like
settings used by the Flash state machine for erase and program operations, and so on. Users can read TI-OTP
but the TI-OTP cannot be programmed or erased. For memory-map and size information of the CPU1-Bank,
CPU1 TI-OTP, CPU1 USER OTP, CPU2 Flash bank, CPU2 TI-OTP, CPU2 USER-OTP, and corresponding ECC
locations, refer to the device data sheet.
The CPU1 Flash bank/USER OTP and CPU2 Flash bank/USER OTP share a common Flash pump. A hardware
semaphore, called the Flash pump semaphore, is provided to control the access of the Flash pump between the
CPU1 subsystem and CPU2 subsystem.
Figure 3-23 depicts the user-programmable OTP memory locations in CPU1 USER-OTP and CPU2 USER-OTP.
For more information on the functionality of these fields, refer to Section 3.13 and Chapter 4.

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3.12.5 Flash Module Controller (FMC)

There is a dedicated Flash module controller in both the CPU1 subsystem (CPU1-FMC) and the CPU2
subsystem (CPU2-FMC). The CPU1 in the CPU1 subsystem interfaces with the CPU1 Flash module controller
(CPU1-FMC), which in turn, interfaces with the CPU1 Flash bank and shared pump to perform erase/program
operations as well as to read data/execute code from the CPU1 Flash bank.

CPU2-Bank

CPU2 System Clock

CPU2 Core
CPU2-FMC

Pump

CPU1-FMC
CPU1 Core
Pump Semaphore
CPU1 System Clock

CPU1-Bank

Figure 3-17. FMC Interface with Core, Bank, and Pump

The CPU2 in the CPU2 subsystem interfaces with the CPU2 Flash module controller (CPU2-FMC) which in turn,
interfaces with the CPU2 Flash bank and shared pump to perform erase and program operations as well as to
read data and execute code from the CPU2 Flash bank. Control signals to the Flash pump are controlled by
either CPU2-FMC or CPU1-FMC, depending on who gains the Flash pump semaphore.
There is a state machine in both CPU1-FMC and CPU2-FMC that generates the erase and program sequences
in hardware. This simplifies the Flash API software that configures control registers in the FMC to perform Flash
erase and program operations (see TMS320F2837xD Flash API Version 1.54 Reference Guide, for details on
Flash API).
3.12.6 Flash and OTP Memory Power-Down Modes and Wakeup
The Flash bank and pump consume a significant amount of power when active. The Flash module provides a
mechanism to power-down Flash banks and pump. Special timers automatically sequence the power-up of the
CPU1 Flash bank and CPU2 Flash bank independently of each other. The shared charge pump module has an
independent power-up timer as well.
The Flash bank and OTP memory operate in three power modes: Sleep (lowest power), Standby, and Active
(highest power)
• Sleep State: This is the state after a device reset. In this state, a CPU data read or opcode fetch
automatically initiates a change in power mode to the standby state and then to the active state. During
this transition time to the active state, the CPU is automatically stalled.
• Standby State: This state uses more power than the sleep state, but takes a shorter time to transition to the
active or read state. In this state, a CPU data read or opcode fetch automatically initiates a change in power
mode to the active state. During this transition time to the active state, the CPU is automatically stalled. Once
the Flash/OTP memory has reached the active state, the CPU access completes as normal.
• Active or Read State: In this state, the bank and pump are in active power mode state (highest power).

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The charge pump operates in two power modes:

• Sleep (lowest power)
• Active (highest power)
Any access to any Flash bank/OTP memory causes the charge pump to go into active mode, if the charge pump
is in sleep mode. An erase or program command causes the charge pump and bank to become active. If any
bank is in active or in standby mode, the charge pump is in active mode, independent of the pump power mode
control configuration (PMPPWR bit field in the FPAC1 register).
To power down the Flash pump, both the CPU1 and CPU2 must each power down the Flash pump without any
Flash accesses in between. The Flash pump does not enter low-power mode if the following sequence is not
followed.
1. When the system is ready to power down the Flash completely, synchronize CPU1 and CPU2. CPU2 enters
the Flash power-down phase (steps 2, 3, 4, and 5) while CPU1 is waiting for CPU2 to complete.
2. Acquire the Pump Semaphore with CPU2.
3. Assign a value of 0x14 to CPU2 VREADST (refer to the FBAC register) to make sure the requisite delay is
needed for the Flash pump/bank to come out of low-power mode later: FBAC.VREADST = 0x14
4. Change the CPU2 Flash Bank Fall Back power mode to Sleep: FBFALLBACK.BNKPWR = 0.
5. Change the CPU2 Flash Charge Pump Fall Back power mode to Sleep: FPAC1.PMPPWR = 0. CPU2 must
notify CPU1 that CPU2 has completed the above sequence. CPU2 must wait until CPU1 completes steps 6,
7, 8, 9, and 10.
6. Acquire the Pump Semaphore with CPU1.
7. Assign a value of 0x14 to CPU1 VREADST (refer to FBAC register) to make sure the requisite delay is
needed for the Flash pump/bank to come out of low-power mode later: FBAC.VREADST = 0x14
8. Change the CPU1 Flash Bank Fall Back power mode to Sleep: FBFALLBACK.BNKPWR = 0.
9. Change the CPU1 Flash Charge Pump Fall Back power mode to Sleep: FPAC1.PMPPWR = 0.
10. Release the Pump Semaphore from the CPU1. CPU1 must notify CPU2 that CPU1 has completed the
power-down sequence so that both subsystems can continue.
The previous procedure must be executed from RAM and not from Flash. Note that exclusive control of the
Flash pump must be gained by a CPU (using Flash pump semaphore PUMPREQUEST) before configuring the
PMPPWR bit field of the FPAC1 register as shown in the previous sequence. As the charge pump is shared
between CPU1-FMC and CPU2-FMC, the effective PMPPWR value used when powering down the pump is
of the FMC (out of CPU1-FMC and CPU2-FMC) that owns the pump. The application software can check the
current power mode of the Flash bank by reading the FBPRDY register. The PUMPRDY bit in the FBPRDY
register in CPU1-FMC and CPU2-FMC together reflect the power mode of the charge pump. A value of 0 in the
PUMPRDY bit in both CPU1-FMC and CPU2-FMC indicates that the charge pump is in sleep mode. A value of
1 in the PUMPRDY bit in either CPU1-FMC or CPU2-FMC or in both CPU1-FMC and CPU2-FMC indicates that
the charge pump is in active mode. Refer to the register descriptions, Section 3.17, for detailed information.
While the pump is in sleep state, a charge pump sleep down counter holds a user configurable value (PSLEEP
bit field in the FPAC1 register) and when the charge pump exits sleep power mode, the down counter delays
from 0 to PSLEEP prescaled SYSCLK clock cycles (prescaled clock is SYSCLK/2) before putting the charge
pump into active power mode. Note that the configured PSLEEP value must yield at least a delay of 20 µs for
the pump to go to active mode. Refer to the register descriptions, Section 3.17, for detailed information.
Following are the number of cycles for the Bank and pump to wake up from low-power modes:
• Pump sleep to active = PSLEEP * (SYSCLK/2) cycles
• Bank sleep to standby = 425 Flash clock cycles
• Bank standby to active = 90 Flash clock cycles
Where in Flash clock = SYSCLK/(RWAIT+1)

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3.12.7 Flash and OTP Memory Performance

Once the Flash bank and pump are in the active power state, a read or fetch access can be classified as a Flash
access (access to an address location in Flash) or an OTP memory access (access to an address location in
OTP memory). Once the CPU throws an access to a Flash memory address, data is returned after RWAIT+1
number of SYSCLK cycles. For a USER-OTP access, data is returned after 11 SYSCLK cycles.
RWAIT defines the number of random access wait-states and is configurable using the RWAIT bit-field in the
FRDCNTL register. At reset, the RWAIT bit-field defaults to a worst-case wait-state count (15), and therefore
needs to be initialized for the appropriate number of wait states to improve performance, based on the CPU
clock rate and the access time of the Flash. The Flash supports 0-wait accesses when the RWAIT bits are set to
zero. This assumes that the CPU speed is low enough to accommodate the access time.
For a given system clock frequency, RWAIT has to be configured using the formula:
RWAIT = ceiling[(SYSCLK/FCLK)-1]

where SYSCLK is the system operating frequency

FCLK is Flash clock frequency. FCLK must be ≤ FCLKmax, allowed maximum Flash clock frequency at
RWAIT=0.
If RWAIT results in a fractional value when calculated using the above formula, RWAIT has to be rounded up to
the nearest integer.
3.12.8 Flash Read Interface
This section provides details about the data read modes to access Flash bank/OTP memory and the
configuration registers which control the read interface. In addition to a standard read mode, the FMC has
a built-in prefetch and cache mechanism to allow increased clock speeds and CPU throughput wherever
applicable.
3.12.8.1 FMC Flash Read Interface
3.12.8.1.1 Standard Read Mode
Standard read mode is defined as the read mode in effect when code prefetch-mechanism and data cache are
disabled. Standard read mode is also the default read mode after reset. During this mode, each read access to
Flash is decoded by the Flash wrapper to fetch the data from the addressed location and the data is returned
after the RWAIT+1 number of cycles.
Prefetch buffers associated with prefetch mechanism and data cache are bypassed in standard read mode;
therefore, every access to the Flash/OTP memory is used by the CPU immediately, and every access creates a
unique Flash bank access.
Standard read mode is the recommended mode for lower system-frequency operation in which RWAIT can be
set to zero to provide single-cycle access operation. The FMC can operate at higher frequencies using standard
read mode at the expense of adding wait states. At higher system frequencies, it is recommended to enable
cache and prefetch mechanisms to improve performance. Refer to the device specific data sheet to determine
the maximum Flash frequency allowed in standard read mode (that is, maximum Flash clock frequency with
RWAIT=0, FCLKMAX).
3.12.8.1.2 Prefetch Mode
Flash memory is typically used to store application code. During code execution, instructions are fetched from
sequential memory addresses, except when a discontinuity occurs. Usually the portion of the code that resides
in sequential addresses makes up the majority of the application code and is referred to as linear code. To
improve the performance of linear code execution, a Flash prefetch-mechanism has been implemented in the
FMC. Figure 3-18 illustrates how this mode functions.

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Flash and OTP

16-bit

Flash prefetch
Instruction buffer

Flash or OTP Read (128-bit)

128-bit 128-bit
buffer buffer

Instruction fetch

128-bit
M Data cache
CPU 32-bit U
X

Data read from data memory

Figure 3-18. Flash Prefetch Mode

This prefetch mechanism does a look-ahead prefetch on linear address increments starting from the address of
the last instruction fetch. The Flash prefetch mechanism is disabled by default. Setting the PREFETCH_EN bit in
the FRD_INTF_CTRL register enables this prefetch mode.
An instruction fetch from the Flash or OTP memory reads out 128 bits per access. The starting address of the
access from Flash is automatically aligned to a 128-bit boundary, such that the instruction location is within the
128 bits to be fetched. With the Flash prefetch mode enabled, the 128 bits read from the instruction fetch are
stored in a 128-bit wide by 2-level deep instruction prefetch buffer. The contents of this prefetch buffer are then
sent to the CPU for processing as required.
Up to four 32-bit or eight 16-bit instructions can reside within a single 128-bit access. The majority of C28x
instructions are 16 bits, so for every 128-bit instruction fetch from the Flash bank, it is likely that there are up to
eight instructions in the prefetch buffer ready to process through the CPU. During the time it takes to process
these instructions, the Flash prefetch mechanism automatically initiates another access to the Flash bank to
prefetch the next 128 bits. In this manner, the Flash prefetch mechanism works in the background to keep the
instruction prefetch buffers as full as possible. Using this technique, the overall efficiency of sequential code
execution from Flash or OTP memory is improved significantly.

Note
If the prefetch mechanism is enabled, then the last two rows (16 16-bit words, 256 bits) of the bank
that does not have a valid address beyond the boundary must not be used, because the prefetch logic
that does a look-ahead prefetch tries to fetch from outside the bank and can result in an ECC error.

The Flash prefetch is aborted only on a PC discontinuity caused by executing an instruction such as a branch,
BANZ, call, or loop. When this occurs, the prefetch mechanism is aborted and the contents of the prefetch buffer
are flushed. There are two possible scenarios when this occurs:
1. If the destination address is within the Flash or OTP memory, the prefetch aborts and then resumes at the
destination address.

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2. If the destination address is outside of the Flash and OTP memory, the prefetch is aborted and begins
again only when a branch is made back into the Flash or OTP memory. The Flash prefetch mechanism only
applies to instruction fetches from program space. Data reads from data memory and from program memory
do not utilize the prefetch buffer capability and thus bypass the prefetch buffer. For example, instructions
such as MAC, DMAC, and PREAD read a data value from program memory. When this read happens, the
prefetch buffer is bypassed but the buffer is not flushed. If an instruction prefetch is already in progress when
a data read operation is initiated, then the data read is stalled until the prefetch completes.
Note that the prefetch mechanism gets bypassed when RWAIT is configured as zero.
3.12.8.1.2.1 Data Cache
Along with the prefetch mechanism, a data cache of 128-bits wide is also implemented to improve data-space
read performance. This data cache is not filled by the prefetch mechanism. When any kind of data-space read
is made by the CPU from an address in the bank, and if the data corresponding to the requested address is
not in the data cache, then 128 bits of data is read from the bank and loaded in the data cache. This data
is eventually sent to the CPU for processing. The starting address of the access from Flash is automatically
aligned to a 128-bit boundary such that the requested address location is within the 128 bits to be read from
the bank. By default, this data cache is disabled and can be enabled by setting DATA_CACHE_EN bit in the
FRD_INTF_CTRL register. Note that the data cache gets bypassed when RWAIT is configured as zero.
Some other points to keep in mind when working with Flash/ OTP memory:
• Reads of the USER OTP locations are hardwired for 10 wait states. The RWAIT bits have no effect on these
locations.
• CPU writes to the Flash or OTP memory-map areas are ignored. The writes complete in a single cycle.
• If a security zone is in the locked state and the respective password lock bits are not all 1s, then,
– Data reads to Zx-CSMPSWD return 0
– Program space reads to Zx-CSMPSWD return 0
– Program fetches to Zx-CSMPSWD return 0
• When the Code Security Module (CSM) is secured, reads to the Flash/OTP memory-map area from outside
the secure zone take the same number of cycles as a normal access. However, the read operation returns a
zero.
• The arbitration scheme in FMC prioritizes CPU accesses in the fixed priority order of data read (highest
priority), program space read and program fetches/program prefetches (lowest priority).
• When FSM interface is active for erase/program operations, data in the prefetch buffers and data cache in
FMC are flushed.
• When data cache is enabled, the debugger memory window open to Flash/OTP memory space invokes data
caching. Hence, the debugger memory window must not be left open for Flash/OTP memory space when
benchmarking the code for performance.

Note
Flash contents are verified for ECC correctness before the contents enter the prefetch buffer or data
cache and not inside the prefetch buffer or data cache itself.

3.12.9 Erase/Program Flash

Flash memory can be programmed either by using the CCS Flash plugin or by using UniFlash. If these methods
are not feasible in an application, the API can be used. The Flash memory must be programmed, erased, and
verified only by using the F021 Flash API library. These functions are written, compiled and validated by Texas
Instruments. The Flash module contains a Flash state machine (FSM) to perform program and erase operations.
This section only provides a high level description for these operations, therefore, refer to the TMS320F2837xD
Flash API Version 1.54 Reference Guide for more information. Note that Flash API execution is interruptible.
However, there must not be any read/fetch access from the Flash bank on which an erase/program operation is
in progress. Flash API must be executed from RAM.

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A typical flow to program Flash is:

Erase → Program → Verify
Always refer to the device-specific support folder in the controlSUITE™ software for the latest Flash API library.
3.12.9.1 Erase
When the target Flash is erased, Flash reads as all 1s. This state is called 'blank.' The erase function must
be executed before programming. The user must not skip erase on sectors that read as 'blank', because these
sectors can require additional erasing due to marginally erased bits columns. The FSM provides an “Erase
Sector” command to erase the target sector. The erase function erases the data and the ECC together. This
command is implemented by the following Flash API function:
Fapi_issueAsyncCommandWithAddress();
The Flash API provides the following function to determine if the Flash bank is 'blank':
Fapi_doBlankCheck();
3.12.9.2 Program
The FSM provides a command to program the USER OTP and Flash. This command is also used to program
ECC check bits.
This command is implemented by the following Flash API function:
Fapi_issueProgrammingCommand();
The Program function provides the options to program data without ECC, data along with user-provided ECC
data, data along with ECC calculated by API software , and to program ECC only.
3.12.9.3 Verify
After programming, the user must perform verify using API function Fapi_doVerify(). This function verifies the
Flash contents against supplied data.
Application software typically perform a CRC check of the Flash memory contents during power-up and at
regular intervals during runtime (as needed). Apart from this, ECC logic, when enabled (enabled by default),
catches single-bit errors, double-bit errors, and address errors whenever the CPU reads/fetches from a Flash
address.
3.12.10 Error Correction Code (ECC) Protection
CPU1-FMC and CPU2-FMC contain an embedded single error correction and double error detection (SECDED)
module. SECDED, when enabled, provides the capability to screen out memory faults. SECDED can detect and
correct single-bit data errors and detect address errors/double-bit data errors. For every 64 bits of Flash/OTP
memory data (aligned on a 64-bit memory boundary) that is programmed, eight ECC check bits have to be
calculated and programmed in ECC memory space. Refer to the device data sheet for the Flash/OTP memory
ECC memory-map. SECDED works with a total of eight user-calculated error correction code (ECC) check bits
associated with each 64-bit wide data word and the corresponding 128-bit memory-aligned address. Users must
program ECC check bits along with Flash data. TI recommends using the AutoEccGeneration option available in
Plugin/API to program ECC. Users can use the F021 Flash API to calculate and program ECC data along with
Flash data. Flash API uses hardware ECC logic in the device to generate the ECC data for the given Flash data.
The Flash Plugin, the Flash programming tool integrated with Code Composer Studio IDE, uses Flash API to
generate and program ECC data).
Figure 3-19 illustrates the ECC logic inputs and outputs.

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Single-bit data error

Address/Double-bit data error
Single-bit Error position
Corrected data out
SECDED ECC[15:8]

Data[127:64]

128-bit aligned 19-bit CPU address

Flash
and
OTP

Single-bit data error

Address/Double-bit data error
Single-bit Error position
Corrected data out
SECDED Data[63:0]

ECC[7:0]

Figure 3-19. ECC Logic Inputs and Outputs

During an instruction fetch or a data read operation, the 19 most-significant address bits (3 least-significant
bits of address are not considered), together with the 64-bit data/8-bit ECC read-out of Flash banks/ECC
memory-map area, pass through the SECDED logic and the eight checkbits are produced in FMC. These eight
calculated ECC check bits are then XORed with the stored check bits (user programmed check bits) associated
with the address and the read data. The 8-bit output is decoded inside the SECDED module to determine one of
three conditions:
• No error occurred
• A correctable error (single bit data error) occurred
• A non-correctable error (double bit data error or address error) occurred
If the SECDED logic finds a single-bit error in the address field, then the error is considered to be a non-
correctable error.

Note
TI recommends programming ECC while programming Flash to avoid any error. Since ECC is
calculated for an entire 64-bit data, a non 64-bit read such as a byte read or a half-word read still
forces the entire 64-bit data to be read and calculated, but only the byte or half-word is actually used
by the CPU.

This ECC (SECDED) feature is enabled at reset. The ECC_ENABLE register can be used to configure( enable/
disable) the ECC feature. The ECC for the application code must be programmed. There are two SECDED
modules in each FMC. Out of the 128-bit data (aligned on a 128-bit memory boundary) read from the bank/OTP
memory address, the lower 64-bits of data and corresponding 8 ECC bits (read from user programmable ECC
memory area) are fed as inputs to one SECDED module along with 128-bit aligned 19-bit address from where
data has been read. The upper 64- bits of data and corresponding 8 ECC bits are fed as inputs to another
SECDED module in parallel, along with 128-bit aligned 19-bit address. Each of the SECDED modules evaluate
their inputs and determine if there is any single-bit data error or double-bit data error/address error.

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ECC logic is bypassed when the 64 data bits and the associated ECC bits fetched from the bank are either all
ones or zeros.
3.12.10.1 Single-Bit Data Error
This section provides information for both single-bit data errors and single-bit ECC check bit errors. If there is a
single bit flip (0 to 1 or 1 to 0) in Flash data or in ECC data, then it is considered as a single-bit data error. The
SECDED module detects and corrects single-bit errors, if any, in the 64-bit Flash data or eight ECC check bits
read from the Flash/ECC memory map before the read data is provided to the CPU.
When SECDED finds and corrects single bit data errors, the following information is logged in the ECC registers
if the ECC feature is enabled:
• Address where the error occurred – if the single-bit error occurs in the lower 64-bits of a 128-bit memory-
aligned data, the lower 64-bit memory-aligned address is captured in the SINGLE_ERR_ADDR_LOW
register. If the single-bit error occurs in the upper 64-bits of a 128-bit memory-aligned data, the upper 64-bit
memory-aligned address is captured in the SINGLE_ERR_ADDR_HIGH register.
• Whether the error occurred in data bits or ECC bits – the ERR_TYPE_L and ERR_TYPE_H bit fields in the
ERR_POS register indicate whether the error occurred in data bits or ECC bits of the lower 64-bits, or the
upper 64-bits respectively, of a 128-bit memory-aligned data.
• Bit position at which error occurred – the ERR_POS_L and ERR_POS_H bit fields in the ERR_POS register
indicate the bit position of the error in the lower 64-bits/lower 8-bit ECC, or the upper 64-bits/upper 8-bit ECC
respectively, of a 128-bit memory-aligned data.
• Whether the corrected value is 0 (FAIL_0_L, FAIL_0_H flags in ERR_STATUS register)
• Whether the corrected value is 1 (FAIL_1_L, FAIL_1_H flags in ERR_STATUS register)
• A single bit error counter that increments on every single bit error occurrence (ERR_CNT register) until a
user-configurable threshold (see ERR_THRESHOLD) is met
• A flag that gets set when one or more single-bit errors occurs after ERR_CNT equals ERR_THRESHOLD
(SINGLE_ERR_INT_FLG flag in the ERR_INTFLG register)
When the ERR_CNT value equals THRESHOLD+1 value and a single bit error occurs, the SINGLE_ERR_INT
flag is set, and an interrupt (FLASH_CORRECTABLE_ERR on C28x PIE has to be enabled for interrupt, if
needed) is fired. The SINGLE_ERR interrupt is not fired again until the SINGLE_ERR_INTFLG is cleared. If the
single error interrupt flag is not cleared using the corresponding error interrupt clear bit in the ERR_INTCLR
register, the error interrupt does not come again, as this is an edge-based interrupt.
When multiple single-bit errors get caught by ECC logic, Flash ECC registers hold the information related to the
latest ECC error. When multiple single-bit errors get caught, both FAIL_0_L and FAIL_1_L (and/or FAIL_0_H and
FAIL_1_H) might get set, indicating that single-bit fail0/fail1 occurred in different 64-bit aligned addresses.
Although ECC is calculated on 64-bit basis, a read of any address location within a 128-bit aligned Flash
memory causes the single-bit error flag to get set when there is a single-bit error in both or in either one of the
lower 64 and upper 64 bits (or corresponding ECC check bits) of that 128-bit data.
3.12.10.2 Uncorrectable Error
Uncorrectable errors include address errors and double-bit errors in data/ECC. When SECDED finds
uncorrectable errors, the following information is logged in ECC registers if the ECC feature is enabled:
• Address where the error occurred – if the uncorrectable error occurs in the lower 64-bits of a 128-bit
memory-aligned data, the lower 64-bit memory-aligned address is captured in the UNC_ERR_ADDR_LOW
register. If the uncorrectable error occurs in the upper 64-bits of a 128-bit memory-aligned data, the upper
64-bit memory-aligned address is captured in the UNC_ERR_ADDR_HIGH register.
• A flag is set indicating that an uncorrectable error occurred – the UNC_ERR_L and UNC_ERR_H flags in the
ERR_STATUS register indicate the uncorrectable error occurrence in the lower 64-bits/lower 8-bit ECC, or
the upper 64-bits/upper 8-bit ECC, respectively, of a 128-bit memory-aligned data.
• A flag is set indicating that an uncorrectable error interrupt is fired (UNC_ERR_INTFLG in ERR_INTFLG
register)

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When an uncorrectable error occurs, the UNC_ERR_INTFLG bit is set and an uncorrectable error interrupt is
fired. This uncorrectable error interrupt generates an NMI, if enabled. If an uncorrectable error interrupt flag is
not cleared using the corresponding error interrupt clear bit in the ERR_INTCLR register, an error interrupt does
not come again, as this is an edge based interrupt.
Although ECC is calculated on 64-bit basis, a read of any address location within a 128-bit aligned Flash
memory causes the uncorrectable error flag to get set when there is a uncorrectable error in both or in either one
of the lower 64 and upper 64 bits (or corresponding ECC check bits) of that 128-bit data. NMI occurs on the CPU
for a read of any address location within a 128-bit aligned Flash memory, when there is an uncorrectable error in
both or in either one of the lower 64 and upper 64 bits (or corresponding ECC check bits) of that 128-bit data.
3.12.10.3 SECDED Logic Correctness Check
Since error detection and correction logic are part of safety-critical logic, safety applications need to make sure
that the SECDED logic is always working properly. For these safety concerns, make sure the correctness of
the SECDED logic, an ECC test mode is provided to test the correctness of ECC logic periodically. In this
ECC test mode, data/ECC and address inputs to the ECC logic are controlled by the ECC test mode registers
FDATAH_TEST, FDATAL_TEST, FECC_TEST, and FADDR_TEST, respectively. Using this test mode, users
can introduce single-bit errors, double-bit errors, or address errors and check whether or not SECDED logic is
catching those errors. Users can also check if SECDED logic is reporting any false errors when no errors are
introduced.
This ECC test mode can be enabled by setting the ECC_TEST_EN bit in the FECC_CTRL register. When
ECC test mode is enabled, the CPU cannot read the data from Flash and instead the CPU gets data from
the ECC test mode registers (FDATAH_TEST/FDATAL_TEST). This is because ECC test mode registers
(FDATAH_TEST, FDATAL_TEST, FECC_TEST) are multiplexed with data from the Flash. Hence, the CPU must
not read/fetch from Flash when ECC test mode is enabled. For this reason, ECC test mode code must be
executed from RAM and not from Flash.
Only one of the SECDED modules (out of the two SECDED modules that work on lower 64 bits and upper 64
bits of a read 128-bit data) at a time can be tested. The ECC_SELECT bit in the FECC_CTRL register can be
configured by users to select one of the SECDED modules for test.
To test the ECC logic using ECC test mode, users can follow the steps below:
1. Obtain the ECC for a given Flash address (128-bit aligned) and 64-bit data by using the Auto ECC
generation option provided in Flash API .
2. Develop an application to test ECC logic using the above data. In this application
• Write the 128-bit aligned 19-bit Flash address in FADDR_TEST
• Write 64-bit data in FDATAH_TEST (upper 32-bits) and FDATAL_TEST (lower 32-bits) registers
• Write the corresponding 8-bit ECC in the FECC_TEST register
• In any of the above three steps, users can insert errors (single-bit data error or double-bit data error or
address error or single-bit ECC error or double-bit ECC error) to check whether or not ECC logic is able
to catch the errors
• Select the ECC logic block (lower 64-bits or upper 64-bits) which needs to be tested using the
ECC_SELECT bit in the FECC_CTRL register
• Enable ECC test mode using the ECC_TEST_EN bit in FECC_CTRL register
• Write a value of 1 in the DO_ECC_CALC bit in FECC_CTRL register to enable ECC test logic for a single
cycle to evaluate the address, data, ECC in FADDR_TEST, FDATAx_TEST and FECC_TEST registers
for ECC errors
Once the above ECC test mode registers are written by the user:
• The FECC_OUTH register holds the data output bits 63:32 from the SECDED block under test
• The FECC_OUTL register holds the data output bits 31:0 from the SECDED block under test
• The FECC_STATUS register holds the status of single-bit error occurrence, uncorrectable error occurrence,
and error position of single- bit error in data/check bits

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3.12.10.4 Reading ECC Memory From a Higher Address Space

In these devices, ECC memory for Flash and OTP memory is allocated at a higher address space (address
width more than 22 bits). C2000 Codegen tools (6.2 and onwards) are updated to include the below intrinsics to
read ECC space.
For 16-bit read: unsigned int variable = __addr32_read_uint16(unsigned long address);
For 32-bit read: unsigned long variable = __addr32_read_uint32(unsigned long address);
3.12.11 Reserved Locations Within Flash and OTP Memory
When allocating code and data to Flash and OTP memory, keep the following reserved locations in mind:
• The entire OTP memory has reserved user-configurable locations for security and boot process. For more
details on the functionality of these fields, refer to Section 3.13 and Chapter 4.
• Refer to Chapter 4 for reserved locations in Flash for real-time operating system usage and a boot-to-Flash
entry point. A boot-to-Flash entry point is reserved for an entry-into-Flash branch instruction. When the
boot-to-Flash boot option is used, the boot ROM jumps to this address in Flash. If the user programs a
branch instruction here, that then redirects code execution to the entry point of the application.
3.12.12 Procedure to Change the Flash Control Registers
During Flash configuration, no accesses to the Flash or OTP memory can be in progress. This includes
instructions still in the CPU pipeline, data reads, and instruction prefetch operations. To be sure that no access
takes place during the configuration change, follow this procedure for any code that modifies the Flash control
registers.
1. Start executing application code from RAM/Flash/OTP memory.
2. Branch to or call the Flash configuration code (that writes to Flash control registers) in RAM. This is required
to properly flush the CPU pipeline before the configuration change. The function that changes the Flash
configuration cannot execute from the Flash or OTP memory. The function must reside in RAM.
3. Execute the Flash configuration code (must be located in RAM) that writes to Flash control registers like
FRDCNTL, FRD_INTF_CTRL, and so on.
4. At the end of the Flash configuration code execution, wait eight cycles to let the write instructions propagate
through the CPU pipeline. This must be done before the return-from-function call is made.
5. Return to the calling function that resides in RAM or Flash/OTP memory and continue execution.
3.12.13 Simple Procedure to Modify an Application from RAM Configuration to Flash Configuration
All of the C2000Ware example projects are provided with both RAM and Flash build configurations. To change
the build configuration from RAM to Flash, import the project in to the CCS IDE and right click on the project and
select 'Build Configurations' -> 'Set Active' -> 'Flash'. By selecting this, notice that:
1. _FLASH symbol is defined in the "Predefined symbols" section under Project Build settings. This is used to
define and execute any Flash-build specific code.
2. Flash-based linker command file is chosen for the application instead of a RAM-based linker command
file. Flash-based linker command files are provided in the C2000Ware for reference (for example:
XXX_FLASH_lnk_cpu1.cmd at C2000Ware_x_xx_xx_xx\device_support\XXX\common\cmd). Flash-based
linker command files have codestart mapped to a Flash entry point address.
3. All of the initialized sections are mapped to Flash memory in the Flash-based linker command file.
4. All of the functions that need to execute from RAM (for initialization or 0-wait performance purpose) are
assigned to the .TI.ramfunc section in the code. For example, Flash_initModule() is assigned to .TI.ramfunc
section.
5. TI.ramfunc section is mapped to a Flash address for “Load” and a RAM address for “RUN” in the Flash-
based linker command file.
6. All of the sections mapped to Flash are aligned on a 128-bit boundary using the ALIGN() directive in the
Flash-based linker command file.
7. memcpy() function is called in the application to copy the .TI.ramfunc content from Flash to RAM. The
memcopy() is called before executing any code that is assigned to .TI.ramfunc section.

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8. For EABI type executable: All uninitialized sections mapped to RAM are defined as NOINIT sections (using
the directive “type=NOINIT”) in the linker cmd file.

3.12.14 Flash Pump Ownership Semaphore

Each CPU subsystem has a Flash bank, which the CPU subsystem can read, program, and erase. Both Flash
banks share a single charge pump for program and erase operations. Hence, only one CPU can program or
erase the Flash at any given time. A CPU can read data and execute code from the Flash even when the other
CPU is programming or erasing. The Flash pump ownership semaphore allows one CPU to take control of the
pump without being interrupted by the other CPU.
The pump ownership semaphore is implemented as a two-bit field in a PUMPREQUEST register with special
write protections. This register requires a key field to be written at the same time as the semaphore bits. The
possible semaphore states are:
00 or 11 Either CPU can write to the semaphore. CPU1 has control of the resource by default.
00 is the reset state.
01 CPU2 has exclusive control of the resource and exclusive write access to the
semaphore.
10 CPU1 has exclusive control of the resource and exclusive write access to the
semaphore.

Each CPU is only allowed to take control of the pump for itself. Direct transfer between the 01 and 10 states is
not allowed. However, CPU1 can force both semaphores into the default state (00) at any time by putting CPU2
into reset. Figure 3-20 shows the allowed states and state transitions.
CPU1 should write 10 to gain pump CPU2 should write 01 to gain pump
control before erasing or programming Semaphore state 00 or 11 control before erasing or programming
its flash bank. its flash bank.
Pump controlled by CPU1

CPU1 should write 00 to relinquish Default at reset

CPU2 should write 00 to relinquish
pump control once the erase or
pump control once the erase or
program is complete.
program is complete.

Semaphore state 10 Semaphore state 01

Not allowed
Pump controlled by CPU1 Pump controlled by CPU2
Not allowed
CPU2 cannot take control of the pump in this CPU1 cannot take control of the pump in this
state. state.

Figure 3-20. Flash Pump Semaphore (PUMPREQUEST) States and State Transitions

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3.12.14.1 Clock Configuration Semaphore

Both CPUs can access the PLL and peripheral clock configuration registers. The clock configuration semaphore
allows one CPU to access the registers without being interrupted by the other CPU.
The clock configuration semaphore is implemented as a two-bit field in a register with special write protections.
This register requires a key field to be written at the same time as the semaphore bits. The possible semaphore
states are:

00 or 11 Either CPU can write to the semaphore. CPU1 has control of the clock configuration
registers by default. 00 is the reset state.
01 CPU2 has exclusive control of the clock configuration registers and exclusive write
access to the semaphore.
10 CPU1 has exclusive control of the clock configuration registers and exclusive write
access to the semaphore.

Each CPU is only allowed to take control of the clock configuration registers for itself. However, CPU1 can force
both semaphores into the default state (00) at any time by putting CPU2 into reset. Figure 3-21 shows the
allowed states and state transitions.
CPU1 should write 10 to gain CPU2 should write 01 to gain
mastership of the clock configuration Semaphore state 00 or 11 mastership of the clock configuration
registers. registers.
Clock configuration registers
are controlled by CPU1
CPU1 should write 00 to relinquish
Default at reset CPU2 should write 00 to relinquish
mastership once configuration is
mastership once configuration is
complete.
complete.

Semaphore state 10 Semaphore state 01

Not allowed
Clock configuration registers Clock configuration registers
are controlled by CPU1 Not allowed are controlled by CPU2

CPU2 cannot take control of the pump in this CPU1 cannot take control of the pump in this
state state

Figure 3-21. Clock Configuration Semaphore (CLKSEM) State Transitions

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3.13 Dual Code Security Module (DCSM)

The dual code security module (DCSM) is a security feature incorporated in this device. It prevents access and
visibility to on-chip secure memories (and other secure resources) to unauthorized persons. It also prevents
duplication and reverse engineering of proprietary code. The term “secure” implies access to on-chip secure
memories and resources are blocked. The term “unsecure” implies access is allowed (the contents of the
memory could be read by any means); for example, through a debugging tool such as the Code Composer
Studio™ IDE.
There are two CPUs on this device and each CPU subsystem has its own CSM for code protection. Each CPU
subsystem’s CSM has dual-zone security, which means the CPU1 subsystem has two zones (zone1/zone2) and
CPU2 also has two zones (zone1/zone2).
3.13.1 Functional Description
The security module restricts the CPU access to on-chip secure memory and resources without interrupting
or stalling CPU execution. When a read occurs to a secure memory location, the read returns a zero value
and CPU execution continues with the next instruction. This, in effect, blocks read and write access to secure
memories through the JTAG port or external peripherals.
The code security mechanism offers protection for two zones, Zone 1 (Z1) and Zone 2 (Z2). The security
mechanism for both the zones is identical. Each zone has a dedicated secure resource and allocated secure
resource. The following are different secure resources available on this device:
• OTP: Each zone has a dedicated secure OTP (USER OTP). This contains the security configurations for
the individual zone. If a zone is secure, the USER OTP content (including CSM passwords) can be read
(execution not allowed) only if the zone is unlocked using the password match flow (PMF).
• CLA: The CLA is a secure resource that can be allocated to either zone by configuring the GRABRAM
location in the USER OTP. CLA configuration can only be performed by code running from the zone to which
it has been allocated. The CLA message RAMs also belong to the same zone.

Table 3-16. CLA Access Filter

CLA Ownership RAM Block Ownership Fetch Access Read Access Write Access

None None Yes Yes Yes

None Z1 or Z2 No No No

Z1 Z1 Yes Yes Yes

Z1 Z2 No No No

Z1 None No Yes Yes

Z2 Z1 No No No

Z2 Z2 Yes Yes Yes

Z2 None No Yes Yes

• RAM: All Dx and LSx RAMs can be secure RAM on this device. These RAMs can be allocated to either zone
by configuring the respective GRABRAM location in the USER OTP.
• Flash Sectors: Flash Sectors can be secure on this device. Each Flash sector can be allocated to either
zone by configuring the respective GRABSECT location in the USER OTP.
• Secure ROM: This device also has secure ROM which is EXEONLY-protected. This ROM contains specific
function for the user, provided by TI.
Table 3-17 shows the status of a RAM block based on the configuration in GRABRAM register.

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Table 3-17. RAM Status

GRAM_RAMx Bits in Z1_GRABRAMR GRAM_RAMx Bits in Z2_GRABRAMR
Register Register Ownership
00 XX GRAM_RAMx is inaccessible
XX 00 GRAM_RAMx is inaccessible
Differential Value (01/10) Differential Value (01/10) GRAM_RAMx is inaccessible
Differential Value (01/10) 11 GRAM_RAMx belongs to Z1
11 Differential Value (01/10) GRAM_RAMx belongs to Z2
11 11 GRAM_RAMx is Non-Secure

The security of each zone is maintained by a 128-bit (four 32-bit words) password (CSM password). The
password for each zone is stored in a dedicated OTP memory location based on a zone-specific link pointer. A
zone can be unsecured by executing the password match flow (PMF), described in Section 3.13.3.3.2.
There are three types of accesses: data/program reads, JTAG access, and instruction fetches (calls, jumps,
code executions, ISRs). Instruction fetches are never blocked. JTAG accesses are always blocked when a
memory is secure. Data reads to a secure memory are always blocked unless the program is executing from
a memory which belongs to the same zone. Data reads to unsecure memory are always allowed. Table 3-18
shows the levels of security.
Table 3-18. Security Levels
PMF Executed With Correct
Password? Operating Mode of the Zone Program Fetch Location Security Description
No Secure Outside secure memory Only instruction fetches by the
CPU are allowed to secure
memory. In other words, code
can still be executed, but not
read.
No Secure Inside secure memory CPU has full access (except
for EXEONLY memories where
read is not allowed). JTAG port
cannot read the secured memory
contents.
Yes Non-Secure Anywhere Full access for CPU and JTAG
port to secure memory of that
zone.

If the password locations of a zone have all 128 bits as ones, the zone is considered unsecure. Since new Flash
devices have erased Flash (all ones), only a read of the password locations is required to bring any zone into
unsecure mode. If the password locations of a zone have all 128 bits as zeros, the zone is secure, regardless
of the contents of the CSMKEY registers. This means the zone cannot be unlocked using PMF, the password
match flow described in Section 3.13.3.3.2. Therefore, the user must never use all zeros as a password. A
password of all zeros prevents debug of secure code or reprogramming the Flash.
CSMKEY registers are user-accessible registers that are used to unsecure the zones.
3.13.1.1 Emulation Code Security Logic (ECSL)
In addition to the CSM, the emulation code security logic (ECSL) has been implemented using a 64-bit password
(part of existing CSM password) for each zone to prevent unauthorized users from stepping through secure
code. A halt in secure code while the emulator is connected trips the ECSL and break the emulation connection
to the specific CPU subsystem for which the ECSL violation occurred. To allow emulation of secure code, while
maintaining the CSM protection against secure memory reads, the user must write the correct 64-bit password
into the CSMKEY (0/1) registers, which matches the password value stored in the USER OTP of that zone. This
disables the ECSL for the specific zone.

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When initially debugging a device with the password locations in OTP memory programmed (secured), the
emulator takes some time to take control of the CPU. During this time, the CPU starts running and executes an
instruction that performs an access to a protected ECSL area and if the CPU is halted when the program counter
(PC) is pointing to a secure location, the ECSL trips and causes the emulator connection to be broken.
A solution to this problem is:
• Use the Wait Boot Mode boot option. In this mode, the CPU is in a loop and hence does not jump to the user
application code. Using this BOOTMODE, the user can connect to CCS and debug the code.

3.13.1.2 CPU Secure Logic

The CPU Secure Logic (CPUSL) on this device prevents a hacker from reading the CPU registers in a watch
window while code is running in a secure zone. All accesses to CPU registers when the PC points to a secure
location are blocked by this logic. The only exception to this is read access to the PC. It is highly recommended
not to write into the CPU register in this case, because proper code execution may get affected. If the CSM is
unlocked using the CSM password match flow, the CPUSL logic also gets disabled.
3.13.1.3 Execute-Only Protection
To achieve a higher level of security on secure Flash sectors and RAM blocks that store critical user code
(instruction opcodes), the Execute-Only protection feature is provided. When the Execute-Only protection is
turned on for any secure Flash sector or RAM block, data reads to that Flash sectors are disallowed from any
code (even from secure code). Execute-only protection for a Flash sector and RAM block can be turned on by
configuring the bit field associated for that particular sector/RAM block in the zone's (which has ownership of that
sector/RAM block) EXEONLYSECT and EXEONLYRAM register, respectively.
3.13.1.4 Password Lock
The password locations for each zone can be locked by programming the zone’s PSWDLOCK field with any
value other than 1111 (0xF) at the PSWDLOCK location in OTP memory. Until the passwords of a zone are
locked, password locations are not secure and can be read from the debugger as well as code running from non-
secure memory. This feature can be used by the user to avoid accidental locking of the zone while programming
the Flash sectors during the software development phase. On a new device, the value for password lock fields
for all zones at the PSWDLOCK location in OTP memory is 1111, which means the password for all zones is
unlocked.

Note
Password unlock only makes password locations non-secure. All other secure memories and other
locations of Flash sectors, which contain a password, remains secure as per security settings. But
since passwords are non-secure, anyone can read the password and make the zone non-secure by
running through PMF.

3.13.1.5 JTAG Lock

The JTAG lock feature can be used to permanently disable any access to the device using the JTAG port. For
example, access by the Code Composer Studio™ IDE debugger or Flash programming tools are blocked. This
feature is enabled by programming the Z1OTP_JTAGLOCK location in user OTP memory with any value other
than 1111 (0xF). Values of CRCLOCK, JTAGLOCK, and PSWDLOCK locations in the OTP memory are copied in
the Z1_OTPSECLOCK register by the boot-ROM code.

CAUTION
If the JTAG lock feature is enabled, all future debug of the device through JTAG is disabled. This
specifically impairs TI's ability to analyze devices returned to TI for failure analysis. If the JTAG lock
feature is enabled, TI rejects any return analysis requests.

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3.13.1.6 Link Pointer and Zone Select

For each of the two security zones of each CPU subsystem on this device, a dedicated OTP memory block
exists that holds the configuration related to zone’s security. The following are the available programmed
configurations:
• Zx-LINKPOINTER1
• Zx-LINKPOINTER2
• Zx-LINKPOINTER3
• Zx-PSWDLOCK
• Zx-CRCLOCK
• Zx-BOOTCTRL
• Zx-EXEONLYRAM
• Zx-EXEONLYSECT
• Zx-GRABRAM
• Zx-GRABSECT
• Zx-CSMPASSWORD
Since OTP memory cannot be erased, to provide flexibility of configuring some of the security settings like
CSM passwords, allocation of RAM/Flash sectors and the attributes, multiple times by the user, the following
configurations are placed in zone select regions of each zone’s OTP Flash.
• Zx-EXEONLYRAM
• Zx-EXEONLYSECT
• Zx-GRABRAM
• Zx-GRABSECT
• Zx-CSMPASSWORD
The location of the zone select region in OTP memory is decided based on the value of three 29-bit link pointers
(Zx-LINKPOINTERx) programmed in the OTP memory of each zone of both CPU subsystems. All OTP memory
locations except link pointer locations are protected with ECC. Since the link pointer locations are not protected
with ECC, three link pointers are provided that need to be programmed with the same value. The final value
of the link pointer is resolved in hardware when a dummy read is done to all the link pointers by comparing
all the three values (bit-wise voting logic). Since in OTP memory, a 1 can be flipped by the user to 0 but a 0
cannot be flipped to a 1 (no erase operation for OTP memory), the most-significant bit position in the resolved
link pointer that is 0 defines the valid base address for the zone select region. While generating the final link
pointer value, if the bit patterns is not one of those listed in Figure 3-22, the final link pointer value becomes All_1
(0xFFFF_FFFF) that selects the Zone-Select-Block1 (also known as the default zone select block).

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Addr Offset Of
Zx-LINKPOINTER Zone-Select
Block
32’bxxx11111111111111111111111111111 0x20
32’bxxx1111111111111111111111111111 0 0x30
32’bxxx111111111111111111111111111 0x 0x40
32’bxxx11111111111111111111111111 0xx 0x50
32’bxxx1111111111111111111111111 0xxx 0x60
32’bxxx111111111111111111111111 0xxxx 0x70 Zone Select Block
32’bxxx11111111111111111111111 0xxxxx 0x80
32’bxxx1111111111111111111111 0xxxxxx 0x90 Addr Offset 32-Bit Content
32’bxxx111111111111111111111 0xxxxxxx 0xa0
0x0 Zx-EXEONLYRAM
32’bxxx11111111111111111111 0xxxxxxxx 0xb0
32’bxxx1111111111111111111 0xxxxxxxxx 0xc0 0x2 Zx-EXEONLYSECT
32’bxxx111111111111111111 0xxxxxxxxxx 0xd0
32’bxxx11111111111111111 0xxxxxxxxxxx 0xe0 0x4 Zx-GRABRAM
32’bxxx1111111111111111 0xxxxxxxxxxxx 0xf0
32’bxxx111111111111111 0xxxxxxxxxxxxx 0x100 0x6 Zx-GRABSECT
32’bxxx11111111111111 0xxxxxxxxxxxxxx 0x110
0x8 Zx-CSMPSWD0
32’bxxx1111111111111 0xxxxxxxxxxxxxxx 0x120
32’bxxx111111111111 0xxxxxxxxxxxxxxxx 0x130 0xa Zx-CSMPSWD1
32’bxxx11111111111 0xxxxxxxxxxxxxxxxx 0x140
32’bxxx1111111111 0xxxxxxxxxxxxxxxxxx 0x150 0xc Zx-CSMPSWD2
32’bxxx111111111 0xxxxxxxxxxxxxxxxxxx 0x160
32’bxxx11111111 0xxxxxxxxxxxxxxxxxxxx 0x170 0xe Zx-CSMPSWD3
32’bxxx1111111 0xxxxxxxxxxxxxxxxxxxxx 0x180
32’bxxx111111 0xxxxxxxxxxxxxxxxxxxxxx 0x190
32’bxxx11111 0xxxxxxxxxxxxxxxxxxxxxxx 0x1a0
32’bxxx1111 0xxxxxxxxxxxxxxxxxxxxxxxx 0x1b0
32’bxxx111 0xxxxxxxxxxxxxxxxxxxxxxxxx 0x1c0
32’bxxx11 0xxxxxxxxxxxxxxxxxxxxxxxxxx 0x1d0
32’bxxx10xxxxxxxxxxxxxxxxxxxxxxxxxxx 0x1e0
32’bxxx0xxxxxxxxxxxxxxxxxxxxxxxxxxxx 0x1f0

Figure 3-22. Storage of Zone-Select Bits in OTP Memory

Note
Address locations for other security settings (PSWDLOCK/CRCLOCK) that are not part of Zone Select
blocks can be programmed only once; therefore, the user must program the address locations toward
the end of the development cycle.
Since linkpointer location in USER OTP does not have ECC, the user must always define a separate
structure and section for linkpointers.

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Zone 1 OTP Flash Zone 2 OTP Flash

0x78000 Z1-LINKPOINTER1 0x78200 Z2-LINKPOINTER1
0x78002 Reserved 0x78202 Reserved
0x78004 Z1-LINKPOINTER2 0x78204 Z2-LINKPOINTER2
0x78006 Reserved 0x78206 Reserved
0x78008 Z1-LINKPOINTER3 0x78208 Z2-LINKPOINTER3
0x7800A Reserved 0x7820A Reserved
0x78010 Z1-PSW DLOCK 0x78210 Z2 PSW DLOCK
Zone Select Block
0x78012 Reserved 0x78212 Reserved
Addr 32-Bit Content
0x78014 Z1-CRCLOCK 0x78214 Z2-CRCLOCK
Offset
0x78016 Reserved 0x78216 Reserved
0x0 Zx-EXEONLYRAM
0x78018 Z1-JTAGLOCK 0x78218 Z2-JTAGLOCK
0x2 Zx-EXEONLYSECT
0x7801A Reserved 0x7821A Reserved
0x4 Zx-GRABRAM
0x7801E Z1-BOOTCTRL 0x7821E Z2-BOOTCTRL
0x78020 ZoneSelectBlock1 0x6 Zx-GRABSECT 0x78220 ZoneSelectBlock1
(16x16Bits) (16x16Bits)
0x8 Zx-CSM PSW D0
0x78030 ZoneSelectBlock2 0xa Zx-CSM PSW D1 0x78230 ZoneSelectBlock2
(16x16Bits) (16x16Bits)
0xc Zx-CSM PSW D2
. .
. 0xe Zx-CSM PSW D3 .

0x781F0 ZoneSelectBlockn 0x783F0 ZoneSelectBlockn

(16x16Bits) (16x16Bits)

Figure 3-23. Location of Zone-Select Block Based on Link-Pointer

3.13.1.6.1 C Code Example to get Zone Select Block Addr for Zone1

unsigned long LinkPointer;

unsigned long *Zone1SelBlockPtr;
int Bitpos = 28;
int ZeroFound = 0;
// Read Z1-Linkpointer register of DCSM module.
LinkPointer = *(unsigned long *)0x5F000;
// Bits 31 30 and 29 as most-sigificant 0 are reserved LinkPointer options
LinkPointer = LinkPointer << 3;
while ((ZeroFound == 0) && (bitpos > -1))
{
if ((LinkPointer & 0x80000000) == 0)
{
ZeroFound = 1;
Zone1SelBlockPtr = (unsigned long *)(0x78000 + ((bitpos + 3)*16));
} else
{
bitpos--;
LinkPointer = LinkPointer << 1;
}
}
if (ZeroFound == 0)
{
//Default in case there is no zero found.
Zone1SelBlockPtr = (unsigned long *)0x78020;
}

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3.13.1.7 Flash and OTP Memory Erase/Program

On this device, OTP memory, as well as normal Flash, are secure resources. Each zone has a dedicated OTP
memory, whereas normal Flash sectors can be allocated to any zone based on the value programmed in the
GRABSECT location in OTP memory. Each zone has CSM passwords; read and write accesses are not allowed
to resources owned by Z1 from code running from memory allocated to Z2 and conversely. Before programming
any secure Flash sector, the user must either unlock the zone to which that particular sector belongs, using PMF
or execute the Flash programming code from secure memory that belongs to the same zone. The same is the
case for erasing any secure Flash sector. To program the security settings in OTP Flash, the user must unlock
the CSM of the respective zone. Unless the zone is unlocked, security settings in OTP Flash cannot be updated.
The OTP Flash content cannot be erased.
This device has only one Flash pump used for erase/program operation of normal Flash and OTP Flash. A
semaphore mechanism is provided to avoid the conflict between Zone1 and Zone2. A zone needs to grab this
semaphore to successfully complete the erase/program operation on the Flash sectors allocated to that zone. A
semaphore can be grabbed by a zone by writing the appropriate value in the SEM field of the FLSEM register.
For further details of this field, see the register description.

Note
If there is a loss of power or a reset of any nature during the Flash programming operation, there is
high probability of some (or possibly all) of the 128 bits in the corresponding 128-bit aligned address
getting corrupted. If this happens while programming the password locations in USER OTP, the
passwords can get corrupted.

3.13.1.8 Safe Copy Code

In some applications, the user may want to copy the code from secure Flash to secure RAM for better
performance. The user cannot do this for EXEONLY Flash sectors because EXEONLY secure memories cannot
be read from anywhere. TI provides specific “Safe Copy Code” library functions for each zone to enable the
user to copy content from EXEONLY secure Flash sectors to EXEONLY RAM blocks. These functions do the
copy-code operation in a highly secure environment and allow a copy to be performed only when the following
conditions are met:
• The secure RAM block and the secure Flash sector belong to the same zone.
• Both the secure RAM block and the secure Flash sector have EXEONLY protection enabled.
For further usage of these library functions, see the device-specific Boot ROM documentation.
3.13.1.9 SafeCRC
Since reads from EXEONLY memories are not allowed, the user cannot calculate the CRC for content in
EXEONLY memories using the VCU-II. But in some safety-critical applications, the user may have to calculate
the CRC on these memories as well. To enable this without compromising on security, TI provides specific
“SafeCRC” library functions for each zone. These functions do the CRC calculation in highly secure environment
and allow a CRC calculation to be performed only when the following conditions are met:
• The source address must be modulo the number of words (based on length_id) for which the CRC needs to
be calculated.
• The destination address must belong to the same zone as the source address.
For further usage of these library functions, see the device-specific Boot ROM documentation.

Note
The user must disable all the interrupts before calling the safe copy code and the safeCRC function. If
there is a vector fetch during copy code operation, the CPU gets reset immediately.

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Disclaimer: Code Security Module Disclaimer The Code Security Module (CSM) included on this device was
designed to password protect the data stored in the associated memory and is warranted by Texas Instruments
(TI), in accordance with its standard terms and conditions, to conform to TI's published specifications for the
warranty period applicable for this device. TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE
CSM CANNOT BE COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED
MEMORY CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT AS SET FORTH
ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS CONCERNING THE CSM OR OPERATION
OF THIS DEVICE, INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR
A PARTICULAR PURPOSE. IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL,
INDIRECT, INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY OUT
OF YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO LOSS
OF DATA, LOSS OF GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR OTHER ECONOMIC
LOSS.
3.13.2 CSM Impact on Other On-Chip Resources
On this device, M0/M1 and GSx memories are not secure. To avoid any potential hacking when the device is
in the default state (post reset), accesses (all types) to all memories (secure as well as non-secure, except
BOOT-ROM and OTP memory) are disabled until proper security initialization is done. This means that after
reset none of the memory resources except BOOT_ROM and OTP memory is accessible to the user.
The following steps are required after reset (any type of reset) to initialize the security on each CPU subsystem.
• Dummy Read to address location of SECDC (0x703F0, TI-reserved register) in TI OTP memory
• Dummy Read to address location of Z1_LINKPOINTER1 in Z1 OTP memory
• Dummy Read to address location of Z1_LINKPOINTER2 in Z1 OTP memory
• Dummy Read to address location of Z1_LINKPOINTER3 in Z1 OTP memory
• Dummy Read to address location of Z1_PSWDLOCK in Z1 OTP memory
• Dummy Read to address location of Z1_CRCLOCK in Z1 OTP memory
• Dummy Read to address location 0x78018 in Z1 OTP memory
• Dummy Read to address location of Z1_BOOTCTRL in Z1 OTP memory
• Read to memory map register of Z1_LINKPOINTER in DCSM module to calculate the address of zone select
block for Z1
• Dummy read to address location of Z1_EXEONLYRAM in Z1 OTP memory
• Dummy read to address location of Z1_EXEONLYSECT in Z1 OTP memory
• Dummy read to address location of Z1_GRABRAM in Z1 OTP memory
• Dummy read to address location of Z1_GRABSECT in Z1 OTP memory
• Dummy Read to address location of Z2_LINKPOINTER1 in Z2 OTP memory
• Dummy Read to address location of Z2_LINKPOINTER2 in Z2 OTP memory
• Dummy Read to address location of Z2_LINKPOINTER3 in Z2 OTP memory
• Dummy Read to address location of Z2_PSWDLOCK in Z2 OTP memory
• Dummy Read to address location of Z2_CRCLOCK in Z2 OTP memory
• Dummy Read to address location 0x78218 in Z2 OTP memory
• Dummy Read to address location of Z2_BOOTCTRL in Z2 OTP memory
• Read to memory map register of Z2_LINKPOINTER in DCSM module to calculate the address of zone select
block for Z2
• Dummy read to address location of Z2_EXEONLYRAM in Z2 OTP memory
• Dummy read to address location of Z2_EXEONLYSECT in Z2 OTP memory
• Dummy read to address location of Z2_GRABRAM in Z2 OTP memory
• Dummy read to address location of Z2_GRABSECT in Z2 OTP memory

Note
Security Initialization is done by BOOTROM code on all the resets that assert SYSRSn (as part of
device initialization). This is not part of the user application code.

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3.13.3 Incorporating Code Security in User Applications

Code security is typically not required in the development phase of a project. However, security is needed
once a robust code is developed for a zone. Before such a code is programmed in the Flash memory, a CSM
password must be chosen to secure the zone. Once a CSM password is in place for a zone, the zone is
secured (programming a password at the appropriate locations and either performing a device reset or setting
the FORCESEC bit (Zx_CR.15) is the action that secures the device). From that time on, access to debug the
contents of secure memory by any means (using JTAG, code running off external/on-chip memory, and so forth)
requires a valid password. A password is not needed to run the code out of secure memory (such as in a typical
end-user usage); however, access to secure memory contents for debug purposes, requires a password.
3.13.3.1 Environments That Require Security Unlocking
The following are the typical situations under which unsecuring can be required:
• Code development using debuggers (such as Code Composer Studio). This is the most common
environment during the design phase of a product.
• Flash programming using TI's Flash utilities such as Code Composer Studio On-Chip Flash Programmer
plug-in or the UniFlash tool. Flash programming is common during code development and testing. Once
the user supplies the necessary password, the Flash utilities disable the security logic before attempting
to program the Flash. The Flash utilities can disable the code security logic in new devices without any
authorization, since new devices come with an erased Flash. However, reprogramming devices that already
contain a custom password require the password to be supplied to the Flash utilities in order to unlock the
device to enable programming. In custom programming solutions that use the Flash API supplied by TI,
unlocking the CSM can be avoided by executing the Flash programming algorithms from secure memory.
• Custom environment defined by the application
In addition to the above, access to secure memory contents can be required in situations such as:
– Using the on-chip bootloader to load code or data into secure SARAM or to erase and program the Flash.
– Executing code from on-chip unsecure memory and requiring access to secure memory for the lookup
table. This is not a suggested operating condition as supplying the password from external code could
compromise code security.
The unsecuring sequence is identical in all the above situations. This sequence is referred to as the password
match flow (PMF) for simplicity. Figure 3-24 explains the sequence of operation that is required every time the
user attempts to unsecure a particular zone. A code example is listed for clarity.

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3.13.3.2 CSM Password Match Flow

Password match flow (PMF) is essentially a sequence of four dummy reads from password locations (PWL)
followed by four writes (32-bit writes) to CSMKEY(0/1/2/3) registers. Figure 3-24 shows how PMF helps to
initialize the security logic registers and disable security logic.

START

Zone secure after reset

or runtime

Dummy Read of CSM PWL

of the secure zone, which
needs to be unsecure

Are CSM YES

PWL = All
Fs?

NO

Write the CSM Password of

that zone into CSMKEYx
registers

NO Correct
Password?

YES

Zone Unsecure

Figure 3-24. CSM Password Match Flow (PMF)

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3.13.3.3 Unsecuring Considerations for Zones With and Without Code Security
Case 1 and Case 2 provide unsecuring considerations for zones with and without code security.
• Case 1: Zone With Code Security
A zone with code security must have a predetermined password stored in the password locations of that
zone. The following are steps to unsecure any secure zone:
1. Perform a dummy read of the password locations of that zone.
2. Write the password into the CSMKEY registers.
3. If the password is correct, the zone becomes unsecure; otherwise, the zone stays secure.
• Case 2: Zone Without Code Security
A zone without code security must have 0x FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF (128 bits of all
ones) stored in the password locations. The following are steps to use this zone:
1. At reset, the CSM locks memory regions protected by the CSM.
2. Perform a dummy read of the password locations.
3. Since the password is all ones, this unlocks the zone and all the secure memories dedicated to that zone
are fully accessible immediately after this operation is completed.

Note
Even if a zone is not protected with a password (all password locations all ones), the CSM locks at
reset. Thus, a dummy read operation must still be performed on these zones prior to reading, writing, or
programming secure memory if the code performing the access is executing from outside of the CSM
protected memory region. The Boot ROM code does this dummy read for convenience.

3.13.3.3.1 C Code Example to Unsecure C28x Zone1

volatile long int *CSM = (volatile long int *)0x5F010; //CSM register file
volatile long int *CSMPWL = (volatile long int *)0x78028; //CSM Password location (assuming default
Zone sel block)
volatile int tmp;
int I;
// Read the 128-bits of the CSM password locations (PWL)
//
for (I=0;I<4; I++) tmp = *CSMPWL++;
// If the password locations (CSMPWL) are all = ones (0xFFFF),
// then the zone will now be unsecure. If the password
// is not all ones (0xFFFF), then the code below is required
// to unsecure the CSM.
// Write the 128-bit password to the CSMKEY registers
// If this password matches that stored in the
// CSLPWL then the CSM will become unsecure. If it does not
// match, then the zone will remain secure.
// An example password of:
// 0x11112222333344445555666677778888 is used.
*CSM++ = 0x22221111; // Register Z1_CSMKEY0 at 0x5F010
*CSM++ = 0x44443333; // Register Z1_CSMKEY1 at 0x5F012
*CSM++ = 0x66665555; // Register Z1_CSMKEY2 at 0x5F014
*CSM++ = 0x88887777; // Register Z1_CSMKEY3 at 0x5F016

3.13.3.3.2 C Code Example to Resecure C28x Zone1

volatile int *Z1_CR = 0x5F019; //CSMSCR register

//Set FORCESEC bit
*Z1_CR = 0x8000;

3.13.3.4 Environments That Require ECSL Unlocking

The following are the typical situations under which unsecuring can be required:
• The user develops some main IP, and then outsources peripheral functions to a subcontractor who must be
able to run the user code during debug and may halt while main IP code is running. If ECSL is not unlocked,

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then Code Composer Studio IDE connections get disconnected, which can be inconvenient for the user. Note
that unlocking ECSL doesn’t enable access to secure code but only avoids disconnection of CCS (JTAG).
3.13.3.5 ECSL Password Match Flow
A password match flow (PMF) is essentially a sequence of eight dummy reads from password locations (PWL)
followed by two writes to KEY registers. Figure 3-25 shows how the PMF helps to initialize the security logic
registers and disable security logic.

START

Zone’s ECSL LOCK after

reset or runtime

Dummy read of ECSL PWL

of the secure zone, which
ECSL needs to be unlocked

Are ECSL YES

PWL = All
Fs?

NO

Write the ECSL Password of

that zone into ECSLKEYx
registers

NO Correct
Password?

YES

Zone ECSL Unlock

Figure 3-25. ECSL Password Match Flow (PMF)

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3.13.3.6 ECSL Disable Considerations for any Zone

A zone with ECSL enabled must have a predetermined ECSL password stored in the ECSL password locations
in Flash (same as lower 64 bits of CSM passwords). The following are steps to disable the ECSL for any
particular zone:
• Perform a dummy read of CAM password locations of that Zone
• Write the password into the CSMKEYx registers, corresponding to that Zone.
• If the password is correct, the ECSL gets disabled; otherwise, the ECSL stays enabled.
3.13.3.6.1 C Code Example to Disable ECSL for C28x-Zone1

volatile long int *ECSL = (volatile int *)0x5F010; //ECSL register file
volatile long int *ECSLPWL = (volatile int *)0x78028; //ECSL Password location (assuming default
Zone sel block)
volatile int tmp;
int I;
// Read the 64-bits of the password locations (PWL)
.
for (I=0;I<2; I++) tmp = *ECSLPWL++;
// If the ECSL password locations (ECSLPWL) are all = ones (0xFFFF),
// then the ECSL will now be disable. If the password
// is not all ones (0xFFFF), then the code below is required
// to disable the ECSL.
// Write the 64-bit password to the CSMKEYx registers
// If this password matches that stored in the
// CSMPWL then ECSL will get disable. If it does not
// match, then the zone will remain secure.
// An example password of:
// 0x1111222233334444 is used.
*ECSL++ = 0x22221111; // Register Z1_CSMKEY0 at 0x5F010
*ECSL++ = 0x44443333; // Register Z1_CSMKEY1 at 0x5F012

3.13.3.7 Device Unique ID

The CPU1 OTP memory contains a 256-bit value that is made up of both pseudo-random and sequential parts.
This value may be used as a seed for code encryption. The starting address of the value is 0x703C0. The first
192 bits are pseudo-random, the next 32 bits are sequential, and the last 32 bits are a checksum value. The
degree of randomness is not specified.

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3.14 JTAG
Gel files perform certain initialization tasks. This helps the users in a debug environment. However, when
executed standalone (without the emulator connected) the application may not work as expected, since there is
no gel file to perform those initializations. For example, gel file disables watchdog. If user code does not service
the watchdog in the application (or fails to disable it), there isdifference in how the application behaves with the
debugger and without.
Common tasks performed by the gel files (but not boot-ROM)
On Reset:
• Disable Flash ECC on some devices.
– Disabling ECC only when using Flash API functions, see the Flash API User Guide for details. Otherwise,
TI suggests to always program ECC and enable ECC-check.
• Disable Watchdog
• Enable CLA clock
• Select real-time mode or C28x mode
On Restart:
• Select real-time mode or C28x mode
• Clear IER and IFR
On Target Connect:
• Select real-time mode or C28x mode

3.15 System Control Register Configuration Restrictions

Memory-mapped registers in the System Control operate on INTOSC1 clock domain; hence, any CPU writes
to these registers requires a delay between subsequent writes otherwise a second write can be lost. The
application needs to take this into consideration and add a delay in terms of the number of NOP instructions
after every write to these registers that are mentioned in Table 3-19. The formula to compute delay between
subsequent writes:
Delay (in SYSCLK cycles) = 3 × (FSYSCLK ÷ FINTOSC1) + 9
For Example - For SYSCLK = 100MHz
Delay (in SYSCLK cycles) = 3 × (100MHz ÷ 10MHz) + 9 = 39 SYSCLK cycles

Table 3-19. System Control Registers Impacted

Registers requiring delay after every write
PERCLKDIVSEL
SYSCLKDIVSEL
SYSPLLCTL1
SYSPLLMULT
WDCR
XCLKOUTDIVSEL
CLKSRCCTL1
CLKSRCCTL2
CLKSRCCTL3
CPU1TMR2CTL (TMR2CLKCTL)

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3.16 Software
3.16.1 SYSCTL Examples
NOTE: These examples are located in the C2000Ware installation at the following location:
C2000Ware_VERSION#/driverlib/DEVICE_GPN/examples/CORE_IF_MULTICORE/sysctl
Cloud access to these examples is available at the following link: dev.ti.com C2000Ware Examples.
3.16.1.1 Missing clock detection (MCD)
FILE: sysctl_ex1_missing_clock_detection.c
This example demonstrates the missing clock detection functionality and the way to handle it. Once the MCD is
simulated by disconnecting the OSCCLK to the MCD module an NMI would be generated. This NMI determines
that an MCD was generated due to a clock failure which is handled in the ISR.
Before an MCD the clock frequency would be as per device initialization (200Mhz). Post MCD the frequency
would move to 10Mhz or INTOSC1.
The example also shows how we can lock the PLL after missing clock, detection, by first explicitly switching the
clock source to INTOSC1, resetting the missing clock detect circuit and then re-locking the PLL. Post a re-lock
the clock frequency would be 200Mhz but using the INTOSC1 as clock source.
External Connections
• None.
Watch Variables
• fail - Indicates that a missing clock was either not detected or was not handled correctly.
• mcd_clkfail_isr - Indicates that the missing clock failure caused an NMI to be triggered and called an the ISR
to handle it.
• mcd_detect - Indicates that a missing clock was detected.
• result - Status of a successful handling of missing clock detection
3.16.1.2 XCLKOUT (External Clock Output) Configuration
FILE: sysctl_ex2_xclkout_config.c
This example demonstrates how to configure the XCLKOUT pin for observing internal clocks through an external
pin, for debugging and testing purposes.
In this example, we are using INTOSC1 as the XCLKOUT clock source and configuring the divider as 8.
Expected frequency of XCLKOUT = (INTOSC1 freq)/8 = 10/8 = 1.25MHz
View the XCLKOUT on GPIO73 using an oscilloscope.
3.16.2 TIMER Examples
NOTE: These examples are located in the C2000Ware installation at the following location:
C2000Ware_VERSION#/driverlib/DEVICE_GPN/examples/CORE_IF_MULTICORE/timer
Cloud access to these examples is available at the following link: dev.ti.com C2000Ware Examples.
3.16.2.1 CPU Timers
FILE: timer_ex1_cputimers.c
This example configures CPU Timer0, 1, and 2 and increments a counter each time the timer asserts an
interrupt. In order to migrate the project within syscfg to any device, click the swtich button under the device view
and select your corresponding device to migrate, saving the project will auto-migrate your project settings.
External Connections
• None
Watch Variables

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• cpuTimer0IntCount
• cpuTimer1IntCount
• cpuTimer2IntCount
3.16.2.2 CPU Timers
FILE: timer_ex1_cputimers_sysconfig.c
This example configures CPU Timer0, 1, and 2 and increments a counter each time the timer asserts an
interrupt.
This example project has support for migration across our C2000 device families. If you are wanting to build this
project from launchpad or controlCARD, please specify in the .syscfg file the board you're using. At any time you
can select another device to migrate this example. External Connections
• None
Watch Variables
• cpuTimer0IntCount
• cpuTimer1IntCount
• cpuTimer2IntCount
3.16.3 MEMCFG Examples
NOTE: These examples are located in the C2000Ware installation at the following location:
C2000Ware_VERSION#/driverlib/DEVICE_GPN/examples/CORE_IF_MULTICORE/memcfg
Cloud access to these examples is available at the following link: dev.ti.com C2000Ware Examples.
3.16.4 INTERRUPT Examples
NOTE: These examples are located in the C2000Ware installation at the following location:
C2000Ware_VERSION#/driverlib/DEVICE_GPN/examples/CORE_IF_MULTICORE/interrupt
Cloud access to these examples is available at the following link: dev.ti.com C2000Ware Examples.
3.16.4.1 External Interrupts (ExternalInterrupt)
FILE: interrupt_ex1_external.c
This program sets up GPIO0 as XINT1 and GPIO1 as XINT2. Two other GPIO signals are used to trigger the
interrupt (GPIO10 triggers XINT1 and GPIO11 triggers XINT2). The user is required to externally connect these
signals for the program to work properly.
XINT1 input is synced to SYSCLKOUT.
XINT2 has a long qualification - 6 samples at 510*SYSCLKOUT each.
GPIO16 will go high outside of the interrupts and low within the interrupts. This signal can be monitored on a
scope.
Each interrupt is fired in sequence - XINT1 first and then XINT2
External Connections
• Connect GPIO10 to GPIO0. GPIO0 will be assigned to XINT1
• Connect GPIO11 to GPIO1. GPIO1 will be assigned to XINT2
Monitor GPIO16 with an oscilloscope. GPIO16 will be high outside of the ISRs and low within each ISR.
Watch Variables
• xint1Count for the number of times through XINT1 interrupt
• xint2Count for the number of times through XINT2 interrupt
• loopCount for the number of times through the idle loop

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3.16.4.2 Multiple interrupt handling of I2C, SCI & SPI Digital Loopback
FILE: interrupt_ex2_with_i2c_sci_spi_loopback.c
This program is used to demonstrate how to handle multiple interrupts when using multiple communication
peripherals like I2C, SCI & SPI Digital Loopback all in a single example. The data transfers would be done with
FIFO Interrupts.
It uses the internal loopback test mode of these modules. Both the TX and RX FIFOs and their interrupts are
used. Other than boot mode pin configuration, no other hardware configuration is required.
A stream of data is sent and then compared to the received stream. The sent data looks like this for I2C and
SCI:
0000 0001
0001 0002
0002 0003
....
00FE 00FF
00FF 0000
etc..
The sent data looks like this for SPI:
0000 0001
0001 0002
0002 0003
....
FFFE FFFF
FFFF 0000
etc..
This pattern is repeated forever.
External Connections
• None
Watch Variables
• sDatai2cA - Data to send through I2C
• rDatai2cA - Received I2C data
• rDataPoint - Used to keep track of the last position in the receive I2C stream for error checking
• sDataspiA - Data to send through SPI
• rDataspiA - Received SPI data
• rDataPointspiA - Used to keep track of the last position in the receive SPI stream for error checking
• sDatasciA - SCI Data being sent
• rDatasciA - SCI Data received
• rDataPointA - Keep track of where we are in the SCI data stream. This is used to check the incoming data
3.16.4.3 CPU Timer Interrupt Software Prioritization
FILE: interrupt_ex3_sw_prioritization.c
This examples demonstrates the software prioritization of interrupts through CPU Timer Interrupts. Software
prioritization of interrupts is achieved by enabling interrupt nesting.
In this device, hardware priorities for CPU Timer 0, 1 and 2 are set as timer 0 being highest priority and timer 2
being lowest priority. This example configures CPU Timer0, 1, and 2 priority in software with timer 2 priority being
highest and timer 0 being lowest in software and prints a trace for the order of execution.
For most applications, the hardware prioritizing of the interrupts is sufficient. For applications that need custom
prioritizing, this example illustrates how this can be done through software.User specific priorities can be
configured in sw_prioritized_isr_level.h header file.

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To enable interrupt nesting, following sequence needs to followed in ISRs. Step 1: Set the global priority: Modify
the IER register to allow CPU interrupts with a higher user priority to be serviced. Note: at this time IER has
already been saved on the stack. Step 2: Set the group priority: (optional) Modify the appropriate PIEIERx
register to allow group interrupts with a higher user set priority to be serviced. Do NOT clear PIEIER register bits
from another group other than that being serviced by this ISR. Doing so can cause erroneous interrupts to occur.
Step 3: Enable interrupts: There are three steps to do this: a. Clear the PIEACK bits b. Wait at least one cycle c.
Clear the INTM bit. Step 4: Run the main part of the ISR Step 5: Set INTM to disable interrupts. Step 6: Restore
PIEIERx (optional depending on step 2) Step 7: Return from ISR
Refer to below link on more details on Interrupt nesting in C28x devices:
<C2000Ware>\docs\c28x_interrupt_nesting\html\index.html
External Connections
• None
Watch Variables
• traceISR - shows the order in which ISRs are executed.
3.16.4.4 EPWM Real-Time Interrupt
FILE: interrupt_ex4_epwm_realtime_interrupt.c
This example configures the ePWM1 Timer and increments a counter each time the ISR is executed. ePWM
interrupt can be configured as time critical to demonstrate real-time mode functionality and real-time interrupt
capability.
The example uses 2 LEDs - LED1 is toggled in the main loop and LED2 is toggled in the EPWM Timer
Interrupt. FREE_SOFT bits and DBGIER.INT3 bit must be set to enable ePWM1 interrupt to be time critical and
operational in real time mode after halt command
How to run the example?
• Add the watch variables as mentioned below and enable Continuous Refresh.
• Enable real-time mode (Run->Advanced->Enable Silicon Real-time Mode)
• Initially, the DBGIER register is set to 0 and the EPWM emulation mode is set to
EPWM_EMULATION_STOP_AFTER_NEXT_TB (FREE_SOFT = 0)
• When the application is running, you will find both LEDs toggling and the watch variables
EPwm1TimerIntCount, EPwm1Regs.TBCTR getting updated.
• When the application is halted, both LEDs stop toggling and the watch variables remain constant. EPWM
counter is stopped on debugger halt.
• To enable EPWM counter run during debugger halt, set emulation mode as
EPWM_EMULATION_FREE_RUN (FREE_SOFT = 2). You will find EPwm1Regs.TBCTR is running, but
EPwm1TimerIntCount remains constant. This means, the EPWM counter is running, but the ISRs are not
getting serviced.
• To enable real-time interrupts, set DBGIER.INT3 = 1 (EPWM1 interrupt is part of PIE Group 3). You will
find that the EPwm1TimerIntCount is incrementing and the LED starts toggling. The EPWM ISR is getting
serviced even during a debugger halt.
For more details, watch this video : C2000 Real-Time Features
External Connections
• None
Watch Variables
• EPwm1TimerIntCount - EPWM1 ISR counter
• EPwm1Regs.TBCTR.TBCTR - EPWM1 Time Base counter
• EPwm1Regs.TBCTL.FREE_SOFT - Set this to 2 to enable free run
• DBGIER.INT3 - Set to 1 to enable real time interrupt

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3.16.5 LPM Examples

NOTE: These examples are located in the C2000Ware installation at the following location:
C2000Ware_VERSION#/driverlib/DEVICE_GPN/examples/CORE_IF_MULTICORE/lpm
Cloud access to these examples is available at the following link: dev.ti.com C2000Ware Examples.
3.16.6 WATCHDOG Examples
NOTE: These examples are located in the C2000Ware installation at the following location:
C2000Ware_VERSION#/driverlib/DEVICE_GPN/examples/CORE_IF_MULTICORE/watchdog
Cloud access to these examples is available at the following link: dev.ti.com C2000Ware Examples.
3.16.6.1 Watchdog
FILE: watchdog_ex1_service.c
This example shows how to service the watchdog or generate a wakeup interrupt using the watchdog. By default
the example will generate a Wake interrupt. To service the watchdog and not generate the interrupt, uncomment
the SysCtl_serviceWatchdog() line in the main for loop.
External Connections
• None.
Watch Variables
• wakeCount - The number of times entered into the watchdog ISR
• loopCount - The number of loops performed while not in ISR

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3.17 System Control Registers

3.17.1 System Control Base Addresses
Table 3-20. System Control Base Address Table
Device Registers Register Name Start Address End Address
CpuTimer0Regs CPUTIMER_REGS 0x0000_0C00 0x0000_0C07
CpuTimer1Regs CPUTIMER_REGS 0x0000_0C08 0x0000_0C0F
CpuTimer2Regs CPUTIMER_REGS 0x0000_0C10 0x0000_0C17
PieCtrlRegs PIE_CTRL_REGS 0x0000_0CE0 0x0000_0CFF
WdRegs WD_REGS 0x0000_7000 0x0000_703F
NmiIntruptRegs NMI_INTRUPT_REGS 0x0000_7060 0x0000_706F
XintRegs XINT_REGS 0x0000_7070 0x0000_707F
SyncSocRegs SYNC_SOC_REGS 0x0000_7940 0x0000_794F
DmaClaSrcSelRegs DMA_CLA_SRC_SEL_REGS 0x0000_7980 0x0000_79BF
FlashPumpSemaphoreRegs FLASH_PUMP_SEMAPHORE_REGS 0x0005_0024 0x0005_0025
DevCfgRegs(1) DEV_CFG_REGS 0x0005_D000 0x0005_D17F
ClkCfgRegs CLK_CFG_REGS 0x0005_D200 0x0005_D2FF
CpuSysRegs CPU_SYS_REGS 0x0005_D300 0x0005_D3FF
RomPrefetchRegs(1) ROM_PREFETCH_REGS 0x0005_E608 0x0005_E609
DcsmZ1Regs DCSM_Z1_REGS 0x0005_F000 0x0005_F02F
DcsmZ2Regs DCSM_Z2_REGS 0x0005_F040 0x0005_F05F
DcsmCommonRegs DCSM_COMMON_REGS 0x0005_F070 0x0005_F07F
MemCfgRegs MEM_CFG_REGS 0x0005_F400 0x0005_F47F
AccessProtectionRegs ACCESS_PROTECTION_REGS 0x0005_F4C0 0x0005_F4FF
MemoryErrorRegs MEMORY_ERROR_REGS 0x0005_F500 0x0005_F53F
RomWaitStateRegs(1) ROM_WAIT_STATE_REGS 0x0005_F540 0x0005_F541
Flash0CtrlRegs FLASH_CTRL_REGS 0x0005_F800 0x0005_FAFF
Flash0EccRegs FLASH_ECC_REGS 0x0005_FB00 0x0005_FB3F
CpuIdRegs CPU_ID_REGS 0x0007_026D 0x0007_026E
UidRegs UID_REGS 0x0007_03C0 0x0007_03CF
DcsmZ1OTPRegs DCSM_Z1_OTP 0x0007_8000 0x0007_81FF
DcsmZ2OTPRegs DCSM_Z2_OTP 0x0007_8200 0x0007_83FF

(1) Only available on CPU1.

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3.17.2 CPUTIMER_REGS Registers

Table 3-21 lists the memory-mapped registers for the CPUTIMER_REGS registers. All register offset addresses
not listed in Table 3-21 should be considered as reserved locations and the register contents should not be
modified.
Table 3-21. CPUTIMER_REGS Registers
Offset Acronym Register Name Write Protection Section
0h TIM CPU-Timer, Counter Register Go
2h PRD CPU-Timer, Period Register Go
4h TCR CPU-Timer, Control Register Go
6h TPR CPU-Timer, Prescale Register Go
7h TPRH CPU-Timer, Prescale Register High Go

Complex bit access types are encoded to fit into small table cells. Table 3-22 shows the codes that are used for
access types in this section.
Table 3-22. CPUTIMER_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
Write Type
W W Write
W1C W Write
1C 1 to clear
Reset or Default Value
-n Value after reset or the default
value

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3.17.2.1 TIM Register (Offset = 0h) [Reset = 0000FFFFh]

TIM is shown in Figure 3-26 and described in Table 3-23.
Return to the Summary Table.
CPU-Timer, Counter Register
Figure 3-26. TIM Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSW LSW
R/W-0h R/W-FFFFh

Table 3-23. TIM Register Field Descriptions

Bit Field Type Reset Description
31-16 MSW R/W 0h CPU-Timer Counter Registers
The TIMH register holds the high 16 bits of the current 32-bit
count of the timer. The TIMH:TIM decrements by one every
(TDDRH:TDDR+1) clock cycles, where TDDRH:TDDR is the timer
prescale dividedown value. When the TIMH:TIM decrements to zero,
the TIMH:TIM register is reloaded with the period value contained
in the PRDH:PRD registers. The timer interrupt (TINT) signal is
generated.
Reset type: SYSRSn
15-0 LSW R/W FFFFh CPU-Timer Counter Registers
The TIM register holds the low 16 bits of the current 32-bit
count of the timer. The TIMH:TIM decrements by one every
(TDDRH:TDDR+1) clock cycles, where TDDRH:TDDR is the timer
prescale dividedown value. When the TIMH:TIM decrements to zero,
the TIMH:TIM register is reloaded with the period value contained
in the PRDH:PRD registers. The timer interrupt (TINT) signal is
generated.
Reset type: SYSRSn

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3.17.2.2 PRD Register (Offset = 2h) [Reset = 0000FFFFh]

PRD is shown in Figure 3-27 and described in Table 3-24.
Return to the Summary Table.
CPU-Timer, Period Register
Figure 3-27. PRD Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSW LSW
R/W-0h R/W-FFFFh

Table 3-24. PRD Register Field Descriptions

Bit Field Type Reset Description
31-16 MSW R/W 0h CPU-Timer Period Registers
The PRDH register holds the high 16 bits of the 32-bit period. When
the TIMH:TIM decrements to zero, the TIMH:TIM register is reloaded
with the period value contained in the PRDH:PRD registers, at the
start of the next timer input clock cycle (the output of the prescaler).
The PRDH:PRD contents are also loaded into the TIMH:TIM when
you set the timer reload bit (TRB) in the Timer Control Register
(TCR).
Reset type: SYSRSn
15-0 LSW R/W FFFFh CPU-Timer Period Registers
The PRD register holds the low 16 bits of the 32-bit period. When
the TIMH:TIM decrements to zero, the TIMH:TIM register is reloaded
with the period value contained in the PRDH:PRD registers, at the
start of the next timer input clock cycle (the output of the prescaler).
The PRDH:PRD contents are also loaded into the TIMH:TIM when
you set the timer reload bit (TRB) in the Timer Control Register
(TCR).
Reset type: SYSRSn

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3.17.2.3 TCR Register (Offset = 4h) [Reset = 0001h]

TCR is shown in Figure 3-28 and described in Table 3-25.
Return to the Summary Table.
CPU-Timer, Control Register
Figure 3-28. TCR Register
15 14 13 12 11 10 9 8
TIF TIE RESERVED FREE SOFT RESERVED
R/W1C-0h R/W-0h R-0h R/W-0h R/W-0h R-0h

7 6 5 4 3 2 1 0
RESERVED TRB TSS RESERVED
R-0h R/W-0h R/W-0h R-1h

Table 3-25. TCR Register Field Descriptions

Bit Field Type Reset Description
15 TIF R/W1C 0h CPU-Timer Overflow Flag.
TIF indicates whether a timer overflow has happened since TIF was
last cleared. TIF is not cleared automatically and does not need to be
cleared to enable the next timer interrupt.
Reset type: SYSRSn
0h (R/W) = The CPU-Timer has not decremented to zero.
Writes of 0 are ignored.
1h (R/W) = This flag gets set when the CPU-timer decrements to
zero.
Writing a 1 to this bit clears the flag.
14 TIE R/W 0h CPU-Timer Interrupt Enable.
Reset type: SYSRSn
0h (R/W) = The CPU-Timer interrupt is disabled.
1h (R/W) = The CPU-Timer interrupt is enabled. If the timer
decrements to zero, and TIE is set, the timer asserts its interrupt
request.
13-12 RESERVED R 0h Reserved
11 FREE R/W 0h If the FREE bit is set to 1, then, upon a software breakpoint, the
timer continues to run. If FREE is 0, then the SOFT bit controls the
emulation behavior.
Reset type: SYSRSn
0h (R/W) = Stop after the next decrement of the TIMH:TIM (hard
stop)
(SOFT bit controls the emulation behavior)
1h (R/W) = Free Run
(SOFT bit is don't care, counter is free running)
10 SOFT R/W 0h If the FREE bit is set to 1, then, upon a software breakpoint, the
timer continues to run (that is, free runs). In this case, SOFT is a
don't care. But if FREE is 0, then SOFT takes effect.
Reset type: SYSRSn
0h (R/W) = Stop after the next decrement of the TIMH:TIM (hard
stop).
(ONLY if FREE=0, if FREE=1 this bit is don't care)
1h (R/W) = Stop after the TIMH:TIM decrements to 0 (soft stop)
In the SOFT STOP mode, the timer generates an interrupt before
shutting down (since reaching 0 is the interrupt causing condition).
(ONLY if FREE=0, if FREE=1 this bit is don't care)
9-6 RESERVED R 0h Reserved

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Table 3-25. TCR Register Field Descriptions (continued)

Bit Field Type Reset Description
5 TRB R/W 0h Timer reload
Reset type: SYSRSn
0h (R/W) = The TRB bit is always read as zero. Writes of 0 are
ignored.
1h (R/W) = When you write a 1 to TRB, the TIMH:TIM is loaded with
the value in the PRDH:PRD,
and the prescaler counter (PSCH:PSC) is loaded with the value in
the timer dividedown
register (TDDRH:TDDR).
4 TSS R/W 0h CPU-Timer stop status bit.
TSS is a 1-bit flag that stops or starts the CPU-timer.
Reset type: SYSRSn
0h (R/W) = Reads of 0 indicate the CPU-timer is running.
To start or restart the CPU-timer, set TSS to 0. At reset, TSS is
cleared to 0 and the
CPU-timer immediately starts.
1h (R/W) = Reads of 1 indicate that the CPU-timer is stopped.
To stop the CPU-timer, set TSS to 1.
3-0 RESERVED R 1h Reserved

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3.17.2.4 TPR Register (Offset = 6h) [Reset = 0000h]

TPR is shown in Figure 3-29 and described in Table 3-26.
Return to the Summary Table.
CPU-Timer, Prescale Register
Figure 3-29. TPR Register
15 14 13 12 11 10 9 8
PSC
R-0h

7 6 5 4 3 2 1 0
TDDR
R/W-0h

Table 3-26. TPR Register Field Descriptions

Bit Field Type Reset Description
15-8 PSC R 0h CPU-Timer Prescale Counter.
These bits hold the current prescale count for the timer. For every
timer clock source cycle that the PSCH:PSC value is greater than
0, the PSCH:PSC decrements by one. One timer clock (output
of the timer prescaler) cycle after the PSCH:PSC reaches 0, the
PSCH:PSC is loaded with the contents of the TDDRH:TDDR, and
the timer counter register (TIMH:TIM) decrements by one. The
PSCH:PSC is also reloaded whenever the timer reload bit (TRB)
is set by software. The PSCH:PSC can be checked by reading the
register, but it cannot be set directly. It must get its value from the
timer divide-down register
(TDDRH:TDDR). At reset, the PSCH:PSC is set to 0.
Reset type: SYSRSn
7-0 TDDR R/W 0h CPU-Timer Divide-Down.
Every (TDDRH:TDDR + 1) timer clock source cycles, the timer
counter register (TIMH:TIM) decrements by one. At reset, the
TDDRH:TDDR bits are cleared to 0. To increase the overall timer
count by an integer factor, write this factor minus one to the
TDDRH:TDDR bits. When the prescaler counter (PSCH:PSC)
value is 0, one timer clock source cycle later, the contents
of the TDDRH:TDDR reload the PSCH:PSC, and the TIMH:TIM
decrements by one. TDDRH:TDDR also reloads the PSCH:PSC
whenever the timer reload bit (TRB) is set by software.
Reset type: SYSRSn

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3.17.2.5 TPRH Register (Offset = 7h) [Reset = 0000h]

TPRH is shown in Figure 3-30 and described in Table 3-27.
Return to the Summary Table.
CPU-Timer, Prescale Register High
Figure 3-30. TPRH Register
15 14 13 12 11 10 9 8
PSCH
R-0h

7 6 5 4 3 2 1 0
TDDRH
R/W-0h

Table 3-27. TPRH Register Field Descriptions

Bit Field Type Reset Description
15-8 PSCH R 0h See description of TIMERxTPR.
Reset type: SYSRSn
7-0 TDDRH R/W 0h See description of TIMERxTPR.
Reset type: SYSRSn

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3.17.3 PIE_CTRL_REGS Registers

Table 3-28 lists the memory-mapped registers for the PIE_CTRL_REGS registers. All register offset addresses
not listed in Table 3-28 should be considered as reserved locations and the register contents should not be
modified.
Table 3-28. PIE_CTRL_REGS Registers
Offset Acronym Register Name Write Protection Section
0h PIECTRL ePIE Control Register Go
1h PIEACK Interrupt Acknowledge Register Go
2h PIEIER1 Interrupt Group 1 Enable Register Go
3h PIEIFR1 Interrupt Group 1 Flag Register Go
4h PIEIER2 Interrupt Group 2 Enable Register Go
5h PIEIFR2 Interrupt Group 2 Flag Register Go
6h PIEIER3 Interrupt Group 3 Enable Register Go
7h PIEIFR3 Interrupt Group 3 Flag Register Go
8h PIEIER4 Interrupt Group 4 Enable Register Go
9h PIEIFR4 Interrupt Group 4 Flag Register Go
Ah PIEIER5 Interrupt Group 5 Enable Register Go
Bh PIEIFR5 Interrupt Group 5 Flag Register Go
Ch PIEIER6 Interrupt Group 6 Enable Register Go
Dh PIEIFR6 Interrupt Group 6 Flag Register Go
Eh PIEIER7 Interrupt Group 7 Enable Register Go
Fh PIEIFR7 Interrupt Group 7 Flag Register Go
10h PIEIER8 Interrupt Group 8 Enable Register Go
11h PIEIFR8 Interrupt Group 8 Flag Register Go
12h PIEIER9 Interrupt Group 9 Enable Register Go
13h PIEIFR9 Interrupt Group 9 Flag Register Go
14h PIEIER10 Interrupt Group 10 Enable Register Go
15h PIEIFR10 Interrupt Group 10 Flag Register Go
16h PIEIER11 Interrupt Group 11 Enable Register Go
17h PIEIFR11 Interrupt Group 11 Flag Register Go
18h PIEIER12 Interrupt Group 12 Enable Register Go
19h PIEIFR12 Interrupt Group 12 Flag Register Go

Complex bit access types are encoded to fit into small table cells. Table 3-29 shows the codes that are used for
access types in this section.
Table 3-29. PIE_CTRL_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1S W Write
1S 1 to set
Reset or Default Value

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Table 3-29. PIE_CTRL_REGS Access Type Codes

(continued)
Access Type Code Description
-n Value after reset or the default
value

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3.17.3.1 PIECTRL Register (Offset = 0h) [Reset = 0000h]

PIECTRL is shown in Figure 3-31 and described in Table 3-30.
Return to the Summary Table.
ePIE Control Register
Figure 3-31. PIECTRL Register
15 14 13 12 11 10 9 8
PIEVECT
R-0h

7 6 5 4 3 2 1 0
PIEVECT ENPIE
R-0h R/W-0h

Table 3-30. PIECTRL Register Field Descriptions

Bit Field Type Reset Description
15-1 PIEVECT R 0h These bits indicate the vector address of the vector fetched from the
ePIE vector table. The least significant bit of the address is ignored
and only bits 1 to 15 of the address are shown. The vector value
can be read by the user to determine which interrupt generated the
vector fetch.
Note: When a NMI is serviced, the PIEVECT bit-field does not reflect
the vector as it does for other interrupts.
Reset type: SYSRSn
0 ENPIE R/W 0h Enable vector fetching from ePIE block. This bit must be set to 1
for peripheral interrupts to work. All ePIE registers (PIEACK, PIEIFR,
PIEIER) can be accessed even when the ePIE block is disabled.
Reset type: SYSRSn

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3.17.3.2 PIEACK Register (Offset = 1h) [Reset = 0000h]

PIEACK is shown in Figure 3-32 and described in Table 3-31.
Return to the Summary Table.
Acknowledge Register
When an interrupt propagates from the ePIE to a CPU interrupt line, the interrupt group's PIEACK bit is set. This
prevents other interrupts in that group from propagating to the CPU while the first interrupt is handled. Writing a
1 to a PIEACK bit clears it and allows another interrupt from the corresponding group to propagate. ISRs for PIE
interrupts should clear the group's PIEACK bit before returning from the interrupt.
Writes of 0 are ignored.
Figure 3-32. PIEACK Register
15 14 13 12 11 10 9 8
RESERVED ACK12 ACK11 ACK10 ACK9
R-0-0h R/W1S-0h R/W1S-0h R/W1S-0h R/W1S-0h

7 6 5 4 3 2 1 0
ACK8 ACK7 ACK6 ACK5 ACK4 ACK3 ACK2 ACK1
R/W1S-0h R/W1S-0h R/W1S-0h R/W1S-0h R/W1S-0h R/W1S-0h R/W1S-0h R/W1S-0h

Table 3-31. PIEACK Register Field Descriptions

Bit Field Type Reset Description
15-12 RESERVED R-0 0h Reserved
11 ACK12 R/W1S 0h Acknowledge PIE Interrupt Group 12
Reset type: SYSRSn
10 ACK11 R/W1S 0h Acknowledge PIE Interrupt Group 11
Reset type: SYSRSn
9 ACK10 R/W1S 0h Acknowledge PIE Interrupt Group 10
Reset type: SYSRSn
8 ACK9 R/W1S 0h Acknowledge PIE Interrupt Group 9
Reset type: SYSRSn
7 ACK8 R/W1S 0h Acknowledge PIE Interrupt Group 8
Reset type: SYSRSn
6 ACK7 R/W1S 0h Acknowledge PIE Interrupt Group 7
Reset type: SYSRSn
5 ACK6 R/W1S 0h Acknowledge PIE Interrupt Group 6
Reset type: SYSRSn
4 ACK5 R/W1S 0h Acknowledge PIE Interrupt Group 5
Reset type: SYSRSn
3 ACK4 R/W1S 0h Acknowledge PIE Interrupt Group 4
Reset type: SYSRSn
2 ACK3 R/W1S 0h Acknowledge PIE Interrupt Group 3
Reset type: SYSRSn
1 ACK2 R/W1S 0h Acknowledge PIE Interrupt Group 2
Reset type: SYSRSn
0 ACK1 R/W1S 0h Acknowledge PIE Interrupt Group 1
Reset type: SYSRSn

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3.17.3.3 PIEIER1 Register (Offset = 2h) [Reset = 0000h]

PIEIER1 is shown in Figure 3-33 and described in Table 3-32.
Return to the Summary Table.
Interrupt Group 1 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the
CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal
can still set the PIEIFR bit for the disabled interrupt.
Figure 3-33. PIEIER1 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-32. PIEIER1 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 1.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 1.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 1.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 1.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 1.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 1.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 1.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 1.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 1.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 1.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 1.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 1.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 1.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 1.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 1.2
Reset type: SYSRSn

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Table 3-32. PIEIER1 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INTx1 R/W 0h Enable for Interrupt 1.1
Reset type: SYSRSn

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3.17.3.4 PIEIFR1 Register (Offset = 3h) [Reset = 0000h]

PIEIFR1 is shown in Figure 3-34 and described in Table 3-33.
Return to the Summary Table.
Interrupt Group 1 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like
the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution
in the application code. Reading the PIE IFR registers is safe.
Figure 3-34. PIEIFR1 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-33. PIEIFR1 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 1.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 1.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 1.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 1.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 1.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 1.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 1.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 1.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 1.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 1.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 1.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 1.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 1.4
Reset type: SYSRSn

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Table 3-33. PIEIFR1 Register Field Descriptions (continued)

Bit Field Type Reset Description
2 INTx3 R/W 0h Flag for Interrupt 1.3
Reset type: SYSRSn
1 INTx2 R/W 0h Flag for Interrupt 1.2
Reset type: SYSRSn
0 INTx1 R/W 0h Flag for Interrupt 1.1
Reset type: SYSRSn

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3.17.3.5 PIEIER2 Register (Offset = 4h) [Reset = 0000h]

PIEIER2 is shown in Figure 3-35 and described in Table 3-34.
Return to the Summary Table.
Interrupt Group 2 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the
CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal
can still set the PIEIFR bit for the disabled interrupt.
Figure 3-35. PIEIER2 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-34. PIEIER2 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 2.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 2.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 2.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 2.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 2.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 2.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 2.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 2.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 2.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 2.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 2.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 2.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 2.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 2.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 2.2
Reset type: SYSRSn

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Table 3-34. PIEIER2 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INTx1 R/W 0h Enable for Interrupt 2.1
Reset type: SYSRSn

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3.17.3.6 PIEIFR2 Register (Offset = 5h) [Reset = 0000h]

PIEIFR2 is shown in Figure 3-36 and described in Table 3-35.
Return to the Summary Table.
Interrupt Group 2 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like
the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution
in the application code. Reading the PIE IFR registers is safe.
Figure 3-36. PIEIFR2 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-35. PIEIFR2 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 2.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 2.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 2.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 2.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 2.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 2.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 2.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 2.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 2.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 2.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 2.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 2.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 2.4
Reset type: SYSRSn

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Table 3-35. PIEIFR2 Register Field Descriptions (continued)

Bit Field Type Reset Description
2 INTx3 R/W 0h Flag for Interrupt 2.3
Reset type: SYSRSn
1 INTx2 R/W 0h Flag for Interrupt 2.2
Reset type: SYSRSn
0 INTx1 R/W 0h Flag for Interrupt 2.1
Reset type: SYSRSn

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3.17.3.7 PIEIER3 Register (Offset = 6h) [Reset = 0000h]

PIEIER3 is shown in Figure 3-37 and described in Table 3-36.
Return to the Summary Table.
Interrupt Group 3 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the
CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal
can still set the PIEIFR bit for the disabled interrupt.
Figure 3-37. PIEIER3 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-36. PIEIER3 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 3.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 3.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 3.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 3.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 3.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 3.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 3.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 3.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 3.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 3.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 3.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 3.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 3.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 3.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 3.2
Reset type: SYSRSn

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Table 3-36. PIEIER3 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INTx1 R/W 0h Enable for Interrupt 3.1
Reset type: SYSRSn

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3.17.3.8 PIEIFR3 Register (Offset = 7h) [Reset = 0000h]

PIEIFR3 is shown in Figure 3-38 and described in Table 3-37.
Return to the Summary Table.
Interrupt Group 3 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like
the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution
in the application code. Reading the PIE IFR registers is safe.
Figure 3-38. PIEIFR3 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-37. PIEIFR3 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 3.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 3.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 3.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 3.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 3.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 3.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 3.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 3.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 3.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 3.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 3.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 3.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 3.4
Reset type: SYSRSn

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Table 3-37. PIEIFR3 Register Field Descriptions (continued)

Bit Field Type Reset Description
2 INTx3 R/W 0h Flag for Interrupt 3.3
Reset type: SYSRSn
1 INTx2 R/W 0h Flag for Interrupt 3.2
Reset type: SYSRSn
0 INTx1 R/W 0h Flag for Interrupt 3.1
Reset type: SYSRSn

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3.17.3.9 PIEIER4 Register (Offset = 8h) [Reset = 0000h]

PIEIER4 is shown in Figure 3-39 and described in Table 3-38.
Return to the Summary Table.
Interrupt Group 4 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the
CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal
can still set the PIEIFR bit for the disabled interrupt.
Figure 3-39. PIEIER4 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-38. PIEIER4 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 4.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 4.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 4.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 4.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 4.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 4.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 4.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 4.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 4.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 4.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 4.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 4.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 4.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 4.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 4.2
Reset type: SYSRSn

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Table 3-38. PIEIER4 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INTx1 R/W 0h Enable for Interrupt 4.1
Reset type: SYSRSn

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3.17.3.10 PIEIFR4 Register (Offset = 9h) [Reset = 0000h]

PIEIFR4 is shown in Figure 3-40 and described in Table 3-39.
Return to the Summary Table.
Interrupt Group 4 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like
the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution
in the application code. Reading the PIE IFR registers is safe.
Figure 3-40. PIEIFR4 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-39. PIEIFR4 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 4.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 4.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 4.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 4.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 4.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 4.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 4.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 4.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 4.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 4.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 4.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 4.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 4.4
Reset type: SYSRSn

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Table 3-39. PIEIFR4 Register Field Descriptions (continued)

Bit Field Type Reset Description
2 INTx3 R/W 0h Flag for Interrupt 4.3
Reset type: SYSRSn
1 INTx2 R/W 0h Flag for Interrupt 4.2
Reset type: SYSRSn
0 INTx1 R/W 0h Flag for Interrupt 4.1
Reset type: SYSRSn

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3.17.3.11 PIEIER5 Register (Offset = Ah) [Reset = 0000h]

PIEIER5 is shown in Figure 3-41 and described in Table 3-40.
Return to the Summary Table.
Interrupt Group 5 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the
CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal
can still set the PIEIFR bit for the disabled interrupt.
Figure 3-41. PIEIER5 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-40. PIEIER5 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 5.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 5.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 5.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 5.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 5.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 5.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 5.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 5.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 5.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 5.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 5.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 5.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 5.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 5.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 5.2
Reset type: SYSRSn

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Table 3-40. PIEIER5 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INTx1 R/W 0h Enable for Interrupt 5.1
Reset type: SYSRSn

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3.17.3.12 PIEIFR5 Register (Offset = Bh) [Reset = 0000h]

PIEIFR5 is shown in Figure 3-42 and described in Table 3-41.
Return to the Summary Table.
Interrupt Group 5 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like
the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution
in the application code. Reading the PIE IFR registers is safe.
Figure 3-42. PIEIFR5 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-41. PIEIFR5 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 5.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 5.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 5.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 5.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 5.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 5.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 5.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 5.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 5.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 5.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 5.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 5.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 5.4
Reset type: SYSRSn

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Table 3-41. PIEIFR5 Register Field Descriptions (continued)

Bit Field Type Reset Description
2 INTx3 R/W 0h Flag for Interrupt 5.3
Reset type: SYSRSn
1 INTx2 R/W 0h Flag for Interrupt 5.2
Reset type: SYSRSn
0 INTx1 R/W 0h Flag for Interrupt 5.1
Reset type: SYSRSn

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3.17.3.13 PIEIER6 Register (Offset = Ch) [Reset = 0000h]

PIEIER6 is shown in Figure 3-43 and described in Table 3-42.
Return to the Summary Table.
Interrupt Group 6 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the
CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal
can still set the PIEIFR bit for the disabled interrupt.
Figure 3-43. PIEIER6 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-42. PIEIER6 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 6.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 6.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 6.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 6.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 6.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 6.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 6.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 6.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 6.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 6.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 6.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 6.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 6.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 6.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 6.2
Reset type: SYSRSn

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Table 3-42. PIEIER6 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INTx1 R/W 0h Enable for Interrupt 6.1
Reset type: SYSRSn

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3.17.3.14 PIEIFR6 Register (Offset = Dh) [Reset = 0000h]

PIEIFR6 is shown in Figure 3-44 and described in Table 3-43.
Return to the Summary Table.
Interrupt Group 6 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like
the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution
in the application code. Reading the PIE IFR registers is safe.
Figure 3-44. PIEIFR6 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-43. PIEIFR6 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 6.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 6.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 6.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 6.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 6.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 6.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 6.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 6.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 6.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 6.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 6.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 6.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 6.4
Reset type: SYSRSn

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Table 3-43. PIEIFR6 Register Field Descriptions (continued)

Bit Field Type Reset Description
2 INTx3 R/W 0h Flag for Interrupt 6.3
Reset type: SYSRSn
1 INTx2 R/W 0h Flag for Interrupt 6.2
Reset type: SYSRSn
0 INTx1 R/W 0h Flag for Interrupt 6.1
Reset type: SYSRSn

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3.17.3.15 PIEIER7 Register (Offset = Eh) [Reset = 0000h]

PIEIER7 is shown in Figure 3-45 and described in Table 3-44.
Return to the Summary Table.
Interrupt Group 7 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the
CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal
can still set the PIEIFR bit for the disabled interrupt.
Figure 3-45. PIEIER7 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-44. PIEIER7 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 7.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 7.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 7.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 7.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 7.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 7.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 7.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 7.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 7.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 7.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 7.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 7.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 7.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 7.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 7.2
Reset type: SYSRSn

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Table 3-44. PIEIER7 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INTx1 R/W 0h Enable for Interrupt 7.1
Reset type: SYSRSn

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3.17.3.16 PIEIFR7 Register (Offset = Fh) [Reset = 0000h]

PIEIFR7 is shown in Figure 3-46 and described in Table 3-45.
Return to the Summary Table.
Interrupt Group 7 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like
the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution
in the application code. Reading the PIE IFR registers is safe.
Figure 3-46. PIEIFR7 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-45. PIEIFR7 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 7.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 7.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 7.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 7.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 7.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 7.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 7.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 7.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 7.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 7.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 7.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 7.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 7.4
Reset type: SYSRSn

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Table 3-45. PIEIFR7 Register Field Descriptions (continued)

Bit Field Type Reset Description
2 INTx3 R/W 0h Flag for Interrupt 7.3
Reset type: SYSRSn
1 INTx2 R/W 0h Flag for Interrupt 7.2
Reset type: SYSRSn
0 INTx1 R/W 0h Flag for Interrupt 7.1
Reset type: SYSRSn

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3.17.3.17 PIEIER8 Register (Offset = 10h) [Reset = 0000h]

PIEIER8 is shown in Figure 3-47 and described in Table 3-46.
Return to the Summary Table.
Interrupt Group 8 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the
CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal
can still set the PIEIFR bit for the disabled interrupt.
Figure 3-47. PIEIER8 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-46. PIEIER8 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 8.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 8.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 8.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 8.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 8.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 8.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 8.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 8.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 8.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 8.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 8.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 8.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 8.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 8.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 8.2
Reset type: SYSRSn

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Table 3-46. PIEIER8 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INTx1 R/W 0h Enable for Interrupt 8.1
Reset type: SYSRSn

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3.17.3.18 PIEIFR8 Register (Offset = 11h) [Reset = 0000h]

PIEIFR8 is shown in Figure 3-48 and described in Table 3-47.
Return to the Summary Table.
Interrupt Group 8 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like
the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution
in the application code. Reading the PIE IFR registers is safe.
Figure 3-48. PIEIFR8 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-47. PIEIFR8 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 8.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 8.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 8.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 8.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 8.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 8.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 8.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 8.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 8.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 8.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 8.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 8.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 8.4
Reset type: SYSRSn

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Table 3-47. PIEIFR8 Register Field Descriptions (continued)

Bit Field Type Reset Description
2 INTx3 R/W 0h Flag for Interrupt 8.3
Reset type: SYSRSn
1 INTx2 R/W 0h Flag for Interrupt 8.2
Reset type: SYSRSn
0 INTx1 R/W 0h Flag for Interrupt 8.1
Reset type: SYSRSn

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3.17.3.19 PIEIER9 Register (Offset = 12h) [Reset = 0000h]

PIEIER9 is shown in Figure 3-49 and described in Table 3-48.
Return to the Summary Table.
Interrupt Group 9 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the
CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal
can still set the PIEIFR bit for the disabled interrupt.
Figure 3-49. PIEIER9 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-48. PIEIER9 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 9.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 9.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 9.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 9.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 9.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 9.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 9.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 9.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 9.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 9.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 9.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 9.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 9.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 9.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 9.2
Reset type: SYSRSn

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Table 3-48. PIEIER9 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INTx1 R/W 0h Enable for Interrupt 9.1
Reset type: SYSRSn

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3.17.3.20 PIEIFR9 Register (Offset = 13h) [Reset = 0000h]

PIEIFR9 is shown in Figure 3-50 and described in Table 3-49.
Return to the Summary Table.
Interrupt Group 9 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like
the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution
in the application code. Reading the PIE IFR registers is safe.
Figure 3-50. PIEIFR9 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-49. PIEIFR9 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 9.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 9.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 9.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 9.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 9.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 9.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 9.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 9.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 9.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 9.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 9.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 9.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 9.4
Reset type: SYSRSn

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Table 3-49. PIEIFR9 Register Field Descriptions (continued)

Bit Field Type Reset Description
2 INTx3 R/W 0h Flag for Interrupt 9.3
Reset type: SYSRSn
1 INTx2 R/W 0h Flag for Interrupt 9.2
Reset type: SYSRSn
0 INTx1 R/W 0h Flag for Interrupt 9.1
Reset type: SYSRSn

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3.17.3.21 PIEIER10 Register (Offset = 14h) [Reset = 0000h]

PIEIER10 is shown in Figure 3-51 and described in Table 3-50.
Return to the Summary Table.
Interrupt Group 10 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the
CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal
can still set the PIEIFR bit for the disabled interrupt.
Figure 3-51. PIEIER10 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-50. PIEIER10 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 10.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 10.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 10.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 10.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 10.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 10.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 10.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 10.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 10.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 10.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 10.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 10.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 10.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 10.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 10.2
Reset type: SYSRSn

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Table 3-50. PIEIER10 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INTx1 R/W 0h Enable for Interrupt 10.1
Reset type: SYSRSn

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3.17.3.22 PIEIFR10 Register (Offset = 15h) [Reset = 0000h]

PIEIFR10 is shown in Figure 3-52 and described in Table 3-51.
Return to the Summary Table.
Interrupt Group 10 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like
the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution
in the application code. Reading the PIE IFR registers is safe.
Figure 3-52. PIEIFR10 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-51. PIEIFR10 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 10.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 10.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 10.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 10.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 10.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 10.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 10.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 10.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 10.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 10.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 10.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 10.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 10.4
Reset type: SYSRSn

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Table 3-51. PIEIFR10 Register Field Descriptions (continued)

Bit Field Type Reset Description
2 INTx3 R/W 0h Flag for Interrupt 10.3
Reset type: SYSRSn
1 INTx2 R/W 0h Flag for Interrupt 10.2
Reset type: SYSRSn
0 INTx1 R/W 0h Flag for Interrupt 10.1
Reset type: SYSRSn

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3.17.3.23 PIEIER11 Register (Offset = 16h) [Reset = 0000h]

PIEIER11 is shown in Figure 3-53 and described in Table 3-52.
Return to the Summary Table.
Interrupt Group 11 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the
CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal
can still set the PIEIFR bit for the disabled interrupt.
Figure 3-53. PIEIER11 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-52. PIEIER11 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 11.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 11.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 11.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 11.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 11.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 11.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 11.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 11.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 11.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 11.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 11.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 11.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 11.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 11.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 11.2
Reset type: SYSRSn

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Table 3-52. PIEIER11 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INTx1 R/W 0h Enable for Interrupt 11.1
Reset type: SYSRSn

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3.17.3.24 PIEIFR11 Register (Offset = 17h) [Reset = 0000h]

PIEIFR11 is shown in Figure 3-54 and described in Table 3-53.
Return to the Summary Table.
Interrupt Group 11 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like
the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution
in the application code. Reading the PIE IFR registers is safe.
Figure 3-54. PIEIFR11 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-53. PIEIFR11 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 11.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 11.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 11.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 11.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 11.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 11.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 11.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 11.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 11.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 11.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 11.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 11.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 11.4
Reset type: SYSRSn

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Table 3-53. PIEIFR11 Register Field Descriptions (continued)

Bit Field Type Reset Description
2 INTx3 R/W 0h Flag for Interrupt 11.3
Reset type: SYSRSn
1 INTx2 R/W 0h Flag for Interrupt 11.2
Reset type: SYSRSn
0 INTx1 R/W 0h Flag for Interrupt 11.1
Reset type: SYSRSn

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3.17.3.25 PIEIER12 Register (Offset = 18h) [Reset = 0000h]

PIEIER12 is shown in Figure 3-55 and described in Table 3-54.
Return to the Summary Table.
Interrupt Group 12 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the
CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal
can still set the PIEIFR bit for the disabled interrupt.
Figure 3-55. PIEIER12 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-54. PIEIER12 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 12.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 12.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 12.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 12.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 12.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 12.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 12.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 12.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 12.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 12.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 12.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 12.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 12.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 12.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 12.2
Reset type: SYSRSn

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Table 3-54. PIEIER12 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INTx1 R/W 0h Enable for Interrupt 12.1
Reset type: SYSRSn

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3.17.3.26 PIEIFR12 Register (Offset = 19h) [Reset = 0000h]

PIEIFR12 is shown in Figure 3-56 and described in Table 3-55.
Return to the Summary Table.
Interrupt Group 12 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like
the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution
in the application code. Reading the PIE IFR registers is safe.
Figure 3-56. PIEIFR12 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-55. PIEIFR12 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 12.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 12.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 12.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 12.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 12.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 12.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 12.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 12.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 12.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 12.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 12.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 12.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 12.4
Reset type: SYSRSn

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Table 3-55. PIEIFR12 Register Field Descriptions (continued)

Bit Field Type Reset Description
2 INTx3 R/W 0h Flag for Interrupt 12.3
Reset type: SYSRSn
1 INTx2 R/W 0h Flag for Interrupt 12.2
Reset type: SYSRSn
0 INTx1 R/W 0h Flag for Interrupt 12.1
Reset type: SYSRSn

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3.17.4 WD_REGS Registers

Table 3-56 lists the memory-mapped registers for the WD_REGS registers. All register offset addresses not
listed in Table 3-56 should be considered as reserved locations and the register contents should not be modified.
Table 3-56. WD_REGS Registers
Offset Acronym Register Name Write Protection Section
22h SCSR System Control & Status Register EALLOW Go
23h WDCNTR Watchdog Counter Register EALLOW Go
25h WDKEY Watchdog Reset Key Register EALLOW Go
29h WDCR Watchdog Control Register EALLOW Go
Note: IORSn reset type is asserted when
XRSn or CPU1.SYSRSn or CPU1.WDRSn or
CPU1.NMIRSn is asserted.
2Ah WDWCR Watchdog Windowed Control Register EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 3-57 shows the codes that are used for
access types in this section.
Table 3-57. WD_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1C W Write
1C 1 to clear
W1S W Write
1S 1 to set
Reset or Default Value
-n Value after reset or the default value
Register Array Variables
i,j,k,l,m,n When these variables are used in a register name,
an offset, or an address, they refer to the value of a
register array where the register is part of a group
of repeating registers. The register groups form a
hierarchical structure and the array is represented
with a formula.
y When this variable is used in a register name, an
offset, or an address it refers to the value of a
register array.

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3.17.4.1 SCSR Register (Offset = 22h) [Reset = 0005h]

SCSR is shown in Figure 3-57 and described in Table 3-58.
Return to the Summary Table.
It is recommended to only use 16 bit accesses to write to this register. Use a read-modify-write instruction may
inadvertently clear other bits.
Figure 3-57. SCSR Register
15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED WDINTS WDENINT WDOVERRIDE
R-0-0h R-1h R/W-0h R/W1C-1h

Table 3-58. SCSR Register Field Descriptions

Bit Field Type Reset Description
15-3 RESERVED R-0 0h Reserved
2 WDINTS R 1h Watchdog interrupt (WDINTn) status signal. This is a read only bit
reflecting the current state of the WDINTn signal from the watchdog
block (after synchronization with SYSCLKOUT). If this bit is 1, the
watchdog interrupt is not active. If this bit is 0, then the watchdog
interrupt is active.
Note: ,If the WDINTn signal is used to wake up from IDLE or
STANDBY condition, then the user should make sure that the
WDINTn signal goes back high again before attempting to go back
into IDLE or STANDBY mode. Reading this bit will tell the user the
current state of this signal.
Reset type: SYSRSn
1 WDENINT R/W 0h If this bit is set to 1, the watchdog reset (WDRSTn) output signal
is disabled and the watchdog interrupt (WDINTn) output signal is
enabled. If this bit is zero, then the WDRSTn output signal is enabled
and the WDINTn output signal is disabled. This is the default state
on system reset (SYSRSn).
Reset type: SYSRSn
0 WDOVERRIDE R/W1C 1h If this bit is set to 1, the user is allowed to change the state of the
Watchdog disable (WDDIS) bit in the Watchdog Control (WDCR)
register. If the WDOVERRIDE bit is cleared, by writing a 1 the
WDDIS bit cannot be modified by the user. Writing a 0 will have
no effect. If this bit is cleared, then it will remain in this state until a
reset occurs. The current state of this bit is readable by the user.
Reset type: SYSRSn

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3.17.4.2 WDCNTR Register (Offset = 23h) [Reset = 0000h]

WDCNTR is shown in Figure 3-58 and described in Table 3-59.
Return to the Summary Table.
Watchdog Counter Register
Figure 3-58. WDCNTR Register
15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
WDCNTR
R-0h

Table 3-59. WDCNTR Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R-0 0h Reserved
7-0 WDCNTR R 0h These bits contain the current value of the WD counter. The 8-bit
counter continually increments at the WDCLK rate. If the counter
overflows, then a watchdog output pulse (WDOUTn) is generated.
If the WDKEY register is written with a valid combination, then the
counter is reset to zero.
Reset type: IORSn

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3.17.4.3 WDKEY Register (Offset = 25h) [Reset = 0000h]

WDKEY is shown in Figure 3-59 and described in Table 3-60.
Return to the Summary Table.
Watchdog Reset Key Register
Figure 3-59. WDKEY Register
15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
WDKEY
R/W-0h

Table 3-60. WDKEY Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R-0 0h Reserved
7-0 WDKEY R/W 0h Writing 0x55 followed by 0xAA will cause the WDCNTR bits to be
cleared.
Note:
[1] Reads from the WDKEY return the value of WDCR register.
Reset type: IORSn

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3.17.4.4 WDCR Register (Offset = 29h) [Reset = 0000h]

WDCR is shown in Figure 3-60 and described in Table 3-61.
Return to the Summary Table.
Watchdog Control Register
This memory mapped register requires a delay of 69 SYSCLK cycles between subsequent writes to the register,
otherwise a second write can be lost. This delay can be realized by adding 69 NOP instructions.
Figure 3-60. WDCR Register
15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED WDDIS WDCHK WDPS
R/W1S-0h R/W-0h R-0/W-0h R/W-0h

Table 3-61. WDCR Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R-0 0h Reserved
7 RESERVED R/W1S 0h Reserved
6 WDDIS R/W 0h Writing a 1 to this bit will disable the watchdog module. Writing
a 0 will enable the module. This bit can only be modified if the
WDOVERRIDE bit in the SCSR2 register is set to 1. On reset, the
watchdog module is enabled.
Reset type: IORSn
5-3 WDCHK R-0/W 0h The user must ALWAYS write 1,0,1 to these bits whenever a write
to this register is performed. Writing any other value will cause an
immediate reset to the core (if WD enabled).
Reset type: IORSn
2-0 WDPS R/W 0h These bits configure the watchdog counter clock (WDCLK) rate
relative to INTOSC1/512:
000 WDCLK = INTOSC1/512/1
001 WDCLK = INTOSC1/512/1
010 WDCLK = INTOSC1/512/2
011 WDCLK = INTOSC1/512/4
100 WDCLK = INTOSC1/512/8
101 WDCLK = INTOSC1/512/16
110 WDCLK = INTOSC1/512/32
111 WDCLK = INTOSC1/512/64
Reset type: IORSn

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3.17.4.5 WDWCR Register (Offset = 2Ah) [Reset = 0000h]

WDWCR is shown in Figure 3-61 and described in Table 3-62.
Return to the Summary Table.
Watchdog Windowed Control Register
Figure 3-61. WDWCR Register
15 14 13 12 11 10 9 8
RESERVED FIRSTKEY
R-0-0h R-0h

7 6 5 4 3 2 1 0
MIN
R/W-0h

Table 3-62. WDWCR Register Field Descriptions

Bit Field Type Reset Description
15-9 RESERVED R-0 0h Reserved
8 FIRSTKEY R 0h This bit indicates if the 1st valid WDKEY (0x55 + 0xAA) got detected
after MIN was configured to a non-zero value
0: First Valid Key after non-zero MIN configuration has not happened
yet
1: First Valid key after non-zero MIN configuration got detected
Notes:
[1] If MIN = 0, this bit is never set
[2] If MIN is changed back to 0x0 from a non-zero value, this bit is
auto-cleared
[3] This bit is added for debug purposes only
Reset type: IORSn
7-0 MIN R/W 0h Watchdog Window Threshold
These bits specify the lower limit of the watchdog counter reset
window. If the counter reset via the WDKEY register before the
counter value reaches the value in this register, the watchdog
immediately triggers a reset or interrupt.
Reset type: IORSn

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3.17.5 NMI_INTRUPT_REGS Registers

Table 3-63 lists the memory-mapped registers for the NMI_INTRUPT_REGS registers. All register offset
addresses not listed in Table 3-63 should be considered as reserved locations and the register contents should
not be modified.
Table 3-63. NMI_INTRUPT_REGS Registers
Offset Acronym Register Name Write Protection Section
0h NMICFG NMI Configuration Register EALLOW Go
1h NMIFLG NMI Flag Register (XRSn Clear) Go
2h NMIFLGCLR NMI Flag Clear Register EALLOW Go
3h NMIFLGFRC NMI Flag Force Register EALLOW Go
4h NMIWDCNT NMI Watchdog Counter Register Go
5h NMIWDPRD NMI Watchdog Period Register EALLOW Go
6h NMISHDFLG NMI Shadow Flag Register Go

Complex bit access types are encoded to fit into small table cells. Table 3-64 shows the codes that are used for
access types in this section.
Table 3-64. NMI_INTRUPT_REGS Access Type
Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1S W Write
1S 1 to set
Reset or Default Value
-n Value after reset or the default
value

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3.17.5.1 NMICFG Register (Offset = 0h) [Reset = 0000h]

NMICFG is shown in Figure 3-62 and described in Table 3-65.
Return to the Summary Table.
NMI Configuration Register
Figure 3-62. NMICFG Register
15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED NMIE
R-0-0h R/W1S-0h

Table 3-65. NMICFG Register Field Descriptions

Bit Field Type Reset Description
15-1 RESERVED R-0 0h Reserved
0 NMIE R/W1S 0h When set to 1 any condition will generate an NMI interrupt to the
C28 CPU and kick off the NMI watchdog counter. As part of boot
sequence this bit should be set after the device security related
initialization is complete.
0 NMI disabled
1 NMI enabled
Reset type: SYSRSn

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3.17.5.2 NMIFLG Register (Offset = 1h) [Reset = 0000h]

NMIFLG is shown in Figure 3-63 and described in Table 3-66.
Return to the Summary Table.
NMI Flag Register (XRSn Clear)
Figure 3-63. NMIFLG Register
15 14 13 12 11 10 9 8
RESERVED RESERVED CPU2NMIWDR CPU2WDRSn CLBNMI
Sn
R-0-0h R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
RESERVED PIEVECTERR CPU2HWBISTE CPU1HWBISTE FLUNCERR RAMUNCERR CLOCKFAIL NMIINT
RR RR
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 3-66. NMIFLG Register Field Descriptions

Bit Field Type Reset Description
15-12 RESERVED R-0 0h Reserved
11 RESERVED R 0h Reserved
10 CPU2NMIWDRSn R 0h CPU2 NMIWDRSn Reset Indication Flag: This bits indicates if
CPU2s NMIWDRSn was fired or not.
0 No CPU2.NMIWDRsn was fired
1 CPU2.NMIWDRSn was fired to CPU2
Note:
[1] This bits is reserved for CPU2.NMIFLG register
Reset type: XRSn
9 CPU2WDRSn R 0h CPU2 WDRSn Reset Indication Flag: This bits indicates if CPU2s
WDRSn was fired or not.
0 No CPU2.WDRsn was fired
1 CPU2.WDRSn was fired to CPU2
Note:
[1] This bits is reserved for CPU2.NMIFLG register
Reset type: XRSn
8 CLBNMI R 0h Configurable Logic Block NMI Flag: This bit indicates if an NMI
was generated by the Configurable Logic Block. This bit can only
be cleared by the user writing to the corresponding clear bit in the
NMIFLGCLR register or by an XRSn reset:
0,No Configurable Logic Block NMI pending
1,Configurable Logic Block NMI generated
Reset type: XRSn
7 RESERVED R 0h Reserved
6 PIEVECTERR R 0h PIE Vector Fetch Error Flag: This bit indicates if an error occurred
on an Vector Fect by the other CPU in the device. For example,
CPU1.NMIWD gets an NMI on an Vector fetch Error on CPU2. This
bit can only be cleared by the user writing to the corresponding clear
bit in the NMIFLGCLR register or by an XRSn reset:
0,No Vector Fetch Error condition (on the other CPU) pending
1,Vector Fetch error condition (on the other CPU) generated
Reset type: XRSn

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Table 3-66. NMIFLG Register Field Descriptions (continued)

Bit Field Type Reset Description
5 CPU2HWBISTERR R 0h HW BIST Error NMI Flag: This bit indicates if the time out error or
a signature mismatch error condition during hardware BIST of C28
CPU2 occurred. This bit can only be cleared by the user writing
to the corresponding clear bit in the NMIFLGCLR register or by an
XRSn reset:
0,No C28 HWBIST error condition pending
1,C28 BIST error condition generated
Reset type: XRSn
4 CPU1HWBISTERR R 0h HW BIST Error NMI Flag: This bit indicates if the time out error or
a signature mismatch error condition during hardware BIST of C28
CPU1 occurred. This bit can only be cleared by the user writing
to the corresponding clear bit in the NMIFLGCLR register or by an
XRSn reset:
0,No C28 HWBIST error condition pending
1,C28 BIST error condition generated
Reset type: XRSn
3 FLUNCERR R 0h Flash Uncorrectable Error NMI Flag: This bit indicates if an
uncorrectable error occurred on a C28 Flash access and that
condition is latched. This bit can only be cleared by the user writing
to the corresponding clear bit in the NMIFLGCLR register or by an
XRSn reset:
0,No C28 Flash uncorrectable error condition pending
1,C28 Flash uncorrectable error condition generated
Reset type: XRSn
2 RAMUNCERR R 0h RAM Uncorrectable Error NMI Flag: This bit indicates if an
uncorrectable error occurred on a RAM access (by any master) and
that condition is latched. This bit can only be cleared by the user
writing to the corresponding clear bit in the NMIFLGCLR register or
by an XRSn reset:
0,No RAM uncorrectable error condition pending
1,RAM uncorrectable error condition generated
Reset type: XRSn
1 CLOCKFAIL R 0h Clock Fail Interrupt Flag: These bits indicates if the CLOCKFAIL
condition is latched. These bits can only be cleared by the user
writing to the respective bit in the NMIFLGCLR register or by an
XRSn reset:
0,No CLOCKFAIL Condition Pending
1,CLOCKFAIL Condition Generated
Reset type: XRSn
0 NMIINT R 0h NMI Interrupt Flag: This bit indicates if an NMI interrupt was
generated. This bit can only be cleared by the user writing to the
respective bit in the NMIFLGCLR register or by an XRSn reset:
0 No NMI Interrupt Generated
1 NMI Interrupt Generated
No further NMI interrupts pulses are generated until this flag is
cleared by the user.
Reset type: XRSn

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3.17.5.3 NMIFLGCLR Register (Offset = 2h) [Reset = 0000h]

NMIFLGCLR is shown in Figure 3-64 and described in Table 3-67.
Return to the Summary Table.
NMI Flag Clear Register
Figure 3-64. NMIFLGCLR Register
15 14 13 12 11 10 9 8
RESERVED RESERVED CPU2NMIWDR CPU2WDRSn CLBNMI
Sn
R-0-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

7 6 5 4 3 2 1 0
RESERVED PIEVECTERR CPU2HWBISTE CPU1HWBISTE FLUNCERR RAMUNCERR CLOCKFAIL NMIINT
RR RR
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-67. NMIFLGCLR Register Field Descriptions

Bit Field Type Reset Description
15-12 RESERVED R-0 0h Reserved
11 RESERVED R-0/W1S 0h Reserved
10 CPU2NMIWDRSn R-0/W1S 0h Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn
9 CPU2WDRSn R-0/W1S 0h Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
[3] CPU2WDRSn and CPU2NMIWDRSn bits are reserved for
CPU2.NMIFLGCLR registers
Reset type: SYSRSn
8 CLBNMI R-0/W1S 0h Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn
7 RESERVED R-0/W1S 0h Reserved

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Table 3-67. NMIFLGCLR Register Field Descriptions (continued)

Bit Field Type Reset Description
6 PIEVECTERR R-0/W1S 0h Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn
5 CPU2HWBISTERR R-0/W1S 0h Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn
4 CPU1HWBISTERR R-0/W1S 0h Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn
3 FLUNCERR R-0/W1S 0h Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn
2 RAMUNCERR R-0/W1S 0h Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn
1 CLOCKFAIL R-0/W1S 0h Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn

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Table 3-67. NMIFLGCLR Register Field Descriptions (continued)

Bit Field Type Reset Description
0 NMIINT R-0/W1S 0h Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn

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3.17.5.4 NMIFLGFRC Register (Offset = 3h) [Reset = 0000h]

NMIFLGFRC is shown in Figure 3-65 and described in Table 3-68.
Return to the Summary Table.
NMI Flag Force Register
Figure 3-65. NMIFLGFRC Register
15 14 13 12 11 10 9 8
RESERVED RESERVED CPU2NMIWDR CPU2WDRSn CLBNMI
Sn
R-0-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

7 6 5 4 3 2 1 0
RESERVED PIEVECTERR CPU2HWBISTE CPU1HWBISTE FLUNCERR RAMUNCERR CLOCKFAIL RESERVED
RR RR
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0-0h

Table 3-68. NMIFLGFRC Register Field Descriptions

Bit Field Type Reset Description
15-12 RESERVED R-0 0h Reserved
11 RESERVED R-0/W1S 0h Reserved
10 CPU2NMIWDRSn R-0/W1S 0h Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
Note:
[1] CPU2WDRSn and CPU2NMIWDRSn bits are reserved for
CPU2.NMIFLGCLR registers
Reset type: SYSRSn
9 CPU2WDRSn R-0/W1S 0h Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
Note:
[1] CPU2WDRSn and CPU2NMIWDRSn bits are reserved for
CPU2.NMIFLGCLR registers
Reset type: SYSRSn
8 CLBNMI R-0/W1S 0h Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
Reset type: SYSRSn
7 RESERVED R-0/W1S 0h Reserved
6 PIEVECTERR R-0/W1S 0h Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
Reset type: SYSRSn
5 CPU2HWBISTERR R-0/W1S 0h Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
Reset type: SYSRSn
4 CPU1HWBISTERR R-0/W1S 0h Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
Reset type: SYSRSn

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Table 3-68. NMIFLGFRC Register Field Descriptions (continued)

Bit Field Type Reset Description
3 FLUNCERR R-0/W1S 0h Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
Reset type: SYSRSn
2 RAMUNCERR R-0/W1S 0h Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
Reset type: SYSRSn
1 CLOCKFAIL R-0/W1S 0h Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
Reset type: SYSRSn
0 RESERVED R-0 0h Reserved

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3.17.5.5 NMIWDCNT Register (Offset = 4h) [Reset = 0000h]

NMIWDCNT is shown in Figure 3-66 and described in Table 3-69.
Return to the Summary Table.
NMI Watchdog Counter Register
Figure 3-66. NMIWDCNT Register
15 14 13 12 11 10 9 8
NMIWDCNT
R-0h

7 6 5 4 3 2 1 0
NMIWDCNT
R-0h

Table 3-69. NMIWDCNT Register Field Descriptions

Bit Field Type Reset Description
15-0 NMIWDCNT R 0h NMI Watchdog Counter: This 16-bit incremental counter will start
incrementing whenever any one of the enabled FAIL flags are set.
If the counter reaches the period value, an NMIRSn signal is fired
which will then resets the system. The counter will reset to zero
when it reaches the period value and will then restart counting if any
of the enabled FAIL flags are set.
If no enabled FAIL flag is set, then the counter will reset to zero and
remain at zero until an enabled FAIL flag is set.
Normally, the software would respond to the NMI interrupt generated
and clear the offending FLAG(s) before the NMI watchdog triggers
a reset. In some situations, the software may decide to allow the
watchdog to reset the device anyway.
The counter is clocked at the SYSCLKOUT rate.
Reset type: SYSRSn

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3.17.5.6 NMIWDPRD Register (Offset = 5h) [Reset = FFFFh]

NMIWDPRD is shown in Figure 3-67 and described in Table 3-70.
Return to the Summary Table.
NMI Watchdog Period Register
Figure 3-67. NMIWDPRD Register
15 14 13 12 11 10 9 8
NMIWDPRD
R/W-FFFFh

7 6 5 4 3 2 1 0
NMIWDPRD
R/W-FFFFh

Table 3-70. NMIWDPRD Register Field Descriptions

Bit Field Type Reset Description
15-0 NMIWDPRD R/W FFFFh NMI Watchdog Period: This 16-bit value contains the period value at
which a reset is generated when the watchdog counter matches. At
reset this value is set at the maximum. The software can decrease
the period value at initialization time.
Writing a PERIOD value that is smaller then the current counter
value will automatically force an NMIRSn and hence reset the
watchdog counter.
Reset type: SYSRSn

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3.17.5.7 NMISHDFLG Register (Offset = 6h) [Reset = 0000h]

NMISHDFLG is shown in Figure 3-68 and described in Table 3-71.
Return to the Summary Table.
NMI Shadow Flag Register
Figure 3-68. NMISHDFLG Register
15 14 13 12 11 10 9 8
RESERVED RESERVED CPU2NMIWDR CPU2WDRSn CLBNMI
Sn
R-0-0h R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
RESERVED PIEVECTERR CPU2HWBISTE CPU1HWBISTE FLUNCERR RAMUNCERR CLOCKFAIL RESERVED
RR RR
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0-0h

Table 3-71. NMISHDFLG Register Field Descriptions

Bit Field Type Reset Description
15-12 RESERVED R-0 0h Reserved
11 RESERVED R 0h Reserved
10 CPU2NMIWDRSn R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for the
NMIFLG register. This register is only reset by a PORESETn reset.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
Reset type: PORESETn
9 CPU2WDRSn R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for the
NMIFLG register. This register is only reset by a PORESETn reset.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
[2] CPU2WDRSn and CPU2NMIWDRSn bits are reserved for
CPU2.NMIFLGCLR registers
Reset type: PORESETn
8 CLBNMI R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for the
NMIFLG register. This register is only reset by a PORESETn reset.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
Reset type: PORESETn
7 RESERVED R 0h Reserved

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Table 3-71. NMISHDFLG Register Field Descriptions (continued)

Bit Field Type Reset Description
6 PIEVECTERR R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for the
NMIFLG register. This register is only reset by a PORESETn reset.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
Reset type: PORESETn
5 CPU2HWBISTERR R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for the
NMIFLG register. This register is only reset by a PORESETn reset.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
Reset type: PORESETn
4 CPU1HWBISTERR R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for the
NMIFLG register. This register is only reset by a PORESETn reset.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
Reset type: PORESETn
3 FLUNCERR R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for the
NMIFLG register. This register is only reset by a PORESETn reset.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
Reset type: PORESETn
2 RAMUNCERR R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for the
NMIFLG register. This register is only reset by a PORESETn reset.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
Reset type: PORESETn
1 CLOCKFAIL R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for the
NMIFLG register. This register is only reset by a PORESETn reset.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
Reset type: PORESETn
0 RESERVED R-0 0h Reserved

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3.17.6 XINT_REGS Registers

Table 3-72 lists the memory-mapped registers for the XINT_REGS registers. All register offset addresses not
listed in Table 3-72 should be considered as reserved locations and the register contents should not be modified.
Table 3-72. XINT_REGS Registers
Offset Acronym Register Name Write Protection Section
0h XINT1CR XINT1 configuration register Go
1h XINT2CR XINT2 configuration register Go
2h XINT3CR XINT3 configuration register Go
3h XINT4CR XINT4 configuration register Go
4h XINT5CR XINT5 configuration register Go
8h XINT1CTR XINT1 counter register Go
9h XINT2CTR XINT2 counter register Go
Ah XINT3CTR XINT3 counter register Go

Complex bit access types are encoded to fit into small table cells. Table 3-73 shows the codes that are used for
access types in this section.
Table 3-73. XINT_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default value
Register Array Variables
i,j,k,l,m,n When these variables are used in a register name,
an offset, or an address, they refer to the value of a
register array where the register is part of a group
of repeating registers. The register groups form a
hierarchical structure and the array is represented
with a formula.
y When this variable is used in a register name, an
offset, or an address it refers to the value of a
register array.

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3.17.6.1 XINT1CR Register (Offset = 0h) [Reset = 0000h]

XINT1CR is shown in Figure 3-69 and described in Table 3-74.
Return to the Summary Table.
XINT1 configuration register
Figure 3-69. XINT1CR Register
15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED POLARITY RESERVED ENABLE
R-0-0h R/W-0h R-0-0h R/W-0h

Table 3-74. XINT1CR Register Field Descriptions

Bit Field Type Reset Description
15-4 RESERVED R-0 0h Reserved
3-2 POLARITY R/W 0h 00: Interrupt is selected as negative edge triggered
01: Interrupt is selected as positive edge triggered
10: Interrupt is selected as negative edge triggered
11: Interrupt is selected as positive or negative edge triggered
Reset type: SYSRSn
1 RESERVED R-0 0h Reserved
0 ENABLE R/W 0h 0: Interrupt Disabled
1: Interrupt Enabled
Reset type: SYSRSn

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3.17.6.2 XINT2CR Register (Offset = 1h) [Reset = 0000h]

XINT2CR is shown in Figure 3-70 and described in Table 3-75.
Return to the Summary Table.
XINT2 configuration register
Figure 3-70. XINT2CR Register
15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED POLARITY RESERVED ENABLE
R-0-0h R/W-0h R-0-0h R/W-0h

Table 3-75. XINT2CR Register Field Descriptions

Bit Field Type Reset Description
15-4 RESERVED R-0 0h Reserved
3-2 POLARITY R/W 0h 00: Interrupt is selected as negative edge triggered
01: Interrupt is selected as positive edge triggered
10: Interrupt is selected as negative edge triggered
11: Interrupt is selected as positive or negative edge triggered
Reset type: SYSRSn
1 RESERVED R-0 0h Reserved
0 ENABLE R/W 0h 0: Interrupt Disabled
1: Interrupt Enabled
Reset type: SYSRSn

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3.17.6.3 XINT3CR Register (Offset = 2h) [Reset = 0000h]

XINT3CR is shown in Figure 3-71 and described in Table 3-76.
Return to the Summary Table.
XINT3 configuration register
Figure 3-71. XINT3CR Register
15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED POLARITY RESERVED ENABLE
R-0-0h R/W-0h R-0-0h R/W-0h

Table 3-76. XINT3CR Register Field Descriptions

Bit Field Type Reset Description
15-4 RESERVED R-0 0h Reserved
3-2 POLARITY R/W 0h 00: Interrupt is selected as negative edge triggered
01: Interrupt is selected as positive edge triggered
10: Interrupt is selected as negative edge triggered
11: Interrupt is selected as positive or negative edge triggered
Reset type: SYSRSn
1 RESERVED R-0 0h Reserved
0 ENABLE R/W 0h 0: Interrupt Disabled
1: Interrupt Enabled
Reset type: SYSRSn

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3.17.6.4 XINT4CR Register (Offset = 3h) [Reset = 0000h]

XINT4CR is shown in Figure 3-72 and described in Table 3-77.
Return to the Summary Table.
XINT4 configuration register
Figure 3-72. XINT4CR Register
15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED POLARITY RESERVED ENABLE
R-0-0h R/W-0h R-0-0h R/W-0h

Table 3-77. XINT4CR Register Field Descriptions

Bit Field Type Reset Description
15-4 RESERVED R-0 0h Reserved
3-2 POLARITY R/W 0h 00: Interrupt is selected as negative edge triggered
01: Interrupt is selected as positive edge triggered
10: Interrupt is selected as negative edge triggered
11: Interrupt is selected as positive or negative edge triggered
Reset type: SYSRSn
1 RESERVED R-0 0h Reserved
0 ENABLE R/W 0h 0: Interrupt Disabled
1: Interrupt Enabled
Reset type: SYSRSn

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3.17.6.5 XINT5CR Register (Offset = 4h) [Reset = 0000h]

XINT5CR is shown in Figure 3-73 and described in Table 3-78.
Return to the Summary Table.
XINT5 configuration register
Figure 3-73. XINT5CR Register
15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED POLARITY RESERVED ENABLE
R-0-0h R/W-0h R-0-0h R/W-0h

Table 3-78. XINT5CR Register Field Descriptions

Bit Field Type Reset Description
15-4 RESERVED R-0 0h Reserved
3-2 POLARITY R/W 0h 00: Interrupt is selected as negative edge triggered
01: Interrupt is selected as positive edge triggered
10: Interrupt is selected as negative edge triggered
11: Interrupt is selected as positive or negative edge triggered
Reset type: SYSRSn
1 RESERVED R-0 0h Reserved
0 ENABLE R/W 0h 0: Interrupt Disabled
1: Interrupt Enabled
Reset type: SYSRSn

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3.17.6.6 XINT1CTR Register (Offset = 8h) [Reset = 0000h]

XINT1CTR is shown in Figure 3-74 and described in Table 3-79.
Return to the Summary Table.
XINT1 counter register
Figure 3-74. XINT1CTR Register
15 14 13 12 11 10 9 8
INTCTR
R-0h

7 6 5 4 3 2 1 0
INTCTR
R-0h

Table 3-79. XINT1CTR Register Field Descriptions

Bit Field Type Reset Description
15-0 INTCTR R 0h This is a free running 16-bit up-counter that is clocked at the
SYSCLKOUT rate. The counter value is reset to 0x0000 when a
valid interrupt edge is detected and then continues counting until
the next valid interrupt edge is detected. The counter must only be
reset by the selected POLARITY edge as selected in the respective
interrupt control register. When the interrupt is disabled, the counter
will stop. The counter is a free-running counter and will wrap around
to zero when the max value is reached. The counter is a read only
register and can only be reset to zero by a valid interrupt edge or by
reset.
Reset type: SYSRSn

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3.17.6.7 XINT2CTR Register (Offset = 9h) [Reset = 0000h]

XINT2CTR is shown in Figure 3-75 and described in Table 3-80.
Return to the Summary Table.
XINT2 counter register
Figure 3-75. XINT2CTR Register
15 14 13 12 11 10 9 8
INTCTR
R-0h

7 6 5 4 3 2 1 0
INTCTR
R-0h

Table 3-80. XINT2CTR Register Field Descriptions

Bit Field Type Reset Description
15-0 INTCTR R 0h This is a free running 16-bit up-counter that is clocked at the
SYSCLKOUT rate. The counter value is reset to 0x0000 when a
valid interrupt edge is detected and then continues counting until
the next valid interrupt edge is detected. The counter must only be
reset by the selected POLARITY edge as selected in the respective
interrupt control register. When the interrupt is disabled, the counter
will stop. The counter is a free-running counter and will wrap around
to zero when the max value is reached. The counter is a read only
register and can only be reset to zero by a valid interrupt edge or by
reset.
Reset type: SYSRSn

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3.17.6.8 XINT3CTR Register (Offset = Ah) [Reset = 0000h]

XINT3CTR is shown in Figure 3-76 and described in Table 3-81.
Return to the Summary Table.
XINT3 counter register
Figure 3-76. XINT3CTR Register
15 14 13 12 11 10 9 8
INTCTR
R-0h

7 6 5 4 3 2 1 0
INTCTR
R-0h

Table 3-81. XINT3CTR Register Field Descriptions

Bit Field Type Reset Description
15-0 INTCTR R 0h This is a free running 16-bit up-counter that is clocked at the
SYSCLKOUT rate. The counter value is reset to 0x0000 when a
valid interrupt edge is detected and then continues counting until
the next valid interrupt edge is detected. The counter must only be
reset by the selected POLARITY edge as selected in the respective
interrupt control register. When the interrupt is disabled, the counter
will stop. The counter is a free-running counter and will wrap around
to zero when the max value is reached. The counter is a read only
register and can only be reset to zero by a valid interrupt edge or by
reset.
Reset type: SYSRSn

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3.17.7 SYNC_SOC_REGS Registers

Table 3-82 lists the memory-mapped registers for the SYNC_SOC_REGS registers. All register offset addresses
not listed in Table 3-82 should be considered as reserved locations and the register contents should not be
modified.
Table 3-82. SYNC_SOC_REGS Registers
Offset Acronym Register Name Write Protection Section
0h SYNCSELECT Sync Input and Output Select Register EALLOW Go
2h ADCSOCOUTSELECT External ADC (Off Chip) SOC Select Register EALLOW Go
4h SYNCSOCLOCK SYNCSEL and EXTADCSOC Select Lock register EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 3-83 shows the codes that are used for
access types in this section.
Table 3-83. SYNC_SOC_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
WSonce W Write
Sonce Set once
Reset or Default Value
-n Value after reset or the default value
Register Array Variables
i,j,k,l,m,n When these variables are used in a register name,
an offset, or an address, they refer to the value of a
register array where the register is part of a group
of repeating registers. The register groups form a
hierarchical structure and the array is represented
with a formula.
y When this variable is used in a register name, an
offset, or an address it refers to the value of a
register array.

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3.17.7.1 SYNCSELECT Register (Offset = 0h) [Reset = 00000000h]

SYNCSELECT is shown in Figure 3-77 and described in Table 3-84.
Return to the Summary Table.
Sync Input and Output Select Register
Figure 3-77. SYNCSELECT Register
31 30 29 28 27 26 25 24
RESERVED SYNCOUT RESERVED
R-0-0h R/W-0h R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED ECAP4SYNCIN ECAP1SYNCIN EPWM10SYNC
IN
R-0-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
EPWM10SYNCIN EPWM7SYNCIN EPWM4SYNCIN
R/W-0h R/W-0h R/W-0h

Table 3-84. SYNCSELECT Register Field Descriptions

Bit Field Type Reset Description
31-29 RESERVED R-0 0h Reserved
28-27 SYNCOUT R/W 0h Select Syncout Source:
00: EPWM1SYNCOUT selected
01: EPWM4SYNCOUT selected
10: EPWM7SYNCOUT selected
11: EPWM10SYNCOUT selected
Reset type: CPU1.SYSRSn
26-16 RESERVED R-0 0h Reserved
15 RESERVED R-0 0h Reserved
14-12 ECAP4SYNCIN R/W 0h Selects Sync Input Source for ECAP4:
000: EPWM1SYNCOUT selected
001: EPWM4SYNCOUT selected
010: EPWM7SYNCOUT selected
011: EPWM10SYNCOUT selected
100: ECAP1SYNCOUT selected
101: EXTSYNCIN1 selected
110: EXTSYNCIN2 selected
111: Reserved
Notes:
[1] Reserved position defaults to 000 selection
Reset type: CPU1.SYSRSn

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Table 3-84. SYNCSELECT Register Field Descriptions (continued)

Bit Field Type Reset Description
11-9 ECAP1SYNCIN R/W 0h Selects Sync Input Source for ECAP1:
000: EPWM1SYNCOUT selected
001: EPWM4SYNCOUT selected
010: EPWM7SYNCOUT selected
011: EPWM10SYNCOUT selected
100: ECAP1SYNCOUT selected (Reserved)
101: EXTSYNCIN1 selected
110: EXTSYNCIN2 selected
111: Reserved
Notes:
[1] Reserved position defaults to 000 selection
Reset type: CPU1.SYSRSn
8-6 EPWM10SYNCIN R/W 0h Selects Sync Input Source for EPWM10:
000: EPWM1SYNCOUT selected
001: EPWM4SYNCOUT selected
010: EPWM7SYNCOUT selected
011: EPWM10SYNCOUT selected (Reserved)
100: ECAP1SYNCOUT selected (Reserved)
101: EXTSYNCIN1 selected
110: EXTSYNCIN2 selected
111: Reserved
Notes:
[1] Reserved position defaults to 000 selection
Reset type: CPU1.SYSRSn
5-3 EPWM7SYNCIN R/W 0h Selects Sync Input Source for EPWM7:
000: EPWM1SYNCOUT selected
001: EPWM4SYNCOUT selected
010: EPWM7SYNCOUT selected (Reserved)
011: EPWM10SYNCOUT selected (Reserved)
100: ECAP1SYNCOUT selected (Reserved)
101: EXTSYNCIN1 selected
110: EXTSYNCIN2 selected
111: Reserved
Notes:
[1] Reserved position defaults to 000 selection
Reset type: CPU1.SYSRSn
2-0 EPWM4SYNCIN R/W 0h Selects Sync Input Source for EPWM4:
000: EPWM1SYNCOUT selected
001: EPWM4SYNCOUT selected (Reserved)
010: EPWM7SYNCOUT selected (Reserved)
011: EPWM10SYNCOUT selected (Reserved)
100: ECAP1SYNCOUT selected (Reserved)
101: EXTSYNCIN1 selected
110: EXTSYNCIN2 selected
111: Reserved
Notes:
[1] Reserved position defaults to 000 selection
Reset type: CPU1.SYSRSn

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3.17.7.2 ADCSOCOUTSELECT Register (Offset = 2h) [Reset = 00000000h]

ADCSOCOUTSELECT is shown in Figure 3-78 and described in Table 3-85.
Return to the Summary Table.
The ADCSOCAO and ADCSOCBO signals will be active low for 32 SYSCLK cycles. They can be used to trigger
a conversion on an external ADC.
Figure 3-78. ADCSOCOUTSELECT Register
31 30 29 28 27 26 25 24
RESERVED PWM12SOCBE PWM11SOCBE PWM10SOCBE PWM9SOCBEN
N N N
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
PWM8SOCBEN PWM7SOCBEN PWM6SOCBEN PWM5SOCBEN PWM4SOCBEN PWM3SOCBEN PWM2SOCBEN PWM1SOCBEN
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED PWM12SOCAE PWM11SOCAE PWM10SOCAE PWM9SOCAEN
N N N
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
PWM8SOCAEN PWM7SOCAEN PWM6SOCAEN PWM5SOCAEN PWM4SOCAEN PWM3SOCAEN PWM2SOCAEN PWM1SOCAEN
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-85. ADCSOCOUTSELECT Register Field Descriptions

Bit Field Type Reset Description
31-28 RESERVED R-0 0h Reserved
27 PWM12SOCBEN R/W 0h ADCSOCBO source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn
26 PWM11SOCBEN R/W 0h ADCSOCBO source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn
25 PWM10SOCBEN R/W 0h ADCSOCBO source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn
24 PWM9SOCBEN R/W 0h ADCSOCBO source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn
23 PWM8SOCBEN R/W 0h ADCSOCBO source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn
22 PWM7SOCBEN R/W 0h ADCSOCBO source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn

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Table 3-85. ADCSOCOUTSELECT Register Field Descriptions (continued)

Bit Field Type Reset Description
21 PWM6SOCBEN R/W 0h ADCSOCBO source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn
20 PWM5SOCBEN R/W 0h ADCSOCBO source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn
19 PWM4SOCBEN R/W 0h ADCSOCBO source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn
18 PWM3SOCBEN R/W 0h ADCSOCBO source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn
17 PWM2SOCBEN R/W 0h ADCSOCBO source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn
16 PWM1SOCBEN R/W 0h ADCSOCBO source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn
15-12 RESERVED R-0 0h Reserved
11 PWM12SOCAEN R/W 0h ADCSOCAO source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn
10 PWM11SOCAEN R/W 0h ADCSOCAO source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn
9 PWM10SOCAEN R/W 0h ADCSOCAO source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn
8 PWM9SOCAEN R/W 0h ADCSOCAO source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn
7 PWM8SOCAEN R/W 0h ADCSOCAO source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn
6 PWM7SOCAEN R/W 0h ADCSOCAO source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn
5 PWM6SOCAEN R/W 0h ADCSOCAO source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn

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Table 3-85. ADCSOCOUTSELECT Register Field Descriptions (continued)

Bit Field Type Reset Description
4 PWM5SOCAEN R/W 0h ADCSOCAO source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn
3 PWM4SOCAEN R/W 0h ADCSOCAO source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn
2 PWM3SOCAEN R/W 0h ADCSOCAO source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn
1 PWM2SOCAEN R/W 0h ADCSOCAO source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn
0 PWM1SOCAEN R/W 0h ADCSOCAO source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn

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3.17.7.3 SYNCSOCLOCK Register (Offset = 4h) [Reset = 00000000h]

SYNCSOCLOCK is shown in Figure 3-79 and described in Table 3-86.
Return to the Summary Table.
SYNCSEL and EXTADCSOC Select Lock register
Figure 3-79. SYNCSOCLOCK Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED ADCSOCOUTS SYNCSELECT
ELECT
R-0-0h R/WSonce-0h R/WSonce-0h

Table 3-86. SYNCSOCLOCK Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-2 RESERVED R-0 0h Reserved
1 ADCSOCOUTSELECT R/WSonce 0h ADCSOCOUTSELECT Register Lock bit:
0: Respective register is not locked
1: Respective register is locked.
Notes:
[1] Any bit in this register, once set can only be creaed through a
CPU1.SYSRSn. Write of 0 to any bit of this regtister has no effect
[2] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed
Reset type: CPU1.SYSRSn
0 SYNCSELECT R/WSonce 0h SYNCSELECT Register Lock bit:
0: Respective register is not locked
1: Respective register is locked.
Notes:
[1] Any bit in this register, once set can only be creaed through a
CPU1.SYSRSn. Write of 0 to any bit of this regtister has no effect
[2] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed
Reset type: CPU1.SYSRSn

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3.17.8 DMA_CLA_SRC_SEL_REGS Registers

Table 3-87 lists the memory-mapped registers for the DMA_CLA_SRC_SEL_REGS registers. All register offset
addresses not listed in Table 3-87 should be considered as reserved locations and the register contents should
not be modified.
Table 3-87. DMA_CLA_SRC_SEL_REGS Registers
Offset Acronym Register Name Write Protection Section
0h CLA1TASKSRCSELLOCK CLA1 Task Trigger Source Select Lock Register EALLOW Go
4h DMACHSRCSELLOCK DMA Channel Triger Source Select Lock Register EALLOW Go
6h CLA1TASKSRCSEL1 CLA1 Task Trigger Source Select Register-1 EALLOW Go
8h CLA1TASKSRCSEL2 CLA1 Task Trigger Source Select Register-2 EALLOW Go
16h DMACHSRCSEL1 DMA Channel Trigger Source Select Register-1 EALLOW Go
18h DMACHSRCSEL2 DMA Channel Trigger Source Select Register-2 EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 3-88 shows the codes that are used for
access types in this section.
Table 3-88. DMA_CLA_SRC_SEL_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
WSonce W Write
Sonce Set once
Reset or Default Value
-n Value after reset or the default value
Register Array Variables
i,j,k,l,m,n When these variables are used in a register name,
an offset, or an address, they refer to the value of a
register array where the register is part of a group
of repeating registers. The register groups form a
hierarchical structure and the array is represented
with a formula.
y When this variable is used in a register name, an
offset, or an address it refers to the value of a
register array.

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3.17.8.1 CLA1TASKSRCSELLOCK Register (Offset = 0h) [Reset = 00000000h]

CLA1TASKSRCSELLOCK is shown in Figure 3-80 and described in Table 3-89.
Return to the Summary Table.
CLA1 Task Trigger Source Select Lock Register
Figure 3-80. CLA1TASKSRCSELLOCK Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED CLA1TASKSRC CLA1TASKSRC
SEL2 SEL1
R-0-0h R/WSonce-0h R/WSonce-0h

Table 3-89. CLA1TASKSRCSELLOCK Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-2 RESERVED R-0 0h Reserved
1 CLA1TASKSRCSEL2 R/WSonce 0h CLA1TASKSRCSEL2 Register Lock bit:
0: Respective register is not locked
1: Respective register is locked.
Notes:
[1] Any SOnce bit in this register, once set can only be cleared
through a SYSRSn. Write of 0 to any bit of this register has no effect
[2] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed
Reset type: SYSRSn
0 CLA1TASKSRCSEL1 R/WSonce 0h CLA1TASKSRCSEL1 Register Lock bit:
0: Respective register is not locked
1: Respective register is locked.
Notes:
[1] Any SOnce bit in this register, once set can only be cleared
through a SYSRSn. Write of 0 to any bit of this register has no effect
[2] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed
Reset type: SYSRSn

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3.17.8.2 DMACHSRCSELLOCK Register (Offset = 4h) [Reset = 00000000h]

DMACHSRCSELLOCK is shown in Figure 3-81 and described in Table 3-90.
Return to the Summary Table.
DMA Channel Triger Source Select Lock Register
Figure 3-81. DMACHSRCSELLOCK Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMACHSRCSE DMACHSRCSE
L2 L1
R-0-0h R/WSonce-0h R/WSonce-0h

Table 3-90. DMACHSRCSELLOCK Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-2 RESERVED R-0 0h Reserved
1 DMACHSRCSEL2 R/WSonce 0h DMACHSRCSEL2 Register Lock bit:
0: Respective register is not locked
1: Respective register is locked.
Notes:
[1] Any SOnce bit in this register, once set can only be cleared
through a SYSRSn. Write of 0 to any bit of this register has no effect
[2] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed
Reset type: SYSRSn
0 DMACHSRCSEL1 R/WSonce 0h DMACHSRCSEL1 Register Lock bit:
0: Respective register is not locked
1: Respective register is locked.
Notes:
[1] Any SOnce bit in this register, once set can only be cleared
through a SYSRSn. Write of 0 to any bit of this register has no effect
[2] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed
Reset type: SYSRSn

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3.17.8.3 CLA1TASKSRCSEL1 Register (Offset = 6h) [Reset = 00000000h]

CLA1TASKSRCSEL1 is shown in Figure 3-82 and described in Table 3-91.
Return to the Summary Table.
CLA1 Task Trigger Source Select Register-1
Figure 3-82. CLA1TASKSRCSEL1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TASK4 TASK3 TASK2 TASK1
R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-91. CLA1TASKSRCSEL1 Register Field Descriptions

Bit Field Type Reset Description
31-24 TASK4 R/W 0h Selects the Trigger Source for TASK4 of CLA1
Reset type: SYSRSn
23-16 TASK3 R/W 0h Selects the Trigger Source for TASK3 of CLA1
Reset type: SYSRSn
15-8 TASK2 R/W 0h Selects the Trigger Source for TASK2 of CLA1
Reset type: SYSRSn
7-0 TASK1 R/W 0h Selects the Trigger Source for TASK1 of CLA1
Reset type: SYSRSn

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3.17.8.4 CLA1TASKSRCSEL2 Register (Offset = 8h) [Reset = 00000000h]

CLA1TASKSRCSEL2 is shown in Figure 3-83 and described in Table 3-92.
Return to the Summary Table.
CLA1 Task Trigger Source Select Register-2
Figure 3-83. CLA1TASKSRCSEL2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TASK8 TASK7 TASK6 TASK5
R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-92. CLA1TASKSRCSEL2 Register Field Descriptions

Bit Field Type Reset Description
31-24 TASK8 R/W 0h Selects the Trigger Source for TASK8 of CLA1
Reset type: SYSRSn
23-16 TASK7 R/W 0h Selects the Trigger Source for TASK7 of CLA1
Reset type: SYSRSn
15-8 TASK6 R/W 0h Selects the Trigger Source for TASK6 of CLA1
Reset type: SYSRSn
7-0 TASK5 R/W 0h Selects the Trigger Source for TASK5 of CLA1
Reset type: SYSRSn

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3.17.8.5 DMACHSRCSEL1 Register (Offset = 16h) [Reset = 00000000h]

DMACHSRCSEL1 is shown in Figure 3-84 and described in Table 3-93.
Return to the Summary Table.
DMA Channel Trigger Source Select Register-1
Figure 3-84. DMACHSRCSEL1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH4 CH3 CH2 CH1
R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-93. DMACHSRCSEL1 Register Field Descriptions

Bit Field Type Reset Description
31-24 CH4 R/W 0h Selects the Trigger and Sync Source CH4 of DMA
Reset type: SYSRSn
23-16 CH3 R/W 0h Selects the Trigger and Sync Source CH3 of DMA
Reset type: SYSRSn
15-8 CH2 R/W 0h Selects the Trigger and Sync Source CH2 of DMA
Reset type: SYSRSn
7-0 CH1 R/W 0h Selects the Trigger and Sync Source CH1 of DMA
Reset type: SYSRSn

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3.17.8.6 DMACHSRCSEL2 Register (Offset = 18h) [Reset = 00000000h]

DMACHSRCSEL2 is shown in Figure 3-85 and described in Table 3-94.
Return to the Summary Table.
DMA Channel Trigger Source Select Register-2
Figure 3-85. DMACHSRCSEL2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED CH6 CH5
R-0-0h R/W-0h R/W-0h

Table 3-94. DMACHSRCSEL2 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-8 CH6 R/W 0h Selects the Trigger and Sync Source CH6 of DMA
Reset type: SYSRSn
7-0 CH5 R/W 0h Selects the Trigger and Sync Source CH5 of DMA
Reset type: SYSRSn

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3.17.9 FLASH_PUMP_SEMAPHORE_REGS Registers

Table 3-95 lists the memory-mapped registers for the FLASH_PUMP_SEMAPHORE_REGS registers. All
register offset addresses not listed in Table 3-95 should be considered as reserved locations and the register
contents should not be modified.
Table 3-95. FLASH_PUMP_SEMAPHORE_REGS Registers
Offset Acronym Register Name Write Protection Section
0h PUMPREQUEST Flash programming semaphore PUMP request EALLOW Go
register

Complex bit access types are encoded to fit into small table cells. Table 3-96 shows the codes that are used for
access types in this section.
Table 3-96. FLASH_PUMP_SEMAPHORE_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default value
Register Array Variables
i,j,k,l,m,n When these variables are used in a register name,
an offset, or an address, they refer to the value of a
register array where the register is part of a group
of repeating registers. The register groups form a
hierarchical structure and the array is represented
with a formula.
y When this variable is used in a register name, an
offset, or an address it refers to the value of a
register array.

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3.17.9.1 PUMPREQUEST Register (Offset = 0h) [Reset = 00000000h]

PUMPREQUEST is shown in Figure 3-86 and described in Table 3-97.
Return to the Summary Table.
Flash programming semaphore PUMP request register
Figure 3-86. PUMPREQUEST Register
31 30 29 28 27 26 25 24
KEY
R-0/W-0h

23 22 21 20 19 18 17 16
KEY
R-0/W-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED PUMP_OWNERSHIP
R-0-0h R/W-0h

Table 3-97. PUMPREQUEST Register Field Descriptions

Bit Field Type Reset Description
31-16 KEY R-0/W 0h In order to write to the semaphore bits, 0x5a5a must be written to
these key bits at the same time. Otherwise, writes are ignored. The
key is cleared immediately after writing, so it must be written again
for every semaphore change.
Reset type: CPU1.SYSRSn
15-2 RESERVED R-0 0h Reserved
1-0 PUMP_OWNERSHIP R/W 0h These bits configure which CPU has control of the flash pump, which
allows write access to the flash memory. The possible values are:
00 or 11: Read-only state. CPU1 has control of the pump, but CPU2
may seize control at any time.
01: CPU2 has exclusive control of the pump and of these semaphore
bits. CPU2 can relinquish control by setting the bits back to 00 or 11.
10: CPU1 has exclusive control of the pump and of these semaphore
bits. CPU1 can relinquish control by setting the bits back to 00 or 11.
Going from 01->10 or 10->01 is not allowed. Going from 00->11 or
11->00 is allowed, but has no effect. The semaphore bits [1:0] must
be written along with the correct key in bits [31:16].
Reset type: CPU1.SYSRSn

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3.17.10 DEV_CFG_REGS Registers

Table 3-98 lists the memory-mapped registers for the DEV_CFG_REGS registers. All register offset addresses
not listed in Table 3-98 should be considered as reserved locations and the register contents should not be
modified.
Table 3-98. DEV_CFG_REGS Registers
Offset Acronym Register Name Write Protection Section
0h DEVCFGLOCK1 Lock bit for CPUSELx registers EALLOW Go
8h PARTIDL Lower 32-bit of Device PART Identification Go
Number
Ah PARTIDH Upper 32-bit of Device PART Identification Go
Number
Ch REVID Device Revision Number Go
10h DC0 Device Capability: Device Information Go
12h DC1 Device Capability: Processing Block Go
Customization
14h DC2 Device Capability: EMIF Customization Go
16h DC3 Device Capability: Peripheral Customization Go
18h DC4 Device Capability: Peripheral Customization Go
1Ah DC5 Device Capability: Peripheral Customization Go
1Ch DC6 Device Capability: Peripheral Customization Go
1Eh DC7 Device Capability: Peripheral Customization Go
20h DC8 Device Capability: Peripheral Customization Go
22h DC9 Device Capability: Peripheral Customization Go
24h DC10 Device Capability: Peripheral Customization Go
26h DC11 Device Capability: Peripheral Customization Go
28h DC12 Device Capability: Peripheral Customization Go
2Ah DC13 Device Capability: Peripheral Customization Go
2Ch DC14 Device Capability: Analog Modules Customization Go
2Eh DC15 Device Capability: Analog Modules Customization Go
32h DC17 Device Capability: Analog Modules Customization Go
34h DC18 Device Capability: CPU1 Lx SRAM Customization Go
36h DC19 Device Capability: CPU2 Lx SRAM Customization Go
38h DC20 Device Capability: GSx SRAM Customization Go
60h PERCNF1 Peripheral Configuration register Go
74h FUSEERR e-Fuse error Status register Go
82h SOFTPRES0 Processing Block Software Reset register EALLOW Go
84h SOFTPRES1 EMIF Software Reset register EALLOW Go
86h SOFTPRES2 Peripheral Software Reset register EALLOW Go
88h SOFTPRES3 Peripheral Software Reset register EALLOW Go
8Ah SOFTPRES4 Peripheral Software Reset register EALLOW Go
8Eh SOFTPRES6 Peripheral Software Reset register EALLOW Go
90h SOFTPRES7 Peripheral Software Reset register EALLOW Go
92h SOFTPRES8 Peripheral Software Reset register EALLOW Go
94h SOFTPRES9 Peripheral Software Reset register EALLOW Go
98h SOFTPRES11 Peripheral Software Reset register EALLOW Go
9Ch SOFTPRES13 Peripheral Software Reset register EALLOW Go
9Eh SOFTPRES14 Peripheral Software Reset register EALLOW Go

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Table 3-98. DEV_CFG_REGS Registers (continued)

Offset Acronym Register Name Write Protection Section
A2h SOFTPRES16 Peripheral Software Reset register EALLOW Go
D6h CPUSEL0 CPU Select register for common peripherals EALLOW Go
D8h CPUSEL1 CPU Select register for common peripherals EALLOW Go
DAh CPUSEL2 CPU Select register for common peripherals EALLOW Go
DCh CPUSEL3 CPU Select register for common peripherals EALLOW Go
DEh CPUSEL4 CPU Select register for common peripherals EALLOW Go
E0h CPUSEL5 CPU Select register for common peripherals EALLOW Go
E2h CPUSEL6 CPU Select register for common peripherals EALLOW Go
E4h CPUSEL7 CPU Select register for common peripherals EALLOW Go
E6h CPUSEL8 CPU Select register for common peripherals EALLOW Go
E8h CPUSEL9 CPU Select register for common peripherals EALLOW Go
ECh CPUSEL11 CPU Select register for common peripherals EALLOW Go
EEh CPUSEL12 CPU Select register for common peripherals EALLOW Go
F2h CPUSEL14 CPU Select register for common peripherals EALLOW Go
122h CPU2RESCTL CPU2 Reset Control Register EALLOW Go
124h RSTSTAT Reset Status register for secondary C28x CPUs Go
125h LPMSTAT LPM Status Register for secondary C28x CPUs Go
12Ch SYSDBGCTL System Debug Control register EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 3-99 shows the codes that are used for
access types in this section.
Table 3-99. DEV_CFG_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1S W Write
1S 1 to set
WOnce W Write
Once Write once
WSonce W Write
Sonce Set once
Reset or Default Value
-n Value after reset or the default value
Register Array Variables
i,j,k,l,m,n When these variables are used in a register name,
an offset, or an address, they refer to the value of a
register array where the register is part of a group
of repeating registers. The register groups form a
hierarchical structure and the array is represented
with a formula.
y When this variable is used in a register name, an
offset, or an address it refers to the value of a
register array.

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3.17.10.1 DEVCFGLOCK1 Register (Offset = 0h) [Reset = 00000000h]

DEVCFGLOCK1 is shown in Figure 3-87 and described in Table 3-100.
Return to the Summary Table.
Lock bit for CPUSELx registers
The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are always
allowed
Note:
Any SOnce bit in this register, once set can only be cleared through a CPU1.SYSRSn. Write of 0 to any bit of
this register has no effect
Figure 3-87. DEVCFGLOCK1 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED CPUSEL14 CPUSEL13 CPUSEL12 CPUSEL11 CPUSEL10 CPUSEL9 CPUSEL8
R-0-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

7 6 5 4 3 2 1 0
CPUSEL7 CPUSEL6 CPUSEL5 CPUSEL4 CPUSEL3 CPUSEL2 CPUSEL1 CPUSEL0
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

Table 3-100. DEVCFGLOCK1 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15 RESERVED R-0 0h Reserved
14 CPUSEL14 R/WSonce 0h Lock bit for CPUSEL14 register:
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn
13 CPUSEL13 R/WSonce 0h Lock bit for CPUSEL13 register:
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn
12 CPUSEL12 R/WSonce 0h Lock bit for CPUSEL12 register:
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn
11 CPUSEL11 R/WSonce 0h Lock bit for CPUSEL11 register:
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn
10 CPUSEL10 R/WSonce 0h Lock bit for CPUSEL10 register:
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn

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Table 3-100. DEVCFGLOCK1 Register Field Descriptions (continued)

Bit Field Type Reset Description
9 CPUSEL9 R/WSonce 0h Lock bit for CPUSEL9 register:
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn
8 CPUSEL8 R/WSonce 0h Lock bit for CPUSEL8 register:
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn
7 CPUSEL7 R/WSonce 0h Lock bit for CPUSEL7 register:
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn
6 CPUSEL6 R/WSonce 0h Lock bit for CPUSEL6 register:
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn
5 CPUSEL5 R/WSonce 0h Lock bit for CPUSEL5 register:
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn
4 CPUSEL4 R/WSonce 0h Lock bit for CPUSEL4 register:
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn
3 CPUSEL3 R/WSonce 0h Lock bit for CPUSEL3 register:
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn
2 CPUSEL2 R/WSonce 0h Lock bit for CPUSEL2 register:
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn
1 CPUSEL1 R/WSonce 0h Lock bit for CPUSEL1 register:
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn
0 CPUSEL0 R/WSonce 0h Lock bit for CPUSEL0 register:
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn

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3.17.10.2 PARTIDL Register (Offset = 8h) [Reset = 00000000h]

PARTIDL is shown in Figure 3-88 and described in Table 3-101.
Return to the Summary Table.
Lower 32-bit of Device PART Identification Number
Figure 3-88. PARTIDL Register
31 30 29 28 27 26 25 24
PARTID_FORMAT_REVISION RESERVED
R-0h R-0h

23 22 21 20 19 18 17 16
FLASH_SIZE
R-0h

15 14 13 12 11 10 9 8
RESERVED INSTASPIN RESERVED RESERVED PIN_COUNT
R-0h R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
QUAL RESERVED RESERVED RESERVED
R-0h R-0h R-0h R-0h

Table 3-101. PARTIDL Register Field Descriptions

Bit Field Type Reset Description
31-28 PARTID_FORMAT_REVIS R 0h Revision of the PARTID format
ION Reset type: XRSn
27-24 RESERVED R 0h Reserved
23-16 FLASH_SIZE R 0h 0x7 - 512KB
0x6 - 256KB
Note: This field shows flash size on CPU1 (see datasheet for flash
size available)
Reset type: XRSn
15 RESERVED R 0h Reserved
14-13 INSTASPIN R 0h 0 = Reserved for future
1 = Reserved for future
2 = Reserved for future
3 = NONE
Reset type: XRSn
12 RESERVED R 0h Reserved
11 RESERVED R 0h Reserved
10-8 PIN_COUNT R 0h 0 = reserved for future
1 = reserved for future
2 = reserved for future
3 = reserved for future
4 = reserved for future
5 = 100 pin
6 = 176 pin
7 = 337 pin
Reset type: XRSn
7-6 QUAL R 0h 0 = Engineering sample.(TMX)
1 = Pilot production (TMP)
2 = Fully qualified (TMS)
Reset type: XRSn
5 RESERVED R 0h Reserved
4-3 RESERVED R 0h Reserved

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Table 3-101. PARTIDL Register Field Descriptions (continued)

Bit Field Type Reset Description
2-0 RESERVED R 0h Reserved

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3.17.10.3 PARTIDH Register (Offset = Ah) [Reset = 00000000h]

PARTIDH is shown in Figure 3-89 and described in Table 3-102.
Return to the Summary Table.
Upper 32-bit of Device PART Identification Number
Figure 3-89. PARTIDH Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DEVICE_CLASS_ID PARTNO
R-0h R-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FAMILY RESERVED
R-0h R-0h

Table 3-102. PARTIDH Register Field Descriptions

Bit Field Type Reset Description
31-24 DEVICE_CLASS_ID R 0h Reserved
Reset type: XRSn
23-16 PARTNO R 0h Refer to Datasheet for Device Part Number
Reset type: XRSn
15-8 FAMILY R 0h Device Family
0x3 - DUAL CORE
0x4 - SINGLE CORE
0x5 - PICCOLO SINGLE CORE
Other values Reserved
Reset type: XRSn
7-0 RESERVED R 0h Reserved

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3.17.10.4 REVID Register (Offset = Ch) [Reset = 00000000h]

REVID is shown in Figure 3-90 and described in Table 3-103.
Return to the Summary Table.
Device Revision Number
Figure 3-90. REVID Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REVID
R-0h

Table 3-103. REVID Register Field Descriptions

Bit Field Type Reset Description
31-0 REVID R 0h These 32-bits specify the silicon revision. See your device specific
datasheet for details.
Reset type: N/A

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3.17.10.5 DC0 Register (Offset = 10h) [Reset = 0000000Xh]

DC0 is shown in Figure 3-91 and described in Table 3-104.
Return to the Summary Table.
Device Capability: Device Information
Figure 3-91. DC0 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED SINGLE_CORE
R-0-0h R-X

Table 3-104. DC0 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-1 RESERVED R-0 0h Reserved
0 SINGLE_CORE R X Single Core vs Dual Core
0: Single Core
1: Dual Core
Reset type: XRSn

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3.17.10.6 DC1 Register (Offset = 12h) [Reset = 00000XXXh]

DC1 is shown in Figure 3-92 and described in Table 3-105.
Return to the Summary Table.
Device Capability: Processing Block Customization
Figure 3-92. DC1 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED CPU2_CLA1
R-0-0h R-X R-X

7 6 5 4 3 2 1 0
RESERVED CPU1_CLA1 RESERVED CPU2_VCU CPU1_VCU CPU2_FPU_TM CPU1_FPU_TM
U U
R-X R-X R-0-0h R-X R-X R-X R-X

Table 3-105. DC1 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-10 RESERVED R-0 0h Reserved
9 RESERVED R X Reserved
8 CPU2_CLA1 R X 0 - feature is not present on this device
1 - feature is present on this device
Reset type: XRSn
7 RESERVED R X Reserved
6 CPU1_CLA1 R X 0 - feature is not present on this device
1 - feature is present on this device
Reset type: XRSn
5-4 RESERVED R-0 0h Reserved
3 CPU2_VCU R X 0 - feature is not present on this device
1 - feature is present on this device
Reset type: XRSn
2 CPU1_VCU R X 0 - feature is not present on this device
1 - feature is present on this device
Reset type: XRSn
1 CPU2_FPU_TMU R X 0 - feature is not present on this device
1 - feature is present on this device
Reset type: XRSn
0 CPU1_FPU_TMU R X 0 - feature is not present on this device
1 - feature is present on this device
Reset type: XRSn

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3.17.10.7 DC2 Register (Offset = 14h) [Reset = 0000000Xh]

DC2 is shown in Figure 3-93 and described in Table 3-106.
Return to the Summary Table.
Device Capability: EMIF Customization
Figure 3-93. DC2 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED EMIF2 EMIF1
R-0-0h R-X R-X

Table 3-106. DC2 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-2 RESERVED R-0 0h Reserved
1 EMIF2 R X EMIF2 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
0 EMIF1 R X EMIF1 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

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3.17.10.8 DC3 Register (Offset = 16h) [Reset = 0000XXXXh]

DC3 is shown in Figure 3-94 and described in Table 3-107.
Return to the Summary Table.
Device Capability: Peripheral Customization
Figure 3-94. DC3 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED EPWM12 EPWM11 EPWM10 EPWM9
R-X R-X R-X R-X R-X R-X R-X R-X

7 6 5 4 3 2 1 0
EPWM8 EPWM7 EPWM6 EPWM5 EPWM4 EPWM3 EPWM2 EPWM1
R-X R-X R-X R-X R-X R-X R-X R-X

Table 3-107. DC3 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15 RESERVED R X Reserved
14 RESERVED R X Reserved
13 RESERVED R X Reserved
12 RESERVED R X Reserved
11 EPWM12 R X EPWM12 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
10 EPWM11 R X EPWM11 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
9 EPWM10 R X EPWM10 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
8 EPWM9 R X EPWM9 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
7 EPWM8 R X EPWM8 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
6 EPWM7 R X EPWM7 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

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Table 3-107. DC3 Register Field Descriptions (continued)

Bit Field Type Reset Description
5 EPWM6 R X EPWM6 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
4 EPWM5 R X EPWM5 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
3 EPWM4 R X EPWM4 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
2 EPWM3 R X EPWM3 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
1 EPWM2 R X EPWM2 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
0 EPWM1 R X EPWM1 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

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3.17.10.9 DC4 Register (Offset = 18h) [Reset = 000000XXh]

DC4 is shown in Figure 3-95 and described in Table 3-108.
Return to the Summary Table.
Device Capability: Peripheral Customization
Figure 3-95. DC4 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED ECAP6 ECAP5 ECAP4 ECAP3 ECAP2 ECAP1
R-X R-X R-X R-X R-X R-X R-X R-X

Table 3-108. DC4 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-8 RESERVED R-0 0h Reserved
7 RESERVED R X Reserved
6 RESERVED R X Reserved
5 ECAP6 R X ECAP6 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
4 ECAP5 R X ECAP5 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
3 ECAP4 R X ECAP4 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
2 ECAP3 R X ECAP3 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
1 ECAP2 R X ECAP2 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
0 ECAP1 R X ECAP1 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

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3.17.10.10 DC5 Register (Offset = 1Ah) [Reset = 0000000Xh]

DC5 is shown in Figure 3-96 and described in Table 3-109.
Return to the Summary Table.
Device Capability: Peripheral Customization
Figure 3-96. DC5 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED EQEP3 EQEP2 EQEP1
R-0-0h R-X R-X R-X R-X

Table 3-109. DC5 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-4 RESERVED R-0 0h Reserved
3 RESERVED R X Reserved
2 EQEP3 R X EQEP3 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
1 EQEP2 R X EQEP2 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
0 EQEP1 R X EQEP1 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

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3.17.10.11 DC6 Register (Offset = 1Ch) [Reset = 000000XXh]

DC6 is shown in Figure 3-97 and described in Table 3-110.
Return to the Summary Table.
Device Capability: Peripheral Customization
Figure 3-97. DC6 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED CLB4 CLB3 CLB2 CLB1
R-X R-X R-X R-X R-X R-X R-X R-X

Table 3-110. DC6 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-8 RESERVED R-0 0h Reserved
7 RESERVED R X Reserved
6 RESERVED R X Reserved
5 RESERVED R X Reserved
4 RESERVED R X Reserved
3 CLB4 R X CLB4 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
2 CLB3 R X CLB3 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
1 CLB2 R X CLB2 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
0 CLB1 R X CLB1 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

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3.17.10.12 DC7 Register (Offset = 1Eh) [Reset = 000000XXh]

DC7 is shown in Figure 3-98 and described in Table 3-111.
Return to the Summary Table.
Device Capability: Peripheral Customization
Figure 3-98. DC7 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RESE RESE RESE RESE RESE RESE SD2 SD1
RVED RVED RVED RVED RVED RVED
R-0-0h R-X R-X R-X R-X R-X R-X R-X R-X

Table 3-111. DC7 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-8 RESERVED R-0 0h Reserved
7 RESERVED R X Reserved
6 RESERVED R X Reserved
5 RESERVED R X Reserved
4 RESERVED R X Reserved
3 RESERVED R X Reserved
2 RESERVED R X Reserved
1 SD2 R X SD2 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
0 SD1 R X SD1 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

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3.17.10.13 DC8 Register (Offset = 20h) [Reset = 0000000Xh]

DC8 is shown in Figure 3-99 and described in Table 3-112.
Return to the Summary Table.
Device Capability: Peripheral Customization
Figure 3-99. DC8 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED SCI_D SCI_C SCI_B SCI_A
R-0-0h R-X R-X R-X R-X

Table 3-112. DC8 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-4 RESERVED R-0 0h Reserved
3 SCI_D R X SCI_D :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
2 SCI_C R X SCI_C :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
1 SCI_B R X SCI_B :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
0 SCI_A R X SCI_A :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

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3.17.10.14 DC9 Register (Offset = 22h) [Reset = 000X000Xh]

DC9 is shown in Figure 3-100 and described in Table 3-113.
Return to the Summary Table.
Device Capability: Peripheral Customization
Figure 3-100. DC9 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED
R-0-0h R-X R-X

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED SPI_C SPI_B SPI_A
R-0-0h R-X R-X R-X R-X

Table 3-113. DC9 Register Field Descriptions

Bit Field Type Reset Description
31-18 RESERVED R-0 0h Reserved
17 RESERVED R X Reserved
16 RESERVED R X Reserved
15-4 RESERVED R-0 0h Reserved
3 RESERVED R X Reserved
2 SPI_C R X SPI_C :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
1 SPI_B R X SPI_B :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
0 SPI_A R X SPI_A :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

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3.17.10.15 DC10 Register (Offset = 24h) [Reset = 000X000Xh]

DC10 is shown in Figure 3-101 and described in Table 3-114.
Return to the Summary Table.
Device Capability: Peripheral Customization
Figure 3-101. DC10 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED
R-0-0h R-X R-X

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED I2C_B I2C_A
R-0-0h R-X R-X

Table 3-114. DC10 Register Field Descriptions

Bit Field Type Reset Description
31-18 RESERVED R-0 0h Reserved
17 RESERVED R X Reserved
16 RESERVED R X Reserved
15-2 RESERVED R-0 0h Reserved
1 I2C_B R X I2C_B :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
0 I2C_A R X I2C_A :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

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3.17.10.16 DC11 Register (Offset = 26h) [Reset = 0000000Xh]

DC11 is shown in Figure 3-102 and described in Table 3-115.
Return to the Summary Table.
Device Capability: Peripheral Customization
Figure 3-102. DC11 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED CAN_B CAN_A
R-0-0h R-X R-X R-X R-X

Table 3-115. DC11 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-4 RESERVED R-0 0h Reserved
3 RESERVED R X Reserved
2 RESERVED R X Reserved
1 CAN_B R X CAN_B :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
0 CAN_A R X CAN_A :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

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3.17.10.17 DC12 Register (Offset = 28h) [Reset = 000X000Xh]

DC12 is shown in Figure 3-103 and described in Table 3-116.
Return to the Summary Table.
Device Capability: Peripheral Customization
Figure 3-103. DC12 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED USB_A
R-0-0h R-X R-X

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED McBSP_B McBSP_A
R-0-0h R-X R-X

Table 3-116. DC12 Register Field Descriptions

Bit Field Type Reset Description
31-20 RESERVED R-0 0h Reserved
19-18 RESERVED R X Reserved
17-16 USB_A R X Capability of the USB_A Module:
2'b00: No USB function
2'b01: Device Only
2'b10: Device or Host
2'b11: Device or Host
Reset type: XRSn
15-2 RESERVED R-0 0h Reserved
1 McBSP_B R X McBSP_B :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
0 McBSP_A R X McBSP_A :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

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3.17.10.18 DC13 Register (Offset = 2Ah) [Reset = 0000000Xh]

DC13 is shown in Figure 3-104 and described in Table 3-117.
Return to the Summary Table.
Device Capability: Peripheral Customization
Figure 3-104. DC13 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED uPP_A
R-0-0h R-X R-X

Table 3-117. DC13 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-2 RESERVED R-0 0h Reserved
1 RESERVED R X Reserved
0 uPP_A R X uPP_A :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

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3.17.10.19 DC14 Register (Offset = 2Ch) [Reset = 0000000Xh]

DC14 is shown in Figure 3-105 and described in Table 3-118.
Return to the Summary Table.
Device Capability: Analog Modules Customization
Figure 3-105. DC14 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED ADC_D ADC_C ADC_B ADC_A
R-0-0h R-X R-X R-X R-X

Table 3-118. DC14 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-4 RESERVED R-0 0h Reserved
3 ADC_D R X ADC_D :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
2 ADC_C R X ADC_C :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
1 ADC_B R X ADC_B :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
0 ADC_A R X ADC_A :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

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3.17.10.20 DC15 Register (Offset = 2Eh) [Reset = 000000XXh]

DC15 is shown in Figure 3-106 and described in Table 3-119.
Return to the Summary Table.
Device Capability: Analog Modules Customization
Figure 3-106. DC15 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
CMPSS8 CMPSS7 CMPSS6 CMPSS5 CMPSS4 CMPSS3 CMPSS2 CMPSS1
R-X R-X R-X R-X R-X R-X R-X R-X

Table 3-119. DC15 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-8 RESERVED R-0 0h Reserved
7 CMPSS8 R X CMPSS8 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
6 CMPSS7 R X CMPSS7 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
5 CMPSS6 R X CMPSS6 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
4 CMPSS5 R X CMPSS5 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
3 CMPSS4 R X CMPSS4 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
2 CMPSS3 R X CMPSS3 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
1 CMPSS2 R X CMPSS2 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

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Table 3-119. DC15 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 CMPSS1 R X CMPSS1 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

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3.17.10.21 DC17 Register (Offset = 32h) [Reset = 000X000Xh]

DC17 is shown in Figure 3-107 and described in Table 3-120.
Return to the Summary Table.
Device Capability: Analog Modules Customization
Figure 3-107. DC17 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED DAC_C DAC_B DAC_A
R-0-0h R-X R-X R-X R-X

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED RESERVED
R-0-0h R-X R-X R-X R-X

Table 3-120. DC17 Register Field Descriptions

Bit Field Type Reset Description
31-20 RESERVED R-0 0h Reserved
19 RESERVED R X Reserved
18 DAC_C R X Buffered-DAC_C :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
17 DAC_B R X Buffered-DAC_B :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
16 DAC_A R X Buffered-DAC_A :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
15-4 RESERVED R-0 0h Reserved
3 RESERVED R X Reserved
2 RESERVED R X Reserved
1 RESERVED R X Reserved
0 RESERVED R X Reserved

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3.17.10.22 DC18 Register (Offset = 34h) [Reset = 000000XXh]

DC18 is shown in Figure 3-108 and described in Table 3-121.
Return to the Summary Table.
Device Capability: CPU1 Lx SRAM Customization
Figure 3-108. DC18 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED LS5_1 LS4_1 LS3_1 LS2_1 LS1_1 LS0_1
R-0-0h R-X R-X R-X R-X R-X R-X

Table 3-121. DC18 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-6 RESERVED R-0 0h Reserved
5 LS5_1 R X LS5_1 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
4 LS4_1 R X LS4_1 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
3 LS3_1 R X LS3_1 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
2 LS2_1 R X LS2_1 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
1 LS1_1 R X LS1_1 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
0 LS0_1 R X LS0_1 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

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3.17.10.23 DC19 Register (Offset = 36h) [Reset = 000000XXh]

DC19 is shown in Figure 3-109 and described in Table 3-122.
Return to the Summary Table.
Device Capability: CPU2 Lx SRAM Customization
Figure 3-109. DC19 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED LS5_2 LS4_2 LS3_2 LS2_2 LS1_2 LS0_2
R-0-0h R-X R-X R-X R-X R-X R-X

Table 3-122. DC19 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-6 RESERVED R-0 0h Reserved
5 LS5_2 R X LS5_2 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
4 LS4_2 R X LS4_2 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
3 LS3_2 R X LS3_2 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
2 LS2_2 R X LS2_2 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
1 LS1_2 R X LS1_2 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
0 LS0_2 R X LS0_2 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

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3.17.10.24 DC20 Register (Offset = 38h) [Reset = 0000XXXXh]

DC20 is shown in Figure 3-110 and described in Table 3-123.
Return to the Summary Table.
Device Capability: GSx SRAM Customization
Figure 3-110. DC20 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
GS15 GS14 GS13 GS12 GS11 GS10 GS9 GS8
R-X R-X R-X R-X R-X R-X R-X R-X

7 6 5 4 3 2 1 0
GS7 GS6 GS5 GS4 GS3 GS2 GS1 GS0
R-X R-X R-X R-X R-X R-X R-X R-X

Table 3-123. DC20 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15 GS15 R X GS15 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
14 GS14 R X GS14 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
13 GS13 R X GS13 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
12 GS12 R X GS12 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
11 GS11 R X GS11 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
10 GS10 R X GS10 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
9 GS9 R X GS9 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

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Table 3-123. DC20 Register Field Descriptions (continued)

Bit Field Type Reset Description
8 GS8 R X GS8 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
7 GS7 R X GS7 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
6 GS6 R X GS6 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
5 GS5 R X GS5 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
4 GS4 R X GS4 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
3 GS3 R X GS3 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
2 GS2 R X GS2 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
1 GS1 R X GS1 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
0 GS0 R X GS0 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

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3.17.10.25 PERCNF1 Register (Offset = 60h) [Reset = 000X000Xh]

PERCNF1 is shown in Figure 3-111 and described in Table 3-124.
Return to the Summary Table.
Peripheral Configuration register
Figure 3-111. PERCNF1 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED USB_A_PHY
R-0-0h R-X R-X

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED ADC_D_MODE ADC_C_MODE ADC_B_MODE ADC_A_MODE
R-0-0h R-X R-X R-X R-X

Table 3-124. PERCNF1 Register Field Descriptions

Bit Field Type Reset Description
31-18 RESERVED R-0 0h Reserved
17 RESERVED R X Reserved
16 USB_A_PHY R X Internal PHY is present present or not for the USB_A module:
0: Internal USB PHY Module is not present
1: Internal USB PHY Module is present.
Reset type: XRSn
15-4 RESERVED R-0 0h Reserved
3 ADC_D_MODE R X 0: 16-bit or 12-bit configurable in software
1: Only 12-bit operation available
Reset type: XRSn
2 ADC_C_MODE R X 0: 16-bit or 12-bit configurable in software
1: Only 12-bit operation available
Reset type: XRSn
1 ADC_B_MODE R X 0: 16-bit or 12-bit configurable in software
1: Only 12-bit operation available
Reset type: XRSn
0 ADC_A_MODE R X 0: 16-bit or 12-bit configurable in software
1: Only 12-bit operation available
Reset type: XRSn

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3.17.10.26 FUSEERR Register (Offset = 74h) [Reset = 00000000h]

FUSEERR is shown in Figure 3-112 and described in Table 3-125.
Return to the Summary Table.
e-Fuse error Status register
Figure 3-112. FUSEERR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED ERR ALERR
R-0-0h R-0h R-0h

Table 3-125. FUSEERR Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-6 RESERVED R-0 0h Reserved
5 ERR R 0h Efuse Self Test Error Status set by hardware after fuse self test
completes, in case of self test error
0: No error during fuse self test
1: Fuse self test error
Reset type: XRSn
4-0 ALERR R 0h Efuse Autoload Error Status set by hardware after fuse auto load
completes
00000: No error in auto load
Other: Non zero value indicates error in autoload
Reset type: XRSn

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3.17.10.27 SOFTPRES0 Register (Offset = 82h) [Reset = 00000000h]

SOFTPRES0 is shown in Figure 3-113 and described in Table 3-126.
Return to the Summary Table.
Processing Block Software Reset register
When bits in this register are set, the respective module is in reset. All design data is lost and the module
registers are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-113. SOFTPRES0 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED CPU2_CLA1 RESERVED CPU1_CLA1
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-126. SOFTPRES0 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-4 RESERVED R-0 0h Reserved
3 RESERVED R/W 0h Reserved
2 CPU2_CLA1 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
1 RESERVED R/W 0h Reserved
0 CPU1_CLA1 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

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3.17.10.28 SOFTPRES1 Register (Offset = 84h) [Reset = 00000000h]

SOFTPRES1 is shown in Figure 3-114 and described in Table 3-127.
Return to the Summary Table.
EMIF Software Reset register
Figure 3-114. SOFTPRES1 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED EMIF2 EMIF1
R-0-0h R/W-0h R/W-0h

Table 3-127. SOFTPRES1 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-2 RESERVED R-0 0h Reserved
1 EMIF2 R/W 0h When this bit is set, only the control logic of the respective EMIF2 is
reset. It does not reset the internal registers except the Total Access
register and the Total Activate register.
This bit must be manually cleared after being set.
1: EMIF2 is under SOFTRESET
0: Module reset is determined by the device Reset Network
Reset type: CPU1.SYSRSn
0 EMIF1 R/W 0h When this bit is set, only the control logic of the respective EMIF1 is
reset. It does not reset the internal registers except the Total Access
register and the Total Activate register.
This bit must be manually cleared after being set.
1: EMIF1 is under SOFTRESET
0: Module reset is determined by the device Reset Network
Reset type: CPU1.SYSRSn

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3.17.10.29 SOFTPRES2 Register (Offset = 86h) [Reset = 00000000h]

SOFTPRES2 is shown in Figure 3-115 and described in Table 3-128.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers
are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-115. SOFTPRES2 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED EPWM12 EPWM11 EPWM10 EPWM9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
EPWM8 EPWM7 EPWM6 EPWM5 EPWM4 EPWM3 EPWM2 EPWM1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-128. SOFTPRES2 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15 RESERVED R/W 0h Reserved
14 RESERVED R/W 0h Reserved
13 RESERVED R/W 0h Reserved
12 RESERVED R/W 0h Reserved
11 EPWM12 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
10 EPWM11 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
9 EPWM10 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
8 EPWM9 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
7 EPWM8 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
6 EPWM7 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
5 EPWM6 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

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Table 3-128. SOFTPRES2 Register Field Descriptions (continued)

Bit Field Type Reset Description
4 EPWM5 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
3 EPWM4 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
2 EPWM3 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
1 EPWM2 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
0 EPWM1 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

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3.17.10.30 SOFTPRES3 Register (Offset = 88h) [Reset = 00000000h]

SOFTPRES3 is shown in Figure 3-116 and described in Table 3-129.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers
are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-116. SOFTPRES3 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED ECAP6 ECAP5 ECAP4 ECAP3 ECAP2 ECAP1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-129. SOFTPRES3 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-8 RESERVED R-0 0h Reserved
7 RESERVED R/W 0h Reserved
6 RESERVED R/W 0h Reserved
5 ECAP6 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
4 ECAP5 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
3 ECAP4 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
2 ECAP3 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
1 ECAP2 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
0 ECAP1 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

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3.17.10.31 SOFTPRES4 Register (Offset = 8Ah) [Reset = 00000000h]

SOFTPRES4 is shown in Figure 3-117 and described in Table 3-130.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers
are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-117. SOFTPRES4 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED EQEP3 EQEP2 EQEP1
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-130. SOFTPRES4 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-4 RESERVED R-0 0h Reserved
3 RESERVED R/W 0h Reserved
2 EQEP3 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
1 EQEP2 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
0 EQEP1 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

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3.17.10.32 SOFTPRES6 Register (Offset = 8Eh) [Reset = 00000000h]

SOFTPRES6 is shown in Figure 3-118 and described in Table 3-131.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers
are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-118. SOFTPRES6 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RESE RESE RESE RESE RESE RESE SD2 SD1
RVED RVED RVED RVED RVED RVED
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-131. SOFTPRES6 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-8 RESERVED R-0 0h Reserved
7 RESERVED R/W 0h Reserved
6 RESERVED R/W 0h Reserved
5 RESERVED R/W 0h Reserved
4 RESERVED R/W 0h Reserved
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 SD2 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
0 SD1 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

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3.17.10.33 SOFTPRES7 Register (Offset = 90h) [Reset = 00000000h]

SOFTPRES7 is shown in Figure 3-119 and described in Table 3-132.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers
are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-119. SOFTPRES7 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED SCI_D SCI_C SCI_B SCI_A
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-132. SOFTPRES7 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-4 RESERVED R-0 0h Reserved
3 SCI_D R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
2 SCI_C R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
1 SCI_B R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
0 SCI_A R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

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3.17.10.34 SOFTPRES8 Register (Offset = 92h) [Reset = 00000000h]

SOFTPRES8 is shown in Figure 3-120 and described in Table 3-133.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers
are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-120. SOFTPRES8 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED
R-0-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED SPI_C SPI_B SPI_A
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-133. SOFTPRES8 Register Field Descriptions

Bit Field Type Reset Description
31-18 RESERVED R-0 0h Reserved
17 RESERVED R/W 0h Reserved
16 RESERVED R/W 0h Reserved
15-4 RESERVED R-0 0h Reserved
3 RESERVED R/W 0h Reserved
2 SPI_C R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
1 SPI_B R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
0 SPI_A R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

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3.17.10.35 SOFTPRES9 Register (Offset = 94h) [Reset = 00000000h]

SOFTPRES9 is shown in Figure 3-121 and described in Table 3-134.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers
are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-121. SOFTPRES9 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED
R-0-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED I2C_B I2C_A
R-0-0h R/W-0h R/W-0h

Table 3-134. SOFTPRES9 Register Field Descriptions

Bit Field Type Reset Description
31-18 RESERVED R-0 0h Reserved
17 RESERVED R/W 0h Reserved
16 RESERVED R/W 0h Reserved
15-2 RESERVED R-0 0h Reserved
1 I2C_B R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
0 I2C_A R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

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3.17.10.36 SOFTPRES11 Register (Offset = 98h) [Reset = 00000000h]

SOFTPRES11 is shown in Figure 3-122 and described in Table 3-135.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers
are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-122. SOFTPRES11 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED USB_A
R-0-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED McBSP_B McBSP_A
R-0-0h R/W-0h R/W-0h

Table 3-135. SOFTPRES11 Register Field Descriptions

Bit Field Type Reset Description
31-18 RESERVED R-0 0h Reserved
17 RESERVED R/W 0h Reserved
16 USB_A R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
15-2 RESERVED R-0 0h Reserved
1 McBSP_B R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
0 McBSP_A R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

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3.17.10.37 SOFTPRES13 Register (Offset = 9Ch) [Reset = 00000000h]

SOFTPRES13 is shown in Figure 3-123 and described in Table 3-136.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers
are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-123. SOFTPRES13 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED ADC_D ADC_C ADC_B ADC_A
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-136. SOFTPRES13 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-4 RESERVED R-0 0h Reserved
3 ADC_D R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
2 ADC_C R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
1 ADC_B R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
0 ADC_A R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

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3.17.10.38 SOFTPRES14 Register (Offset = 9Eh) [Reset = 00000000h]

SOFTPRES14 is shown in Figure 3-124 and described in Table 3-137.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers
are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-124. SOFTPRES14 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
CMPSS8 CMPSS7 CMPSS6 CMPSS5 CMPSS4 CMPSS3 CMPSS2 CMPSS1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-137. SOFTPRES14 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-8 RESERVED R-0 0h Reserved
7 CMPSS8 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
6 CMPSS7 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
5 CMPSS6 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
4 CMPSS5 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
3 CMPSS4 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
2 CMPSS3 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
1 CMPSS2 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
0 CMPSS1 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

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3.17.10.39 SOFTPRES16 Register (Offset = A2h) [Reset = 00000000h]

SOFTPRES16 is shown in Figure 3-125 and described in Table 3-138.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers
are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-125. SOFTPRES16 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED DAC_C DAC_B DAC_A
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED RESERVED
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-138. SOFTPRES16 Register Field Descriptions

Bit Field Type Reset Description
31-20 RESERVED R-0 0h Reserved
19 RESERVED R/W 0h Reserved
18 DAC_C R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
17 DAC_B R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
16 DAC_A R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
15-4 RESERVED R-0 0h Reserved
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 RESERVED R/W 0h Reserved
0 RESERVED R/W 0h Reserved

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3.17.10.40 CPUSEL0 Register (Offset = D6h) [Reset = 00000000h]

CPUSEL0 is shown in Figure 3-126 and described in Table 3-139.
Return to the Summary Table.
CPU Select register for common peripherals
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by this
register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx register.
The reset for each peripheral is also driven from the selected CPU.
Figure 3-126. CPUSEL0 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED EPWM12 EPWM11 EPWM10 EPWM9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
EPWM8 EPWM7 EPWM6 EPWM5 EPWM4 EPWM3 EPWM2 EPWM1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-139. CPUSEL0 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15 RESERVED R/W 0h Reserved
14 RESERVED R/W 0h Reserved
13 RESERVED R/W 0h Reserved
12 RESERVED R/W 0h Reserved
11 EPWM12 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
10 EPWM11 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
9 EPWM10 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
8 EPWM9 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
7 EPWM8 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
6 EPWM7 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

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Table 3-139. CPUSEL0 Register Field Descriptions (continued)

Bit Field Type Reset Description
5 EPWM6 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
4 EPWM5 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
3 EPWM4 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
2 EPWM3 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
1 EPWM2 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
0 EPWM1 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

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3.17.10.41 CPUSEL1 Register (Offset = D8h) [Reset = 00000000h]

CPUSEL1 is shown in Figure 3-127 and described in Table 3-140.
Return to the Summary Table.
CPU Select register for common peripherals
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by this
register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx register.
The reset for each peripheral is also driven from the selected CPU.
Figure 3-127. CPUSEL1 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED ECAP6 ECAP5 ECAP4 ECAP3 ECAP2 ECAP1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-140. CPUSEL1 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-8 RESERVED R-0 0h Reserved
7 RESERVED R/W 0h Reserved
6 RESERVED R/W 0h Reserved
5 ECAP6 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
4 ECAP5 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
3 ECAP4 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
2 ECAP3 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
1 ECAP2 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
0 ECAP1 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

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3.17.10.42 CPUSEL2 Register (Offset = DAh) [Reset = 00000000h]

CPUSEL2 is shown in Figure 3-128 and described in Table 3-141.
Return to the Summary Table.
CPU Select register for common peripherals
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by this
register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx register.
The reset for each peripheral is also driven from the selected CPU.
Figure 3-128. CPUSEL2 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED EQEP3 EQEP2 EQEP1
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-141. CPUSEL2 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-4 RESERVED R-0 0h Reserved
3 RESERVED R/W 0h Reserved
2 EQEP3 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
1 EQEP2 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
0 EQEP1 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

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3.17.10.43 CPUSEL3 Register (Offset = DCh) [Reset = 00000000h]

CPUSEL3 is shown in Figure 3-129 and described in Table 3-142.
Return to the Summary Table.
CPU Select register for common peripherals
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by this
register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx register.
The reset for each peripheral is also driven from the selected CPU.
Figure 3-129. CPUSEL3 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-142. CPUSEL3 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-8 RESERVED R-0 0h Reserved
7 RESERVED R/W 0h Reserved
6 RESERVED R/W 0h Reserved
5 RESERVED R/W 0h Reserved
4 RESERVED R/W 0h Reserved
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 RESERVED R/W 0h Reserved
0 RESERVED R/W 0h Reserved

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3.17.10.44 CPUSEL4 Register (Offset = DEh) [Reset = 00000000h]

CPUSEL4 is shown in Figure 3-130 and described in Table 3-143.
Return to the Summary Table.
CPU Select register for common peripherals
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by this
register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx register.
The reset for each peripheral is also driven from the selected CPU.
Figure 3-130. CPUSEL4 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RESE RESE RESE RESE RESE RESE SD2 SD1
RVED RVED RVED RVED RVED RVED
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-143. CPUSEL4 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-8 RESERVED R-0 0h Reserved
7 RESERVED R/W 0h Reserved
6 RESERVED R/W 0h Reserved
5 RESERVED R/W 0h Reserved
4 RESERVED R/W 0h Reserved
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 SD2 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
0 SD1 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

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3.17.10.45 CPUSEL5 Register (Offset = E0h) [Reset = 00000000h]

CPUSEL5 is shown in Figure 3-131 and described in Table 3-144.
Return to the Summary Table.
CPU Select register for common peripherals
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by this
register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx register.
The reset for each peripheral is also driven from the selected CPU.
Figure 3-131. CPUSEL5 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED SCI_D SCI_C SCI_B SCI_A
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-144. CPUSEL5 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-4 RESERVED R-0 0h Reserved
3 SCI_D R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
2 SCI_C R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
1 SCI_B R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
0 SCI_A R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

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3.17.10.46 CPUSEL6 Register (Offset = E2h) [Reset = 00000000h]

CPUSEL6 is shown in Figure 3-132 and described in Table 3-145.
Return to the Summary Table.
CPU Select register for common peripherals
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by this
register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx register.
The reset for each peripheral is also driven from the selected CPU.
Figure 3-132. CPUSEL6 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED
R-0-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED SPI_C SPI_B SPI_A
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-145. CPUSEL6 Register Field Descriptions

Bit Field Type Reset Description
31-18 RESERVED R-0 0h Reserved
17 RESERVED R/W 0h Reserved
16 RESERVED R/W 0h Reserved
15-4 RESERVED R-0 0h Reserved
3 RESERVED R/W 0h Reserved
2 SPI_C R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
1 SPI_B R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
0 SPI_A R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

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3.17.10.47 CPUSEL7 Register (Offset = E4h) [Reset = 00000000h]

CPUSEL7 is shown in Figure 3-133 and described in Table 3-146.
Return to the Summary Table.
CPU Select register for common peripherals
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by this
register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx register.
The reset for each peripheral is also driven from the selected CPU.
Figure 3-133. CPUSEL7 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED
R-0-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED I2C_B I2C_A
R-0-0h R/W-0h R/W-0h

Table 3-146. CPUSEL7 Register Field Descriptions

Bit Field Type Reset Description
31-18 RESERVED R-0 0h Reserved
17 RESERVED R/W 0h Reserved
16 RESERVED R/W 0h Reserved
15-2 RESERVED R-0 0h Reserved
1 I2C_B R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
0 I2C_A R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

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3.17.10.48 CPUSEL8 Register (Offset = E6h) [Reset = 00000000h]

CPUSEL8 is shown in Figure 3-134 and described in Table 3-147.
Return to the Summary Table.
CPU Select register for common peripherals
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by this
register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx register.
The reset for each peripheral is also driven from the selected CPU.
Figure 3-134. CPUSEL8 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED CAN_B CAN_A
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-147. CPUSEL8 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-4 RESERVED R-0 0h Reserved
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 CAN_B R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
0 CAN_A R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

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3.17.10.49 CPUSEL9 Register (Offset = E8h) [Reset = 00000000h]

CPUSEL9 is shown in Figure 3-135 and described in Table 3-148.
Return to the Summary Table.
CPU Select register for common peripherals
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by this
register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx register.
The reset for each peripheral is also driven from the selected CPU.
Figure 3-135. CPUSEL9 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED McBSP_B McBSP_A
R-0-0h R/W-0h R/W-0h

Table 3-148. CPUSEL9 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-2 RESERVED R-0 0h Reserved
1 McBSP_B R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
0 McBSP_A R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

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3.17.10.50 CPUSEL11 Register (Offset = ECh) [Reset = 00000000h]

CPUSEL11 is shown in Figure 3-136 and described in Table 3-149.
Return to the Summary Table.
CPU Select register for common peripherals
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by this
register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx register.
The reset for each peripheral is also driven from the selected CPU.
Figure 3-136. CPUSEL11 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED ADC_D ADC_C ADC_B ADC_A
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-149. CPUSEL11 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-4 RESERVED R-0 0h Reserved
3 ADC_D R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Note:
[1] These CPUSEL bits affect the ownership of only ADC
Configuration registers by CPU1 or CPU2 (which are mapped on
the mapped to VBUS32). ADC result registers are readable from all
masters without any CPUSEL dependency.
Reset type: CPU1.SYSRSn
2 ADC_C R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Note:
[1] These CPUSEL bits affect the ownership of only ADC
Configuration registers by CPU1 or CPU2 (which are mapped on
the mapped to VBUS32). ADC result registers are readable from all
masters without any CPUSEL dependency.
Reset type: CPU1.SYSRSn
1 ADC_B R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Note:
[1] These CPUSEL bits affect the ownership of only ADC
Configuration registers by CPU1 or CPU2 (which are mapped on
the mapped to VBUS32). ADC result registers are readable from all
masters without any CPUSEL dependency.
Reset type: CPU1.SYSRSn

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Table 3-149. CPUSEL11 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 ADC_A R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Note:
[1] These CPUSEL bits affect the ownership of only ADC
Configuration registers by CPU1 or CPU2 (which are mapped on
the mapped to VBUS32). ADC result registers are readable from all
masters without any CPUSEL dependency.
Reset type: CPU1.SYSRSn

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3.17.10.51 CPUSEL12 Register (Offset = EEh) [Reset = 00000000h]

CPUSEL12 is shown in Figure 3-137 and described in Table 3-150.
Return to the Summary Table.
CPU Select register for common peripherals
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by this
register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx register.
The reset for each peripheral is also driven from the selected CPU.
Figure 3-137. CPUSEL12 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
CMPSS8 CMPSS7 CMPSS6 CMPSS5 CMPSS4 CMPSS3 CMPSS2 CMPSS1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-150. CPUSEL12 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-8 RESERVED R-0 0h Reserved
7 CMPSS8 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
6 CMPSS7 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
5 CMPSS6 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
4 CMPSS5 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
3 CMPSS4 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
2 CMPSS3 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
1 CMPSS2 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

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Table 3-150. CPUSEL12 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 CMPSS1 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

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3.17.10.52 CPUSEL14 Register (Offset = F2h) [Reset = 00000000h]

CPUSEL14 is shown in Figure 3-138 and described in Table 3-151.
Return to the Summary Table.
CPU Select register for common peripherals
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by this
register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx register.
The reset for each peripheral is also driven from the selected CPU.
Figure 3-138. CPUSEL14 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED DAC_C DAC_B DAC_A
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED RESERVED
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-151. CPUSEL14 Register Field Descriptions

Bit Field Type Reset Description
31-20 RESERVED R-0 0h Reserved
19 RESERVED R/W 0h Reserved
18 DAC_C R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
17 DAC_B R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
16 DAC_A R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
15-4 RESERVED R-0 0h Reserved
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 RESERVED R/W 0h Reserved
0 RESERVED R/W 0h Reserved

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3.17.10.53 CPU2RESCTL Register (Offset = 122h) [Reset = 00000001h]

CPU2RESCTL is shown in Figure 3-139 and described in Table 3-152.
Return to the Summary Table.
CPU2 Reset Control Register
Figure 3-139. CPU2RESCTL Register
31 30 29 28 27 26 25 24
KEY
R-0/W-0h

23 22 21 20 19 18 17 16
KEY
R-0/W-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESET
R-0-0h R/W-1h

Table 3-152. CPU2RESCTL Register Field Descriptions

Bit Field Type Reset Description
31-16 KEY R-0/W 0h Write to this register succeeds only if this field is written with a value
of 0xa5a5
Note:
[1] Due to this KEY, only 32-bit writes will succeed (provided the KEY
matches). 16-bit writes to the upper or lower half of this register will
be ignored
Reset type: N/A
15-1 RESERVED R-0 0h Reserved
0 RESET R/W 1h This bit controls the reset input of CPU2 core.
1: CPU2 is held in reset (CPU2.RSn = 0)
0: CPU2 reset is deactivated (CPU2.RSn = 1)
Note:
[1] If CPU2 is not used at-all by an application, it's advisable to put
CPU2 in STANDBY mode rather than in reset to save on active
power component on the CPU2 subsystem. This is because, all
clocks keep toggling when reset is active on the CPU2 sub-system.
[2] Note: If CPU2 is in Standby mode, writing to this bit will have
no effect. CPU2 may be reset by any Chip-level reset (POR, XRSn,
CPU1.WDRSn, or CPU1.NMIWDRSn) or HIBRESETn. Alternately
CPU2 may be woken up by any configured wake-up event.
Reset type: CPU1.SYSRSn

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3.17.10.54 RSTSTAT Register (Offset = 124h) [Reset = 0000h]

RSTSTAT is shown in Figure 3-140 and described in Table 3-153.
Return to the Summary Table.
Reset Status register for secondary C28x CPUs
Figure 3-140. RSTSTAT Register
15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED CPU2HWBIST CPU2HWBIST CPU2NMIWDR CPU2RES
RST1 RST0 ST
R-0-0h R/W1S-0h R/W1S-0h R/W1S-0h R-0h

Table 3-153. RSTSTAT Register Field Descriptions

Bit Field Type Reset Description
15-4 RESERVED R-0 0h Reserved
3 CPU2HWBISTRST1 R/W1S 0h CPU2HWBISTRST0 and CPU2HWBISTRST1 together indicates
whether a HWBIST reset was issued to CPU2 or not
00: CPU2 was not reset by the CPU2 HWBIST
11: CPU2 was reset due to CPU2 HWBIST reset
This status bit is a latched flag. This flag can be cleared by the CPU1
by writing a 1
Reset type: CPU1.SYSRSn
2 CPU2HWBISTRST0 R/W1S 0h CPU2HWBISTRST0 and CPU2HWBISTRST1 together indicates
whether a HWBIST reset was issued to CPU2 or not
00: CPU2 was not reset by the CPU2 HWBIST
11: CPU2 was reset due to CPU2 HWBIST reset
This status bit is a latched flag. This flag can be cleared by the CPU1
by writing a 1
Reset type: CPU1.SYSRSn
1 CPU2NMIWDRST R/W1S 0h Indicates whether a CPU2.NMIWD reset was issued to CPU2 or not
0: CPU2 was not reset by the CPU2.NMIWD
1: CPU2 was reset due to CPU2.NMIWD reset
This status bit is a latched flag.This flag can be cleared by the CPU1
by writing a 1
Reset type: CPU1.SYSRSn
0 CPU2RES R 0h Reset status of CPU2 to CPU1
0: CPU2 core is in reset
1: CPU2 core is out of reset
Reset type: CPU1.SYSRSn

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3.17.10.55 LPMSTAT Register (Offset = 125h) [Reset = 0000h]

LPMSTAT is shown in Figure 3-141 and described in Table 3-154.
Return to the Summary Table.
LPM Status Register for secondary C28x CPUs
Figure 3-141. LPMSTAT Register
15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED CPU2LPMSTAT
R-0-0h R-0h

Table 3-154. LPMSTAT Register Field Descriptions

Bit Field Type Reset Description
15-2 RESERVED R-0 0h Reserved
1-0 CPU2LPMSTAT R 0h These bits indicate the power mode CPU2
00: CPU2 is in ACTIVE mode
01: CPU2 is in IDLE mode
10: CPU2 is in STANDBY mode
11: Reserved
Reset type: CPU1.SYSRSn

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3.17.10.56 SYSDBGCTL Register (Offset = 12Ch) [Reset = 00000000h]

SYSDBGCTL is shown in Figure 3-142 and described in Table 3-155.
Return to the Summary Table.
System Debug Control register
Figure 3-142. SYSDBGCTL Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED BIT_0
R-0-0h R/W-0h

Table 3-155. SYSDBGCTL Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-1 RESERVED R-0 0h Reserved
0 BIT_0 R/W 0h This bit is for use in PLL startup and is only reset by POR.
Reset type: POR

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3.17.11 CLK_CFG_REGS Registers

Table 3-156 lists the memory-mapped registers for the CLK_CFG_REGS registers. All register offset addresses
not listed in Table 3-156 should be considered as reserved locations and the register contents should not be
modified.
Table 3-156. CLK_CFG_REGS Registers
Offset Acronym Register Name Write Protection Section
0h CLKSEM Clock Control Semaphore Register EALLOW Go
2h CLKCFGLOCK1 Lock bit for CLKCFG registers EALLOW Go
8h CLKSRCCTL1 Clock Source Control register-1 EALLOW Go
Ah CLKSRCCTL2 Clock Source Control register-2 EALLOW Go
Ch CLKSRCCTL3 Clock Source Control register-3 EALLOW Go
Eh SYSPLLCTL1 SYSPLL Control register-1 EALLOW Go
14h SYSPLLMULT SYSPLL Multiplier register EALLOW Go
16h SYSPLLSTS SYSPLL Status register Go
18h AUXPLLCTL1 AUXPLL Control register-1 EALLOW Go
1Eh AUXPLLMULT AUXPLL Multiplier register EALLOW Go
20h AUXPLLSTS AUXPLL Status register Go
22h SYSCLKDIVSEL System Clock Divider Select register EALLOW Go
24h AUXCLKDIVSEL Auxillary Clock Divider Select register EALLOW Go
26h PERCLKDIVSEL Peripheral Clock Divider Selet register EALLOW Go
28h XCLKOUTDIVSEL XCLKOUT Divider Select register EALLOW Go
2Ch LOSPCP Low Speed Clock Source Prescalar EALLOW Go
2Eh MCDCR Missing Clock Detect Control Register EALLOW Go
30h X1CNT 10-bit Counter on X1 Clock Go

Complex bit access types are encoded to fit into small table cells. Table 3-157 shows the codes that are used for
access types in this section.
Table 3-157. CLK_CFG_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1S W Write
1S 1 to set
WSonce W Write
Sonce Set once
Reset or Default Value
-n Value after reset or the default value
Register Array Variables
i,j,k,l,m,n When these variables are used in a register name,
an offset, or an address, they refer to the value of a
register array where the register is part of a group
of repeating registers. The register groups form a
hierarchical structure and the array is represented
with a formula.

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Table 3-157. CLK_CFG_REGS Access Type Codes (continued)

Access Type Code Description
y When this variable is used in a register name, an
offset, or an address it refers to the value of a
register array.

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3.17.11.1 CLKSEM Register (Offset = 0h) [Reset = 00000000h]

CLKSEM is shown in Figure 3-143 and described in Table 3-158.
Return to the Summary Table.
Clock Control Semaphore Register
Figure 3-143. CLKSEM Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
R-0/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED SEM
R-0-0h R/W-0h

Table 3-158. CLKSEM Register Field Descriptions

Bit Field Type Reset Description
31-16 KEY R-0/W 0h Writing the value 0xa5a5 will allow the writing of the SEM bits, else
writes are ignored. Reads will return 0.
Note:
[1] Due to this KEY, only 32-bit writes will succeed (provided the KEY
matches). 16-bit writes to the upper or lower half of this register will
be ignored
Reset type: N/A
15-2 RESERVED R-0 0h Reserved
1-0 SEM R/W 0h This register provides a mechanism to acquire all the CLKCFG
registers (except this register) by CPU1 or CPU2. A CPU can
perform read/writes to any of the CLKCFG registers (except this
register) only if it owns the semaphore. Otherwise, writes are ignored
and reads will return 0x0.
Semaphore State Transitions:
A value of 00, 10, 11 gives ownership to CPU1
A value of 01 gives ownership to CPU2.
The following are the only state transitions allowed on these bits.
00,11 <-> 01 (allowed by CPU2)
00,11 <-> 10 (allowed by CPU1)
If a CPU doesn't own the CLK_CFG_REGS set of registers (as
defined by the state of this semaphore), reads from that CPU to all
those registers return 0x0 and writes are ignore. Note that this is not
true of CLKSEM register. The CLKSEM register's reads and writes
are always allowed from both CPU1 and CPU2.
Reset type: CPU1.SYSRSn

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3.17.11.2 CLKCFGLOCK1 Register (Offset = 2h) [Reset = 00000000h]

CLKCFGLOCK1 is shown in Figure 3-144 and described in Table 3-159.
Return to the Summary Table.
Lock bit for CLKCFG registers
Notes:
[1] Any bit in this register, once set can only be cleared through a CPU1.SYSRSn. Write of 0 to any bit of this
register has no effect
[2] The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are always
allowed
Figure 3-144. CLKCFGLOCK1 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
LOSPCP RESERVED PERCLKDIVSE AUXCLKDIVSE SYSCLKDIVSE AUXPLLMULT RESERVED RESERVED
L L L
R/WSonce-0h R-0-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R-0-0h R-0-0h

7 6 5 4 3 2 1 0
AUXPLLCTL1 SYSPLLMULT SYSPLLCTL3 SYSPLLCTL2 SYSPLLCTL1 CLKSRCCTL3 CLKSRCCTL2 CLKSRCCTL1
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

Table 3-159. CLKCFGLOCK1 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15 LOSPCP R/WSonce 0h Lock bit for LOSPCP register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: CPU1.SYSRSn
14 RESERVED R-0 0h Reserved
13 PERCLKDIVSEL R/WSonce 0h Lock bit for PERCLKDIVSEL register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: CPU1.SYSRSn
12 AUXCLKDIVSEL R/WSonce 0h Lock bit for AUXCLKDIVSEL register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: CPU1.SYSRSn
11 SYSCLKDIVSEL R/WSonce 0h Lock bit for SYSCLKDIVSEL register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: CPU1.SYSRSn
10 AUXPLLMULT R/WSonce 0h Lock bit for AUXPLLMULT register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: CPU1.SYSRSn
9 RESERVED R-0 0h Reserved
8 RESERVED R-0 0h Reserved

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Table 3-159. CLKCFGLOCK1 Register Field Descriptions (continued)

Bit Field Type Reset Description
7 AUXPLLCTL1 R/WSonce 0h Lock bit for AUXPLLCTL1 register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: CPU1.SYSRSn
6 SYSPLLMULT R/WSonce 0h Lock bit for SYSPLLMULT register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: CPU1.SYSRSn
5 SYSPLLCTL3 R/WSonce 0h Lock bit for SYSPLLCTL3 register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: CPU1.SYSRSn
4 SYSPLLCTL2 R/WSonce 0h Lock bit for SYSPLLCTL2 register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: CPU1.SYSRSn
3 SYSPLLCTL1 R/WSonce 0h Lock bit for SYSPLLCTL1 register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: CPU1.SYSRSn
2 CLKSRCCTL3 R/WSonce 0h Lock bit for CLKSRCCTL3 register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: CPU1.SYSRSn
1 CLKSRCCTL2 R/WSonce 0h Lock bit for CLKSRCCTL2 register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: CPU1.SYSRSn
0 CLKSRCCTL1 R/WSonce 0h Lock bit for CLKSRCCTL1 register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: CPU1.SYSRSn

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3.17.11.3 CLKSRCCTL1 Register (Offset = 8h) [Reset = 00000000h]

CLKSRCCTL1 is shown in Figure 3-145 and described in Table 3-160.
Return to the Summary Table.
Clock Source Control register-1
This memory mapped register requires a delay of 69 SYSCLK cycles between subsequent writes to the register,
otherwise a second write can be lost. This delay can be realized by adding 69 NOP instructions.
Figure 3-145. CLKSRCCTL1 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED WDHALTI XTALOFF INTOSC2OFF RESERVED OSCCLKSRCSEL
R-0-0h R/W-0h R/W-0h R/W-0h R-0-0h R/W-0h

Table 3-160. CLKSRCCTL1 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-6 RESERVED R-0 0h Reserved
5 WDHALTI R/W 0h Watchdog HALT Mode Ignore Bit: This bit determines if CPU1.WD is
functional in the HALT mode or not.
0 = CPU1.WD is not functional in the HALT mode. Clock to
CPU1.WD is gated when system enters HALT mode. Additionally,
INTOSC1 and INTOSC2 are powered-down when system enters
HALT mode
1 = CPU1.WD is functional in the HALT mode. Clock to CPU1.WD
is not gated and INTOSC1/2 are not powered-down when system
enters HALT mode
Notes:
[1] Clock to CPU2.WD clocks is always gated in the HALT mode.
Reset type: XRSn
4 XTALOFF R/W 0h Crystal (External) Oscillator Off Bit: This bit turns external oscillator
off:
0 = Crystal (External) Oscillator On (default on reset)
1 = Crystal (External) Oscillator Off
NOTE: Ensure no resources are using a clock source prior
to disabling it. For example OSCCLKSRCSEL (SYSPLL),
AUXOSCCLKSRCSEL (AUXPLL), CANxBCLKSEL (CAN Clock),
TMR2CLKSRCSEL (CPUTIMER2) and XCLKOUTSEL(XCLKOUT).
Reset type: XRSn

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Table 3-160. CLKSRCCTL1 Register Field Descriptions (continued)

Bit Field Type Reset Description
3 INTOSC2OFF R/W 0h Internal Oscillator 2 Off Bit: This bit turns oscillator 2 off:
0 = Internal Oscillator 2 On (default on reset)
1 = Internal Oscillator 2 Off
This bit could be used by the user to turn off the internal oscillator 2 if
it is not used.
NOTE: Ensure no resources are using a clock source
prior to disabling it. For example OSCCLKSRCSEL
(SYSPLL), AUXOSCCLKSRCSEL (AUXPLL), TMR2CLKSRCSEL
(CPUTIMER2) and XCLOCKOUT (XCLKOUT).
Reset type: XRSn
2 RESERVED R-0 0h Reserved
1-0 OSCCLKSRCSEL R/W 0h Oscillator Clock Source Select Bit: This bit selects the source for
OSCCLK.
00 = INTOSC2 (default on reset)
01 = External Oscillator (XTAL)
10 = INTOSC1
11 = reserved (default to INTOSC1)
At power-up or after an XRSn, INTOSC2 is selected by default.
Whenever the user changes the clock source using these bits,
the SYSPLLMULT register will be forced to zero and the PLL will
be bypassed and powered down. This prevents potential PLL
overshoot. The user will then have to write to the SYSPLLMULT
register to configure the appropriate multiplier.
The user must wait 10 OSCCLK cycles before writing to
SYSPLLMULT
or disabling the previous clock source to allow the change to
complete..
Notes:
[1] Reserved selection defaults to 00 configuration
[2] INTOSC1 is recommended to be used only after missing clock
detection. If user wants to re-lock the PLL with INTOSC1 (the
back-up clock source) after missing clock is detected, he can do a
MCLKCLR and lock the PLL.
Reset type: XRSn

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3.17.11.4 CLKSRCCTL2 Register (Offset = Ah) [Reset = 00000000h]

CLKSRCCTL2 is shown in Figure 3-146 and described in Table 3-161.
Return to the Summary Table.
Clock Source Control register-2
This memory mapped register requires a delay of 69 SYSCLK cycles between subsequent writes to the register,
otherwise a second write can be lost. This delay can be realized by adding 69 NOP instructions.
Figure 3-146. CLKSRCCTL2 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED
R-0-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED CANBBCLKSEL CANABCLKSEL AUXOSCCLKSRCSEL
R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-161. CLKSRCCTL2 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-10 RESERVED R-0 0h Reserved
9-8 RESERVED R/W 0h Reserved
7-6 RESERVED R/W 0h Reserved
5-4 CANBBCLKSEL R/W 0h CANB Bit-Clock Source Select Bit:
00 = PERx.SYSCLK (default on reset)
01 = External Oscillator (XTAL)
10 = AUXCLKIN (from GPIO)
11 = Reserved
Missing clock detect circuit doesnt have any impact on these bits.
Reset type: XRSn
3-2 CANABCLKSEL R/W 0h CANA Bit-Clock Source Select Bit:
00 = PERx.SYSCLK (default on reset)
01 = External Oscillator (XTAL)
10 = AUXCLKIN (from GPIO)
11 = Reserved
Missing clock detect circuit doesnt have any impact on these bits.
Reset type: XRSn

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Table 3-161. CLKSRCCTL2 Register Field Descriptions (continued)

Bit Field Type Reset Description
1-0 AUXOSCCLKSRCSEL R/W 0h Oscillator Clock Source Select Bit: This bit selects the source for
AUXOSCCLK:
00 = INTOSC2 (default on reset)
01 = External Oscillator (XTAL)
10 = AUXCLKIN (from GPIO)
11 = Reserved
Whenever the user changes the clock source using these bits,
the AUXPLLMULT register will be forced to zero and the PLL will
be bypassed and powered down. This prevents potential PLL
overshoot. The user will then have to write to the AUXPLLMULT
register to configure the appropriate multiplier.
The user must wait 10 OSCCLK cycles before writing to
AUXPLLMULT
or disabling the previous clock source to allow the change to
complete.
The missing clock detection circuit does not affect these bits.
Reset type: XRSn

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3.17.11.5 CLKSRCCTL3 Register (Offset = Ch) [Reset = 00000000h]

CLKSRCCTL3 is shown in Figure 3-147 and described in Table 3-162.
Return to the Summary Table.
Clock Source Control register-3
This memory mapped register requires a delay of 69 SYSCLK cycles between subsequent writes to the register,
otherwise a second write can be lost. This delay can be realized by adding 69 NOP instructions.
Figure 3-147. CLKSRCCTL3 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED XCLKOUTSEL
R-0-0h R/W-0h

Table 3-162. CLKSRCCTL3 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-3 RESERVED R-0 0h Reserved
2-0 XCLKOUTSEL R/W 0h XCLKOUT Source Select Bit: This bit selects the source for
XCLKOUT:
000 = PLLSYSCLK (default on reset)
001 = PLLRAWCLK
010 = CPU1.SYSCLK
011 = CPU2.SYSCLK
100 = AUXPLLRAWCLK
101 = INTOSC1
110 = INTOSC2
111 = Reserved
Reset type: CPU1.SYSRSn

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3.17.11.6 SYSPLLCTL1 Register (Offset = Eh) [Reset = 00000000h]

SYSPLLCTL1 is shown in Figure 3-148 and described in Table 3-163.
Return to the Summary Table.
SYSPLL Control register-1
This memory mapped register requires a delay of 69 SYSCLK cycles between subsequent writes to the register,
otherwise a second write can be lost. This delay can be realized by adding 69 NOP instructions.
Figure 3-148. SYSPLLCTL1 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED PLLCLKEN PLLEN
R-0-0h R/W-0h R/W-0h

Table 3-163. SYSPLLCTL1 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-2 RESERVED R-0 0h Reserved
1 PLLCLKEN R/W 0h SYSPLL bypassed or included in the PLLSYSCLK path: This bit
decides if the SYSPLL is bypassed when PLLSYSCLK is generated
1 = PLLSYSCLK is fed from the SYSPLL clock output. Users need
to make sure that the PLL is locked before enabling this clock to the
system.
0 = SYSPLL is bypassed. Clock to system is direct feed from
OSCCLK
Reset type: XRSn
0 PLLEN R/W 0h SYSPLL enabled or disabled: This bit decides if the SYSPLL is
enabled or not
1 = SYSPLL is enabled
0 = SYSPLL is powered off. Clock to system is direct feed from
OSCCLK
Reset type: XRSn

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3.17.11.7 SYSPLLMULT Register (Offset = 14h) [Reset = 00000000h]

SYSPLLMULT is shown in Figure 3-149 and described in Table 3-164.
Return to the Summary Table.
SYSPLL Multiplier register
NOTE: FMULT and IMULT fields must be written at the same time for correct PLL operation.
This memory mapped register requires a delay of 69 SYSCLK cycles between subsequent writes to the register,
otherwise a second write can be lost. This delay can be realized by adding 69 NOP instructions.
Figure 3-149. SYSPLLMULT Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED FMULT
R-0-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED IMULT
R-0-0h R/W-0h

Table 3-164. SYSPLLMULT Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-10 RESERVED R-0 0h Reserved
9-8 FMULT R/W 0h SYSPLL Fractional Multiplier:
00 Fractional Multiplier = 0
01 Fractional Multiplier = 0.25
10 Fractional Multiplier = 0.5
11 Fractional Multiplier = 0.75
Reset type: XRSn
7 RESERVED R-0 0h Reserved
6-0 IMULT R/W 0h SYSPLL Integer Multiplier:
For 0000000 Fout = Fref (PLLBYPASS) Integer Multiplier = 1
0000001 Integer Multiplier = 1
0000010 Integer Multiplier = 2
0000011 Integer Multiplier = 3
.......
1111111 Integer Multipler = 127
Reset type: XRSn

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3.17.11.8 SYSPLLSTS Register (Offset = 16h) [Reset = 00000000h]

SYSPLLSTS is shown in Figure 3-150 and described in Table 3-165.
Return to the Summary Table.
SYSPLL Status register
Figure 3-150. SYSPLLSTS Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED SLIPS LOCKS
R-0-0h R-0h R-0h

Table 3-165. SYSPLLSTS Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-2 RESERVED R-0 0h Reserved
1 SLIPS R 0h SYSPLL Slip Status Bit: This bit indicates whether the SYSPLL is out
of lock range
0 = SYSPLL is not out of lock
1 = SYSPLL is out of loc
The SLIPS bit will only be set on a PLL slip condition after the PLL is
used as the SYSCLK source by seting the
SYSPLLCTL1[PLLCLKEN] bit. Disabling and re-enabling the PLL
with PLLEN is the only way to clear this bit.
Note:
[1] If SYSPLL out of lock condition is detected then interrupts are
fired to CPU1 and CPU2 through their respective ePIE modules.
Software can decide to relock the PLL or switch to PLL bypass mode
in the interrupt handler
Reset type: XRSn
0 LOCKS R 0h SYSPLL Lock Status Bit: This bit indicates whether the SYSPLL is
locked or not
0 = SYSPLL is not yet locked
1 = SYSPLL is locked
Reset type: XRSn

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3.17.11.9 AUXPLLCTL1 Register (Offset = 18h) [Reset = 00000000h]

AUXPLLCTL1 is shown in Figure 3-151 and described in Table 3-166.
Return to the Summary Table.
AUXPLL Control register-1
Figure 3-151. AUXPLLCTL1 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED PLLCLKEN PLLEN
R-0-0h R/W-0h R/W-0h

Table 3-166. AUXPLLCTL1 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-2 RESERVED R-0 0h Reserved
1 PLLCLKEN R/W 0h AUXPLL bypassed or included in the AUXPLLCLK path: This bit
decides if the AUXPLL is bypassed when AUXPLLCLK is generated
1 = AUXPLLCLK is fed from the AUXPLL clock output. Users need
to make sure that the PLL is locked before enabling this clock to the
AUXPLLCLK connected modules.
0 = AUXPLL is bypassed. Clock to modules connected to
AUXPLLCLK is direct feed from AUXOSCCLK
Reset type: XRSn
0 PLLEN R/W 0h AUXPLL enabled or disabled: This bit decides if the AUXPLL is
enabled or not
1 = AUXPLL is enabled
0 = AUXPLL is powered off. Clock to system is direct feed from
AUXOSCCLK
Reset type: XRSn

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3.17.11.10 AUXPLLMULT Register (Offset = 1Eh) [Reset = 00000000h]

AUXPLLMULT is shown in Figure 3-152 and described in Table 3-167.
Return to the Summary Table.
AUXPLL Multiplier register
NOTE: FMULT and IMULT fields must be written at the same time for correct PLL operation.
This memory mapped register requires a delay of 69 SYSCLK cycles between subsequent writes to the register,
otherwise a second write can be lost. This delay can be realized by adding 69 NOP instructions.
Figure 3-152. AUXPLLMULT Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED FMULT
R-0-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED IMULT
R-0-0h R/W-0h

Table 3-167. AUXPLLMULT Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-10 RESERVED R-0 0h Reserved
9-8 FMULT R/W 0h AUXPLL Fractional Multiplier :
00 Fractional Multiplier = 0
01 Fractional Multiplier = 0.25
10 Fractional Multiplier = 0.5
11 Fractional Multiplier = 0.75
Reset type: XRSn
7 RESERVED R-0 0h Reserved
6-0 IMULT R/W 0h AUXPLL Integer Multiplier:
For 0000000 Fout = Fref (PLLBYPASS) Integer Multiplier = 1
0000001 Integer Multiplier = 1
0000010 Integer Multiplier = 2
0000011 Integer Multiplier = 3
.......
1111111 Integer Multipler = 127
Reset type: XRSn

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3.17.11.11 AUXPLLSTS Register (Offset = 20h) [Reset = 00000000h]

AUXPLLSTS is shown in Figure 3-153 and described in Table 3-168.
Return to the Summary Table.
AUXPLL Status register
Figure 3-153. AUXPLLSTS Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED SLIPS LOCKS
R-0-0h R-0h R-0h

Table 3-168. AUXPLLSTS Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-2 RESERVED R-0 0h Reserved
1 SLIPS R 0h AUXPLL Slip Status Bit: This bit indicates whether the AUXPLL is
out of lock range
0 = AUXPLL is not out of lock
1 = AUXPLL is out of lock
The SLIPS bit will only be set on a PLL slip condition after the PLL is
used as the AUXPLLCLK source by seting the
AUXPLLCTL1[PLLCLKEN] bit. Disabling and re-enabling the PLL
with PLLEN is the only way to clear this bit.
Note:
[1] If AUXPLL out of lock condition is detected then interrupts are
fired to CPU1 and CPU2 through their respective ePIE modules.
Software can decide to relock the PLL or switch to PLL bypass mode
in the interrupt handler
Reset type: XRSn
0 LOCKS R 0h AUXPLL Lock Status Bit: This bit indicates whether the AUXPLL is
locked or not
0 = AUXPLL is not yet locked
1 = AUXPLL is locked
Reset type: XRSn

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3.17.11.12 SYSCLKDIVSEL Register (Offset = 22h) [Reset = 00000002h]

SYSCLKDIVSEL is shown in Figure 3-154 and described in Table 3-169.
Return to the Summary Table.
System Clock Divider Select register
This memory mapped register requires a delay of 69 SYSCLK cycles between subsequent writes to the register,
otherwise a second write can be lost. This delay can be realized by adding 69 NOP instructions.
Figure 3-154. SYSCLKDIVSEL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED PLLSYSCLKDIV
R-0-0h R/W-2h

Table 3-169. SYSCLKDIVSEL Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-6 RESERVED R-0 0h Reserved
5-0 PLLSYSCLKDIV R/W 2h PLLSYSCLK Divide Select: This bit selects the divider setting for the
PLLSYSCLK.
000000 = /1
000001 = /2
000010 = /4 (default on reset)
000011 = /6
000100 = /8
......
111111 = /126
Reset type: XRSn

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3.17.11.13 AUXCLKDIVSEL Register (Offset = 24h) [Reset = 00000001h]

AUXCLKDIVSEL is shown in Figure 3-155 and described in Table 3-170.
Return to the Summary Table.
Auxillary Clock Divider Select register
This memory mapped register requires a delay of 69 SYSCLK cycles between subsequent writes to the register,
otherwise a second write can be lost. This delay can be realized by adding 69 NOP instructions.
Figure 3-155. AUXCLKDIVSEL Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED AUXPLLDIV
R-0-0h R/W-1h

Table 3-170. AUXCLKDIVSEL Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-2 RESERVED R-0 0h Reserved
1-0 AUXPLLDIV R/W 1h AUXPLLCLK Divide Select: This bit selects the divider setting for the
AUXPLLCK.
00 = /1
01 = /2 (default on reset)
10 = /4
11 = /8
Reset type: XRSn

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3.17.11.14 PERCLKDIVSEL Register (Offset = 26h) [Reset = 00000051h]

PERCLKDIVSEL is shown in Figure 3-156 and described in Table 3-171.
Return to the Summary Table.
Peripheral Clock Divider Selet register
This memory mapped register requires a delay of 69 SYSCLK cycles between subsequent writes to the register,
otherwise a second write can be lost. This delay can be realized by adding 69 NOP instructions.
Figure 3-156. PERCLKDIVSEL Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED EMIF2CLKDIV RESERVED EMIF1CLKDIV RESERVED EPWMCLKDIV
R-0-0h R/W-1h R-0-0h R/W-1h R/W-0h R/W-1h

Table 3-171. PERCLKDIVSEL Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-7 RESERVED R-0 0h Reserved
6 EMIF2CLKDIV R/W 1h EMIF2 Clock Divide Select: This bit selects whether the EMIF2
module run with a /1 or /2 clock.
0: /1 of CPU1.SYSCLK is selected
1: /2 of CPU1.SYSCLK is selected
Reset type: CPU1.SYSRSn
5 RESERVED R-0 0h Reserved
4 EMIF1CLKDIV R/W 1h EMIF1 Clock Divide Select: This bit selects whether the EMIF1
module run with a /1 or /2 clock.
For single core device
0: /1 of CPU1.SYSCLK is selected
1: /2 of CPU1.SYSCLK is selected
For Dual core device
0: /1 of PLLSYSCLK is selected
1: /2 of PLLSYSCLK is selected
Reset type: CPU1.SYSRSn
3-2 RESERVED R/W 0h Reserved
1-0 EPWMCLKDIV R/W 1h EPWM Clock Divide Select: This bit selects whether the EPWM
modules run with a /1 or /2 clock. This divider sits in front of the
PLLSYSCLK
x0 = /1 of PLLSYSCLK
x1 = /2 of PLLSYSLCK (default on reset)
Note: /1 should only be used when SYSCLK is 100MHz or less, see
the datasheet for EPWMCLK specifications
Reset type: CPU1.SYSRSn

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3.17.11.15 XCLKOUTDIVSEL Register (Offset = 28h) [Reset = 00000003h]

XCLKOUTDIVSEL is shown in Figure 3-157 and described in Table 3-172.
Return to the Summary Table.
XCLKOUT Divider Select register
This memory mapped register requires a delay of 69 SYSCLK cycles between subsequent writes to the register,
otherwise a second write can be lost. This delay can be realized by adding 69 NOP instructions.
Figure 3-157. XCLKOUTDIVSEL Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED XCLKOUTDIV
R-0-0h R/W-3h

Table 3-172. XCLKOUTDIVSEL Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-2 RESERVED R-0 0h Reserved
1-0 XCLKOUTDIV R/W 3h XCLKOUT Divide Select: This bit selects the divider setting for the
XCLKOUT.
00 = /1
01 = /2
10 = /4
11 = /8 (default on reset)
Reset type: CPU1.SYSRSn

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3.17.11.16 LOSPCP Register (Offset = 2Ch) [Reset = 00000002h]

LOSPCP is shown in Figure 3-158 and described in Table 3-173.
Return to the Summary Table.
Low Speed Clock Source Prescalar
Figure 3-158. LOSPCP Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED LSPCLKDIV
R-0-0h R/W-2h

Table 3-173. LOSPCP Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-3 RESERVED R-0 0h Reserved
2-0 LSPCLKDIV R/W 2h These bits configure the low-speed peripheral clock (LSPCLK) rate
relative to SYSCLK of CPU1 and CPU2.
000,LSPCLK = / 1
001,LSPCLK = / 2
010,LSPCLK = / 4 (default on reset)
011,LSPCLK = / 6
100,LSPCLK = / 8
101,LSPCLK = / 10
110,LSPCLK = / 12
111,LSPCLK = / 14
Note:
[1] This clock is used as strobe for the SCI and SPI modules.
Reset type: CPU1.SYSRSn

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3.17.11.17 MCDCR Register (Offset = 2Eh) [Reset = 00000000h]

MCDCR is shown in Figure 3-159 and described in Table 3-174.
Return to the Summary Table.
Missing Clock Detect Control Register
Figure 3-159. MCDCR Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED OSCOFF MCLKOFF MCLKCLR MCLKSTS
R-0-0h R/W-0h R/W-0h R-0/W1S-0h R-0h

Table 3-174. MCDCR Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-4 RESERVED R-0 0h Reserved
3 OSCOFF R/W 0h Oscillator Clock Off Bit:
0 = OSCCLK Connected to OSCCLK Counter in MCD module
1 = OSCCLK Disconnected to OSCCLK Counter in MCD module
Reset type: XRSn
2 MCLKOFF R/W 0h Missing Clock Detect Off Bit:
0 = Missing Clock Detect Circuit Enabled
1 = Missing Clock Detect Circuit Disabled
Reset type: XRSn
1 MCLKCLR R-0/W1S 0h Missing Clock Clear Bit:
Write 1' to this bit to clear MCLKSTS bit and reset the missing clock
detect circuit.'
Reset type: XRSn
0 MCLKSTS R 0h Missing Clock Status Bit:
0 = OSCCLK Is OK
1 = OSCCLK Detected Missing, CLOCKFAILn Generated
Reset type: XRSn

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3.17.11.18 X1CNT Register (Offset = 30h) [Reset = 00000000h]

X1CNT is shown in Figure 3-160 and described in Table 3-175.
Return to the Summary Table.
10-bit Counter on X1 Clock
Figure 3-160. X1CNT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED X1CNT
R-0-0h R-0h

Table 3-175. X1CNT Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-10 RESERVED R-0 0h Reserved
9-0 X1CNT R 0h X1 Counter:
- This counter increments on every X1 CLOCKs positive-edge.
- Once it reaches the values of 0x3ff, it freezes
- Before switching from INTOSC2 to X1, application must check
this counter and make sure that it has saturated. This will ensure
that the Crystal connected to X1/X2 is oscillating. Note: Since
this bit counter cannot be reset locally, TI recommends using the
'SysCtl_pollCpuTimer' function in C2000Ware to detect the validity of
the clock on X1
Reset type: POR

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3.17.12 CPU_SYS_REGS Registers

Table 3-176 lists the memory-mapped registers for the CPU_SYS_REGS registers. All register offset addresses
not listed in Table 3-176 should be considered as reserved locations and the register contents should not be
modified.
Table 3-176. CPU_SYS_REGS Registers
Offset Acronym Register Name Write Protection Section
0h CPUSYSLOCK1 Lock bit for CPUSYS registers EALLOW Go
6h HIBBOOTMODE HIB Boot Mode Register EALLOW Go
8h IORESTOREADDR IORestore() routine Address Register EALLOW Go
Ah PIEVERRADDR PIE Vector Fetch Error Address register EALLOW Go
22h PCLKCR0 Peripheral Clock Gating Registers EALLOW Go
24h PCLKCR1 Peripheral Clock Gating Registers EALLOW Go
26h PCLKCR2 Peripheral Clock Gating Registers EALLOW Go
28h PCLKCR3 Peripheral Clock Gating Registers EALLOW Go
2Ah PCLKCR4 Peripheral Clock Gating Registers EALLOW Go
2Eh PCLKCR6 Peripheral Clock Gating Registers EALLOW Go
30h PCLKCR7 Peripheral Clock Gating Registers EALLOW Go
32h PCLKCR8 Peripheral Clock Gating Registers EALLOW Go
34h PCLKCR9 Peripheral Clock Gating Registers EALLOW Go
36h PCLKCR10 Peripheral Clock Gating Registers EALLOW Go
38h PCLKCR11 Peripheral Clock Gating Registers EALLOW Go
3Ah PCLKCR12 Peripheral Clock Gating Registers EALLOW Go
3Ch PCLKCR13 Peripheral Clock Gating Registers EALLOW Go
3Eh PCLKCR14 Peripheral Clock Gating Registers EALLOW Go
42h PCLKCR16 Peripheral Clock Gating Registers EALLOW Go
74h SECMSEL Secondary Master Select register for common EALLOW Go
peripherals: Selects between CLA & DMA
76h LPMCR LPM Control Register EALLOW Go
78h GPIOLPMSEL0 GPIO LPM Wakeup select registers EALLOW Go
7Ah GPIOLPMSEL1 GPIO LPM Wakeup select registers EALLOW Go
7Ch TMR2CLKCTL Timer2 Clock Measurement functionality control EALLOW Go
register
80h RESC Reset Cause register Go

Complex bit access types are encoded to fit into small table cells. Table 3-177 shows the codes that are used for
access types in this section.
Table 3-177. CPU_SYS_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1C W Write
1C 1 to clear
W1S W Write
1S 1 to set

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Table 3-177. CPU_SYS_REGS Access Type Codes (continued)

Access Type Code Description
WSonce W Write
Sonce Set once
Reset or Default Value
-n Value after reset or the default value
Register Array Variables
i,j,k,l,m,n When these variables are used in a register name,
an offset, or an address, they refer to the value of a
register array where the register is part of a group
of repeating registers. The register groups form a
hierarchical structure and the array is represented
with a formula.
y When this variable is used in a register name, an
offset, or an address it refers to the value of a
register array.

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3.17.12.1 CPUSYSLOCK1 Register (Offset = 0h) [Reset = 00000000h]

CPUSYSLOCK1 is shown in Figure 3-161 and described in Table 3-178.
Return to the Summary Table.
Lock bit for CPUSYS registers
Notes:
[1] Any bit in this register, once set can only be cleared through a CPU1.SYSRSn. Write of 0 to any bit of this
register has no effect
[2] The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are always
allowed
Figure 3-161. CPUSYSLOCK1 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
GPIOLPMSEL1 GPIOLPMSEL0 LPMCR SECMSEL PCLKCR16 PCLKCR15 PCLKCR14 PCLKCR13
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

15 14 13 12 11 10 9 8
PCLKCR12 PCLKCR11 PCLKCR10 PCLKCR9 PCLKCR8 PCLKCR7 PCLKCR6 PCLKCR5
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

7 6 5 4 3 2 1 0
PCLKCR4 PCLKCR3 PCLKCR2 PCLKCR1 PCLKCR0 PIEVERRADDR IORESTOREA HIBBOOTMOD
DDR E
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

Table 3-178. CPUSYSLOCK1 Register Field Descriptions

Bit Field Type Reset Description
31-24 RESERVED R-0 0h Reserved
23 GPIOLPMSEL1 R/WSonce 0h Lock bit for GPIOLPMSEL1 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
22 GPIOLPMSEL0 R/WSonce 0h Lock bit for GPIOLPMSEL0 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
21 LPMCR R/WSonce 0h Lock bit for LPMCR Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
20 SECMSEL R/WSonce 0h Lock bit for SECMSEL Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
19 PCLKCR16 R/WSonce 0h Lock bit for PCLKCR16 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
18 PCLKCR15 R/WSonce 0h Lock bit for PCLKCR15 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn

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Table 3-178. CPUSYSLOCK1 Register Field Descriptions (continued)

Bit Field Type Reset Description
17 PCLKCR14 R/WSonce 0h Lock bit for PCLKCR14 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
16 PCLKCR13 R/WSonce 0h Lock bit for PCLKCR13 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
15 PCLKCR12 R/WSonce 0h Lock bit for PCLKCR12 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
14 PCLKCR11 R/WSonce 0h Lock bit for PCLKCR11 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
13 PCLKCR10 R/WSonce 0h Lock bit for PCLKCR10 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
12 PCLKCR9 R/WSonce 0h Lock bit for PCLKCR9 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
11 PCLKCR8 R/WSonce 0h Lock bit for PCLKCR8 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
10 PCLKCR7 R/WSonce 0h Lock bit for PCLKCR7 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
9 PCLKCR6 R/WSonce 0h Lock bit for PCLKCR6 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
8 PCLKCR5 R/WSonce 0h Lock bit for PCLKCR5 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
7 PCLKCR4 R/WSonce 0h Lock bit for PCLKCR4 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
6 PCLKCR3 R/WSonce 0h Lock bit for PCLKCR3 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
5 PCLKCR2 R/WSonce 0h Lock bit for PCLKCR2 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
4 PCLKCR1 R/WSonce 0h Lock bit for PCLKCR1 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn

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Table 3-178. CPUSYSLOCK1 Register Field Descriptions (continued)

Bit Field Type Reset Description
3 PCLKCR0 R/WSonce 0h Lock bit for PCLKCR0 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
2 PIEVERRADDR R/WSonce 0h Lock bit for PIEVERRADDR Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
1 IORESTOREADDR R/WSonce 0h Lock bit for IORESTOREADDR Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
0 HIBBOOTMODE R/WSonce 0h Lock bit for HIBBOOTMODE register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn

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3.17.12.2 HIBBOOTMODE Register (Offset = 6h) [Reset = 0000000Fh]

HIBBOOTMODE is shown in Figure 3-162 and described in Table 3-179.
Return to the Summary Table.
HIB Boot Mode Register
Figure 3-162. HIBBOOTMODE Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BMODE
R/W-Fh

Table 3-179. HIBBOOTMODE Register Field Descriptions

Bit Field Type Reset Description
31-0 BMODE R/W Fh This register defined the boot mode on a HIB Wakeup. Its the
responsibility of user to initialize the appropriate boot mode before
going into HIB mode. Refer to the Boot ROM section for more details
on this register
Reset type: POR

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3.17.12.3 IORESTOREADDR Register (Offset = 8h) [Reset = 003FFFFFh]

IORESTOREADDR is shown in Figure 3-163 and described in Table 3-180.
Return to the Summary Table.
IORestore() routine Address Register
Figure 3-163. IORESTOREADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED ADDR
R-0-0h R/W-003FFFFFh

Table 3-180. IORESTOREADDR Register Field Descriptions

Bit Field Type Reset Description
31-22 RESERVED R-0 0h Reserved
21-0 ADDR R/W 003FFFFFh This register defines the address of the restoreIO() routine on a HIB
wakeup. Its the responsibility of user to initialize this register with the
restoreIO() routine address before going into HIB mode. Refer to the
Boot ROM section for more details on this register.
Reset type: POR

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3.17.12.4 PIEVERRADDR Register (Offset = Ah) [Reset = 003FFFFFh]

PIEVERRADDR is shown in Figure 3-164 and described in Table 3-181.
Return to the Summary Table.
PIE Vector Fetch Error Address register
Figure 3-164. PIEVERRADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED ADDR
R-0-0h R/W-003FFFFFh

Table 3-181. PIEVERRADDR Register Field Descriptions

Bit Field Type Reset Description
31-22 RESERVED R-0 0h Reserved
21-0 ADDR R/W 003FFFFFh This register defines the address of the PIE Vector Fetch Error
handler routine. Its the responsibility of user to initialize this register.
If this register is not initialized, a default error handler at address
0x3fffbe will get executed. Refer to the Boot ROM section for more
details on this register.
Reset type: XRSn

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3.17.12.5 PCLKCR0 Register (Offset = 22h) [Reset = 00000038h]

PCLKCR0 is shown in Figure 3-165 and described in Table 3-182.
Return to the Summary Table.
Peripheral Clock Gating Registers
Figure 3-165. PCLKCR0 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED GTBCLKSYNC TBCLKSYNC RESERVED HRPWM
R-0-0h R/W-0h R/W-0h R-0-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED CPUTIMER2 CPUTIMER1 CPUTIMER0 DMA RESERVED CLA1
R-0-0h R/W-1h R/W-1h R/W-1h R/W-0h R/W-0h R/W-0h

Table 3-182. PCLKCR0 Register Field Descriptions

Bit Field Type Reset Description
31-20 RESERVED R-0 0h Reserved
19 GTBCLKSYNC R/W 0h EPWM Time Base Clock Global sync: When set by CPU1, PWM
time bases of all modules start counting. The effect of this bit is seen
on all the EPMW modules irrespective of their partitioning based on
CPUSEL
Notes:
1. This bit on the CPU2.PCLKCR0 register has no effect.
2. Writing '1' to this bit overrides the effect of write '1' to the
TBCLKSYNC bit at the same time
Reset type: SYSRSn
18 TBCLKSYNC R/W 0h EPWM Time Base Clock sync: When set PWM time bases of all
the PWM modules belonging to the same CPU-Subsystem (as
partitioned using their CPUSEL bits) start counting. This bit only
impacts the TBCTR of all EPWM modules. Everything except the
TBCTR of each module enabled in PCLKCR2 will still be clocked by
EPWMCLK.
Notes:
1. This bit from CPU1.PCLKCR0 or CPU2.PCLKCR0 is selected
and fed to the individual EPWM modules based on their respective
CPUSEL bit.
Reset type: SYSRSn
17 RESERVED R-0 0h Reserved
16 HRPWM R/W 0h HRPWM Clock Enable Bit: When set, this enables the clock to the
HRPWM module
1: HRPWM clock is enabled
0: HRPWM clock is disabled
Note:
[1] This bit is present only in CPU1.PCLKCR0. This bit is not used
(R/W) in CPU2.PCLKCR0
Reset type: SYSRSn
15-6 RESERVED R-0 0h Reserved

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Table 3-182. PCLKCR0 Register Field Descriptions (continued)

Bit Field Type Reset Description
5 CPUTIMER2 R/W 1h CPUTIMER2 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
4 CPUTIMER1 R/W 1h CPUTIMER1 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
3 CPUTIMER0 R/W 1h CPUTIMER0 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
2 DMA R/W 0h DMA Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
1 RESERVED R/W 0h Reserved
0 CLA1 R/W 0h CLA1 Clock Enable Bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.17.12.6 PCLKCR1 Register (Offset = 24h) [Reset = 00000000h]

PCLKCR1 is shown in Figure 3-166 and described in Table 3-183.
Return to the Summary Table.
Peripheral Clock Gating Registers
Figure 3-166. PCLKCR1 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED EMIF2 EMIF1
R-0-0h R/W-0h R/W-0h

Table 3-183. PCLKCR1 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-2 RESERVED R-0 0h Reserved
1 EMIF2 R/W 0h EMIF2 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Notes:
[1] These bits are not used (R/W) in CPU2.PCLKCR1 register.
EMIF1 & EMIF2 clock enabled are controlled only from
CPU1.PCLKCR1 register.
Reset type: SYSRSn
0 EMIF1 R/W 0h EMIF1 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Notes:
[1] These bits are not used (R/W) in CPU2.PCLKCR1 register.
EMIF1 & EMIF2 clock enabled are controlled only from
CPU1.PCLKCR1 register.
Reset type: SYSRSn

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3.17.12.7 PCLKCR2 Register (Offset = 26h) [Reset = 00000000h]

PCLKCR2 is shown in Figure 3-167 and described in Table 3-184.
Return to the Summary Table.
Peripheral Clock Gating Registers
Figure 3-167. PCLKCR2 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED EPWM12 EPWM11 EPWM10 EPWM9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
EPWM8 EPWM7 EPWM6 EPWM5 EPWM4 EPWM3 EPWM2 EPWM1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-184. PCLKCR2 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15 RESERVED R/W 0h Reserved
14 RESERVED R/W 0h Reserved
13 RESERVED R/W 0h Reserved
12 RESERVED R/W 0h Reserved
11 EPWM12 R/W 0h EPWM12 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
10 EPWM11 R/W 0h EPWM11 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
9 EPWM10 R/W 0h EPWM10 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
8 EPWM9 R/W 0h EPWM9 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
7 EPWM8 R/W 0h EPWM8 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
6 EPWM7 R/W 0h EPWM7 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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Table 3-184. PCLKCR2 Register Field Descriptions (continued)

Bit Field Type Reset Description
5 EPWM6 R/W 0h EPWM6 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
4 EPWM5 R/W 0h EPWM5 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
3 EPWM4 R/W 0h EPWM4 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Notes:
[1] This bit is also used to enable clocking for CLB4
Reset type: SYSRSn
2 EPWM3 R/W 0h EPWM3 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Notes:
[1] This bit is also used to enable clocking for CLB3
Reset type: SYSRSn
1 EPWM2 R/W 0h EPWM2 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Notes:
[1] This bit is also used to enable clocking for CLB2
Reset type: SYSRSn
0 EPWM1 R/W 0h EPWM1 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Notes:
[1] This bit is also used to enable clocking for CLB1
Reset type: SYSRSn

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3.17.12.8 PCLKCR3 Register (Offset = 28h) [Reset = 00000000h]

PCLKCR3 is shown in Figure 3-168 and described in Table 3-185.
Return to the Summary Table.
Peripheral Clock Gating Registers
Figure 3-168. PCLKCR3 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED ECAP6 ECAP5 ECAP4 ECAP3 ECAP2 ECAP1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-185. PCLKCR3 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-8 RESERVED R-0 0h Reserved
7 RESERVED R/W 0h Reserved
6 RESERVED R/W 0h Reserved
5 ECAP6 R/W 0h ECAP6 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
4 ECAP5 R/W 0h ECAP5 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
3 ECAP4 R/W 0h ECAP4 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
2 ECAP3 R/W 0h ECAP3 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
1 ECAP2 R/W 0h ECAP2 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
0 ECAP1 R/W 0h ECAP1 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.17.12.9 PCLKCR4 Register (Offset = 2Ah) [Reset = 00000000h]

PCLKCR4 is shown in Figure 3-169 and described in Table 3-186.
Return to the Summary Table.
Peripheral Clock Gating Registers
Figure 3-169. PCLKCR4 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED EQEP3 EQEP2 EQEP1
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-186. PCLKCR4 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-4 RESERVED R-0 0h Reserved
3 RESERVED R/W 0h Reserved
2 EQEP3 R/W 0h EQEP3 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
1 EQEP2 R/W 0h EQEP2 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
0 EQEP1 R/W 0h EQEP1 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.17.12.10 PCLKCR6 Register (Offset = 2Eh) [Reset = 00000000h]

PCLKCR6 is shown in Figure 3-170 and described in Table 3-187.
Return to the Summary Table.
Peripheral Clock Gating Registers
Figure 3-170. PCLKCR6 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RESE RESE RESE RESE RESE RESE SD2 SD1
RVED RVED RVED RVED RVED RVED
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-187. PCLKCR6 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-8 RESERVED R-0 0h Reserved
7 RESERVED R/W 0h Reserved
6 RESERVED R/W 0h Reserved
5 RESERVED R/W 0h Reserved
4 RESERVED R/W 0h Reserved
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 SD2 R/W 0h SD2 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
0 SD1 R/W 0h SD1 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.17.12.11 PCLKCR7 Register (Offset = 30h) [Reset = 00000000h]

PCLKCR7 is shown in Figure 3-171 and described in Table 3-188.
Return to the Summary Table.
Peripheral Clock Gating Registers
Figure 3-171. PCLKCR7 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED SCI_D SCI_C SCI_B SCI_A
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-188. PCLKCR7 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-4 RESERVED R-0 0h Reserved
3 SCI_D R/W 0h SCI_D Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
2 SCI_C R/W 0h SCI_C Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
1 SCI_B R/W 0h SCI_B Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
0 SCI_A R/W 0h SCI_A Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.17.12.12 PCLKCR8 Register (Offset = 32h) [Reset = 00000000h]

PCLKCR8 is shown in Figure 3-172 and described in Table 3-189.
Return to the Summary Table.
Peripheral Clock Gating Registers
Figure 3-172. PCLKCR8 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED
R-0-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED SPI_C SPI_B SPI_A
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-189. PCLKCR8 Register Field Descriptions

Bit Field Type Reset Description
31-18 RESERVED R-0 0h Reserved
17 RESERVED R/W 0h Reserved
16 RESERVED R/W 0h Reserved
15-4 RESERVED R-0 0h Reserved
3 RESERVED R/W 0h Reserved
2 SPI_C R/W 0h SPI_C Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
1 SPI_B R/W 0h SPI_B Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
0 SPI_A R/W 0h SPI_A Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.17.12.13 PCLKCR9 Register (Offset = 34h) [Reset = 00000000h]

PCLKCR9 is shown in Figure 3-173 and described in Table 3-190.
Return to the Summary Table.
Peripheral Clock Gating Registers
Figure 3-173. PCLKCR9 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED
R-0-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED I2C_B I2C_A
R-0-0h R/W-0h R/W-0h

Table 3-190. PCLKCR9 Register Field Descriptions

Bit Field Type Reset Description
31-18 RESERVED R-0 0h Reserved
17 RESERVED R/W 0h Reserved
16 RESERVED R/W 0h Reserved
15-2 RESERVED R-0 0h Reserved
1 I2C_B R/W 0h I2C_B Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
0 I2C_A R/W 0h I2C_A Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.17.12.14 PCLKCR10 Register (Offset = 36h) [Reset = 00000000h]

PCLKCR10 is shown in Figure 3-174 and described in Table 3-191.
Return to the Summary Table.
Peripheral Clock Gating Registers
Figure 3-174. PCLKCR10 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED CAN_B CAN_A
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-191. PCLKCR10 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-4 RESERVED R-0 0h Reserved
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 CAN_B R/W 0h CAN_B Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
0 CAN_A R/W 0h CAN_A Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.17.12.15 PCLKCR11 Register (Offset = 38h) [Reset = 00000000h]

PCLKCR11 is shown in Figure 3-175 and described in Table 3-192.
Return to the Summary Table.
Peripheral Clock Gating Registers
Figure 3-175. PCLKCR11 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED USB_A
R-0-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED McBSP_B McBSP_A
R-0-0h R/W-0h R/W-0h

Table 3-192. PCLKCR11 Register Field Descriptions

Bit Field Type Reset Description
31-18 RESERVED R-0 0h Reserved
17 RESERVED R/W 0h Reserved
16 USB_A R/W 0h USB_A Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Notes:
[1] This bit is not used (R/W) in CPU2.PCLKCR11 register. USB_A
clock enabled is controlled only from CPU1.PCLKCR11 register
Reset type: SYSRSn
15-2 RESERVED R-0 0h Reserved
1 McBSP_B R/W 0h McBSP_B Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
0 McBSP_A R/W 0h McBSP_A Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.17.12.16 PCLKCR12 Register (Offset = 3Ah) [Reset = 00000000h]

PCLKCR12 is shown in Figure 3-176 and described in Table 3-193.
Return to the Summary Table.
Peripheral Clock Gating Registers
Figure 3-176. PCLKCR12 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED uPP_A
R-0-0h R/W-0h R/W-0h

Table 3-193. PCLKCR12 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-2 RESERVED R-0 0h Reserved
1 RESERVED R/W 0h Reserved
0 uPP_A R/W 0h uPP_A Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Notes:
[1]] This bit also affects the uPP message RAM wrapper associated
with the respective uPP module
[2] This bit is not used (R/W) in CPU2.PCLKCR12 register. UPP_A
clock enabled is controlled only from CPU1.PCLKCR12 register
Reset type: SYSRSn

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3.17.12.17 PCLKCR13 Register (Offset = 3Ch) [Reset = 00000000h]

PCLKCR13 is shown in Figure 3-177 and described in Table 3-194.
Return to the Summary Table.
Peripheral Clock Gating Registers
Figure 3-177. PCLKCR13 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED ADC_D ADC_C ADC_B ADC_A
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-194. PCLKCR13 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-4 RESERVED R-0 0h Reserved
3 ADC_D R/W 0h ADC_D Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
2 ADC_C R/W 0h ADC_C Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
1 ADC_B R/W 0h ADC_B Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
0 ADC_A R/W 0h ADC_A Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.17.12.18 PCLKCR14 Register (Offset = 3Eh) [Reset = 00000000h]

PCLKCR14 is shown in Figure 3-178 and described in Table 3-195.
Return to the Summary Table.
Peripheral Clock Gating Registers
Figure 3-178. PCLKCR14 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
CMPSS8 CMPSS7 CMPSS6 CMPSS5 CMPSS4 CMPSS3 CMPSS2 CMPSS1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-195. PCLKCR14 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-8 RESERVED R-0 0h Reserved
7 CMPSS8 R/W 0h CMPSS8 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
6 CMPSS7 R/W 0h CMPSS7 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
5 CMPSS6 R/W 0h CMPSS6 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
4 CMPSS5 R/W 0h CMPSS5 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
3 CMPSS4 R/W 0h CMPSS4 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
2 CMPSS3 R/W 0h CMPSS3 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
1 CMPSS2 R/W 0h CMPSS2 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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Table 3-195. PCLKCR14 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 CMPSS1 R/W 0h CMPSS1 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.17.12.19 PCLKCR16 Register (Offset = 42h) [Reset = 00000000h]

PCLKCR16 is shown in Figure 3-179 and described in Table 3-196.
Return to the Summary Table.
Peripheral Clock Gating Registers
Figure 3-179. PCLKCR16 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED DAC_C DAC_B DAC_A
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED RESERVED
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-196. PCLKCR16 Register Field Descriptions

Bit Field Type Reset Description
31-20 RESERVED R-0 0h Reserved
19 RESERVED R/W 0h Reserved
18 DAC_C R/W 0h Buffered_DAC_C Clock Enable Bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
17 DAC_B R/W 0h Buffered_DAC_B Clock Enable Bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
16 DAC_A R/W 0h Buffered_DAC_A Clock Enable Bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
15-4 RESERVED R-0 0h Reserved
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 RESERVED R/W 0h Reserved
0 RESERVED R/W 0h Reserved

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3.17.12.20 SECMSEL Register (Offset = 74h) [Reset = 00000000h]

SECMSEL is shown in Figure 3-180 and described in Table 3-197.
Return to the Summary Table.
Secondary Master Select register for common peripherals: Selects between CLA & DMA
Figure 3-180. SECMSEL Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED
R-0-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED PF2SEL PF1SEL
R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-197. SECMSEL Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-14 RESERVED R-0 0h Reserved
13-12 RESERVED R/W 0h Reserved
11-10 RESERVED R/W 0h Reserved
9-8 RESERVED R/W 0h Reserved
7-6 RESERVED R/W 0h Reserved
5-4 RESERVED R/W 0h Reserved
3-2 PF2SEL R/W 0h This bit selects whether the dual ported bridge is connected with
DMA or CLA as the secondary master (C28x is always connected as
primary master)
x0: Bridge is connected to CLA
x1: Bridge is connected to DMA
Reset type: SYSRSn
1-0 PF1SEL R/W 0h This bit selects whether the dual ported bridge is connected with
DMA or CLA as the secondary master (C28x is always connected as
primary master)
x0: Bridge is connected to CLA
x1: Bridge is connected to DMA
Reset type: SYSRSn

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3.17.12.21 LPMCR Register (Offset = 76h) [Reset = 000000FCh]

LPMCR is shown in Figure 3-181 and described in Table 3-198.
Return to the Summary Table.
LPM Control Register
Figure 3-181. LPMCR Register
31 30 29 28 27 26 25 24
IOISODIS RESERVED
R/W1S-0h R-0-0h

23 22 21 20 19 18 17 16
RESERVED M0M1MODE
R-0-0h R/W-0h

15 14 13 12 11 10 9 8
WDINTE RESERVED
R/W-0h R-0-0h

7 6 5 4 3 2 1 0
QUALSTDBY LPM
R/W-3Fh R/W-0h

Table 3-198. LPMCR Register Field Descriptions

Bit Field Type Reset Description
31 IOISODIS R/W1S 0h 0: Indicates IO ISOLATION is not turned ON
1: Indicates IO ISOLATION is turned ON. This bit is set one by
hardware ONLY during HIB. This bit cant be set to 1 by software
Writing 0 to this bit has not effect.
Writing 1 to this bit deactivates IO ISOLATION
Notes:
[1] This bit is reserved in the register mapped to CPU2
Reset type: raw-XRSn
30-18 RESERVED R-0 0h Reserved
17-16 M0M1MODE R/W 0h These bit control the state of CPU1's and CPU2's M0 & M1
memories when Device goes into HIB mode.
00: CPUx's M0 & M1 memories ON with low-leakage mode
01: CPUx's M0 & M1 memories OFF
1x: Reserved
Notes:
[1] Low-leakage mode for M0 & M1 memories uses the 'Retention'
feature of the SRAMs.
[2] These bits take effect only when device goes into HIB mode. If
the device is not in HIB mode, the value in this bit doesn't control the
state of CPU1's and CPU2's M0 & M1 memories
Reset type: POR
15 WDINTE R/W 0h When this bit is set to 1, it enables the watchdog interrupt signal to
wake the device from STANDBY mode.
Note:
[1] To use this signal, the user must also enable the WDINTn signal
using the WDENINT bit in the SCSR register. This signal will not
wake the device from HALT mode because the clock to watchdog
module is turned off
Reset type: SYSRSn
14-8 RESERVED R-0 0h Reserved

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Table 3-198. LPMCR Register Field Descriptions (continued)

Bit Field Type Reset Description
7-2 QUALSTDBY R/W 3Fh Select number of OSCCLK clock cycles to qualify the selected inputs
when waking the from STANDBY mode:
000000 = 2 OSCCLKs
000001 = 3 OSCCLKs
......
111111 = 65 OSCCLKs
Note: The LPMCR.QUALSTDBY register should be set to a value
greater than the ratio of INTOSC1/PLLSYSCLK to ensure proper
wake up.
Reset type: SYSRSn
1-0 LPM R/W 0h These bits set the low power mode for the device. Takes effect when
CPU executes the IDLE instruction (when IDLE instruction is out of
EXE Phase of the Pipeline)
00: IDLE Mode
01: STANDBY Mode
10: HALT Mode (treated as STANDBY for CPU2)
11: HIB Mode (treated as STANDBY for CPU2)
Reset type: SYSRSn

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3.17.12.22 GPIOLPMSEL0 Register (Offset = 78h) [Reset = 00000000h]

GPIOLPMSEL0 is shown in Figure 3-182 and described in Table 3-199.
Return to the Summary Table.
GPIO LPM Wakeup select registers
Connects the selected pin to the LPM circuit. Refer to LPM section of the TRM for the wakeup capabilities of the
selected pin.
Figure 3-182. GPIOLPMSEL0 Register
31 30 29 28 27 26 25 24
GPIO31 GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-199. GPIOLPMSEL0 Register Field Descriptions

Bit Field Type Reset Description
31 GPIO31 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
30 GPIO30 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
29 GPIO29 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
28 GPIO28 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
27 GPIO27 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
26 GPIO26 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
25 GPIO25 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
24 GPIO24 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
23 GPIO23 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

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Table 3-199. GPIOLPMSEL0 Register Field Descriptions (continued)

Bit Field Type Reset Description
22 GPIO22 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
21 GPIO21 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
20 GPIO20 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
19 GPIO19 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
18 GPIO18 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
17 GPIO17 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
16 GPIO16 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
15 GPIO15 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
14 GPIO14 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
13 GPIO13 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
12 GPIO12 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
11 GPIO11 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
10 GPIO10 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
9 GPIO9 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
8 GPIO8 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
7 GPIO7 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
6 GPIO6 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

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Table 3-199. GPIOLPMSEL0 Register Field Descriptions (continued)

Bit Field Type Reset Description
5 GPIO5 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
4 GPIO4 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
3 GPIO3 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
2 GPIO2 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
1 GPIO1 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
0 GPIO0 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

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3.17.12.23 GPIOLPMSEL1 Register (Offset = 7Ah) [Reset = 00000000h]

GPIOLPMSEL1 is shown in Figure 3-183 and described in Table 3-200.
Return to the Summary Table.
GPIO LPM Wakeup select registers
Connects the selected pin to the LPM circuit. Refer to LPM section of the TRM for the wakeup capabilities of the
selected pin.
Figure 3-183. GPIOLPMSEL1 Register
31 30 29 28 27 26 25 24
GPIO63 GPIO62 GPIO61 GPIO60 GPIO59 GPIO58 GPIO57 GPIO56
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO55 GPIO54 GPIO53 GPIO52 GPIO51 GPIO50 GPIO49 GPIO48
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO47 GPIO46 GPIO45 GPIO44 GPIO43 GPIO42 GPIO41 GPIO40
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO39 GPIO38 GPIO37 GPIO36 GPIO35 GPIO34 GPIO33 GPIO32
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-200. GPIOLPMSEL1 Register Field Descriptions

Bit Field Type Reset Description
31 GPIO63 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
30 GPIO62 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
29 GPIO61 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
28 GPIO60 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
27 GPIO59 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
26 GPIO58 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
25 GPIO57 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
24 GPIO56 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
23 GPIO55 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

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Table 3-200. GPIOLPMSEL1 Register Field Descriptions (continued)

Bit Field Type Reset Description
22 GPIO54 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
21 GPIO53 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
20 GPIO52 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
19 GPIO51 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
18 GPIO50 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
17 GPIO49 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
16 GPIO48 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
15 GPIO47 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
14 GPIO46 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
13 GPIO45 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
12 GPIO44 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
11 GPIO43 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
10 GPIO42 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
9 GPIO41 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
8 GPIO40 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
7 GPIO39 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
6 GPIO38 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

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Table 3-200. GPIOLPMSEL1 Register Field Descriptions (continued)

Bit Field Type Reset Description
5 GPIO37 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
4 GPIO36 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
3 GPIO35 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
2 GPIO34 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
1 GPIO33 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
0 GPIO32 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

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3.17.12.24 TMR2CLKCTL Register (Offset = 7Ch) [Reset = 00000000h]

TMR2CLKCTL is shown in Figure 3-184 and described in Table 3-201.
Return to the Summary Table.
Timer2 Clock Measurement functionality control register
This memory mapped register requires a delay of 69 SYSCLK cycles between subsequent writes to the register,
otherwise a second write can be lost. This delay can be realized by adding 69 NOP instructions.
Figure 3-184. TMR2CLKCTL Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED TMR2CLKPRESCALE TMR2CLKSRCSEL
R-0-0h R/W-0h R/W-0h

Table 3-201. TMR2CLKCTL Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-6 RESERVED R-0 0h Reserved
5-3 TMR2CLKPRESCALE R/W 0h CPU Timer 2 Clock Pre-Scale Value: These bits select the pre-scale
value for the selected clock source for CPU Timer 2:
0,0,0,/1 (default on reset)
0,0,1,/2,
0,1,0,/4
0,1,1,/8
1,0,0,/16
1,0,1,spare (defaults to /16)
1,1,0,spare (defaults to /16)
1,1,1,spare (defaults to /16)
Note:
[1] The CPU Timer2s Clock sync logic detects an input clock edge
when configured for any clock source other than SYSCLK and
generates an appropriate clock pulse to the CPU timer2. If SYSCLK
is approximately the same or less then the input clock source, then
the user would need to configure the pre-scale value such that
SYSCLK is at least twice as fast as the pre-scaled value.
[2] Pre-scaler is bypassed if SYSCLK is selected as the source of
CPU Timer 2 in TMR2CLKSRCSEL of TMR2CLKCTL.
Reset type: SYSRSn

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Table 3-201. TMR2CLKCTL Register Field Descriptions (continued)

Bit Field Type Reset Description
2-0 TMR2CLKSRCSEL R/W 0h CPU Timer 2 Clock Source Select Bit: This bit selects the source for
CPU Timer 2:
000 =SYSCLK Selected (default on reset, pre-scale is bypassed)
001 = INTOSC1
010 = INTOSC2
011 = XTAL
100 = Reserved
101 = Reserved
110 = AUXPLLCLK
111 = reserved
Reset type: SYSRSn

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3.17.12.25 RESC Register (Offset = 80h) [Reset = 00000003h]

RESC is shown in Figure 3-185 and described in Table 3-202.
Return to the Summary Table.
Reset Cause register
Figure 3-185. RESC Register
31 30 29 28 27 26 25 24
TRSTn_pin_stat XRSn_pin_statu RESERVED
us s
R-0h R-0h R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED SCCRESETn
R-0-0h R/W1C-0h

7 6 5 4 3 2 1 0
RESERVED HIBRESETn HWBISTn RESERVED NMIWDRSn WDRSn XRSn POR
R-0-0h R/W1C-0h R/W1C-0h R-0-0h R/W1C-0h R/W1C-0h R/W1C-1h R/W1C-1h

Table 3-202. RESC Register Field Descriptions

Bit Field Type Reset Description
31 TRSTn_pin_status R 0h Reading this bit provides the current status of TRSTn at the
respective C28x CPUs TRSTn input port. Reset value is reflective
of the pin status.
Reset type: N/A
30 XRSn_pin_status R 0h Reading this bit provides the current status of the XRSn pin. Reset
value is reflective of the pin status.
Reset type: N/A
29-16 RESERVED R-0 0h Reserved
15-9 RESERVED R-0 0h Reserved
8 SCCRESETn R/W1C 0h If this bit is set, indicates that the device was reset by SCCRESETn
(fired by DCSM).
Writing a 1 to this bit will force the bit to 0
Writing of 0 will have no effect.
Reset type: POR
7 RESERVED R-0 0h Reserved
6 HIBRESETn R/W1C 0h If this bit is set, indicates that the device was reset due to a
Hibernate mode Wakeup.
Writing a 1 to this bit will force the bit to 0
Writing of 0 will have no effect.
Reset type: raw-XRSn
5 HWBISTn R/W1C 0h If this bit is set, indicates that the device was reset by HWBIST.
Writing a 1 to this bit will force the bit to 0
Writing of 0 will have no effect.
Reset type: POR
4 RESERVED R-0 0h Reserved

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Table 3-202. RESC Register Field Descriptions (continued)

Bit Field Type Reset Description
3 NMIWDRSn R/W1C 0h If this bit is set, indicates that the device was reset by NMIWDRSn.
Writing a 1 to this bit will force the bit to 0
Writing of 0 will have no effect.
To know the exact cause of NMI after the reset, software needs to
read CPU1/2.NMISHDFLG registers
Reset type: POR
2 WDRSn R/W1C 0h If this bit is set, indicates that the device was reset by WDRSn.
Writing a 1 to this bit will force the bit to 0
Writing of 0 will have no effect.
Reset type: POR
1 XRSn R/W1C 1h If this bit is set, indicates that the device was reset by XRSn.
Writing a 1 to this bit will force the bit to 0
Writing of 0 will have no effect.
Reset type: POR
0 POR R/W1C 1h If this bit is set, indicates that the device was reset by PORn. This bit
is cleared by the Boot-ROM. As such, this bit cannot be used by the
application to determine a POR.
Writing a 1 to this bit will force the bit to 0
Writing of 0 will have no effect.
Reset type: POR

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3.17.13 ROM_PREFETCH_REGS Registers

Table 3-203 lists the memory-mapped registers for the ROM_PREFETCH_REGS registers. All register offset
addresses not listed in Table 3-203 should be considered as reserved locations and the register contents should
not be modified.
Table 3-203. ROM_PREFETCH_REGS Registers
Offset Acronym Register Name Write Protection Section
0h ROMPREFETCH ROM Prefetch Configuration Register EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 3-204 shows the codes that are used for
access types in this section.
Table 3-204. ROM_PREFETCH_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default value
Register Array Variables
i,j,k,l,m,n When these variables are used in a register name,
an offset, or an address, they refer to the value of a
register array where the register is part of a group
of repeating registers. The register groups form a
hierarchical structure and the array is represented
with a formula.
y When this variable is used in a register name, an
offset, or an address it refers to the value of a
register array.

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3.17.13.1 ROMPREFETCH Register (Offset = 0h) [Reset = 00000000h]

ROMPREFETCH is shown in Figure 3-186 and described in Table 3-205.
Return to the Summary Table.
ROM Prefetch Configuration Register
Figure 3-186. ROMPREFETCH Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED PFENABLE
R-0h R/W-0h

Table 3-205. ROMPREFETCH Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-1 RESERVED R 0h Reserved
0 PFENABLE R/W 0h 0: Prefetch is disabled for secure ROM and boot ROM.
1: Prefetch is enabled for secure ROM and boot ROM.
Reset type: SYSRSn

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3.17.14 DCSM_Z1_REGS Registers

Table 3-206 lists the memory-mapped registers for the DCSM_Z1_REGS registers. All register offset addresses
not listed in Table 3-206 should be considered as reserved locations and the register contents should not be
modified.
Table 3-206. DCSM_Z1_REGS Registers
Offset Acronym Register Name Write Protection Section
0h Z1_LINKPOINTER Zone 1 Link Pointer Go
2h Z1_OTPSECLOCK Zone 1 OTP Secure JTAG lock Go
4h Z1_BOOTCTRL Boot Mode Go
6h Z1_LINKPOINTERERR Link Pointer Error Go
10h Z1_CSMKEY0 Zone 1 CSM Key 0 Go
12h Z1_CSMKEY1 Zone 1 CSM Key 1 Go
14h Z1_CSMKEY2 Zone 1 CSM Key 2 Go
16h Z1_CSMKEY3 Zone 1 CSM Key 3 Go
19h Z1_CR Zone 1 CSM Control Register Go
1Ah Z1_GRABSECTR Zone 1 Grab Flash Sectors Register Go
1Ch Z1_GRABRAMR Zone 1 Grab RAM Blocks Register Go
1Eh Z1_EXEONLYSECTR Zone 1 Flash Execute_Only Sector Register Go
20h Z1_EXEONLYRAMR Zone 1 RAM Execute_Only Block Register Go

Complex bit access types are encoded to fit into small table cells. Table 3-207 shows the codes that are used for
access types in this section.
Table 3-207. DCSM_Z1_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default value
Register Array Variables
i,j,k,l,m,n When these variables are used in a register name,
an offset, or an address, they refer to the value of a
register array where the register is part of a group
of repeating registers. The register groups form a
hierarchical structure and the array is represented
with a formula.
y When this variable is used in a register name, an
offset, or an address it refers to the value of a
register array.

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3.17.14.1 Z1_LINKPOINTER Register (Offset = 0h) [Reset = E0000000h]

Z1_LINKPOINTER is shown in Figure 3-187 and described in Table 3-208.
Return to the Summary Table.
Zone 1 Link Pointer
Figure 3-187. Z1_LINKPOINTER Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED LINKPOINTER
R-7h R-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINKPOINTER
R-0h

Table 3-208. Z1_LINKPOINTER Register Field Descriptions

Bit Field Type Reset Description
31-29 RESERVED R 7h Reserved
28-0 LINKPOINTER R 0h This is resolved Link-Pointer value which is generated by looking at
the three physical Link-Pointer values loaded from OTP.
Reset type: SYSRSn

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3.17.14.2 Z1_OTPSECLOCK Register (Offset = 2h) [Reset = 00000FFFh]

Z1_OTPSECLOCK is shown in Figure 3-188 and described in Table 3-209.
Return to the Summary Table.
Zone 1 OTP Secure JTAG lock
Figure 3-188. Z1_OTPSECLOCK Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED CRCLOCK PSWDLOCK JTAGLOCK
R-0h R-Fh R-Fh R-Fh

Table 3-209. Z1_OTPSECLOCK Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-12 RESERVED R 0h Reserved
11-8 CRCLOCK R Fh Value in this field gets loaded from Z1_CRCLOCK[3:0] when a read
is issued to address location of Z1_CRCLOCK in OTP.
1111 : VCU has ability to calculate CRC on secure memories.
Other Value : VCU doesn't have ability to calculate CRC on secure
memories.
Reset type: SYSRSn
7-4 PSWDLOCK R Fh Value in this field gets loaded from Z1_PSWDLOCK[3:0] when a
read is issued to address location of Z1_PSWDLOCK in OTP.
1111 : CSM password locations in OTP are not protected and can be
read from debugger as well as code running from anywhere.
Other Value : CSM password locations in OTP are protected and
can't be read without unlocking CSM of that zone.
Reset type: SYSRSn
3-0 JTAGLOCK R Fh Value in this field gets loaded from Z1_JTAGLOCK[3:0] when a read
is issued to address location of Z1_JTAGLOCK in OTP.
1111 : JTAG/Emulation access is allowed.
Other Value : JTAG/Emulation access not allowed.
Reset type: SYSRSn

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3.17.14.3 Z1_BOOTCTRL Register (Offset = 4h) [Reset = 00000000h]

Z1_BOOTCTRL is shown in Figure 3-189 and described in Table 3-210.
Return to the Summary Table.
Boot Mode
Figure 3-189. Z1_BOOTCTRL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOOTPIN1 BOOTPIN0 BMODE KEY
R-0h R-0h R-0h R-0h

Table 3-210. Z1_BOOTCTRL Register Field Descriptions

Bit Field Type Reset Description
31-24 BOOTPIN1 R 0h This field gets loaded with Z1_BOOTCTRL[31:24] when a dummy
read is issued to address location of Z1_BOOTCTRL in OTP.
This assigns the pin to be used as BOOTPIN1.
0 : Pick default bootmode pin.
1 : Pick GPIO0 as BOOTPIN1.
2 : Pick GPIO1 as BOOTPIN1.
....
....
n : Pick GPIOn-1 as BOOTPIN1.
Reset type: SYSRSn
23-16 BOOTPIN0 R 0h This field gets loaded with Z1_BOOTCTRL[23:16] when a dummy
read is issued to address location of Z1_BOOTCTRL in OTP.
This assigns the pin to be used as BOOTPIN1.
0 : Pick default bootmode pin.
1 : Pick GPIO0 as BOOTPIN1.
2 : Pick GPIO1 as BOOTPIN1.
....
....
n : Pick GPIOn-1 as BOOTPIN1.
Reset type: SYSRSn
15-8 BMODE R 0h This field gets loaded with Z1_BOOTCTRL[15:8] when a dummy
read is issued to address location of Z1_BOOTCTRL in OTP.
Reset type: SYSRSn
7-0 KEY R 0h This field gets loaded with Z1_BOOTCTRL[7:0] when a dummy read
is issued to address location of Z1_BOOTCTRL in OTP.
Reset type: SYSRSn

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3.17.14.4 Z1_LINKPOINTERERR Register (Offset = 6h) [Reset = FFFFFFFFh]

Z1_LINKPOINTERERR is shown in Figure 3-190 and described in Table 3-211.
Return to the Summary Table.
Link Pointer Error
Figure 3-190. Z1_LINKPOINTERERR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1_LINKPOINTERERR
R-FFFFFFFFh

Table 3-211. Z1_LINKPOINTERERR Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1_LINKPOINTERERR R FFFFFFFFh These bits indicate errors during formation of the resolved Link-
Pointer value after the three physical Link-Pointer values loaded of
OTP.
0 : No Error.
Other : Error on bit positions which is set to 1.
Reset type: SYSRSn

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3.17.14.5 Z1_CSMKEY0 Register (Offset = 10h) [Reset = 00000000h]

Z1_CSMKEY0 is shown in Figure 3-191 and described in Table 3-212.
Return to the Summary Table.
Zone 1 CSM Key 0
Figure 3-191. Z1_CSMKEY0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1_CSMKEY0
R-0h

Table 3-212. Z1_CSMKEY0 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1_CSMKEY0 R 0h To unclock Zone1, user needs to write this regsiter with exact value
as Z1_CSMPSWD0, programmed in OTP (zone gets unlock only if
128 bit password in OTP match with value written in four CSMKEY
registers.)
Reset type: SYSRSn

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3.17.14.6 Z1_CSMKEY1 Register (Offset = 12h) [Reset = 00000000h]

Z1_CSMKEY1 is shown in Figure 3-192 and described in Table 3-213.
Return to the Summary Table.
Zone 1 CSM Key 1
Figure 3-192. Z1_CSMKEY1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1_CSMKEY1
R-0h

Table 3-213. Z1_CSMKEY1 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1_CSMKEY1 R 0h To unclock Zone1, user needs to write this regsiter with exact value
as Z1_CSMPSWD1, programmed in OTP (zone gets unlock only if
128 bit password in OTP match with value written in four CSMKEY
registers.)
Reset type: SYSRSn

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3.17.14.7 Z1_CSMKEY2 Register (Offset = 14h) [Reset = 00000000h]

Z1_CSMKEY2 is shown in Figure 3-193 and described in Table 3-214.
Return to the Summary Table.
Zone 1 CSM Key 2
Figure 3-193. Z1_CSMKEY2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1_CSMKEY2
R-0h

Table 3-214. Z1_CSMKEY2 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1_CSMKEY2 R 0h To unclock Zone1, user needs to write this regsiter with exact value
as Z1_CSMPSWD2, programmed in OTP (zone gets unlock only if
128 bit password in OTP match with value written in four CSMKEY
registers.)
Reset type: SYSRSn

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3.17.14.8 Z1_CSMKEY3 Register (Offset = 16h) [Reset = 00000000h]

Z1_CSMKEY3 is shown in Figure 3-194 and described in Table 3-215.
Return to the Summary Table.
Zone 1 CSM Key 3
Figure 3-194. Z1_CSMKEY3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1_CSMKEY3
R-0h

Table 3-215. Z1_CSMKEY3 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1_CSMKEY3 R 0h To unclock Zone1, user needs to write this regsiter with exact value
as Z1_CSMPSWD3, programmed in OTP (zone gets unlock only if
128 bit password in OTP match with value written in four CSMKEY
registers.)
Reset type: SYSRSn

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3.17.14.9 Z1_CR Register (Offset = 19h) [Reset = 0008h]

Z1_CR is shown in Figure 3-195 and described in Table 3-216.
Return to the Summary Table.
Zone 1 CSM Control Register
Figure 3-195. Z1_CR Register
15 14 13 12 11 10 9 8
FORCESEC RESERVED
R-0/W-0h R-0h

7 6 5 4 3 2 1 0
RESERVED ARMED UNSECURE ALLONE ALLZERO RESERVED
R-0h R-0h R-0h R-0h R-1h R-0h

Table 3-216. Z1_CR Register Field Descriptions

Bit Field Type Reset Description
15 FORCESEC R-0/W 0h A write '1' to this fields resets the state of zone. If zone is unlocked,
it'll lock(secure) the zone and also resets all the bits in this register.
Reset type: SYSRSn
14-8 RESERVED R 0h Reserved
7 RESERVED R 0h Reserved
6 ARMED R 0h 0 : Dummy read to CSM Password locations in OTP hasn't been
performed.
1 : Dummy read to CSM Password locations in OTP has been
performed.
Reset type: SYSRSn
5 UNSECURE R 0h Indiacates the state of Zone.
0 : Zone is in lock(secure) state.
1 : Zone is in unlock(unsecure) state.
Reset type: SYSRSn
4 ALLONE R 0h Indicates the state of CSM passowrds.
0 : CSM Passwords are not all ones.
1 : CSM Passwords are all ones and zone is in unlock state.
Reset type: SYSRSn
3 ALLZERO R 1h Indicates the state of CSM passowrds.
0 : CSM Passwords are not all zeros.
1 : CSM Passwords are all zero and device is permanently locked.
Reset type: SYSRSn
2-0 RESERVED R 0h Reserved

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3.17.14.10 Z1_GRABSECTR Register (Offset = 1Ah) [Reset = 00000000h]

Z1_GRABSECTR is shown in Figure 3-196 and described in Table 3-217.
Return to the Summary Table.
Zone 1 Grab Flash Sectors Register
Figure 3-196. Z1_GRABSECTR Register
31 30 29 28 27 26 25 24
RESERVED RESERVED GRAB_SECTN GRAB_SECTM
R-0h R-0h R-0h R-0h

23 22 21 20 19 18 17 16
GRAB_SECTL GRAB_SECTK GRAB_SECTJ GRAB_SECTI
R-0h R-0h R-0h R-0h

15 14 13 12 11 10 9 8
GRAB_SECTH GRAB_SECTG GRAB_SECTF GRAB_SECTE
R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
GRAB_SECTD GRAB_SECTC GRAB_SECTB GRAB_SECTA
R-0h R-0h R-0h R-0h

Table 3-217. Z1_GRABSECTR Register Field Descriptions

Bit Field Type Reset Description
31-30 RESERVED R 0h Reserved
29-28 RESERVED R 0h Reserved
27-26 GRAB_SECTN R 0h Value in this field gets loaded from Z1_GRABSECT[27:26] when a
read is issued to address location of Z1_GRABSECT in OTP.
00 : Invalid. Flash Sector N is inaccessible.
01 : Request to allocate Flash Sector N to Zone1.
10 : Request to allocate Flash Sector N to Zone1.
11 : Request to make Flash sector N Non-Secure.
Reset type: SYSRSn
25-24 GRAB_SECTM R 0h Value in this field gets loaded from Z1_GRABSECT[25:24] when a
read is issued to address location of Z1_GRABSECT in OTP.
00 : Invalid. Flash Sector M is inaccessible.
01 : Request to allocate Flash Sector M to Zone1.
10 : Request to allocate Flash Sector M to Zone1.
11 : Request to make Flash sector M Non-Secure.
Reset type: SYSRSn
23-22 GRAB_SECTL R 0h Value in this field gets loaded from Z1_GRABSECT[23:22] when a
read is issued to address location of Z1_GRABSECT in OTP.
00 : Invalid. Flash Sector L is inaccessible.
01 : Request to allocate Flash Sector L to Zone1.
10 : Request to allocate Flash Sector L to Zone1.
11 : Request to make Flash sector L Non-Secure.
Reset type: SYSRSn
21-20 GRAB_SECTK R 0h Value in this field gets loaded from Z1_GRABSECT[21:20] when a
read is issued to address location of Z1_GRABSECT in OTP.
00 : Invalid. Flash Sector K is inaccessible.
01 : Request to allocate Flash Sector K to Zone1.
10 : Request to allocate Flash Sector K to Zone1.
11 : Request to make Flash sector K Non-Secure.
Reset type: SYSRSn

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Table 3-217. Z1_GRABSECTR Register Field Descriptions (continued)

Bit Field Type Reset Description
19-18 GRAB_SECTJ R 0h Value in this field gets loaded from Z1_GRABSECT[19:18] when a
read is issued to address location of Z1_GRABSECT in OTP.
00 : Invalid. Flash Sector J is inaccessible.
01 : Request to allocate Flash Sector J to Zone1.
10 : Request to allocate Flash Sector J to Zone1.
11 : Request to make Flash sector J Non-Secure.
Reset type: SYSRSn
17-16 GRAB_SECTI R 0h Value in this field gets loaded from Z1_GRABSECT[17:16] when a
read is issued to address location of Z1_GRABSECT in OTP.
00 : Invalid. Flash Sector I is inaccessible.
01 : Request to allocate Flash Sector I to Zone1.
10 : Request to allocate Flash Sector I to Zone1.
11 : Request to make Flash sector I Non-Secure.
Reset type: SYSRSn
15-14 GRAB_SECTH R 0h Value in this field gets loaded from Z1_GRABSECT[15:14] when a
read is issued to address location of Z1_GRABSECT in OTP.
00 : Invalid. Flash Sector H is inaccessible.
01 : Request to allocate Flash Sector H to Zone1.
10 : Request to allocate Flash Sector H to Zone1.
11 : Request to make Flash sector H Non-Secure.
Reset type: SYSRSn
13-12 GRAB_SECTG R 0h Value in this field gets loaded from Z1_GRABSECT[13:12] when a
read is issued to address location of Z1_GRABSECT in OTP.
00 : Invalid. Flash Sector G is inaccessible.
01 : Request to allocate Flash Sector G to Zone1.
10 : Request to allocate Flash Sector G to Zone1.
11 : Request to make Flash sector G Non-Secure.
Reset type: SYSRSn
11-10 GRAB_SECTF R 0h Value in this field gets loaded from Z1_GRABSECT[11:10] when a
read is issued to address location of Z1_GRABSECT in OTP.
00 : Invalid. Flash Sector F is inaccessible.
01 : Request to allocate Flash Sector F to Zone1.
10 : Request to allocate Flash Sector F to Zone1.
11 : Request to make Flash sector F Non-Secure.
Reset type: SYSRSn
9-8 GRAB_SECTE R 0h Value in this field gets loaded from Z1_GRABSECT[9:8] when a read
is issued to address location of Z1_GRABSECT in OTP.
00 : Invalid. Flash Sector E is inaccessible.
01 : Request to allocate Flash Sector E to Zone1.
10 : Request to allocate Flash Sector E to Zone1.
11 : Request to make Flash sector E Non-Secure.
Reset type: SYSRSn
7-6 GRAB_SECTD R 0h Value in this field gets loaded from Z1_GRABSECT[7:6] when a read
is issued to address location of Z1_GRABSECT in OTP.
00 : Invalid. Flash Sector D is inaccessible.
01 : Request to allocate Flash Sector D to Zone1.
10 : Request to allocate Flash Sector D to Zone1.
11 : Request to make Flash sector D Non-Secure.
Reset type: SYSRSn
5-4 GRAB_SECTC R 0h Value in this field gets loaded from Z1_GRABSECT[5:4] when a read
is issued to address location of Z1_GRABSECT in OTP.
00 : Invalid. Flash Sector C is inaccessible.
01 : Request to allocate Flash Sector C to Zone1.
10 : Request to allocate Flash Sector C to Zone1.
11 : Request to make Flash sector C Non-Secure.
Reset type: SYSRSn

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Table 3-217. Z1_GRABSECTR Register Field Descriptions (continued)

Bit Field Type Reset Description
3-2 GRAB_SECTB R 0h Value in this field gets loaded from Z1_GRABSECT[3:2] when a read
is issued to address location of Z1_GRABSECT in OTP.
00 : Invalid. Flash Sector B is inaccessible.
01 : Request to allocate Flash Sector B to Zone1.
10 : Request to allocate Flash Sector B to Zone1.
11 : Request to make Flash sector B Non-Secure.
Reset type: SYSRSn
1-0 GRAB_SECTA R 0h Value in this field gets loaded from Z1_GRABSECT[1:0] when a read
is issued to address location of Z1_GRABSECT in OTP.
00 : Invalid. Flash Sector A is inaccessible.
01 : Request to allocate Flash Sector A to Zone1.
10 : Request to allocate Flash Sector A to Zone1.
11 : Request to make Flash sector A Non-Secure.
Reset type: SYSRSn

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3.17.14.11 Z1_GRABRAMR Register (Offset = 1Ch) [Reset = 00000000h]

Z1_GRABRAMR is shown in Figure 3-197 and described in Table 3-218.
Return to the Summary Table.
Zone 1 Grab RAM Blocks Register
Figure 3-197. Z1_GRABRAMR Register
31 30 29 28 27 26 25 24
RESERVED GRAB_CLA1 RESERVED
R-0h R-0h R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
GRAB_RAM7 GRAB_RAM6 GRAB_RAM5 GRAB_RAM4
R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
GRAB_RAM3 GRAB_RAM2 GRAB_RAM1 GRAB_RAM0
R-0h R-0h R-0h R-0h

Table 3-218. Z1_GRABRAMR Register Field Descriptions

Bit Field Type Reset Description
31-30 RESERVED R 0h Reserved
29-28 GRAB_CLA1 R 0h Value in this field gets loaded from Z1_GRABRAM[29:28] when a
read is issued to address location of Z1_GRABRAM in OTP.
00 : Invalid. CLA1 is inaccessible.
01 : Request to allocate CLA1 to Zone1.
10 : Request to allocate CLA1 to Zone1.
11 : Request to make CLA1 Non-Secure.
Reset type: SYSRSn
27-16 RESERVED R 0h Reserved
15-14 GRAB_RAM7 R 0h Value in this field gets loaded from Z1_GRABRAM[15:14] when a
read is issued to address location of Z1_GRABRAM in OTP.
00 : Invalid. D1 RAM is inaccessible.
01 : Request to allocate D1 RAM to Zone1.
10 : Request to allocate D1 RAM to Zone1.
11 : Request to make D1 RAM Non-Secure.
Reset type: SYSRSn
13-12 GRAB_RAM6 R 0h Value in this field gets loaded from Z1_GRABRAM[13:12] when a
read is issued to address location of Z1_GRABRAM in OTP.
00 : Invalid. D0 RAM is inaccessible.
01 : Request to allocate D0 RAM to Zone1.
10 : Request to allocate D0 RAM to Zone1.
11 : Request to make D0 RAM Non-Secure.
Reset type: SYSRSn
11-10 GRAB_RAM5 R 0h Value in this field gets loaded from Z1_GRABRAM[11:10] when a
read is issued to address location of Z1_GRABRAM in OTP.
00 : Invalid. LS5 RAM is inaccessible.
01 : Request to allocate LS5 RAM to Zone1.
10 : Request to allocate LS5 RAM to Zone1.
11 : Request to make LS5 RAM Non-Secure.
Reset type: SYSRSn

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Table 3-218. Z1_GRABRAMR Register Field Descriptions (continued)

Bit Field Type Reset Description
9-8 GRAB_RAM4 R 0h Value in this field gets loaded from Z1_GRABRAM[9:8] when a read
is issued to address location of Z1_GRABRAM in OTP.
00 : Invalid. LS4 RAM is inaccessible.
01 : Request to allocate LS4 RAM to Zone1.
10 : Request to allocate LS4 RAM to Zone1.
11 : Request to make LS4 RAM Non-Secure.
Reset type: SYSRSn
7-6 GRAB_RAM3 R 0h Value in this field gets loaded from Z1_GRABRAM[7:6] when a read
is issued to address location of Z1_GRABRAM in OTP.
00 : Invalid. LS3 RAM is inaccessible.
01 : Request to allocate LS3 RAM to Zone1.
10 : Request to allocate LS3 RAM to Zone1.
11 : Request to make LS3 RAM Non-Secure.
Reset type: SYSRSn
5-4 GRAB_RAM2 R 0h Value in this field gets loaded from Z1_GRABRAM[5:4] when a read
is issued to address location of Z1_GRABRAM in OTP.
00 : Invalid. LS2 RAM is inaccessible.
01 : Request to allocate LS2 RAM to Zone1.
10 : Request to allocate LS2 RAM to Zone1.
11 : Request to make LS2 RAM Non-Secure.
Reset type: SYSRSn
3-2 GRAB_RAM1 R 0h Value in this field gets loaded from Z1_GRABRAM[3:2] when a read
is issued to address location of Z1_GRABRAM in OTP.
00 : Invalid. LS1 RAM is inaccessible.
01 : Request to allocate LS1 RAM to Zone1.
10 : Request to allocate LS1 RAM to Zone1.
11 : Request to make LS1 RAM Non-Secure.
Reset type: SYSRSn
1-0 GRAB_RAM0 R 0h Value in this field gets loaded from Z1_GRABRAM[1:0] when a read
is issued to address location of Z1_GRABRAM in OTP.
00 : Invalid. LS0 RAM is inaccessible.
01 : Request to allocate LS0 RAM to Zone1.
10 : Request to allocate LS0 RAM to Zone1.
11 : Request to make LS0 RAM Non-Secure.
Reset type: SYSRSn

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3.17.14.12 Z1_EXEONLYSECTR Register (Offset = 1Eh) [Reset = 00000000h]

Z1_EXEONLYSECTR is shown in Figure 3-198 and described in Table 3-219.
Return to the Summary Table.
Zone 1 Flash Execute_Only Sector Register
Figure 3-198. Z1_EXEONLYSECTR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED EXEONLY_SE EXEONLY_SE EXEONLY_SE EXEONLY_SE EXEONLY_SE EXEONLY_SE
CTN CTM CTL CTK CTJ CTI
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
EXEONLY_SE EXEONLY_SE EXEONLY_SE EXEONLY_SE EXEONLY_SE EXEONLY_SE EXEONLY_SE EXEONLY_SE
CTH CTG CTF CTE CTD CTC CTB CTA
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 3-219. Z1_EXEONLYSECTR Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15 RESERVED R 0h Reserved
14 RESERVED R 0h Reserved
13 EXEONLY_SECTN R 0h Value in this field gets loaded from Z1_EXEONLYSECT[13:13] when
a read is issued to Z1_EXEONLYSECT address location in OTP.
0 : Execute-Only protection is enabled for Flash Sector N (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for Flash Sector N (only if it's
allocated to Zone1)
Reset type: SYSRSn
12 EXEONLY_SECTM R 0h Value in this field gets loaded from Z1_EXEONLYSECT[12:12] when
a read is issued to Z1_EXEONLYSECT address location in OTP.
0 : Execute-Only protection is enabled for Flash Sector M (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for Flash Sector M (only if it's
allocated to Zone1)
Reset type: SYSRSn
11 EXEONLY_SECTL R 0h Value in this field gets loaded from Z1_EXEONLYSECT[11:11] when
a read is issued to Z1_EXEONLYSECT address location in OTP.
0 : Execute-Only protection is enabled for Flash Sector L (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for Flash Sector L (only if it's
allocated to Zone1)
Reset type: SYSRSn
10 EXEONLY_SECTK R 0h Value in this field gets loaded from Z1_EXEONLYSECT[10:10] when
a read is issued to Z1_EXEONLYSECT address location in OTP.
0 : Execute-Only protection is enabled for Flash Sector K (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for Flash Sector K (only if it's
allocated to Zone1)
Reset type: SYSRSn

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Table 3-219. Z1_EXEONLYSECTR Register Field Descriptions (continued)

Bit Field Type Reset Description
9 EXEONLY_SECTJ R 0h Value in this field gets loaded from Z1_EXEONLYSECT[9:9] when a
read is issued to Z1_EXEONLYSECT address location in OTP.
0 : Execute-Only protection is enabled for Flash Sector J (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for Flash Sector J (only if it's
allocated to Zone1)
Reset type: SYSRSn
8 EXEONLY_SECTI R 0h Value in this field gets loaded from Z1_EXEONLYSECT[8:8] when a
read is issued to Z1_EXEONLYSECT address location in OTP.
0 : Execute-Only protection is enabled for Flash Sector I (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for Flash Sector I (only if it's
allocated to Zone1)
Reset type: SYSRSn
7 EXEONLY_SECTH R 0h Value in this field gets loaded from Z1_EXEONLYSECT[7:7] when a
read is issued to Z1_EXEONLYSECT address location in OTP.
0 : Execute-Only protection is enabled for Flash Sector H (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for Flash Sector H (only if it's
allocated to Zone1)
Reset type: SYSRSn
6 EXEONLY_SECTG R 0h Value in this field gets loaded from Z1_EXEONLYSECT[6:6] when a
read is issued to Z1_EXEONLYSECT address location in OTP.
0 : Execute-Only protection is enabled for Flash Sector G (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for Flash Sector G (only if it's
allocated to Zone1)
Reset type: SYSRSn
5 EXEONLY_SECTF R 0h Value in this field gets loaded from Z1_EXEONLYSECT[5:5] when a
read is issued to Z1_EXEONLYSECT address location in OTP.
0 : Execute-Only protection is enabled for Flash Sector F (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for Flash Sector F (only if it's
allocated to Zone1)
Reset type: SYSRSn
4 EXEONLY_SECTE R 0h Value in this field gets loaded from Z1_EXEONLYSECT[4:4] when a
read is issued to Z1_EXEONLYSECT address location in OTP.
0 : Execute-Only protection is enabled for Flash Sector E (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for Flash Sector E (only if it's
allocated to Zone1)
Reset type: SYSRSn
3 EXEONLY_SECTD R 0h Value in this field gets loaded from Z1_EXEONLYSECT[3:3] when a
read is issued to Z1_EXEONLYSECT address location in OTP.
0 : Execute-Only protection is enabled for Flash Sector D (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for Flash Sector D (only if it's
allocated to Zone1)
Reset type: SYSRSn
2 EXEONLY_SECTC R 0h Value in this field gets loaded from Z1_EXEONLYSECT[2:2] when a
read is issued to Z1_EXEONLYSECT address location in OTP.
0 : Execute-Only protection is enabled for Flash Sector C (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for Flash Sector C (only if it's
allocated to Zone1)
Reset type: SYSRSn

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Table 3-219. Z1_EXEONLYSECTR Register Field Descriptions (continued)

Bit Field Type Reset Description
1 EXEONLY_SECTB R 0h Value in this field gets loaded from Z1_EXEONLYSECT[1:1] when a
read is issued to Z1_EXEONLYSECT address location in OTP.
0 : Execute-Only protection is enabled for Flash Sector B (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for Flash Sector B (only if it's
allocated to Zone1)
Reset type: SYSRSn
0 EXEONLY_SECTA R 0h Value in this field gets loaded from Z1_EXEONLYSECT[0:0] when a
read is issued to Z1_EXEONLYSECT address location in OTP.
0 : Execute-Only protection is enabled for Flash Sector A (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for Flash Sector A (only if it's
allocated to Zone1)
Reset type: SYSRSn

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3.17.14.13 Z1_EXEONLYRAMR Register (Offset = 20h) [Reset = 00000000h]

Z1_EXEONLYRAMR is shown in Figure 3-199 and described in Table 3-220.
Return to the Summary Table.
Zone 1 RAM Execute_Only Block Register
Figure 3-199. Z1_EXEONLYRAMR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA
M7 M6 M5 M4 M3 M2 M1 M0
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 3-220. Z1_EXEONLYRAMR Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-8 RESERVED R 0h Reserved
7 EXEONLY_RAM7 R 0h Value in this field gets loaded from Z1_EXEONLYRAM[7:7] when a
read is issued to Z1_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for D1 RAM (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for D1 RAM (only if it's
allocated to Zone1)
Reset type: SYSRSn
6 EXEONLY_RAM6 R 0h Value in this field gets loaded from Z1_EXEONLYRAM[6:6] when a
read is issued to Z1_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for D0 RAM (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for D0 RAM (only if it's
allocated to Zone1)
Reset type: SYSRSn
5 EXEONLY_RAM5 R 0h Value in this field gets loaded from Z1_EXEONLYRAM[5:5] when a
read is issued to Z1_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for LS5 RAM (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for LS5 RAM (only if it's
allocated to Zone1)
Reset type: SYSRSn
4 EXEONLY_RAM4 R 0h Value in this field gets loaded from Z1_EXEONLYRAM[4:4] when a
read is issued to Z1_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for LS4 RAM (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for LS4 RAM (only if it's
allocated to Zone1)
Reset type: SYSRSn

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Table 3-220. Z1_EXEONLYRAMR Register Field Descriptions (continued)

Bit Field Type Reset Description
3 EXEONLY_RAM3 R 0h Value in this field gets loaded from Z1_EXEONLYRAM[3:3] when a
read is issued to Z1_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for LS3 RAM (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for LS3 RAM (only if it's
allocated to Zone1)
Reset type: SYSRSn
2 EXEONLY_RAM2 R 0h Value in this field gets loaded from Z1_EXEONLYRAM[2:2] when a
read is issued to Z1_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for LS2 RAM (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for LS2 RAM (only if it's
allocated to Zone1)
Reset type: SYSRSn
1 EXEONLY_RAM1 R 0h Value in this field gets loaded from Z1_EXEONLYRAM[1:1] when a
read is issued to Z1_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for LS1 RAM (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for LS1 RAM (only if it's
allocated to Zone1)
Reset type: SYSRSn
0 EXEONLY_RAM0 R 0h Value in this field gets loaded from Z1_EXEONLYRAM[0:0] when a
read is issued to Z1_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for LS0 RAM (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for LS0 RAM (only if it's
allocated to Zone1)
Reset type: SYSRSn

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3.17.15 DCSM_Z2_REGS Registers

Table 3-221 lists the memory-mapped registers for the DCSM_Z2_REGS registers. All register offset addresses
not listed in Table 3-221 should be considered as reserved locations and the register contents should not be
modified.
Table 3-221. DCSM_Z2_REGS Registers
Offset Acronym Register Name Write Protection Section
0h Z2_LINKPOINTER Zone 2 Link Pointer Go
2h Z2_OTPSECLOCK Zone 2 OTP Secure JTAG lock Go
4h Z2_BOOTCTRL Boot Mode Go
6h Z2_LINKPOINTERERR Link Pointer Error Go
10h Z2_CSMKEY0 Zone 2 CSM Key 0 Go
12h Z2_CSMKEY1 Zone 2 CSM Key 1 Go
14h Z2_CSMKEY2 Zone 2 CSM Key 2 Go
16h Z2_CSMKEY3 Zone 2 CSM Key 3 Go
19h Z2_CR Zone 2 CSM Control Register Go
1Ah Z2_GRABSECTR Zone 2 Grab Flash Sectors Register Go
1Ch Z2_GRABRAMR Zone 2 Grab RAM Blocks Register Go
1Eh Z2_EXEONLYSECTR Zone 2 Flash Execute_Only Sector Register Go
20h Z2_EXEONLYRAMR Zone 2 RAM Execute_Only Block Register Go

Complex bit access types are encoded to fit into small table cells. Table 3-222 shows the codes that are used for
access types in this section.
Table 3-222. DCSM_Z2_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default value
Register Array Variables
i,j,k,l,m,n When these variables are used in a register name,
an offset, or an address, they refer to the value of a
register array where the register is part of a group
of repeating registers. The register groups form a
hierarchical structure and the array is represented
with a formula.
y When this variable is used in a register name, an
offset, or an address it refers to the value of a
register array.

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3.17.15.1 Z2_LINKPOINTER Register (Offset = 0h) [Reset = E0000000h]

Z2_LINKPOINTER is shown in Figure 3-200 and described in Table 3-223.
Return to the Summary Table.
Zone 2 Link Pointer
Figure 3-200. Z2_LINKPOINTER Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED LINKPOINTER
R-7h R-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINKPOINTER
R-0h

Table 3-223. Z2_LINKPOINTER Register Field Descriptions

Bit Field Type Reset Description
31-29 RESERVED R 7h Reserved
28-0 LINKPOINTER R 0h This is the Resolved Link-Pointer value which is generated by
looking at the three physical Link-Pointer values loaded from OTP.
Reset type: SYSRSn

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3.17.15.2 Z2_OTPSECLOCK Register (Offset = 2h) [Reset = 00000FFFh]

Z2_OTPSECLOCK is shown in Figure 3-201 and described in Table 3-224.
Return to the Summary Table.
Zone 2 OTP Secure JTAG lock
Figure 3-201. Z2_OTPSECLOCK Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED CRCLOCK PSWDLOCK JTAGLOCK
R-0h R-Fh R-Fh R-Fh

Table 3-224. Z2_OTPSECLOCK Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-12 RESERVED R 0h Reserved
11-8 CRCLOCK R Fh Value in this field gets loaded from Z2_CRCLOCK[3:0] when a read
is issued to address location of Z2_CRCLOCK in OTP.
1111 : VCU has ability to calculate CRC on secure memories.
Other Value : VCU doesn't have ability to calculate CRC on secure
memories.
Reset type: SYSRSn
7-4 PSWDLOCK R Fh Value in this field gets loaded from Z2_PSWDLOCK[3:0] when a
read is issued to address location of Z2_PSWDLOCK in OTP.
1111 : CSM password locations in OTP are not protected and can be
read from debugger as well as code running from anywhere.
Other Value : CSM password locations in OTP are protected and
can't be read without unlocking CSM of that zone.
Reset type: SYSRSn
3-0 JTAGLOCK R Fh Value in this field gets loaded from Z2_JTAGLOCK[3:0] when a read
is issued to address location of Z2_JTAGLOCK in OTP.
1111 : JTAG/Emulation access is allowed.
Other Value : JTAG/Emulation access not allowed.
Reset type: SYSRSn

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3.17.15.3 Z2_BOOTCTRL Register (Offset = 4h) [Reset = 00000000h]

Z2_BOOTCTRL is shown in Figure 3-202 and described in Table 3-225.
Return to the Summary Table.
Boot Mode
Figure 3-202. Z2_BOOTCTRL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOOTPIN1 BOOTPIN0 BMODE KEY
R-0h R-0h R-0h R-0h

Table 3-225. Z2_BOOTCTRL Register Field Descriptions

Bit Field Type Reset Description
31-24 BOOTPIN1 R 0h This field gets loaded with Z2_BOOTCTRL[31:24] when a dummy
read is issued to address location of Z2_BOOTCTRL in OTP.
This assigns the pin to be used as BOOTPIN1.
0 : Pick default bootmode pin.
1 : Pick GPIO0 as BOOTPIN1.
2 : Pick GPIO1 as BOOTPIN1.
....
....
n : Pick GPIOn-1 as BOOTPIN1.
Reset type: SYSRSn
23-16 BOOTPIN0 R 0h This field gets loaded with Z2_BOOTCTRL[23:16] when a dummy
read is issued to address location of Z2_BOOTCTRL in OTP.
This assigns the pin to be used as BOOTPIN1.
0 : Pick default bootmode pin.
1 : Pick GPIO0 as BOOTPIN1.
2 : Pick GPIO1 as BOOTPIN1.
....
....
n : Pick GPIOn-1 as BOOTPIN1.
Reset type: SYSRSn
15-8 BMODE R 0h This field gets loaded with Z2_BOOTCTRL[15:8] when a dummy
read is issued to address location of Z2_BOOTCTRL in OTP.
Reset type: SYSRSn
7-0 KEY R 0h This field gets loaded with Z2_BOOTCTRL[7:0] when a dummy read
is issued to address location of Z2_BOOTCTRL in OTP.
Reset type: SYSRSn

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3.17.15.4 Z2_LINKPOINTERERR Register (Offset = 6h) [Reset = FFFFFFFFh]

Z2_LINKPOINTERERR is shown in Figure 3-203 and described in Table 3-226.
Return to the Summary Table.
Link Pointer Error
Figure 3-203. Z2_LINKPOINTERERR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2_LINKPOINTERERR
R-FFFFFFFFh

Table 3-226. Z2_LINKPOINTERERR Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2_LINKPOINTERERR R FFFFFFFFh These bits indicate errors during formation of the resolved Link-
Pointer value after the three physical Link-Pointer values loaded of
OTP.
0 : No Error.
Other : Error on bit positions which is set to 1.
Reset type: SYSRSn

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3.17.15.5 Z2_CSMKEY0 Register (Offset = 10h) [Reset = 00000000h]

Z2_CSMKEY0 is shown in Figure 3-204 and described in Table 3-227.
Return to the Summary Table.
Zone 2 CSM Key 0
Figure 3-204. Z2_CSMKEY0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2_CSMKEY0
R-0h

Table 3-227. Z2_CSMKEY0 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2_CSMKEY0 R 0h To unclock Zone2, user needs to write this regsiter with exact value
as Z2_CSMPSWD0, programmed in OTP (zone gets unlock only if
128 bit password in OTP match with value written in four CSMKEY
registers.)
Reset type: SYSRSn

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3.17.15.6 Z2_CSMKEY1 Register (Offset = 12h) [Reset = 00000000h]

Z2_CSMKEY1 is shown in Figure 3-205 and described in Table 3-228.
Return to the Summary Table.
Zone 2 CSM Key 1
Figure 3-205. Z2_CSMKEY1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2_CSMKEY1
R-0h

Table 3-228. Z2_CSMKEY1 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2_CSMKEY1 R 0h To unclock Zone2, user needs to write this regsiter with exact value
as Z2_CSMPSWD1, programmed in OTP (zone gets unlock only if
128 bit password in OTP match with value written in four CSMKEY
registers.)
Reset type: SYSRSn

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3.17.15.7 Z2_CSMKEY2 Register (Offset = 14h) [Reset = 00000000h]

Z2_CSMKEY2 is shown in Figure 3-206 and described in Table 3-229.
Return to the Summary Table.
Zone 2 CSM Key 2
Figure 3-206. Z2_CSMKEY2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2_CSMKEY2
R-0h

Table 3-229. Z2_CSMKEY2 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2_CSMKEY2 R 0h To unclock Zone2, user needs to write this regsiter with exact value
as Z2_CSMPSWD2, programmed in OTP (zone gets unlock only if
128 bit password in OTP match with value written in four CSMKEY
registers.)
Reset type: SYSRSn

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3.17.15.8 Z2_CSMKEY3 Register (Offset = 16h) [Reset = 00000000h]

Z2_CSMKEY3 is shown in Figure 3-207 and described in Table 3-230.
Return to the Summary Table.
Zone 2 CSM Key 3
Figure 3-207. Z2_CSMKEY3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2_CSMKEY3
R-0h

Table 3-230. Z2_CSMKEY3 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2_CSMKEY3 R 0h To unclock Zone2, user needs to write this regsiter with exact value
as Z2_CSMPSWD3, programmed in OTP (zone gets unlock only if
128 bit password in OTP match with value written in four CSMKEY
registers.)
Reset type: SYSRSn

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3.17.15.9 Z2_CR Register (Offset = 19h) [Reset = 0008h]

Z2_CR is shown in Figure 3-208 and described in Table 3-231.
Return to the Summary Table.
Zone 2 CSM Control Register
Figure 3-208. Z2_CR Register
15 14 13 12 11 10 9 8
FORCESEC RESERVED
R-0/W-0h R-0-0h

7 6 5 4 3 2 1 0
RESERVED ARMED UNSECURE ALLONE ALLZERO RESERVED
R-0h R-0h R-0h R-0h R-1h R-0h

Table 3-231. Z2_CR Register Field Descriptions

Bit Field Type Reset Description
15 FORCESEC R-0/W 0h A write '1' to this fields resets the state of zone. If zone is unlocked,
it'll lock(secure) the zone and also resets all the bits in this register.
Reset type: SYSRSn
14-8 RESERVED R-0 0h Reserved
7 RESERVED R 0h Reserved
6 ARMED R 0h 0 : Dummy read to CSM Password locations in OTP hasn't been
performed.
1 : Dummy read to CSM Password locations in OTP has been
performed.
Reset type: SYSRSn
5 UNSECURE R 0h Indiacates the state of Zone.
0 : Zone is in lock(secure) state.
1 : Zone is in unlock(unsecure) state.
Reset type: SYSRSn
4 ALLONE R 0h Indicates the state of CSM passowrds.
0 : CSM Passwords are not all ones.
1 : CSM Passwords are all ones and zone is in unlock state.
Reset type: SYSRSn
3 ALLZERO R 1h Indicates the state of CSM passowrds.
0 : CSM Passwords are not all zeros.
1 : CSM Passwords are all zero and device is permanently locked.
Reset type: SYSRSn
2-0 RESERVED R 0h Reserved

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3.17.15.10 Z2_GRABSECTR Register (Offset = 1Ah) [Reset = 00000000h]

Z2_GRABSECTR is shown in Figure 3-209 and described in Table 3-232.
Return to the Summary Table.
Zone 2 Grab Flash Sectors Register
Figure 3-209. Z2_GRABSECTR Register
31 30 29 28 27 26 25 24
RESERVED RESERVED GRAB_SECTN GRAB_SECTM
R-0h R-0h R-0h R-0h

23 22 21 20 19 18 17 16
GRAB_SECTL GRAB_SECTK GRAB_SECTJ GRAB_SECTI
R-0h R-0h R-0h R-0h

15 14 13 12 11 10 9 8
GRAB_SECTH GRAB_SECTG GRAB_SECTF GRAB_SECTE
R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
GRAB_SECTD GRAB_SECTC GRAB_SECTB GRAB_SECTA
R-0h R-0h R-0h R-0h

Table 3-232. Z2_GRABSECTR Register Field Descriptions

Bit Field Type Reset Description
31-30 RESERVED R 0h Reserved
29-28 RESERVED R 0h Reserved
27-26 GRAB_SECTN R 0h Value in this field gets loaded from Z2_GRABSECT[27:26] when a
read is issued to address location of Z2_GRABSECT in OTP.
00 : Invalid. Flash Sector N is inaccessible.
01 : Request to allocate Flash Sector N to Zone2.
10 : Request to allocate Flash Sector N to Zone2.
11 : Request to make Flash sector N Non-Secure.
Reset type: SYSRSn
25-24 GRAB_SECTM R 0h Value in this field gets loaded from Z2_GRABSECT[25:24] when a
read is issued to address location of Z2_GRABSECT in OTP.
00 : Invalid. Flash Sector M is inaccessible.
01 : Request to allocate Flash Sector M to Zone2.
10 : Request to allocate Flash Sector M to Zone2.
11 : Request to make Flash sector M Non-Secure.
Reset type: SYSRSn
23-22 GRAB_SECTL R 0h Value in this field gets loaded from Z2_GRABSECT[23:22] when a
read is issued to address location of Z2_GRABSECT in OTP.
00 : Invalid. Flash Sector L is inaccessible.
01 : Request to allocate Flash Sector L to Zone2.
10 : Request to allocate Flash Sector L to Zone2.
11 : Request to make Flash sector L Non-Secure.
Reset type: SYSRSn
21-20 GRAB_SECTK R 0h Value in this field gets loaded from Z2_GRABSECT[21:20] when a
read is issued to address location of Z2_GRABSECT in OTP.
00 : Invalid. Flash Sector K is inaccessible.
01 : Request to allocate Flash Sector K to Zone2.
10 : Request to allocate Flash Sector K to Zone2.
11 : Request to make Flash sector K Non-Secure.
Reset type: SYSRSn

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Table 3-232. Z2_GRABSECTR Register Field Descriptions (continued)

Bit Field Type Reset Description
19-18 GRAB_SECTJ R 0h Value in this field gets loaded from Z2_GRABSECT[19:18] when a
read is issued to address location of Z2_GRABSECT in OTP.
00 : Invalid. Flash Sector J is inaccessible.
01 : Request to allocate Flash Sector J to Zone2.
10 : Request to allocate Flash Sector J to Zone2.
11 : Request to make Flash sector J Non-Secure.
Reset type: SYSRSn
17-16 GRAB_SECTI R 0h Value in this field gets loaded from Z2_GRABSECT[17:16] when a
read is issued to address location of Z2_GRABSECT in OTP.
00 : Invalid. Flash Sector I is inaccessible.
01 : Request to allocate Flash Sector I to Zone2.
10 : Request to allocate Flash Sector I to Zone2.
11 : Request to make Flash sector I Non-Secure.
Reset type: SYSRSn
15-14 GRAB_SECTH R 0h Value in this field gets loaded from Z2_GRABSECT[15:14] when a
read is issued to address location of Z2_GRABSECT in OTP.
00 : Invalid. Flash Sector H is inaccessible.
01 : Request to allocate Flash Sector H to Zone2.
10 : Request to allocate Flash Sector H to Zone2.
11 : Request to make Flash sector H Non-Secure.
Reset type: SYSRSn
13-12 GRAB_SECTG R 0h Value in this field gets loaded from Z2_GRABSECT[13:12] when a
read is issued to address location of Z2_GRABSECT in OTP.
00 : Invalid. Flash Sector G is inaccessible.
01 : Request to allocate Flash Sector G to Zone2.
10 : Request to allocate Flash Sector G to Zone2.
11 : Request to make Flash sector G Non-Secure.
Reset type: SYSRSn
11-10 GRAB_SECTF R 0h Value in this field gets loaded from Z2_GRABSECT[11:10] when a
read is issued to address location of Z2_GRABSECT in OTP.
00 : Invalid. Flash Sector F is inaccessible.
01 : Request to allocate Flash Sector F to Zone2.
10 : Request to allocate Flash Sector F to Zone2.
11 : Request to make Flash sector F Non-Secure.
Reset type: SYSRSn
9-8 GRAB_SECTE R 0h Value in this field gets loaded from Z2_GRABSECT[9:8] when a read
is issued to address location of Z2_GRABSECT in OTP.
00 : Invalid. Flash Sector E is inaccessible.
01 : Request to allocate Flash Sector E to Zone2.
10 : Request to allocate Flash Sector E to Zone2.
11 : Request to make Flash sector E Non-Secure.
Reset type: SYSRSn
7-6 GRAB_SECTD R 0h Value in this field gets loaded from Z2_GRABSECT[7:6] when a read
is issued to address location of Z2_GRABSECT in OTP.
00 : Invalid. Flash Sector D is inaccessible.
01 : Request to allocate Flash Sector D to Zone2.
10 : Request to allocate Flash Sector D to Zone2.
11 : Request to make Flash sector D Non-Secure.
Reset type: SYSRSn
5-4 GRAB_SECTC R 0h Value in this field gets loaded from Z2_GRABSECT[5:4] when a read
is issued to address location of Z2_GRABSECT in OTP.
00 : Invalid. Flash Sector C is inaccessible.
01 : Request to allocate Flash Sector C to Zone2.
10 : Request to allocate Flash Sector C to Zone2.
11 : Request to make Flash sector C Non-Secure.
Reset type: SYSRSn

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Table 3-232. Z2_GRABSECTR Register Field Descriptions (continued)

Bit Field Type Reset Description
3-2 GRAB_SECTB R 0h Value in this field gets loaded from Z2_GRABSECT[3:2] when a read
is issued to address location of Z2_GRABSECT in OTP.
00 : Invalid. Flash Sector B is inaccessible.
01 : Request to allocate Flash Sector B to Zone2.
10 : Request to allocate Flash Sector B to Zone2.
11 : Request to make Flash sector B Non-Secure.
Reset type: SYSRSn
1-0 GRAB_SECTA R 0h Value in this field gets loaded from Z2_GRABSECT[1:0] when a read
is issued to address location of Z2_GRABSECT in OTP.
00 : Invalid. Flash Sector A is inaccessible.
01 : Request to allocate Flash Sector A to Zone2.
10 : Request to allocate Flash Sector A to Zone2.
11 : Request to make Flash sector A Non-Secure.
Reset type: SYSRSn

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3.17.15.11 Z2_GRABRAMR Register (Offset = 1Ch) [Reset = 00000000h]

Z2_GRABRAMR is shown in Figure 3-210 and described in Table 3-233.
Return to the Summary Table.
Zone 2 Grab RAM Blocks Register
Figure 3-210. Z2_GRABRAMR Register
31 30 29 28 27 26 25 24
RESERVED GRAB_CLA1 RESERVED
R-0h R-0h R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
GRAB_RAM7 GRAB_RAM6 GRAB_RAM5 GRAB_RAM4
R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
GRAB_RAM3 GRAB_RAM2 GRAB_RAM1 GRAB_RAM0
R-0h R-0h R-0h R-0h

Table 3-233. Z2_GRABRAMR Register Field Descriptions

Bit Field Type Reset Description
31-30 RESERVED R 0h Reserved
29-28 GRAB_CLA1 R 0h Value in this field gets loaded from Z2_GRABRAM[29:28] when a
read is issued to address location of Z2_GRABRAM in OTP.
00 : Invalid. CLA1 is inaccessible.
01 : Request to allocate CLA1 to Zone2.
10 : Request to allocate CLA1 to Zone2.
11 : Request to make CLA1 Non-Secure.
Reset type: SYSRSn
27-16 RESERVED R 0h Reserved
15-14 GRAB_RAM7 R 0h Value in this field gets loaded from Z2_GRABRAM[15:14] when a
read is issued to address location of Z2_GRABRAM in OTP.
00 : Invalid. D1 RAM is inaccessible.
01 : Request to allocate D1 RAM to Zone2.
10 : Request to allocate D1 RAM to Zone2.
11 : Request to make D1 RAM Non-Secure.
Reset type: SYSRSn
13-12 GRAB_RAM6 R 0h Value in this field gets loaded from Z2_GRABRAM[13:12] when a
read is issued to address location of Z2_GRABRAM in OTP.
00 : Invalid. D0 RAM is inaccessible.
01 : Request to allocate D0 RAM to Zone2.
10 : Request to allocate D0 RAM to Zone2.
11 : Request to make D0 RAM Non-Secure.
Reset type: SYSRSn
11-10 GRAB_RAM5 R 0h Value in this field gets loaded from Z2_GRABRAM[11:10] when a
read is issued to address location of Z2_GRABRAM in OTP.
00 : Invalid. LS5 RAM is inaccessible.
01 : Request to allocate LS5 RAM to Zone2.
10 : Request to allocate LS5 RAM to Zone2.
11 : Request to make LS5 RAM Non-Secure.
Reset type: SYSRSn

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Table 3-233. Z2_GRABRAMR Register Field Descriptions (continued)

Bit Field Type Reset Description
9-8 GRAB_RAM4 R 0h Value in this field gets loaded from Z2_GRABRAM[9:8] when a read
is issued to address location of Z2_GRABRAM in OTP.
00 : Invalid. LS4 RAM is inaccessible.
01 : Request to allocate LS4 RAM to Zone2.
10 : Request to allocate LS4 RAM to Zone2.
11 : Request to make LS4 RAM Non-Secure.
Reset type: SYSRSn
7-6 GRAB_RAM3 R 0h Value in this field gets loaded from Z2_GRABRAM[7:6] when a read
is issued to address location of Z2_GRABRAM in OTP.
00 : Invalid. LS3 RAM is inaccessible.
01 : Request to allocate LS3 RAM to Zone2.
10 : Request to allocate LS3 RAM to Zone2.
11 : Request to make LS3 RAM Non-Secure.
Reset type: SYSRSn
5-4 GRAB_RAM2 R 0h Value in this field gets loaded from Z2_GRABRAM[5:4] when a read
is issued to address location of Z2_GRABRAM in OTP.
00 : Invalid. LS2 RAM is inaccessible.
01 : Request to allocate LS2 RAM to Zone2.
10 : Request to allocate LS2 RAM to Zone2.
11 : Request to make LS2 RAM Non-Secure.
Reset type: SYSRSn
3-2 GRAB_RAM1 R 0h Value in this field gets loaded from Z2_GRABRAM[3:2] when a read
is issued to address location of Z2_GRABRAM in OTP.
00 : Invalid. LS1 RAM is inaccessible.
01 : Request to allocate LS1 RAM to Zone2.
10 : Request to allocate LS1 RAM to Zone2.
11 : Request to make LS1 RAM Non-Secure.
Reset type: SYSRSn
1-0 GRAB_RAM0 R 0h Value in this field gets loaded from Z2_GRABRAM[1:0] when a read
is issued to address location of Z2_GRABRAM in OTP.
00 : Invalid. LS0 RAM is inaccessible.
01 : Request to allocate LS0 RAM to Zone2.
10 : Request to allocate LS0 RAM to Zone2.
11 : Request to make LS0 RAM Non-Secure.
Reset type: SYSRSn

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3.17.15.12 Z2_EXEONLYSECTR Register (Offset = 1Eh) [Reset = 00000000h]

Z2_EXEONLYSECTR is shown in Figure 3-211 and described in Table 3-234.
Return to the Summary Table.
Zone 2 Flash Execute_Only Sector Register
Figure 3-211. Z2_EXEONLYSECTR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED EXEONLY_SE EXEONLY_SE EXEONLY_SE EXEONLY_SE EXEONLY_SE EXEONLY_SE
CTN CTM CTL CTK CTJ CTI
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
EXEONLY_SE EXEONLY_SE EXEONLY_SE EXEONLY_SE EXEONLY_SE EXEONLY_SE EXEONLY_SE EXEONLY_SE
CTH CTG CTF CTE CTD CTC CTB CTA
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 3-234. Z2_EXEONLYSECTR Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15 RESERVED R 0h Reserved
14 RESERVED R 0h Reserved
13 EXEONLY_SECTN R 0h Value in this field gets loaded from Z2_EXEONLYSECT[13:13] when
a read is issued to Z2_EXEONLYSECT address location in OTP.
0 : Execute-Only protection is enabled for Flash Sector N (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for Flash Sector N (only if it's
allocated to Zone2)
Reset type: SYSRSn
12 EXEONLY_SECTM R 0h Value in this field gets loaded from Z2_EXEONLYSECT[12:12] when
a read is issued to Z2_EXEONLYSECT address location in OTP.
0 : Execute-Only protection is enabled for Flash Sector M (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for Flash Sector M (only if it's
allocated to Zone2)
Reset type: SYSRSn
11 EXEONLY_SECTL R 0h Value in this field gets loaded from Z2_EXEONLYSECT[11:11] when
a read is issued to Z2_EXEONLYSECT address location in OTP.
0 : Execute-Only protection is enabled for Flash Sector L (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for Flash Sector L (only if it's
allocated to Zone2)
Reset type: SYSRSn
10 EXEONLY_SECTK R 0h Value in this field gets loaded from Z2_EXEONLYSECT[10:10] when
a read is issued to Z2_EXEONLYSECT address location in OTP.
0 : Execute-Only protection is enabled for Flash Sector K (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for Flash Sector K (only if it's
allocated to Zone2)
Reset type: SYSRSn

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Table 3-234. Z2_EXEONLYSECTR Register Field Descriptions (continued)

Bit Field Type Reset Description
9 EXEONLY_SECTJ R 0h Value in this field gets loaded from Z2_EXEONLYSECT[9:9] when a
read is issued to Z2_EXEONLYSECT address location in OTP.
0 : Execute-Only protection is enabled for Flash Sector J (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for Flash Sector J (only if it's
allocated to Zone2)
Reset type: SYSRSn
8 EXEONLY_SECTI R 0h Value in this field gets loaded from Z2_EXEONLYSECT[8:8] when a
read is issued to Z2_EXEONLYSECT address location in OTP.
0 : Execute-Only protection is enabled for Flash Sector I (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for Flash Sector I (only if it's
allocated to Zone2)
Reset type: SYSRSn
7 EXEONLY_SECTH R 0h Value in this field gets loaded from Z2_EXEONLYSECT[7:7] when a
read is issued to Z2_EXEONLYSECT address location in OTP.
0 : Execute-Only protection is enabled for Flash Sector H (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for Flash Sector H (only if it's
allocated to Zone2)
Reset type: SYSRSn
6 EXEONLY_SECTG R 0h Value in this field gets loaded from Z2_EXEONLYSECT[6:6] when a
read is issued to Z2_EXEONLYSECT address location in OTP.
0 : Execute-Only protection is enabled for Flash Sector G (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for Flash Sector G (only if it's
allocated to Zone2)
Reset type: SYSRSn
5 EXEONLY_SECTF R 0h Value in this field gets loaded from Z2_EXEONLYSECT[5:5] when a
read is issued to Z2_EXEONLYSECT address location in OTP.
0 : Execute-Only protection is enabled for Flash Sector F (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for Flash Sector F (only if it's
allocated to Zone2)
Reset type: SYSRSn
4 EXEONLY_SECTE R 0h Value in this field gets loaded from Z2_EXEONLYSECT[4:4] when a
read is issued to Z2_EXEONLYSECT address location in OTP.
0 : Execute-Only protection is enabled for Flash Sector E (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for Flash Sector E (only if it's
allocated to Zone2)
Reset type: SYSRSn
3 EXEONLY_SECTD R 0h Value in this field gets loaded from Z2_EXEONLYSECT[3:3] when a
read is issued to Z2_EXEONLYSECT address location in OTP.
0 : Execute-Only protection is enabled for Flash Sector D (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for Flash Sector D (only if it's
allocated to Zone2)
Reset type: SYSRSn
2 EXEONLY_SECTC R 0h Value in this field gets loaded from Z2_EXEONLYSECT[2:2] when a
read is issued to Z2_EXEONLYSECT address location in OTP.
0 : Execute-Only protection is enabled for Flash Sector C (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for Flash Sector C (only if it's
allocated to Zone2)
Reset type: SYSRSn

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Table 3-234. Z2_EXEONLYSECTR Register Field Descriptions (continued)

Bit Field Type Reset Description
1 EXEONLY_SECTB R 0h Value in this field gets loaded from Z2_EXEONLYSECT[1:1] when a
read is issued to Z2_EXEONLYSECT address location in OTP.
0 : Execute-Only protection is enabled for Flash Sector B (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for Flash Sector B (only if it's
allocated to Zone2)
Reset type: SYSRSn
0 EXEONLY_SECTA R 0h Value in this field gets loaded from Z2_EXEONLYSECT[0:0] when a
read is issued to Z2_EXEONLYSECT address location in OTP.
0 : Execute-Only protection is enabled for Flash Sector A (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for Flash Sector A (only if it's
allocated to Zone2)
Reset type: SYSRSn

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3.17.15.13 Z2_EXEONLYRAMR Register (Offset = 20h) [Reset = 00000000h]

Z2_EXEONLYRAMR is shown in Figure 3-212 and described in Table 3-235.
Return to the Summary Table.
Zone 2 RAM Execute_Only Block Register
Figure 3-212. Z2_EXEONLYRAMR Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA
M7 M6 M5 M4 M3 M2 M1 M0
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 3-235. Z2_EXEONLYRAMR Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-8 RESERVED R-0 0h Reserved
7 EXEONLY_RAM7 R 0h Value in this field gets loaded from Z2_EXEONLYRAM[7:7] when a
read is issued to Z2_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for D1 RAM (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for D1 RAM (only if it's
allocated to Zone2)
Reset type: SYSRSn
6 EXEONLY_RAM6 R 0h Value in this field gets loaded from Z2_EXEONLYRAM[6:6] when a
read is issued to Z2_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for D0 RAM (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for D0 RAM (only if it's
allocated to Zone2)
Reset type: SYSRSn
5 EXEONLY_RAM5 R 0h Value in this field gets loaded from Z2_EXEONLYRAM[5:5] when a
read is issued to Z2_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for LS5 RAM (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for LS5 RAM (only if it's
allocated to Zone2)
Reset type: SYSRSn
4 EXEONLY_RAM4 R 0h Value in this field gets loaded from Z2_EXEONLYRAM[4:4] when a
read is issued to Z2_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for LS4 RAM (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for LS4 RAM (only if it's
allocated to Zone2)
Reset type: SYSRSn

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Table 3-235. Z2_EXEONLYRAMR Register Field Descriptions (continued)

Bit Field Type Reset Description
3 EXEONLY_RAM3 R 0h Value in this field gets loaded from Z2_EXEONLYRAM[3:3] when a
read is issued to Z2_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for LS3 RAM (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for LS3 RAM (only if it's
allocated to Zone2)
Reset type: SYSRSn
2 EXEONLY_RAM2 R 0h Value in this field gets loaded from Z2_EXEONLYRAM[2:2] when a
read is issued to Z2_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for LS2 RAM (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for LS2 RAM (only if it's
allocated to Zone2)
Reset type: SYSRSn
1 EXEONLY_RAM1 R 0h Value in this field gets loaded from Z2_EXEONLYRAM[1:1] when a
read is issued to Z2_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for LS1 RAM (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for LS1 RAM (only if it's
allocated to Zone2)
Reset type: SYSRSn
0 EXEONLY_RAM0 R 0h Value in this field gets loaded from Z2_EXEONLYRAM[0:0] when a
read is issued to Z2_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for LS0 RAM (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for LS0 RAM (only if it's
allocated to Zone2)
Reset type: SYSRSn

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3.17.16 DCSM_COMMON_REGS Registers

Table 3-236 lists the memory-mapped registers for the DCSM_COMMON_REGS registers. All register offset
addresses not listed in Table 3-236 should be considered as reserved locations and the register contents should
not be modified.
Table 3-236. DCSM_COMMON_REGS Registers
Offset Acronym Register Name Write Protection Section
0h FLSEM Flash Wrapper Semaphore Register EALLOW Go
2h SECTSTAT Sectors Status Register Go
4h RAMSTAT RAM Status Register Go

Complex bit access types are encoded to fit into small table cells. Table 3-237 shows the codes that are used for
access types in this section.
Table 3-237. DCSM_COMMON_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default value
Register Array Variables
i,j,k,l,m,n When these variables are used in a register name,
an offset, or an address, they refer to the value of a
register array where the register is part of a group
of repeating registers. The register groups form a
hierarchical structure and the array is represented
with a formula.
y When this variable is used in a register name, an
offset, or an address it refers to the value of a
register array.

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3.17.16.1 FLSEM Register (Offset = 0h) [Reset = 00000000h]

FLSEM is shown in Figure 3-213 and described in Table 3-238.
Return to the Summary Table.
Flash Wrapper Semaphore Register
Figure 3-213. FLSEM Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY RESERVED SEM
R-0/W-0h R-0h R/W-0h

Table 3-238. FLSEM Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-8 KEY R-0/W 0h Writing a value 0xA5 into this field will allow the writing of the SEM
bits, else writes are ignored. Reads will return 0.
Reset type: SYSRSn
7-2 RESERVED R 0h Reserved
1-0 SEM R/W 0h 00 : C28X Flash Wrapper registers can be written by code running
from non-secure zone.
01 : Flash Wrapper registers can be written by code running from
Zone1 security zone only. User must set this value to perform flash
operation on flash sectors of Zone1.
10 : C28X Flash Wrapper registers can be written by code running
from Zone2 security zone only. User must set this value to perform
flash operation on flash sectors of Zone2.
11 : C28X Flash Wrapper registers can be written by code running
from non-secure zone.
Allowed State Transitions in this field.
00 to 11 : Code running from anywhere.
11 to 00 : Not allowed.
00/11 to 01 : Code running from Zone1 only can perform this
transition.
01 to 00/11 : Code running from Zone1 only can perform this
transition.
00/11 to 10 : Code running from Zone2 only can perform this
transition.
10 to 00/11 : Code running from Zone2 can perform this transition
Reset type: SYSRSn

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3.17.16.2 SECTSTAT Register (Offset = 2h) [Reset = 00000000h]

SECTSTAT is shown in Figure 3-214 and described in Table 3-239.
Return to the Summary Table.
Sectors Status Register
Figure 3-214. SECTSTAT Register
31 30 29 28 27 26 25 24
RESERVED RESERVED STATUS_SECTN STATUS_SECTM
R-0h R-0h R-0h R-0h

23 22 21 20 19 18 17 16
STATUS_SECTL STATUS_SECTK STATUS_SECTJ STATUS_SECTI
R-0h R-0h R-0h R-0h

15 14 13 12 11 10 9 8
STATUS_SECTH STATUS_SECTG STATUS_SECTF STATUS_SECTE
R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
STATUS_SECTD STATUS_SECTC STATUS_SECTB STATUS_SECTA
R-0h R-0h R-0h R-0h

Table 3-239. SECTSTAT Register Field Descriptions

Bit Field Type Reset Description
31-30 RESERVED R 0h Reserved
29-28 RESERVED R 0h Reserved
27-26 STATUS_SECTN R 0h Reflects the status of flash sector N.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
25-24 STATUS_SECTM R 0h Reflects the status of flash sector M.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
23-22 STATUS_SECTL R 0h Reflects the status of flash sector L.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
21-20 STATUS_SECTK R 0h Reflects the status of flash sector K.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

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Table 3-239. SECTSTAT Register Field Descriptions (continued)

Bit Field Type Reset Description
19-18 STATUS_SECTJ R 0h Reflects the status of flash sector J.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
17-16 STATUS_SECTI R 0h Reflects the status of flash sector I.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
15-14 STATUS_SECTH R 0h Reflects the status of flash sector H.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
13-12 STATUS_SECTG R 0h Reflects the status of flash sector G.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
11-10 STATUS_SECTF R 0h Reflects the status of flash sector F.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
9-8 STATUS_SECTE R 0h Reflects the status of flash sector E.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
7-6 STATUS_SECTD R 0h Reflects the status of flash sector D.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
5-4 STATUS_SECTC R 0h Reflects the status of flash sector C.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

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Table 3-239. SECTSTAT Register Field Descriptions (continued)

Bit Field Type Reset Description
3-2 STATUS_SECTB R 0h Reflects the status of flash sector B.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
1-0 STATUS_SECTA R 0h Reflects the status of flash sector A.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

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3.17.16.3 RAMSTAT Register (Offset = 4h) [Reset = 00000000h]

RAMSTAT is shown in Figure 3-215 and described in Table 3-240.
Return to the Summary Table.
RAM Status Register
Figure 3-215. RAMSTAT Register
31 30 29 28 27 26 25 24
RESERVED STATUS_CLA1 RESERVED
R-0h R-0h R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
STATUS_RAM7 STATUS_RAM6 STATUS_RAM5 STATUS_RAM4
R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
STATUS_RAM3 STATUS_RAM2 STATUS_RAM1 STATUS_RAM0
R-0h R-0h R-0h R-0h

Table 3-240. RAMSTAT Register Field Descriptions

Bit Field Type Reset Description
31-30 RESERVED R 0h Reserved
29-28 STATUS_CLA1 R 0h Reflects the status of CLA1.
00 : CLA is in-accessible
01 : CLA belongs to Zone1.
10 : CLA belongs to Zone2.
11: CLA is un-secure and code running in both zone have full access
to it.
Reset type: SYSRSn
27-16 RESERVED R 0h Reserved
15-14 STATUS_RAM7 R 0h Reflects the status of D1 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
13-12 STATUS_RAM6 R 0h Reflects the status of D0 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
11-10 STATUS_RAM5 R 0h Reflects the status of LS5 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

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Table 3-240. RAMSTAT Register Field Descriptions (continued)

Bit Field Type Reset Description
9-8 STATUS_RAM4 R 0h Reflects the status of LS4 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
7-6 STATUS_RAM3 R 0h Reflects the status of LS3 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
5-4 STATUS_RAM2 R 0h Reflects the status of LS2 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
3-2 STATUS_RAM1 R 0h Reflects the status of LS1 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
1-0 STATUS_RAM0 R 0h Reflects the status of LS0 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

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3.17.17 MEM_CFG_REGS Registers

Table 3-241 lists the memory-mapped registers for the MEM_CFG_REGS registers. All register offset addresses
not listed in Table 3-241 should be considered as reserved locations and the register contents should not be
modified.
Table 3-241. MEM_CFG_REGS Registers
Offset Acronym Register Name Write Protection Section
0h DxLOCK Dedicated RAM Config Lock Register EALLOW Go
2h DxCOMMIT Dedicated RAM Config Lock Commit Register EALLOW Go
8h DxACCPROT0 Dedicated RAM Config Register EALLOW Go
10h DxTEST Dedicated RAM TEST Register EALLOW Go
12h DxINIT Dedicated RAM Init Register EALLOW Go
14h DxINITDONE Dedicated RAM InitDone Status Register Go
20h LSxLOCK Local Shared RAM Config Lock Register EALLOW Go
22h LSxCOMMIT Local Shared RAM Config Lock Commit Register EALLOW Go
24h LSxMSEL Local Shared RAM Master Sel Register EALLOW Go
26h LSxCLAPGM Local Shared RAM Prog/Exe control Register EALLOW Go
28h LSxACCPROT0 Local Shared RAM Config Register 0 EALLOW Go
2Ah LSxACCPROT1 Local Shared RAM Config Register 1 EALLOW Go
30h LSxTEST Local Shared RAM TEST Register EALLOW Go
32h LSxINIT Local Shared RAM Init Register EALLOW Go
34h LSxINITDONE Local Shared RAM InitDone Status Register Go
40h GSxLOCK Global Shared RAM Config Lock Register EALLOW Go
42h GSxCOMMIT Global Shared RAM Config Lock Commit EALLOW Go
Register
44h GSxMSEL Global Shared RAM Master Sel Register EALLOW Go
48h GSxACCPROT0 Global Shared RAM Config Register 0 EALLOW Go
4Ah GSxACCPROT1 Global Shared RAM Config Register 1 EALLOW Go
4Ch GSxACCPROT2 Global Shared RAM Config Register 2 EALLOW Go
4Eh GSxACCPROT3 Global Shared RAM Config Register 3 EALLOW Go
50h GSxTEST Global Shared RAM TEST Register EALLOW Go
52h GSxINIT Global Shared RAM Init Register EALLOW Go
54h GSxINITDONE Global Shared RAM InitDone Status Register Go
70h MSGxTEST Message RAM TEST Register EALLOW Go
72h MSGxINIT Message RAM Init Register EALLOW Go
74h MSGxINITDONE Message RAM InitDone Status Register Go

Complex bit access types are encoded to fit into small table cells. Table 3-242 shows the codes that are used for
access types in this section.
Table 3-242. MEM_CFG_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write

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Table 3-242. MEM_CFG_REGS Access Type Codes (continued)

Access Type Code Description
W1S W Write
1S 1 to set
WSonce W Write
Sonce Set once
Reset or Default Value
-n Value after reset or the default value
Register Array Variables
i,j,k,l,m,n When these variables are used in a register name,
an offset, or an address, they refer to the value of a
register array where the register is part of a group
of repeating registers. The register groups form a
hierarchical structure and the array is represented
with a formula.
y When this variable is used in a register name, an
offset, or an address it refers to the value of a
register array.

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3.17.17.1 DxLOCK Register (Offset = 0h) [Reset = 00000000h]

DxLOCK is shown in Figure 3-216 and described in Table 3-243.
Return to the Summary Table.
Dedicated RAM Config Lock Register
Figure 3-216. DxLOCK Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED LOCK_D1 LOCK_D0 RESERVED
R-0h R/W-0h R/W-0h R-0h

Table 3-243. DxLOCK Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-4 RESERVED R 0h Reserved
3 LOCK_D1 R/W 0h Locks the write to access protection and master select fields for D1
RAM:
0: Write to ACCPROT and Mselect fields are allowed.
1: Write to ACCPROT and Mselect fields are blocked.
Reset type: SYSRSn
2 LOCK_D0 R/W 0h Locks the write to access protection and master select fields for D0
RAM:
0: Write to ACCPROT and Mselect fields are allowed.
1: Write to ACCPROT and Mselect fields are blocked.
Reset type: SYSRSn
1-0 RESERVED R 0h Reserved

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3.17.17.2 DxCOMMIT Register (Offset = 2h) [Reset = 00000000h]

DxCOMMIT is shown in Figure 3-217 and described in Table 3-244.
Return to the Summary Table.
Dedicated RAM Config Lock Commit Register
Figure 3-217. DxCOMMIT Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED COMMIT_D1 COMMIT_D0 RESERVED
R-0h R/WSonce-0h R/WSonce-0h R-0h

Table 3-244. DxCOMMIT Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-4 RESERVED R 0h Reserved
3 COMMIT_D1 R/WSonce 0h Permanently Locks the write to access protection and master select
fields for D1 RAM:
0: Write to ACCPROT and Mselect fields are allowed based on value
of lock field in DxLOCK register.
1: Write to ACCPROT and Mselect fields are permanently blocked.
Reset type: SYSRSn
2 COMMIT_D0 R/WSonce 0h Permanently Locks the write to access protection and master select
fields for D0 RAM:
0: Write to ACCPROT and Mselect fields are allowed based on value
of lock field in DxLOCK register.
1: Write to ACCPROT and Mselect fields are permanently blocked.
Reset type: SYSRSn
1-0 RESERVED R 0h Reserved

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3.17.17.3 DxACCPROT0 Register (Offset = 8h) [Reset = 00000000h]

DxACCPROT0 is shown in Figure 3-218 and described in Table 3-245.
Return to the Summary Table.
Dedicated RAM Config Register
Figure 3-218. DxACCPROT0 Register
31 30 29 28 27 26 25 24
RESERVED CPUWRPROT_ FETCHPROT_
D1 D1
R-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED CPUWRPROT_ FETCHPROT_
D0 D0
R-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED
R-0h

Table 3-245. DxACCPROT0 Register Field Descriptions

Bit Field Type Reset Description
31-26 RESERVED R 0h Reserved
25 CPUWRPROT_D1 R/W 0h CPU WR Protection For D1 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
24 FETCHPROT_D1 R/W 0h Fetch Protection For D1 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
23-18 RESERVED R 0h Reserved
17 CPUWRPROT_D0 R/W 0h CPU WR Protection For D0 RAM:
0: CPU Writes are allowed.
1: CPU Writes are block.
Reset type: SYSRSn
16 FETCHPROT_D0 R/W 0h Fetch Protection For D0 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
15-0 RESERVED R 0h Reserved

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3.17.17.4 DxTEST Register (Offset = 10h) [Reset = 00000000h]

DxTEST is shown in Figure 3-219 and described in Table 3-246.
Return to the Summary Table.
Dedicated RAM TEST Register
Figure 3-219. DxTEST Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
TEST_D1 TEST_D0 TEST_M1 TEST_M0
R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-246. DxTEST Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-8 RESERVED R 0h Reserved
7-6 TEST_D1 R/W 0h Selects the different modes for D1 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ECC bits.
10: Writes are allowed to ECC bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn
5-4 TEST_D0 R/W 0h Selects the different modes for D0 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ECC bits.
10: Writes are allowed to ECC bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn
3-2 TEST_M1 R/W 0h Selects the different modes for M1 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ECC bits.
10: Writes are allowed to ECC bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn
1-0 TEST_M0 R/W 0h Selects the different modes for M0 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ECC bits.
10: Writes are allowed to ECC bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn

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3.17.17.5 DxINIT Register (Offset = 12h) [Reset = 00000000h]

DxINIT is shown in Figure 3-220 and described in Table 3-247.
Return to the Summary Table.
Dedicated RAM Init Register
Figure 3-220. DxINIT Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED INIT_D1 INIT_D0 INIT_M1 INIT_M0
R-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-247. DxINIT Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-4 RESERVED R 0h Reserved
3 INIT_D1 R-0/W1S 0h RAM Initialization control for D1 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
2 INIT_D0 R-0/W1S 0h RAM Initialization control for D0 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
1 INIT_M1 R-0/W1S 0h RAM Initialization control for M1 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
0 INIT_M0 R-0/W1S 0h RAM Initialization control for M0 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn

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3.17.17.6 DxINITDONE Register (Offset = 14h) [Reset = 00000000h]

DxINITDONE is shown in Figure 3-221 and described in Table 3-248.
Return to the Summary Table.
Dedicated RAM InitDone Status Register
Figure 3-221. DxINITDONE Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED INITDONE_D1 INITDONE_D0 INITDONE_M1 INITDONE_M0
R-0h R-0h R-0h R-0h R-0h

Table 3-248. DxINITDONE Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-4 RESERVED R 0h Reserved
3 INITDONE_D1 R 0h RAM Initialization status for D1 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
2 INITDONE_D0 R 0h RAM Initialization status for D0 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
1 INITDONE_M1 R 0h RAM Initialization status for M1 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
0 INITDONE_M0 R 0h RAM Initialization status for M0 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn

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3.17.17.7 LSxLOCK Register (Offset = 20h) [Reset = 00000000h]

LSxLOCK is shown in Figure 3-222 and described in Table 3-249.
Return to the Summary Table.
Local Shared RAM Config Lock Register
Figure 3-222. LSxLOCK Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED LOCK_LS5 LOCK_LS4 LOCK_LS3 LOCK_LS2 LOCK_LS1 LOCK_LS0
R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-249. LSxLOCK Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-6 RESERVED R 0h Reserved
5 LOCK_LS5 R/W 0h Locks the write to access protection and master select fields for LS5
RAM:
0: Write to ACCPROT and Mselect fields are allowed.
1: Write to ACCPROT and Mselect fields are blocked.
Reset type: SYSRSn
4 LOCK_LS4 R/W 0h Locks the write to access protection and master select fields for LS4
RAM:
0: Write to ACCPROT and Mselect fields are allowed.
1: Write to ACCPROT and Mselect fields are blocked.
Reset type: SYSRSn
3 LOCK_LS3 R/W 0h Locks the write to access protection and master select fields for LS3
RAM:
0: Write to ACCPROT and Mselect fields are allowed.
1: Write to ACCPROT and Mselect fields are blocked.
Reset type: SYSRSn
2 LOCK_LS2 R/W 0h Locks the write to access protection and master select fields for LS2
RAM:
0: Write to ACCPROT and Mselect fields are allowed.
1: Write to ACCPROT and Mselect fields are blocked.
Reset type: SYSRSn
1 LOCK_LS1 R/W 0h Locks the write to access protection and master select fields for LS1
RAM:
0: Write to ACCPROT and Mselect fields are allowed.
1: Write to ACCPROT and Mselect fields are blocked.
Reset type: SYSRSn

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Table 3-249. LSxLOCK Register Field Descriptions (continued)

Bit Field Type Reset Description
0 LOCK_LS0 R/W 0h Locks the write to access protection and master select fields for LS0
RAM:
0: Write to ACCPROT and Mselect fields are allowed.
1: Write to ACCPROT and Mselect fields are blocked.
Reset type: SYSRSn

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3.17.17.8 LSxCOMMIT Register (Offset = 22h) [Reset = 00000000h]

LSxCOMMIT is shown in Figure 3-223 and described in Table 3-250.
Return to the Summary Table.
Local Shared RAM Config Lock Commit Register
Figure 3-223. LSxCOMMIT Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED COMMIT_LS5 COMMIT_LS4 COMMIT_LS3 COMMIT_LS2 COMMIT_LS1 COMMIT_LS0
R-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

Table 3-250. LSxCOMMIT Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-6 RESERVED R 0h Reserved
5 COMMIT_LS5 R/WSonce 0h Permanently Locks the write to access protection and master select
fields for LS5 RAM:
0: Write to ACCPROT and Mselect fields are allowed based on value
of lock field in LSxLOCK register.
1: Write to ACCPROT and Mselect fields are permanently blocked.
Reset type: SYSRSn
4 COMMIT_LS4 R/WSonce 0h Permanently Locks the write to access protection and master select
fields for LS4 RAM:
0: Write to ACCPROT and Mselect fields are allowed based on value
of lock field in LSxLOCK register.
1: Write to ACCPROT and Mselect fields are permanently blocked.
Reset type: SYSRSn
3 COMMIT_LS3 R/WSonce 0h Permanently Locks the write to access protection and master select
fields for LS3 RAM:
0: Write to ACCPROT and Mselect fields are allowed based on value
of lock field in LSxLOCK register.
1: Write to ACCPROT and Mselect fields are permanently blocked.
Reset type: SYSRSn
2 COMMIT_LS2 R/WSonce 0h Permanently Locks the write to access protection and master select
fields for LS2 RAM:
0: Write to ACCPROT and Mselect fields are allowed based on value
of lock field in LSxLOCK register.
1: Write to ACCPROT and Mselect fields are permanently blocked.
Reset type: SYSRSn
1 COMMIT_LS1 R/WSonce 0h Permanently Locks the write to access protection and master select
fields for LS1 RAM:
0: Write to ACCPROT and Mselect fields are allowed based on value
of lock field in LSxLOCK register.
1: Write to ACCPROT and Mselect fields are permanently blocked.
Reset type: SYSRSn

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Table 3-250. LSxCOMMIT Register Field Descriptions (continued)

Bit Field Type Reset Description
0 COMMIT_LS0 R/WSonce 0h Permanently Locks the write to access protection and master select
fields for LS0 RAM:
0: Write to ACCPROT and Mselect fields are allowed based on value
of lock field in LSxLOCK register.
1: Write to ACCPROT and Mselect fields are permanently blocked.
Reset type: SYSRSn

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3.17.17.9 LSxMSEL Register (Offset = 24h) [Reset = 00000000h]

LSxMSEL is shown in Figure 3-224 and described in Table 3-251.
Return to the Summary Table.
Local Shared RAM Master Sel Register
Figure 3-224. LSxMSEL Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED MSEL_LS5 MSEL_LS4
R-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
MSEL_LS3 MSEL_LS2 MSEL_LS1 MSEL_LS0
R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-251. LSxMSEL Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-12 RESERVED R 0h Reserved
11-10 MSEL_LS5 R/W 0h Master Select for LS5 RAM:
00: Memory is dedicated to CPU.
01: Memory is shared between CPU and CLA1.
10: Reserved.
11: Reserved.
Reset type: SYSRSn
9-8 MSEL_LS4 R/W 0h Master Select for LS4 RAM:
00: Memory is dedicated to CPU.
01: Memory is shared between CPU and CLA1.
10: Reserved.
11: Reserved.
Reset type: SYSRSn
7-6 MSEL_LS3 R/W 0h Master Select for LS3 RAM:
00: Memory is dedicated to CPU.
01: Memory is shared between CPU and CLA1.
10: Reserved.
11: Reserved.
Reset type: SYSRSn
5-4 MSEL_LS2 R/W 0h Master Select for LS2 RAM:
00: Memory is dedicated to CPU.
01: Memory is shared between CPU and CLA1.
10: Reserved.
11: Reserved.
Reset type: SYSRSn
3-2 MSEL_LS1 R/W 0h Master Select for LS1 RAM:
00: Memory is dedicated to CPU.
01: Memory is shared between CPU and CLA1.
10: Reserved.
11: Reserved.
Reset type: SYSRSn

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Table 3-251. LSxMSEL Register Field Descriptions (continued)

Bit Field Type Reset Description
1-0 MSEL_LS0 R/W 0h Master Select for LS0 RAM:
00: Memory is dedicated to CPU.
01: Memory is shared between CPU and CLA1.
10: Reserved.
11: Reserved.
Reset type: SYSRSn

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3.17.17.10 LSxCLAPGM Register (Offset = 26h) [Reset = 00000000h]

LSxCLAPGM is shown in Figure 3-225 and described in Table 3-252.
Return to the Summary Table.
Local Shared RAM Prog/Exe control Register
Figure 3-225. LSxCLAPGM Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED CLAPGM_LS5 CLAPGM_LS4 CLAPGM_LS3 CLAPGM_LS2 CLAPGM_LS1 CLAPGM_LS0
R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-252. LSxCLAPGM Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-6 RESERVED R 0h Reserved
5 CLAPGM_LS5 R/W 0h Selects LS5 RAM as program vs data memory for CLA:
0: CLA Data memory.
1: CLA Program memory.
Reset type: SYSRSn
4 CLAPGM_LS4 R/W 0h Selects LS4 RAM as program vs data memory for CLA:
0: CLA Data memory.
1: CLA Program memory.
Reset type: SYSRSn
3 CLAPGM_LS3 R/W 0h Selects LS3 RAM as program vs data memory for CLA:
0: CLA Data memory.
1: CLA Program memory.
Reset type: SYSRSn
2 CLAPGM_LS2 R/W 0h Selects LS2 RAM as program vs data memory for CLA:
0: CLA Data memory.
1: CLA Program memory.
Reset type: SYSRSn
1 CLAPGM_LS1 R/W 0h Selects LS1 RAM as program vs data memory for CLA:
0: CLA Data memory.
1: CLA Program memory.
Reset type: SYSRSn
0 CLAPGM_LS0 R/W 0h Selects LS0 RAM as program vs data memory for CLA:
0: CLA Data memory.
1: CLA Program memory.
Reset type: SYSRSn

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3.17.17.11 LSxACCPROT0 Register (Offset = 28h) [Reset = 00000000h]

LSxACCPROT0 is shown in Figure 3-226 and described in Table 3-253.
Return to the Summary Table.
Local Shared RAM Config Register 0
Figure 3-226. LSxACCPROT0 Register
31 30 29 28 27 26 25 24
RESERVED CPUWRPROT_ FETCHPROT_L
LS3 S3
R-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED CPUWRPROT_ FETCHPROT_L
LS2 S2
R-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED CPUWRPROT_ FETCHPROT_L
LS1 S1
R-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED CPUWRPROT_ FETCHPROT_L
LS0 S0
R-0h R/W-0h R/W-0h

Table 3-253. LSxACCPROT0 Register Field Descriptions

Bit Field Type Reset Description
31-26 RESERVED R 0h Reserved
25 CPUWRPROT_LS3 R/W 0h CPU WR Protection For LS3 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
24 FETCHPROT_LS3 R/W 0h Fetch Protection For LS3 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
23-18 RESERVED R 0h Reserved
17 CPUWRPROT_LS2 R/W 0h CPU WR Protection For LS2 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
16 FETCHPROT_LS2 R/W 0h Fetch Protection For LS2 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
15-10 RESERVED R 0h Reserved
9 CPUWRPROT_LS1 R/W 0h CPU WR Protection For LS1 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
8 FETCHPROT_LS1 R/W 0h Fetch Protection For LS1 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn

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Table 3-253. LSxACCPROT0 Register Field Descriptions (continued)

Bit Field Type Reset Description
7-2 RESERVED R 0h Reserved
1 CPUWRPROT_LS0 R/W 0h CPU WR Protection For LS0 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
0 FETCHPROT_LS0 R/W 0h Fetch Protection For LS0 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn

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3.17.17.12 LSxACCPROT1 Register (Offset = 2Ah) [Reset = 00000000h]

LSxACCPROT1 is shown in Figure 3-227 and described in Table 3-254.
Return to the Summary Table.
Local Shared RAM Config Register 1
Figure 3-227. LSxACCPROT1 Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED CPUWRPROT_ FETCHPROT_L
LS5 S5
R-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED CPUWRPROT_ FETCHPROT_L
LS4 S4
R-0h R/W-0h R/W-0h

Table 3-254. LSxACCPROT1 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-10 RESERVED R 0h Reserved
9 CPUWRPROT_LS5 R/W 0h CPU WR Protection For LS5 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
8 FETCHPROT_LS5 R/W 0h Fetch Protection For LS5 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
7-2 RESERVED R 0h Reserved
1 CPUWRPROT_LS4 R/W 0h CPU WR Protection For LS4 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
0 FETCHPROT_LS4 R/W 0h Fetch Protection For LS4 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn

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3.17.17.13 LSxTEST Register (Offset = 30h) [Reset = 00000000h]

LSxTEST is shown in Figure 3-228 and described in Table 3-255.
Return to the Summary Table.
Local Shared RAM TEST Register
Figure 3-228. LSxTEST Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED TEST_LS5 TEST_LS4
R-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
TEST_LS3 TEST_LS2 TEST_LS1 TEST_LS0
R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-255. LSxTEST Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-12 RESERVED R 0h Reserved
11-10 TEST_LS5 R/W 0h Selects the different modes for LS5 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn
9-8 TEST_LS4 R/W 0h Selects the different modes for LS4 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn
7-6 TEST_LS3 R/W 0h Selects the different modes for LS3 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn
5-4 TEST_LS2 R/W 0h Selects the different modes for LS2 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn
3-2 TEST_LS1 R/W 0h Selects the different modes for LS1 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn

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Table 3-255. LSxTEST Register Field Descriptions (continued)

Bit Field Type Reset Description
1-0 TEST_LS0 R/W 0h Selects the different modes for LS0 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn

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3.17.17.14 LSxINIT Register (Offset = 32h) [Reset = 00000000h]

LSxINIT is shown in Figure 3-229 and described in Table 3-256.
Return to the Summary Table.
Local Shared RAM Init Register
Figure 3-229. LSxINIT Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED INIT_LS5 INIT_LS4 INIT_LS3 INIT_LS2 INIT_LS1 INIT_LS0
R-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-256. LSxINIT Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-6 RESERVED R 0h Reserved
5 INIT_LS5 R-0/W1S 0h RAM Initialization control for LS5 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
4 INIT_LS4 R-0/W1S 0h RAM Initialization control for LS4 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
3 INIT_LS3 R-0/W1S 0h RAM Initialization control for LS3 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
2 INIT_LS2 R-0/W1S 0h RAM Initialization control for LS2 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
1 INIT_LS1 R-0/W1S 0h RAM Initialization control for LS1 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
0 INIT_LS0 R-0/W1S 0h RAM Initialization control for LS0 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn

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3.17.17.15 LSxINITDONE Register (Offset = 34h) [Reset = 00000000h]

LSxINITDONE is shown in Figure 3-230 and described in Table 3-257.
Return to the Summary Table.
Local Shared RAM InitDone Status Register
Figure 3-230. LSxINITDONE Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED INITDONE_LS5 INITDONE_LS4 INITDONE_LS3 INITDONE_LS2 INITDONE_LS1 INITDONE_LS0
R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 3-257. LSxINITDONE Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-6 RESERVED R 0h Reserved
5 INITDONE_LS5 R 0h RAM Initialization status for LS5 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
4 INITDONE_LS4 R 0h RAM Initialization status for LS4 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
3 INITDONE_LS3 R 0h RAM Initialization status for LS3 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
2 INITDONE_LS2 R 0h RAM Initialization status for LS2 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
1 INITDONE_LS1 R 0h RAM Initialization status for LS1 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
0 INITDONE_LS0 R 0h RAM Initialization status for LS0 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn

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3.17.17.16 GSxLOCK Register (Offset = 40h) [Reset = 00000000h]

GSxLOCK is shown in Figure 3-231 and described in Table 3-258.
Return to the Summary Table.
Global Shared RAM Config Lock Register
Figure 3-231. GSxLOCK Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
LOCK_GS15 LOCK_GS14 LOCK_GS13 LOCK_GS12 LOCK_GS11 LOCK_GS10 LOCK_GS9 LOCK_GS8
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
LOCK_GS7 LOCK_GS6 LOCK_GS5 LOCK_GS4 LOCK_GS3 LOCK_GS2 LOCK_GS1 LOCK_GS0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-258. GSxLOCK Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15 LOCK_GS15 R/W 0h Locks the write to access protection and master select fields for
GS15 RAM:
0: Write to ACCPROT and Mselect fields are allowed.
1: Write to ACCPROT and Mselect fields are blocked.
Reset type: SYSRSn
14 LOCK_GS14 R/W 0h Locks the write to access protection and master select fields for
GS14 RAM:
0: Write to ACCPROT and Mselect fields are allowed.
1: Write to ACCPROT and Mselect fields are blocked.
Reset type: SYSRSn
13 LOCK_GS13 R/W 0h Locks the write to access protection and master select fields for
GS13 RAM:
0: Write to ACCPROT and Mselect fields are allowed.
1: Write to ACCPROT and Mselect fields are blocked.
Reset type: SYSRSn
12 LOCK_GS12 R/W 0h Locks the write to access protection and master select fields for
GS12 RAM:
0: Write to ACCPROT and Mselect fields are allowed.
1: Write to ACCPROT and Mselect fields are blocked.
Reset type: SYSRSn
11 LOCK_GS11 R/W 0h Locks the write to access protection and master select fields for
GS11 RAM:
0: Write to ACCPROT and Mselect fields are allowed.
1: Write to ACCPROT and Mselect fields are blocked.
Reset type: SYSRSn
10 LOCK_GS10 R/W 0h Locks the write to access protection and master select fields for
GS10 RAM:
0: Write to ACCPROT and Mselect fields are allowed.
1: Write to ACCPROT and Mselect fields are blocked.
Reset type: SYSRSn

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Table 3-258. GSxLOCK Register Field Descriptions (continued)

Bit Field Type Reset Description
9 LOCK_GS9 R/W 0h Locks the write to access protection and master select fields for GS9
RAM:
0: Write to ACCPROT and Mselect fields are allowed.
1: Write to ACCPROT and Mselect fields are blocked.
Reset type: SYSRSn
8 LOCK_GS8 R/W 0h Locks the write to access protection and master select fields for GS8
RAM:
0: Write to ACCPROT and Mselect fields are allowed.
1: Write to ACCPROT and Mselect fields are blocked.
Reset type: SYSRSn
7 LOCK_GS7 R/W 0h Locks the write to access protection and master select fields for GS7
RAM:
0: Write to ACCPROT and Mselect fields are allowed.
1: Write to ACCPROT and Mselect fields are blocked.
Reset type: SYSRSn
6 LOCK_GS6 R/W 0h Locks the write to access protection and master select fields for GS6
RAM:
0: Write to ACCPROT and Mselect fields are allowed.
1: Write to ACCPROT and Mselect fields are blocked.
Reset type: SYSRSn
5 LOCK_GS5 R/W 0h Locks the write to access protection and master select fields for GS5
RAM:
0: Write to ACCPROT and Mselect fields are allowed.
1: Write to ACCPROT and Mselect fields are blocked.
Reset type: SYSRSn
4 LOCK_GS4 R/W 0h Locks the write to access protection and master select fields for GS4
RAM:
0: Write to ACCPROT and Mselect fields are allowed.
1: Write to ACCPROT and Mselect fields are blocked.
Reset type: SYSRSn
3 LOCK_GS3 R/W 0h Locks the write to access protection and master select fields for GS3
RAM:
0: Write to ACCPROT and Mselect fields are allowed.
1: Write to ACCPROT and Mselect fields are blocked.
Reset type: SYSRSn
2 LOCK_GS2 R/W 0h Locks the write to access protection and master select fields for GS2
RAM:
0: Write to ACCPROT and Mselect fields are allowed.
1: Write to ACCPROT and Mselect fields are blocked.
Reset type: SYSRSn
1 LOCK_GS1 R/W 0h Locks the write to access protection and master select fields for GS1
RAM:
0: Write to ACCPROT and Mselect fields are allowed.
1: Write to ACCPROT and Mselect fields are blocked.
Reset type: SYSRSn
0 LOCK_GS0 R/W 0h Locks the write to access protection and master select fields for GS0
RAM:
0: Write to ACCPROT and Mselect fields are allowed.
1: Write to ACCPROT and Mselect fields are blocked.
Reset type: SYSRSn

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3.17.17.17 GSxCOMMIT Register (Offset = 42h) [Reset = 00000000h]

GSxCOMMIT is shown in Figure 3-232 and described in Table 3-259.
Return to the Summary Table.
Global Shared RAM Config Lock Commit Register
Figure 3-232. GSxCOMMIT Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
COMMIT_GS15 COMMIT_GS14 COMMIT_GS13 COMMIT_GS12 COMMIT_GS11 COMMIT_GS10 COMMIT_GS9 COMMIT_GS8
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

7 6 5 4 3 2 1 0
COMMIT_GS7 COMMIT_GS6 COMMIT_GS5 COMMIT_GS4 COMMIT_GS3 COMMIT_GS2 COMMIT_GS1 COMMIT_GS0
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

Table 3-259. GSxCOMMIT Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15 COMMIT_GS15 R/WSonce 0h Permanently Locks the write to access protection and master select
fields for GS15 RAM:
0: Write to ACCPROT and Mselect fields are allowed based on value
of lock field in GSxLOCK register.
1: Write to ACCPROT and Mselect fields are permanently blocked.
Reset type: SYSRSn
14 COMMIT_GS14 R/WSonce 0h Permanently Locks the write to access protection and master select
fields for GS14 RAM:
0: Write to ACCPROT and Mselect fields are allowed based on value
of lock field in GSxLOCK register.
1: Write to ACCPROT and Mselect fields are permanently blocked.
Reset type: SYSRSn
13 COMMIT_GS13 R/WSonce 0h Permanently Locks the write to access protection and master select
fields for GS13 RAM:
0: Write to ACCPROT and Mselect fields are allowed based on value
of lock field in GSxLOCK register.
1: Write to ACCPROT and Mselect fields are permanently blocked.
Reset type: SYSRSn
12 COMMIT_GS12 R/WSonce 0h Permanently Locks the write to access protection and master select
fields for GS12 RAM:
0: Write to ACCPROT and Mselect fields are allowed based on value
of lock field in GSxLOCK register.
1: Write to ACCPROT and Mselect fields are permanently blocked.
Reset type: SYSRSn
11 COMMIT_GS11 R/WSonce 0h Permanently Locks the write to access protection and master select
fields for GS11 RAM:
0: Write to ACCPROT and Mselect fields are allowed based on value
of lock field in GSxLOCK register.
1: Write to ACCPROT and Mselect fields are permanently blocked.
Reset type: SYSRSn

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Table 3-259. GSxCOMMIT Register Field Descriptions (continued)

Bit Field Type Reset Description
10 COMMIT_GS10 R/WSonce 0h Permanently Locks the write to access protection and master select
fields for GS10 RAM:
0: Write to ACCPROT and Mselect fields are allowed based on value
of lock field in GSxLOCK register.
1: Write to ACCPROT and Mselect fields are permanently blocked.
Reset type: SYSRSn
9 COMMIT_GS9 R/WSonce 0h Permanently Locks the write to access protection and master select
fields for GS9 RAM:
0: Write to ACCPROT and Mselect fields are allowed based on value
of lock field in GSxLOCK register.
1: Write to ACCPROT and Mselect fields are permanently blocked.
Reset type: SYSRSn
8 COMMIT_GS8 R/WSonce 0h Permanently Locks the write to access protection and master select
fields for GS2 RAM:
0: Write to ACCPROT and Mselect fields are allowed based on value
of lock field in GSxLOCK register.
1: Write to ACCPROT and Mselect fields are permanently blocked.
Reset type: SYSRSn
7 COMMIT_GS7 R/WSonce 0h Permanently Locks the write to access protection and master select
fields for GS7 RAM:
0: Write to ACCPROT and Mselect fields are allowed based on value
of lock field in GSxLOCK register.
1: Write to ACCPROT and Mselect fields are permanently blocked.
Reset type: SYSRSn
6 COMMIT_GS6 R/WSonce 0h Permanently Locks the write to access protection and master select
fields for GS6 RAM:
0: Write to ACCPROT and Mselect fields are allowed based on value
of lock field in GSxLOCK register.
1: Write to ACCPROT and Mselect fields are permanently blocked.
Reset type: SYSRSn
5 COMMIT_GS5 R/WSonce 0h Permanently Locks the write to access protection and master select
fields for GS5 RAM:
0: Write to ACCPROT and Mselect fields are allowed based on value
of lock field in GSxLOCK register.
1: Write to ACCPROT and Mselect fields are permanently blocked.
Reset type: SYSRSn
4 COMMIT_GS4 R/WSonce 0h Permanently Locks the write to access protection and master select
fields for GS4 RAM:
0: Write to ACCPROT and Mselect fields are allowed based on value
of lock field in GSxLOCK register.
1: Write to ACCPROT and Mselect fields are permanently blocked.
Reset type: SYSRSn
3 COMMIT_GS3 R/WSonce 0h Permanently Locks the write to access protection and master select
fields for GS3 RAM:
0: Write to ACCPROT and Mselect fields are allowed based on value
of lock field in GSxLOCK register.
1: Write to ACCPROT and Mselect fields are permanently blocked.
Reset type: SYSRSn
2 COMMIT_GS2 R/WSonce 0h Permanently Locks the write to access protection and master select
fields for GS2 RAM:
0: Write to ACCPROT and Mselect fields are allowed based on value
of lock field in GSxLOCK register.
1: Write to ACCPROT and Mselect fields are permanently blocked.
Reset type: SYSRSn

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Table 3-259. GSxCOMMIT Register Field Descriptions (continued)

Bit Field Type Reset Description
1 COMMIT_GS1 R/WSonce 0h Permanently Locks the write to access protection and master select
fields for GS1 RAM:
0: Write to ACCPROT and Mselect fields are allowed based on value
of lock field in GSxLOCK register.
1: Write to ACCPROT and Mselect fields are permanently blocked.
Reset type: SYSRSn
0 COMMIT_GS0 R/WSonce 0h Permanently Locks the write to access protection and master select
fields for GS0 RAM:
0: Write to ACCPROT and Mselect fields are allowed based on value
of lock field in GSxLOCK register.
1: Write to ACCPROT and Mselect fields are permanently blocked.
Reset type: SYSRSn

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3.17.17.18 GSxMSEL Register (Offset = 44h) [Reset = 00000000h]

GSxMSEL is shown in Figure 3-233 and described in Table 3-260.
Return to the Summary Table.
Global Shared RAM Master Sel Register
Figure 3-233. GSxMSEL Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
MSEL_GS15 MSEL_GS14 MSEL_GS13 MSEL_GS12 MSEL_GS11 MSEL_GS10 MSEL_GS9 MSEL_GS8
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
MSEL_GS7 MSEL_GS6 MSEL_GS5 MSEL_GS4 MSEL_GS3 MSEL_GS2 MSEL_GS1 MSEL_GS0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-260. GSxMSEL Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15 MSEL_GS15 R/W 0h Master Select for GS15 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn
14 MSEL_GS14 R/W 0h Master Select for GS14 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn
13 MSEL_GS13 R/W 0h Master Select for GS13 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn
12 MSEL_GS12 R/W 0h Master Select for GS12 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn
11 MSEL_GS11 R/W 0h Master Select for GS11 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn
10 MSEL_GS10 R/W 0h Master Select for GS10 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn
9 MSEL_GS9 R/W 0h Master Select for GS9 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn

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Table 3-260. GSxMSEL Register Field Descriptions (continued)

Bit Field Type Reset Description
8 MSEL_GS8 R/W 0h Master Select for GS8 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn
7 MSEL_GS7 R/W 0h Master Select for GS7 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn
6 MSEL_GS6 R/W 0h Master Select for GS6 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn
5 MSEL_GS5 R/W 0h Master Select for GS5 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn
4 MSEL_GS4 R/W 0h Master Select for GS4 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn
3 MSEL_GS3 R/W 0h Master Select for GS3 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn
2 MSEL_GS2 R/W 0h Master Select for GS2 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn
1 MSEL_GS1 R/W 0h Master Select for GS1 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn
0 MSEL_GS0 R/W 0h Master Select for GS0 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn

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3.17.17.19 GSxACCPROT0 Register (Offset = 48h) [Reset = 00000000h]

GSxACCPROT0 is shown in Figure 3-234 and described in Table 3-261.
Return to the Summary Table.
Global Shared RAM Config Register 0
Figure 3-234. GSxACCPROT0 Register
31 30 29 28 27 26 25 24
RESERVED DMAWRPROT_ CPUWRPROT_ FETCHPROT_
GS3 GS3 GS3
R-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED DMAWRPROT_ CPUWRPROT_ FETCHPROT_
GS2 GS2 GS2
R-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED DMAWRPROT_ CPUWRPROT_ FETCHPROT_
GS1 GS1 GS1
R-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED DMAWRPROT_ CPUWRPROT_ FETCHPROT_
GS0 GS0 GS0
R-0h R/W-0h R/W-0h R/W-0h

Table 3-261. GSxACCPROT0 Register Field Descriptions

Bit Field Type Reset Description
31-27 RESERVED R 0h Reserved
26 DMAWRPROT_GS3 R/W 0h DMA WR Protection For GS3 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn
25 CPUWRPROT_GS3 R/W 0h CPU WR Protection For GS3 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
24 FETCHPROT_GS3 R/W 0h Fetch Protection For GS3 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
23-19 RESERVED R 0h Reserved
18 DMAWRPROT_GS2 R/W 0h DMA WR Protection For GS2 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn
17 CPUWRPROT_GS2 R/W 0h CPU WR Protection For GS2 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
16 FETCHPROT_GS2 R/W 0h Fetch Protection For GS2 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
15-11 RESERVED R 0h Reserved

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Table 3-261. GSxACCPROT0 Register Field Descriptions (continued)

Bit Field Type Reset Description
10 DMAWRPROT_GS1 R/W 0h DMA WR Protection For GS1 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn
9 CPUWRPROT_GS1 R/W 0h CPU WR Protection For GS1 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
8 FETCHPROT_GS1 R/W 0h Fetch Protection For GS1 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
7-3 RESERVED R 0h Reserved
2 DMAWRPROT_GS0 R/W 0h DMA WR Protection For GS0 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn
1 CPUWRPROT_GS0 R/W 0h CPU WR Protection For GS0 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
0 FETCHPROT_GS0 R/W 0h Fetch Protection For GS0 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn

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3.17.17.20 GSxACCPROT1 Register (Offset = 4Ah) [Reset = 00000000h]

GSxACCPROT1 is shown in Figure 3-235 and described in Table 3-262.
Return to the Summary Table.
Global Shared RAM Config Register 1
Figure 3-235. GSxACCPROT1 Register
31 30 29 28 27 26 25 24
RESERVED DMAWRPROT_ CPUWRPROT_ FETCHPROT_
GS7 GS7 GS7
R-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED DMAWRPROT_ CPUWRPROT_ FETCHPROT_
GS6 GS6 GS6
R-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED DMAWRPROT_ CPUWRPROT_ FETCHPROT_
GS5 GS5 GS5
R-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED DMAWRPROT_ CPUWRPROT_ FETCHPROT_
GS4 GS4 GS4
R-0h R/W-0h R/W-0h R/W-0h

Table 3-262. GSxACCPROT1 Register Field Descriptions

Bit Field Type Reset Description
31-27 RESERVED R 0h Reserved
26 DMAWRPROT_GS7 R/W 0h DMA WR Protection For GS7 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn
25 CPUWRPROT_GS7 R/W 0h CPU WR Protection For GS7 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
24 FETCHPROT_GS7 R/W 0h Fetch Protection For GS7 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
23-19 RESERVED R 0h Reserved
18 DMAWRPROT_GS6 R/W 0h DMA WR Protection For GS6 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn
17 CPUWRPROT_GS6 R/W 0h CPU WR Protection For GS6 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
16 FETCHPROT_GS6 R/W 0h Fetch Protection For GS6 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
15-11 RESERVED R 0h Reserved

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Table 3-262. GSxACCPROT1 Register Field Descriptions (continued)

Bit Field Type Reset Description
10 DMAWRPROT_GS5 R/W 0h DMA WR Protection For GS5 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn
9 CPUWRPROT_GS5 R/W 0h CPU WR Protection For GS5 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
8 FETCHPROT_GS5 R/W 0h Fetch Protection For GS5 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
7-3 RESERVED R 0h Reserved
2 DMAWRPROT_GS4 R/W 0h DMA WR Protection For GS4 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn
1 CPUWRPROT_GS4 R/W 0h CPU WR Protection For GS4 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
0 FETCHPROT_GS4 R/W 0h Fetch Protection For GS4 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn

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3.17.17.21 GSxACCPROT2 Register (Offset = 4Ch) [Reset = 00000000h]

GSxACCPROT2 is shown in Figure 3-236 and described in Table 3-263.
Return to the Summary Table.
Global Shared RAM Config Register 2
Figure 3-236. GSxACCPROT2 Register
31 30 29 28 27 26 25 24
RESERVED DMAWRPROT_ CPUWRPROT_ FETCHPROT_
GS11 GS11 GS11
R-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED DMAWRPROT_ CPUWRPROT_ FETCHPROT_
GS10 GS10 GS10
R-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED DMAWRPROT_ CPUWRPROT_ FETCHPROT_
GS9 GS9 GS9
R-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED DMAWRPROT_ CPUWRPROT_ FETCHPROT_
GS8 GS8 GS8
R-0h R/W-0h R/W-0h R/W-0h

Table 3-263. GSxACCPROT2 Register Field Descriptions

Bit Field Type Reset Description
31-27 RESERVED R 0h Reserved
26 DMAWRPROT_GS11 R/W 0h DMA WR Protection For GS11 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn
25 CPUWRPROT_GS11 R/W 0h CPU WR Protection For GS11 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
24 FETCHPROT_GS11 R/W 0h Fetch Protection For GS11 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
23-19 RESERVED R 0h Reserved
18 DMAWRPROT_GS10 R/W 0h DMA WR Protection For GS10 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn
17 CPUWRPROT_GS10 R/W 0h CPU WR Protection For GS10 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
16 FETCHPROT_GS10 R/W 0h Fetch Protection For GS10 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
15-11 RESERVED R 0h Reserved

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Table 3-263. GSxACCPROT2 Register Field Descriptions (continued)

Bit Field Type Reset Description
10 DMAWRPROT_GS9 R/W 0h DMA WR Protection For GS9 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn
9 CPUWRPROT_GS9 R/W 0h CPU WR Protection For GS9 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
8 FETCHPROT_GS9 R/W 0h Fetch Protection For GS9 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
7-3 RESERVED R 0h Reserved
2 DMAWRPROT_GS8 R/W 0h DMA WR Protection For GS8 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn
1 CPUWRPROT_GS8 R/W 0h CPU WR Protection For GS8 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
0 FETCHPROT_GS8 R/W 0h Fetch Protection For GS8 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn

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3.17.17.22 GSxACCPROT3 Register (Offset = 4Eh) [Reset = 00000000h]

GSxACCPROT3 is shown in Figure 3-237 and described in Table 3-264.
Return to the Summary Table.
Global Shared RAM Config Register 3
Figure 3-237. GSxACCPROT3 Register
31 30 29 28 27 26 25 24
RESERVED DMAWRPROT_ CPUWRPROT_ FETCHPROT_
GS15 GS15 GS15
R-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED DMAWRPROT_ CPUWRPROT_ FETCHPROT_
GS14 GS14 GS14
R-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED DMAWRPROT_ CPUWRPROT_ FETCHPROT_
GS13 GS13 GS13
R-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED DMAWRPROT_ CPUWRPROT_ FETCHPROT_
GS12 GS12 GS12
R-0h R/W-0h R/W-0h R/W-0h

Table 3-264. GSxACCPROT3 Register Field Descriptions

Bit Field Type Reset Description
31-27 RESERVED R 0h Reserved
26 DMAWRPROT_GS15 R/W 0h DMA WR Protection For GS15 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn
25 CPUWRPROT_GS15 R/W 0h CPU WR Protection For GS15 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
24 FETCHPROT_GS15 R/W 0h Fetch Protection For GS15 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
23-19 RESERVED R 0h Reserved
18 DMAWRPROT_GS14 R/W 0h DMA WR Protection For GS14 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn
17 CPUWRPROT_GS14 R/W 0h CPU WR Protection For GS14 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
16 FETCHPROT_GS14 R/W 0h Fetch Protection For GS14 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
15-11 RESERVED R 0h Reserved

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Table 3-264. GSxACCPROT3 Register Field Descriptions (continued)

Bit Field Type Reset Description
10 DMAWRPROT_GS13 R/W 0h DMA WR Protection For GS13 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn
9 CPUWRPROT_GS13 R/W 0h CPU WR Protection For GS13 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
8 FETCHPROT_GS13 R/W 0h Fetch Protection For GS13 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
7-3 RESERVED R 0h Reserved
2 DMAWRPROT_GS12 R/W 0h DMA WR Protection For GS12 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn
1 CPUWRPROT_GS12 R/W 0h CPU WR Protection For GS12 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
0 FETCHPROT_GS12 R/W 0h Fetch Protection For GS12 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn

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3.17.17.23 GSxTEST Register (Offset = 50h) [Reset = 00000000h]

GSxTEST is shown in Figure 3-238 and described in Table 3-265.
Return to the Summary Table.
Global Shared RAM TEST Register
Figure 3-238. GSxTEST Register
31 30 29 28 27 26 25 24
TEST_GS15 TEST_GS14 TEST_GS13 TEST_GS12
R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
TEST_GS11 TEST_GS10 TEST_GS9 TEST_GS8
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
TEST_GS7 TEST_GS6 TEST_GS5 TEST_GS4
R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
TEST_GS3 TEST_GS2 TEST_GS1 TEST_GS0
R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-265. GSxTEST Register Field Descriptions

Bit Field Type Reset Description
31-30 TEST_GS15 R/W 0h Selects the different modes for GS15 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn
29-28 TEST_GS14 R/W 0h Selects the different modes for GS14 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn
27-26 TEST_GS13 R/W 0h Selects the different modes for GS13 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn
25-24 TEST_GS12 R/W 0h Selects the different modes for GS12 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn
23-22 TEST_GS11 R/W 0h Selects the different modes for GS11 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn

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Table 3-265. GSxTEST Register Field Descriptions (continued)

Bit Field Type Reset Description
21-20 TEST_GS10 R/W 0h Selects the different modes for GS10 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn
19-18 TEST_GS9 R/W 0h Selects the different modes for GS9 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn
17-16 TEST_GS8 R/W 0h Selects the different modes for GS8 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn
15-14 TEST_GS7 R/W 0h Selects the different modes for GS7 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn
13-12 TEST_GS6 R/W 0h Selects the different modes for GS6 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn
11-10 TEST_GS5 R/W 0h Selects the different modes for GS5 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn
9-8 TEST_GS4 R/W 0h Selects the different modes for GS4 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn
7-6 TEST_GS3 R/W 0h Selects the different modes for GS3 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn
5-4 TEST_GS2 R/W 0h Selects the different modes for GS2 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn

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Table 3-265. GSxTEST Register Field Descriptions (continued)

Bit Field Type Reset Description
3-2 TEST_GS1 R/W 0h Selects the different modes for GS1 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn
1-0 TEST_GS0 R/W 0h Selects the different modes for GS0 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn

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3.17.17.24 GSxINIT Register (Offset = 52h) [Reset = 00000000h]

GSxINIT is shown in Figure 3-239 and described in Table 3-266.
Return to the Summary Table.
Global Shared RAM Init Register
Figure 3-239. GSxINIT Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
INIT_GS15 INIT_GS14 INIT_GS13 INIT_GS12 INIT_GS11 INIT_GS10 INIT_GS9 INIT_GS8
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

7 6 5 4 3 2 1 0
INIT_GS7 INIT_GS6 INIT_GS5 INIT_GS4 INIT_GS3 INIT_GS2 INIT_GS1 INIT_GS0
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-266. GSxINIT Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15 INIT_GS15 R-0/W1S 0h RAM Initialization control for GS15 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
14 INIT_GS14 R-0/W1S 0h RAM Initialization control for GS14 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
13 INIT_GS13 R-0/W1S 0h RAM Initialization control for GS13 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
12 INIT_GS12 R-0/W1S 0h RAM Initialization control for GS12 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
11 INIT_GS11 R-0/W1S 0h RAM Initialization control for GS11 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
10 INIT_GS10 R-0/W1S 0h RAM Initialization control for GS10 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
9 INIT_GS9 R-0/W1S 0h RAM Initialization control for GS9 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn

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Table 3-266. GSxINIT Register Field Descriptions (continued)

Bit Field Type Reset Description
8 INIT_GS8 R-0/W1S 0h RAM Initialization control for GS8 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
7 INIT_GS7 R-0/W1S 0h RAM Initialization control for GS7 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
6 INIT_GS6 R-0/W1S 0h RAM Initialization control for GS6 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
5 INIT_GS5 R-0/W1S 0h RAM Initialization control for GS5 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
4 INIT_GS4 R-0/W1S 0h RAM Initialization control for GS4 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
3 INIT_GS3 R-0/W1S 0h RAM Initialization control for GS3 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
2 INIT_GS2 R-0/W1S 0h RAM Initialization control for GS2 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
1 INIT_GS1 R-0/W1S 0h RAM Initialization control for GS1 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
0 INIT_GS0 R-0/W1S 0h RAM Initialization control for GS0 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn

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3.17.17.25 GSxINITDONE Register (Offset = 54h) [Reset = 00000000h]

GSxINITDONE is shown in Figure 3-240 and described in Table 3-267.
Return to the Summary Table.
Global Shared RAM InitDone Status Register
Figure 3-240. GSxINITDONE Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
INITDONE_GS INITDONE_GS INITDONE_GS INITDONE_GS INITDONE_GS INITDONE_GS INITDONE_GS INITDONE_GS
15 14 13 12 11 10 9 8
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
INITDONE_GS INITDONE_GS INITDONE_GS INITDONE_GS INITDONE_GS INITDONE_GS INITDONE_GS INITDONE_GS
7 6 5 4 3 2 1 0
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 3-267. GSxINITDONE Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15 INITDONE_GS15 R 0h RAM Initialization status for GS15 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
14 INITDONE_GS14 R 0h RAM Initialization status for GS14 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
13 INITDONE_GS13 R 0h RAM Initialization status for GS13 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
12 INITDONE_GS12 R 0h RAM Initialization status for GS12 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
11 INITDONE_GS11 R 0h RAM Initialization status for GS11 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
10 INITDONE_GS10 R 0h RAM Initialization status for GS10 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
9 INITDONE_GS9 R 0h RAM Initialization status for GS9 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn

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Table 3-267. GSxINITDONE Register Field Descriptions (continued)

Bit Field Type Reset Description
8 INITDONE_GS8 R 0h RAM Initialization status for GS8 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
7 INITDONE_GS7 R 0h RAM Initialization status for GS7 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
6 INITDONE_GS6 R 0h RAM Initialization status for GS6 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
5 INITDONE_GS5 R 0h RAM Initialization status for GS5 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
4 INITDONE_GS4 R 0h RAM Initialization status for GS4 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
3 INITDONE_GS3 R 0h RAM Initialization status for GS3 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
2 INITDONE_GS2 R 0h RAM Initialization status for GS2 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
1 INITDONE_GS1 R 0h RAM Initialization status for GS1 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
0 INITDONE_GS0 R 0h RAM Initialization status for GS0 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn

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3.17.17.26 MSGxTEST Register (Offset = 70h) [Reset = 00000000h]

MSGxTEST is shown in Figure 3-241 and described in Table 3-268.
Return to the Summary Table.
Message RAM TEST Register
Figure 3-241. MSGxTEST Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED
R-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED TEST_CLA1TOCPU TEST_CPUTOCLA1 TEST_CPUTOCPU
R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-268. MSGxTEST Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-10 RESERVED R 0h Reserved
9-8 RESERVED R/W 0h Reserved
7-6 RESERVED R/W 0h Reserved
5-4 TEST_CLA1TOCPU R/W 0h Selects the different modes for CLA1TOCPU MSG RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn
3-2 TEST_CPUTOCLA1 R/W 0h Selects the different modes for CPUTOCLA1 MSG RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn
1-0 TEST_CPUTOCPU R/W 0h Selects the different modes for CPUTOCPU MSG RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn

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3.17.17.27 MSGxINIT Register (Offset = 72h) [Reset = 00000000h]

MSGxINIT is shown in Figure 3-242 and described in Table 3-269.
Return to the Summary Table.
Message RAM Init Register
Figure 3-242. MSGxINIT Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED INIT_CLA1TOC INIT_CPUTOCL INIT_CPUTOC
PU A1 PU
R-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-269. MSGxINIT Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-5 RESERVED R 0h Reserved
4 RESERVED R-0/W1S 0h Reserved
3 RESERVED R-0/W1S 0h Reserved
2 INIT_CLA1TOCPU R-0/W1S 0h RAM Initialization control for CLA1TOCPU MSG RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
1 INIT_CPUTOCLA1 R-0/W1S 0h RAM Initialization control for CPUTOCLA1 MSG RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
0 INIT_CPUTOCPU R-0/W1S 0h RAM Initialization control for CPUTOCPU MSG RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn

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3.17.17.28 MSGxINITDONE Register (Offset = 74h) [Reset = 00000000h]

MSGxINITDONE is shown in Figure 3-243 and described in Table 3-270.
Return to the Summary Table.
Message RAM InitDone Status Register
Figure 3-243. MSGxINITDONE Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED INITDONE_CL INITDONE_CP INITDONE_CP
A1TOCPU UTOCLA1 UTOCPU
R-0h R-0h R-0h R-0h R-0h R-0h

Table 3-270. MSGxINITDONE Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-5 RESERVED R 0h Reserved
4 RESERVED R 0h Reserved
3 RESERVED R 0h Reserved
2 INITDONE_CLA1TOCPU R 0h RAM Initialization status for CLA1TOCPU MSG RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
1 INITDONE_CPUTOCLA1 R 0h RAM Initialization status for CPUTOCLA1 MSG RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
0 INITDONE_CPUTOCPU R 0h RAM Initialization status for CPUTOCPU MSG RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn

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3.17.18 ACCESS_PROTECTION_REGS Registers

Table 3-271 lists the memory-mapped registers for the ACCESS_PROTECTION_REGS registers. All register
offset addresses not listed in Table 3-271 should be considered as reserved locations and the register contents
should not be modified.
Table 3-271. ACCESS_PROTECTION_REGS Registers
Offset Acronym Register Name Write Protection Section
0h NMAVFLG Non-Master Access Violation Flag Register Go
2h NMAVSET Non-Master Access Violation Flag Set Register EALLOW Go
4h NMAVCLR Non-Master Access Violation Flag Clear Register EALLOW Go
6h NMAVINTEN Non-Master Access Violation Interrupt Enable EALLOW Go
Register
8h NMCPURDAVADDR Non-Master CPU Read Access Violation Address Go
Ah NMCPUWRAVADDR Non-Master CPU Write Access Violation Address Go
Ch NMCPUFAVADDR Non-Master CPU Fetch Access Violation Address Go
Eh NMDMAWRAVADDR Non-Master DMA Write Access Violation Address Go
10h NMCLA1RDAVADDR Non-Master CLA1 Read Access Violation Go
Address
12h NMCLA1WRAVADDR Non-Master CLA1 Write Access Violation Address Go
14h NMCLA1FAVADDR Non-Master CLA1 Fetch Access Violation Go
Address
20h MAVFLG Master Access Violation Flag Register Go
22h MAVSET Master Access Violation Flag Set Register EALLOW Go
24h MAVCLR Master Access Violation Flag Clear Register EALLOW Go
26h MAVINTEN Master Access Violation Interrupt Enable Register EALLOW Go
28h MCPUFAVADDR Master CPU Fetch Access Violation Address Go
2Ah MCPUWRAVADDR Master CPU Write Access Violation Address Go
2Ch MDMAWRAVADDR Master DMA Write Access Violation Address Go

Complex bit access types are encoded to fit into small table cells. Table 3-272 shows the codes that are used for
access types in this section.
Table 3-272. ACCESS_PROTECTION_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1S W Write
1S 1 to set
Reset or Default Value
-n Value after reset or the default value
Register Array Variables
i,j,k,l,m,n When these variables are used in a register name,
an offset, or an address, they refer to the value of a
register array where the register is part of a group
of repeating registers. The register groups form a
hierarchical structure and the array is represented
with a formula.

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Table 3-272. ACCESS_PROTECTION_REGS Access Type Codes (continued)

Access Type Code Description
y When this variable is used in a register name, an
offset, or an address it refers to the value of a
register array.

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3.17.18.1 NMAVFLG Register (Offset = 0h) [Reset = 00000000h]

NMAVFLG is shown in Figure 3-244 and described in Table 3-273.
Return to the Summary Table.
Non-Master Access Violation Flag Register
Figure 3-244. NMAVFLG Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED
R-0h R-0h R-0h

7 6 5 4 3 2 1 0
RESERVED CLA1FETCH CLA1WRITE CLA1READ DMAWRITE CPUFETCH CPUWRITE CPUREAD
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 3-273. NMAVFLG Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-10 RESERVED R 0h Reserved
9 RESERVED R 0h Reserved
8 RESERVED R 0h Reserved
7 RESERVED R 0h Reserved
6 CLA1FETCH R 0h Non Master CLA1 Fetch Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn
5 CLA1WRITE R 0h Non Master CLA1 Write Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn
4 CLA1READ R 0h Non Master CLA1 Read Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn
3 DMAWRITE R 0h Non Master DMA Write Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn
2 CPUFETCH R 0h Non Master CPU Fetch Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn
1 CPUWRITE R 0h Non Master CPU Write Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn

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Table 3-273. NMAVFLG Register Field Descriptions (continued)

Bit Field Type Reset Description
0 CPUREAD R 0h Non Master CPU Read Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn

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3.17.18.2 NMAVSET Register (Offset = 2h) [Reset = 00000000h]

NMAVSET is shown in Figure 3-245 and described in Table 3-274.
Return to the Summary Table.
Non-Master Access Violation Flag Set Register
Figure 3-245. NMAVSET Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED
R-0h R-0/W1S-0h R-0/W1S-0h

7 6 5 4 3 2 1 0
RESERVED CLA1FETCH CLA1WRITE CLA1READ DMAWRITE CPUFETCH CPUWRITE CPUREAD
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-274. NMAVSET Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-10 RESERVED R 0h Reserved
9 RESERVED R-0/W1S 0h Reserved
8 RESERVED R-0/W1S 0h Reserved
7 RESERVED R-0/W1S 0h Reserved
6 CLA1FETCH R-0/W1S 0h 0: No action.
1: CLA1 Fetch Access Violation Flag in NMAVFLG register will be set
and interrupt will be generated if enabled..
Reset type: SYSRSn
5 CLA1WRITE R-0/W1S 0h 0: No action.
1: CLA1 Write Access Violation Flag in NMAVFLG register will be set
and interrupt will be generated if enabled..
Reset type: SYSRSn
4 CLA1READ R-0/W1S 0h 0: No action.
1: CLA1 Read Access Violation Flag in NMAVFLG register will be set
and interrupt will be generated if enabled..
Reset type: SYSRSn
3 DMAWRITE R-0/W1S 0h 0: No action.
1: DMA Write Access Violation Flag in NMAVFLG register will be set
and interrupt will be generated if enabled..
Reset type: SYSRSn
2 CPUFETCH R-0/W1S 0h 0: No action.
1: CPU Fetch Access Violation Flag in NMAVFLG register will be set
and interrupt will be generated if enabled..
Reset type: SYSRSn
1 CPUWRITE R-0/W1S 0h 0: No action.
1: CPU Write Access Violation Flag in NMAVFLG register will be set
and interrupt will be generated if enabled..
Reset type: SYSRSn

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Table 3-274. NMAVSET Register Field Descriptions (continued)

Bit Field Type Reset Description
0 CPUREAD R-0/W1S 0h 0: No action.
1: CPU Read Access Violation Flag in NMAVFLG register will be set
and interrupt will be generated if enabled..
Reset type: SYSRSn

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3.17.18.3 NMAVCLR Register (Offset = 4h) [Reset = 00000000h]

NMAVCLR is shown in Figure 3-246 and described in Table 3-275.
Return to the Summary Table.
Non-Master Access Violation Flag Clear Register
Figure 3-246. NMAVCLR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED
R-0h R-0/W1S-0h R-0/W1S-0h

7 6 5 4 3 2 1 0
RESERVED CLA1FETCH CLA1WRITE CLA1READ DMAWRITE CPUFETCH CPUWRITE CPUREAD
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-275. NMAVCLR Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-10 RESERVED R 0h Reserved
9 RESERVED R-0/W1S 0h Reserved
8 RESERVED R-0/W1S 0h Reserved
7 RESERVED R-0/W1S 0h Reserved
6 CLA1FETCH R-0/W1S 0h 0: No action.
1: CLA1 Fetch Access Violation Flag in NMAVFLG register will be
cleared.
Reset type: SYSRSn
5 CLA1WRITE R-0/W1S 0h 0: No action.
1: CLA1 Write Access Violation Flag in NMAVFLG register will be
cleared.
Reset type: SYSRSn
4 CLA1READ R-0/W1S 0h 0: No action.
1: CLA1 Read Access Violation Flag in NMAVFLG register will be
cleared.
Reset type: SYSRSn
3 DMAWRITE R-0/W1S 0h 0: No action.
1: DMA Write Access Violation Flag in NMAVFLG register will be
cleared.
Reset type: SYSRSn
2 CPUFETCH R-0/W1S 0h 0: No action.
1: CPU Fetch Access Violation Flag in NMAVFLG register will be
cleared.
Reset type: SYSRSn
1 CPUWRITE R-0/W1S 0h 0: No action.
1: CPU Write Access Violation Flag in NMAVFLG register will be
cleared.
Reset type: SYSRSn

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Table 3-275. NMAVCLR Register Field Descriptions (continued)

Bit Field Type Reset Description
0 CPUREAD R-0/W1S 0h 0: No action.
1: CPU Read Access Violation Flag in NMAVFLG register will be
cleared.
Reset type: SYSRSn

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3.17.18.4 NMAVINTEN Register (Offset = 6h) [Reset = 00000000h]

NMAVINTEN is shown in Figure 3-247 and described in Table 3-276.
Return to the Summary Table.
Non-Master Access Violation Interrupt Enable Register
Figure 3-247. NMAVINTEN Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED
R-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED CLA1FETCH CLA1WRITE CLA1READ DMAWRITE CPUFETCH CPUWRITE CPUREAD
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-276. NMAVINTEN Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-10 RESERVED R 0h Reserved
9 RESERVED R/W 0h Reserved
8 RESERVED R/W 0h Reserved
7 RESERVED R/W 0h Reserved
6 CLA1FETCH R/W 0h 0: CLA1 Non Master Fetch Access Violation Interrupt is disabled.
1: CLA1 Non Master Fetch Access Violation Interrupt is enabled.
Reset type: SYSRSn
5 CLA1WRITE R/W 0h 0: CLA1 Non Master Write Access Violation Interrupt is disabled.
1: CLA1 Non Master Write Access Violation Interrupt is enabled.
Reset type: SYSRSn
4 CLA1READ R/W 0h 0: CLA1 Non Master Read Access Violation Interrupt is disabled.
1: CLA1 Non Master Read Access Violation Interrupt is enabled.
Reset type: SYSRSn
3 DMAWRITE R/W 0h 0: DMA Non Master Write Access Violation Interrupt is disabled.
1: DMA Non Master Write Access Violation Interrupt is enabled.
Reset type: SYSRSn
2 CPUFETCH R/W 0h 0: CPU Non Master Fetch Access Violation Interrupt is disabled.
1: CPU Non Master Fetch Access Violation Interrupt is enabled.
Reset type: SYSRSn
1 CPUWRITE R/W 0h 0: CPU Non Master Write Access Violation Interrupt is disabled.
1: CPU Non Master Write Access Violation Interrupt is enabled.
Reset type: SYSRSn
0 CPUREAD R/W 0h 0: CPU Non Master Read Access Violation Interrupt is disabled.
1: CPU Non Master Read Access Violation Interrupt is enabled.
Reset type: SYSRSn

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3.17.18.5 NMCPURDAVADDR Register (Offset = 8h) [Reset = 00000000h]

NMCPURDAVADDR is shown in Figure 3-248 and described in Table 3-277.
Return to the Summary Table.
Non-Master CPU Read Access Violation Address
Figure 3-248. NMCPURDAVADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NMCPURDAVADDR
R-0h

Table 3-277. NMCPURDAVADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 NMCPURDAVADDR R 0h This register captures the address location for which non master
CPU read access vaiolation occurred.
Reset type: SYSRSn

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3.17.18.6 NMCPUWRAVADDR Register (Offset = Ah) [Reset = 00000000h]

NMCPUWRAVADDR is shown in Figure 3-249 and described in Table 3-278.
Return to the Summary Table.
Non-Master CPU Write Access Violation Address
Figure 3-249. NMCPUWRAVADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NMCPUWRAVADDR
R-0h

Table 3-278. NMCPUWRAVADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 NMCPUWRAVADDR R 0h This register captures the address location for which non master
CPU write access vaiolation occurred.
Reset type: SYSRSn

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3.17.18.7 NMCPUFAVADDR Register (Offset = Ch) [Reset = 00000000h]

NMCPUFAVADDR is shown in Figure 3-250 and described in Table 3-279.
Return to the Summary Table.
Non-Master CPU Fetch Access Violation Address
Figure 3-250. NMCPUFAVADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NMCPUFAVADDR
R-0h

Table 3-279. NMCPUFAVADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 NMCPUFAVADDR R 0h This register captures the address location for which non master
CPU fetch access vaiolation occurred.
Reset type: SYSRSn

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3.17.18.8 NMDMAWRAVADDR Register (Offset = Eh) [Reset = 00000000h]

NMDMAWRAVADDR is shown in Figure 3-251 and described in Table 3-280.
Return to the Summary Table.
Non-Master DMA Write Access Violation Address
Figure 3-251. NMDMAWRAVADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NMDMAWRAVADDR
R-0h

Table 3-280. NMDMAWRAVADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 NMDMAWRAVADDR R 0h This register captures the address location for which non master
DMA write access vaiolation occurred.
Reset type: SYSRSn

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3.17.18.9 NMCLA1RDAVADDR Register (Offset = 10h) [Reset = 00000000h]

NMCLA1RDAVADDR is shown in Figure 3-252 and described in Table 3-281.
Return to the Summary Table.
Non-Master CLA1 Read Access Violation Address
Figure 3-252. NMCLA1RDAVADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NMCLA1RDAVADDR
R-0h

Table 3-281. NMCLA1RDAVADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 NMCLA1RDAVADDR R 0h This register captures the address location for which non master
CLA1 read access vaiolation occurred.
Reset type: SYSRSn

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3.17.18.10 NMCLA1WRAVADDR Register (Offset = 12h) [Reset = 00000000h]

NMCLA1WRAVADDR is shown in Figure 3-253 and described in Table 3-282.
Return to the Summary Table.
Non-Master CLA1 Write Access Violation Address
Figure 3-253. NMCLA1WRAVADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NMCLA1WRAVADDR
R-0h

Table 3-282. NMCLA1WRAVADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 NMCLA1WRAVADDR R 0h This register captures the address location for which non master
CLA1 write access vaiolation occurred.
Reset type: SYSRSn

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3.17.18.11 NMCLA1FAVADDR Register (Offset = 14h) [Reset = 00000000h]

NMCLA1FAVADDR is shown in Figure 3-254 and described in Table 3-283.
Return to the Summary Table.
Non-Master CLA1 Fetch Access Violation Address
Figure 3-254. NMCLA1FAVADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NMCLA1FAVADDR
R-0h

Table 3-283. NMCLA1FAVADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 NMCLA1FAVADDR R 0h This register captures the address location for which non master
CLA1 fetch access vaiolation occurred.
Reset type: SYSRSn

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3.17.18.12 MAVFLG Register (Offset = 20h) [Reset = 00000000h]

MAVFLG is shown in Figure 3-255 and described in Table 3-284.
Return to the Summary Table.
Master Access Violation Flag Register
Figure 3-255. MAVFLG Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED DMAWRITE CPUWRITE CPUFETCH
R-0h R-0h R-0h R-0h

Table 3-284. MAVFLG Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-3 RESERVED R 0h Reserved
2 DMAWRITE R 0h Master DMA Write Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn
1 CPUWRITE R 0h Master CPU Write Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn
0 CPUFETCH R 0h Master CPU Fetch Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn

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3.17.18.13 MAVSET Register (Offset = 22h) [Reset = 00000000h]

MAVSET is shown in Figure 3-256 and described in Table 3-285.
Return to the Summary Table.
Master Access Violation Flag Set Register
Figure 3-256. MAVSET Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED DMAWRITE CPUWRITE CPUFETCH
R-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-285. MAVSET Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-3 RESERVED R 0h Reserved
2 DMAWRITE R-0/W1S 0h 0: No action.
1: DMA Write Access Violation Flag in MAVFLG register will be set
and interrupt will be generated if enabled..
Reset type: SYSRSn
1 CPUWRITE R-0/W1S 0h 0: No action.
1: CPU Write Access Violation Flag in MAVFLG register will be set
and interrupt will be generated if enabled..
Reset type: SYSRSn
0 CPUFETCH R-0/W1S 0h 0: No action.
1: CPU Fetch Access Violation Flag in MAVFLG register will be set
and interrupt will be generated if enabled..
Reset type: SYSRSn

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3.17.18.14 MAVCLR Register (Offset = 24h) [Reset = 00000000h]

MAVCLR is shown in Figure 3-257 and described in Table 3-286.
Return to the Summary Table.
Master Access Violation Flag Clear Register
Figure 3-257. MAVCLR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED DMAWRITE CPUWRITE CPUFETCH
R-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-286. MAVCLR Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-3 RESERVED R 0h Reserved
2 DMAWRITE R-0/W1S 0h 0: No action.
1: DMA Write Access Violation Flag in MAVFLG register will be
cleared.
Reset type: SYSRSn
1 CPUWRITE R-0/W1S 0h 0: No action.
1: CPU Write Access Violation Flag in MAVFLG register will be
cleared .
Reset type: SYSRSn
0 CPUFETCH R-0/W1S 0h 0: No action.
1: CPU Fetch Access Violation Flag in MAVFLG register will be
cleared.
Reset type: SYSRSn

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3.17.18.15 MAVINTEN Register (Offset = 26h) [Reset = 00000000h]

MAVINTEN is shown in Figure 3-258 and described in Table 3-287.
Return to the Summary Table.
Master Access Violation Interrupt Enable Register
Figure 3-258. MAVINTEN Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED DMAWRITE CPUWRITE CPUFETCH
R-0h R/W-0h R/W-0h R/W-0h

Table 3-287. MAVINTEN Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-3 RESERVED R 0h Reserved
2 DMAWRITE R/W 0h 0: DMA Write Access Violation Interrupt is disabled.
1: DMA Write Access Violation Interrupt is enabled.
Reset type: SYSRSn
1 CPUWRITE R/W 0h 0: CPU Write Access Violation Interrupt is disabled.
1: CPU Write Access Violation Interrupt is enabled.
Reset type: SYSRSn
0 CPUFETCH R/W 0h 0: CPU Fetch Access Violation Interrupt is disabled.
1: CPU Fetch Access Violation Interrupt is enabled.
Reset type: SYSRSn

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3.17.18.16 MCPUFAVADDR Register (Offset = 28h) [Reset = 00000000h]

MCPUFAVADDR is shown in Figure 3-259 and described in Table 3-288.
Return to the Summary Table.
Master CPU Fetch Access Violation Address
Figure 3-259. MCPUFAVADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCPUFAVADDR
R-0h

Table 3-288. MCPUFAVADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 MCPUFAVADDR R 0h This register captures the address location for which master CPU
fetch access vaiolation occurred.
Reset type: SYSRSn

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3.17.18.17 MCPUWRAVADDR Register (Offset = 2Ah) [Reset = 00000000h]

MCPUWRAVADDR is shown in Figure 3-260 and described in Table 3-289.
Return to the Summary Table.
Master CPU Write Access Violation Address
Figure 3-260. MCPUWRAVADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCPUWRAVADDR
R-0h

Table 3-289. MCPUWRAVADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 MCPUWRAVADDR R 0h This register captures the address location for which master CPU
write access vaiolation occurred.
Reset type: SYSRSn

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3.17.18.18 MDMAWRAVADDR Register (Offset = 2Ch) [Reset = 00000000h]

MDMAWRAVADDR is shown in Figure 3-261 and described in Table 3-290.
Return to the Summary Table.
Master DMA Write Access Violation Address
Figure 3-261. MDMAWRAVADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDMAWRAVADDR
R-0h

Table 3-290. MDMAWRAVADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 MDMAWRAVADDR R 0h This register captures the address location for which master DMA
write access vaiolation occurred.
Reset type: SYSRSn

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3.17.19 MEMORY_ERROR_REGS Registers

Table 3-291 lists the memory-mapped registers for the MEMORY_ERROR_REGS registers. All register offset
addresses not listed in Table 3-291 should be considered as reserved locations and the register contents should
not be modified.
Table 3-291. MEMORY_ERROR_REGS Registers
Offset Acronym Register Name Write Protection Section
0h UCERRFLG Uncorrectable Error Flag Register Go
2h UCERRSET Uncorrectable Error Flag Set Register EALLOW Go
4h UCERRCLR Uncorrectable Error Flag Clear Register EALLOW Go
6h UCCPUREADDR Uncorrectable CPU Read Error Address Go
8h UCDMAREADDR Uncorrectable DMA Read Error Address Go
Ah UCCLA1READDR Uncorrectable CLA1 Read Error Address Go
20h CERRFLG Correctable Error Flag Register Go
22h CERRSET Correctable Error Flag Set Register EALLOW Go
24h CERRCLR Correctable Error Flag Clear Register EALLOW Go
26h CCPUREADDR Correctable CPU Read Error Address Go
2Eh CERRCNT Correctable Error Count Register Go
30h CERRTHRES Correctable Error Threshold Value Register EALLOW Go
32h CEINTFLG Correctable Error Interrupt Flag Status Register Go
34h CEINTCLR Correctable Error Interrupt Flag Clear Register EALLOW Go
36h CEINTSET Correctable Error Interrupt Flag Set Register EALLOW Go
38h CEINTEN Correctable Error Interrupt Enable Register EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 3-292 shows the codes that are used for
access types in this section.
Table 3-292. MEMORY_ERROR_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1S W Write
1S 1 to set
Reset or Default Value
-n Value after reset or the default value
Register Array Variables
i,j,k,l,m,n When these variables are used in a register name,
an offset, or an address, they refer to the value of a
register array where the register is part of a group
of repeating registers. The register groups form a
hierarchical structure and the array is represented
with a formula.
y When this variable is used in a register name, an
offset, or an address it refers to the value of a
register array.

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3.17.19.1 UCERRFLG Register (Offset = 0h) [Reset = 00000000h]

UCERRFLG is shown in Figure 3-262 and described in Table 3-293.
Return to the Summary Table.
Uncorrectable Error Flag Register
Figure 3-262. UCERRFLG Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED CLA1RDERR DMARDERR CPURDERR
R-0h R-0h R-0h R-0h R-0h

Table 3-293. UCERRFLG Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-4 RESERVED R 0h Reserved
3 RESERVED R 0h Reserved
2 CLA1RDERR R 0h CLA1 Uncorrectable Read Error Flag
0: No Error.
1: Uncorrectable error occurred during CLA1 read.
Reset type: SYSRSn
1 DMARDERR R 0h DMA Uncorrectable Read Error Flag
0: No Error.
1: Uncorrectable error occurred during DMA read.
Reset type: SYSRSn
0 CPURDERR R 0h CPU Uncorrectable Read Error Flag
0: No Error.
1: Uncorrectable error occurred during CPU read.
Reset type: SYSRSn

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3.17.19.2 UCERRSET Register (Offset = 2h) [Reset = 00000000h]

UCERRSET is shown in Figure 3-263 and described in Table 3-294.
Return to the Summary Table.
Uncorrectable Error Flag Set Register
Figure 3-263. UCERRSET Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED CLA1RDERR DMARDERR CPURDERR
R-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-294. UCERRSET Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-4 RESERVED R 0h Reserved
3 RESERVED R-0/W1S 0h Reserved
2 CLA1RDERR R-0/W1S 0h 0: No action.
1: CLA1 Read Error Flag in UCERRFLG register will be set and
interrupt will be generated if enabled..
Reset type: SYSRSn
1 DMARDERR R-0/W1S 0h 0: No action.
1: DMA Read Error Flag in UCERRFLG register will be set and
interrupt will be generated if enabled..
Reset type: SYSRSn
0 CPURDERR R-0/W1S 0h 0: No action.
1: CPU Read Error Flag in UCERRFLG register will be set and
interrupt will be generated if enabled..
Reset type: SYSRSn

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3.17.19.3 UCERRCLR Register (Offset = 4h) [Reset = 00000000h]

UCERRCLR is shown in Figure 3-264 and described in Table 3-295.
Return to the Summary Table.
Uncorrectable Error Flag Clear Register
Figure 3-264. UCERRCLR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED CLA1RDERR DMARDERR CPURDERR
R-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-295. UCERRCLR Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-4 RESERVED R 0h Reserved
3 RESERVED R-0/W1S 0h Reserved
2 CLA1RDERR R-0/W1S 0h 0: No action.
1: CLA1 Read Error Flag in UCERRFLG register will be cleared.
Reset type: SYSRSn
1 DMARDERR R-0/W1S 0h 0: No action.
1: DMA Read Error Flag in UCERRFLG register will be cleared .
Reset type: SYSRSn
0 CPURDERR R-0/W1S 0h 0: No action.
1: CPU Read Error Flag in UCERRFLG register will be cleared.
Reset type: SYSRSn

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3.17.19.4 UCCPUREADDR Register (Offset = 6h) [Reset = 00000000h]

UCCPUREADDR is shown in Figure 3-265 and described in Table 3-296.
Return to the Summary Table.
Uncorrectable CPU Read Error Address
Figure 3-265. UCCPUREADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UCCPUREADDR
R-0h

Table 3-296. UCCPUREADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 UCCPUREADDR R 0h This register captures the address location for which CPU read/fetch
access resulted in uncorrectable ECC/Parity error.
Reset type: SYSRSn

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3.17.19.5 UCDMAREADDR Register (Offset = 8h) [Reset = 00000000h]

UCDMAREADDR is shown in Figure 3-266 and described in Table 3-297.
Return to the Summary Table.
Uncorrectable DMA Read Error Address
Figure 3-266. UCDMAREADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UCDMAREADDR
R-0h

Table 3-297. UCDMAREADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 UCDMAREADDR R 0h This register captures the address location for which DMA read
access resulted in uncorrectable ECC/Parity error.
Reset type: SYSRSn

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3.17.19.6 UCCLA1READDR Register (Offset = Ah) [Reset = 00000000h]

UCCLA1READDR is shown in Figure 3-267 and described in Table 3-298.
Return to the Summary Table.
Uncorrectable CLA1 Read Error Address
Figure 3-267. UCCLA1READDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UCCLA1READDR
R-0h

Table 3-298. UCCLA1READDR Register Field Descriptions

Bit Field Type Reset Description
31-0 UCCLA1READDR R 0h This register captures the address location for which CLA1 read/
fetch access resulted in uncorrectable ECC/Parity error.
Reset type: SYSRSn

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3.17.19.7 CERRFLG Register (Offset = 20h) [Reset = 00000000h]

CERRFLG is shown in Figure 3-268 and described in Table 3-299.
Return to the Summary Table.
Correctable Error Flag Register
Figure 3-268. CERRFLG Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED CLA1RDERR DMARDERR CPURDERR
R-0h R-0h R-0h R-0h R-0h

Table 3-299. CERRFLG Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-4 RESERVED R 0h Reserved
3 RESERVED R 0h Reserved
2 CLA1RDERR R 0h CLA1 Correctable Read Error Flag
0: No Error.
1: Correctable error occurred during CLA1 read.
Reset type: SYSRSn
1 DMARDERR R 0h DMA Correctable Read Error Flag
0: No Error.
1: Correctable error occurred during DMA read.
Reset type: SYSRSn
0 CPURDERR R 0h CPU Correctable Read Error Flag
0: No Error.
1: Correctable error occurred during CPU read.
Reset type: SYSRSn

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3.17.19.8 CERRSET Register (Offset = 22h) [Reset = 00000000h]

CERRSET is shown in Figure 3-269 and described in Table 3-300.
Return to the Summary Table.
Correctable Error Flag Set Register
Figure 3-269. CERRSET Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED CLA1RDERR DMARDERR CPURDERR
R-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-300. CERRSET Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-4 RESERVED R 0h Reserved
3 RESERVED R-0/W1S 0h Reserved
2 CLA1RDERR R-0/W1S 0h 0: No action.
1: CLA1 Read Error Flag in CERRFLG register will be set and
interrupt will be generated if enabled..
Reset type: SYSRSn
1 DMARDERR R-0/W1S 0h 0: No action.
1: DMA Read Error Flag in CERRFLG register will be set and
interrupt will be generated if enabled..
Reset type: SYSRSn
0 CPURDERR R-0/W1S 0h 0: No action.
1: CPU Read Error Flag in CERRFLG register will be set and
interrupt will be generated if enabled..
Reset type: SYSRSn

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3.17.19.9 CERRCLR Register (Offset = 24h) [Reset = 00000000h]

CERRCLR is shown in Figure 3-270 and described in Table 3-301.
Return to the Summary Table.
Correctable Error Flag Clear Register
Figure 3-270. CERRCLR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED CLA1RDERR DMARDERR CPURDERR
R-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-301. CERRCLR Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-4 RESERVED R 0h Reserved
3 RESERVED R-0/W1S 0h Reserved
2 CLA1RDERR R-0/W1S 0h 0: No action.
1: CLA1 Read Error Flag in CERRFLG register will be cleared.
Reset type: SYSRSn
1 DMARDERR R-0/W1S 0h 0: No action.
1: DMA Read Error Flag in CERRFLG register will be cleared .
Reset type: SYSRSn
0 CPURDERR R-0/W1S 0h 0: No action.
1: CPU Read Error Flag in CERRFLG register will be cleared.
Reset type: SYSRSn

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3.17.19.10 CCPUREADDR Register (Offset = 26h) [Reset = 00000000h]

CCPUREADDR is shown in Figure 3-271 and described in Table 3-302.
Return to the Summary Table.
Correctable CPU Read Error Address
Figure 3-271. CCPUREADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCPUREADDR
R-0h

Table 3-302. CCPUREADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 CCPUREADDR R 0h This register captures the address location for which CPU read/fetch
access resulted in correctable ECC error.
Reset type: SYSRSn

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3.17.19.11 CERRCNT Register (Offset = 2Eh) [Reset = 00000000h]

CERRCNT is shown in Figure 3-272 and described in Table 3-303.
Return to the Summary Table.
Correctable Error Count Register
Figure 3-272. CERRCNT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED CERRCNT
R-0h R-0h

Table 3-303. CERRCNT Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-0 CERRCNT R 0h This register holds the count of how many times correctable error
occurred.
Reset type: SYSRSn

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3.17.19.12 CERRTHRES Register (Offset = 30h) [Reset = 00000000h]

CERRTHRES is shown in Figure 3-273 and described in Table 3-304.
Return to the Summary Table.
Correctable Error Threshold Value Register
Figure 3-273. CERRTHRES Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED CERRTHRES
R-0h R/W-0h

Table 3-304. CERRTHRES Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-0 CERRTHRES R/W 0h When value in CERRCNT register is greater or equal to than value
configured in this register, corretable interrupt gets generated, if
enabled.
Reset type: SYSRSn

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3.17.19.13 CEINTFLG Register (Offset = 32h) [Reset = 00000000h]

CEINTFLG is shown in Figure 3-274 and described in Table 3-305.
Return to the Summary Table.
Correctable Error Interrupt Flag Status Register
Figure 3-274. CEINTFLG Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED CEINTFLAG
R-0h R-0h

Table 3-305. CEINTFLG Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-1 RESERVED R 0h Reserved
0 CEINTFLAG R 0h Total corrected error count exceeded threshold Flag
0: Total correctable errors < Threshold value configured in
CERRTHRES register.
1: Total correctable errors >= Threshold value configured in
CERRTHRES register.
Reset type: SYSRSn

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3.17.19.14 CEINTCLR Register (Offset = 34h) [Reset = 00000000h]

CEINTCLR is shown in Figure 3-275 and described in Table 3-306.
Return to the Summary Table.
Correctable Error Interrupt Flag Clear Register
Figure 3-275. CEINTCLR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED CEINTCLR
R-0h R-0/W1S-0h

Table 3-306. CEINTCLR Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-1 RESERVED R 0h Reserved
0 CEINTCLR R-0/W1S 0h 0: No action.
1: Total corrected error count exceeded flag in CEINTFLG register
will be cleared.
Reset type: SYSRSn

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3.17.19.15 CEINTSET Register (Offset = 36h) [Reset = 00000000h]

CEINTSET is shown in Figure 3-276 and described in Table 3-307.
Return to the Summary Table.
Correctable Error Interrupt Flag Set Register
Figure 3-276. CEINTSET Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED CEINTSET
R-0h R-0/W1S-0h

Table 3-307. CEINTSET Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-1 RESERVED R 0h Reserved
0 CEINTSET R-0/W1S 0h 0: No action.
1: Total corrected error count exceeded flag in CEINTFLG register
will be set and interrupt will be generated if enabled.
Reset type: SYSRSn

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3.17.19.16 CEINTEN Register (Offset = 38h) [Reset = 00000000h]

CEINTEN is shown in Figure 3-277 and described in Table 3-308.
Return to the Summary Table.
Correctable Error Interrupt Enable Register
Figure 3-277. CEINTEN Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED CEINTEN
R-0h R/W-0h

Table 3-308. CEINTEN Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-1 RESERVED R 0h Reserved
0 CEINTEN R/W 0h 0: Correctable Error Interrupt is disabled.
1: Correctable Error Interrupt is enabled.
Reset type: SYSRSn

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3.17.20 ROM_WAIT_STATE_REGS Registers

Table 3-309 lists the memory-mapped registers for the ROM_WAIT_STATE_REGS registers. All register offset
addresses not listed in Table 3-309 should be considered as reserved locations and the register contents should
not be modified.
Table 3-309. ROM_WAIT_STATE_REGS Registers
Offset Acronym Register Name Write Protection Section
0h ROMWAITSTATE ROM Wait State Configuration Register EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 3-310 shows the codes that are used for
access types in this section.
Table 3-310. ROM_WAIT_STATE_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default value
Register Array Variables
i,j,k,l,m,n When these variables are used in a register name,
an offset, or an address, they refer to the value of a
register array where the register is part of a group
of repeating registers. The register groups form a
hierarchical structure and the array is represented
with a formula.
y When this variable is used in a register name, an
offset, or an address it refers to the value of a
register array.

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3.17.20.1 ROMWAITSTATE Register (Offset = 0h) [Reset = 00000000h]

ROMWAITSTATE is shown in Figure 3-278 and described in Table 3-311.
Return to the Summary Table.
ROM Wait State Configuration Register
Figure 3-278. ROMWAITSTATE Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED WSDISABLE
R-0h R/W-0h

Table 3-311. ROMWAITSTATE Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-1 RESERVED R 0h Reserved
0 WSDISABLE R/W 0h 0: C28x ROM Wait State is enabled. C28x CPU accesses to ROM
are are 1-wait.
1: C28x ROM Wait State is disabled. C28x CPU accesses to ROM
are 0-wait.
Reset type: SYSRSn

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3.17.21 FLASH_CTRL_REGS Registers

Table 3-312 lists the memory-mapped registers for the FLASH_CTRL_REGS registers. All register offset
addresses not listed in Table 3-312 should be considered as reserved locations and the register contents should
not be modified.
Table 3-312. FLASH_CTRL_REGS Registers
Offset Acronym Register Name Write Protection Section
0h FRDCNTL Flash Read Control Register EALLOW Go
1Eh FBAC Flash Bank Access Control Register EALLOW Go
20h FBFALLBACK Flash Bank Fallback Power Register EALLOW Go
22h FBPRDY Flash Bank Pump Ready Register EALLOW Go
24h FPAC1 Flash Pump Access Control Register 1 EALLOW Go
2Ah FMSTAT Flash Module Status Register EALLOW Go
180h FRD_INTF_CTRL Flash Read Interface Control Register EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 3-313 shows the codes that are used for
access types in this section.
Table 3-313. FLASH_CTRL_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default value
Register Array Variables
i,j,k,l,m,n When these variables are used in a register name,
an offset, or an address, they refer to the value of a
register array where the register is part of a group
of repeating registers. The register groups form a
hierarchical structure and the array is represented
with a formula.
y When this variable is used in a register name, an
offset, or an address it refers to the value of a
register array.

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3.17.21.1 FRDCNTL Register (Offset = 0h) [Reset = 00000F00h]

FRDCNTL is shown in Figure 3-279 and described in Table 3-314.
Return to the Summary Table.
Flash Read Control Register
Figure 3-279. FRDCNTL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RWAIT RESERVED
R-0h R/W-Fh R-0h

Table 3-314. FRDCNTL Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-12 RESERVED R 0h Reserved
11-8 RWAIT R/W Fh Random read waitstate
These bits indicate how many waitstates are added to a flash read/
fetch access. The RWAIT value can be set anywhere from 0 to 0xF.
For a flash access, data is returned in RWAIT+1 SYSCLK cycles.
Note: The required wait states for each SYSCLK frequency can be
found in the device data manual.
Reset type: SYSRSn
7-0 RESERVED R 0h Reserved

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3.17.21.2 FBAC Register (Offset = 1Eh) [Reset = 0000000Fh]

FBAC is shown in Figure 3-280 and described in Table 3-315.
Return to the Summary Table.
Flash Bank Access Control Register
Figure 3-280. FBAC Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RESERVED VREADST
R-0h R/W-0h R/W-Fh

Table 3-315. FBAC Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-8 RESERVED R/W 0h Reserved
7-0 VREADST R/W Fh This bit-field ensures that the requisite delay is introduced for the
flash pump/bank to come out of low-power mode, so that the
flash/OTP array is ready for CPU accesses.
Recommended configuration:
0xF (reset value) - If SYSCLK=10MHz (INTOSC)
0x14 - If SYSCLK > 10MHz
Before entering any low-power mode for the flash bank/pump, this
bit must be configured as described in the 'Flash and OTP Memory'
chapter of the TRM. Applications typically use the flash bank/pump
low-power modes to reduce power for following reasons:
(i) during the device-level low-power modes such as IDLE/
STANDBY/HALT
(ii) while running code off RAM after powering down the flash.
Reset type: SYSRSn

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3.17.21.3 FBFALLBACK Register (Offset = 20h) [Reset = 00000000h]

FBFALLBACK is shown in Figure 3-281 and described in Table 3-316.
Return to the Summary Table.
Flash Bank Fallback Power Register
Figure 3-281. FBFALLBACK Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED BNKPWR0
R-0h R/W-0h

Table 3-316. FBFALLBACK Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-2 RESERVED R 0h Reserved
1-0 BNKPWR0 R/W 0h Bank Power Mode Control
00 Sleep (Sense amplifiers and sense reference disabled)
01 Standby (Sense amplifiers disabled, but sense reference
enabled)
10 Reserved
11 Active (Both sense amplifiers and sense reference enabled)
Note: If the bank and pump are not in active mode and an access is
made, the value of this register is automatically changed to active.
Reset type: SYSRSn

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3.17.21.4 FBPRDY Register (Offset = 22h) [Reset = 00000000h]

FBPRDY is shown in Figure 3-282 and described in Table 3-317.
Return to the Summary Table.
Flash Bank Pump Ready Register
Figure 3-282. FBPRDY Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
PUMPRDY RESERVED
R-0h R-0h

7 6 5 4 3 2 1 0
RESERVED BANKRDY
R-0h R-0h

Table 3-317. FBPRDY Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15 PUMPRDY R 0h Pump Ready. This is a read-only bit which allows software to
determine if the pump is ready for flash access before attempting
the actual access. If an access is made to a bank when the pump is
not ready, wait states are asserted until it becomes ready.
0 Pump is not ready.
1 Pump is ready, in active power state.
Reset type: SYSRSn
14-1 RESERVED R 0h Reserved
0 BANKRDY R 0h Bank Ready. This is a read-only register which allows software to
determine if the bank is ready for Flash access before the access is
attempted.
Note: The user should wait for both the pump and the bank to be
ready before attempting an access.
0 Bank is not ready.
1 Bank is in active power mode and is ready for access.
Reset type: SYSRSn

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3.17.21.5 FPAC1 Register (Offset = 24h) [Reset = 08600000h]

FPAC1 is shown in Figure 3-283 and described in Table 3-318.
Return to the Summary Table.
Flash Pump Access Control Register 1
Figure 3-283. FPAC1 Register
31 30 29 28 27 26 25 24
RESERVED PSLEEP
R-0h R/W-860h

23 22 21 20 19 18 17 16
PSLEEP
R/W-860h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED PMPPWR
R-0h R/W-0h

Table 3-318. FPAC1 Register Field Descriptions

Bit Field Type Reset Description
31-28 RESERVED R 0h Reserved
27-16 PSLEEP R/W 860h Pump sleep. These bits contain the starting count value for the
charge pump sleep down counter. While the charge pump is in
sleep mode, the power mode management logic holds the charge
pump sleep counter at this value. When the charge pump exits sleep
power mode, the down counter delays from 0 to PSLEEP prescaled
SYSCLK clock cycles before putting the charge pump into active
power mode.
Note: The pump sleep down counter uses a prescaled clock which is
divided by 2 of input SYSCLK. The configured PSLEEP value should
yield a delay of at least 20 microseconds for the pump to go to active
mode.
Reset type: SYSRSn
15-1 RESERVED R 0h Reserved
0 PMPPWR R/W 0h Flash Charge Pump Control Power Mode.
Configures the power mode of the charge pump.
0 Sleep (all pump circuits disabled)
1 Active (all pump circuits active)
Reset type: SYSRSn

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3.17.21.6 FMSTAT Register (Offset = 2Ah) [Reset = 00000000h]

FMSTAT is shown in Figure 3-284 and described in Table 3-319.
Return to the Summary Table.
Flash Module Status Register
Figure 3-284. FMSTAT Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED
R-0h R-0h R-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED PGV RESERVED EV RESERVED BUSY
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
ERS PGM INVDAT CSTAT VOLTSTAT ESUSP PSUSP RESERVED
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 3-319. FMSTAT Register Field Descriptions

Bit Field Type Reset Description
31-18 RESERVED R 0h Reserved
17 RESERVED R 0h Reserved
16 RESERVED R 0h Reserved
15 RESERVED R 0h Reserved
14 RESERVED R 0h Reserved
13 RESERVED R 0h Reserved
12 PGV R 0h Program verify When set, indicates that a word is not successfully
programmed after the maximum allowed number of program pulses
are given for program operation.
Reset type: SYSRSn
11 RESERVED R 0h Reserved
10 EV R 0h Erase verify When set, indicates that a sector is not successfully
erased after the maximum allowed number of erase pulses are given
for erase operation.
Reset type: SYSRSn
9 RESERVED R 0h Reserved
8 BUSY R 0h When set, this bit indicates that a program, erase, or suspend
operation is being processed.
Reset type: SYSRSn
7 ERS R 0h Erase Active. When set, this bit indicates that the flash module is
actively performing an erase operation. This bit is set when erasing
starts and is cleared when erasing is complete. It is also cleared
when the erase is suspended and set when the erase resumes.
Reset type: SYSRSn
6 PGM R 0h Program Active. When set, this bit indicates that the flash module
is currently performing a program operation. This bit is set when
programming starts and is cleared when programming is complete.
It is also cleared when programming is suspended and set when
programming is resumed.
Reset type: SYSRSn

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Table 3-319. FMSTAT Register Field Descriptions (continued)

Bit Field Type Reset Description
5 INVDAT R 0h Invalid Data. When set, this bit indicates that the user attempted to
program a '1' where a '0' was already present.
Reset type: SYSRSn
4 CSTAT R 0h Command Status. Once the FSM starts any failure will set this bit.
When set, this bit informs the host that the program, erase, or
validate sector command failed and the command was stopped. This
bit is cleared by the Clear Status command. For some errors, this will
be the only indication of an FSM error because the cause does not
fall within the other error bit types.
Reset type: SYSRSn
3 VOLTSTAT R 0h Core Voltage Status. When set, this bit indicates that the core
voltage generator of the pump power upply dipped below the lower
limit allowable during a program or erase operation.
Reset type: SYSRSn
2 ESUSP R 0h When set, this bit indicates that the flash module has received and
processed an erase suspend operation. This bit remains set until the
erase resume command has been issued or until the Clear_More
command is run.
Reset type: SYSRSn
1 PSUSP R 0h When set, this bit indicates that the flash module has received
and processed a program suspend operation. This bit remains set
until the program resume command has been issued or until the
Clear_More command is run.
Reset type: SYSRSn
0 RESERVED R 0h Reserved

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3.17.21.7 FRD_INTF_CTRL Register (Offset = 180h) [Reset = 00000000h]

FRD_INTF_CTRL is shown in Figure 3-285 and described in Table 3-320.
Return to the Summary Table.
Flash Read Interface Control Register
Figure 3-285. FRD_INTF_CTRL Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED DATA_CACHE_ PREFETCH_E
EN N
R-0h R/W-0h R/W-0h

Table 3-320. FRD_INTF_CTRL Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-2 RESERVED R 0h Reserved
1 DATA_CACHE_EN R/W 0h Data cache enable.
0 A value of 0 disables the data cache.
1 A value of 1 enables the data cache.
Reset type: SYSRSn
0 PREFETCH_EN R/W 0h Prefetch enable.
0 A value of 0 disables prefetch mechanism.
1 A value of 1 enables pre-fetch mechanism.
Reset type: SYSRSn

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3.17.22 FLASH_ECC_REGS Registers

Table 3-321 lists the memory-mapped registers for the FLASH_ECC_REGS registers. All register offset
addresses not listed in Table 3-321 should be considered as reserved locations and the register contents should
not be modified.
Table 3-321. FLASH_ECC_REGS Registers
Offset Acronym Register Name Write Protection Section
0h ECC_ENABLE ECC Enable EALLOW Go
2h SINGLE_ERR_ADDR_LOW Single Error Address Low EALLOW Go
4h SINGLE_ERR_ADDR_HIGH Single Error Address High EALLOW Go
6h UNC_ERR_ADDR_LOW Uncorrectable Error Address Low EALLOW Go
8h UNC_ERR_ADDR_HIGH Uncorrectable Error Address High EALLOW Go
Ah ERR_STATUS Error Status EALLOW Go
Ch ERR_POS Error Position EALLOW Go
Eh ERR_STATUS_CLR Error Status Clear EALLOW Go
10h ERR_CNT Error Control EALLOW Go
12h ERR_THRESHOLD Error Threshold EALLOW Go
14h ERR_INTFLG Error Interrupt Flag EALLOW Go
16h ERR_INTCLR Error Interrupt Flag Clear EALLOW Go
18h FDATAH_TEST Data High Test EALLOW Go
1Ah FDATAL_TEST Data Low Test EALLOW Go
1Ch FADDR_TEST ECC Test Address EALLOW Go
1Eh FECC_TEST ECC Test Address EALLOW Go
20h FECC_CTRL ECC Control EALLOW Go
22h FOUTH_TEST Test Data Out High EALLOW Go
24h FOUTL_TEST Test Data Out Low EALLOW Go
26h FECC_STATUS ECC Status EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 3-322 shows the codes that are used for
access types in this section.
Table 3-322. FLASH_ECC_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1S W Write
1S 1 to set
Reset or Default Value
-n Value after reset or the default value
Register Array Variables
i,j,k,l,m,n When these variables are used in a register name,
an offset, or an address, they refer to the value of a
register array where the register is part of a group
of repeating registers. The register groups form a
hierarchical structure and the array is represented
with a formula.

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Table 3-322. FLASH_ECC_REGS Access Type Codes (continued)

Access Type Code Description
y When this variable is used in a register name, an
offset, or an address it refers to the value of a
register array.

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3.17.22.1 ECC_ENABLE Register (Offset = 0h) [Reset = 0000000Ah]

ECC_ENABLE is shown in Figure 3-286 and described in Table 3-323.
Return to the Summary Table.
ECC Enable
Figure 3-286. ECC_ENABLE Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED ENABLE
R-0h R/W-Ah

Table 3-323. ECC_ENABLE Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-4 RESERVED R 0h Reserved
3-0 ENABLE R/W Ah ECC enable. A value of 0xA would enable ECC. Any other value
would disable ECC.
Reset type: SYSRSn

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3.17.22.2 SINGLE_ERR_ADDR_LOW Register (Offset = 2h) [Reset = 00000000h]

SINGLE_ERR_ADDR_LOW is shown in Figure 3-287 and described in Table 3-324.
Return to the Summary Table.
Single Error Address Low
Figure 3-287. SINGLE_ERR_ADDR_LOW Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ERR_ADDR_L
R/W-0h

Table 3-324. SINGLE_ERR_ADDR_LOW Register Field Descriptions

Bit Field Type Reset Description
31-0 ERR_ADDR_L R/W 0h 64-bit aligned address at which a single bit error occurred in the
lower 64-bits of a 128-bit aligned memory.
Reset type: SYSRSn

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3.17.22.3 SINGLE_ERR_ADDR_HIGH Register (Offset = 4h) [Reset = 00000000h]

SINGLE_ERR_ADDR_HIGH is shown in Figure 3-288 and described in Table 3-325.
Return to the Summary Table.
Single Error Address High
Figure 3-288. SINGLE_ERR_ADDR_HIGH Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ERR_ADDR_H
R/W-0h

Table 3-325. SINGLE_ERR_ADDR_HIGH Register Field Descriptions

Bit Field Type Reset Description
31-0 ERR_ADDR_H R/W 0h 64-bit aligned address at which a single bit error occurred in the
upper 64-bits of a 128-bit aligned memory.
Reset type: SYSRSn

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3.17.22.4 UNC_ERR_ADDR_LOW Register (Offset = 6h) [Reset = 00000000h]

UNC_ERR_ADDR_LOW is shown in Figure 3-289 and described in Table 3-326.
Return to the Summary Table.
Uncorrectable Error Address Low
Figure 3-289. UNC_ERR_ADDR_LOW Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UNC_ERR_ADDR_L
R/W-0h

Table 3-326. UNC_ERR_ADDR_LOW Register Field Descriptions

Bit Field Type Reset Description
31-0 UNC_ERR_ADDR_L R/W 0h 64-bit aligned address at which an uncorrectable error occurred in
the lower 64-bits of a 128-bit aligned memory.
Reset type: SYSRSn

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3.17.22.5 UNC_ERR_ADDR_HIGH Register (Offset = 8h) [Reset = 00000000h]

UNC_ERR_ADDR_HIGH is shown in Figure 3-290 and described in Table 3-327.
Return to the Summary Table.
Uncorrectable Error Address High
Figure 3-290. UNC_ERR_ADDR_HIGH Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UNC_ERR_ADDR_H
R/W-0h

Table 3-327. UNC_ERR_ADDR_HIGH Register Field Descriptions

Bit Field Type Reset Description
31-0 UNC_ERR_ADDR_H R/W 0h 64-bit aligned address at which an uncorrectable error occurred in
the upper 64-bits of a 128-bit aligned memory.
Reset type: SYSRSn

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3.17.22.6 ERR_STATUS Register (Offset = Ah) [Reset = 00000000h]

ERR_STATUS is shown in Figure 3-291 and described in Table 3-328.
Return to the Summary Table.
Error Status
Figure 3-291. ERR_STATUS Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED UNC_ERR_H FAIL_1_H FAIL_0_H
R-0h R-0h R-0h R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED UNC_ERR_L FAIL_1_L FAIL_0_L
R-0h R-0h R-0h R-0h

Table 3-328. ERR_STATUS Register Field Descriptions

Bit Field Type Reset Description
31-19 RESERVED R 0h Reserved
18 UNC_ERR_H R 0h Uncorrectable error. A value of 1 indicates that an un-correctable
error occurred in upper 64bits of a 128-bit aligned address. Cleared
by writing a 1 to UNC_ERR_H_CLR bit of ERR_STATUS_CLR
register.
Reset type: SYSRSn
17 FAIL_1_H R 0h Fail on 1.
0 Fail on 1 single bit error did not occur in upper 64bits of a 128-bit
aligned address.
1 A value of 1 would indicate that a single bit error occurred in upper
64bits of a 128-bit aligned address and the corrected value was 1.
Cleared by writing a 1 to FAIL_1_H_CLR bit of ERR_STATUS_CLR
register.
Note: This bit is updated on every flash access which results in a
single bit error, So, in case of multiple single bit error, the status
would correspond to the last error which occured.
Reset type: SYSRSn
16 FAIL_0_H R 0h Fail on 0.
0 Fail on 0 single bit error did not occur in upper 64bits of a 128-bit
aligned address.
1 A value of 1 would indicate that a single bit error occurred in upper
64bits of a 128-bit aligned address and the corrected value was 0.
Cleared by writing a 1 to FAIL_0_H_CLR bit of ERR_STATUS_CLR
register.
Note: This bit is updated on every flash access which results in a
single bit error, So, in case of multiple single bit error, the status
would correspond to the last error which occurred.
Reset type: SYSRSn
15-3 RESERVED R 0h Reserved

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Table 3-328. ERR_STATUS Register Field Descriptions (continued)

Bit Field Type Reset Description
2 UNC_ERR_L R 0h Uncorrectable error. A value of 1 indicates that an un-correctable
error occurred in lower 64bits of a 128-bit aligned address. Cleared
by writing a 1 to UNC_ERR_L_CLR bit of ERR_STATUS_CLR
register.
Reset type: SYSRSn
1 FAIL_1_L R 0h Fail on 1.
0 Fail on 1 single bit error did not occur in lower 64bits of a 128-bit
aligned address.
1 A value of 1 would indicate that a single bit error occurred in lower
64bits of a 128-bit aligned address and the corrected value was 1.
Cleared by writing a 1 to FAIL_1_L_CLR bit of ERR_STATUS_CLR
register.
Note: This bit is updated on every flash access which results in a
single bit error, So, in case of multiple single bit error, the status
would correspond to the last error which occured.
Reset type: SYSRSn
0 FAIL_0_L R 0h Fail on 0.
0 Fail on 0 single bit error did not occur in lower 64bits of a 128-bit
aligned address.
1 Would indicate that a single bit error occurred in lower 64bits of a
128-bit aligned address and the corrected value was 0. Cleared by
writing a 1 to FAIL_0_L_CLR bit of ERR_STATUS_CLR register.
Note: This bit is updated on every flash access which results in a
single bit error, So, in case of multiple single bit error, the status
would correspond to the last error which occured.
Reset type: SYSRSn

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3.17.22.7 ERR_POS Register (Offset = Ch) [Reset = 00000000h]

ERR_POS is shown in Figure 3-292 and described in Table 3-329.
Return to the Summary Table.
Error Position
Figure 3-292. ERR_POS Register
31 30 29 28 27 26 25 24
RESERVED ERR_TYPE_H
R-0h R-0h

23 22 21 20 19 18 17 16
RESERVED ERR_POS_H
R-0h R-0h

15 14 13 12 11 10 9 8
RESERVED ERR_TYPE_L
R-0h R-0h

7 6 5 4 3 2 1 0
RESERVED ERR_POS_L
R-0h R-0h

Table 3-329. ERR_POS Register Field Descriptions

Bit Field Type Reset Description
31-25 RESERVED R 0h Reserved
24 ERR_TYPE_H R 0h Error type
0 Indicates that a single bit error occured in upper 64 data bits of a
128-bit aligned address.
1 Indicates that a single bit error occured in ECC check bits of upper
64bits of a 128-bit aligned address.
Reset type: SYSRSn
23-22 RESERVED R 0h Reserved
21-16 ERR_POS_H R 0h Error position. Bit position of the single bit error in upper 64bits of
a 128-bit aligned address. The position is interpreted depending on
whether the ERR_TYPE bit indicates a check bit or a data bit. If
ERR_TYPE indicates a check bit error, the error position could range
from 0 to 7, else it could range from 0 to 63.
Reset type: SYSRSn
15-9 RESERVED R 0h Reserved
8 ERR_TYPE_L R 0h Error type
0 Indicates that a single bit error occured in lower 64 data bits of a
128-bit aligned address.
1 Indicates that a single bit error occured in ECC check bits of lower
64bits of a 128-bit aligned address.
Reset type: SYSRSn
7-6 RESERVED R 0h Reserved
5-0 ERR_POS_L R 0h Error position. Bit position of the single bit error in lower 64bits of
a 128-bit aligned address. The position is interpreted depending on
whether the ERR_TYPE bit indicates a check bit or a data bit. If
ERR_TYPE indicates a check bit error, the error position could range
from 0 to 7, else it could range from 0 to 63.
Reset type: SYSRSn

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3.17.22.8 ERR_STATUS_CLR Register (Offset = Eh) [Reset = 00000000h]

ERR_STATUS_CLR is shown in Figure 3-293 and described in Table 3-330.
Return to the Summary Table.
Error Status Clear
Figure 3-293. ERR_STATUS_CLR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED UNC_ERR_H_ FAIL_1_H_CLR FAIL_0_H_CLR
CLR
R-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED UNC_ERR_L_C FAIL_1_L_CLR FAIL_0_L_CLR
LR
R-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-330. ERR_STATUS_CLR Register Field Descriptions

Bit Field Type Reset Description
31-19 RESERVED R 0h Reserved
18 UNC_ERR_H_CLR R-0/W1S 0h Uncorrectable error clear. Writing a 1 to this bit will clear the
UNC_ERR_H bit of ERR_STATUS
register. Writes of 0 have no effect. Read returns 0.
Reset type: SYSRSn
17 FAIL_1_H_CLR R-0/W1S 0h Fail on 1 clear. Writing a 1 to this bit will clear the FAIL_1_H bit of
ERR_STATUS register. Writes of 0
have no effect. Read returns 0.
Reset type: SYSRSn
16 FAIL_0_H_CLR R-0/W1S 0h Fail on 0 clear. Writing a 1 to this bit will clear the FAIL_0_H bit of
ERR_STATUS register. Writes of 0
have no effect. Read returns 0.
Reset type: SYSRSn
15-3 RESERVED R 0h Reserved
2 UNC_ERR_L_CLR R-0/W1S 0h Uncorrectable error clear. Writing a 1 to this bit will clear the
UNC_ERR_L bit of ERR_STATUS
register. Writes of 0 have no effect. Read returns 0.
Reset type: SYSRSn
1 FAIL_1_L_CLR R-0/W1S 0h Fail on 1 clear. Writing a 1 to this bit will clear the FAIL_1_L bit of
ERR_STATUS register. Writes of 0
have no effect. Read returns 0.
Reset type: SYSRSn
0 FAIL_0_L_CLR R-0/W1S 0h Fail on 0 clear. Writing a 1 to this bit will clear the FAIL_0_L bit of
ERR_STATUS register. Writes of 0
have no effect. Read returns 0.
Reset type: SYSRSn

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3.17.22.9 ERR_CNT Register (Offset = 10h) [Reset = 00000000h]

ERR_CNT is shown in Figure 3-294 and described in Table 3-331.
Return to the Summary Table.
Error Control
Figure 3-294. ERR_CNT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED ERR_CNT
R-0h R/W-0h

Table 3-331. ERR_CNT Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-0 ERR_CNT R/W 0h Single bit error count. This counter increments with every single bit
ECC error occurrence. Upon reaching the threshold value counter
stops counting on single bit errors. ERR_CNT can be cleared
(irrespective of whether threshold is met or not) using 'Single Err
Int Clear' bit. This is applicable for ECC logic test mode and normal
operational mode.
Reset type: SYSRSn

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3.17.22.10 ERR_THRESHOLD Register (Offset = 12h) [Reset = 00000000h]

ERR_THRESHOLD is shown in Figure 3-295 and described in Table 3-332.
Return to the Summary Table.
Error Threshold
Figure 3-295. ERR_THRESHOLD Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED ERR_THRESHOLD
R-0h R/W-0h

Table 3-332. ERR_THRESHOLD Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-0 ERR_THRESHOLD R/W 0h Single bit error threshold. Sets the threshold for single bit errors.
When the ERR_CNT value equals the THRESHOLD value and
a single bit error occurs, SINGLE_ERR_INT flag is set, and an
interrupt is fired.
Reset type: SYSRSn

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3.17.22.11 ERR_INTFLG Register (Offset = 14h) [Reset = 00000000h]

ERR_INTFLG is shown in Figure 3-296 and described in Table 3-333.
Return to the Summary Table.
Error Interrupt Flag
Figure 3-296. ERR_INTFLG Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED UNC_ERR_INT SINGLE_ERR_I
FLG NTFLG
R-0h R-0h R-0h

Table 3-333. ERR_INTFLG Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-2 RESERVED R 0h Reserved
1 UNC_ERR_INTFLG R 0h Uncorrectable bit error interrupt flag. When a Un-correctable error
occurs, this bit is set and the UNC_ERR_INT interrupt is fired. When
UNC_ERR_INTCLR bit of ERR_INTCLR register is written a value of
1 this bit is cleared.
Reset type: SYSRSn
0 SINGLE_ERR_INTFLG R 0h Single bit error interrupt flag. When the ERR_CNT value equals
the ERR_THRESHOLD value and a single bit error occurs then
SINGLE_ERR_INT flag is set and SINGLE_ERR_INT interrupt is
fired. When SINGLE_ERR_INTCLR bit of ERR_INTCLR register is
written a value of 1 this bit is cleared.
Reset type: SYSRSn

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3.17.22.12 ERR_INTCLR Register (Offset = 16h) [Reset = 00000000h]

ERR_INTCLR is shown in Figure 3-297 and described in Table 3-334.
Return to the Summary Table.
Error Interrupt Flag Clear
Figure 3-297. ERR_INTCLR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED UNC_ERR_INT SINGLE_ERR_I
CLR NTCLR
R-0h R-0/W1S-0h R-0/W1S-0h

Table 3-334. ERR_INTCLR Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-2 RESERVED R 0h Reserved
1 UNC_ERR_INTCLR R-0/W1S 0h Uncorrectable bit error interrupt flag clear. Writing a 1 to this bit will
clear UNC_ERR_INT_FLG. Writes of 0 have no effect.
Reset type: SYSRSn
0 SINGLE_ERR_INTCLR R-0/W1S 0h Single bit error interrupt flag clear. Writing a 1 to this bit will clear
SINGLE_ERR_INT_FLG. Writes of 0 have no effect.
Reset type: SYSRSn

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3.17.22.13 FDATAH_TEST Register (Offset = 18h) [Reset = 00000000h]

FDATAH_TEST is shown in Figure 3-298 and described in Table 3-335.
Return to the Summary Table.
Data High Test
Figure 3-298. FDATAH_TEST Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FDATAH
R/W-0h

Table 3-335. FDATAH_TEST Register Field Descriptions

Bit Field Type Reset Description
31-0 FDATAH R/W 0h High double word of selected 64-bit data. User-configurable bits
63:32 of the selected data block in ECC test mode.
Reset type: SYSRSn

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3.17.22.14 FDATAL_TEST Register (Offset = 1Ah) [Reset = 00000000h]

FDATAL_TEST is shown in Figure 3-299 and described in Table 3-336.
Return to the Summary Table.
Data Low Test
Figure 3-299. FDATAL_TEST Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FDATAL
R/W-0h

Table 3-336. FDATAL_TEST Register Field Descriptions

Bit Field Type Reset Description
31-0 FDATAL R/W 0h Low double word of selected 64-bit data. User-configurable bits 31:0
of the selected data block in ECC test mode.
Reset type: SYSRSn

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3.17.22.15 FADDR_TEST Register (Offset = 1Ch) [Reset = 00000000h]

FADDR_TEST is shown in Figure 3-300 and described in Table 3-337.
Return to the Summary Table.
ECC Test Address
Figure 3-300. FADDR_TEST Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED ADDRH
R-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDRL RESERVED
R/W-0h R-0h

Table 3-337. FADDR_TEST Register Field Descriptions

Bit Field Type Reset Description
31-22 RESERVED R 0h Reserved
21-16 ADDRH R/W 0h Address for selected 64-bit data. User-configurable address bits of
the selected data in ECC test mode. Left-shift the address by one bit
(to provide byte address) and ignore the three least significant bits of
the address and write the bits 21:16 in remaining address bits in this
field.
Reset type: SYSRSn
15-3 ADDRL R/W 0h Address for selected 64-bit data. User-configurable address bits of
the selected data in ECC test mode. Left-shift the address by one bit
(to provide byte address) and ignore the three least significant bits of
the address and write the bits 15:3 in remaining address bits in this
field.
Reset type: SYSRSn
2-0 RESERVED R 0h Reserved

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3.17.22.16 FECC_TEST Register (Offset = 1Eh) [Reset = 00000000h]

FECC_TEST is shown in Figure 3-301 and described in Table 3-338.
Return to the Summary Table.
ECC Test Address
Figure 3-301. FECC_TEST Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RESERVED ECC
R-0h R-0h R/W-0h

Table 3-338. FECC_TEST Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-8 RESERVED R 0h Reserved
7-0 ECC R/W 0h 8-bit ECC for selected 64-bit data. User-configurable ECC bits of the
selected 64-bit data block in ECC test mode.
Reset type: SYSRSn

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3.17.22.17 FECC_CTRL Register (Offset = 20h) [Reset = 00000000h]

FECC_CTRL is shown in Figure 3-302 and described in Table 3-339.
Return to the Summary Table.
ECC Control
Figure 3-302. FECC_CTRL Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED DO_ECC_CAL ECC_SELECT ECC_TEST_EN
C
R-0h R-0/W1S-0h R/W-0h R/W-0h

Table 3-339. FECC_CTRL Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-3 RESERVED R 0h Reserved
2 DO_ECC_CALC R-0/W1S 0h Enable ECC calculation. ECC logic will calculate ECC in one cycle
for the data and address written in ECC test registers when ECC test
logic is enabled by setting ECC_TEST_EN.
Reset type: SYSRSn
1 ECC_SELECT R/W 0h ECC block select.
0 Selects the ECC block on bits [63:0] of bank data.
1 Selects the ECC block on bits [127:64] of bank data.
Reset type: SYSRSn
0 ECC_TEST_EN R/W 0h ECC test mode enable.
0 ECC test mode disabled
1 ECC test mode enabled
Reset type: SYSRSn

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3.17.22.18 FOUTH_TEST Register (Offset = 22h) [Reset = 00000000h]

FOUTH_TEST is shown in Figure 3-303 and described in Table 3-340.
Return to the Summary Table.
Test Data Out High
Figure 3-303. FOUTH_TEST Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAOUTH
R-0h

Table 3-340. FOUTH_TEST Register Field Descriptions

Bit Field Type Reset Description
31-0 DATAOUTH R 0h High double word test data out. Holds bits 63:32 of the data out of
the selected ECC block.
Reset type: SYSRSn

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3.17.22.19 FOUTL_TEST Register (Offset = 24h) [Reset = 00000000h]

FOUTL_TEST is shown in Figure 3-304 and described in Table 3-341.
Return to the Summary Table.
Test Data Out Low
Figure 3-304. FOUTL_TEST Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAOUTL
R-0h

Table 3-341. FOUTL_TEST Register Field Descriptions

Bit Field Type Reset Description
31-0 DATAOUTL R 0h Low double word test data out. Holds bits 31:0 of the data out of the
selected ECC block.
Reset type: SYSRSn

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3.17.22.20 FECC_STATUS Register (Offset = 26h) [Reset = 00000000h]

FECC_STATUS is shown in Figure 3-305 and described in Table 3-342.
Return to the Summary Table.
ECC Status
Figure 3-305. FECC_STATUS Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED ERR_TYPE
R-0h R-0h

7 6 5 4 3 2 1 0
DATA_ERR_POS UNC_ERR SINGLE_ERR
R-0h R-0h R-0h

Table 3-342. FECC_STATUS Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-9 RESERVED R 0h Reserved
8 ERR_TYPE R 0h Test mode ECC single bit error indicator. When 1, indicates that the
single bit error is in check bits. When 0, indicates that the single bit
error is in data bits (If SINGLE_ERR field is also set).
Reset type: SYSRSn
7-2 DATA_ERR_POS R 0h Test mode single bit error position. Holds the bit position where the
single bit error occurred.
The position is interpreted depending on whether the CHK_ERR bit
indicates a check bit or a data bit. If CHK_ERR indicates a check
bit error, the error position could range from 0 to 7, or it could range
from 0 to 63.
Reset type: SYSRSn
1 UNC_ERR R 0h Test mode ECC double bit error. When 1 indicates that the ECC test
resulted in an uncorrectable bit error.
Reset type: SYSRSn
0 SINGLE_ERR R 0h Test mode ECC single bit error. When 1 indicates that the ECC test
resulted in a single bit error.
Reset type: SYSRSn

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3.17.23 CPU_ID_REGS Registers

Table 3-343 lists the memory-mapped registers for the CPU_ID_REGS registers. All register offset addresses
not listed in Table 3-343 should be considered as reserved locations and the register contents should not be
modified.
Table 3-343. CPU_ID_REGS Registers
Offset Acronym Register Name Write Protection Section
0h CPUID Indicates CPU1 or CPU2 Go

Complex bit access types are encoded to fit into small table cells. Table 3-344 shows the codes that are used for
access types in this section.
Table 3-344. CPU_ID_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
Reset or Default Value
-n Value after reset or the default
value

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3.17.23.1 CPUID Register (Offset = 0h) [Reset = 0000h]

CPUID is shown in Figure 3-306 and described in Table 3-345.
Return to the Summary Table.
This register can be used to identify on which CPU the code is executing.
Figure 3-306. CPUID Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
CPUID
R-0h

Table 3-345. CPUID Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R 0h Reserved
7-0 CPUID R 0h CPUID = 1 for CPU1, 2 for CPU2
Reset type: N/A

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3.17.24 UID_REGS Registers

Table 3-346 lists the memory-mapped registers for the UID_REGS registers. All register offset addresses not
listed in Table 3-346 should be considered as reserved locations and the register contents should not be
modified.
Table 3-346. UID_REGS Registers
Offset Acronym Register Name Write Protection Section
0h UID_PSRAND0 UID Psuedo-random 192 bit number Go
2h UID_PSRAND1 UID Psuedo-random 192 bit number Go
4h UID_PSRAND2 UID Psuedo-random 192 bit number Go
6h UID_PSRAND3 UID Psuedo-random 192 bit number Go
8h UID_PSRAND4 UID Psuedo-random 192 bit number Go
Ah UID_PSRAND5 UID Psuedo-random 192 bit number Go
Ch UID_UNIQUE UID Unique 32 bit number Go
Eh UID_CHECKSUM UID Checksum Go

Complex bit access types are encoded to fit into small table cells. Table 3-347 shows the codes that are used for
access types in this section.
Table 3-347. UID_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
Reset or Default Value
-n Value after reset or the default
value

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3.17.24.1 UID_PSRAND0 Register (Offset = 0h) [Reset = 00000000h]

UID_PSRAND0 is shown in Figure 3-307 and described in Table 3-348.
Return to the Summary Table.
UID Psuedo-random 192 bit number
Figure 3-307. UID_PSRAND0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RandomID
R-0h

Table 3-348. UID_PSRAND0 Register Field Descriptions

Bit Field Type Reset Description
31-0 RandomID R 0h Psuedorandom portion of the UID
Reset type: N/A

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3.17.24.2 UID_PSRAND1 Register (Offset = 2h) [Reset = 00000000h]

UID_PSRAND1 is shown in Figure 3-308 and described in Table 3-349.
Return to the Summary Table.
UID Psuedo-random 192 bit number
Figure 3-308. UID_PSRAND1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RandomID
R-0h

Table 3-349. UID_PSRAND1 Register Field Descriptions

Bit Field Type Reset Description
31-0 RandomID R 0h Psuedorandom portion of the UID
Reset type: N/A

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3.17.24.3 UID_PSRAND2 Register (Offset = 4h) [Reset = 00000000h]

UID_PSRAND2 is shown in Figure 3-309 and described in Table 3-350.
Return to the Summary Table.
UID Psuedo-random 192 bit number
Figure 3-309. UID_PSRAND2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RandomID
R-0h

Table 3-350. UID_PSRAND2 Register Field Descriptions

Bit Field Type Reset Description
31-0 RandomID R 0h Psuedorandom portion of the UID
Reset type: N/A

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3.17.24.4 UID_PSRAND3 Register (Offset = 6h) [Reset = 00000000h]

UID_PSRAND3 is shown in Figure 3-310 and described in Table 3-351.
Return to the Summary Table.
UID Psuedo-random 192 bit number
Figure 3-310. UID_PSRAND3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RandomID
R-0h

Table 3-351. UID_PSRAND3 Register Field Descriptions

Bit Field Type Reset Description
31-0 RandomID R 0h Psuedorandom portion of the UID
Reset type: N/A

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3.17.24.5 UID_PSRAND4 Register (Offset = 8h) [Reset = 00000000h]

UID_PSRAND4 is shown in Figure 3-311 and described in Table 3-352.
Return to the Summary Table.
UID Psuedo-random 192 bit number
Figure 3-311. UID_PSRAND4 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RandomID
R-0h

Table 3-352. UID_PSRAND4 Register Field Descriptions

Bit Field Type Reset Description
31-0 RandomID R 0h Psuedorandom portion of the UID
Reset type: N/A

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3.17.24.6 UID_PSRAND5 Register (Offset = Ah) [Reset = 00000000h]

UID_PSRAND5 is shown in Figure 3-312 and described in Table 3-353.
Return to the Summary Table.
UID Psuedo-random 192 bit number
Figure 3-312. UID_PSRAND5 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RandomID
R-0h

Table 3-353. UID_PSRAND5 Register Field Descriptions

Bit Field Type Reset Description
31-0 RandomID R 0h Psuedorandom portion of the UID
Reset type: N/A

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3.17.24.7 UID_UNIQUE Register (Offset = Ch) [Reset = 00000000h]

UID_UNIQUE is shown in Figure 3-313 and described in Table 3-354.
Return to the Summary Table.
UID Unique 32 bit number
Figure 3-313. UID_UNIQUE Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UniqueID
R-0h

Table 3-354. UID_UNIQUE Register Field Descriptions

Bit Field Type Reset Description
31-0 UniqueID R 0h Unique portion of the UID. This identifier will be unique across all
devices with the same PARTIDH.
Reset type: N/A

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3.17.24.8 UID_CHECKSUM Register (Offset = Eh) [Reset = 00000000h]

UID_CHECKSUM is shown in Figure 3-314 and described in Table 3-355.
Return to the Summary Table.
Fletcher checksum of UID_PSRAND and UID_UNIQUE registers
Figure 3-314. UID_CHECKSUM Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Checksum
R-0h

Table 3-355. UID_CHECKSUM Register Field Descriptions

Bit Field Type Reset Description
31-0 Checksum R 0h Fletcher checksum of UID_PSRANDx and UID_UINIQUE
Reset type: N/A

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3.17.25 DCSM_Z1_OTP Registers

Table 3-356 lists the memory-mapped registers for the DCSM_Z1_OTP registers. All register offset addresses
not listed in Table 3-356 should be considered as reserved locations and the register contents should not be
modified.
Table 3-356. DCSM_Z1_OTP Registers
Offset Acronym Register Name Write Protection Section
0h Z1OTP_LINKPOINTER1 Zone 1 Link Pointer1 in Z1 OTP Go
4h Z1OTP_LINKPOINTER2 Zone 1 Link Pointer2 in Z1 OTP Go
8h Z1OTP_LINKPOINTER3 Zone 1 Link Pointer3 in Z1 OTP Go
10h Z1OTP_PSWDLOCK Secure Password Lock in Z1 OTP Go
14h Z1OTP_CRCLOCK Secure CRC Lock in Z1 OTP Go
18h Z1OTP_JTAGLOCK Secure JTAG Lock in Z1 OTP Go
1Eh Z1OTP_BOOTCTRL Boot Mode in Z1 OTP Go

Complex bit access types are encoded to fit into small table cells. Table 3-357 shows the codes that are used for
access types in this section.
Table 3-357. DCSM_Z1_OTP Access Type Codes
Access Type Code Description
Read Type
R R Read
Reset or Default Value
-n Value after reset or the default value
Register Array Variables
i,j,k,l,m,n When these variables are used in a register name,
an offset, or an address, they refer to the value of a
register array where the register is part of a group
of repeating registers. The register groups form a
hierarchical structure and the array is represented
with a formula.
y When this variable is used in a register name, an
offset, or an address it refers to the value of a
register array.

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3.17.25.1 Z1OTP_LINKPOINTER1 Register (Offset = 0h) [Reset = FFFFFFFFh]

Z1OTP_LINKPOINTER1 is shown in Figure 3-315 and described in Table 3-358.
Return to the Summary Table.
Zone 1 Link Pointer1 in Z1 OTP
Figure 3-315. Z1OTP_LINKPOINTER1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1OTP_LINKPOINTER1
R-FFFFFFFFh

Table 3-358. Z1OTP_LINKPOINTER1 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1OTP_LINKPOINTER1 R FFFFFFFFh Zone1 Link Pointer 1 location in USER OTP.
Reset type: SYSRSn

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3.17.25.2 Z1OTP_LINKPOINTER2 Register (Offset = 4h) [Reset = FFFFFFFFh]

Z1OTP_LINKPOINTER2 is shown in Figure 3-316 and described in Table 3-359.
Return to the Summary Table.
Zone 1 Link Pointer2 in Z1 OTP
Figure 3-316. Z1OTP_LINKPOINTER2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1OTP_LINKPOINTER2
R-FFFFFFFFh

Table 3-359. Z1OTP_LINKPOINTER2 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1OTP_LINKPOINTER2 R FFFFFFFFh Zone1 Link Pointer 2 location in USER OTP.
Reset type: SYSRSn

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3.17.25.3 Z1OTP_LINKPOINTER3 Register (Offset = 8h) [Reset = FFFFFFFFh]

Z1OTP_LINKPOINTER3 is shown in Figure 3-317 and described in Table 3-360.
Return to the Summary Table.
Zone 1 Link Pointer3 in Z1 OTP
Figure 3-317. Z1OTP_LINKPOINTER3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1OTP_LINKPOINTER3
R-FFFFFFFFh

Table 3-360. Z1OTP_LINKPOINTER3 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1OTP_LINKPOINTER3 R FFFFFFFFh Zone1 Link Pointer 3 location in USER OTP.
Reset type: SYSRSn

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3.17.25.4 Z1OTP_PSWDLOCK Register (Offset = 10h) [Reset = FFFFFFFFh]

Z1OTP_PSWDLOCK is shown in Figure 3-318 and described in Table 3-361.
Return to the Summary Table.
Secure Password Lock in Z1 OTP
Figure 3-318. Z1OTP_PSWDLOCK Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1OTP_PSWDLOCK
R-FFFFFFFFh

Table 3-361. Z1OTP_PSWDLOCK Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1OTP_PSWDLOCK R FFFFFFFFh Zone1 password lock location in USER OTP.
Reset type: SYSRSn

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3.17.25.5 Z1OTP_CRCLOCK Register (Offset = 14h) [Reset = FFFFFFFFh]

Z1OTP_CRCLOCK is shown in Figure 3-319 and described in Table 3-362.
Return to the Summary Table.
Secure CRC Lock in Z1 OTP
Figure 3-319. Z1OTP_CRCLOCK Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1OTP_CRCLOCK
R-FFFFFFFFh

Table 3-362. Z1OTP_CRCLOCK Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1OTP_CRCLOCK R FFFFFFFFh Zone1 CRC lock location in USER OTP.
Reset type: SYSRSn

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3.17.25.6 Z1OTP_JTAGLOCK Register (Offset = 18h) [Reset = FFFFFFFFh]

Z1OTP_JTAGLOCK is shown in Figure 3-320 and described in Table 3-363.
Return to the Summary Table.
Secure JTAG Lock in Z1 OTP
Figure 3-320. Z1OTP_JTAGLOCK Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1OTP_JTAGLOCK
R-FFFFFFFFh

Table 3-363. Z1OTP_JTAGLOCK Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1OTP_JTAGLOCK R FFFFFFFFh Zone1 JTAG lock location in USER OTP.
Reset type: SYSRSn

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3.17.25.7 Z1OTP_BOOTCTRL Register (Offset = 1Eh) [Reset = FFFFFFFFh]

Z1OTP_BOOTCTRL is shown in Figure 3-321 and described in Table 3-364.
Return to the Summary Table.
Boot Mode in Z1 OTP
Figure 3-321. Z1OTP_BOOTCTRL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1OTP_BOOTCTRL
R-FFFFFFFFh

Table 3-364. Z1OTP_BOOTCTRL Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1OTP_BOOTCTRL R FFFFFFFFh Zone1 Boot control location in USER OTP.
Reset type: SYSRSn

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3.17.26 DCSM_Z2_OTP Registers

Table 3-365 lists the memory-mapped registers for the DCSM_Z2_OTP registers. All register offset addresses
not listed in Table 3-365 should be considered as reserved locations and the register contents should not be
modified.
Table 3-365. DCSM_Z2_OTP Registers
Offset Acronym Register Name Write Protection Section
0h Z2OTP_LINKPOINTER1 Zone 2 Link Pointer1 in Z2 OTP Go
4h Z2OTP_LINKPOINTER2 Zone 2 Link Pointer2 in Z2 OTP Go
8h Z2OTP_LINKPOINTER3 Zone 2 Link Pointer3 in Z2 OTP Go
10h Z2OTP_PSWDLOCK Secure Password Lock in Z2 OTP Go
14h Z2OTP_CRCLOCK Secure CRC Lock in Z2 OTP Go
18h Z2OTP_JTAGLOCK Secure JTAG Lock in Z2 OTP Go
1Eh Z2OTP_BOOTCTRL Boot Mode in Z2 OTP Go

Complex bit access types are encoded to fit into small table cells. Table 3-366 shows the codes that are used for
access types in this section.
Table 3-366. DCSM_Z2_OTP Access Type Codes
Access Type Code Description
Read Type
R R Read
Reset or Default Value
-n Value after reset or the default value
Register Array Variables
i,j,k,l,m,n When these variables are used in a register name,
an offset, or an address, they refer to the value of a
register array where the register is part of a group
of repeating registers. The register groups form a
hierarchical structure and the array is represented
with a formula.
y When this variable is used in a register name, an
offset, or an address it refers to the value of a
register array.

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3.17.26.1 Z2OTP_LINKPOINTER1 Register (Offset = 0h) [Reset = FFFFFFFFh]

Z2OTP_LINKPOINTER1 is shown in Figure 3-322 and described in Table 3-367.
Return to the Summary Table.
Zone 2 Link Pointer1 in Z2 OTP
Figure 3-322. Z2OTP_LINKPOINTER1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2OTP_LINKPOINTER1
R-FFFFFFFFh

Table 3-367. Z2OTP_LINKPOINTER1 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2OTP_LINKPOINTER1 R FFFFFFFFh Zone2 Link Pointer 1 location in USER OTP.
Reset type: SYSRSn

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3.17.26.2 Z2OTP_LINKPOINTER2 Register (Offset = 4h) [Reset = FFFFFFFFh]

Z2OTP_LINKPOINTER2 is shown in Figure 3-323 and described in Table 3-368.
Return to the Summary Table.
Zone 2 Link Pointer2 in Z2 OTP
Figure 3-323. Z2OTP_LINKPOINTER2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2OTP_LINKPOINTER2
R-FFFFFFFFh

Table 3-368. Z2OTP_LINKPOINTER2 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2OTP_LINKPOINTER2 R FFFFFFFFh Zone2 Link Pointer 2 location in USER OTP.
Reset type: SYSRSn

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3.17.26.3 Z2OTP_LINKPOINTER3 Register (Offset = 8h) [Reset = FFFFFFFFh]

Z2OTP_LINKPOINTER3 is shown in Figure 3-324 and described in Table 3-369.
Return to the Summary Table.
Zone 2 Link Pointer3 in Z2 OTP
Figure 3-324. Z2OTP_LINKPOINTER3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2OTP_LINKPOINTER3
R-FFFFFFFFh

Table 3-369. Z2OTP_LINKPOINTER3 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2OTP_LINKPOINTER3 R FFFFFFFFh Zone2 Link Pointer 3 location in USER OTP.
Reset type: SYSRSn

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3.17.26.4 Z2OTP_PSWDLOCK Register (Offset = 10h) [Reset = FFFFFFFFh]

Z2OTP_PSWDLOCK is shown in Figure 3-325 and described in Table 3-370.
Return to the Summary Table.
Secure Password Lock in Z2 OTP
Figure 3-325. Z2OTP_PSWDLOCK Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2OTP_PSWDLOCK
R-FFFFFFFFh

Table 3-370. Z2OTP_PSWDLOCK Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2OTP_PSWDLOCK R FFFFFFFFh Zone2 password lock location in USER OTP.
Reset type: SYSRSn

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3.17.26.5 Z2OTP_CRCLOCK Register (Offset = 14h) [Reset = FFFFFFFFh]

Z2OTP_CRCLOCK is shown in Figure 3-326 and described in Table 3-371.
Return to the Summary Table.
Secure CRC Lock in Z2 OTP
Figure 3-326. Z2OTP_CRCLOCK Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2OTP_CRCLOCK
R-FFFFFFFFh

Table 3-371. Z2OTP_CRCLOCK Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2OTP_CRCLOCK R FFFFFFFFh Zone2 CRC lock location in USER OTP.
Reset type: SYSRSn

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3.17.26.6 Z2OTP_JTAGLOCK Register (Offset = 18h) [Reset = FFFFFFFFh]

Z2OTP_JTAGLOCK is shown in Figure 3-327 and described in Table 3-372.
Return to the Summary Table.
Secure JTAG Lock in Z2 OTP
Figure 3-327. Z2OTP_JTAGLOCK Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2OTP_JTAGLOCK
R-FFFFFFFFh

Table 3-372. Z2OTP_JTAGLOCK Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2OTP_JTAGLOCK R FFFFFFFFh Zone2 JTAG lock location in USER OTP.
Reset type: SYSRSn

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3.17.26.7 Z2OTP_BOOTCTRL Register (Offset = 1Eh) [Reset = FFFFFFFFh]

Z2OTP_BOOTCTRL is shown in Figure 3-328 and described in Table 3-373.
Return to the Summary Table.
Boot Mode in Z2 OTP
Figure 3-328. Z2OTP_BOOTCTRL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2OTP_BOOTCTRL
R-FFFFFFFFh

Table 3-373. Z2OTP_BOOTCTRL Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2OTP_BOOTCTRL R FFFFFFFFh Zone2 Boot control location in USER OTP.
Reset type: SYSRSn

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3.17.27 Register to Driverlib Function Mapping

3.17.27.1 CPUTIMER Registers to Driverlib Functions

Table 3-374. CPUTIMER Registers to Driverlib Functions
File Driverlib Function
TIM
cputimer.h CPUTimer_getTimerCount
sysctl.c SysCtl_setClock
PRD
cputimer.h CPUTimer_setPeriod
sysctl.c SysCtl_setClock
sysctl.c SysCtl_setAuxClock
sysctl.c SysCtl_selectXTAL
TCR
cputimer.c CPUTimer_setEmulationMode
cputimer.h CPUTimer_clearOverflowFlag
cputimer.h CPUTimer_disableInterrupt
cputimer.h CPUTimer_enableInterrupt
cputimer.h CPUTimer_reloadTimerCounter
cputimer.h CPUTimer_stopTimer
cputimer.h CPUTimer_resumeTimer
cputimer.h CPUTimer_startTimer
cputimer.h CPUTimer_getTimerOverflowStatus
sysctl.c SysCtl_setClock
sysctl.c SysCtl_setAuxClock
sysctl.c SysCtl_selectXTAL
TPR
cputimer.h CPUTimer_setPreScaler
sysctl.c SysCtl_setClock
sysctl.c SysCtl_setAuxClock
sysctl.c SysCtl_selectXTAL
TPRH
cputimer.h CPUTimer_setPreScaler
sysctl.c SysCtl_setClock
sysctl.c SysCtl_setAuxClock
sysctl.c SysCtl_selectXTAL

3.17.27.2 ASYSCTL Registers to Driverlib Functions

Table 3-375. ASYSCTL Registers to Driverlib Functions
File Driverlib Function
INTOSC1TRIM
-
INTOSC2TRIM
-
TSNSCTL
asysctl.h ASysCtl_enableTemperatureSensor
asysctl.h ASysCtl_disableTemperatureSensor

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Table 3-375. ASYSCTL Registers to Driverlib Functions (continued)

File Driverlib Function
LOCK
asysctl.h ASysCtl_lockTemperatureSensor
ANAREFTRIMA
-
ANAREFTRIMB
-
ANAREFTRIMC
-
ANAREFTRIMD
-

3.17.27.3 PIE Registers to Driverlib Functions

Table 3-376. PIE Registers to Driverlib Functions
File Driverlib Function
CTRL
interrupt.c Interrupt_initModule
interrupt.c Interrupt_defaultHandler
interrupt.h Interrupt_enablePIE
interrupt.h Interrupt_disablePIE
ACK
interrupt.c Interrupt_disable
interrupt.h Interrupt_clearACKGroup
IER1
interrupt.c Interrupt_initModule
interrupt.c Interrupt_enable
interrupt.c Interrupt_disable
IFR1
interrupt.c Interrupt_initModule
IER2
interrupt.c Interrupt_initModule
IFR2
interrupt.c Interrupt_initModule
IER3
interrupt.c Interrupt_initModule
IFR3
interrupt.c Interrupt_initModule
IER4
interrupt.c Interrupt_initModule
IFR4
interrupt.c Interrupt_initModule
IER5
interrupt.c Interrupt_initModule
IFR5
interrupt.c Interrupt_initModule
IER6

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Table 3-376. PIE Registers to Driverlib Functions (continued)

File Driverlib Function
interrupt.c Interrupt_initModule
IFR6
interrupt.c Interrupt_initModule
IER7
interrupt.c Interrupt_initModule
IFR7
interrupt.c Interrupt_initModule
IER8
interrupt.c Interrupt_initModule
IFR8
interrupt.c Interrupt_initModule
IER9
interrupt.c Interrupt_initModule
IFR9
interrupt.c Interrupt_initModule
IER10
interrupt.c Interrupt_initModule
IFR10
interrupt.c Interrupt_initModule
IER11
interrupt.c Interrupt_initModule
IFR11
interrupt.c Interrupt_initModule
IER12
interrupt.c Interrupt_initModule
IFR12
interrupt.c Interrupt_initModule

3.17.27.4 SYSCTL Registers to Driverlib Functions

Table 3-377. SYSCTL Registers to Driverlib Functions
File Driverlib Function
DEVCFGLOCK1
sysctl.h SysCtl_lockCPUSelectRegs
PARTIDL
sysctl.c SysCtl_getDeviceParametric
PARTIDH
sysctl.c SysCtl_getDeviceParametric
REVID
adc.h ADC_getTemperatureC
adc.h ADC_getTemperatureK
sysctl.h SysCtl_getDeviceRevision
DC0
-
DC1
-

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Table 3-377. SYSCTL Registers to Driverlib Functions (continued)

File Driverlib Function
DC2
-
DC3
-
DC4
-
DC5
-
DC6
-
DC7
-
DC8
-
DC9
-
DC10
-
DC11
-
DC12
-
DC13
-
DC14
-
DC15
-
DC17
-
DC18
-
DC19
-
DC20
-
PERCNF1
sysctl.h SysCtl_isPresentUSBPHY
FUSEERR
sysctl.h SysCtl_getEfuseError
SOFTPRES0
sysctl.h SysCtl_resetPeripheral
SOFTPRES1
- See SOFTPRES0
SOFTPRES2

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Table 3-377. SYSCTL Registers to Driverlib Functions (continued)

File Driverlib Function
- See SOFTPRES0
SOFTPRES3
- See SOFTPRES0
SOFTPRES4
- See SOFTPRES0
SOFTPRES6
- See SOFTPRES0
SOFTPRES7
- See SOFTPRES0
SOFTPRES8
- See SOFTPRES0
SOFTPRES9
- See SOFTPRES0
SOFTPRES11
- See SOFTPRES0
SOFTPRES13
- See SOFTPRES0
SOFTPRES14
- See SOFTPRES0
SOFTPRES16
- See SOFTPRES0
CPUSEL0
sysctl.h SysCtl_selectCPUForPeripheralInstance
sysctl.h SysCtl_selectCPUForPeripheral
CPUSEL1
- See CPUSEL0
CPUSEL2
- See CPUSEL0
CPUSEL4
- See CPUSEL0
CPUSEL5
- See CPUSEL0
CPUSEL6
- See CPUSEL0
CPUSEL7
- See CPUSEL0
CPUSEL8
- See CPUSEL0
CPUSEL9
- See CPUSEL0
CPUSEL11
- See CPUSEL0
CPUSEL12
- See CPUSEL0
CPUSEL14

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Table 3-377. SYSCTL Registers to Driverlib Functions (continued)

File Driverlib Function
- See CPUSEL0
CPU2RESCTL
-
RSTSTAT
-
LPMSTAT
-
SYSDBGCTL
sysctl.c SysCtl_setClock
CLKSEM
-
CLKCFGLOCK1
-
CLKSRCCTL1
sysctl.c SysCtl_getClock
sysctl.c SysCtl_selectXTAL
sysctl.c SysCtl_selectOscSource
sysctl.c SysCtl_selectOscSourceAuxPLL
sysctl.h SysCtl_turnOnOsc
sysctl.h SysCtl_turnOffOsc
sysctl.h SysCtl_enableWatchdogInHalt
sysctl.h SysCtl_disableWatchdogInHalt
CLKSRCCTL2
can.h CAN_selectClockSource
sysctl.c SysCtl_getAuxClock
sysctl.c SysCtl_selectXTAL
sysctl.c SysCtl_selectOscSourceAuxPLL
CLKSRCCTL3
sysctl.h SysCtl_selectClockOutSource
SYSPLLCTL1
sysctl.c SysCtl_getClock
sysctl.c SysCtl_setClock
sysctl.h SysCtl_enterHaltMode
sysctl.h SysCtl_enterHibernateMode
SYSPLLMULT
sysctl.c SysCtl_getClock
sysctl.c SysCtl_setClock
SYSPLLSTS
sysctl.c SysCtl_setClock
AUXPLLCTL1
sysctl.c SysCtl_getAuxClock
sysctl.c SysCtl_setAuxClock
sysctl.c SysCtl_selectXTAL
AUXPLLMULT
sysctl.c SysCtl_getAuxClock

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Table 3-377. SYSCTL Registers to Driverlib Functions (continued)

File Driverlib Function
sysctl.c SysCtl_setAuxClock
AUXPLLSTS
sysctl.c SysCtl_setAuxClock
SYSCLKDIVSEL
sysctl.c SysCtl_getClock
sysctl.c SysCtl_setClock
sysctl.h SysCtl_setPLLSysClk
AUXCLKDIVSEL
sysctl.c SysCtl_getAuxClock
sysctl.c SysCtl_setAuxClock
sysctl.c SysCtl_selectXTAL
sysctl.h SysCtl_setAuxPLLClk
PERCLKDIVSEL
sysctl.h SysCtl_setEPWMClockDivider
sysctl.h SysCtl_setEMIF1ClockDivider
sysctl.h SysCtl_setEMIF2ClockDivider
XCLKOUTDIVSEL
sysctl.h SysCtl_setXClk
LOSPCP
sysctl.c SysCtl_getLowSpeedClock
sysctl.h SysCtl_setLowSpeedClock
MCDCR
sysctl.h SysCtl_enableMCD
sysctl.h SysCtl_disableMCD
sysctl.h SysCtl_isMCDClockFailureDetected
sysctl.h SysCtl_resetMCD
sysctl.h SysCtl_connectMCDClockSource
sysctl.h SysCtl_disconnectMCDClockSource
X1CNT
sysctl.h SysCtl_getExternalOscCounterValue
CPUSYSLOCK1
-
HIBBOOTMODE
-
IORESTOREADDR
-
PIEVERRADDR
sysctl.h SysCtl_getPIEVErrAddr
PCLKCR0
sysctl.h SysCtl_enablePeripheral
sysctl.h SysCtl_disablePeripheral
PCLKCR1
- See PCLKCR0
PCLKCR2
- See PCLKCR0

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Table 3-377. SYSCTL Registers to Driverlib Functions (continued)

File Driverlib Function
PCLKCR3
- See PCLKCR0
PCLKCR4
- See PCLKCR0
PCLKCR6
- See PCLKCR0
PCLKCR7
- See PCLKCR0
PCLKCR8
- See PCLKCR0
PCLKCR9
- See PCLKCR0
PCLKCR10
- See PCLKCR0
PCLKCR11
- See PCLKCR0
PCLKCR12
- See PCLKCR0
PCLKCR13
- See PCLKCR0
PCLKCR14
- See PCLKCR0
PCLKCR16
- See PCLKCR0
SECMSEL
sysctl.h SysCtl_selectSecController
LPMCR
sysctl.h SysCtl_enterIdleMode
sysctl.h SysCtl_enterStandbyMode
sysctl.h SysCtl_enterHaltMode
sysctl.h SysCtl_enterHibernateMode
sysctl.h SysCtl_setStandbyQualificationPeriod
sysctl.h SysCtl_enableWatchdogStandbyWakeup
sysctl.h SysCtl_disableWatchdogStandbyWakeup
GPIOLPMSEL0
sysctl.h SysCtl_enableLPMWakeupPin
sysctl.h SysCtl_disableLPMWakeupPin
GPIOLPMSEL1
sysctl.h SysCtl_enableLPMWakeupPin
sysctl.h SysCtl_disableLPMWakeupPin
TMR2CLKCTL
cputimer.h CPUTimer_selectClockSource
sysctl.c SysCtl_setClock
sysctl.c SysCtl_setAuxClock
sysctl.c SysCtl_selectXTAL

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Table 3-377. SYSCTL Registers to Driverlib Functions (continued)

File Driverlib Function
sysctl.h SysCtl_setCputimer2Clk
RESC
sysctl.h SysCtl_getResetCause
sysctl.h SysCtl_clearResetCause
sysctl.h SysCtl_getWatchdogResetStatus
sysctl.h SysCtl_clearWatchdogResetStatus
SCSR
sysctl.c SysCtl_setClock
sysctl.h SysCtl_setWatchdogMode
sysctl.h SysCtl_isWatchdogInterruptActive
sysctl.h SysCtl_clearWatchdogOverride
WDCNTR
sysctl.h SysCtl_getWatchdogCounterValue
WDKEY
sysctl.h SysCtl_serviceWatchdog
sysctl.h SysCtl_enableWatchdogReset
sysctl.h SysCtl_resetWatchdog
WDCR
sysctl.c SysCtl_setClock
sysctl.h SysCtl_resetDevice
sysctl.h SysCtl_disableWatchdog
sysctl.h SysCtl_enableWatchdog
sysctl.h SysCtl_isWatchdogEnabled
sysctl.h SysCtl_setWatchdogPrescaler
WDWCR
sysctl.c SysCtl_setClock
sysctl.h SysCtl_setWatchdogWindowValue
CLA1TASKSRCSELLOCK
-
DMACHSRCSELLOCK
-
CLA1TASKSRCSEL1
cla.c CLA_setTriggerSource
CLA1TASKSRCSEL2
cla.c CLA_setTriggerSource
DMACHSRCSEL1
dma.c DMA_configMode
DMACHSRCSEL2
dma.c DMA_configMode
SYNCSELECT
sysctl.h SysCtl_setSyncInputConfig
sysctl.h SysCtl_setSyncOutputConfig
ADCSOCOUTSELECT
sysctl.h SysCtl_enableExtADCSOCSource
sysctl.h SysCtl_disableExtADCSOCSource

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Table 3-377. SYSCTL Registers to Driverlib Functions (continued)

File Driverlib Function
SYNCSOCLOCK
sysctl.h SysCtl_lockExtADCSOCSelect
sysctl.h SysCtl_lockSyncSelect

3.17.27.5 NMI Registers to Driverlib Functions

Table 3-378. NMI Registers to Driverlib Functions
File Driverlib Function
CFG
sysctl.h SysCtl_enableNMIGlobalInterrupt
FLG
sysctl.h SysCtl_getNMIStatus
sysctl.h SysCtl_getNMIFlagStatus
sysctl.h SysCtl_isNMIFlagSet
sysctl.h SysCtl_clearNMIStatus
sysctl.h SysCtl_clearAllNMIFlags
sysctl.h SysCtl_forceNMIFlags
FLGCLR
sysctl.h SysCtl_clearNMIStatus
sysctl.h SysCtl_clearAllNMIFlags
FLGFRC
sysctl.h SysCtl_forceNMIFlags
WDCNT
sysctl.h SysCtl_getNMIWatchdogCounter
WDPRD
sysctl.h SysCtl_setNMIWatchdogPeriod
sysctl.h SysCtl_getNMIWatchdogPeriod
SHDFLG
sysctl.h SysCtl_getNMIShadowFlagStatus
sysctl.h SysCtl_isNMIShadowFlagSet

3.17.27.6 XINT Registers to Driverlib Functions

Table 3-379. XINT Registers to Driverlib Functions
File Driverlib Function
1CR
gpio.c GPIO_setInterruptPin
gpio.h GPIO_setInterruptType
gpio.h GPIO_getInterruptType
gpio.h GPIO_enableInterrupt
gpio.h GPIO_disableInterrupt
gpio.h GPIO_getInterruptCounter
2CR
- See 1CR
3CR
- See 1CR
4CR

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Table 3-379. XINT Registers to Driverlib Functions (continued)

File Driverlib Function
- See 1CR
5CR
- See 1CR
1CTR
gpio.h GPIO_getInterruptCounter
2CTR
-
3CTR
-

3.17.27.7 DCSM Registers to Driverlib Functions

Table 3-380. DCSM Registers to Driverlib Functions
File Driverlib Function
Z1OTP_LINKPOINTER1
-
Z1OTP_LINKPOINTER2
-
Z1OTP_LINKPOINTER3
-
Z1OTP_PSWDLOCK
-
Z1OTP_CRCLOCK
-
Z1OTP_BOOTCTRL
-
Z2OTP_LINKPOINTER1
-
Z2OTP_LINKPOINTER2
-
Z2OTP_LINKPOINTER3
-
Z2OTP_PSWDLOCK
-
Z2OTP_CRCLOCK
-
Z2OTP_BOOTCTRL
-
Z1_LINKPOINTER
dcsm.c DCSM_unlockZone1CSM
dcsm.h DCSM_getZone1LinkPointerError
Z1_OTPSECLOCK
-
Z1_BOOTCTRL
-
Z1_LINKPOINTERERR

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Table 3-380. DCSM Registers to Driverlib Functions (continued)

File Driverlib Function
dcsm.h DCSM_getZone1LinkPointerError
Z1_CSMKEY0
dcsm.c DCSM_unlockZone1CSM
Z1_CSMKEY1
dcsm.c DCSM_unlockZone1CSM
Z1_CSMKEY2
dcsm.c DCSM_unlockZone1CSM
Z1_CSMKEY3
dcsm.c DCSM_unlockZone1CSM
Z1_CR
dcsm.h DCSM_secureZone1
dcsm.h DCSM_getZone1CSMSecurityStatus
dcsm.h DCSM_getZone1ControlStatus
Z1_GRABSECTR
-
Z1_GRABRAMR
-
Z1_EXEONLYSECTR
dcsm.c DCSM_getZone1FlashEXEStatus
Z1_EXEONLYRAMR
dcsm.c DCSM_getZone1RAMEXEStatus
Z2_LINKPOINTER
dcsm.c DCSM_unlockZone2CSM
dcsm.h DCSM_getZone2LinkPointerError
Z2_OTPSECLOCK
-
Z2_BOOTCTRL
-
Z2_LINKPOINTERERR
dcsm.h DCSM_getZone2LinkPointerError
Z2_CSMKEY0
dcsm.c DCSM_unlockZone2CSM
Z2_CSMKEY1
dcsm.c DCSM_unlockZone2CSM
Z2_CSMKEY2
dcsm.c DCSM_unlockZone2CSM
Z2_CSMKEY3
dcsm.c DCSM_unlockZone2CSM
Z2_CR
dcsm.h DCSM_secureZone2
dcsm.h DCSM_getZone2CSMSecurityStatus
dcsm.h DCSM_getZone2ControlStatus
Z2_GRABSECTR
-
Z2_GRABRAMR

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Table 3-380. DCSM Registers to Driverlib Functions (continued)

File Driverlib Function
-
Z2_EXEONLYSECTR
dcsm.c DCSM_getZone2FlashEXEStatus
Z2_EXEONLYRAMR
dcsm.c DCSM_getZone2RAMEXEStatus
FLSEM
dcsm.c DCSM_claimZoneSemaphore
dcsm.c DCSM_releaseZoneSemaphore
SECTSTAT
dcsm.h DCSM_getFlashSectorZone
RAMSTAT
dcsm.h DCSM_getRAMZone

3.17.27.8 MEMCFG Registers to Driverlib Functions

Table 3-381. MEMCFG Registers to Driverlib Functions
File Driverlib Function
DXLOCK
memcfg.c MemCfg_lockConfig
memcfg.c MemCfg_unlockConfig
DXCOMMIT
memcfg.c MemCfg_commitConfig
DXACCPROT0
memcfg.c MemCfg_setProtection
DXTEST
memcfg.c MemCfg_setTestMode
DXINIT
memcfg.c MemCfg_initSections
memcfg.c MemCfg_getInitStatus
DXINITDONE
memcfg.c MemCfg_getInitStatus
LSXLOCK
memcfg.c MemCfg_lockConfig
memcfg.c MemCfg_unlockConfig
LSXCOMMIT
memcfg.c MemCfg_commitConfig
LSXMSEL
memcfg.c MemCfg_setLSRAMControllerSel
LSXCLAPGM
memcfg.h MemCfg_setCLAMemType
LSXACCPROT0
memcfg.c MemCfg_setProtection
LSXACCPROT1
-
LSXTEST
memcfg.c MemCfg_setTestMode

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Table 3-381. MEMCFG Registers to Driverlib Functions (continued)

File Driverlib Function
LSXINIT
memcfg.c MemCfg_initSections
memcfg.c MemCfg_getInitStatus
LSXINITDONE
memcfg.c MemCfg_getInitStatus
GSXLOCK
memcfg.c MemCfg_lockConfig
memcfg.c MemCfg_unlockConfig
GSXCOMMIT
memcfg.c MemCfg_commitConfig
GSXMSEL
memcfg.c MemCfg_setGSRAMControllerSel
GSXACCPROT0
memcfg.c MemCfg_setProtection
GSXACCPROT1
- See GSXACCPROT0
GSXACCPROT2
- See GSXACCPROT0
GSXACCPROT3
- See GSXACCPROT0
GSXTEST
memcfg.c MemCfg_setTestMode
GSXINIT
memcfg.c MemCfg_initSections
memcfg.c MemCfg_getInitStatus
GSXINITDONE
memcfg.c MemCfg_getInitStatus
MSGXTEST
memcfg.c MemCfg_setTestMode
MSGXINIT
memcfg.c MemCfg_initSections
memcfg.c MemCfg_getInitStatus
MSGXINITDONE
memcfg.c MemCfg_getInitStatus
EMIF1LOCK
emif.h EMIF_lockAccessConfig
emif.h EMIF_unlockAccessConfig
EMIF1COMMIT
emif.h EMIF_commitAccessConfig
EMIF1MSEL
emif.h EMIF_selectController
EMIF1ACCPROT0
emif.h EMIF_setAccessProtection
EMIF2LOCK
-

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Table 3-381. MEMCFG Registers to Driverlib Functions (continued)

File Driverlib Function
EMIF2COMMIT
-
EMIF2ACCPROT0
-
NMAVFLG
memcfg.h MemCfg_getViolationInterruptStatus
NMAVSET
memcfg.h MemCfg_forceViolationInterrupt
NMAVCLR
memcfg.h MemCfg_clearViolationInterruptStatus
NMAVINTEN
memcfg.h MemCfg_enableViolationInterrupt
memcfg.h MemCfg_disableViolationInterrupt
NMCPURDAVADDR
memcfg.c MemCfg_getViolationAddress
NMCPUWRAVADDR
memcfg.c MemCfg_getViolationAddress
NMCPUFAVADDR
-
NMDMAWRAVADDR
-
NMCLA1RDAVADDR
-
NMCLA1WRAVADDR
-
NMCLA1FAVADDR
-
MAVFLG
memcfg.h MemCfg_getViolationInterruptStatus
MAVSET
memcfg.h MemCfg_forceViolationInterrupt
MAVCLR
memcfg.h MemCfg_clearViolationInterruptStatus
MAVINTEN
memcfg.h MemCfg_enableViolationInterrupt
memcfg.h MemCfg_disableViolationInterrupt
MCPUFAVADDR
memcfg.c MemCfg_getViolationAddress
MCPUWRAVADDR
-
MDMAWRAVADDR
-
UCERRFLG
memcfg.h MemCfg_getUncorrErrorStatus
UCERRSET

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Table 3-381. MEMCFG Registers to Driverlib Functions (continued)

File Driverlib Function
memcfg.h MemCfg_forceUncorrErrorStatus
UCERRCLR
memcfg.h MemCfg_clearUncorrErrorStatus
UCCPUREADDR
memcfg.c MemCfg_getUncorrErrorAddress
UCDMAREADDR
memcfg.c MemCfg_getUncorrErrorAddress
UCCLA1READDR
-
CERRFLG
memcfg.h MemCfg_getCorrErrorStatus
CERRSET
memcfg.h MemCfg_forceCorrErrorStatus
CERRCLR
memcfg.h MemCfg_clearCorrErrorStatus
CCPUREADDR
memcfg.c MemCfg_getCorrErrorAddress
CERRCNT
memcfg.h MemCfg_getCorrErrorCount
CERRTHRES
memcfg.h MemCfg_setCorrErrorThreshold
CEINTFLG
memcfg.h MemCfg_getCorrErrorInterruptStatus
CEINTCLR
memcfg.h MemCfg_clearCorrErrorInterruptStatus
CEINTSET
memcfg.h MemCfg_forceCorrErrorInterrupt
CEINTEN
memcfg.h MemCfg_enableCorrErrorInterrupt
memcfg.h MemCfg_disableCorrErrorInterrupt
ROMWAITSTATE
memcfg.h MemCfg_enableROMWaitState
memcfg.h MemCfg_disableROMWaitState
ROMPREFETCH
memcfg.h MemCfg_enableROMPrefetch
memcfg.h MemCfg_disableROMPrefetch

3.17.27.9 FLASH Registers to Driverlib Functions

Table 3-382. FLASH Registers to Driverlib Functions
File Driverlib Function
FRDCNTL
flash.h Flash_setWaitstates
FBAC
flash.h Flash_setBankPowerUpDelay
FBFALLBACK

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Table 3-382. FLASH Registers to Driverlib Functions (continued)

File Driverlib Function
flash.h Flash_setBankPowerMode
FBPRDY
flash.h Flash_isBankReady
flash.h Flash_isPumpReady
FPAC1
flash.h Flash_setPumpPowerMode
flash.h Flash_setPumpWakeupTime
FMSTAT
-
FRD_INTF_CTRL
flash.h Flash_enablePrefetch
flash.h Flash_disablePrefetch
flash.h Flash_enableCache
flash.h Flash_disableCache
ECC_ENABLE
flash.h Flash_enableECC
flash.h Flash_disableECC
SINGLE_ERR_ADDR_LOW
flash.h Flash_getSingleBitErrorAddressLow
SINGLE_ERR_ADDR_HIGH
flash.h Flash_getSingleBitErrorAddressHigh
UNC_ERR_ADDR_LOW
flash.h Flash_getUncorrectableErrorAddressLow
UNC_ERR_ADDR_HIGH
flash.h Flash_getUncorrectableErrorAddressHigh
ERR_STATUS
flash.h Flash_getLowErrorStatus
flash.h Flash_getHighErrorStatus
flash.h Flash_clearLowErrorStatus
flash.h Flash_clearHighErrorStatus
ERR_POS
flash.h Flash_getLowErrorPosition
flash.h Flash_getHighErrorPosition
flash.h Flash_getLowErrorType
flash.h Flash_getHighErrorType
ERR_STATUS_CLR
flash.h Flash_clearLowErrorStatus
flash.h Flash_clearHighErrorStatus
ERR_CNT
flash.h Flash_getErrorCount
ERR_THRESHOLD
flash.h Flash_setErrorThreshold
ERR_INTFLG
flash.h Flash_getInterruptFlag
ERR_INTCLR

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Table 3-382. FLASH Registers to Driverlib Functions (continued)

File Driverlib Function
flash.h Flash_clearSingleErrorInterruptFlag
flash.h Flash_clearUncorrectableInterruptFlag
FDATAH_TEST
flash.h Flash_setDataHighECCTest
FDATAL_TEST
flash.h Flash_setDataLowECCTest
FADDR_TEST
flash.h Flash_setECCTestAddress
FECC_TEST
flash.h Flash_setECCTestECCBits
FECC_CTRL
flash.h Flash_enableECCTestMode
flash.h Flash_disableECCTestMode
flash.h Flash_selectLowECCBlock
flash.h Flash_selectHighECCBlock
flash.h Flash_performECCCalculation
FOUTH_TEST
flash.h Flash_getTestDataOutHigh
FOUTL_TEST
flash.h Flash_getTestDataOutLow
FECC_STATUS
flash.h Flash_getECCTestStatus
flash.h Flash_getECCTestErrorPosition
flash.h Flash_getECCTestSingleBitErrorType
PUMPREQUEST
flash.h Flash_claimPumpSemaphore
flash.h Flash_releasePumpSemaphore

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Chapter 4
ROM Code and Peripheral Booting

This chapter describes the booting functionality.

Further information about the boot-loading process can be found in the TMS320F28004x Boot Features and
Configurations Application Report.

4.1 Introduction...............................................................................................................................................................615
4.2 Boot ROM Registers.................................................................................................................................................615
4.3 Device Boot Sequence.............................................................................................................................................615
4.4 Device Boot Modes.................................................................................................................................................. 616
4.5 Configuring Boot Mode Pins................................................................................................................................... 617
4.6 Configuring Get Boot Options.................................................................................................................................619
4.7 Configuring Emulation Boot Options..................................................................................................................... 620
4.8 Device Boot Flow Diagrams.................................................................................................................................... 621
4.9 Device Reset and Exception Handling................................................................................................................... 627
4.10 Boot ROM Description........................................................................................................................................... 629

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4.1 Introduction
This chapter explains the boot ROM code functionality including the boot procedure when executed, the
functions and features of the boot ROM code, and details the ROM memory map contents. On every reset,
the device executes a boot sequence in the ROM depending on the reset type and boot configuration. This
sequence initializes the device to run application code. The boot ROM also contains peripheral bootloaders
which can be used to load an application into RAM. ROM Memory is shown in Table 4-1.
Table 4-1. ROM Memory
ROM CPU1 Size CPU2 Size
Unsecure boot ROM 64KB 64KB
Secure ROM 64KB 64KB
CLA Data ROM 8KB 8KB

4.2 Boot ROM Registers

The boot process code accesses several memory addresses and registers during execution. There are two sets
of addresses, one for emulation and one for standalone boot flow. The emulation boot-control locations emulate
OTP configurations and can be written to as many times as needed. The user configurable DCSM OTP locations
used in the standalone boot flow program the device OTP and thus can only be written once. Table 4-2 details
these locations.
Table 4-2. Boot ROM Registers
Boot Flow Register Name Boot ROM Name Address
Emulation - EMU_BOOTCTRL 0x0000 0D00
Standalone (Using Z1) Z1_BOOTCTRL Z1_BOOTCTRL 0x0005 F004
Standalone (Using Z2) Z2_BOOTCTRL Z2_BOOTCTRL 0x0005 F044

4.3 Device Boot Sequence

The boot sequence, Table 4-3, describes the general boot ROM procedure each time the CPU core is reset. For
dual-core devices, CPU1 is the master controller and controls the boot process. Each CPU goes through a boot
procedure, but under the control of CPU1. The exception to this rule is when CPU2 is set to boot-to-Flash, in
which CPU1 is not involved.
During booting, the boot ROM code updates a boot status location in RAM that details the actions taken during
this process. Refer to Section 4.10.11 for more details.
Table 4-3. Boot ROM Sequence
Step CPU1 Action CPU2 Action
1 After reset, the FUSE error register is checked for any errors and are handled Held in reset.
accordingly.
2 Clock and Flash Configuration Held in reset.
3 Device configuration registers are programmed from OTP. Held in reset.
4 All CPU RAMs are initialized. Held in reset.
5 Any pending NMI is handled by the code. Held in reset.
6 DCSM initialization sequence is executed. Held in reset.
7 Bring CPU2 out of reset. Brought out of reset and performs:
1. Clock and Flash Configuration
2. All CPU RAMs are initialized
3. DCSM initialization
8 Based on the boot mode select GPIO pins and boot mode set in OTP, the boot Based on the boot mode value
mode is determined, and the appropriate boot sequence is executed. Refer to read from OTP, the appropriate boot
Section 4.8 for a flow chart of the device boot sequences. sequence is executed.

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4.4 Device Boot Modes

This section explains the boot modes supported on this device. The boot ROM uses the boot select GPIO pins to
determine the boot mode configuration. The device can be configured to boot to RAM, boot to Flash, execute a
bootloader, or hold in a wait mode.
Table 4-4 shows the boot mode options available through selection by the default boot mode select pins. The
boot mode select pins’ GPIOs and realized boot mode for when Get boot mode is selected can be customized
through the BOOTCTRL register detailed in Section 4.5.
Table 4-4. Device Default Boot Modes for CPU1
Boot Mode GPIO72 GPIO84
(Default boot mode select pin 1) (Default boot mode select pin 0)
Parallel IO 0 0
SCI 0 1
Wait 1 0
Get / Flash(1) 1 1

(1) Get boot mode, by default, on an unprogrammed device, or when the BOOTCTRL register contains an invalid key, boots to Flash
mode. Get boot mode can be programmed on the device to change the default boot mode. Refer to Section 4.6 for more details on
using Get boot mode.

Table 4-5. All Available Boot Modes

Boot Mode CPU Support
Parallel IO CPU1 and CPU2
SCI CPU1 and CPU2
Wait CPU1 and CPU2
Get CPU1 and CPU2
SPI CPU1 and CPU2
I2C CPU1 and CPU2
CAN CPU1 and CPU2
RAM CPU1 and CPU2
Flash CPU1 and CPU2
USB CPU1 Only

Note
All the peripheral boot modes that are supported use the first instance of the peripheral module (SCIA,
SPIA, I2CA, CANA, and so forth). Whenever these boot modes are referred to in this chapter, such
as SCI boot, the mode is actually referring to the first module instance, meaning the SCI boot on the
SCIA port. The same applies to the other peripheral boots.

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4.5 Configuring Boot Mode Pins

This section details how the boot mode select pins can be customized by the user, by programming the
BOOTCTRL register location in user-configurable DCSM OTP. The BOOTCTRL register, when programmed
with a valid key, allows different GPIOs to be used for the two boot mode select pins. Additionally, the boot
mode select pins allow the same GPIO to be assigned to each pin for single GPIO use cases. Also within
the BOOTCTRL register, the default boot mode for use with Get boot can be changed. When debugging,
EMU_BOOTCTRL is the emulation equivalent of the BOOTCTRL register and allows users to experiment with
different boot modes without writing to OTP memory. Refer to Section 4.7 for details on values that can be set in
the EMU_BOOTCTRL control word.

Note
Refer to Section 3.13 for the address of the BOOTCTRL register location in the user-configurable
DCSM OTP.

Table 4-6. BOOTCTRL Register Bit Fields for CPU1

Bit Name Description
31-24 Boot Mode Select Pin 1 (BMSP1) Set to the GPIO pin to be used during boot
(up to 255).
0 = Default BMSP1
1 = GPIO0
2 = GPIO1
...
255 = GPIO254
23-16 Boot Mode Select Pin 0 (BMSP0) Set to the GPIO pin to be used during boot
(up to 255).
0 = Default BMSP0
1 = GPIO0
2 = GPIO1
...
255 = GPIO254
15-8 Boot Mode (BMODE) Boot mode definition when using Get boot
mode option. Refer to Section 4.6 for valid
BMODE values.
7-0 Key Write 0x5A to these 8-bits to tell the boot
ROM code that the bits in this register are
valid

Table 4-7. BOOTCTRL Register Bit Fields for CPU2

Bit Name Description
31-24 Reserved Reserved
23-16 Reserved Reserved
15-8 Boot Mode (BMODE) Boot mode definition when using Get boot
mode option. Refer to Section 4.6 for valid
BMODE values.
7-0 Key Write 0x5A to these 8-bits to tell the boot
ROM code that the bits in this register are
valid

On this device, the DCSM has two zones. Each zone, Z1 and Z2, has a copy of the BOOTCTRL register. The
boot ROM is designed to be able to read from either location and uses the procedure in Figure 4-1 to identify
which register to use. By default, if the Z1 BOOTCTRL is programmed, then that register is given the priority.
If the Z1 BOOTCTRL is not programmed, then the boot ROM checks if Z2 BOOTCTRL is programmed; if not
programmed, then the factory default options are used.

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Get_mode - Boot Option

Decode Zones selection as below

Z1-BOOTCTRL. OTP_KEY = Z2-BOOTCTRL. OTP_KEY = Use Factory default

NO NO
0x5A? 0x5A? Options

YES YES

Use Z1 BOOTCTRL Use Z2 BOOTCTRL

register register

Figure 4-1. Z1 and Z2 BOOTCTRL Selection

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4.6 Configuring Get Boot Options

In Get boot mode, the boot ROM reads the boot mode (BMODE) bit field in the BOOTCTRL register to
determine which boot procedure to execute. By default, Get boot mode executes Flash boot when in standalone
mode or wait boot mode when an emulator is connected to the device. Table 4-8 lists the values that can be
set to the BMODE field in BOOTCTRL for CPU1 and the corresponding boot mode represented.Table 4-9 lists
the acceptable values for CPU2. For additional details on the GPIOs used for each boot mode, refer to Section
4.10.6. When debugging the device using an emulator and EMU_BOOTCTRL, the BMODE field has some
additional values that can be found in Section 4.7.
Table 4-8. Get Mode Decoding on CPU1
Key BMODE Value Realized Boot Mode
!= 0x5A Don’t Care Flash Boot / Wait Boot(1)
0x00 Parallel Boot
0x01 SCI Boot 0
0x02 Wait Boot
0x04 SPI Boot 0
0x05 I2C Boot 0
0x07 CAN Boot 0
= 0x5A 0x0A RAM Boot
0x0B Flash Boot
0x0C USB Boot
0x81 SCI Boot 1
0x84 SPI Boot 1
0x85 I2C Boot 1
0x87 CAN Boot 1
Other Flash Boot / Wait Boot(1)

(1) When an emulator is connected (TRSTn = 1) to the device, then an invalid EMU BOOTCTRL key or invalid EMU configured boot mode
results in wait boot mode. If an emulator is connected with a valid EMU BOOTCTRL key and the EMU boot mode is configured to
"Get Mode" boot then an invalid OTP BOOTCTRL key results in Flash boot mode. If an emulator is not connected with the boot mode
selected to "Get Mode" boot, then an invalid OTP BOOTCTRL key or invalid OTP memory configured boot mode results in Flash boot
mode.

Table 4-9. Get Mode Decoding on CPU2

Key BMODE Value Realized Boot Mode
!= 0x5A Don’t Care Wait Boot
= 0x5A 0x0A Wait Boot / RAM Boot(1)
0x0B Flash Boot
Other Wait Boot

(1) Only after a hibernate reset, CPU2 can boot in RAM boot mode. After any other resets, CPU2 boots in wait boot mode.

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4.7 Configuring Emulation Boot Options

When connected to the device using an emulator, the EMU_BOOTCTRL control word is used to determine the
boot mode. This control word allows the user to experiment with various boot mode settings before writing to
the BOOTCTRL register in the user-configurable DCSM OTP. The values that can be set in the BMODE field of
the EMU_BOOTCTRL control word are listed in Section 4.7. Some notable options include being able to have
emulation boot read from the boot mode select pins, emulate standalone boot using the values in OTP, and boot
according to the Get boot value stored in OTP memory. Refer to Section 4.10.6 for details on the GPIOs used in
the various boot modes.

Note
EMU_BOOTCTRL is not actually a register, but refers to a location in RAM (PIE RAM). PIE RAM
starts at 0xD00, but the first few locations are reserved (when initializing the PIE vector table in
application code) for these boot ROM variables.

Table 4-10. Emulation Boot Options

Key BMODE Value Realized Boot Mode CPU Support
!= 0x5A Don’t Care Wait Boot CPU1 and CPU2
0xFE Boot as per BMSP0 and BMSP1 CPU1 Only
0xFF Emulate Standalone boot CPU1 and CPU2
0x00 Parallel Boot CPU1 and CPU2
0x01 SCI Boot 0 CPU1 and CPU2
0x02 Wait Boot CPU1 and CPU2
0x03 Get Mode(read OTP CPU1 and CPU2
BOOTCTRL)
= 0x5A 0x04 SPI Boot 0 CPU1 and CPU2
0x05 I2C Boot 0 CPU1 and CPU2
0x07 CAN Boot 0 CPU1 and CPU2
0x0A RAM Boot CPU1 and CPU2
0x0B Flash Boot CPU1 and CPU2
0x0C USB Boot CPU1 Only
0x81 SCI Boot 1 CPU1 Only
0x84 SPI Boot 1 CPU1 Only
0x85 I2C Boot 1 CPU1 Only
0x87 CAN Boot 1 CPU1 Only
Other Wait Boot CPU1 and CPU2

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4.8 Device Boot Flow Diagrams

Figure 4-2 shows the device boot flow for CPU1 detailing the actions executed by boot ROM after a reset. Figure
4-3 shows the device boot flow for CPU2.

Note
For CPU1, the PLL is not used in the device clock path during boot, only INTOSC is used.

Reset
XRSn or
POR or
No No Hibernate No Other Resets
WD or NMIWD
resets

HWBIST Yes Yes

RESET Clean up Stack
-> PLL power up for Boot ROM
-> PLL power up
-> clock dividers config -> clock dividers config
-> Flash Power up -> Flash Power up
Yes
-> PLL configuration ->PLL configuration
-> Device Config -> Device Config
Branch to
Application DCSM INIT

M0M1
No Retention Yes
Initialize all ON
RAMs
Initialize all Initialize all RAMs
RAMs except for M0/M1

DCSM INIT

DCSM INIT

PLL Bypass On a single core

On a single core device device this has
this has no effect PLL Bypass no effect
Bring CPU2 out
of RESET Bring CPU2 out
of RESET
Call application
IORESTORE On a single
function core device this
has no effect

Bring CPU2 out

of RESET
Select Boot
Mode

Valid
Boot as per
Hibernate Boot
Yes Hibernate Boot
Key == 0x5A
TRSTn == 1 Mode
Yes No

No

EMU Boot Standalone Fall Back to

Boot default Boot

Figure 4-2. CPU1 Device Boot Flow

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Reset

XRSn or POR Hibernate Other Resets

No

HWBIST RESET Yes

Yes

Yes M0M1
No Yes
Retention ON
Branch to
Application Clean up Stack for
Initialize all RAMs
Boot ROM
except for M0/M1
Initialize all RAMs

Initialize all RAMs

DCSM INIT

Call application
IORESTORE
function
DCSM INIT

Hibernate Boot Boot as per

Yes
Key == 0x5A Hibernate Boot

No

Fall Back to default

Select Boot Mode
Boot

TRSTn == 1

No
Yes

EMU Boot Standalone Boot

Figure 4-3. CPU2 Device Boot Flow

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4.8.1 Emulation Boot Flow Diagrams

Figure 4-4 shows the boot flow for CPU1 when running the device in emulation mode. Figure 4-5 shows the
emulation boot flow for CPU2.
32 bit wide register named EMUBOOTCTRL located at 0xD00

WAIT BOOT MODE Bits 7:0 EMU_KEY ± Use 0x5A to indicate validity of this location
Emulation Boot Mode
> Init PIE values.
While(1)
> Install C2C1IPC Handler
No > Disable WatchDOG Bits 15:8 EMU_BMODE - Use this field to define upto 256 boot modes

Bits 23:16 EMU_BOOTPIN 0

0-> Pick the default boot pin-0 (GPIO 84)
1 -> Pick GPIO0 as boot pin-0
EMUBOOTCTRL.E 2 -> Pick GPIO1 as boot pin-0
MU_KEY == 0x5A? «.
255 -> Pick GPIO255 as boot pin-0

Emulate Standalone Go to Stand-Alone 31:24 EMU_BOOTPIN1

Yes Boot Mode sequence Boot Mode flow 0 -> Pick the default boot pin-1 (GPIO 72)
Yes 1 -> Pick GPIO0 as boot pin-1
2 -> Pick GPIO1 as boot pin-1
«.
255 -> Pick GPIO255 as boot pin-1
EMUBOOTCTRL.EMU_
BMODE == 0xFF

Valid Valid
EMUBOOTCTRL. EMUBOOTPIN0 = EMUBOOTPIN1 =
Read EmuBoot pins NO EMUBOOTCTRL. No
EMUBOOTPIN0 GPIO84 GPIO72
EMUBOOTPIN1
No Yes

Yes
EMUBOOTCTRL.EMU
_BMODE == 0xFE
Yes EMUBOOTPIN0 = EMUBOOTPIN1 = BootMode =
EMUBOOTCTRL.EM EMUBOOTCTRL.EM (*EMUBOOTPIN1 << 1) |
UBOOTPIN0 UBOOTPIN1 (*EMUBOOTPIN0)

No

------------------------------------------------------------------------------------------------
EMU_BMODE Value | Realized Boot Mode
------------------------------------------------------------------------------------------------
0x00 Parallel Boot Boot Mode = 0 -> Parallel Boot Mode
0x01 SCIBOOT(0) Boot Mode = 1 -> SCIBOOT Mode
0x02 WAIT BOOT Boot Mode = 2 -> WAIT BOOT Mode
0x03 GET MODE (OTP) Is Get Mode Boot Mode = 3 -> GET MODE (read OTP Boot
0x04 SPIBOOT(0) Mode values)
0x05 I2CBOOT(0)
No Yes
0x07 CANBOOT(0)
0x0A RAMBOOT
0x0B FLASHBOOT
0x0C USB BOOT
0x81 SCIBOOT(1) ± Alternate IO
0x84 SPIBOOT(1)- Alternate IO
0x85 I2CBOOT(1) ± Alternate IO
0x87 CANBOOT(1) ± Alternate IO
Start Boot LOAD Get Mode
0x47 CANBOOT(TEST)(0) ± TESTMODE
0xC7 CANBOOT(TEST)(1) ± TEESTMODE, Alternate
IO
Other WAIT BOOT

Figure 4-4. CPU1 Emulation Boot Flow

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32 bit wide register named EMUBOOTCTRL located at 0xD00

Bits 7:0 EMU_KEY - Use 0x5A to indicate validity of this location

values.

Bits 15:8 EMU_BMODE - Use this field to define upto 256 boot modes

Bits 31:16 RESERVED A

GET MODE

EMU_BMODE Value | Realized Boot Mode

No
0x00 Parallel Boot
0x01 SCIBOOT
0x02 WAIT BOOT
EMU BOOT EMUKEY == 0x5A Yes 0x03 GET MODE (OTP)
0x04 SPIBOOT
0x05 I2CBOOT
0x07 CANBOOT
0x0B FLASHBOOT
Other WAIT BOOT

Figure 4-5. CPU2 Emulation Boot Flow

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4.8.2 Standalone and Hibernate Boot Flow Diagrams

Figure 4-6 shows the device boot flow for CPU1 when running the device in standalone boot mode or when
booting from hibernate. Figure 4-7 shows the standalone boot flow and hibernate boot flow for CPU2.

Findou t wh ich bo ot BOO TP IN0 =

Zx-
pins to rea d ± user GPIO84
Stand Alon e B oot BOO TCTRL.OTP_K No
configured or Factor y BOO TP IN1 =
EY == 0x5A
default GPIO72 32 bit wide regis ter name d Zx-BOOTCTRL located at 0x780 1E for Zone1 and 0x782 1E for Zone 2

Bits 7:0 OTP_KEY ± Use 0x5A to ind ica te validity of this locatio n
values.
Yes
Bits 15:8 OTP_BMODE - Use this field to d efin e u pto 256 boo t modes
BOO TP IN0 =
Bits 23:16 OTP_BOO TP IN 0
ZxB OOTCTRL.OTPBO O Yes
Zx- 0-> Pick the default boo t pin-0 (GPIO 84)
TPIN0
BOO TCTRL.OTP_BO 1 -> Pick GP IO0 as b oot pin-0
OTPIN0 is valid? 2 -> Pick GP IO1 as b oot pin-0
«.
255 -> Pick GP IO255 as b oot pin-0

31:24 OTP_BOO TP IN1

0 -> Pick the default boo t pin-1 (GPIO 72)
No 1 -> Pick GP IO0 as b oot pin-1
2 -> Pick GP IO1 as b oot pin-1
Zx- «.
BOO TP IN1 = 255 -> Pick GP IO255 as b oot pin-1
BOO TCTRL.OTP BOO TP IN0 =
ZxB OOTCTRL.OTPBO O Yes
_BOO TP IN1 is GPIO84
TPIN1
valid?

No
Boo t Mode = 0 -> Par allel Boot Mod e
Boo tMode = Boo t Mode = 1 -> SCIBOOT Mo de
BOO TP IN0 = (*BOO TP IN1 << Boo t Mode = 2 -> WAIT BOO T Mode
GPIO72 1)|(*BOO TP IN0) Boo t Mode = 3 -> GET MODE (read OTP Boot
Mode values)

Yes GET MODE Start bo ot LO AD

Hiberna te Boo t

GET MODE (boo t Mode) ----- --------- ---------- --------- --------- --------- ---------- --------- --------- --------- --------
Boo tMode Va lue | Realized Boo t Mo de
----- --------- ---------- --------- --------- --------- ---------- --------- --------- --------- --------
0x00 Par allel Boot
0x01 SCIBOOT(0)
Zx- Boo tMode = Zx- 0x02 WAIT BOO T
BOO TCTRL.OTP Yes OTPBO OTCTRL.OT 0x04 SPIBO OT(0)
_KEY == 0x5A P_BMODE 0x05 I2CBOOT(0)
0x07 CANBOOT(0)
0x0A RAMBOOT
0x0B FLASHBO OT
No 0x0C USB BOO T
0x81 SCIBOOT(1) ± Alterna te IO
Is Get Mod e 0x84 SPIBO OT(1)- Alterna te IO
Ena ble Wa tchdog 0x85 I2CBOOT(1) ± Alterna te IO
Boo t to Flash 0x87 CANBOOT(1) ± Alterna te IO
0x47 CANBOOT(TEST)(0) ± TESTMODE
0xC7 CANBOOT(TEST)(1) ± TEESTMODE, Alterna te IO
No Other FLASHBO OT (if stand Alone) EMUBOOT (if CCS con nected)

Figure 4-6. CPU1 Standalone and Hibernate Boot Flow

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Stand Alon e

Zx- Yes Zx.BOO TCTRL.OTP_BMODE

BOO TCTRL.OTP_KEY
== FLASH BOOT
== 0x5A

Yes
No
Get Mo de

WAIT BOO T MODE FLASH BOOT

> Init PIE No
> Install C2C1IPC Handl er
A > Disa ble WatchDOG
> LPM = IDL E MODE

No
B

WAIT BOO T

No
HiBern ate Bo ot RAM B OOT MODE Flash B oot Mode

Yes Yes

Boo t to RAM Boo t to Flash

Figure 4-7. CPU2 Standalone and Hibernate Boot Flow

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4.9 Device Reset and Exception Handling

4.9.1 Reset Causes and Handling
This section explains the actions boot ROM performs upon reset after checking the reset cause.
Table 4-11. Boot ROM Reset Causes and Actions
Reset Source CPU1 Boot ROM Action CPU2 Boot ROM Action
POR 1. Adjust clock divider to /1
2. Device configuration 1. RAM Initialization
3. RAM initialization 2. Continue default boot flow
4. Continue default boot flow
XRS 1. Adjust clock divider to /1
2. Device configuration 1. RAM Initialization
3. RAM initialization 2. Continue default boot flow
4. Continue default boot flow
HWBIST Branch to application code Branch to application code
Hibernate 1. Adjust clock divider to /1
2. Device configuration 1. RAM initialization (Either all RAMS
except for M0M1 or all RAMS)
3. RAM initialization (Either all RAMS 2. Continue default boot flow
except for M0M1 or all RAMS)
4. Continue default boot flow
WDRS (CPU1) 1. Adjust clock divider to /1
2. Device configuration 1. RAM initialization
3. RAM initialization 2. Continue default boot flow
4. Continue default boot flow
WDRS (CPU2) Exception handled by CPU1 1. Clear boot stack
2. Continue default boot flow
NMIWDRS (CPU1) 1. Adjust clock divider to /1
2. Device configuration 1. RAM initialization
3. RAM initialization 2. Continue default boot flow
4. Continue default boot flow
NMIWDRS (CPU2) Exception handled by CPU1 1. Clear boot stack
2. Continue default boot flow
Debugger (CPU1) 1. Clear boot stack No Action
2. Continue default boot flow
Debugger (CPU2) Exception handled by CPU1 1. Clear boot stack
2. Continue default boot flow
SCCRESET (CPU1) 1. Clear boot stack No Action
2. Continue default boot flow
SCCRESET (CPU2) Exception handled by CPU1 1. Clear boot stack
2. Continue default boot flow

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4.9.2 Exceptions and Interrupts Handling

This section explains the actions boot ROM performs if any exceptions that can occur happen during boot.
Table 4-12. Boot ROM Exceptions and Actions
Exception Event Source CPU1 Boot ROM Action CPU2 Boot ROM Action Event Logged
Single-bit error in FUSEERR Ignore and continue to boot Ignore and continue to boot No
Multi-bit error in FUSEERR Reset the device No action required No
Clock fail condition detected Clear the NMI and continue to boot Clear the NMI and continue to boot Yes
Double-bit ECC error from RAM Reset the device Send IPC to CPU1, clear NMI flag, Yes
and wait forever
Double-bit error from Flash Reset the device Send IPC to CPU1, clear NMI flag, Yes
and wait forever
PIE Vector Error Ignore and continue to boot Ignore and continue to boot Yes
HWBIST Error Ignore and continue to boot Send IPC to CPU1, clear NMI flag, Yes
and wait forever
ITRAP Exception Provide ROM location where ROM Provide ROM location to CPU1 of Yes
loops where ROM loops
CPU2 NMIWDRST Ignore and continue to boot No action required Yes
CPU2 WDRST Ignore and continue to boot No action required Yes
Any spurious PIE interrupt occurs Acknowledge interrupt and continue Send IPC to CPU1 and No
to boot acknowledge interrupt

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4.10 Boot ROM Description

This section explains the details regarding the device boot ROM.
4.10.1 Entry Points
Table 4-13 gives the entry point addresses for various boot modes. These entry points indicate to the boot ROM
where to branch to at the end of booting as per the selected boot mode.
Table 4-13. Entry Point Addresses for CPU1 and CPU2
Entry Point Address
RAM 0x0000 0000
Flash 0x0008 0000

4.10.2 Wait Points

During boot ROM execution, there are situations where the CPU can enter a wait loop in the code. This state
can occur for a variety of reasons.
Table 4-14 gives the address ranges that the CPU1 PC register value falls between, if the boot code has entered
one of these instances. Table 4-15 gives the addresses for CPU2.
Table 4-14. Wait Point Addresses for CPU1
Address Range Description
0x003F E2D4 – 0x003F E2EF In Wait Boot
0x003F E73E – 0x003F E824 In NMI Handler (startup)
0x003F E35A – 0x003F E468 In NMI Handler (PIE)
0x003F E468 – 0x003F E495 In ITRAP ISR

Table 4-15. Wait Point Addresses for CPU2

Address Range Description
0x003F E44C – 0x003F E451 In Idle Mode
0x003F DEAA – 0x003F DFC2 In NMI Handler
0x003F DE61 – 0x003F DEAA In PIE Vector Mismatch Handler
0x003F DFC2 – 0x003F E00B In ITRAP ISR

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4.10.3 Memory Maps

This section details the ROM memory maps.
4.10.3.1 CPU1 Boot ROM Memory Map
Table 4-16. CPU1 Boot ROM Memory Map
Memory Start Address End Address Length
ROM Signature 0x003F 8000 0x003F 8001 0x0002
TI-RTOS (ROM)(1) 0x003F 8002 0x003F 9E0F 0x1E0E
PLC Tables 1 0x003F 9E10 0x003F D817 0x3A08
PLC Tables 2 0x003F D818 0x003F DE17 0x0600
Boot 0x003F DE18 0x003F FF31 0x211A
CRC Table 0x003F FF32 0x003F FF39 0x0008
BIST Signature 0x003F FF3A 0x003F FF79 0x0040
Version 0x003F FF7A 0x003F FF7B 0x0002
Checksum 0x003F FF7C 0x003F FFBD 0x0042
Vectors 0x003F FFBE 0x003F FFFF 0x0042
TI-RTOS (Flash) 0x0008 2000 0x0008 3FFF 0x2000

(1) The SYS/BIOS (TI-RTOS) section in ROM is no longer supported and must not be used for new designs.

4.10.3.2 CPU2 Boot ROM Memory Map

Table 4-17. CPU2 Boot ROM Memory Map
Memory Start Address End Address Length
ROM Signature 0x003F 8000 0x003F 8001 0x0002
TI-RTOS (ROM)(1) 0x003F 8002 0x003F 9E0F 0x1E0E
PLC Tables 1 0x003F 9E10 0x003F D817 0x3A08
PLC Tables 2 0x003F D818 0x003F DE17 0x0600
Boot 0x003F DE18 0x003F FF31 0x211A
CRC Table 0x003F FF32 0x003F FF39 0x0008
BIST Signature 0x003F FF3A 0x003F FF79 0x0040
Version 0x003F FF7A 0x003F FF7B 0x0002
Checksum 0x003F FF7C 0x003F FFBD 0x0042
Vectors 0x003F FFBE 0x003F FFFF 0x0042
TI-RTOS (Flash) 0x0008 2000 0x0008 3FFF 0x2000

(1) The SYS/BIOS (TI-RTOS) section in ROM is no longer supported and must not be used for new designs.

4.10.3.3 CLA Data ROM Memory Map

Table 4-18. CLA Data ROM Memory Map
Memory Start Address End Address Length
FFT Tables (Load) 0x0100 1070 0x0100 186F 0x0800
Data (Load) 0x0100 1870 0x0100 1FF9 0x078A
Version (Load) 0x0100 1FFA 0x0100 1FFF 0x0006

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4.10.3.4 Reserved RAM and Flash Memory-Map

Table 4-19. Reserved RAM and Flash Memory-Map for CPU1
Memory Description Start Address End Address Length
RAM Boot ROM 0x0000 0002 0x0000 0122 0x0121
TI-RTOS(1) 0x0000 0780 0x0000 07FF 0x0080
Flash TI-RTOS(1) (2) 0x0008 2000 0x0008 2823 0x0824

(1) If not planning on using TI-RTOS in ROM, then these memory locations are free to be used by the application.
(2) For using the TI-RTOS in Flash sector A, TI recommends that this sector be made unsecure, or at minimum, the sector must be
verified that there is no secure zone claiming this sector.

Table 4-20. Reserved RAM and Flash Memory-Map for CPU2

Memory Description Start Address End Address Length
RAM Boot ROM 0x0000 0002 0x0000 00A1 0x00A0
TI-RTOS(1) 0x0000 0780 0x0000 07FF 0x0080
Flash TI-RTOS(1) (2) 0x0008 2000 0x0008 2823 0x0824

(1) If not planning to use TI-RTOS in ROM, then these memory locations are free to be used by the application.
(2) For using the TI-RTOS in Flash sector A, TI recommends that this sector be made unsecure, or at minimum, the sector must be
verified that there is no secure zone claiming this sector.

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4.10.3.5 ROM Tables

This section details the boot ROM and CLA ROM symbol tables.
4.10.3.5.1 Boot ROM Tables
The boot ROM symbols and their addresses can be located in the .map file that is included with the released
boot ROM source and header code. Within the .map file, locate the Global Symbols category to get a list of the
boot ROM symbols and addresses present.
4.10.3.5.2 CLA ROM Tables
Table 4-21. CLA Data ROM Tables
Start Address From CLA in Hex Start Address From CPU in Hex
_CLAatan2HalfPITable F870 0100 1870
_CLAINV2PI F874 0100 1874
_CLAatan2Table F876 0100 1876
_CLAasinHalfPITable F9FC 0100 19FC
_CLAatan2TableEnd F9FC 0100 19FC
_CLAasinTable FA00 0100 1A00
_CLAacosinHalfPITable FB86 0100 1B86
_CLAasinTableEnd FB86 0100 1B86
_CLAacosinTable FB8A 0100 1B8A
_CLAacosinTableEnd FD0A 0100 1D0A
_CLAsinTable FD0A 0100 1D0A
_CLAsincosTable FD0A 0100 1D0A
_CLAsincosTable_Sin0 FD0A 0100 1D0A
_CLAcosTable FD4A 0100 1D4A
_CLAsincosTable_Cos0 FD4A 0100 1D4A
_CLAsinTableEnd FE0A 0100 1E0A
_CLAcosTableEnd FE4C 0100 1E4C
_CLAsincosTable_TABLE_SIZE FE4C 0100 1E4C
_CLAsincosTable_TABLE_SIZEDivTwoPi FE4E 0100 1E4E
_CLAsincosTable_TwoPiDivTABLE_SIZE FE50 0100 1E50
_CLAsincosTable_TABLE_MASK FE52 0100 1E52
_CLAsincosTable_Coef0 FE54 0100 1E54
_CLAsincosTable_Coef1 FE56 0100 1E56
_CLAsincosTable_Coef1_pos FE58 0100 1E58
_CLAsincosTable_Coef2 FE5A 0100 1E5A
_CLAsincosTable_Coef3 FE5C 0100 1E5C
_CLAsincosTable_Coef3_neg FE5E 0100 1E5E
_CLALNV2 FE60 0100 1E60
_CLAsincosTableEnd FE60 0100 1E60
_CLALNVe FE62 0100 1E62
_CLALNV10 FE64 0100 1E64
_CLABIAS FE66 0100 1E66
_CLALN_TABLE_MASK1 FE68 0100 1E68
_CLALN_TABLE_MASK2 FE6A 0100 1E6A
_CLALnTable FE6C 0100 1E6C
_CLAINV1 FF32 0100 1F32
_CLALnTableEnd FF32 0100 1F32

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Table 4-21. CLA Data ROM Tables (continued)

Start Address From CLA in Hex Start Address From CPU in Hex
_CLAINV2 FF34 0100 1F34
_CLAINV3 FF36 0100 1F36
_CLAINV4 FF38 0100 1F38
_CLAINV5 FF3A 0100 1F3A
_CLAINV6 FF3C 0100 1F3C
_CLAINV7 FF3E 0100 1F3E
_CLALOG10 FF40 0100 1F40
_CLAExpTable FF42 0100 1F42
_CLAExpTableEnd FFF4 0100 1FF4
CROM VERSION FFFA 0100 1FFA (2 16-bit words)
.word 0x0100 ; Boot ROM
Version v1.0
.word 0x0413 ; Month/Year:
(ex: 0x0109 = 1/09 = Jan 2009)

4.10.4 Boot Modes

The available boot modes supported on this device are detailed in this section. Each boot mode allows for
various options, providing configurations with different IOs to be used, depending on the application.
While each subsection gives details regarding the implementation of the native boot modes on the device, the
subsections do not address utilizing each boot mode for common system operations such as:
• Device Firmware Upgrade (DFU)
• Erasing the Flash memory
• Verifying the Flash memory
• Unlocking the security zones
• Running the embedded code from "main"
• Resetting the MCU
These operations and more are covered in the Serial Flash Programming of C2000™ Microcontrollers
Application Report.
4.10.4.1 Wait Boot Mode
The wait boot mode puts the CPU in a loop and does not branch to the user application code. The device can
enter wait boot mode either manually or because an error occurred during boot up. TI recommends using wait
boot when using a debugger to avoid any JTAG complications.
Actions resulting in entering wait boot mode:
• Wait boot is set by the user as the boot mode
• The boot mode is unrecognized and a debugger is connected to the device
• The emulation BOOCTRL key is not equal to 0xA5 or 0x5A
• An error occurs during emulation boot and the boot mode pins are decoded with a value not recognized as a
valid boot mode

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4.10.4.2 SCI Boot Mode

The SCI boot mode asynchronously transfers code from SCI-A to internal memory. This boot mode only
supports an incoming 8-bit data stream and follows the data flow as outlined in Example 4-1.

SCIRXDA
Control Host
Subsystem (Data and program
boot ROM SCITXDA source)

Figure 4-8. Overview of SCI Bootloader Operation

The device communicates with the external host by communication through the SCI-A peripheral. The autobaud
feature of the SCI port is used to lock baud rates with the host. For this reason the SCI loader is very flexible and
you can use a number of different baud rates to communicate with the device.
After each data transfer, the bootloader echoes back the 8-bit character received to the host. This allows the
host to check that each character was received by the bootloader.
At higher baud rates, the slew rate of the incoming data bits can be affected by transceiver and connector
performance. While normal serial communications can work well, this slew rate can limit reliable auto-baud
detection at higher baud rates (typically beyond 100kbaud) and cause the auto-baud lock feature to fail. To avoid
this, the following is recommended:
1. Achieve a baud-lock between the host and SCI bootloader using a lower baud rate.
2. Load the incoming application or custom loader at this lower baud rate.
3. The host can then handshake with the loaded application to set the SCI baud rate register to the desired
high baud rate.

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SCI_Boot

Enable the SCI-A clock Echo autobaud character

set the LSPCLK to /4

Enable the SCIA TX and RX pin Read KeyValue

functionality and pullups on
TX and RX

Valid No
Setup SCI-A for KeyValue Jump to Flash
1 stop, 8-bit character, (0x08AA)
no parity, use internal ?
SC clock, no loopback,
disable Rx/Tx interrupts
Yes

Read and discard 8

Disable SCI FIFOs reserved words

Prime SCI-A baud register Read EntryPoint address

Enable autobaud detection Read data in the standard

boot stream format

No Autobaud
lock
?

Return
Yes EntryPoint

Figure 4-9. Overview of SCI Boot Function

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4.10.4.3 SPI Boot Mode

The SPI loader expects an SPI-compatible 16-bit or 24-bit addressable serial EEPROM or serial Flash device to
be present on the SPI-A pins as indicated in Figure 4-10. The SPI bootloader supports an 8-bit data stream and
does not support a 16-bit data stream.

Serial SPI
EEPROM
SPIA_SIMO
DIN
Control SPIA_SOMI
DOUT
subsystem SPIA_CLK CLK
SPIA_STE CS

Figure 4-10. SPI Loader

The SPI boot ROM loader initializes the SPI module to interface to a serial SPI EEPROM or Flash. Devices
of this type include, but are not limited to, the Xicor X25320 (4Kx8) and Xicor X25256 (32Kx8) SPI serial SPI
EEPROMs and the Atmel AT25F1024A Serial Flash.
The SPI boot ROM loader initializes the SPI with the following settings: FIFO enabled, 8-bit character, internal
SPICLK master mode and talk mode, clock phase = 1, polarity = 0, using the slowest baud rate.
If the download is to be performed from an SPI port on another device, then that device must be setup to operate
in the slave mode and mimic a serial SPI EEPROM. Immediately after entering the SPI_Boot function, the pin
functions for the SPI pins are set to primary and the SPI is initialized. The initialization is done at the slowest
speed possible. Once the SPI is initialized and the key value read, you can specify a change in baud rate or
low-speed peripheral clock.
Table 4-22. SPI 8-Bit Data Stream
Byte Contents
1 LSB: AA (KeyValue for memory width = 8 bits)
2 MSB: 08h (KeyValue for memory width = 8 bits)
3 LSB: LOSPCP
4 MSB: SPIBRR
5 LSB: reserved for future use
6 MSB: reserved for future use
... ...
... Data for this section.
17 LSB: reserved for future use
18 MSB: reserved for future use
19 LSB: Upper half (MSW) of Entry point PC[23:16]
20 MSB: Upper half (MSW) of Entry point PC[31:24] (Note: Always 0x00)
21 LSB: Lower half (LSW) of Entry point PC[7:0]
22 MSB: Lower half (LSW) of Entry point PC[15:8]
... ....
... Data for this section.
... Blocks of data in the format size/destination address/data as shown in the generic
data stream description
... ...
... Data for this section.
n LSB: 00h
n+1 MSB: 00h - indicates the end of the source

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The data transfer is done in "burst" mode from the serial SPI EEPROM. The transfer is carried out entirely in
byte mode (SPI at 8 bits/character). A step-by-step description of the sequence follows:
1. The SPI-A port is initialized
2. The GPIO19 (SPISTE) pin is used as a chip-select for the serial SPI EEPROM or Flash
3. The SPI-A outputs a read command for the serial SPI EEPROM or Flash
4. The SPI-A sends the serial SPI EEPROM an address 0x0000; that is, the host requires that the EEPROM or
Flash must have the downloadable packet starting at address 0x0000 in the EEPROM or Flash. The loader
is compatible with both 16-bit addresses and 24-bit addresses.
5. The next word fetched must match the key value for an 8-bit data stream (0x08AA). The least significant
byte of this word is the byte read first and the most significant byte is the next byte fetched. This is true of
all word transfers on the SPI. If the key value does not match, then the load is aborted and the bootloader
jumps to Flash.
6. The next 2 bytes fetched can be used to change the value of the low speed peripheral clock register
(LOSPCP) and the SPI baud rate register (SPIBRR). The first byte read is the LOSPCP value and the
second byte read is the SPIBRR value. The next 7 words are reserved for future enhancements. The SPI
bootloader reads these 7 words and discards them.
7. The next two words makeup the 32-bit entry point address where execution can continue after the boot load
process is complete. This is typically the entry point for the program being downloaded through the SPI port.
8. Multiple blocks of code and data are then copied into memory from the external serial SPI EEPROM through
the SPI port. The blocks of code are organized in the standard data stream structure presented earlier. This
is done until a block size of 0x0000 is encountered. At that point in time the entry point address is returned to
the calling routine that then exits the bootloader and resumes execution at the address specified.

SPI_Boot

Enable the SPI-A clock

Set the LSPCLK to 4 Valid No
KeyValue Jump to Flash
(0x08AA)
?
Enable SPI_SIMO, SPI_SOMI
and SPI_CLK and enable
pullups. Configure SPI_STE Yes
pin as GPIO and drive low.
Read LOSPCP value Change LOSPCP

Set up SPI-A for

8-bit character,
Use internal SPI clock,
master mode
Use slowest baud rate (0x7F)
Relinquish SPI-A from reset

Read SPIBRR value Change SPIBRR

Set SPISTE pin high

Enable EEPROM
Send read command and Read and discard 7
start at EEPROM address reserved words
0x0000

Read EntryPoint Return

Read KeyValue address Call CopyData EntryPoint

Figure 4-11. Data Transfer From EEPROM Flow

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4.10.4.4 I2C Boot Mode

The I2C bootloader expects an 8-bit wide I2C-compatible EEPROM device to be present at address 0x50 on the
I2C-A bus as indicated in Figure 4-12. The EEPROM must adhere to conventional I2C EEPROM protocol, as
described in this section, with a 16-bit base address architecture.
SDA SCL

I2CA_SDA
Control
subsystem
I2CA_SCL
I2C
SDA EEPROM

SCL Slave Address

0x50

Figure 4-12. EEPROM Device at Address 0x50

If the download is to be performed from a device other than an EEPROM, then that device must be set up to
operate in the slave mode and mimic the I2C EEPROM. Immediately after entering the I2C boot function, the
GPIO pins are configured for I2C-A operation and the I2C is initialized. The following requirements must be met
when booting from the I2C module:
• The input frequency to the device must be in the appropriate range.
• The EEPROM must be at slave address 0x50.

The bit-period prescalers (I2CCLKH and I2CCLKL) are configured by the bootloader to run the I2C at a 50
percent duty cycle at 100kHz bit rate (standard I2C mode) when the system clock is 10MHz. These registers can
be modified after receiving the first few bytes from the EEPROM. This allows the communication to be increased
up to a 400kHz bit rate (fast I2C mode) during the remaining data reads.
Arbitration, bus busy, and slave signals are not checked. Therefore, no other master is allowed to control the bus
during this initialization phase. If the application requires another master during I2C boot mode, that master must
be configured to hold off sending any I2C messages until the application software signals that the application
software is past the bootloader portion of initialization.
The non-acknowledgment bit is checked only during the first message sent to initialize the EEPROM base
address. This is to make sure that an EEPROM is present at address 0x50 before continuing. If an EEPROM is
not present, the non-acknowledgment bit is not checked during the address phase of the data read messages
(I2C_Get Word). If a non-acknowledgment is received during the data read messages, the I2C bus hangs. Table
4-23 shows the 8-bit data stream used by the I2C.

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NACK Yes
I2C_Boot
received Jump to Flash
?
Enable I2CA_SDA and
I2CA_SCL pins No
Enable pullups on
I2CA_SDA and I2CA_SCL Read KeyValue

Enable I2C-A clock

Valid No
KeyValue Jump to Flash
(0x08AA)
Set slave address 0x50
?
I2C prescaler I2CPSC = or 0
Yes
100-kHz bit rate Put 12c-A in Reset
Read I2CPSC value Set I2CPSC value
Enable TX/RX FIFOs to Read I2CCLKH value Set I2CCLKH value
receive 2 bytes. Read 12CCLKL value Set I2CCLKL value
Bring I2C-A out of Reset

Place I2C in master

transmitter mode
Set EEPROM address
pointer to 0x0000 Read and discard 5
reserved words

Read EntryPoint
address

Read data in standard

boot stream format

Return
EntryPoint

Figure 4-13. Overview of I2C Boot Function

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Table 4-23. I2C 8-Bit Data Stream

Byte Contents
1 LSB: AA (KeyValue for memory width = 8 bits)
2 MSB: 08h (KeyValue for memory width = 8 bits)
3 LSB: I2CPSC[7:0]
4 reserved
5 LSB: I2CCLKH[7:0]
6 MSB: I2CCLKH[15:8]
7 LSB: I2CCLKL[7:0]
8 MSB: I2CCLKL[15:8]
... ...
... Data for this section.
...
17 LSB: Reserved for future use
18 MSB: Reserved for future use
19 LSB: Upper half of entry point PC
20 MSB: Upper half of entry point PC[22:16] (Note: Always 0x00)
21 LSB: Lower half of entry point PC[15:8]
22 MSB: Lower half of entry point PC[7:0]
... ...
... Data for this section.
...
Blocks of data in the format size/destination address/data as shown in the generic data stream description.
... ...
... Data for this section.
...
n LSB: 00h
n+1 MSB: 00h - indicates the end of the source

The I2C EEPROM protocol required by the I2C bootloader is shown in Figure 4-14 and Figure 4-15. The first
communication, which sets the EEPROM address pointer to 0x0000 and reads the KeyValue (0x08AA), is shown
in Figure 4-14. All subsequent reads are shown in Figure 4-15 and are read two bytes at a time.
RESTART

NO ACK
START

WRITE

READ

STOP
MSB

MSB

ACK
ACK

ACK

ACK
ACK
LSB

LSB

SDA LINE
1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 1 01 0 0 0 0 1 0

Device Address Address Device DATA BYTE 1 DATA BYTE 2

Address Pointer, MSB Pointer, LSB Address

Figure 4-14. Random Read

NO ACK
START

READ

STOP
ACK

ACK

SDA LINE
1 01 0 0 0 0 1 0

Device DATA BYTE n DATA BYTE n+1

Address

Figure 4-15. Sequential Read

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4.10.4.5 Parallel Boot Mode

The parallel general purpose I/O (GPIO) boot mode asynchronously transfers code from GPIO58-GPIO63,
GPIO64-GPIO65 to internal memory. Each value is 8 bits long and follows the same data flow as outlined in
Figure 4-16.
28x control − GPIO69
Host control − GPIO70 Host
boot ROM (data and program
8 source)

Data GP I/O port GPIO[63-58, 64, 65]

Figure 4-16. Overview of Parallel GPIO Bootloader Operation

The control subsystem communicates with the external host device by polling/driving the GPIO70 and GPIO69
lines. The handshake protocol shown in Figure 4-17 must be used to successfully transfer each word using
GPIO[63-58,64,65]. This protocol is very robust and allows for a slower or faster host to communicate with the
master subsystem.
Two consecutive 8-bit words are read to form a single 16-bit word. The most significant byte (MSB) is read first
followed by the least-significant byte (LSB). In this case, data is read from GPIO[63-58,64,65].
The 8-bit data stream is shown in Table 4-24.
Table 4-24. Parallel GPIO Boot 8-Bit Data Stream
Bytes GPIO[63:58,64,65] GPIO[63:58,64,65] Description
(Byte 1 of 2) (Byte 2 of 2)
1 2 AA 08 0x08AA (KeyValue for memory width = 16 bits)
3 4 00 00 8 reserved words (words 2 - 9)
... ... ... ... ...
17 18 00 00 Last reserved word
19 20 BB 00 Entry point PC[22:16]
21 22 DD CC Entry point PC[15:0] (PC = 0x00BB CCDD)
23 24 NN MM Block size of the first block of data to load = 0xMMNN words
25 26 BB AA Destination address of first block Addr[31:16]
27 28 DD CC Destination address of first block Addr[15:0] (Addr = 0xAABB CCDD)
29 30 BB AA First word of the first block in the source being loaded = 0xAABB
... ...
... Data for this section.
...
. BB AA Last word of the first block of the source being loaded = 0xAABB
. NN MM Block size of the 2nd block to load = 0xMMNN words
. BB AA Destination address of second block Addr[31:16]
. DD CC Destination address of second block Addr[15:0]
. BB AA First word of the second block in the source being loaded
. …
n n+1 BB AA Last word of the last block of the source being loaded
(More sections if required)
n+2 n+3 00 00 Block size of 0000h - indicates end of the source program

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The device first signals the host that the device is ready to begin data transfer by pulling the GPIO69 pin low.
The host load then initiates the data transfer by pulling the GPIO70 pin low. The complete protocol is shown in
Figure 4-17.
1 2 3 4 5 6

Host control
GPIO70

Device control
GPIO69

Figure 4-17. Parallel GPIO Bootloader Handshake Protocol

1. The device indicates the device is ready to start receiving data by pulling the GPIO69 pin low.
2. The bootloader waits until the host puts data on GPIO [63-58,64,65]. The host signals to the device that data
is ready by pulling the GPIO70 pin low.
3. The device reads the data and signals the host that the read is complete by pulling GPIO69 high.
4. The bootloader waits until the host acknowledges the device by pulling GPIO70 high.
5. The device again indicates the device is ready for more data by pulling the GPIO69 pin low.
This process is repeated for each data value to be sent.
Figure 4-18 shows an overview of the Parallel GPIO bootloader flow.

Parallel_Boot

Initialize GP I/O MUX Read and discard 8

and Dir registers reserved words
GPIO[63-58,64,65] = input
GPIO70 = input
GPIO69 = output
Enable pullups on Read EntryPoint
address
GPIO[63-58,64,65]

Call
CopyData

Valid
No KeyValue
Return Flash EntryPoint (0x08AA)
?
Return
Yes EntryPoint

Figure 4-18. Parallel GPIO Mode Overview

Figure 4-19 shows the transfer flow from the host side. The operating speed of the CPU and host are not critical
in this mode as the host waits for the device and the device waits for the host. In this manner, the protocol works
with both a host running faster and a host running slower than the device.

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Start transfer

No Device ready
(GPIO69=0)
?

Yes No Device ack

(GPIO69=1)
Load GPIO[63-58,64,65] with data ?

Yes
Signal that data
is ready Acknowledge device
(GPIO70=0) (GPIO70=1)

More Yes
data
?

No

End transfer

Figure 4-19. Parallel GPIO Mode - Host Transfer Flow

Figure 4-20 shows the flow used to read a single word of data from the parallel port.
• 8-bit data stream
The 8-bit routine, shown in Figure 4-20, discards the upper 8 bits of the first read from the port and treats
the lower 8 bits masked with GPIO65 in bit position 7 and GPIO64 in bit position 6 as the least-significant
byte (LSB) of the word to be fetched. The routine then performs a second read to fetch the most-significant
byte (MSB). The routine then combines the MSB and LSB into a single 16-bit value to be passed back to the
calling routine.

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Parallel_GetWordData A
8 bit

Signal host that device is ready Signal host that device

is ready to read MSB
(GPIO69 = 0) (GPIO69 = 0)

Data Data
ready No ready No
(GPIO70 = 0) (GPIO70 = 0)
? ?

Yes Yes

Read word of data

from GPIO[63-58,64,65] Read GPIO for LSB and
MSB of 16-bit data

Device ack read complete

(GPIO69 = 1)

Device ack read complete

(GPIO69 = 1)

Host
ack No
(GPIO70 = 1)
? Host
ack No
Yes (GPIO70 = 1)
?

Yes

WordData = MSB:LSB

A
Return WordData

Figure 4-20. 8-Bit Parallel GetWord Function

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4.10.4.6 CAN Boot Mode

The CAN bootloader asynchronously transfers code from CAN-A to internal memory. The host can be any CAN
node. The communication is first done with 11-bit standard identifiers (with a MSGID of 0x1) using two bytes per
data frame. The host can download a kernel to reconfigure the CAN if higher data throughput is desired.

28x

CAN bus
CAN
host

28x

Figure 4-21. Overview of CAN-A Bootloader Operation

The bit timing registers are programmed in such a way that a 50kbps bit rate is achieved with the 10MHz
INTOSC1 oscillator, a shown in Table 4-25.
Table 4-25. Bit-Rate Value for Internal Oscillators
OSCCLK SYSCLKOUT Bit Rate
10MHz 10MHz 50kbps

The SYSCLKOUT values shown are the reset values with the default PLL setting. The BRP and bit-time values
are hard-coded to 10 and 20, respectively.

Note
The CPU1 CAN boot loader uses INTOSC1 as the bit clock source and INTOSC2 as the system clock
source. The CPU2 CAN boot loader does not change either clock source, so CPU1 must configure the
clock sources before starting the CPU2 CAN boot loader.

Mailbox 1 is programmed with a standard MSGID of 0x1 for boot-loader communication. The CAN host can
transmit only 2 bytes at a time, LSB first and MSB next. For example, to transmit the word 0x08AA to the device,
transmit AA first, followed by 08. The program flow of the CAN bootloader is identical to the SCI bootloader. The
data sequence for the CAN bootloader is shown in Table 4-26.

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Table 4-26. CAN 8-Bit Data Stream

Bytes Byte 1 of 2 Byte 2 of 2 Description
1 2 AA 08 0x08AA (KeyValue for memory width = 16 bits)
3 4 00 00 reserved
5 6 00 00 reserved
7 8 00 00 reserved
9 10 00 00 reserved
11 12 00 00 reserved
13 14 00 00 reserved
15 16 00 00 reserved
17 18 00 00 reserved
19 20 BB AA Entry point PC[22:16]
21 22 DD CC Entry point PC[15:0] (PC = 0xAABB CCDD)
23 24 NN MM Block size of the first block of data to load = 0xMMNN words
25 26 BB AA Destination address of first block Addr[31:16]
27 28 DD CC Destination address of first block Addr[15:0] (Addr = 0xAABB CCDD)
29 30 BB AA First word of the first block in the source being loaded = 0xAABB
... ....
... Data for this section.
...
. BB AA Last word of the first block of the source being loaded = 0xAABB
. NN MM Block size of the 2nd block to load = 0xMMNN words
. BB AA Destination address of second block Addr[31:16]
. DD CC Destination address of second block Addr[15:0]
. BB AA First word of the second block in the source being loaded
. …
n n+1 BB AA Last word of the last block of the source being loaded
(More sections if required)
n+2 n+3 00 00 Block size of 0000h - indicates end of the source program

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4.10.4.7 USB Boot Mode

In USB boot mode, the device enumerates with vendor ID 0x1CBE and product ID 0x00FF. The device
descriptor and interface descriptor both show the class as 0xFF (vendor-specific), the subclass as 0x00, and
the protocol as 0x00. After enumeration, the device waits for data. Data can be sent using bulk OUT transfers
to endpoint 1. The data is interpreted as a series of 8-bit bytes in the standard data stream format described
in Section 4.10.5, shown here in Table 4-27. No reserved bytes are used. Once the data transfer is complete
(block size of 0x0000 sent), the device disconnects from the USB bus, allowing other software to make use of
the module if desired. Figure 4-22 illustrates the flow for USB boot mode.
USB_Boot

Host sends boot

loader data in the
Wait for standard stream
connection format via bulk OUT
transfers to
endpoint 1

Enumerate to host
PC with ID 1cbe:00ff Valid key
Jump to flash
(0x08AA)?

Host PC installs
drivers
MCU loads data into
RAM

MCU waits
for data MCU disconnects
from the USB bus

Return EntryPoint

Figure 4-22. USB Boot Flow

Implementing PC-side USB software is not trivial. It is recommended to use the TI-provided tools and drivers to
load data in USB boot mode. Hex and binary files for loader tools can be generated from COFF (.out) files using
the hex2000 tool. To produce a plain binary file in the boot loader format, use the following command line:
hex2000 -boot -b Program_to_Load.out -o Binary_Loader_Data.dat
For more information on hex2000, see the TMS320C28x Assembly Language Tools User's Guide.

Note
INTOSC2 must be enabled before invoking the USB boot loader. If INTOSC2 is not enabled, the
boot loader hangs. A debugger reset or SCC reset does not enable INTOSC2, if INTOSC2 has been
disabled by the application.

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Table 4-27. USB 8-Bit Data Stream

Bytes First Byte Second Byte Description
(LSB) (MSB)
1 2 AA 08 0x08AA (KeyValue for memory width = 16 bits)
3 4 00 00 reserved
5 6 00 00 reserved
7 8 00 00 reserved
9 10 00 00 reserved
11 12 00 00 reserved
13 14 00 00 reserved
15 16 00 00 reserved
17 18 00 00 reserved
19 20 BB AA Entry point PC[22:16]
21 22 DD CC Entry point PC[15:0] (PC = 0xAABB CCDD)
23 24 NN MM Block size of the first block of data to load = 0xMMNN words
25 26 BB AA Destination address of first block Addr[31:16]
27 28 DD CC Destination address of first block Addr[15:0] (Addr = 0xAABB CCDD)
29 30 BB AA First word of the first block in the source being loaded = 0xAABB
... ....
... Data for this section.
...
. BB AA Last word of the first block of the source being loaded = 0xAABB
. NN MM Block size of the 2nd block to load = 0xMMNN words
. BB AA Destination address of second block Addr[31:16]
. DD CC Destination address of second block Addr[15:0]
. BB AA First word of the second block in the source being loaded
. …
n n+1 BB AA Last word of the last block of the source being loaded
(More sections if required)
n+2 n+3 00 00 Block size of 0000h - indicates end of the source program

4.10.5 Boot Data Stream Structure

This section details the data transfer protocols or stream structures that allow boot data transfer between boot
ROM and host device. This data transfer protocol is compatible to the respective bootloaders on other C2000
devices.
4.10.5.1 Bootloader Data Stream Structure
Table 4-28 and Example 4-1 show the structure of the data stream incoming to the bootloader. The basic
structure is the same for all the bootloaders and is based on the C54x source data stream generated by
the C54x hex utility. The C28x hex utility (hex2000.exe) has been updated to support this structure. The
hex2000.exe utility is included with the C2000 code generation tools. All values in the data stream structure are
in hex.
The first 16-bit word in the data stream is known as the key value. The key value is used to indicate to the
bootloader the width of the incoming stream: 8 or 16 bits. Note that not all bootloaders accept both 8 and 16-bit
streams. Refer to the detailed information on each loader for the valid data stream width. For an 8-bit data
stream, the key value is 0x08AA and for a 16-bit stream the key value is 0x10AA. If a bootloader receives an
invalid key value, then the load is aborted.
The next eight words are used to initialize register values or otherwise enhance the bootloader by passing
values to it. If a bootloader does not use these values then they are reserved for future use and the bootloader

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simply reads the value and then discards it. Currently only the SPI and I2C and parallel bootloaders use these
words to initialize registers.
The tenth and eleventh words comprise the 22-bit entry point address. This address is used to initialize the PC
after the boot load is complete. This address is most likely the entry point of the program downloaded by the
bootloader.
The twelfth word in the data stream is the size of the first data block to be transferred. The size of the block is
defined as 8-bit data stream format. For example, to transfer a block of 20 8-bit data values from an 8-bit data
stream, the block size is 0x000A to indicate 10 16-bit words.
The next two words indicate to the loader the destination address of the block of data. Following the size and
address is the 16-bit words that makeup that block of data.
This pattern of block size/destination address repeats for each block of data to be transferred. Once all the
blocks have been transferred, a block size of 0x0000 signals to the loader that the transfer is complete. At this
point, the loader returns the entry point address to the calling routine that cleans up and exits. Execution then
continues at the entry point address as determined by the input data stream contents.
Table 4-28. LSB/MSB Loading Sequence in 8-Bit Data Stream
Byte Contents
LSB (First Byte of 2) MSB (Second Byte of 2)
1 2 LSB: AA (KeyValue for memory width = 8 bits) MSB: 08h (KeyValue for memory width = 8 bits)
3 4 LSB: Register initialization value or reserved MSB: Register initialization value or reserved
5 6 LSB: Register initialization value or reserved MSB: Register initialization value or reserved
7 8 LSB: Register initialization value or reserved MSB: Register initialization value or reserved
... ... ... ...
17 18 LSB: Register initialization value or reserved MSB: Register initialization value or reserved
19 20 LSB: Upper half of Entry point PC[23:16] MSB: Upper half of entry point PC[31:24] (Always 0x00)
21 22 LSB: Lower half of Entry point PC[7:0] MSB: Lower half of Entry point PC[15:8]
23 24 LSB: Block size in words of the first block to load. If the MSB: block size
block size is 0, this indicates the end of the source program.
Otherwise another block follows. For example, a block size of
0x000A indicates 10 words or 20 bytes in the block.
25 26 LSB: MSW destination address, first block Addr[23:16] MSB: MSW destination address, first block Addr[31:24]
27 28 LSB: LSW destination address, first block Addr[7:0] MSB: LSW destination address, first block Addr[15:8]
29 30 LSB: First word of the first block being loaded MSB: First word of the first block being loaded
... ... ... ...
. . LSB: Last word of the first block to load MSB: Last word of the first block to load
. . LSB: Block size of the second block MSB: Block size of the second block
. . LSB: MSW destination address, second block Addr[23:16] MSB: MSW destination address, second block Addr[31:24]
. . LSB: LSW destination address, second block Addr[7:0] MSB: LSW destination address, second block Addr[15:8]
. . LSB: First word of the second block being loaded MSB: First word of the second block being loaded
... ... ... ...
. . LSB: Last word of the second block MSB: Last word of the second block
. . LSB: Block size of the last block MSB: Block size of the last block
. . LSB: MSW of destination address of last block Addr[23:16] MSB: MSW destination address, last block Addr[31:24]
. . LSB: LSW destination address, last block Addr[7:0] MSB: LSW destination address, last block Addr[15:8]
. . LSB: First word of the last block being loaded MSB: First word of the last block being loaded
... ... ... ...
. . LSB: Last word of the last block MSB: Last word of the last block
n n+1 LSB: 00h MSB: 00h - indicates the end of the source

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Example 4-1. Data Stream Structure 8-bit

AA 08 ; 0x08AA 8-bit key value

00 00 00 00 ; 8 reserved words
00 00 00 00
00 00 00 00
00 00 00 00
3F 00 00 80 ; 0x003F8000 EntryAddr, starting point after boot load completes
05 00 ; 0x0005 - First block consists of 5 16-bit words
3F 00 10 90 ; 0x003F9010 - First block will be loaded starting at 0x3F9010
01 00 ; Data loaded = 0x0001 0x0002 0x0003 0x0004 0x0005
02 00
03 00
04 00
05 00
02 00 ; 0x0002 - 2nd block consists of 2 16-bit words
3F 00 00 80 ; 0x003F8000 - 2nd block will be loaded starting at 0x3F8000
00 77 ; Data loaded = 0x7700 0x7625
25 76
00 00 ; 0x0000 - Size of 0 indicates end of data stream
After load has completed the following memory values will have been initialized as follows:
Location Value
0x3F9010 0x0001
0x3F9011 0x0002
0x3F9012 0x0003
0x3F9013 0x0004
0x3F9014 0x0005
0x3F8000 0x7700
0x3F8001 0x7625
PC Begins execution at 0x3F8000

4.10.6 GPIO Assignments

This section details the GPIOs and boot options used for each boot mode set in the BMODE bit-field of the
BOOTCTRL register in OTP memory. Refer to Section 4.5 on the details of the BOOTCTRL fields.

Note
The peripheral bootloader GPIO configurations only apply to CPU1. CPU1 user application can
configure any available first instance of a peripheral (SCIA, SPIA, CANA, and so forth) GPIO for
CPU2 to use for a CPU2 particular bootloader.

Table 4-29. SCI Boot Options

Option BMODE Value SCITXDA GPIO SCIRXDA GPIO
0 (default) 0x01 GPIO84 GPIO85
1 0x81 GPIO29 GPIO28

Table 4-30. CAN Boot Options

Option BMODE Value CANTXA GPIO CANRXA GPIO
0 0x07 GPIO71 GPIO70
1 0x87 GPIO63 GPIO62

Table 4-31. I2C Boot Options

Option BMODE Value SDAA GPIO SCLA GPIO
0 0x05 GPIO91 GPIO92
1 0x85 GPIO32 GPIO33

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Table 4-32. USB Boot Options

Option BMODE Value USBDM GPIO USBDP GPIO
0 0x0C GPIO42 GPIO43

Table 4-33. RAM Boot Options

Option BMODE Value RAM Entry Point CPU Support
(Address)
0 0x0A 0x0000 0000 CPU1 and CPU2

Table 4-34. Flash Boot Options

Option BMODE Value Flash Entry Point Flash Sector CPU Support
(Address)
0 0x0B 0x0008 0000 Sector A CPU1 and CPU2

Table 4-35. Wait Boot Options

Option BMODE Value CPU Support
0 (default) 0x02 CPU1 and CPU2

Table 4-36. SPI Boot Options

Option BMODE Value SPISIMOA SPISOMIA SPICLKA SPISTEA
0 0x04 GPIO58 GPIO59 GPIO60 GPIO61
1 0x84 GPIO16 GPIO17 GPIO18 GPIO19

Table 4-37. Parallel Boot Options

Option BMODE Value D0-D7 GPIO DSP Control GPIO Host Control GPIO CPU Support
0 (default) 0x0 D0 - GPIO65 GPIO69 GPIO70 CPU1 and CPU2
D1 - GPIO64
D2 - GPIO58
D3 - GPIO59
D4 - GPIO60
D5 - GPIO61
D6 - GPIO62
D7 - GPIO63

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4.10.7 Secure ROM Function APIs

Within secure ROM of each core, functions are available to be called by the application to perform EXEONLY
Flash/RAM tasks in a secure manner.

Note
The application must disable interrupts before calling one of the EXEONLY function APIs.
If a vector fetch request is given by the CPU while the program counter (PC) is within the EXEONLY
function API code of the Secure ROM, a reset fires. The consequence of this is if an NMI or ITRAP
occurs while the PC is executing one of the EXEONLY API functions, the NMI/ITRAP cannot be
serviced because a reset is fired to that subsystem.

The safe copy code zone 1 and zone 2 functions allow EXEONLY Flash to be copied to EXEONLY RAM in
a secure manner. The source must be from EXEONLY Flash and the destination to EXEONLY RAM. There is
no support to copy EXEONLY ROM or EXEONLY RAM to RAM. Both Flash and RAM must be set to EXEONLY
and configured for the same zone. Additionally, the copy size must not cross over the Flash sector boundary.
Any violations of these requirements results in a failure status returned. Upon successful copy of the data, the
number of 16-bit words copied is returned.
Table 4-38. Safe Copy Code Function
CPU Function Prototype Function Parameters Function Return Value

Uint16 SafeCopyCodeZ1(Uint32 size, size : The number of 16-bit words to 0xXXXX : Returns the number of 16-
Uint16 *dst, Uint16 *src) copy bit words copied

dst : The destination memory address 0x0000 : Indicates one of the

CPU1, CPU2 in EXEONLY RAM following: Copy length is zero; Copy
size crosses over Flash sector
src : The source memory address in boundary; Flash and RAM do not
Uint16 SafeCopyCodeZ2(Uint32 size, EXEONLY Flash belong to the same zone; Flash and/or
Uint16 *dst, Uint16 *src) RAM are not set to EXEONLY; Error
occurred during data copy

The safe CRC calculation zone 1 and zone 2 functions allow a safety CRC check of EXEONLY memory in
a secure manner. The CRC length provided must be a value from 1 to 8 where 1 represents a CRC size of
32 16-bit words and 8 represents a CRC size of 4096 16-bit words. The source address specifies the starting
address for the CRC and the destination address is the location that the resulting CRC value is stored. The
source and destination memories must be configured for the same zone. Additionally, the CRC length must not
cross over the Flash sector or RAM block boundary. Any violations of these requirements results in a failure
status returned. Upon successful CRC, the number of 16-bit words CRC'd is returned.
Table 4-39. Safe CRC Calculation Function
CPU Function Prototype Function Parameters Function Return Value

len_id : A number from 1 to 8 that

Uint16 SafeCRCCalcZ1(Uint16 len_id, corresponds to length options of 32, 0xXXXX : Returns the number of 16-
Uint16 *dst, Uint16 *src) 64, 128, 256, 512, 1024, 2048, or bit words CRC'd
4096 16-bit words

dst : The destination memory address 0x0000 : Indicates one of the

CPU1, CPU2 for resulting CRC following: Invalid length option; Source
address is not modulo of length value;
src : The source memory address to Destination address is not within
Uint16 SafeCRCCalcZ2(Uint16 size, begin CRC calculation secure RAM; CRC size crosses over
Uint16 *dst, Uint16 *src) Flash sector or RAM block boundary;
The source and destination memory
do not belong to the same zone

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4.10.8 Boot IPC

For CPU1 and CPU2 to communicate during the boot process, a set of inter-processor communication (IPC)
registers are used. Each core polls for supported IPC commands that determine what specific action should be
performed. Actions include performing reads or writes to a particular memory address, branching to an address,
or calling a function. The supported commands differ depending on the core.
Prior to sending an IPC command to CPU2 boot ROM, the CPU1 application should perform the necessary
GPIO mux configurations for the peripheral IO pins. CPU2 peripheral loaders do not configure any of the GPIO
mux options and only configure the peripheral as required for the application load. Once configured, CPU1 can
then assign the peripheral to CPU2 through configuration of the CPU select register.
4.10.8.1 CPU1 IPC Commands
This section details the commands CPU1 boot ROM supports. These commands can be used by CPU2
applications to have CPU1 boot ROM to perform an action such as configure peripherals or IOs. To use these
IPC commands, CPU1 boot ROM must be in Wait Boot mode. Additionally, watchdog is disabled when using
IPC.

Note
All 32-bit operations are done in little-endian format (C28x is 16-bit addressable). Example: a 32-bit
IPC write is handled as:
• Data[15:0] is written in address
• Data [31:16] is written in address + 1

Table 4-40. C2TOC1IPC Commands Table

C2TOC1IPCFLG
IPCRECVADDR IPCRECVDATA IPCLOCALREPLY [31] = ?
IPCRECVCOM (CPU2 - R/W, (CPU2 - R/W, (CPU2 - R, C2TOC1IPCFLAG
Value (CPU2 - R/W, CPU1- R) CPU1- R) CPU1- R) CPU1 - R/W) [0] = 0 Description
0 C2C1_BROM_IPC_ NOT-USED NOT-USED Look at error codes 0x01 Illegal command
COMMAND_ILLEGAL table
1 C2C1_BROM_IPC_SET_ Address of the Data in Data read back 0x00 = Command *(address) |= data;
BITS_16 16-bit register C2TOC1IPCDAT from address after success
AW[15:0] write
2 C2C1_BROM_IPC_SET_ Address of the Data; Data read back Same as above *(address) |= data;
BITS_32 32-bit register from address after
write
3 C2C1_BROM_IPC_CLEAR_ Address of the Data in Data read back Same as above *(address) &=
BITS_16 16-bit register C2TOC1IPCDAT after write ~data;
AW[15:0]
4 C2C1_BROM_IPC_CLEAR_ Address of the Data Data read back Same as above *(address) &=
BITS_32 32-bit register after write ~data;
5 C2C1_BROM_IPC_DATA_ Address of the Data in Data read back Same as above *(address) = data;
WRITE_16 16-bit register MTOCIPCDATA from the address
W[15:0]
6 C2C1_BROM_IPC_DATA_ Address of the Data Same as above Same as above *(address) = data;
WRITE_32 32-bit register
7 C2C1_BROM_IPC_DATA_ Address of the --NOT_USED-- Data in Same as above C2TOC1IPCDATA
READ_16 16-bit register C2TOC1IPCDATA R[15:0] =
R[15:0] *(address);
Only 16 bit read
from address
8 C2C1_BROM_IPC_DATA_ Address of the Same as above 32-bit data Same as above C2TOC1IPCDATA
READ_32 32-bit register R[31:0] =
*(address);
32 bits read from
address

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Table 4-40. C2TOC1IPC Commands Table (continued)

C2TOC1IPCFLG
IPCRECVADDR IPCRECVDATA IPCLOCALREPLY [31] = ?
IPCRECVCOM (CPU2 - R/W, (CPU2 - R/W, (CPU2 - R, C2TOC1IPCFLAG
Value (CPU2 - R/W, CPU1- R) CPU1- R) CPU1- R) CPU1 - R/W) [0] = 0 Description
9 C2C1_BROM_IPC_SET_ Address of the Data in Data read back 0x00 = Command EALLOW;
BITS_ PROTECTED_16 16-bit register C2TOC1IPCDAT from address after success *(address) |= data;
AW[15:0] write EDIS;
10 C2C1_BROM_IPC_SET_ Address of the Data; Data read back Same as above EALLOW;
BITS_ PROTECTED_32 32-bit register from address after *(address) |= data;
write EDIS;
11 C2C1_BROM_IPC_CLEAR_ Address of the Data in Data read back Same as above EALLOW;
BITS_ PROTECTED_16 16-bit register C2TOC1IPCDAT after write *(address) &=
AW[15:0] ~data;
EDIS;
12 C2C1_BROM_IPC_CLEAR_ Address of the Data Data read back Same as above EALLOW;
BITS_ PROTECTED_32 32-bit register after write *(address) &=
~data;
EDIS;
13 C2C1_BROM_IPC_DATA_ Address of the Data in Data read back Same as above EALLOW;
WRITE_ PROTECTED_16 16-bit register C2TOC1IPCDAT from the address *(address) &=
AW[15:0] ~data;
EDIS;
14 C2C1_BROM_IPC_DATA_ Address of the Data Same as above Same as above EALLOW;
WRITE_ PROTECTED_32 32-bit register *(address) &=
~data;
EDIS;
15 C2C1_BROM_IPC_DATA_ Address of the --NOT_USED-- Data in Same as above EALLOW;
READ_ PROTECTED_16 32-bit register C2TOC1IPCDATA C2TOC1IPCDATA
R[15:0] R[15:0] =
*(address);
EDIS;
Only 16 bit read
from address
16 C2C1_BROM_IPC_DATA_ Address of the Data Same as above Same as above EALLOW;
READ_ PROTECTED_32 32-bit register C2TOC1IPCDATA
R[31:0] =
*(address);
EDIS;
32 bits read from
address

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4.10.8.2 CPU2 IPC Commands

This section details the commands that CPU2 boot ROM supports. These commands can be used by CPU1
applications to have CPU2 perform a specific action. To use these IPC commands, CPU2 boot ROM must be in
Wait Boot mode.
Table 4-41. C1TOC2IPC Commands Table
C1TOC2IPCFLG[31]
IPCRECVADDR IPCRECVDATA IPCLOCALREPLY =?
IPCRECVCOM (CPU1 - R/W, (CPU1 - R/W, (CPU1 - R, C1TOC2IPCFLAG[0]
Value (CPU1 - R/W, CPU2 R) BCPU2- R) CPU2- R) CPU2 - R/W) =0 Description
0 C1C2_BROM_IPC_ NOT-USED NOT-USED Look at error 0x01 Illegal command
COMMAND_ILLEGAL codes table
1 C1C2_BROM_IPC_SET_ Address of the Data in Data read back 0x00 = Command *(address) |= data;
BITS_16 16-bit register C1TOC2IPCDATA from address after success
W[15:0] write
2 C1C2_BROM_IPC_SET_ Address of the Data; Data read back Same as above *(address) |= data;
BITS_32 32-bit register from address after
write
3 C1C2_BROM_IPC_CLEAR_ Address of the Data in Data read back Same as above *(address) &=
BITS_16 16-bit register C1TOC2IPCDATA after write ~data;
W[15:0]
4 C1C2_BROM_IPC_CLEAR_ Address of the Data Data read back Same as above *(address) &=
BITS_32 32-bit register after write ~data;
5 C1C2_BROM_IPC_DATA_ Address of the Data in Data read back Same as above *(address) = data;
WRITE_16 16-bit register MTOCIPCDATA from the address
W[15:0]
6 C1C2_BROM_IPC_DATA_ Address of the Data Same as above Same as above *(address) = data;
WRITE_32 32-bit register
7 C1C2_BROM_IPC_DATA_ Address of the NOT-USED Data in Same as above C1TOC2IPCDATA
READ_16 16-bit register C1TOC2IPCDATA R[15:0] =
R[15:0] *(address);
16 bits read from
address
8 C1C2_BROM_IPC_DATA_ Address of the Same as above 32 bit data Same as above C1TOC2IPCDATA
READ_32 32-bit register R[31:0] =
*(address);
32 bits read from
address
9 C1C2_BROM_IPC_SET_ Address of the Data in Data read back 0x00 = Command EALLOW;
BITS_ PROTECTED_16 16-bit register C1TOC2IPCDATA from address after success *(address) |= data;
W[15:0] write EDIS;
10 C1C2_BROM_IPC_SET_ Address of the Data; Data read back Same as above EALLOW;
BITS_ PROTECTED_32 32-bit register from address after *(address) |= data;
write EDIS;
11 C1C2_BROM_IPC_CLEAR_ Address of the Data in Data read back Same as above EALLOW;
BITS_ PROTECTED_16 16-bit register C1TOC2IPCDATA after write *(address) &=
W[15:0] ~data;
EDIS;
12 C1C2_BROM_IPC_CLEAR_ Address of the Data Data read back Same as above EALLOW;
BITS_ PROTECTED_32 32-bit register after write *(address) &=
~data;
EDIS;
13 C1C2_BROM_IPC_DATA_ Address of the Data in Data read back Same as above EALLOW;
WRITE_ PROTECTED_16 16-bit register C1TOC2IPCDATA from the address *(address) = data;
W[15:0] EDIS;
14 C1C2_BROM_IPC_DATA_ Address of the Data Same as above Same as above EALLOW;
WRITE_ PROTECTED_32 32-bit register *(address) = data;
EDIS;

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Table 4-41. C1TOC2IPC Commands Table (continued)

C1TOC2IPCFLG[31]
IPCRECVADDR IPCRECVDATA IPCLOCALREPLY =?
IPCRECVCOM (CPU1 - R/W, (CPU1 - R/W, (CPU1 - R, C1TOC2IPCFLAG[0]
Value (CPU1 - R/W, CPU2 R) BCPU2- R) CPU2- R) CPU2 - R/W) =0 Description
15 C1C2_BROM_IPC_DATA_ Address of the NOT-USED Data in Same as above EALLOW;
READ_ PROTECTED_16 16-bit register C1TOC2IPCDATA C1TOC2IPCDATA
R[15:0] R[15:0] =
*(address);
16 bits read from
address
16 C1C2_BROM_IPC_DATA_ Address of the Same as above 32 bit data Same as above EALLOW;
READ_ PROTECTED_32 32-bit register C1TOC2IPCDATA
R[31:0] =
*(address);
EDIS;
32 bits read from
address
17 C1C2_BROM_IPC_ Address where _NOT- NOT- Same as above C2-BootROM
BRANCH_CALL to branch to USED_BY_BOOT USED_BY_BOOT jumps to the
ROM ROM address in ADDR
(code at the (code at the register and starts
branch can use branch can use executing the code
this though) this though) from that address.
PIE is enabled
when this branch
occurs, it is up to
the application to
disable and reload
PIE interrupt
handlers if it wants
to.
18 C1C2_BROM_IPC_ Address of the Parameter for the Result of function Same as above C2-BootROM
FUNCTION_CALL function function call call (return value if jumps to the
any from function) address in ADDR
register and starts
executing the code
from that address;
Data in DATAW
register can be
used as parameter
to the function
call. C-BootROM
returns back to
where it was
after servicing the
function call.
Function call is
performed from
inside the interrupt
service routine on
Aria so user has to
keep this in mind.

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Table 4-41. C1TOC2IPC Commands Table (continued)

C1TOC2IPCFLG[31]
IPCRECVADDR IPCRECVDATA IPCLOCALREPLY =?
IPCRECVCOM (CPU1 - R/W, (CPU1 - R/W, (CPU1 - R, C1TOC2IPCFLAG[0]
Value (CPU1 - R/W, CPU2 R) BCPU2- R) CPU2- R) CPU2 - R/W) =0 Description
19 C1C2_BROM_IPC_ NOT-USED NOT-USED NOT-USED Same as above Execute loaders
EXECUTE_ as per requested
BOOTMODE_CMD value in
C1TOC2BOOT
MODE register.
• C1TOC2BOOTMODE =
0xA,
C1C2_BROM_
BOOTMODE_
BOOT_FROM_RAM

• C1TOC2BOOTMODE =
0xB,
C1C2_BROM_
BOOTMODE_
BOOT_FROM_FLASH

• C1TOC2BOOTMODE =
0x1,
C1C2_BROM_
BOOTMODE_
BOOT_FROM_SCI

• C1TOC2BOOTMODE =
0x4,
C1C2_BROM_
BOOTMODE_
BOOT_FROM_SPI

• C1TOC2BOOTMODE =
0x5,
C1C2_BROM_
BOOTMODE_
BOOT_FROM_I2C

• C1TOC2BOOTMODE =
0x0,
C1C2_BROM_
BOOTMODE_
BOOT_FROM_
PARALLEL

• C1TOC2BOOTMODE =
0x7,
C1C2_BROM_v
BOOTMODE_
BOOT_FROM_CAN

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4.10.8.3 CPU2 IPC Error Commands

This section details the commands CPU2 boot ROM supports. These commands can be used by CPU1
applications to have CPU2 perform a specific action. To use these IPC commands, CPU2 boot ROM must
be in Wait Boot mode.
Table 4-42. CPU2 Error Command Values
Error Value Description Note
0x0000 0000 Invalid Command Value Default value when starting boot
0xFFFF FFFE CPU2 has got an ITRAP Address where ITRAP occurred is placed in IPCADDR
register
0xFFFF FFFD CPU2 got a spurious PIE interrupt Interrupt number placed in IPCDATAW register
0xFFFF FFFC CPU2 got a PIE vector mismatch error -
0xFFFF FFFB CPU2 got an uncorrectable Flash error -
0xFFFF FFFA CPU2 got an uncorrectable RAM error -

4.10.9 Clock Initializations

During boot up, the boot ROM initializes the device clocking, depending upon the reset source, to assist in
faster boot time response. Clock configurations are performed by the boot ROM code only for POR, XRS, and
HIBERNATE reset types. For all other resets, the boot ROM starts executing with the clocks that were already
set up before reset.
Only CPU1 performs the clock configuration for the device during boot up.
Table 4-43. Boot Clock Sources
Source Frequency Description
INTOSC2 10MHz Default clock source.
INTOSC1 10MHz Set as clock source, if missing clock is detected at power up or right
after device reset.

Table 4-44. Clock State After Boot ROM

Reset Source Clock State
POR/XRS/HIBERNATE Bypassed PLL.
PLL multiplier is set to 0x0
Clock divider is set to /1.
All other Resets Maintain clocks setup before device reset.

Note
If the PLL is used during the boot process, the PLL is bypassed by the boot ROM code before
branching to the user application.

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4.10.10 Wait State Configuration

This section details the ROM memory wait state configurations. By default, the CPU1 and CPU2 ROM memory
on this device is not zero-wait state; the ROM memory is 1-wait state with prefetch disabled. ROM does support
prefetch enable and disable configurations to provide better execution speeds at varying clock frequencies.
Configuring the wait state enables user applications to adjust for when performing callbacks into ROM or secure
copy code (SCC).
Table 4-45. ROM Wait States
Wait State Disable Bit Pre-Fetch Enable Bit C28x ROM Configuration
ROMWAITSTATE Register ROMPREFETCH Register
(Bit 0 – 0x5F540) (Bit 0 – 0x5E608)
0 0 • Wait state enabled
• Prefetch disabled
• Maximum Frequency: 200MHz

0 1 • Wait state enabled

• Prefetch enabled
• Maximum Frequency: 180MHz

1 Don’t Care • 0 Wait state

• Prefetch disabled
• Maximum Frequency: 150MHz

4.10.11 Boot Status information

Boot ROM keeps a record of the different events that can occur during boot ROM execution. This is because
NMI and other exceptions are enabled by default in the device, and must be handled accordingly. Boot ROM
stores the boot status information in a RAM location so that the user application can look at this boot status and
take the necessary actions per the application’s needs to handle these events.
4.10.11.1 CPU1 Booting Status
This section details the boot status RAM location and the bit field definitions for CPU1. When the specific bit field
is set, the described event or action has occurred.
Table 4-46. CPU1 Boot Status Address
Description Address
CPU1 Boot ROM Status 0x0000 002C

Table 4-47. CPU1 Boot Status Bit Fields

Bit Description
31 CPU1 Boot ROM has finished running
30 Boot ROM detected a missing clock NMI
29 Boot ROM detected a RAM bit error NMI
28 Boot ROM detected a Flash bit error NMI
27 Boot ROM detected CPU1 HWBIST error NMI
26 Boot ROM detected CPU2 HWBIST error NMI
25 Boot ROM detected PIE vector error NMI
22 Boot ROM detected CPU2 watchdog reset
21 Boot ROM detected CPU2 NMI watchdog reset
20 Boot ROM detected OVF NMI
19 Boot ROM detected a PIE mismatch
18 Boot ROM detected CPU1 to CPU2 branch

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Table 4-47. CPU1 Boot Status Bit Fields (continued)

Bit Description
17 Boot ROM detected an ITRAP
15 Boot ROM handled POR
14 Boot ROM handled XRS
13 Boot ROM handled HWBIST reset
12 Boot ROM handled hibernate reset
11 Boot ROM handled all the resets
10 DCSM initialization has completed
9 Flash boot has started
8 CPU1 Boot ROM has started running

4.10.11.2 CPU1 Boot Mode Status

This section details the boot mode that is determined during CPU1 boot.
Table 4-48. CPU1 Boot Mode Status Address
Description Address
CPU1 Boot Mode Address 0x0000 0038

Table 4-49. CPU1 Boot Mode Status Values

Boot Mode Value
Parallel Boot 0x0
SCI Boot 0x1
SCI Boot (ALT) 0x81
Wait Boot 0x2
Get Boot 0x3
SPI Boot 0x4
SPI Boot (ALT) 0x84
I2C Boot 0x5
I2C Boot (ALT) 0x85
CAN Boot 0x7
CAN Boot (ALT) 0x87
RAM Boot 0xA
Flash Boot 0xB
USB Boot 0xC
USB Boot (ALT) 0x8C

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4.10.11.3 CPU2 Booting Status

This section details the boot status bit field definitions for CPU2. When the specific bit field is set, the described
event or action has occurred. These status bits can be read from the C2TOC1BOOTSTS register.
Table 4-50. CPU2 Boot Status Address
Description Address
CPU2 Boot ROM Status 0x0000 0002

Table 4-51. CPU2 Boot Status Bit Fields

Bit Description
31 CPU2 Boot ROM has finished running
30 Boot ROM detected a missing clock NMI
29 Boot ROM detected a RAM bit error NMI
28 Boot ROM detected a Flash bit error NMI
27 Boot ROM detected CPU1 HWBIST error NMI
26 Boot ROM detected CPU2 HWBIST error NMI
25 Boot ROM detected PIE vector error NMI
22 Boot ROM detected CPU2 watchdog reset
21 Boot ROM detected CPU2 NMI watchdog reset
20 Boot ROM detected OVF NMI
19 Boot ROM detected a PIE mismatch
18 Boot ROM detected CPU1 to CPU2 branch
17 Boot ROM detected an ITRAP
11 Boot ROM handled all the resets
10 DCSM initialization has completed
9 Flash boot has started
8 CPU2 Boot ROM has started running
3-0 0 – Invalid Status. CPU2 hasn’t set a valid status yet
1 – CPU2 Boot ROM has started running
2 – CPU2 Boot ROM has completed and is ready for IPC commands
3 – CPU2 ACKs the boot command in C1TOC2BOOTMODE register
4 – CPU2 doesn’t support the command in C1TOC2BOOTMODE register
5 – CPU2 NAKs the boot command in C1TOC2BOOTMODE register

4.10.11.4 CPU1 IPC NAK Status

Table 4-52 details the NAK status information for CPU1, if boot ROM IPC command support is enabled. These
NAK status bits are returned by CPU1 in the C2TOC1IPCDATAR[11:0] register.
Table 4-52. CPU1 IPC NAK Status Bit Fields
Bit Description
3-0 0 – Invalid Value or value isn’t set
1 – Command not supported
2 – Command not set correctly
3 – CPU is trying to send a second command before the first one is complete
4 – Command execution resulted in an error
5 – Command cannot be executed in the current state of the boot ROM

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4.10.11.5 CPU2 IPC NAK Status

Table 4-53 details the NAK status information for CPU2, if boot ROM IPC command support is enabled. These
NAK status bits are returned by CPU1 in the C1TOC2IPCDATAR[11:0] register.
Table 4-53. CPU2 IPC NAK Status Bit Fields
Bit Description
3-0 0 – Invalid Value or value isn’t set
1 – Command not supported
2 – Command not set correctly
3 – CPU1 is trying to send a second command before the first one is complete
4 – Command execution resulted in an error
5 – Command cannot be executed in the current state of the boot ROM

4.10.12 ROM Version

The ROM revision and release date information is stored at the ROM locations specified in Table 4-54.
Table 4-54. Boot ROM Version Information for CPU1 and CPU2
Start Address End Address Contents
0x003F FF7A 0x003F FF7A Revision Number
0x003F FF7B 0x003F FF7B Revision Date

Interpreting the contents:

• Reading a revision value of 0x100 represents version 1.0.
• Reading a revision date value of 0x0715 represents 07/15 or July 2015.

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www.ti.com Direct Memory Access (DMA)

Chapter 5
Direct Memory Access (DMA)

The direct memory access (DMA) module provides a hardware method of transferring data between peripherals
and memory without intervention from the CPU; thereby, freeing up bandwidth for other system functions.
Additionally, the DMA has the capability to orthogonally rearrange the data as the data is transferred as well as
“ping-pong” data between buffers. These features are useful for structuring data into blocks for CPU processing.

5.1 Introduction...............................................................................................................................................................664
5.2 Architecture.............................................................................................................................................................. 666
5.3 Address Pointer and Transfer Control....................................................................................................................671
5.4 Pipeline Timing and Throughput.............................................................................................................................677
5.5 CPU and CLA Arbitration.........................................................................................................................................678
5.6 Channel Priority........................................................................................................................................................679
5.7 Overrun Detection Feature...................................................................................................................................... 680
5.8 Software.................................................................................................................................................................... 681
5.9 DMA Registers.......................................................................................................................................................... 682

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5.1 Introduction
The strength of a controller is not measured purely in processor speed, but in total system capabilities. As a
part of the equation, any time the CPU bandwidth for a given function can be reduced, the greater the system
capabilities. Many times applications spend a significant amount of the bandwidth moving data, whether moving
data from off-chip memory to on-chip memory, from a peripheral such as an analog-to-digital converter (ADC)
to RAM, or from one peripheral to another. Furthermore, many times this data comes in a format that is not
conducive to the optimum processing powers of the CPU. The DMA module described in this chapter has the
ability to free up CPU bandwidth and rearrange the data into a pattern for more streamlined processing.
The DMA module is an event-based machine, meaning the DMA module requires a peripheral or software
trigger to start a DMA transfer. Although the DMA module can be made into a periodic time-driven machine
by configuring a timer as the DMA trigger source, there is no mechanism within the module to start memory
transfers periodically. The DMA module has six independent DMA channels that can be configured separately
and each channel contains an independent PIE interrupt to let the CPU know when a DMA transfer has either
started or completed. Five of the six channels are exactly the same, while Channel 1 has the ability to be
configured at a higher priority than the others. At the heart of the DMA is a state machine and tightly coupled
address control logic. This address control logic allows for rearrangement of the block of data during the transfer
as well as the process of ping-ponging data between buffers. Each of these features is discussed in detail in this
chapter.
5.1.1 Features
DMA features include:
• Six channels with independent PIE interrupts
• Each DMA channel can be triggered from multiple peripheral trigger sources independently
• Word Size: 16-bit or 32-bit (SPI limited to 16-bit)
• Throughput: 3 cycles/word without arbitration

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5.1.2 Block Diagram

Figure 5-1 shows a device-level block diagram of the DMA.
ADC ADC CPU1 CPU1 Global Shared MSG RAM MSG RAM
WRAPPER RESULTS XINT TIMER 16x 4Kx16 1Kx16 1Kx16
(4) (4) (5) (3) GS0-15 RAMs CPU2 to CPU1 CPU1 to CPU2

C28x CPU1 Bus

CPU1.DMA Bus

TINT (0-2)

DMA_CHx (1-6)
XINT (1-5) DMA Trigger
Source Selection
ADC INT (A-D) (1-4), EVT (A-D) DMACHSRCSEL1.CHx DMA C28x
SDxFLTy (x = 1 to 2, y = 1 to 4) DMACHSRCSEL2.CHx CPU1 CPU1
SOCA (1-12), SOCB (1-12) CHx.MODE.PERINTSEL
MXEVT (A-B), MREVT (A-B) (x = 1 to 6) PIE
SPITX (A-C), SPIRX (A-C)

DMA Trigger

DMA_CHx (1-6)
Source Selection

DMACHSRCSEL1.CHx DMA C28x

DMACHSRCSEL2.CHx CPU2 CPU2
XINT (1-5) CHx.MODE.PERINTSEL
(x = 1 to 6)
TINT (0-2) PIE

CPU2.DMA Bus
C28x CPU2 Bus

DMA Trigger Source

CMPSS

CPU2 CPU2
eQEP
eCAP

CPU and DMA Data Path

DAC

SDFM EPWM McBSP SPI

(8) EMIF1 XINT TIMER
(12) (2) (3)
(5) (3)

Figure 5-1. DMA Block Diagram

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5.2 Architecture

5.2.1 Common Peripheral Architecture

There are two CPU subsystems; the CPU1 subsystem and CPU2 subsystem, with each containing a CLA and
a DMA. The architecture allows several peripherals to be common between the two subsystems. Based on
application need, these common peripherals can be attached to one of the two subsystems. Figure 5-2 shows
how the CPUs and subsystems can be connected to the peripherals on peripheral frames 1 and 2. The clock,
clock-enable, and reset muxing for the common peripherals are described in detail in other sections of this
document.
Refer to Section 5.5 for more details on the arbitration scheme for all masters.
CPU1 SYSCLK
CPU1 SYSRSn
CPU1.PCLKRx
CPU1
Arbiter CPU1 Peripheral Frame 1
CPU1.CLA1

CPU1.DMA

CPU1.SECMSEL CPU2 SYSCLK

CPU2 SYSRSn
CPU2.PCLKRx
CPU2

CPU2.CLA1 Arbiter CPU2 Peripheral Frame 1

CPU2.DMA
CPUSELx.PERy
CPU2.SECMSEL

ePWM
SDFM CMPSS eQEP eCAP DAC
HRPWM

Do not have integrated DMA trigger capability

CPU1 SYSCLK
CPU1 SYSRSn
CPU1.PCLKRx
CPU1
Arbiter CPU1 Peripheral Frame 2
CPU1.CLA1

CPU1.DMA

CPU1.SECMSEL CPU2 SYSCLK

CPU2 SYSRSn
CPU2.PCLKRx
CPU2

CPU2.CLA1 Arbiter CPU2 Peripheral Frame 2

CPU2.DMA
CPUSELx.PERy
CPU2.SECMSEL

SPI McBSP
uPP DMA Access is not supported
A/B/C A/B

Figure 5-2. Common Peripheral Architecture

Note
If CPU and DMA make an access to the same peripheral frame in the same cycle, the DMA has
priority and the CPU is stalled.

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A CPUSEL bit associated with each peripheral defines whether the peripheral belongs to the CPU1 or CPU2
subsystem. If a peripheral belongs to a CPU subsystem, the peripheral can be accessed by the CPU and
one of the secondary masters (DMA or CLA1). Refer to CPUSELx register definition for more details. The
secondary master is statically selected using the SECMSEL register mapped to the respective CPU. Refer to
CPUx.SECMSEL register definition for more details. If a secondary master is not selected, all writes from that
master are ignored and all reads return 0x0 to any of the peripherals.
Similarly, if a peripheral does not belong to a CPU subsystem (as defined by the associated CPUSEL bit), all
writes to that peripheral are ignored and all reads to that peripheral return 0x0 from any of the masters belonging
to the unselected CPU subsystem. Note that since the arbiter has no knowledge regarding the ownership of
individual peripherals (as can be seen from Figure 5-2), arbitration still happens even if the C28x or the selected
secondary master tries to access a peripheral that does not belong to the CPU subsystem. See Section 5.5 for
more information.
5.2.2 Peripheral Interrupt Event Trigger Sources
Each DMA Channel can be configured to trigger by software and other peripheral triggers events.
DMACHSRCSELx register can be used to configure DMA Trigger sources for each DMA channel.
CHx.MODE.PERINTSEL register bit field can be set to channel number (CHx.MODE.PERINTSEL = x) as shown
in Figure 5-3. Included in these DMA Trigger sources are five external interrupt signals that can be connected to
most of the general-purpose input/output (GPIO) pins on the device. This adds significant flexibility to the event
trigger capabilities. Upon receipt of a peripheral interrupt event signal, the DMA automatically sends a clear
signal to the interrupt source so that subsequent interrupt events occur.

Note
To use the system-level DMA Trigger source selection, the DMA internal trigger source selection
configuration for each channel can be done using the DMACHSRCSELx register and the
CHx.MODE.PERINTSEL register. See Table 5-1 or the DMACHSRCSELx register definition for a
complete list of DMA trigger sources.

Regardless of the value of the MODE.CHx[PERINTSEL] bit field, software can always force a trigger by using
the CONTROL.CHx[PERINTFRC] bit. Likewise, software can always clear a pending DMA trigger using the
CONTROL.CHx[PERINTCLR] bit.
Once a particular peripheral trigger event sets a channel’s PERINTFLG bit, the bit remains pending until the
priority logic of the state machine starts the burst transfer for that channel. Once the burst transfer starts, the
flag is cleared. If a new peripheral trigger event is generated while a burst is in progress, the burst completes
before responding to the new peripheral trigger event (after proper prioritization). If a third peripheral trigger
event occurs before the pending event is serviced, an error flag is set in the CONTROL.CHx[OVRFLG] bit. If a
peripheral trigger event occurs at the same time as the latched flag is being cleared, the trigger event has priority
and the PERINTFLG remains set.
Figure 5-4 shows a diagram of the trigger select circuit.
Table 5-1 shows the peripheral trigger source options that are available for each channel.

CAUTION
See the Device Errata "ADC:DMA Read of Stale Result" Advisory regarding the potential for the
DMA to read the ADC result registers before the result is ready

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DMA
DMACHSRCSELx.CH1 CH1.MODE.PERINTSEL[4:0] = 1
256 X 1
Mux ‘1’ 0
1
All DMA Trigger
Sources 2

6
Trigger Source for CH1
7
(Active Low)

DMACHSRCSELx.CH2 31

256 X 1
Mux
CH2.MODE.PERINTSEL[4:0] = 2

0
1

Trigger Source for CH2

6 (Active Low)
7

31

DMACHSRCSELx.CH6
256 X 1
Mux

CH6.MODE.PERINTSEL[4:0] = 6

0
1

Trigger Source for CH6

6
(Active Low)
7

31

Figure 5-3. DMA Trigger Architecture

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DMA Trigger event clears PERINTFLG bit

PERINTSEL

Clear
PERINTCLR
Latch DMA Trigger Event
(DMACHSRCSELx) Peripheral DMA Trigger

Set MODE.CHx.PERINTE
Software Trigger
[PERINTFRC = 1]

PERINTFLG gets set at this point

Note: See Figure 5-3.

Figure 5-4. Peripheral Interrupt Trigger Input Diagram

Table 5-1. DMA Trigger Source Options

Select Index Trigger Source
0 DMA_SOFTWARE_TRIGGER
1 ADCAINT1_DMA
2 ADCAINT2_DMA
3 ADCAINT3_DMA
4 ADCAINT4_DMA
5 ADCAEVT
6 ADCBINT1_DMA
7 ADCBINT2_DMA
8 ADCBINT3_DMA
9 ADCBINT4_DMA
10 ADCBEVT
11 ADCCINT1_DMA
12 ADCCINT2_DMA
13 ADCCINT3_DMA
14 ADCCINT4_DMA
15 ADCCEVT
16 ADCDINT1_DMA
17 ADCDINT2_DMA
18 ADCDINT3_DMA
19 ADCDINT4_DMA
20 ADCDEVT
21-28 Reserved
29 XINT1
30 XINT2
31 XINT3
32 XINT4
33 XINT5
34-35 Reserved
36 EPWM1_SOCA
37 EPWM1_SOCB
38 EPWM2_SOCA

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Table 5-1. DMA Trigger Source Options (continued)

Select Index Trigger Source
39 EPWM2_SOCB
40 EPWM3_SOCA
41 EPWM3_SOCB
42 EPWM4_SOCA
43 EPWM4_SOCB
44 EPWM5_SOCA
45 EPWM5_SOCB
46 EPWM6_SOCA
47 EPWM6_SOCB
48 EPWM7_SOCA
49 EPWM7_SOCB
50 EPWM8_SOCA
51 EPWM8_SOCB
52 EPWM9_SOCA
53 EPWM9_SOCB
54 EPWM10_SOCA
55 EPWM10_SOCB
56 EPWM11_SOCA
57 EPWM11_SOCB
58 EPWM12_SOCA
59 EPWM12_SOCB
60-67 Reserved
68 CPU_TINT0
69 CPU_TINT1
70 CPU_TINT2
71 MCBSPA_XEVT
72 MCBSPA_REVT
73 MCBSPB_XEVT
74 MCBSPB_REVT
75-94 Reserved
95 SD1FLT1_DRINT
96 SD1FLT2_DRINT
97 SD1FLT3_DRINT
98 SD1FLT4_DRINT
99 SD2FLT1_DRINT
100 SD2FLT2_DRINT
101 SD2FLT3_DRINT
102 SD2FLT4_DRINT
103-108 Reserved
109 SPIA_TXDMA
110 SPIA_RXDMA
111 SPIB_TXDMA
112 SPIB_RXDMA
113 SPIC_TXDMA
114 SPIC_RXDMA

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Table 5-1. DMA Trigger Source Options (continued)

Select Index Trigger Source
115-126 Reserved
127 CLB1_INT
128 CLB2_INT
129 CLB3_INT
130 CLB4_INT
131-255 Reserved

5.2.3 DMA Bus

The DMA bus architecture consists of a 32-bit address bus, a 32-bit data read bus, and a 32-bit data write bus.
Memories and register locations connected to the DMA bus by way of interfaces that sometimes share resources
with the CPU memory or peripheral bus. Arbitration rules are defined in Section 5.5.
5.3 Address Pointer and Transfer Control
The DMA state machine is, at the most basic level, two nested loops.
Burst (Inner) Loop:
The burst (inner) loop transfers a programmable number of words set by (BURST_SIZE + 1) register when a
DMA channel trigger (Peripheral or Software trigger) is received. The BURST_SIZE register allows a maximum
of 32 sixteen-bit words to be transferred in one burst. Each DMA channel supports both 16-bit or 32-bit
word burst that can be controlled by MODE.DATASIZE bit field. Each DMA channel contains a shadowed
address pointer for the source (SRC_ADDR_SHADOW) and the destination (DST_ADDR_SHADOW) address.
At the beginning of each transfer, the shadowed version of each pointer is copied into the respective active
(SRC_ADDR_ACTIVE or DST_ADDR_ACTIVE) register. During the burst loop, after each word is transferred,
the signed value contained in the appropriate source or destination BURST_STEP register is added to the active
register:
SRC_ADDR_ACTIVE = SRC_ADDR_ACTIVE + SRC_BURST_STEP
DST_ADDR_ACTIVE = DST_ADDR_ACTIVE + DST_BURST_STEP
The burst (inner) loop transfers a burst of data when a DMA Channel Trigger (Peripheral or Software trigger) is
received.
Transfer (Outer) Loop:
The Transfer (outer) loop transfers a programmable number of bursts set by (TRANSFER_SIZE + 1) register for
each channel. Since TRANSFER_SIZE is a 16-bit register, the total size of a transfer allowed is well beyond any
practical requirement. During the transfer loop, after each burst is complete, there are two methods that can be
used to modify the active address pointer:
Method 1 (Default): When address wrapping is disabled (SRC_WRAP_SIZE or DST_WRAP_SIZE is greater
than TRANSFER_SIZE), active address pointer is updated as shown below
SRC_ADDR_ACTIVE = SRC_ADDR_ACTIVE + SRC_TRANSFER_STEP
DST_ADDR_ACTIVE = DST_ADDR_ACTIVE + DST_TRANSFER_STEP

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Method 2: Address wrapping gets enabled when SRC_WRAP_SIZE or DST_WRAP_SIZE is less than
TRANSFER_SIZE. This allows the channel to wrap multiple times within a single transfer. When the number of
bursts is equal to (SRC/DST_WRAP_SIZE + 1) register, the state machine modifies the active address pointers
as:
SRC_BEG_ADDR_ACTIVE = SRC_BEG_ADDR_ACTIVE + SRC_WRAP_STEP
DST_BEG_ADDR_ACTIVE = DST_BEG_ADDR_ACTIVE + DST_WRAP_STEP
SRC_ADDR_ACTIVE = SRC_BEG_ADDR_ACTIVE
DST_ADDR_ACTIVE = DST_BEG_ADDR_ACTIVE
At the end of DMA transfer, DMA can have transferred (BURST_SIZE + 1) x (TRANSFER_SIZE + 1) words.
OneShot Mode:
OneShot mode is disabled by default.
When OneShot mode is disabled (MODE.CHx[ONESHOT] = 0), DMA transfers one burst [(BURST_SIZE + 1)
words] of data each time a DMA Channel Trigger is received. After the burst is completed, the state machine
moves on to the next pending channel in the priority scheme, even if another trigger for the channel just
completed is pending. This feature keeps any single channel from monopolizing the DMA bus.
When OneShot mode is enabled (MODE.CHx[ONESHOT] = 1), DMA transfers all the bursts [(BURST_SIZE + 1)
x (TRANSFER_SIZE + 1) words] on a single DMA channel trigger. Be careful when using this mode, since this
can create a condition where one trigger uses up the majority of the DMA bandwidth.
Continuous Mode:
Continuous mode is disabled by default.
When Continuous mode is disabled (MODE.CHx[CONTINUOUS] = 0), DMA state machine disables channel
after all bursts in a transfer loop (TRANSFER_COUNT = 0) are complete. The channel must be re-enabled by
setting the RUN bit in the CONTROL register before another transfer can be started on that channel.
When Continuous mode is enabled (MODE.CHx[CONTINUOUS] = 1), DMA state machine keep channel active
even after all bursts in a transfer loop (TRANSFER_COUNT = 0) are complete.
Each DMA channel can trigger an EPIE interrupt for each DMA transfer either at start of DMA transfer or end of
DMA transfer using MODE.CHx[CHINTMODE] bit.

Source/Destination The value written into the shadow register is the start address of the first location where
Address Pointers data is read or written to.
(SRC/DST_ADDR)
At the beginning of a transfer the shadow register (SRC/DST_ADDR_SHADOW) is
copied into the active register (SRC/DST_ADDR_ACTIVE). The active register performs
as the current address pointer.

Source/Destination This is the wrap pointer.

Begin Address Pointers
The value written into the shadow register (SRC/DST_BEG_ADDR_SHADOW) is
(SRC/DST_BEG_ADDR)
loaded into the active register (SRC/DST_BEG_ADDR_ACTIVE) at the start of a
transfer. On a wrap condition, the active register (SRC/DST_BEG_ADDR_ACTIVE)
is incremented by the signed value in the appropriate SRC/DST_WRAP_STEP
register prior to being loaded into the active register (SRC/DST_ADDR_ACTIVE).

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For each channel, the transfer process can be controlled with the following size values:

Source and This specifies the number of words to be transferred in a burst.

Destination
This value is loaded into the BURST_COUNT register at the beginning of each burst. The
Burst Size
BURST_COUNT decrements each word that is transferred and when the register reaches
(BURST_SIZE)
a zero value, the burst is complete, indicating that the next channel can be serviced. The
behavior of the current channel is defined by the ONE_SHOT bit in the MODE register. The
maximum size of the burst is dictated by the type of peripheral. For the ADC, the burst
size can be all 16 registers (if all 16 registers are used). For RAM, the burst size can be
up to the maximum allowed by the BURST_SIZE register, which is 32. See Table 5-2 to
understand how BURST_SIZE register affects the number of 16-bit words transferred with
respect to DATASIZE.

Table 5-2. BURSTSIZE versus DATASIZE Behavior

Number of 16-bit words transferred in
BURSTSIZE
DataSize = 16-bit data DataSize = 32-bit data
0 1 2
1 2 2
2 3 4
3 4 4
4 5 6
5 6 6
6 7 8
7 8 8
8 9 10
9 10 10
10 11 12
11 12 12
* * *
* * *
* * *
30 31 32
31 32 32

Source and This specifies the number of bursts to be transferred per CPU interrupt (if enabled).
Destination
Whether this interrupt is generated at the beginning or the end of the transfer
Transfer Size
is defined in the CHINTMODE bit in the MODE register. Whether the channel
(TRANSFER_SIZE)
remains enabled or not after the transfer is completed is defined by the
CONTINUOUS bit in the MODE register. The TRANSFER_SIZE register is loaded
into the TRANSFER_COUNT register at the beginning of each transfer. The
TRANSFER_COUNT register keeps track of how many bursts of data the channel
has transferred and when the register reaches zero, the DMA transfer is complete.

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Source/Destination This specifies the number of bursts to be transferred before the current address pointer
Wrap Size (SRC/ wraps around to the beginning.
DST_WRAP_SIZE)
This feature is used to implement a circular addressing type function. This value is
loaded into the appropriate SRC/DST_WRAP_COUNT register at the beginning of
each transfer. The SRC/DST_WRAP_COUNT registers keep track of how many bursts
of data the channel has transferred and when the registers reach zero, the wrap
procedure is performed on the appropriate source or destination address pointer. A
separate size and count register is allocated for source and destination pointers. To
disable the wrap function, assign the value of these registers to be larger than the
TRANSFER_SIZE.

Note
The value written to the SIZE registers is one less than the intended size. So, to transfer three 16-bit
words, the value 2 can be placed in the SIZE register.
Regardless of the state of the DATASIZE bit, the value specified in the SIZE registers are for 16-bit
addresses. So, to transfer three 32-bit words, the value 5 can be placed in the SIZE register.

For each source/destination pointer, the address changes can be controlled with the following step values:

Source/Destination Within each burst transfer, the address source and destination step sizes are
Burst Step (SRC/ specified by these registers.
DST_BURST_STEP)
This value is a signed 2s compliment number so that the address pointer can be
incremented or decremented as required. If no increment is desired, such as when
accessing the data receive or transmit registers in a communication peripheral, the
value of these registers can be set to zero.

Source/Destination This specifies the address offset to start the next burst transfer after
Transfer Step (SRC/ completing the current burst transfer.
DST_TRANSFER_STEP)
This is used in cases where registers or data memory locations are spaced at
constant intervals. This value is a signed 2s compliment number so that the
address pointer can be incremented or decremented as required.

Source/Destination When the wrap counter reaches zero, this value specifies the number of words to
Wrap Step (SRC/ add/subtract from the SRC/DST_BEG_ADDR pointer and hence sets the new start
DST_WRAP_STEP) address.
This implements a circular type of addressing mode, useful in many applications.
This value is a signed 2s compliment number so that the address pointer can be
incremented or decremented as required.

Note
Regardless of the state of the DATASIZE bit, the value specified in the STEP registers are for 16-bit
addresses. So, to increment one 32-bit address, a value of 2 can be placed in these registers.

Channel This mode bit selects whether the DMA interrupt from the respective channel is generated
Interrupt Mode at the beginning of a new transfer or at the end of the transfer.
(CHINTMODE)
If implementing a ping-pong buffer scheme with continuous mode of operation, then the
interrupt can be generated at the beginning, just after the working registers are copied to
the shadow set. If the DMA does not operate in continuous mode, then the interrupt is
typically generated at the end when the transfer is complete.

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All of the previous features and modes are shown in Figure 5-5. The following items are in reference to Figure
5-5.
• The HALT points represent where the channel halts operation when interrupted by a high priority channel 1
trigger, or when the HALT command is set, or when an emulation halt is issued and the FREE bit is cleared to
0.
• The SRC/DST_ADDR_ACTIVE registers are not affected by SRC/DST_BEG_ADDR_ACTIVE at the start of
a transfer. SRC/DST_BEG_ADDR_ACTIVE only affects the SRC/DST_ADDR_ACTIVE registers on a wrap.
Following is what happens when a transfer first starts:
– SRC/DST_BEG_ADDR_SHADOW remains unchanged.
– SRC/DST_ADDR_SHADOW remains unchanged.
– SRC/DST_BEG_ADDR_ACTIVE = SRC/DST_BEG_ADDR_SHADOW
– SRC/DST_ADDR_ACTIVE = SRC/DST_ADDR_SHADOW
• The active registers get updated when a wrap occurs. The shadow registers remain unchanged. Specifically:
– SRC/DST_BEG_ADDR_SHADOW remains unchanged.
– SRC/DST_ADDR_SHADOW remains unchanged.
– SRC/DST_BEG_ADDR_ACTIVE += SRC/DST_WRAP_STEP
– SRC/DST_ADDR_ACTIVE = SRC/DST_BEG_ADDR_ACTIVE
• The best way to remember this is:
– The shadow registers never change except by software.
– The active registers never change except by hardware, and a shadow register is only copied into the
active register, never an active register by another name.

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No
DMA trigger event?

Yes

Start DMA Transfer

When CHINTMODE == 0,
Generate EPIE interrupt at
beginning of DMA transfer
All shadow registers are copied to ACTIVE registers:-
SRC_BEG_ADDR_ACTIVE = SRC_BEG_ADDR_SHADOW
DST_BEG_ADDR_ACTIVE = DST_BEG_ADDR_SHADOW
SRC_ADDR_ACTIVE = SRC_ADDR_SHADOW
DST_ADDR_ACTIVE = DST_ADDR_SHADOW

Update wrap counters from wrap size registers:-

SRC_WRAP_COUNT = SRC_WRAP_SIZE
DST_WRAP_COUNT = DST_WRAP_SIZE

Yes WRAP_COUNT !=
WRAP_COUNT = WRAP_SIZE
WRAP_SIZE

No

TRANSFER_COUNT = TRANSFER_SIZE
DMA Transfer in Progress (TRANSFER_STS = 1)

HALT
BURST_COUNT = BURST_SIZE
here
BURST in Progress (BURST_STS = 1)

*DST_ADDR_ACTIVE = *SRC_ADDR_ACTIVE

Yes (Words pending in bursts)

BURST_COUNT > 0 BURST_COUNT --

SRC_ADDR_ACTIVE += SRC_BURST_STEP
HALT DST_ADDR_ACTIVE += DST_BURST_STEP
No (Burst Complete)
here
Points where
Burst Complete (BURSTSTS = 0) When CHINTMODE == 1, state machine
RC_ADDR_ACTIVE += SRC_TRANSFER_STEP Generate EPIE interrupt branches to next
DST_ADDR_ACTIVE += DST_TRANSFER_STEP at end of DMA transfer channel
Yes

TRANSFER_COUNT > 0 End DMA Transfer CONTINUOUS Enabled? DMA Channel disabled
No [TRANSFERSTS = 0] [CONTINUOUS = 1] No RUNSTS = 0

Yes
TRANSFER_COUNT--

Yes Yes
SRC_WRAP_COUNT -- SRC_WRAP_COUNT > 0 DST_WRAP_COUNT -- DST_WRAP_COUNT > 0

No No

SRC_WRAP_COUNT = SRC_WRAP_SIZE DST_WRAP_COUNT = DST_WRAP_SIZE

SRC_BEG_ADDR_ACTIVE += SRC_WRAP_STEP DST_BEG_ADDR_ACTIVE += DST_WRAP_STEP
SRC_ADDR_ACTIVE = SRC_BEG_ADDR_ACTIVE DST_ADDR_ACTIVE = DST_BEG_ADDR_ACTIVE

(Don’t need to wait for HALT

DMA trigger event) here
ONESHOT Enabled?
Yes [ONESHOT = 1]

Points where No
state machine Wait for DMA Trigger Event
branches to next
channel No Another DMA trigger
event

Yes

Figure 5-5. DMA State Diagram

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5.4 Pipeline Timing and Throughput

In addition to the pipeline there are a few other behaviors of the DMA that affect the total throughput:
• A 1-cycle delay is added at the beginning of each burst
• A 1-cycle delay is added when returning from a CH1 high-priority interrupt
• Collisions with the CPU can add delay slots (see Section 5.5)
• 32-bit transfers run at double the speed of a 16-bit transfer (takes the same amount of time to transfer a
32-bit word as to transfer a 16-bit word)
For example, to transfer 128 16-bit words from GS0 RAM to GS3 RAM, a channel can be configured to transfer
8 bursts of 16 words/burst. This gives:
8 bursts * [(3 cycles/word * 16 words/burst) + 1] = 392 cycles

If instead the channel were configured to transfer the same amount of data 32 bits at a time (the word size is
configured to 32 bits), the transfer can take:

8 bursts * [(3 cycles/word * 8 words/burst) + 1] = 200 cycles

The DMA module consists of a 3-stage pipeline as shown in Figure 5-6 and Figure 5-7.

Figure 5-6. 3-Stage Pipeline DMA Transfer

Figure 5-7. 3-stage Pipeline with One Read Stall

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5.5 CPU and CLA Arbitration

Typically, DMA activity is independent of CPU and CLA activity. However, when the DMA and CPU (or CLA)
try to access the same peripheral at the same time, an arbitration procedure is required to resolve the conflict.
All instances of the same peripheral type conflict with each other. For instance, CAN-A and CAN-B conflict.
Accesses to global shared RAM, across different instances, do not have this conflict. Different peripheral types
can share a bus interface, which creates further opportunities for conflicts. These bus interfaces are:
• Peripheral frame 1: ePWM, eCAP, eQEP, CMPSS, DAC , SDFM
• Peripheral frame 2: PMBus, SPI
Conflict Example: The CLA is accessing DAC-A while the DMA is simultaneously accessing DAC-B.
Conflict Example: The CPU is accessing an SPI FIFO while the DMA is simultaneously accessing a PMBus
register.
Non-conflict Example: The CPU is accessing a shared ePWM while the DMA is accessing an SPI.
Non-conflict Example: The CPU is accessing GS0 while the DMA is accessing GS1
The exception to all this is the ADC result registers, which are duplicated for each bus master. The CPU, DMA,
and CLA can all simultaneously read these result registers with no stalls or arbitration needed for any master.
A DMA transfer consists of four phases: send source address, read source data, send destination address, and
write destination data (see Section 5.4). Suppose CPU accesses a peripheral/memory causing conflict in middle
of a DMA transfer, CPU is stalled till the current DMA access is complete and not until the completion of whole
DMA transfer.
The following priority schemes are implemented for the various interfaces on the device:
• The fixed priority scheme for the peripheral frames is:
– CLA/DMA Write
– CLA/DMA Read
– CPU Write
– CPU Read
• The priority scheme for GSx RAM accesses is round-robin.
• The ADC results are duplicated for each CPU, CLA, and DMA so that no arbitration is needed when reading
the result registers. This allows all masters to access the ADC result registers simultaneously without delay.

Note
If the CPU is performing a read-modify-write operation and the DMA performs a write to the same
location, the DMA write can be lost if the operation occurs in between the CPU read and the CPU
write. Avoid mixing CPU writes with DMA writes to the same locations.

Arbitration within DMA channels is based on a round-robin priority or Channel 1 high-priority scheme described
in Section 5.6.

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5.6 Channel Priority

Two priority schemes exist when determining channel priority: Round-robin mode and Channel 1 high-priority
mode.
5.6.1 Round-Robin Mode
In this mode, all channels have equal priority and each enabled channel is serviced in round-robin fashion as:
CH1 → CH2 → CH3 → CH4 → CH5 → CH6 → CH1 → CH2 → …

In the case above, after each channel has transferred a burst of words, the next channel is serviced. The user
can specify the size of the burst for each channel. Once CH6 (or the last enabled channel) has been serviced,
and no other channels are pending, the round-robin state machine enters an idle state.
From the idle state, channel 1 (if enabled) is always serviced first. However, if the DMA is currently processing
another channel x, all other pending channels between x and the end of the round are serviced before CH1.
All the channels are of equal priority. For instance, take an example where CH1, CH4, and CH5 are enabled
in round-robin mode and CH4 is currently being processed. Then CH1 and CH5 both receive an interrupt
trigger from the respective peripherals before CH4 completes. CH1 and CH5 are now both pending. When CH4
completes the burst, CH5 is serviced next. Only after CH5 completes is CH1 serviced. Upon completion of CH1,
if there are no more channels pending, the round-robin state machine enters an idle state.
A more complicated example is:
• Assume all channels are enabled, and the DMA is in an idle state,
• Initially a trigger occurs on CH1, CH3, and CH5 on the same cycle,
• When the CH1 burst transfer starts, requests from CH3 and CH5 are pending,
• Before completion of the CH1 burst, the DMA receives a request from CH2. Now the pending requests are
from CH2, CH3, and CH5,
• After completing the CH1 burst, CH2 is serviced since this channel is next in the round-robin scheme after
CH1.
• After the burst from CH2 is finished, the CH3 burst is serviced, followed by CH5 burst.
• Now while the CH5 burst is being serviced, the DMA receives a request from CH1, CH3, and CH6.
• The burst from CH6 starts after the completion of the CH5 burst, since this channel is the next channel after
CH5 in the round-robin scheme.
• This is followed by the CH1 burst and then the CH3 burst
• After the CH3 burst finishes, assuming no more triggers have occurred, the round-robin state machine enters
an idle state.
The round-robin state machine can be reset to the idle state using the DMACTRL[PRIORITYRESET] bit.

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5.6.2 Channel 1 High-Priority Mode

In this mode, Channel 1 has high priority over all the other channels. Channels 2 to 6 have equal priority and
each enabled channel is serviced in a round-robin fashion.

Higher priority: CH1

Lower priority: CH2 → CH3 → CH4 → CH5 → CH6 → CH2 → …

Given an example where CH1, CH4, and CH5 are enabled in Channel 1 high-priority mode and CH4 is currently
being processed. Then CH1 and CH5 both receive an interrupt trigger from the respective peripherals before
CH4 completes. CH1 and CH5 are now both pending. When the current CH4 word transfer is completed,
regardless of whether the DMA has completed the entire CH4 burst, CH4 execution is suspended and CH1 is
serviced. After the CH1 burst completes, CH4 resumes execution.
Upon completion of CH4, CH5 is serviced. After CH5 completes, if there are no more channels pending, the
round-robin state machine enters an idle state.
Typically Channel 1 is used in this mode for the ADC, since the data rate is so high. However, Channel 1
high-priority mode can be used in conjunction with any peripheral.

Note
High-priority mode and ONESHOT mode cannot be used at the same time on Channel 1. Other
channels can use ONESHOT mode when Channel 1 is in high-priority mode.

5.7 Overrun Detection Feature

The DMA contains overrun detection logic. When a peripheral event trigger is received by the DMA, the
PERINTFLG bit in the CONTROL register is set, pending the channel to the DMA state machine. When the burst
for that channel is started, the PERINTFLG is cleared. If however, between the time that the PERINTFLG bit is
set by an event trigger and cleared by the start of the burst, an additional event trigger arrives, the second trigger
is lost. This condition sets the OVRFLG bit in the CONTROL register as in Figure 5-8. If the overrun interrupt is
enabled, the channel interrupt is generated to the PIE module.

DMA
channel interrupt DMACHx interrupt generated
PIE at beginning or end of transfer

CHx.MODE[CHINTE] CHx.CONTROL[OVRFLG]

CHx.CONTROL[PERINTFLG]
PERx_INT
Latch

CHx.CONTROL[ERRCLR]
CHx.MODE[OVERINTE]

Figure 5-8. Overrun Detection Logic

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5.8 Software
5.8.1 DMA Examples
NOTE: These examples are located in the C2000Ware installation at the following location:
C2000Ware_VERSION#/driverlib/DEVICE_GPN/examples/CORE_IF_MULTICORE/dma
Cloud access to these examples is available at the following link: dev.ti.com C2000Ware Examples.
5.8.1.1 DMA GSRAM Transfer (dma_ex1_gsram_transfer)
FILE: dma_ex1_gsram_transfer.c
This example uses one DMA channel to transfer data from a buffer in RAMGS0 to a buffer in RAMGS1. The
example sets the DMA channel PERINTFRC bit repeatedly until the transfer of 16 bursts (where each burst is 8
16-bit words) has been completed. When the whole transfer is complete, it will trigger the DMA interrupt.
: This example project has support for migration across our C2000 device families. If you are wanting to build
this project from launchpad or controlCARD, please specify in the .syscfg file the board you're using. At any time
you can select another device to migrate this example. Watch Variables
• sData - Data to send
• rData - Received data
5.8.1.2 DMA Transfer Shared Peripheral - C28X_DUAL
FILE: dma_ex1_shared_periph_cpu1.c
This example shows how to initiate a DMA transfer on CPU1 from a shared peripheral which is owned by CPU2.
In this specific example, a timer ISR is used on CPU2 to initiate a SPI transfer which will trigger the CPU1 DMA.
CPU1's DMA will then in turn update the ePWM1 CMPA value for the PWM which it owns. The PWM output can
be observed on the GPIO pins. It is recommended to run the c28x1 core first, followed by the C28x2 core.

Watch Pins
• GPIO0 and GPIO1 - ePWM output can be viewed with oscilloscope
5.8.1.3 DMA Transfer for Shared Peripheral Example (CPU2) - C28X_DUAL
FILE: dma_ex1_shared_periph_cpu2.c
This example shows how to initiate a DMA transfer on CPU1 from a shared peripheral that is owned by CPU2. In
this specific example, a timer ISR is used on CPU2 to initiate a SPI transfer that triggers the CPU1 DMA. CPU1
DMA then updates the ePWM1 CMPA value for the PWM that the DMA owns. The PWM output can be observed
on the GPIO pins. It is recommended to run the c28x1 core first, followed by the C28x2 core.
5.8.1.4 DMA GSRAM Transfer (dma_ex2_gsram_transfer)
FILE: dma_ex2_gsram_transfer.c
This example uses one DMA channel to transfer data from a buffer in RAMGS0 to a buffer in RAMGS1. The
example sets the DMA channel PERINTFRC bit repeatedly until the transfer of 16 bursts (where each burst is 8
16-bit words) has been completed. When the whole transfer is complete, it will trigger the DMA interrupt.
Watch Variables
• sData - Data to send
• rData - Received data

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5.9 DMA Registers

This section describes the Direct Memory Access Registers.
5.9.1 DMA Base Addresses
Table 5-3. DMA Base Address Table
Device Registers Register Name Start Address End Address
DmaRegs DMA_REGS 0x0000_1000 0x0000_11FF

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5.9.2 DMA_REGS Registers

Table 5-4 lists the memory-mapped registers for the DMA_REGS registers. All register offset addresses not
listed in Table 5-4 should be considered as reserved locations and the register contents should not be modified.
Table 5-4. DMA_REGS Registers
Offset Acronym Register Name Write Protection Section
0h DMACTRL DMA Control Register EALLOW Go
1h DEBUGCTRL Debug Control Register EALLOW Go
4h PRIORITYCTRL1 Priority Control 1 Register EALLOW Go
6h PRIORITYSTAT Priority Status Register EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 5-5 shows the codes that are used for
access types in this section.
Table 5-5. DMA_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1S W Write
1S 1 to set
Reset or Default Value
-n Value after reset or the default
value

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5.9.2.1 DMACTRL Register (Offset = 0h) [Reset = 0000h]

DMACTRL is shown in Figure 5-9 and described in Table 5-6.
Return to the Summary Table.
DMA Control Register
Figure 5-9. DMACTRL Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED PRIORITYRES HARDRESET
ET
R-0h R-0/W1S-0h R-0/W1S-0h

Table 5-6. DMACTRL Register Field Descriptions

Bit Field Type Reset Description
15-2 RESERVED R 0h Reserved
1 PRIORITYRESET R-0/W1S 0h The priority reset bit resets the round-robin state machine when a 1
is written. Service starts from the first enabled channel. Writes of 0
are ignored and this bit always reads back a 0.
When a 1 is written to this bit, any pending burst transfer completes
before resetting the channel priority machine. If CH1 is configured as
a high-priority channel, and this bit is
written to while CH1 is servicing a burst, both the CH1 burst and
the next pending low-priority burst are completed before the state
machine is reset.
If CH1 is high-priority, the state machine restarts from CH2 (or the
next highest enabled channel).
Reset type: SYSRSn
0 HARDRESET R-0/W1S 0h Writing a 1 to the hard reset bit resets the whole DMA and aborts any
current access (similar to applying a device reset). Writes of 0 are
ignored and this bit always reads back a 0.
For a soft reset, a bit is provided for each channel to perform a
gentler reset. Refer to the channel control registers.
When writing to this bit, there is a one cycle delay before it takes
effect. Hence, a one-cycle delay (such as a NOP instruction) is
required in software before attempting to access any other DMA
register.
Reset type: SYSRSn

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5.9.2.2 DEBUGCTRL Register (Offset = 1h) [Reset = 0000h]

DEBUGCTRL is shown in Figure 5-10 and described in Table 5-7.
Return to the Summary Table.
Debug Control Register
Figure 5-10. DEBUGCTRL Register
15 14 13 12 11 10 9 8
FREE RESERVED
R/W-0h R-0h

7 6 5 4 3 2 1 0
RESERVED
R-0h

Table 5-7. DEBUGCTRL Register Field Descriptions

Bit Field Type Reset Description
15 FREE R/W 0h Emulation Control
This bit specifies the action when an emulation halt event occurs.
Reset type: SYSRSn
0h (R/W) = The DMA completes the current read-write operation,
then halts.
1h (R/W) = The DMA continues running during an emulation halt.
14-0 RESERVED R 0h Reserved

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5.9.2.3 PRIORITYCTRL1 Register (Offset = 4h) [Reset = 0000h]

PRIORITYCTRL1 is shown in Figure 5-11 and described in Table 5-8.
Return to the Summary Table.
Priority Control 1 Register
Figure 5-11. PRIORITYCTRL1 Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED CH1PRIORITY
R-0h R/W-0h

Table 5-8. PRIORITYCTRL1 Register Field Descriptions

Bit Field Type Reset Description
15-1 RESERVED R 0h Reserved
0 CH1PRIORITY R/W 0h DMA Channel 1 Priority
This bit selects whether CH1 has high priority or not. The priority
can only be changed when all channels are disabled. A priority
reset should be performed before restarting channels after changing
priority
Reset type: SYSRSn
0h (R/W) = CH1 has the same priority as the other channels
1h (R/W) = CH1 has a higher priority than the other channels

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5.9.2.4 PRIORITYSTAT Register (Offset = 6h) [Reset = 0000h]

PRIORITYSTAT is shown in Figure 5-12 and described in Table 5-9.
Return to the Summary Table.
Priority Status Register
Figure 5-12. PRIORITYSTAT Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED ACTIVESTS_SHADOW RESERVED ACTIVESTS
R-0h R-0h R-0h R-0h

Table 5-9. PRIORITYSTAT Register Field Descriptions

Bit Field Type Reset Description
15-7 RESERVED R 0h Reserved
6-4 ACTIVESTS_SHADOW R 0h Active Channel Status Shadow
These bits are only meaningful when CH1 is in high-priority mode.
When CH1 is serviced, the ACTIVESTS bits are copied to the
shadow bits and indicate which channel was interrupted by CH1.
When CH1 service is completed, the shadow bits are copied back
to the ACTIVESTS bits. If this bit field is zero or the same as the
ACTIVESTS bit field, then no channel is pending due to a CH1
interrupt. When CH1 is not a higher priority channel, these bits
should be ignored.
Reset type: SYSRSn
0h (R/W) = No channel is active
1h (R/W) = CH 1
2h (R/W) = CH 2
3h (R/W) = CH 3
4h (R/W) = CH 4
5h (R/W) = CH 5
6h (R/W) = CH 6
7h (R/W) = Reserved
3 RESERVED R 0h Reserved
2-0 ACTIVESTS R 0h Active Channel Status
These bits indicate which channel (if any) is currently active or
performing a transfer.
Reset type: SYSRSn
0h (R/W) = No channel is active
1h (R/W) = CH 1
2h (R/W) = CH 2
3h (R/W) = CH 3
4h (R/W) = CH 4
5h (R/W) = CH 5
6h (R/W) = CH 6
7h (R/W) = Reserved

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5.9.3 DMA_CH_REGS Registers

Table 5-10 lists the memory-mapped registers for the DMA_CH_REGS registers. All register offset addresses
not listed in Table 5-10 should be considered as reserved locations and the register contents should not be
modified.
Table 5-10. DMA_CH_REGS Registers
Offset Acronym Register Name Write Protection Section
0h MODE Mode Register EALLOW Go
1h CONTROL Control Register EALLOW Go
2h BURST_SIZE Burst Size Register EALLOW Go
3h BURST_COUNT Burst Count Register EALLOW Go
4h SRC_BURST_STEP Source Burst Step Register EALLOW Go
5h DST_BURST_STEP Destination Burst Step Register EALLOW Go
6h TRANSFER_SIZE Transfer Size Register EALLOW Go
7h TRANSFER_COUNT Transfer Count Register EALLOW Go
8h SRC_TRANSFER_STEP Source Transfer Step Register EALLOW Go
9h DST_TRANSFER_STEP Destination Transfer Step Register EALLOW Go
Ah SRC_WRAP_SIZE Source Wrap Size Register EALLOW Go
Bh SRC_WRAP_COUNT Source Wrap Count Register EALLOW Go
Ch SRC_WRAP_STEP Source Wrap Step Register EALLOW Go
Dh DST_WRAP_SIZE Destination Wrap Size Register EALLOW Go
Eh DST_WRAP_COUNT Destination Wrap Count Register EALLOW Go
Fh DST_WRAP_STEP Destination Wrap Step Register EALLOW Go
10h SRC_BEG_ADDR_SHADOW Source Begin Address Shadow Register EALLOW Go
12h SRC_ADDR_SHADOW Source Address Shadow Register EALLOW Go
14h SRC_BEG_ADDR_ACTIVE Source Begin Address Active Register EALLOW Go
16h SRC_ADDR_ACTIVE Source Address Active Register EALLOW Go
18h DST_BEG_ADDR_SHADOW Destination Begin Address Shadow Register EALLOW Go
1Ah DST_ADDR_SHADOW Destination Address Shadow Register EALLOW Go
1Ch DST_BEG_ADDR_ACTIVE Destination Begin Address Active Register EALLOW Go
1Eh DST_ADDR_ACTIVE Destination Address Active Register EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 5-11 shows the codes that are used for
access types in this section.
Table 5-11. DMA_CH_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1S W Write
1S 1 to set
Reset or Default Value
-n Value after reset or the default
value

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5.9.3.1 MODE Register (Offset = 0h) [Reset = 0000h]

MODE is shown in Figure 5-13 and described in Table 5-12.
Return to the Summary Table.
Mode Register
Figure 5-13. MODE Register
15 14 13 12 11 10 9 8
CHINTE DATASIZE RESERVED RESERVED CONTINUOUS ONESHOT CHINTMODE PERINTE
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
OVRINTE RESERVED PERINTSEL
R/W-0h R-0h R/W-0h

Table 5-12. MODE Register Field Descriptions

Bit Field Type Reset Description
15 CHINTE R/W 0h Channel Interrupt Enable Bit
This bit enables the DMA channel's CPU interrupt.
Reset type: SYSRSn
0h (R/W) = Interrupt disabled
1h (R/W) = Interrupt enabled
14 DATASIZE R/W 0h Data Size Mode Bit
This bit determines whether the DMA channel transfers 16 bits or 32
bits of data per read/write operation. Regardless of this setting, all
data lengths and offsets in other DMA registers refer to 16- bit words.
The pointer step increments must be configured to accomodate 32-
bit words.
Reset type: SYSRSn
0h (R/W) = 16-bit data transfer size
1h (R/W) = 32-bit data transfer size
13 RESERVED R/W 0h Reserved
12 RESERVED R/W 0h Reserved
11 CONTINUOUS R/W 0h Continuous Mode Bit
If this bit is set to 1, then the channel re-initializes when
TRANSFER_COUNT is zero and waits for the next event trigger.
Otherwise, the DMA stops and clears the RUNSTS bit.
Reset type: SYSRSn
10 ONESHOT R/W 0h One Shot Mode
If this bit is set to 1, each peripheral event trigger causes the channel
to perform an entire transfer. Otherwise, the channel only performs
one burst per trigger.
Reset type: SYSRSn
9 CHINTMODE R/W 0h Channel Interrupt Generation Mode
This bit specifies when the DMA channel generates a CPU interrupt
for a transfer.
Reset type: SYSRSn
0h (R/W) = Generate interrupt at beginning of new transfer
1h (R/W) = Generate interrupt at end of transfer.
8 PERINTE R/W 0h Peripheral Event Trigger Enable
This bit enables peripheral event triggers on the DMA channel.
Reset type: SYSRSn
0h (R/W) = Peripheral event trigger disabled. Neither the selected
peripheral nor software can start a DMA burst.
1h (R/W) = Peripheral event trigger enabled.

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Table 5-12. MODE Register Field Descriptions (continued)

Bit Field Type Reset Description
7 OVRINTE R/W 0h Overflow Interrupt Enable
The bit determines whether the DMA module generates a CPU
interrupt when it detects an overflow event.
Reset type: SYSRSn
0h (R/W) = Overflow interrupt disabled
1h (R/W) = Overflow interrupt enabled
6-5 RESERVED R 0h Reserved
4-0 PERINTSEL R/W 0h Peripheral Event Trigger Source Select
These are legacy bits and should be set to the channel number. The
actual source selection is done via the DMACHSRCSELn registers,
which are part of the DMA_CLA_SRC_SEL_REGS group.
Reset type: SYSRSn

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5.9.3.2 CONTROL Register (Offset = 1h) [Reset = 0000h]

CONTROL is shown in Figure 5-14 and described in Table 5-13.
Return to the Summary Table.
Control Register
Figure 5-14. CONTROL Register
15 14 13 12 11 10 9 8
RESERVED OVRFLG RUNSTS BURSTSTS TRANSFERST RESERVED RESERVED PERINTFLG
S
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
ERRCLR RESERVED RESERVED PERINTCLR PERINTFRC SOFTRESET HALT RUN
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 5-13. CONTROL Register Field Descriptions

Bit Field Type Reset Description
15 RESERVED R 0h Reserved
14 OVRFLG R 0h Overflow Flag
This bit indicates that a peripheral event trigger was received while
PERINTFLG was already set. It can be cleared by writing to the
ERRCLR bit.
Reset type: SYSRSn
0h (R/W) = No overflow detected
1h (R/W) = Overflow detected
13 RUNSTS R 0h Run Status Flag
This bit indicates that the DMA channel is ready to respond
to peripheral event triggers. This bit is set when a 1 is
written to the RUN bit. It is cleared when a transfer completes
(TRANSFER_COUNT = 0) and continuous mode is disabled, or
when the HARDRESET, SOFTRESET, or HALT bit is set.
Reset type: SYSRSn
0h (R/W) = The channel is disabled
1h (R/W) = The channel is enabled
12 BURSTSTS R 0h Burst Status Flag
This bit is set when a DMA burst begins. The BURST_COUNT is
set to the BURST_SIZE. This bit is cleared when BURST_COUNT
reaches zero, or when the HARDRESET or SOFTRESET bit is set.
Reset type: SYSRSn
0h (R/W) = No burst activity
1h (R/W) = The DMA is currently servicing or suspending a burst
transfer from this channel
11 TRANSFERSTS R 0h Transfer Status Flag
This bit is set when a DMA transfer begins. The address registers
are copied to the shadow set and the TRANSFER_COUNT is set to
the TRANSFER_SIZE. This bit is cleared when TRANSFER_COUNT
reaches zero, or when the HARDRESET or SOFTRESET bit is set.
Reset type: SYSRSn
0h (R/W) = No transfer activity
1h (R/W) = The channel is currently in the middle of a transfer
regardless of whether a burst of data is actively being transferred
or not
10 RESERVED R 0h Reserved
9 RESERVED R 0h Reserved

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Table 5-13. CONTROL Register Field Descriptions (continued)

Bit Field Type Reset Description
8 PERINTFLG R 0h Peripheral Event Trigger Flag
This bit indicates whether a peripheral event trigger has arrived. This
bit is automatically cleared when the first burst transfer begins.
Reset type: SYSRSn
0h (R/W) = Waiting for event trigger
1h (R/W) = Event trigger pending
7 ERRCLR R-0/W1S 0h Clear Error
Writing a 1 to this bit will clear the OVRFLG bit. This is normally
done when initializing the DMA module or if an overflow condition is
detected. If an overflow event occurs at the same time this bit is set,
the overrun has priority and the OVRFLG bit is set.
Reset type: SYSRSn
6 RESERVED R-0/W1S 0h Reserved
5 RESERVED R-0/W1S 0h Reserved
4 PERINTCLR R-0/W1S 0h Clear Peripheral Event Trigger
Writing a 1 to this bit clears PERINTFLG, which cancels a pending
event trigger. This is normally done when initializing the DMA
module. If an event trigger arrives at the same time this bit is set,
the trigger has priority and PERINTFLG is set.
Reset type: SYSRSn
3 PERINTFRC R-0/W1S 0h Force Peripheral Event Trigger
If the PERINTE bit of the MODE register is set, writing a 1 to this bit
sets PERINTFLG, which triggers a DMA burst. This bit can be used
to start a DMA transfer in software.
Reset type: SYSRSn
2 SOFTRESET R-0/W1S 0h Channel Soft Reset
Writing a 1 to this bit places the channel into its default state after the
current read/write access has completed:
RUNSTS = 0
TRANSFERSTS = 0
BURSTSTS = 0
BURST_COUNT = 0
TRANSFER_COUNT = 0
SRC_WRAP_COUNT = 0
DST_WRAP_COUNT = 0
When writing to this bit, there is a one cycle delay before it takes
effect. Hence, a one-cycle delay (such as a NOP instruction) is
required in software before attempting to access any other DMA
register.
Reset type: SYSRSn
1 HALT R-0/W1S 0h Halt Channel
Writing a 1 to this bit halts the DMA channel in its current state after
any ongoing read/write access has completed.
Reset type: SYSRSn
0 RUN R-0/W1S 0h Run Channel
Writing a 1 to this bit enables the DMA channel and sets the
RUNSTS bit to 1. This bit is also used to resume after a channel
halt.
The RUN bit is typically used to start the DMA channel after
configuration. The channel will then wait for the first peripheral event
trigger (PERINTFLG == 1) to start a burst.
Reset type: SYSRSn

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5.9.3.3 BURST_SIZE Register (Offset = 2h) [Reset = 0000h]

BURST_SIZE is shown in Figure 5-15 and described in Table 5-14.
Return to the Summary Table.
Burst Size Register
Figure 5-15. BURST_SIZE Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED BURSTSIZE
R-0h R/W-0h

Table 5-14. BURST_SIZE Register Field Descriptions

Bit Field Type Reset Description
15-5 RESERVED R 0h Reserved
4-0 BURSTSIZE R/W 0h These bits specify the burst size in 16-bit words. The actual size is
equal to BURSTSIZE + 1.
Reset type: SYSRSn

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5.9.3.4 BURST_COUNT Register (Offset = 3h) [Reset = 0000h]

BURST_COUNT is shown in Figure 5-16 and described in Table 5-15.
Return to the Summary Table.
Burst Count Register
Figure 5-16. BURST_COUNT Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED BURSTCOUNT
R-0h R-0h

Table 5-15. BURST_COUNT Register Field Descriptions

Bit Field Type Reset Description
15-5 RESERVED R 0h Reserved
4-0 BURSTCOUNT R 0h These bits indicate the number of words left in the current burst.
Reset type: SYSRSn
0h (R/W) = 0 word left in a burst
1h (R/W) = 1 word left in a burst
2h (R/W) = 2 word left in a burst
3h (R/W) = 3 word left in a burst
4h (R/W) = 4 word left in a burst
5h (R/W) = 5 word left in a burst
6h (R/W) = 6 word left in a burst
7h (R/W) = 7 word left in a burst
8h (R/W) = 8 word left in a burst
9h (R/W) = 9 word left in a burst
Ah (R/W) = 10 word left in a burst
Bh (R/W) = 11 word left in a burst
Ch (R/W) = 12 word left in a burst
Dh (R/W) = 13 word left in a burst
Eh (R/W) = 14 word left in a burst
Fh (R/W) = 15 word left in a burst
10h (R/W) = 16 word left in a burst
11h (R/W) = 17 word left in a burst
12h (R/W) = 18 word left in a burst
13h (R/W) = 19 word left in a burst
14h (R/W) = 20 word left in a burst
15h (R/W) = 21 word left in a burst
16h (R/W) = 22 word left in a burst
17h (R/W) = 23 word left in a burst
18h (R/W) = 24 word left in a burst
19h (R/W) = 25 word left in a burst
1Ah (R/W) = 26 word left in a burst
1Bh (R/W) = 27 word left in a burst
1Ch (R/W) = 28 word left in a burst
1Dh (R/W) = 29 word left in a burst
1Eh (R/W) = 30 word left in a burst
1Fh (R/W) = 31 word left in a burst

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5.9.3.5 SRC_BURST_STEP Register (Offset = 4h) [Reset = 0000h]

SRC_BURST_STEP is shown in Figure 5-17 and described in Table 5-16.
Return to the Summary Table.
Source Burst Step Register
Figure 5-17. SRC_BURST_STEP Register
15 14 13 12 11 10 9 8
SRCBURSTSTEP
R/W-0h

7 6 5 4 3 2 1 0
SRCBURSTSTEP
R/W-0h

Table 5-16. SRC_BURST_STEP Register Field Descriptions

Bit Field Type Reset Description
15-0 SRCBURSTSTEP R/W 0h These bits specify the change in the source address after each
word in a burst. The size must be a 16-bit two's complement value
between -4096 and 4095 (inclusive). This value is added to the
source address after each read/write operation in a burst.
Reset type: SYSRSn
0h (R/W) = No address change
1h (R/W) = Add 1 to the address
2h (R/W) = Add 2 to the address
FFEh (R/W) = Add 4094 to the address
FFFh (R/W) = Add 4095 to the address
F000h (R/W) = Subtract 4096 from the address
F001h (R/W) = Subtract 4095 from the address
FFFEh (R/W) = Subtract 2 from the address
FFFFh (R/W) = Subtract 1 from the address

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5.9.3.6 DST_BURST_STEP Register (Offset = 5h) [Reset = 0000h]

DST_BURST_STEP is shown in Figure 5-18 and described in Table 5-17.
Return to the Summary Table.
Destination Burst Step Register
Figure 5-18. DST_BURST_STEP Register
15 14 13 12 11 10 9 8
DSTBURSTSTEP
R/W-0h

7 6 5 4 3 2 1 0
DSTBURSTSTEP
R/W-0h

Table 5-17. DST_BURST_STEP Register Field Descriptions

Bit Field Type Reset Description
15-0 DSTBURSTSTEP R/W 0h These bits specify the change in the destination address after each
word in a burst. The size must be a 16-bit two's complement value
between -4096 and 4095 (inclusive). This value is added to the
destination address after each read/write operation in a burst.
Reset type: SYSRSn
0h (R/W) = No address change
1h (R/W) = Add 1 to the address
2h (R/W) = Add 2 to the address
FFEh (R/W) = Add 4094 to the address
FFFh (R/W) = Add 4095 to the address
F000h (R/W) = Subtract 4096 from the address
F001h (R/W) = Subtract 4095 from the address
FFFEh (R/W) = Subtract 2 from the address
FFFFh (R/W) = Subtract 1 from the address

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5.9.3.7 TRANSFER_SIZE Register (Offset = 6h) [Reset = 0000h]

TRANSFER_SIZE is shown in Figure 5-19 and described in Table 5-18.
Return to the Summary Table.
Transfer Size Register
Figure 5-19. TRANSFER_SIZE Register
15 14 13 12 11 10 9 8
TRANSFERSIZE
R/W-0h

7 6 5 4 3 2 1 0
TRANSFERSIZE
R/W-0h

Table 5-18. TRANSFER_SIZE Register Field Descriptions

Bit Field Type Reset Description
15-0 TRANSFERSIZE R/W 0h These bits specify the transfer size in bursts. The actual size is equal
to TRANSFERSIZE + 1.
Reset type: SYSRSn

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5.9.3.8 TRANSFER_COUNT Register (Offset = 7h) [Reset = 0000h]

TRANSFER_COUNT is shown in Figure 5-20 and described in Table 5-19.
Return to the Summary Table.
Transfer Count Register
Figure 5-20. TRANSFER_COUNT Register
15 14 13 12 11 10 9 8
TRANSFERCOUNT
R-0h

7 6 5 4 3 2 1 0
TRANSFERCOUNT
R-0h

Table 5-19. TRANSFER_COUNT Register Field Descriptions

Bit Field Type Reset Description
15-0 TRANSFERCOUNT R 0h These bits indicate the number of bursts left in the current transfer.
Reset type: SYSRSn

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5.9.3.9 SRC_TRANSFER_STEP Register (Offset = 8h) [Reset = 0000h]

SRC_TRANSFER_STEP is shown in Figure 5-21 and described in Table 5-20.
Return to the Summary Table.
Source Transfer Step Register
Figure 5-21. SRC_TRANSFER_STEP Register
15 14 13 12 11 10 9 8
SRCTRANSFERSTEP
R/W-0h

7 6 5 4 3 2 1 0
SRCTRANSFERSTEP
R/W-0h

Table 5-20. SRC_TRANSFER_STEP Register Field Descriptions

Bit Field Type Reset Description
15-0 SRCTRANSFERSTEP R/W 0h These bits specify the change in the source address after a burst
completes. The size must be a 16-bit two's complement value
between -4096 and 4095 (inclusive). This value is added to the
source address after each burst completes.
Reset type: SYSRSn
0h (R/W) = No address change
1h (R/W) = Add 1 to the address
2h (R/W) = Add 2 to the address
FFEh (R/W) = Add 4094 to the address
FFFh (R/W) = Add 4095 to the address
F000h (R/W) = Subtract 4096 from the address
F001h (R/W) = Subtract 4095 from the address
FFFEh (R/W) = Subtract 2 from the address
FFFFh (R/W) = Subtract 1 from the address

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5.9.3.10 DST_TRANSFER_STEP Register (Offset = 9h) [Reset = 0000h]

DST_TRANSFER_STEP is shown in Figure 5-22 and described in Table 5-21.
Return to the Summary Table.
Destination Transfer Step Register
Figure 5-22. DST_TRANSFER_STEP Register
15 14 13 12 11 10 9 8
DSTTRANSFERSTEP
R/W-0h

7 6 5 4 3 2 1 0
DSTTRANSFERSTEP
R/W-0h

Table 5-21. DST_TRANSFER_STEP Register Field Descriptions

Bit Field Type Reset Description
15-0 DSTTRANSFERSTEP R/W 0h These bits specify the change in the destination address after a
burst completes. The size must be a 16-bit two's complement value
between -4096 and 4095 (inclusive). This value is added to the
destination address after each burst completes.
Reset type: SYSRSn
0h (R/W) = No address change
1h (R/W) = Add 1 to the address
2h (R/W) = Add 2 to the address
FFEh (R/W) = Add 4094 to the address
FFFh (R/W) = Add 4095 to the address
F000h (R/W) = Subtract 4096 from the address
F001h (R/W) = Subtract 4095 from the address
FFFEh (R/W) = Subtract 2 from the address
FFFFh (R/W) = Subtract 1 from the address

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5.9.3.11 SRC_WRAP_SIZE Register (Offset = Ah) [Reset = FFFFh]

SRC_WRAP_SIZE is shown in Figure 5-23 and described in Table 5-22.
Return to the Summary Table.
Source Wrap Size Register
Figure 5-23. SRC_WRAP_SIZE Register
15 14 13 12 11 10 9 8
WRAPSIZE
R/W-FFFFh

7 6 5 4 3 2 1 0
WRAPSIZE
R/W-FFFFh

Table 5-22. SRC_WRAP_SIZE Register Field Descriptions

Bit Field Type Reset Description
15-0 WRAPSIZE R/W FFFFh These bits specify the number of bursts to transfer before the source
address wraps around to the beginning address. The actual number
is equal to WRAPSIZE + 1. To disable the wrapping function, set
WRAPSIZE to a value larger than TRANSFERSIZE.
Reset type: SYSRSn

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5.9.3.12 SRC_WRAP_COUNT Register (Offset = Bh) [Reset = 0000h]

SRC_WRAP_COUNT is shown in Figure 5-24 and described in Table 5-23.
Return to the Summary Table.
Source Wrap Count Register
Figure 5-24. SRC_WRAP_COUNT Register
15 14 13 12 11 10 9 8
WRAPSIZE
R-0h

7 6 5 4 3 2 1 0
WRAPSIZE
R-0h

Table 5-23. SRC_WRAP_COUNT Register Field Descriptions

Bit Field Type Reset Description
15-0 WRAPSIZE R 0h These bits indicate the number of bursts left before wrapping the
source address.
Reset type: SYSRSn

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5.9.3.13 SRC_WRAP_STEP Register (Offset = Ch) [Reset = 0000h]

SRC_WRAP_STEP is shown in Figure 5-25 and described in Table 5-24.
Return to the Summary Table.
Source Wrap Step Register
Figure 5-25. SRC_WRAP_STEP Register
15 14 13 12 11 10 9 8
WRAPSTEP
R/W-0h

7 6 5 4 3 2 1 0
WRAPSTEP
R/W-0h

Table 5-24. SRC_WRAP_STEP Register Field Descriptions

Bit Field Type Reset Description
15-0 WRAPSTEP R/W 0h These bits specify the change in the source beginning address when
the wrap counter reaches zero. The size must be a 16-bit two's
complement value between -4096 and 4095 (inclusive). This value is
added to the source address when wrapping occurs.
Reset type: SYSRSn
0h (R/W) = No address change
1h (R/W) = Add 1 to the address
2h (R/W) = Add 2 to the address
FFEh (R/W) = Add 4094 to the address
FFFh (R/W) = Add 4095 to the address
F000h (R/W) = Subtract 4096 from the address
F001h (R/W) = Subtract 4095 from the address
FFFEh (R/W) = Subtract 2 from the address
FFFFh (R/W) = Subtract 1 from the address

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5.9.3.14 DST_WRAP_SIZE Register (Offset = Dh) [Reset = FFFFh]

DST_WRAP_SIZE is shown in Figure 5-26 and described in Table 5-25.
Return to the Summary Table.
Destination Wrap Size Register
Figure 5-26. DST_WRAP_SIZE Register
15 14 13 12 11 10 9 8
WRAPSIZE
R/W-FFFFh

7 6 5 4 3 2 1 0
WRAPSIZE
R/W-FFFFh

Table 5-25. DST_WRAP_SIZE Register Field Descriptions

Bit Field Type Reset Description
15-0 WRAPSIZE R/W FFFFh These bits specify the number of bursts to transfer before the
destination address wraps around to the beginning address. The
actual number is equal to WRAPSIZE + 1. To disable the wrapping
function, set WRAPSIZE to a value larger than TRANSFERSIZE.
Reset type: SYSRSn

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5.9.3.15 DST_WRAP_COUNT Register (Offset = Eh) [Reset = 0000h]

DST_WRAP_COUNT is shown in Figure 5-27 and described in Table 5-26.
Return to the Summary Table.
Destination Wrap Count Register
Figure 5-27. DST_WRAP_COUNT Register
15 14 13 12 11 10 9 8
WRAPSIZE
R-0h

7 6 5 4 3 2 1 0
WRAPSIZE
R-0h

Table 5-26. DST_WRAP_COUNT Register Field Descriptions

Bit Field Type Reset Description
15-0 WRAPSIZE R 0h These bits indicate the number of bursts left before wrapping the
destination address.
Reset type: SYSRSn

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5.9.3.16 DST_WRAP_STEP Register (Offset = Fh) [Reset = 0000h]

DST_WRAP_STEP is shown in Figure 5-28 and described in Table 5-27.
Return to the Summary Table.
Destination Wrap Step Register
Figure 5-28. DST_WRAP_STEP Register
15 14 13 12 11 10 9 8
WRAPSTEP
R/W-0h

7 6 5 4 3 2 1 0
WRAPSTEP
R/W-0h

Table 5-27. DST_WRAP_STEP Register Field Descriptions

Bit Field Type Reset Description
15-0 WRAPSTEP R/W 0h These bits specify the change in the destination beginning address
when the wrap counter reaches zero. The size must be a 16-bit two's
complement value between -4096 and 4095 (inclusive). This value is
added to the destination address when wrapping occurs.
Reset type: SYSRSn
0h (R/W) = No address change
1h (R/W) = Add 1 to the address
2h (R/W) = Add 2 to the address
FFEh (R/W) = Add 4094 to the address
FFFh (R/W) = Add 4095 to the address
F000h (R/W) = Subtract 4096 from the address
F001h (R/W) = Subtract 4095 from the address
FFFEh (R/W) = Subtract 2 from the address
FFFFh (R/W) = Subtract 1 from the address

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5.9.3.17 SRC_BEG_ADDR_SHADOW Register (Offset = 10h) [Reset = 00000000h]

SRC_BEG_ADDR_SHADOW is shown in Figure 5-29 and described in Table 5-28.
Return to the Summary Table.
Source Begin Address Shadow Register
Figure 5-29. SRC_BEG_ADDR_SHADOW Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BEGADDR
R/W-0h

Table 5-28. SRC_BEG_ADDR_SHADOW Register Field Descriptions

Bit Field Type Reset Description
31-0 BEGADDR R/W 0h Shadow Source Beginning Address
At the start of a transfer, the value in this register is loaded into
the SRC_BEG_ADDR_ACTIVE register and used as the beginning
value for the source address. This register can be safely updated
during a transfer.
Reset type: SYSRSn

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5.9.3.18 SRC_ADDR_SHADOW Register (Offset = 12h) [Reset = 00000000h]

SRC_ADDR_SHADOW is shown in Figure 5-30 and described in Table 5-29.
Return to the Summary Table.
Source Address Shadow Register
Figure 5-30. SRC_ADDR_SHADOW Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR
R/W-0h

Table 5-29. SRC_ADDR_SHADOW Register Field Descriptions

Bit Field Type Reset Description
31-0 ADDR R/W 0h Shadow Source Address
At the start of a transfer, the value in this register is loaded into the
SRC_ADDR_ACTIVE register and used as the value of the source
address. This register can be safely updated during a transfer.
Reset type: SYSRSn

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5.9.3.19 SRC_BEG_ADDR_ACTIVE Register (Offset = 14h) [Reset = 00000000h]

SRC_BEG_ADDR_ACTIVE is shown in Figure 5-31 and described in Table 5-30.
Return to the Summary Table.
Source Begin Address Active Register
Figure 5-31. SRC_BEG_ADDR_ACTIVE Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BEGADDR
R-0h

Table 5-30. SRC_BEG_ADDR_ACTIVE Register Field Descriptions

Bit Field Type Reset Description
31-0 BEGADDR R 0h Active Source Beginning Address
If a transfer is ongoing, this register holds the current beginning
value for the source address. This address may be updated after
wrapping.
When a transfer starts, this register is loaded with the shadow
address from the SRC_BEG_ADDR_SHADOW register.
Reset type: SYSRSn

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5.9.3.20 SRC_ADDR_ACTIVE Register (Offset = 16h) [Reset = 00000000h]

SRC_ADDR_ACTIVE is shown in Figure 5-32 and described in Table 5-31.
Return to the Summary Table.
Source Address Active Register
Figure 5-32. SRC_ADDR_ACTIVE Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR
R-0h

Table 5-31. SRC_ADDR_ACTIVE Register Field Descriptions

Bit Field Type Reset Description
31-0 ADDR R 0h Active Source Address
If a transfer is ongoing, this register holds the current value of the
source address. This address may change after a write, a burst, or
wrapping.
Reset type: SYSRSn

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5.9.3.21 DST_BEG_ADDR_SHADOW Register (Offset = 18h) [Reset = 00000000h]

DST_BEG_ADDR_SHADOW is shown in Figure 5-33 and described in Table 5-32.
Return to the Summary Table.
Destination Begin Address Shadow Register
Figure 5-33. DST_BEG_ADDR_SHADOW Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BEGADDR
R/W-0h

Table 5-32. DST_BEG_ADDR_SHADOW Register Field Descriptions

Bit Field Type Reset Description
31-0 BEGADDR R/W 0h Shadow Destination Beginning Address
At the start of a transfer, the value in this register is loaded into
the DST_BEG_ADDR_ACTIVE register and used as the beginning
value for the destination address. This register can be safely updated
during a transfer.
Reset type: SYSRSn

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5.9.3.22 DST_ADDR_SHADOW Register (Offset = 1Ah) [Reset = 00000000h]

DST_ADDR_SHADOW is shown in Figure 5-34 and described in Table 5-33.
Return to the Summary Table.
Destination Address Shadow Register
Figure 5-34. DST_ADDR_SHADOW Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR
R/W-0h

Table 5-33. DST_ADDR_SHADOW Register Field Descriptions

Bit Field Type Reset Description
31-0 ADDR R/W 0h Shadow Destination Address
At the start of a transfer, the value in this register is loaded into
the DST_ADDR_ACTIVE register and used as the value of the
destination address. This register can be safely updated during a
transfer.
Reset type: SYSRSn

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5.9.3.23 DST_BEG_ADDR_ACTIVE Register (Offset = 1Ch) [Reset = 00000000h]

DST_BEG_ADDR_ACTIVE is shown in Figure 5-35 and described in Table 5-34.
Return to the Summary Table.
Destination Begin Address Active Register
Figure 5-35. DST_BEG_ADDR_ACTIVE Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BEGADDR
R-0h

Table 5-34. DST_BEG_ADDR_ACTIVE Register Field Descriptions

Bit Field Type Reset Description
31-0 BEGADDR R 0h Active Destination Beginning Address
If a transfer is ongoing, this register holds the current destination
value for the source address. This address may be updated after
wrapping.
When a transfer starts, this register is loaded with the shadow
address from the DST_BEG_ADDR_SHADOW register.
Reset type: SYSRSn

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5.9.3.24 DST_ADDR_ACTIVE Register (Offset = 1Eh) [Reset = 00000000h]

DST_ADDR_ACTIVE is shown in Figure 5-36 and described in Table 5-35.
Return to the Summary Table.
Destination Address Active Register
Figure 5-36. DST_ADDR_ACTIVE Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR
R-0h

Table 5-35. DST_ADDR_ACTIVE Register Field Descriptions

Bit Field Type Reset Description
31-0 ADDR R 0h Active Destination Address
If a transfer is ongoing, this register holds the current value of the
destination address. This address may change after a write, a burst,
or wrapping.
Reset type: SYSRSn

5.9.4 DMA Registers to Driverlib Functions

Table 5-36. DMA Registers to Driverlib Functions
File Driverlib Function
CTRL
dma.h DMA_initController
DEBUGCTRL
dma.h DMA_setEmulationMode
PRIORITYCTRL1
dma.h DMA_setPriorityMode
PRIORITYSTAT
-
MODE
dma.c DMA_configMode
dma.h DMA_enableTrigger
dma.h DMA_disableTrigger
dma.h DMA_enableInterrupt
dma.h DMA_disableInterrupt
dma.h DMA_enableOverrunInterrupt
dma.h DMA_disableOverrunInterrupt
dma.h DMA_setInterruptMode
CONTROL
dma.h DMA_triggerSoftReset
dma.h DMA_forceTrigger
dma.h DMA_clearTriggerFlag
dma.h DMA_getTransferStatusFlag
dma.h DMA_getBurstStatusFlag
dma.h DMA_getRunStatusFlag
dma.h DMA_getOverflowFlag
dma.h DMA_getTriggerFlagStatus
dma.h DMA_startChannel

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Table 5-36. DMA Registers to Driverlib Functions (continued)

File Driverlib Function
dma.h DMA_stopChannel
dma.h DMA_clearErrorFlag
BURST_SIZE
dma.c DMA_configBurst
BURST_COUNT
-
SRC_BURST_STEP
dma.c DMA_configBurst
DST_BURST_STEP
dma.c DMA_configBurst
TRANSFER_SIZE
dma.c DMA_configTransfer
TRANSFER_COUNT
-
SRC_TRANSFER_STEP
dma.c DMA_configTransfer
DST_TRANSFER_STEP
dma.c DMA_configTransfer
SRC_WRAP_SIZE
dma.c DMA_configWrap
SRC_WRAP_COUNT
-
SRC_WRAP_STEP
dma.c DMA_configWrap
DST_WRAP_SIZE
dma.c DMA_configWrap
DST_WRAP_COUNT
-
DST_WRAP_STEP
dma.c DMA_configWrap
SRC_BEG_ADDR_SHADOW
dma.c DMA_configAddresses
dma.h DMA_configSourceAddress
SRC_ADDR_SHADOW
dma.c DMA_configAddresses
dma.h DMA_configSourceAddress
SRC_BEG_ADDR_ACTIVE
-
SRC_ADDR_ACTIVE
-
DST_BEG_ADDR_SHADOW
dma.c DMA_configAddresses
dma.h DMA_configDestAddress
DST_ADDR_SHADOW
dma.c DMA_configAddresses

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Table 5-36. DMA Registers to Driverlib Functions (continued)

File Driverlib Function
dma.h DMA_configDestAddress
DST_BEG_ADDR_ACTIVE
-
DST_ADDR_ACTIVE
-

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Chapter 6
Control Law Accelerator (CLA)

The Control Law Accelerator (CLA) Type-1 is an independent, fully-programmable, 32-bit floating-point math
processor that brings concurrent control-loop execution to the C28x family. The low interrupt latency of the
CLA allows the CLA to read ADC samples "just-in-time." This significantly reduces the ADC sample to output
delay to enable faster system response and higher MHz control loops. By using the CLA to service time-critical
control loops, the main CPU is free to perform other system tasks such as communications and diagnostics. This
chapter provides an overview of the architectural structure and components of the control law accelerator.

6.1 Introduction...............................................................................................................................................................718
6.2 CLA Interface............................................................................................................................................................ 720
6.3 CLA and CPU Arbitration.........................................................................................................................................726
6.4 CLA Configuration and Debug................................................................................................................................ 729
6.5 Pipeline......................................................................................................................................................................732
6.6 Software.................................................................................................................................................................... 738
6.7 Instruction Set...........................................................................................................................................................739
6.8 CLA Registers...........................................................................................................................................................870

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6.1 Introduction
The Control Law Accelerator extends the capabilities of the C28x CPU by adding parallel processing. Time-
critical control loops serviced by the CLA can achieve low ADC sample to output delay. Thus, the CLA enables
faster system response and higher frequency control loops. Utilizing the CLA for time-critical tasks frees up the
main CPU to perform other system and communication functions concurrently.
6.1.1 Features
The following is a list of major features of the CLA:
• C compilers are available for CLA software development.
• Clocked at the same rate as the main CPU (SYSCLKOUT).
• An independent architecture allowing CLA algorithm execution independent of the main C28x CPU.
– Complete bus architecture:
• Program Address Bus (PAB) and Program Data Bus (PDB)
• Data Read Address Bus (DRAB), Data Read Data Bus (DRDB), Data Write Address Bus (DWAB), and
Data Write Data Bus (DWDB)
– Independent eight stage pipeline.
– 16-bit program counter (MPC)
– Four 32-bit result registers (MR0-MR3)
– Two 16-bit auxiliary registers (MAR0, MAR1)
– Status register (MSTF)
• Instruction set includes:
– IEEE single-precision (32-bit) floating-point math operations
– Floating-point math with parallel load or store
– Floating-point multiply with parallel add or subtract
– 1/X and 1/sqrt(X) estimations
– Data type conversions.
– Conditional branch and call
– Data load/store operations
• The CLA program code can consist of up to eight tasks or interrupt service routines
– The start address of each task is specified by the MVECT registers.
– No limit on task size as long as the tasks fit within the configurable CLA program memory space.
– One task is serviced at a time until completion. There is no nesting of tasks.
– Upon task completion a task-specific interrupt is flagged within the PIE.
– When a task finishes the next highest-priority pending task is automatically started.
• Task trigger mechanisms:
– C28x CPU using the IACK instruction
– Task1 to Task8: up to 256 possible trigger sources from peripherals connected to the shared bus on which
the CLA assumes secondary ownership.
• Memory and Shared Peripherals:
– Two dedicated message RAMs for communication between the CLA and the main CPU.
– The C28x CPU can map CLA program and data memory to the main CPU space or CLA space.
– The CLA, on reset, is the secondary master for all peripherals that can have either the CLA or DMA as
their secondary master.

6.1.2 CLA Related Collateral

Foundational Materials
• C2000 Academy - CLA
• C2000 CLA C Compiler Series (Video)
• CLA Hands On Workshop (Video)
• CLA usage in Valley Switching Boost Power Factor Correction (PFC) Reference Design (Video)

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• Enhancing the Computational Performance of the C2000™ Microcontroller Family Application Report

Getting Started Materials

• CLA Software Development Guide
• Software Examples to Showcase Unique Capabilities of TI's C2000™ CLA Application Report

Expert Materials
• Digital Control of Two Phase Interleaved PFC and Motor Drive Using MCU With CLA Application Report
• Sensorless Field Oriented Control:3-Phase Perm.Magnet Synch. Motors With CLA Application Report
6.1.3 Block Diagram
Figure 6-1 is a block diagram of the CLA.

CLA Control
Register Set
MIFR(16) CLA_INT1
From MPERINT1 to
MIOVF(16)
Shared to MICLR(16) CLA_INT8
Peripherals MPERINT8 MICLROVF(16) INT11 C28x
PIE
MIFRC(16) INT12 CPU
MIER(16)
MIRUN(16)
LVF
LUF
MVECT1(16)
MVECT2(16)
MVECT3(16)
SYSCLK MVECT4(16)
CLA Clock Enable MVECT5(16)
SYSRSn CPU Read/Write Data Bus
MVECT6(16)
MVECT7(16)
MVECT8(16) CLA Program
CLA Program Bus Memory (LSx)
MCTL(16)

LSxMSEL[MSEL_LSx]
LSxCLAPGM[CLAPGM_LSx]

CPU Data Bus

CLA Data
CLA Execution Memory (LSx)
CLA Data Bus

Register Set
MPC(16) CLA Message
MSTF(32) RAMs
MR0(32)
MR1(32)
MR2(32) Shared
MR3(32) Peripherals
MAR0(16) MEALLOW
MAR1(16)

CPU Read Data Bus

Figure 6-1. CLA Block Diagram

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6.2 CLA Interface

This section describes how the C28x main CPU can interface to the CLA and conversely.
6.2.1 CLA Memory
The CLA can access three types of memory: program, data and message RAMs. The behavior and arbitration
for each type of memory is described in this chapter. The CLA RAMs are protected by the DCSM module. Refer
to the Dual Code Security Module (DCSM) section of the System Control and Interrupts chapter for more details
on the security scheme.
• CLA Program Memory
The CLA program can be loaded with any of the local shared memories (LSxRAM) on the core. At reset,
all memory blocks are mapped to the CPU. While mapped to the CPU space, the CPU can copy the
CLA program code into the memory. During debug, the memory can also be loaded directly by the Code
Composer Studio™ IDE.
Once the memory is initialized with CLA code, the CPU maps the memory to the CLA program space by:
1. Assigning ownership of the memory block to the CLA by writing a 1 to the memory block’s
MemCfgRegs.LSxMSEL[MSEL_LSx] bit.
2. Specifying the memory block as a code block for the CLA by writing a 1 to the
MemCfgRegs.LSxCLAPGM[CLAPGM_LSx] bit.
When a memory block is configured as CLA program memory, debug accesses are allowed only on cycles
where the CLA is not fetching a new instruction. A detailed explanation of the memory configurations and
access arbitration (CPU, CLA, and DEBUG) process can be found in the Memory Controller Module section
of the System Control and Interrupts chapter.
All CLA program fetches are performed as 32-bit read operations and all opcodes must be aligned to an even
address. Since all CLA opcodes are 32-bits, this alignment occurs naturally.

• CLA Data Memory

Any of the device’s LSxRAMs can serve as data memory blocks to the CLA. At reset, all blocks are mapped
to the CPU memory space, whereby the CPU can initialize the memory with data tables, coefficients, and so
on, for the CLA to use.
Once the memory is initialized with CLA data, the CPU maps the memory to the CLA data space by:
1. Assigning ownership of the memory block to the CLA by writing a 1 to the memory block’s
MemCfgRegs.LSxMSEL[MSEL_LSx] bit.
2. Specifying the memory block as a data block for the CLA by writing a 0 to the
MemCfgRegs.LSxCLAPGM[CLAPGM_LSx] bit. The value of this bit at reset is 0.
When a memory block is configured as CLA data memory, CLA read and write accesses are arbitrated along
with CPU accesses. The user has the option of turning on CPU fetch or write protection to the memory by
writing to the appropriate bits of the MemCfgRegs.LSxACCPROTx registers. A detailed explanation of the
memory configurations and access arbitration (CPU, CLA, and DEBUG) process can be found in the Memory
Controller Module section of the System Control and Interrupts chapter.

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• CLA Shared Message RAMs

There are two memory blocks for data sharing and communication between the CLA and the CPU on each
CPU subsystem. The message RAMs are always mapped to both CPU and CLA memory spaces, and only
data access is allowed; no program fetches can be performed.
– CLA to CPU Message RAM: The CLA can use this block to pass data to the CPU. This block is both
readable and writable by the CLA. This block is also readable by the CPU but writes by the CPU are
ignored.
– CPU to CLA Message RAM: The CPU can use this block to pass data and messages to the CLA. This
message RAM is both readable and writable by the CPU. The CLA can perform reads but writes by the
CLA are ignored.

6.2.2 CLA Memory Bus

The CLA has dedicated bus architecture similar to that of the C28x CPU where there are separate program read,
data read, and data write buses. Thus, there can be simultaneous instruction fetch, data read, and data write in
a single cycle. Like the C28x CPU, the CLA expects memory logic to align any 32-bit read or write to an even
address. If the address-generation logic generates an odd address, the CLA can begin reading or writing at the
previous even address. This alignment does not affect the address values generated by the address-generation
logic.
• CLA Program Bus
The CLA program bus has an access range of 32K 32-bit instructions. Since all CLA instructions are 32
bits, this bus always fetches 32 bits at a time and the opcodes must be even-word aligned. The amount of
program space available for the CLA is limited to the number of available LSxRAM blocks. This number is
device-dependent and can be described in the data sheet.

• CLA Data Read Bus

The CLA data read bus has a 64K x 16 address range. The bus can perform 16 or 32-bit reads and can
automatically stall if there are memory access conflicts. The data read bus has access to both the message
RAMs, CLA data memory, and the shared peripherals.

• CLA Data Write Bus

The CLA data write bus has a 64K x 16 address range. This bus can perform 16 or 32-bit writes. The bus can
automatically stall if there are memory access conflicts. The data write bus has access to the CLA to CPU
message RAM, CLA data memory, and the shared peripherals.

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6.2.3 Shared Peripherals and EALLOW Protection

For a given CPU subsystem, the CLA and DMA share secondary access to some peripherals. The secondary
ownership of the bus is determined by the CpuSysRegs.SECMSEL[VBUS32_x] bit. If the bit is set to 0, the CLA
is the secondary owner. If the bit is set to 1, the DMA is the secondary owner. By default, at reset, the CLA is
given the secondary ownership of the bus and, therefore, can access all the peripherals connected to the bus.

Note
The CLA read access time to the bus is 2-wait states while write access is 0-wait.

Refer to the device data sheet for the list of peripherals connected to the bus.
Several peripheral control registers are protected from spurious 28x CPU writes by the EALLOW protection
mechanism. These same registers are also protected from spurious CLA writes. The EALLOW bit in the CPU
status register 1 (ST1) indicates the state of protection for the CPU. Likewise, the MEALLOW bit in the CLA
status register (MSTF) indicates the state of write protection for the CLA. The MEALLOW CLA instruction
enables write access by the CLA to EALLOW protected registers. Likewise, the MEDIS CLA instruction disables
write access. This way the CLA can enable and disable write access independent of the CPU.
The ADC offers the option to generate an early interrupt pulse at the start of a sample conversion. If this option
is used to start an ADC-triggered CLA task, use the intervening cycles until the completion of the conversion
to perform preliminary calculations or loads and stores before finally reading the ADC value. The CLA pipeline
activity for this scenario is shown in Section 6.5.
6.2.4 CLA Tasks and Interrupt Vectors
The CLA program code is divided up into tasks or interrupt service routines. Tasks do not have a fixed starting
location or length. The CLA program memory can be divided up as desired. The CLA uses the contents of the
interrupt vectors (MVECT1 to MVECT8) to determine where a task begins; tasks are terminated by the MSTOP
instruction.
The CLA supports eight tasks. Task 1 has the highest priority and task 8 has the lowest priority.
A task can be requested by a peripheral interrupt or by software:
• Peripheral interrupt trigger
Each task can be triggered by software-selectable interrupt sources. The trigger for each task is defined by
writing an appropriate value to the DmaClaSrcSelRegs.CLA1TASKSRCSELx[TASKx] bit field. Each option
specifies an interrupt source from a specific peripheral on the shared bus. The peripheral interrupt triggers
are listed in Table 6-1.
For example, task 1 (MVECT1) can be set to trigger on EPWMINT1 by writing 36 to
DmaClaSrcSelRegs.CLA1TASKSRCSEL1.TASK1. To disable the triggering of a task by a peripheral, set
the DmaClaSrcSelRegs.CLA1TASKSRCSELx[TASKx] bit field to 0. Note that a CLA task only triggers on a
level transition (an edge) of the configured interrupt source.

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Table 6-1. Configuration Options

Select Value CLA Trigger Source

0 CLA_SOFTWARE_TRIGGER

1 ADCAINT1

2 ADCAINT2

3 ADCAINT3

4 ADCAINT4

5 ADCA_EVT_INT

6 ADCBINT1

7 ADCBINT2

8 ADCBINT3

9 ADCBINT4

10 ADCB_EVT_INT

11 ADCCINT1

12 ADCCINT2

13 ADCCINT3

14 ADCCINT4

15 ADCC_EVT_INT

16 ADCDINT1

17 ADCDINT2

18 ADCDINT3

19 ADCDINT4

20 ADCD_EVT_INT

21-28 Reserved

29 XINT1

30 XINT2

31 XINT3

32 XINT4

33 XINT5

34-35 Reserved

36 EPWM1_INT

37 EPWM2_INT

38 EPWM3_INT

39 EPWM4_INT

40 EPWM5_INT

41 EPWM6_INT

42 EPWM7_INT

43 EPWM8_INT

44 EPWM9_INT

45 EPWM10_INT

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Table 6-1. Configuration Options (continued)

Select Value CLA Trigger Source

46 EPWM11_INT

47 EPWM12_INT

48-67 Reserved

68 CPU_TINT0

69 CPU_TINT1

70 CPU_TINT2

71 MCBSPA_TX

72 MCBSPA_RX

73 MCBSPB_TX

74 MCBSPB_RX

75 ECAP1_INT

76 ECAP2_INT

77 ECAP3_INT

78 ECAP4_INT

79 ECAP5_INT

80 ECAP6_INT

81-82 Reserved

83 EQEP1_INT

84 EQEP2_INT

85 EQEP3_INT

86-94 Reserved

95 SD1_ERRINT

96 SD2_ERRINT

97-106 Reserved

107 UPPA_INT

108 Reserved

109 SPIA_TXINT

110 SPIA_RXINT

111 SPIB_TXINT

112 SPIB_RXINT

113 SPIC_TXINT

114 SPIC_RXINT

115-126 Reserved

127 CLB1_INT

128 CLB2_INT

129 CLB3_INT

130 CLB4_INT

131-255 Reserved

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• Software Trigger
CPU software can trigger tasks by writing to the MIFRC register or by the IACK instruction. Using the
IACK instruction is more efficient because the instruction does not require the need to issue an EALLOW
to set MIFR bits. Set the MCTL[IACKE] bit to enable the IACK feature. Each bit in the operand of the IACK
instruction corresponds to a task. For example, IACK #0x0001 sets bit 0 in the MIFR register to start task 1.
Likewise, IACK #0x0003 set bits 0 and 1 in the MIFR register to start task 1 and task 2.
The CLA has a fetch mechanism and can run and execute a task independent of the CPU. Only one task is
serviced at a time; there is no nesting of tasks. The task currently running is indicated in the MIRUN register.
Interrupts that have been received but not yet serviced are indicated in the flag register (MIFR). If an interrupt
request from a peripheral is received and that same task is already flagged, then the overflow flag bit is set.
Overflow flags remain set until the flags are cleared by the CPU.
If the CLA is idle (no task is currently running), then the highest priority interrupt request that is both flagged
(MIFR) and enabled (MIER) starts.
The flow is as follows:
1. The associated RUN register bit is set (MIRUN) and the flag bit (MIFR) is cleared.
2. The CLA begins execution at the location indicated by the associated interrupt vector (MVECTx). MVECT
contains the absolute 16-bit address of the task in the lower 64K memory space.
3. The CLA executes instructions until the MSTOP instruction is found. This indicates the end of the task.
4. The MIRUN bit is cleared.
5. The task-specific interrupt to the PIE is issued. This informs the main CPU that the task has completed.
6. The CLA returns to idle.
Once a task completes the next highest-priority pending task is automatically serviced and this sequence
repeats.

6.2.5 CLA Software Interrupt to CPU

The CLA can issue a software interrupt to the C28x CPU (on the same subsystem) at any point in the code
through the use of the CLA1SOFTINTEN and CLA1INTFRC registers. See Section 6.8 for a description of these
registers. If a software interrupt is selected for a CLA task, then an end-of-task interrupt is not issued to the C28x
CPU when that task completes.

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6.3 CLA and CPU Arbitration

Typically, CLA activity is independent of the CPU activity. Under the circumstance where the CLA or CPU
attempt to concurrently access memory or a peripheral register within the same interface, an arbitration
procedure occurs. This section describes this arbitration.
The arbitration follows a fixed arbitration scheme with highest priority first:
1. CLA WRITE
2. CLA READ
3. CPU WRITE
4. CPU READ
Refer to the Memory Controller Module section of the System Control and Interrupts chapter.
6.3.1 CLA Message RAM
Message RAMs consist of two blocks:
• CLA to CPU Message RAM
• CPU to CLA Message RAM
These blocks are useful for passing data between the CLA and CPU. No opcode fetches, from either the CLA
or CPU, are allowed from the message RAMs. A write protection violation is not generated if the CLA attempts
to write to the CPU to CLA message RAM, but the write is ignored. The arbitration scheme for the message
RAMs are the same as those for the shared memories, described in the Memory Controller Module section of
the System Control and Interrupts chapter.
The message RAMs have the following characteristics:
• CLA to CPU Message RAM:
The following accesses are allowed:
– CPU reads
– CLA data reads and writes
– CPU debug reads and writes
The following accesses are ignored:
– CPU writes
• CPU to CLA Message RAM:
The following accesses are allowed:
– CPU reads and writes
– CLA reads
– CPU debug reads and writes
The following accesses are ignored:
– CLA writes

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6.3.2 CLA Program Memory

The behavior of the program memory depends on the state of the MMEMCFG[PROGE] bit. This bit controls
whether the memory is mapped to CLA space or CPU space.
• MMEMCFG[PROGE] == 0
In this case, the memory is mapped to the CPU. The CLA is halted and no tasks can be incoming.
– Any CLA fetch is treated as an illegal opcode condition as described in Section 6.4.4. This condition does
not occur, if the proper procedure is followed to map the program memory.
– CLA reads and writes cannot occur
– The memory block behaves as any normal RAM block mapped to CPU memory space.

Priority of accesses are (highest priority first):

1. CPU data write, program write, debug write
2. CPU data read, program read, debug read
3. CPU fetch, program read

• MMEMCFG[PROGE] == 1
In this case, the memory block is mapped to CLA space. The CPU can only make debug accesses.
– CLA reads and writes cannot occur
– CLA fetches are allowed
– CPU fetches return 0 that is an illegal opcode and causes an ITRAP interrupt.
– CPU data reads and program reads return 0
– CPU data writes and program writes are ignored

Priority of accesses are (highest priority first):

1. CLA fetch
2. CPU debug write
3. CPU debug read

Note
Because the CLA fetch has higher priority than CPU debug reads, there is a possibility for the CLA
to permanently block debug accesses if the CLA is executing in a loop. This can occur when initially
developing CLA code due to a bug. To avoid this issue, the program memory returns all 0x0000 for
CPU debug reads (ignore writes) when the CLA is running. When the CLA is halted or idle, then
normal CPU debug read and write access can be performed.

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6.3.3 CLA Data Memory

There are independent data memory blocks. The behavior of the data memory depends on the state of the
MMEMCFG[RAM0E] MMEMCFG[RAM1E] bits. These bits determine whether the memory blocks are mapped to
CLA space or CPU space.
• MMEMCFG[RAMxE] == 0
In this case the memory block is mapped to the CPU.
– CLA fetches cannot occur to this block.
– CLA reads return 0.
– CLA writes are ignored.
– The memory block behaves as any normal RAM block mapped to the CPU memory space.

Priority of accesses are (highest priority first):

1. CPU data write/program write/debug access write
2. CPU data read/debug access read
3. CPU fetch/program read

• MMEMCFG[RAMxE] == 1
In this case the memory block is mapped to CLA space. The CPU can make only debug accesses.
– CLA fetches cannot occur to this block.
– CLA read and CLA writes are allowed.
– CPU fetches return 0
– CPU data reads and program reads return 0.
– CPU data writes and program writes are ignored.

Priority of accesses are (highest priority first):

1. CLA data write
2. CPU debug write
3. CPU debug read
4. CLA read

6.3.4 Peripheral Registers (ePWM, HRPWM, Comparator)

Accesses to the registers follow these rules:
• If both the CPU and CLA request access at the same time, then the CLA has priority and the main CPU is
stalled.
• If a CPU access is in-progress and another CPU access is pending, then the CLA has priority over the
pending CPU access. In this case, the CLA access begins when the current CPU access completes.
• While a CPU access is in-progress, any incoming CLA access is stalled.
• While a CLA access is in-progress, any incoming CPU access is stalled.
• A CPU write operation has priority over a CPU read operation.
• A CLA write operation has priority over a CLA read operation.
• If the CPU is performing a read-modify-write operation and the CLA performs a write to the same location, the
CLA write can be lost if the operation occurs in-between the CPU read and write. For this reason, do not mix
CPU and CLA accesses to same location.

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6.4 CLA Configuration and Debug

This section discusses the steps necessary to configure and debug the CLA.
6.4.1 Building a CLA Application
The control law accelerator can be programmed in either CLA assembly code, using the instructions described
in Section 6.7, or a reduced subset of the C language. CLA assembly code resides in the same project with
C28x code. The only restriction is the CLA code must be in the assembly section. This can be easily done
using the .sect assembly directive. This does not prevent CLA and C28x code from being linked into the same
memory region in the linker command file.
System and CLA initialization are performed by the main CPU. This can typically be done in C or C++ but can
also include C28x assembly code. The main CPU also copies the CLA code to the program memory and, if
needed, initialize the CLA data RAMs. Once system initialization is complete and the application begins, the
CLA services the interrupts using the CLA assembly code (or tasks). The main CPU can perform other tasks
concurrently with CLA program execution.
The CLA Type 1 requires Codegen V6.2.4 or later with the compiler switch: --cla_support=cla1.
6.4.2 Typical CLA Initialization Sequence
A typical CLA initialization sequence is performed by the main CPU as described in this section.
1. Copy CLA code into the CLA program RAM: The source for the CLA code can initially reside in the Flash
or a data stream from a communications peripheral or anywhere the main CPU can access. The debugger
can also be used to load code directly to the CLA program RAM during development.
2. Initialize CLA data RAM, if necessary: Populate the CLA data RAM with any required data coefficients or
constants.
3. Configure the CLA registers: Configure the CLA registers, but keep interrupts disabled until later (leave
MIER = 0):
• Enable the CLA peripheral clock using the assigned PCLKCRn register: The peripheral clock control
(PCLKCRn) registers are defined in the System Control and Interrupts chapter.
• Populate the CLA task interrupt vectors:
– MVECT1 to MVECT8
Each vector needs to be initialized with the start address of the task to be executed when the CLA
receives the associated interrupt. This address is the full 16-bit starting address of the task in the
lower 64K section of memory.
• Select the task interrupt sources: For each task select the interrupt source in the CLA1TASKSRCSELx
register. If a task is software triggered, select no interrupt.
• Enable IACK to start a task from software, if desired: To enable the IACK instruction to start a task set
the MCTL[IACKE] bit. Using the IACK instruction avoids having to set and clear the EALLOW bit.
• Map CLA data RAM to CLA space, if necessary: Map the data RAM to the CLA space by
first, assigning ownership of the memory block to the CLA by writing a 1 to the memory block’s
MemCfgRegs.LSxMSEL[MSEL_LSx] bit, and then specifying the memory block as a CLA data block
by writing a 0 to the MemCfgRegs.LSxCLAPGM[CLAPGM_LSx] bit. When an LSx memory is configured
as a CLA data memory, the CLA read/write accesses are arbitrated along with CPU accesses. The user
has the option of turning on CPU fetch or write protection to the memory by writing to the appropriate bits
of the MemCfgRegs.LSxACCPROTx registers.
• Map CLA program RAM to CLA space: Map the CLA program RAM to CLA space by first
assigning ownership of the memory block to the CLA by writing a 1 to the memory block’s
MemCfgRegs.LSxMSEL[MSEL_LSx] bit, and then specifying the memory block as CLA code memory
by writing a 1 to the MemCfgRegs.LSxCLAPGM[CLAPGM_LSx] bit. When an LSx memory is configured
as CLA program memory, only debug accesses are allowed on cycles in which the CLA is not fetching a
new instruction.
4. Initialize the PIE vector table and registers: When a CLA task completes, the associated interrupt in the
PIE is flagged. The CLA overflow and underflow flags also have associated interrupts within the PIE.

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5. Enable CLA tasks/interrupts: Set appropriate bits in the interrupt enable register (MIER) to allow the CLA
to service interrupts. Note that a CLA task only triggers on a level transition (a falling edge) of the configured
interrupt source. If a peripheral is enabled and an interrupt fires before the CLA is configured, then the CLA
does not recognize the interrupt edge and does not respond. To avoid this, configure the CLA before the
peripherals or clear any pending peripheral interrupts before setting bits in the MIER register.
6. Initialize other peripherals: Initialize any peripherals (such as ePWM, ADC, and others) that generate
interrupt triggers for enabled CLA tasks.
The CLA is now ready to service interrupts and the message RAMs can be used to pass data between the
CPU and the CLA. Mapping of the CLA program and data RAMs typically occurs only during the initialization
process. If the RAM mapping needs to be changed after initialization, the CLA interrupts must be disabled
and all tasks must be completed (by checking the MIRUN register) prior to modifying the RAM ownership.

6.4.3 Debugging CLA Code

Debugging the CLA code is a simple process that occurs independently of the main CPU.
6.4.3.1 Breakpoint Support (MDEBUGSTOP)
1. Insert a breakpoint in CLA code
Insert a CLA breakpoint (MDEBUGSTOP instruction) into the code where the CLA is to halt, then rebuild
and reload the code. Because the CLA does not flush the pipeline when in single-step, the MDEBUGSTOP
instruction must be inserted as part of the code. The debugger cannot insert the MDEBUGSTOP instruction
as needed.
If CLA breakpoints are not enabled, then the MDEBUGSTOP instruction is ignored and is treated
as a MNOP. The MDEBUGSTOP instruction can be placed anywhere in the CLA code as long as
the MDEBUGSTOP instruction is not within three instructions of a MBCNDD, MCCNDD, or MRCNDD
instruction. When programming in C, the user can use the __mdebugstop() intrinsic instead; the compiler
makes sure that the placement of the MDEBUSTOP instruction in the generated assembly does not violate
any of the pipeline restrictions.
2. Enable CLA breakpoints
Enable the CLA breakpoints in the debugger. In the Code Composer Studio™ IDE, this is done by
connecting to the CLA core (or tap) from the debug perspective. Breakpoints are disabled when the core is
disconnected.
3. Start the task
There are three ways to start the task:
a. The peripheral can assert an interrupt,
b. The main CPU can execute an IACK instruction, or
c. The user can manually write to the MIFRC register in the debugger window
When the task starts, the CLA executes instructions until the MDEBUGSTOP is in the D2 phase of the
pipeline. At this point, the CLA halts and the pipeline is frozen. The MPC register reflects the address of the
MDEBUGSTOP instruction.

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4. Single-step the CLA code

Once halted, the user can single-step the CLA code. The behavior of a CLA single-step is different than the
main C28x. When issuing a CLA single-step, the pipeline is clocked only one cycle and then again frozen.
On the C28x CPU, the pipeline is flushed for each single-step.
Run to the next MDEBUGSTOP or to the end of the task. If another task is pending, the task automatically
starts when run to the end of the task.

Note
A CLA fetch has higher priority than CPU debug reads. For this reason, the CLA to permanently
block CPU debug accesses if the CLA is executing in a loop is possible. This can occur when initially
developing CLA code due to a bug that causes an infinite loop. To avoid locking up the main CPU,
the program memory returns all 0x0000 for CPU debug reads when the CLA is running. When the
CLA is halted or idle, then normal CPU debug read and write access to CLA program memory can be
performed.
If the CLA gets caught in an infinite loop, use a soft or hard reset to exit the condition. A debugger
reset also exits the condition.

There are special cases that can occur when single-stepping a task such that the program counter, MPC,
reaches the MSTOP instruction at the end of the task.
• MPC halts at or after the MSTOP with a task already pending
If single-stepping or halted in "task A" and "task B" comes in before the MPC reaches the MSTOP, then
"task B" starts if continuing to step through the MSTOP instruction. Basically, if "task B" is pending before
the MPC reaches MSTOP in "task A" then there is no issue in "task B" starting and no special action is
required.
• MPC halts at or after the MSTOP with no task pending
In this case, if single-stepped or halted in "task A" and the MPC has reached the MSTOP with no tasks
pending. If "task B" comes in at this point, "task B" is flagged in the MIFR register but "task B" can or
cannot start if continuing to single-step through the MSTOP instruction of "task A."
Depending on exactly when the new task comes in, to reliably start "task B", perform a soft reset and
reconfigure the MIER bits. Once this is done, start single-stepping "task B."
This case can be handled slightly differently if there is control over when "task B" comes in (for example,
using the IACK instruction to start the task). In this case, the task is single-stepped or halted in "task A"
and the MPC has reached the MSTOP with no tasks pending. Before forcing "task B," run free to force
the CLA out of the debug state. Once this is done, force "task B" and continue debugging.
5. Disable CLA breakpoints, if desired
In the Code Composer Studio™ IDE, disable the CLA breakpoints by disconnecting the CLA core in the
debug perspective. Make sure to first issue a run or reset; otherwise, the CLA is halted and no other tasks
start.

6.4.4 CLA Illegal Opcode Behavior

If the CLA fetches an opcode that does not correspond to a legal instruction, the CLA behaves as follows:
• The CLA halts with the illegal opcode in the D2 phase of the pipeline as if a breakpoint. This occurs whether
CLA breakpoints are enabled or not.
• The CLA issues the task-specific interrupt to the PIE.
• The MIRUN bit for the task remains set.
Further single-stepping is ignored once execution halts due to an illegal op-code. To exit this situation, issue
either a soft or hard reset of the CLA as described in Section 6.4.5.

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6.4.5 Resetting the CLA

There are times when resetting the CLA is needed. For example, during code debug the CLA can enter an
infinite loop due to a code bug. The CLA has two types of resets: hard and soft. Both of these resets can be
performed by the debugger or by the main CPU.
• Hard Reset Writing a 1 to the MCTL[HARDRESET] bit performs a hard reset of the CLA. The behavior of a
hard reset is the same as a system reset (using XRS or the debugger). In this case, all CLA configuration and
execution registers can be set to the default state and CLA execution halts.
• Soft Reset Writing a 1 to the MCTL[SOFTRESET] bit performs a soft reset of the CLA. If a task is executing,
the task halts and the associated MIRUN bit is cleared. All bits within the interrupt enable (MIER) register are
also cleared, so that no new tasks start.

6.5 Pipeline
This section describes the CLA pipeline stages and presents cases where pipeline alignment must be
considered.
6.5.1 Pipeline Overview
The CLA pipeline is very similar to the C28x pipeline with eight stages:
1. Fetch 1 (F1): During the F1 stage the program read address is placed on the CLA program address bus.
2. Fetch 2 (F2): During the F2 stage the instruction is read using the CLA program data bus.
3. Decode 1 (D1): During D1 the instruction is decoded.
4. Decode 2 (D2): Generate the data read address. Changes to MAR0 and MAR1 due to post-increment using
indirect addressing takes place in the D2 phase. Conditional branch decisions are also made at this stage
based on the MSTF register flags.
5. Read 1 (R1): Place the data read address on the CLA data-read address bus. If a memory conflict exists,
the R1 stage is stalled.
6. Read 2 (R2): Read the data value using the CLA data read data bus.
7. Execute (EXE): Execute the operation. Changes to MAR0 and MAR1 due to loading an immediate value or
value from memory take place in this stage.
8. Write (W): Place the write address and write data on the CLA write data bus. If a memory conflict exists, the
W stage is stalled.

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6.5.2 CLA Pipeline Alignment

The majority of the CLA instructions do not require any special pipeline considerations. This section lists the few
operations that do require special consideration.
• Write Followed by Read
In both the C28x pipeline and the CLA pipeline, the read operation occurs before the write. This means that
if a read operation immediately follows a write, then the read completes first as shown in Table 6-2. In most
cases this does not cause a problem since the contents of one memory location does not depend on the
state of another. For accesses to peripherals where a write to one location can affect the value in another
location, the code must wait for the write to complete before issuing the read as shown in Table 6-3.
This behavior is different for the C28x CPU. For the C28x CPU, any write followed by read to the same
location is protected by what is called write-followed-by-read protection. This protection automatically stalls
the pipeline so that the write completes before the read. In addition, some peripheral frames are protected
such that a C28x CPU write to one location within the frame always completes before a read to the frame.
The CLA does not have this protection mechanism. Instead, the code must wait to perform the read.
Table 6-2. Write Followed by Read - Read Occurs First
Instruction F1 F2 D1 D2 R1 R2 E W
I1 MMOV16 @Reg1, MR3 I1
I2 MMOV16 MR2, @Reg2 I2 I1
I2 I1
I2 I1
I2 I1
I2 I1
I2 I1
I2 I1

Table 6-3. Write Followed by Read - Write Occurs First

Instruction F1 F2 D1 D2 R1 R2 E W
I1 MMOV16 @Reg1, MR3 I1
I2 I2 I1
I3 I3 I2 I1
I4 I4 I3 I2 I1
I5 MMOV16 MR2, @Reg2 I5 I4 I3 I2 I1
I5 I4 I3 I2 I1
I5 I4 I3 I2 I1
I5 I4 I3 I2 I1
I5 I4 I3
I5 I4
I5

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• Delayed Conditional instructions: MBCNDD, MCCNDD, and MRCNDD

Referring to Example 6-1, the following applies to delayed conditional instructions:
– I1: I1 is the last instruction that can effect the CNDF flags for the branch, call, or return instruction. The
CNDF flags are tested in the D2 phase of the pipeline. That is, a decision is made whether to branch or
not when MBCNDD, MCCNDD, or MRCNDD is in the D2 phase.
– I2, I3, and I4: The three instructions preceding MBCNDD can change the MSTF flags but have no effect
on whether the MBCNDD instruction branches or not. This is because the flag modification occurs after
the D2 phase of the branch, call, or return instruction. These three instructions must not be a MSTOP,
MDEBUGSTOP, MBCNDD, MCCNDD, or MRCNDD.
– I5, I6, and I7: The three instructions following a branch, call, or return are always executed irrespective of
whether the condition is true or not. These instructions must not be MSTOP, MDEBUGSTOP, MBCNDD,
MCCNDD, or MRCNDD.
For a more detailed description, refer to the description for MBCNDD, MCCNDD, and MRCNDD.

Example 6-1. Code Fragment For MBCNDD, MCCNDD, or MRCNDD

<Instruction 1> ; I1 Last instruction that can affect flags for

; the branch, call or return operation
<Instruction 2> ; I2 Cannot be stop, branch, call or return
<Instruction 3> ; I3 Cannot be stop, branch, call or return
<Instruction 4> ; I4 Cannot be stop, branch, call or return
<branch/call/ret> ; MBCNDD, MCCNDD or MRCNDD
; I5-I7: Three instructions after are always
; executed whether the branch/call or return is
; taken or not
<Instruction 5> ; I5 Cannot be stop, branch, call or return
<Instruction 6> ; I6 Cannot be stop, branch, call or return
<Instruction 7> ; I7 Cannot be stop, branch, call or return
<Instruction 8> ; I8
<Instruction 9> ; I9
....

• Stop or Halting a Task: MSTOP and MDEBUGSTOP

The MSTOP and MDEBUGSTOP instructions cannot be placed three instructions before or after a conditional
branch, call or return instruction (MBCNDD, MCCNDD, or MRCNDD). Refer to Example 6-1. To single-step
through a branch/call or return, insert the MDEBUGSTOP at least four instructions back and step from there.

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• Loading MAR0 or MAR1

A load of auxiliary register MAR0 or MAR1 occurs in the EXE phase of the pipeline. Any post increment of
MAR0 or MAR1 using indirect addressing occurs in the D2 phase of the pipeline. Referring to Example 6-2,
the following applies when loading the auxiliary registers:
– I1 and I2: The two instructions following the load instruction use the value in MAR0 or MAR1 before the
update occurs.
– I3: Loading of an auxiliary register occurs in the EXE phase while updates due to post-increment
addressing occur in the D2 phase. Thus I3 cannot use the auxiliary register or there is a conflict. In
the case of a conflict, the update due to address-mode post increment wins and the auxiliary register is
not updated with #_X.
– I4: Starting with the 4th instruction MAR0 or MAR1 has the new value.

Example 6-2. Code Fragment for Loading MAR0 or MAR1

; Assume MAR0 is 50 and #_X is 20

MMOVI16 MAR0, #_X ; Load MAR0 with address of X (20)

<Instruction 1> ; I1 uses the old value of MAR0 (50)
<Instruction 2> ; I2 uses the old value of MAR0 (50)
<Instruction 3> ; I3 Cannot use MAR0
<Instruction 4> ; I4 uses the new value of MAR0 (20)
<Instruction 5> ; I5 uses the new value of MAR0 (20)
....

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6.5.2.1 ADC Early Interrupt to CLA Response

The ADC can be configured to generate an early interrupt pulse before the ADC conversion completes. If this
option is used to start a CLA task, the CLA is able to read the result as soon as the conversion result is available
in the ADC result register. This combination of just-in-time sampling along with the low interrupt response of the
CLA enable faster system response and higher frequency control loops. The CLA task trigger to first instruction
fetch interrupt latency is 4 cycles.
Timings for ADC conversions are shown in the timing diagrams of the ADC chapter. If the ADCCLK is a divided
down version of the SYSCLK, the user has to account for the conversion time in SYSCLK cycles.
For example, if using the 12-bit ADC with ADCCLK at SYSCLK / 4, the ADC can take 10.5 ADCCLK x 4
SYSCLK = 42 SYSCLK cycles to complete a conversion. If using the ADC in 16-bit mode at the same ADCCLK,
the ADC can take 29.5 ADCCLK x 4 SYSCLK = 118 SYSCLK cycles, and so on.
From a CLA perspective, the pipeline activity is shown in Table 6-4 for an N-cycle (SYSCLK) ADC conversion.
The N-2 instruction arrives in the R2 phase just in time to read the result register. While the prior instructions
enter the R2 phase of the pipeline too soon to read the conversion, the instructions can be efficiently used for
pre-processing calculations needed by the task.
Table 6-4. ADC to CLA Early Interrupt Response
ADC Activity CLA Activity F1 F2 D1 D2 R1 R2 E W
Sample
Sample
...
Sample
Conversion(Cycle 1) Interrupt Received
Conversion(Cycle 2) Task Startup
Conversion(Cycle 3) Task Startup
Conversion(Cycle 4) I(Cycle 4) I(Cycle 4)
Conversion(Cycle 5) I(Cycle 5) I(Cycle 5) I(Cycle 4)
Conversion(...) ... ... ... ... ... ... ...
Conversion(Cycle N-6) I(Cycle N-6) I(Cycle N-6) I(Cycle N-7) I(Cycle N-8) I(Cycle N-9) I(Cycle N-10) I(Cycle N-11)
Conversion(Cycle N-5) I(Cycle N-5) I(Cycle N-5) I(Cycle N-6) I(Cycle N-7) I(Cycle N-8) I(Cycle N-9) I(Cycle N-10)
Conversion(Cycle N-4) I(Cycle N-4) I(Cycle N-4) I(Cycle N-5) I(Cycle N-6) I(Cycle N-7) I(Cycle N-8) I(Cycle N-9)
Conversion(Cycle N-3) I(Cycle N-3) I(Cycle N-3) I(Cycle N-4) I(Cycle N-5) I(Cycle N-6) I(Cycle N-7) I(Cycle N-8)
Read
Conversion(Cycle N-2) Read RESULT I(Cycle N-3) I(Cycle N-4) I(Cycle N-5) I(Cycle N-6) I(Cycle N-7)
RESULT
Read
Conversion(Cycle N-1) I(Cycle N-3) I(Cycle N-4) I(Cycle N-5) I(Cycle N-6)
RESULT
Read
Conversion(Cycle N-0) I(Cycle N-3) I(Cycle N-4) I(Cycle N-5)
RESULT
Read
Conversion Complete I(Cycle N-3) I(Cycle N-4)
RESULT
Read
RESULT Latched I(Cycle N-3)
RESULT
Read
RESULT Available
RESULT

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6.5.3 Parallel Instructions

Parallel instructions are single opcodes that perform two operations in parallel. The following types of parallel
instructions are available: math operation in parallel with a move operation, or two math operations in parallel.
Both operations complete in a single cycle and there are no special pipeline alignment requirements.
Example 6-3. Math Operation with Parallel Load

; MADDF32 || MMOV32 instruction: 32-bit floating-point add with parallel move

; MADDF32 is a 1 cycle operation
; MMOV32 is a 1 cycle operation
MADDF32 MR0, MR1, #2 ; MR0 = MR1 + 2,
|| MMOV32 MR1, @Val ; MR1 gets the contents of Val
; <-- MMOV32 completes here (MR1 is valid)
; <-- DDF32 completes here (MR0 is valid)
MMPYF32 MR0, MR0, MR1 ; Any instruction, can use MR1 and/or MR0

Example 6-4. Multiply with Parallel Add

; MMPYF32 || MADDF32 instruction: 32-bit floating-point multiply with parallel add

; MMPYF32 is a 1 cycle operation
; MADDF32 is a 1 cycle operation
MMPYF32 MR0, MR1, MR3 ; MR0 = MR1 * MR3
|| MADDF32 MR1, MR2, MR0 ; MR1 = MR2 + MR0 (Uses value of MR0 before MMPYF32)
; <-- MMPYF32 and MADDF32 complete here (MR0 and MR1 are valid)
MMPYF32 MR1, MR1, MR0 ; Any instruction, can use MR1 and/or MR0

6.5.4 CLA Task Execution Latency

The CLA task execution latency depends on the state of the system:
• CLA task trigger of new task (normal or background) without background task active:
Task takes 8 cycles from CLA task trigger to first instruction of task to reach the D2 phase of pipeline.

Note
If background task has been configured in the system, then the compiler during code compilation
adds context save instructions at the start of each regular task and restore instructions at end of each
task so that register content can be saved and restored in case a background task is executing while
the regular task is triggered. When a regular task is entered, this compiler-generated context save
instruction is the first instruction of the task.

• CLA task trigger of normal task when background task is active:

Task takes 9 cycles from CLA task trigger to first instruction of normal task to reach the D2 phase of pipeline.
There is a difference of one clock cycle to force the MSTOP in the D2 phase of the background task before
the task exits as compared to a new task trigger without the background task active.

Note
If the MBCNDD/MCCNDD/MRCNDD instructions in the background task are in the D2 phase of the
pipeline when a new task gets triggered, the task takes a minimum of 3 more cycles to complete these
uninterruptible instructions adding to the delay.

• Returning to background task from normal task:

The task takes 5 cycles to return from a normal task to resume the background task instruction at the D2
phase of the pipeline.

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6.6 Software
6.6.1 CLA Examples
NOTE: These examples are located in the C2000Ware installation at the following location:
C2000Ware_VERSION#/driverlib/DEVICE_GPN/examples/CORE_IF_MULTICORE/cla
Cloud access to these examples is available at the following link: dev.ti.com C2000Ware Examples.
6.6.1.1 CLA arcsine(x) using a lookup table (cla_asin_cpu01)
FILE: cla_ex1_asin.c
In this example, Task 1 of the CLA will calculate the arcsine of an input argument in the range (-1.0 to 1.0) using
a lookup table.

Memory Allocation
• CLA1 Math Tables (RAMLS0)
• CLA1 to CPU Message RAM
– fResult - Result of the lookup algorithm
• CPU to CLA1 Message RAM
– fVal - Sample input to the lookup algorithm
Watch Variables
• fVal - Argument to task 1
• fResult - Result of arcsin(fVal)
6.6.1.2 CLA arctangent(x) using a lookup table (cla_atan_cpu01)
FILE: cla_ex2_atan.c
In this example, Task 1 of the CLA will calculate the arctangent of an input argument using a lookup table.

Memory Allocation
• CLA1 Math Tables (RAMLS0)
• CLA1 to CPU Message RAM
– fResult - Result of the lookup algorithm
• CPU to CLA1 Message RAM
– fNum - Numerator of sample input
– fDen - Denominator of sample input
Watch Variables
• fVal - Argument to task 1
• fResult - Result of arctan(fVal)

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6.7 Instruction Set

This section describes the assembly language instructions of the control law accelerator. Also described are
parallel operations, conditional operations, resource constraints, and addressing modes. The instructions listed
here are independent from C28x and C28x+FPU instruction sets.
6.7.1 Instruction Descriptions
This section gives detailed information on the instruction set. Each instruction presents the following information:
• Operands
• Opcode
• Description
• Exceptions
• Pipeline
• Examples
• See also
The example INSTRUCTION is shown to familiarize you with the way each instruction is described. The example
describes the kind of information you find in each part of the individual instruction description and where to
obtain more information. CLA instructions follow the same format as the C28x instructions; the source operands
are always on the right and the destination operands are on the left.
The explanations for the syntax of the operands used in the instruction descriptions for the CLA are given in
Table 6-5.
Table 6-5. Operand Nomenclature
Symbol Description
#16FHi 16-bit immediate (hex or float) value that represents the upper 16-bits of an IEEE 32-bit floating-point value.
Lower 16-bits of the mantissa are assumed to be zero.
#16FHiHex 16-bit immediate hex value that represents the upper 16-bits of an IEEE 32-bit floating-point value.
Lower 16-bits of the mantissa are assumed to be zero.
#16FLoHex A 16-bit immediate hex value that represents the lower 16-bits of an IEEE 32-bit floating-point value
#32Fhex 32-bit immediate value that represents an IEEE 32-bit floating-point value
#32F Immediate float value represented in floating-point representation
#0.0 Immediate zero
#SHIFT Immediate value of 1 to 32 used for arithmetic and logical shifts.
addr Opcode field indicating the addressing mode
CNDF Condition to test the flags in the MSTF register
FLAG Selected flags from MSTF register (OR) 8 bit mask indicating which floating-point status flags to change
MAR0 Auxiliary register 0
MAR1 Auxiliary register 1
MARx Either MAR0 or MAR1
mem16 16-bit memory location accessed using direct, indirect, or offset addressing modes
mem32 32-bit memory location accessed using direct, indirect, or offset addressing modes
MRa MR0 to MR3 registers
MRb MR0 to MR3 registers
MRc MR0 to MR3 registers
MRd MR0 to MR3 registers
MRe MR0 to MR3 registers
MRf MR0 to MR3 registers
MSTF CLA Floating-point Status Register
shift Opcode field indicating the number of bits to shift.
VALUE Flag value of 0 or 1 for selected flag (OR) 8 bit mask indicating the flag value; 0 or 1

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Each instruction has a table that gives a list of the operands and a short description. Instructions always have
the destination operands first followed by the source operands.
Table 6-6. INSTRUCTION dest, source1, source2 Short Description
Description
dest1 Description for the 1st operand for the instruction
source1 Description for the 2nd operand for the instruction
source2 Description for the 3rd operand for the instruction
Opcode This section shows the opcode for the instruction
Description Detailed description of the instruction execution is described. Any constraints on the operands imposed by the
processor or the assembler are discussed.
Restrictions Any constraints on the operands or use of the instruction imposed by the processor are discussed.
Pipeline This section describes the instruction in terms of pipeline cycles as described in Section 6.5
Example Examples of instruction execution. If applicable, register and memory values are given before and after instruction
execution. Some examples are code fragments while other examples are full tasks that assume the CLA is correctly
configured and the main CPU has passed the CLA data.
Operands Each instruction has a table that gives a list of the operands and a short description. Instructions always have the
destination operands first followed by the source operands.

6.7.2 Addressing Modes and Encoding

The CLA uses the same address to access data and registers as the main CPU. For example, if the main CPU
accesses an ePWM register at address 0x00 6800, then the CLA accesses the register using address 0x6800.
Since all CLA accessible memory and registers are within the low 64k x 16 of memory, only the low 16-bits of the
address are used by the CLA.
To address the CLA data memory, message RAMs and shared peripherals, the CLA supports two addressing
modes:
• Direct addressing mode: Uses the address of the variable or register directly.
• Indirect addressing with 16-bit post increment. This mode uses either XAR0 or XAR1.
The CLA does not use a data page pointer or a stack pointer. The two addressing modes are encoded as shown
Table 6-7.

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Table 6-7. Addressing Modes

Addressing Mode 'addr' Opcode Description
Field
Encode(1)
@dir 0000 Direct Addressing Mode
Example 1: MMOV32 MR1, @_VarA
Example 2: MMOV32 MR1, @_EPwm1Regs.CMPA.all
In this case, the 'mmmm mmmm mmmm mmmm' opcode field is populated with the 16-bit
address of the variable. This is the low 16-bits of the address to access the variable using the
main CPU.
For example, @_VarA populates the address of the variable VarA. and
@_EPwm1Regs.CMPA.all populates the address of the CMPA register.
*MAR0[#imm16]++ 0001 MAR0 Indirect Addressing with 16-bit Immediate Post Increment
*MAR1[#imm16]++ 0010 MAR1 Indirect Addressing with 16-bit Immediate Post Increment
addr = MAR0 (or MAR1) Access memory using the address stored in MAR0 (or MAR1).
MAR0 (or MAR1) += Then post increment MAR0 (or MAR1) by #imm16.
#imm16
Example 1: MMOV32 MR0, *MAR0[2]++
Example 2: MMOV32 MR1, *MAR1[-2]++
For a post increment of 0, the assembler accepts both *MAR0 and *MAR0[0]++.
The 'mmmm mmmm mmmm mmmm' opcode field is populated with the signed 16-bit pointer
offset. For example, if #imm16 is 2, then the opcode field is 0x0002. Likewise, if #imm16 is -2,
then the opcode field is 0xFFFE.
If addition of the 16-bit immediate causes overflow, then the value wraps around on a 16-bit
boundary.
*MAR0+[#imm16] 0101 MAR0 Offset Addressing with 16-bit Immediate Offset
*MAR1+[#imm16] 0110 MAR1 Offset Addressing with 16-bit Immediate Offset
addr = MAR0 Add the offset #imm16
(or MAR1) + #imm16to address stored in MAR0(MAR1) to access the desired memory
the base location
Example 1: MMOV32 MR0, *MAR0+[2]
Example 1: MMOV32 MR1, *MAR1+[-2]
The ‘mmmm mmmm mmmm mmmm’ opcode field is populated with the signed 16-bit pointer
offset. For example, if #imm16 is 2, then the opcode field is 0x0002. Likewise, if #imm16 is -2,
then the opcode field is 0xFFFE.
If the addition of the 16-bit immediate causes overflow, the value wraps around on a 16-bit
boundary.

(1) Values not shown are reserved.

Encoding for the shift fields in the MASR32, MLSR32 and MLSL32 instructions is shown in Table 6-8.
Table 6-8. Shift Field Encoding
Shift Value 'shift' Opcode
Field Encode
1 0000
2 0001
3 0010
.... ....
32 1111

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For instructions that use MRx (where x can be 'a' through 'f') as operands, the trailing alphabet appears in the
opcode as a two-bit field. For example:

MMPYF32 MRa, MRb, MRc ||

MADDF32 MRd, MRe, MRf

whose opcode is,

LSW: 0000 ffee ddcc bbaa

MSW: 0111 1010 0000 0000

The two-bit field specifies one of four working registers according to Table 6-9.
Table 6-9. Operand Encoding
Two-Bit Field Working Register
00 MR0
01 MR1
10 MR2
11 MR3

Table 6-10 shows the condition field encoding for conditional instructions such as MNEGF, MSWAPF, MBCNDD,
MCCNDD, and MRCNDD.
Table 6-10. Condition Field Encoding
Encode(1) CNDF Description MSTF Flags Tested
0000 NEQ Not equal to zero ZF == 0
0001 EQ Equal to zero ZF == 1
0010 GT Greater than zero ZF == 0 AND NF == 0
0011 GEQ Greater than or equal to zero NF == 0
0100 LT Less than zero NF == 1
0101 LEQ Less than or equal to zero ZF == 1 OR NF == 1
1010 TF Test flag set TF == 1
1011 NTF Test flag not set TF == 0
1100 LU Latched underflow LUF == 1
1101 LV Latched overflow LVF == 1
1110 UNC Unconditional None
1111 UNCF(2) Unconditional with flag modification None

(1) Values not shown are reserved.

(2) This is the default operation, if no CNDF field is specified. This condition allows the ZF and NF flags to be modified when a conditional
operation is executed. All other conditions do not modify these flags.

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6.7.3 Instructions
The instructions are listed alphabetically.

Instruction Set Summary

MABSF32 MRa, MRb — 32-Bit Floating-Point Absolute Value...........................................................................745
MADD32 MRa, MRb, MRc — 32-Bit Integer Add................................................................................................746
MADDF32 MRa, #16FHi, MRb — 32-Bit Floating-Point Addition........................................................................747
MADDF32 MRa, MRb, #16FHi — 32-Bit Floating-Point Addition........................................................................749
MADDF32 MRa, MRb, MRc — 32-Bit Floating-Point Addition............................................................................751
MADDF32 MRd, MRe, MRf||MMOV32 mem32, MRa — 32-Bit Floating-Point Addition with Parallel Move...... 752
MADDF32 MRd, MRe, MRf ||MMOV32 MRa, mem32 — 32-Bit Floating-Point Addition with Parallel Move..... 753
MAND32 MRa, MRb, MRc — Bitwise AND.........................................................................................................755
MASR32 MRa, #SHIFT — Arithmetic Shift Right................................................................................................ 756
MBCNDD 16BitDest {, CNDF} — Branch Conditional Delayed......................................................................... 758
MCCNDD 16BitDest {, CNDF} — Call Conditional Delayed...............................................................................763
MCMP32 MRa, MRb — 32-Bit Integer Compare for Equal, Less Than or Greater Than....................................767
MCMPF32 MRa, MRb — 32-Bit Floating-Point Compare for Equal, Less Than or Greater Than.......................769
MCMPF32 MRa, #16FHi — 32-Bit Floating-Point Compare for Equal, Less Than or Greater Than...................770
MDEBUGSTOP — Debug Stop Task.................................................................................................................. 772
MEALLOW — Enable CLA Write Access to EALLOW Protected Registers....................................................... 773
MEDIS — Disable CLA Write Access to EALLOW Protected Registers............................................................. 774
MEINVF32 MRa, MRb — 32-Bit Floating-Point Reciprocal Approximation.........................................................775
MEISQRTF32 MRa, MRb — 32-Bit Floating-Point Square-Root Reciprocal Approximation.............................. 777
MF32TOI16 MRa, MRb — Convert 32-Bit Floating-Point Value to 16-Bit Integer............................................... 779
MF32TOI16R MRa, MRb — Convert 32-Bit Floating-Point Value to 16-Bit Integer and Round..........................780
MF32TOI32 MRa, MRb — Convert 32-Bit Floating-Point Value to 32-Bit Integer............................................... 781
MF32TOUI16 MRa, MRb — Convert 32-Bit Floating-Point Value to 16-bit Unsigned Integer ............................783
MF32TOUI16R MRa, MRb — Convert 32-Bit Floating-Point Value to 16-bit Unsigned Integer and Round....... 784
MF32TOUI32 MRa, MRb — Convert 32-Bit Floating-Point Value to 32-Bit Unsigned Integer ........................... 785
MFRACF32 MRa, MRb — Fractional Portion of a 32-Bit Floating-Point Value................................................... 786
MI16TOF32 MRa, MRb — Convert 16-Bit Integer to 32-Bit Floating-Point Value .............................................. 787
MI16TOF32 MRa, mem16 — Convert 16-Bit Integer to 32-Bit Floating-Point Value ......................................... 788
MI32TOF32 MRa, mem32 — Convert 32-Bit Integer to 32-Bit Floating-Point Value ......................................... 789
MI32TOF32 MRa, MRb — Convert 32-Bit Integer to 32-Bit Floating-Point Value .............................................. 790
MLSL32 MRa, #SHIFT — Logical Shift Left........................................................................................................ 791
MLSR32 MRa, #SHIFT — Logical Shift Right..................................................................................................... 793
MMACF32 MR3, MR2, MRd, MRe, MRf ||MMOV32 MRa, mem32 — 32-Bit Floating-Point Multiply and
Accumulate with Parallel Move............................................................................................................................ 794
MMAXF32 MRa, MRb — 32-Bit Floating-Point Maximum...................................................................................797
MMAXF32 MRa, #16FHi — 32-Bit Floating-Point Maximum...............................................................................799
MMINF32 MRa, MRb — 32-Bit Floating-Point Minimum..................................................................................... 801
MMINF32 MRa, #16FHi — 32-Bit Floating-Point Minimum................................................................................. 803
MMOV16 MARx, MRa, #16I — Load the Auxiliary Register with MRa + 16-bit Immediate Value...................... 805
MMOV16 MARx, mem16 — Load MAR1 with 16-bit Value................................................................................ 808
MMOV16 mem16, MARx — Move 16-Bit Auxiliary Register Contents to Memory............................................. 811
MMOV16 mem16, MRa — Move 16-Bit Floating-Point Register Contents to Memory....................................... 812
MMOV32 mem32, MRa — Move 32-Bit Floating-Point Register Contents to Memory ...................................... 814
MMOV32 mem32, MSTF — Move 32-Bit MSTF Register to Memory.................................................................816
MMOV32 MRa, mem32 {, CNDF} — Conditional 32-Bit Move........................................................................... 817
MMOV32 MRa, MRb {, CNDF} — Conditional 32-Bit Move................................................................................819
MMOV32 MSTF, mem32 — Move 32-Bit Value from Memory to the MSTF Register.........................................821
MMOVD32 MRa, mem32 — Move 32-Bit Value from Memory with Data Copy..................................................822
MMOVF32 MRa, #32F — Load the 32-Bits of a 32-Bit Floating-Point Register.................................................. 824

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MMOVI16 MARx, #16I — Load the Auxiliary Register with the 16-Bit Immediate Value.................................... 826
MMOVI32 MRa, #32FHex — Load the 32-Bits of a 32-Bit Floating-Point Register with the Immediate............. 828
MMOVIZ MRa, #16FHi — Load the Upper 16-Bits of a 32-Bit Floating-Point Register ......................................830
MMOVZ16 MRa, mem16 — Load MRx with 16-Bit Value...................................................................................831
MMOVXI MRa, #16FLoHex — Move Immediate Value to the Lower 16-Bits of a Floating-Point Register.........832
MMPYF32 MRa, MRb, MRc — 32-Bit Floating-Point Multiply.............................................................................833
MMPYF32 MRa, #16FHi, MRb — 32-Bit Floating-Point Multiply ....................................................................... 834
MMPYF32 MRa, MRb, #16FHi — 32-Bit Floating-Point Multiply ....................................................................... 836
MMPYF32 MRa, MRb, MRc||MADDF32 MRd, MRe, MRf — 32-Bit Floating-Point Multiply with Parallel Add...838
MMPYF32 MRd, MRe, MRf ||MMOV32 MRa, mem32 — 32-Bit Floating-Point Multiply with Parallel Move...... 840
MMPYF32 MRd, MRe, MRf ||MMOV32 mem32, MRa — 32-Bit Floating-Point Multiply with Parallel Move...... 842
MMPYF32 MRa, MRb, MRc ||MSUBF32 MRd, MRe, MRf — 32-Bit Floating-Point Multiply with Parallel Subtract
.............................................................................................................................................................................843
MNEGF32 MRa, MRb{, CNDF} — Conditional Negation....................................................................................845
MNOP — No Operation....................................................................................................................................... 847
MOR32 MRa, MRb, MRc — Bitwise OR............................................................................................................. 848
MRCNDD {CNDF} — Return Conditional Delayed..............................................................................................849
MSETFLG FLAG, VALUE — Set or Clear Selected Floating-Point Status Flags............................................... 852
MSTOP — Stop Task...........................................................................................................................................853
MSUB32 MRa, MRb, MRc — 32-Bit Integer Subtraction.................................................................................... 855
MSUBF32 MRa, MRb, MRc — 32-Bit Floating-Point Subtraction.......................................................................856
MSUBF32 MRa, #16FHi, MRb — 32-Bit Floating-Point Subtraction...................................................................857
MSUBF32 MRd, MRe, MRf ||MMOV32 MRa, mem32 — 32-Bit Floating-Point Subtraction with Parallel Move....
859
MSUBF32 MRd, MRe, MRf ||MMOV32 mem32, MRa — 32-Bit Floating-Point Subtraction with Parallel Move....
860
MSWAPF MRa, MRb {, CNDF} — Conditional Swap......................................................................................... 861
MTESTTF CNDF — Test MSTF Register Flag Condition....................................................................................863
MUI16TOF32 MRa, mem16 — Convert Unsigned 16-Bit Integer to 32-Bit Floating-Point Value........................865
MUI16TOF32 MRa, MRb — Convert Unsigned 16-Bit Integer to 32-Bit Floating-Point Value............................ 866
MUI32TOF32 MRa, mem32 — Convert Unsigned 32-Bit Integer to 32-Bit Floating-Point Value........................867
MUI32TOF32 MRa, MRb — Convert Unsigned 32-Bit Integer to 32-Bit Floating-Point Value............................ 868
MXOR32 MRa, MRb, MRc — Bitwise Exclusive Or............................................................................................ 869

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MABSF32 MRa, MRb

32-Bit Floating-Point Absolute Value

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1110 0010 0000

Description
The absolute value of MRb is loaded into MRa. Only the sign bit of the operand is
modified by the MABSF32 instruction.

if (MRb < 0) {MRa = -MRb};

else {MRa = MRb};

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified as follows:

NF = 0;
ZF = 0;
if ( MRa(30:23) == 0) ZF = 1;

Pipeline
This is a single-cycle instruction.

Example
MMOVIZ MR0, #-2.0 ; MR0 = -2.0 (0xC0000000)
MABSF32 MR0, MR0 ; MR0 = 2.0 (0x40000000), ZF = NF = 0
MMOVIZ MR0, #5.0 ; MR0 = 5.0 (0x40A00000)
MABSF32 MR0, MR0 ; MR0 = 5.0 (0x40A00000), ZF = NF = 0
MMOVIZ MR0, #0.0 ; MR0 = 0.0
MABSF32 MR0, MR0 ; MR0 = 0.0 ZF = 1, NF = 0

See also
MNEGF32 MRa, MRb {, CNDF}

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MADD32 MRa, MRb, MRc

32-Bit Integer Add

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point destination register (MR0 to MR3)
MRc CLA floating-point destination register (MR0 to MR3)

Opcode
LSW: 0000 0000 000cc bbaa
MSW: 0111 1110 1100 0000

Description
32-bit integer addition of MRb and MRc.

MRa(31:0) = MRb(31:0) + MRc(31:0);

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified based on the integer results of the operation.

NF = MRa(31);
ZF = 0;
if(MRa(31:0) == 0) { ZF = 1; };

Pipeline
This is a single-cycle instruction.

Example
; Given A = (int32)1
; B = (int32)2
; C = (int32)-7
;
; Calculate Y2 = A + B + C
;
_Cla1Task1:
MMOV32 MR0, @_A ; MR0 = 1 (0x00000001)
MMOV32 MR1, @_B ; MR1 = 2 (0x00000002)
MMOV32 MR2, @_C ; MR2 = -7 (0xFFFFFFF9)
MADD32 MR3, MR0, MR1 ; A + B
MADD32 MR3, MR2, MR3 ; A + B + C = -4 (0xFFFFFFFC)
MMOV32 @_y2, MR3 ; Store y2
MSTOP ; end of task

See also
MAND32 MRa, MRb, MRc
MASR32 MRa, #SHIFT
MLSL32 MRa, #SHIFT
MLSR32 MRa, #SHIFT
MOR32 MRa, MRb, MRc
MXOR32 MRa, MRb, MRc
MSUB32 MRa, MRb, MRc

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MADDF32 MRa, #16FHi, MRb

32-Bit Floating-Point Addition

Operands MRa CLA floating-point destination register (MR0 to MR3)

#16FHi A 16-bit immediate value that represents the upper 16-bits of an
IEEE 32-bit floating-point value. The low 16-bits of the mantissa
are assumed to be all 0.
MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: IIII IIII IIII IIII
MSW: 0111 0111 1100 bbaa

Description
Add MRb to the floating-point value represented by the immediate operand. Store the
result of the addition in MRa.
#16FHi is a 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit
floating-point value. The low 16-bits of the mantissa are assumed to be all 0. #16FHi is
most useful for representing constants where the lowest 16-bits of the mantissa are 0.
Some examples are 2.0 (0x40000000), 4.0 (0x40800000), 0.5 (0x3F000000), and -1.5
(0xBFC00000). The assembler accepts either a hex or float as the immediate value. That
is, the value -1.5 can be represented as #-1.5 or #0xBFC0.

MRa = MRb + #16FHi:0;

This instruction can also be written as MADDF32 MRa, MRb, #16FHi.

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MADDF32 generates an underflow condition.
• LVF = 1 if MADDF32 generates an overflow condition.

Pipeline
This is a single-cycle instruction.

Example
; Add to MR1 the value 2.0 in 32-bit floating-point format
; Store the result in MR0
MADDF32 MR0, #2.0, MR1 ; MR0 = 2.0 + MR1
; Add to MR3 the value -2.5 in 32-bit floating-point format
; Store the result in MR2
MADDF32 MR2, #-2.5, MR3 ; MR2 = -2.5 + MR3
; Add to MR3 the value 0x3FC00000 (1.5)
; Store the result in MR3
MADDF32 MR3, #0x3FC0, MR3 ; MR3 = 1.5 + MR3

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MADDF32 MRa, #16FHi, MRb (continued)

32-Bit Floating-Point Addition

See also
MADDF32 MRa, MRb, #16FHi
MADDF32 MRa, MRb, MRc
MADDF32 MRd, MRe, MRf || MMOV32 MRa, mem32
MADDF32 MRd, MRe, MRf || MMOV32 mem32, MRa
MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf

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MADDF32 MRa, MRb, #16FHi

32-Bit Floating-Point Addition

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)
#16FHi A 16-bit immediate value that represents the upper 16-bits of an
IEEE 32-bit floating-point value. The low 16-bits of the mantissa
are assumed to be all 0.

Opcode
LSW: IIII IIII IIII IIII
MSW: 0111 0111 1100 bbaa

Description
Add MRb to the floating-point value represented by the immediate operand. Store the
result of the addition in MRa.
#16FHi is a 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit
floating-point value. The low 16-bits of the mantissa are assumed to be all 0. #16FHi is
most useful for representing constants where the lowest 16-bits of the mantissa are 0.
Some examples are 2.0 (0x40000000), 4.0 (0x40800000), 0.5 (0x3F000000), and -1.5
(0xBFC00000). The assembler accepts either a hex or float as the immediate value. That
is, the value -1.5 can be represented as #-1.5 or #0xBFC0.

MRa = MRb + #16FHi:0;

This instruction can also be written as MADDF32 MRa, #16FHi, MRb.

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MADDF32 generates an underflow condition.
• LVF = 1 if MADDF32 generates an overflow condition.

Pipeline
This is a single-cycle instruction.

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MADDF32 MRa, MRb, #16FHi (continued)

32-Bit Floating-Point Addition

Example 1
; X is an array of 32-bit floating-point values
; Find the maximum value in an array X
; and store the value in Result
;
_Cla1Task1:
MMOVI16 MAR1,#_X ; Start address
MUI16TOF32 MR0, @_len ; Length of the array
MNOP ; delay for MAR1 load
MNOP ; delay for MAR1 load
MMOV32 MR1, *MAR1[2]++ ; MR1 = X0
LOOP
MMOV32 MR2, *MAR1[2]++ ; MR2 = next element
MMAXF32 MR1, MR2 ; MR1 = MAX(MR1, MR2)
MADDF32 MR0, MR0, #-1.0 ; Decrement the counter
MCMPF32 MR0 #0.0 ; Set/clear flags for MBCNDD
MNOP
MNOP
MNOP
MBCNDD LOOP, NEQ ; Branch if not equal to zero
MMOV32 @_Result, MR1 ; Always executed
MNOP ; Always executed
MNOP ; Always executed
MSTOP ; End of task

Example 2
; Show the basic operation of MADDF32
;
; Add to MR1 the value 2.0 in 32-bit floating-point format
; Store the result in MR0
MADDF32 MR0, MR1, #2.0 ; MR0 = MR1 + 2.0
; Add to MR3 the value -2.5 in 32-bit floating-point format
; Store the result in MR2
MADDF32 MR2, MR3, #-2.5 ; MR2 = MR3 + (-2.5)
; Add to MR0 the value 0x3FC00000 (1.5)
; Store the result in MR0
MADDF32 MR0, MR0, #0x3FC0 ; MR0 = MR0 + 1.5

See also
MADDF32 MRa, #16FHi, MRb
MADDF32 MRa, MRb, MRc
MADDF32 MRd, MRe, MRf || MMOV32 MRa, mem32
MADDF32 MRd, MRe, MRf || MMOV32 mem32, MRa
MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf

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MADDF32 MRa, MRb, MRc

32-Bit Floating-Point Addition

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)
MRc CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 000 0000 00cc bbaa
MSW: 0111 1100 0010 0000

Description
Add the contents of MRc to the contents of MRb and load the result into MRa.

MRa = MRb + MRc;

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MADDF32 generates an underflow condition.
• LVF = 1 if MADDF32 generates an overflow condition.

Pipeline
This is a single-cycle instruction.

Example
; Given M1, X1, and B1 are 32-bit floating-point numbers
; Calculate Y1 = M1*X1+B1
;
_Cla1Task1:
MMOV32 MR0,@M1 ; Load MR0 with M1
MMOV32 MR1,@X1 ; Load MR1 with X1
MMPYF32 MR1,MR1,MR0 ; Multiply M1*X1
|| MMOV32 MR0,@B1 ; and in parallel load MR0 with B1
MADDF32 MR1,MR1,MR0 ; Add M*X1 to B1 and store in MR1
MMOV32 @Y1,MR1 ; Store the result
MSTOP ; end of task

See also
MADDF32 MRa, #16FHi, MRb
MADDF32 MRa, MRb, #16FHi
MADDF32 MRd, MRe, MRf || MMOV32 MRa, mem32
MADDF32 MRd, MRe, MRf || MMOV32 mem32, MRa
MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf

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MADDF32 MRd, MRe, MRf||MMOV32 mem32, MRa

32-Bit Floating-Point Addition with Parallel Move

Operands MRd CLA floating-point destination register for the MADDF32 (MR0 to
MR3)
MRe CLA floating-point source register for the MADDF32 (MR0 to MR3)
MRf CLA floating-point source register for the MADDF32 (MR0 to MR3)
mem32 32-bit memory location accessed using one of the available
addressing modes. This is the destination of the MMOV32.
MRa CLA floating-point source register for the MMOV32 (MR0 to MR3)

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0101 ffee ddaa addr

Description
Perform an MADDF32 and a MMOV32 in parallel. Add MRf to the contents of MRe
and store the result in MRd. In parallel move the contents of MRa to the 32-bit location
mem32.

MRd = MRe + MRf;

[mem32] = MRa;

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MADDF32 generates an underflow condition.
• LVF = 1 if MADDF32 generates an overflow condition.

Pipeline
Both MADDF32 and MMOV32 complete in a single cycle.

Example
; Given A, B, and C are 32-bit floating-point numbers
; Calculate Y2 = (A * B)
; Y3 = (A * B) + C
;
_Cla1Task2:
MMOV32 MR0, @_A ; Load MR0 with A
MMOV32 MR1, @_B ; Load MR1 with B
MMPYF32 MR1, MR1, MR0 ; Multiply A*B
|| MMOV32 MR0, @_C ; and in parallel load MR0 with C
MADDF32 MR1, MR1, MR0 ; Add (A*B) to C
|| MMOV32 @_Y2, MR1 ; and in parallel store A*B
MMOV32 @_Y3, MR1 ; Store the A*B + C
MSTOP ; end of task

See also
MADDF32 MRa, #16FHi, MRb
MADDF32 MRa, MRb, #16FHi
MADDF32 MRa, MRb, MRc
MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf
MADDF32 MRd, MRe, MRf || MMOV32 MRa, mem32

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MADDF32 MRd, MRe, MRf ||MMOV32 MRa, mem32

32-Bit Floating-Point Addition with Parallel Move

Operands MRd CLA floating-point destination register for the MADDF32 (MR0 to
MR3).
MRd cannot be the same register as MRa.
MRe CLA floating-point source register for the MADDF32 (MR0 to MR3)
MRf CLA floating-point source register for the MADDF32 (MR0 to MR3)
MRa CLA floating-point destination register for the MMOV32 (MR0 to
MR3).
MRa cannot be the same register as MRd.
mem32 32-bit memory location accessed using one of the available
addressing modes. This is the source for the MMOV32.

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0001 ffee ddaa addr

Description
Perform an MADDF32 and a MMOV32 operation in parallel. Add MRf to the contents
of MRe and store the result in MRd. In parallel move the contents of the 32-bit location
mem32 to MRa.

MRd = MRe + MRf;

MRa = [mem32];

Restrictions
The destination register for the MADDF32 and the MMOV32 must be unique. That is,
MRa and MRd cannot be the same register.

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MADDF32 generates an underflow condition.
• LVF = 1 if MADDF32 generates an overflow condition.
The MMOV32 Instruction sets the NF and ZF flags as follows:

NF = MRa(31);
ZF = 0;
if(MRa(30:23) == 0) { ZF = 1; NF = 0; };

Pipeline
The MADDF32 and the MMOV32 both complete in a single cycle.

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MADDF32 MRd, MRe, MRf ||MMOV32 MRa, mem32 (continued)

32-Bit Floating-Point Addition with Parallel Move

Example 1
; Given A, B, and C are 32-bit floating-point numbers
; Calculate Y1 = A + 4B
; Y2 = A + C
;
_Cla1Task1:
MMOV32 MR0, @A ; Load MR0 with A
MMOV32 MR1, @B ; Load MR1 with B
MMPYF32 MR1, MR1, #4.0 ; Multiply 4 * B
|| MMOV32 MR2, @C and in parallel load C
MADDF32 MR3, MR0, MR1 ; Add A + 4B
MADDF32 MR3, MR0, MR2 ; Add A + C
|| MMOV32 @Y1, MR3 ; and in parallel store A+4B
MMOV32 @Y2, MR3 ; store A + C MSTOP
; end of task

Example 2
; Given A, B, and C are 32-bit floating-point numbers
; Calculate Y3 = (A + B)
; Y4 = (A + B) * C
;
_Cla1Task2:
MMOV32 MR0, @A ; Load MR0 with A
MMOV32 MR1, @B ; Load MR1 with B
MADDF32 MR1, MR1, MR0 ; Add A+B
|| MMOV32 MR0, @C ; and in parallel load MR0 with C
MMPYF32 MR1, MR1, MR0 ; Multiply (A+B) by C
|| MMOV32 @Y3, MR1 ; and in parallel store A+B
MMOV32 @Y4, MR1 ; Store the (A+B) * C
MSTOP ; end of task

See also
MADDF32 MRa, #16FHi, MRb
MADDF32 MRa, MRb, #16FHi
MADDF32 MRa, MRb, MRc
MADDF32 MRd, MRe, MRf || MMOV32 mem32, MRa
MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf

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MAND32 MRa, MRb, MRc

Bitwise AND

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)
MRc CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 00cc bbaa
MSW: 0111 1100 0110 0000

Description
Bitwise AND of MRb with MRc.

MRa(31:0) = MRb(31:0) AND MRc(31:0);

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified based on the integer results of the operation.

NF = MRa(31);
ZF = 0;
if(MRa(31:0) == 0) { ZF = 1; }

Pipeline
This is a single-cycle instruction.

Example
MMOVIZ MR0, #0x5555 ; MR0 = 0x5555AAAA
MMOVXI MR0, #0xAAAA
MMOVIZ MR1, #0x5432 ; MR1 = 0x5432FEDC
MMOVXI MR1, #0xFEDC
; 0101 AND 0101 = 0101 (5)
; 0101 AND 0100 = 0100 (4)
; 0101 AND 0011 = 0001 (1)
; 0101 AND 0010 = 0000 (0)
; 1010 AND 1111 = 1010 (A)
; 1010 AND 1110 = 1010 (A)
; 1010 AND 1101 = 1000 (8)
; 1010 AND 1100 = 1000 (8)
MAND32 MR2, MR1, MR0 ; MR3 = 0x5410AA88

See also
MADD32 MRa, MRb, MRc
MASR32 MRa, #SHIFT
MLSL32 MRa, #SHIFT
MLSR32 MRa, #SHIFT
MOR32 MRa, MRb, MRc
MXOR32 MRa, MRb, MRc
MSUB32 MRa, MRb, MRc

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MASR32 MRa, #SHIFT

Arithmetic Shift Right

Operands MRa CLA floating-point source/destination register (MR0 to MR3)

#SHIFT Number of bits to shift (1 to 32)

Opcode
LSW: 0000 0000 0shi ftaa
MSW: 0111 1011 0100 0000

Description
Arithmetic shift right of MRa by the number of bits indicated. The number of bits can be 1
to 32.

MARa(31:0) = Arithmetic Shift(MARa(31:0) by #SHIFT bits);

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified based on the integer results of the operation.

NF = MRa(31);
ZF = 0;
if(MRa(31:0) == 0) { ZF = 1; }

Pipeline
This is a single-cycle instruction.

Example
; Given m2 = (int32)32
; x2 = (int32)64
; b2 = (int32)-128
;
; Calculate
; m2 = m2/2
; x2 = x2/4
; b2 = b2/8
;
_Cla1Task2:
MMOV32 MR0, @_m2 ; MR0 = 32 (0x00000020)
MMOV32 MR1, @_x2 ; MR1 = 64 (0x00000040)
MMOV32 MR2, @_b2 ; MR2 = -128 (0xFFFFFF80)
MASR32 MR0, #1 ; MR0 = 16 (0x00000010)
MASR32 MR1, #2 ; MR1 = 16 (0x00000010)
MASR32 MR2, #3 ; MR2 = -16 (0xFFFFFFF0)
MMOV32 @_m2, MR0 ; store results
MMOV32 @_x2, MR1
MMOV32 @_b2, MR2
MSTOP ; end of task

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MASR32 MRa, #SHIFT (continued)

Arithmetic Shift Right

See also
MADD32 MRa, MRb, MRc
MAND32 MRa, MRb, MRc
MLSL32 MRa, #SHIFT
MLSR32 MRa, #SHIFT
MOR32 MRa, MRb, MRc
MXOR32 MRa, MRb, MRc
MSUB32 MRa, MRb, MRc

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MBCNDD 16BitDest {, CNDF}

Branch Conditional Delayed

Operands 16BitDest 16-bit destination if condition is true

CNDF Optional condition tested

Opcode
LSW: dest dest dest dest
MSW: 0111 1001 1000 cndf

Description
If the specified condition is true, then branch by adding the signed 16BitDest value to the
MPC value. Otherwise, continue without branching. If the address overflows, the address
wraps around. Therefore, a value of "0xFFFE" puts the MPC back to the MBCNDD
instruction.
Refer to the Pipeline section for important information regarding this instruction.

if (CNDF == TRUE) MPC += 16BitDest;

CNDF is one of the following conditions:

Encode(1) CNDF Description MSTF Flags Tested
0000 NEQ Not equal to zero ZF == 0
0001 EQ Equal to zero ZF == 1
0010 GT Greater than zero ZF == 0 AND NF == 0
0011 GEQ Greater than or equal NF == 0
to zero
0100 LT Less than zero NF == 1
0101 LEQ Less than or equal to ZF == 1 OR NF == 1
zero
1010 TF Test flag set TF == 1
1011 NTF Test flag not set TF == 0
1100 LU Latched underflow LUF == 1
1101 LV Latched overflow LVF == 1
1110 UNC Unconditional None
1111 UNCF(2) Unconditional with flag None
modification

(1) Values not shown are reserved.

(2) This is the default operation, if no CNDF field is specified. This condition
allows the ZF and NF flags to be modified when a conditional operation is
executed. All other conditions do not modify these flags.

Restrictions
The MBCNDD instruction is not allowed three instructions before or after a MBCNDD,
MCCNDD, or MRCNDD instruction. Refer to the Pipeline section for more information.

Flags
This instruction does not modify flags in the MSTF register.
Flag TF ZF NF LUF LVF
Modified No No No No No

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MBCNDD 16BitDest {, CNDF} (continued)

Branch Conditional Delayed

Pipeline
The MBCNDD instruction alone is a single-cycle instruction. As shown in Table 6-11, 6
instruction slots are executed for each branch; 3 slots before the branch instruction (I2-I4)
and 3 slots after the branch instruction (I5-I7). The total number of cycles for a branch
taken or not taken depends on the usage of these slots. That is, the number of cycles
depends on how many slots are filled with a MNOP as well as which slots are filled. The
effective number of cycles for a branch can, therefore, range from 1 to 7 cycles. The
number of cycles for a branch taken cannot be the same as for a branch not taken.
Referring to Table 6-11 and Table 6-12, the instructions before and after MBCNDD have
the following properties:
• I1
– I1 is the last instruction that can effect the CNDF flags for the MBCNDD instruction.
The CNDF flags are tested in the D2 phase of the pipeline. That is, a decision is
made whether to branch or not when MBCNDD is in the D2 phase.
– There are no restrictions on the type of instruction for I1.
• I2, I3, and I4
– The three instructions proceeding MBCNDD can change MSTF flags but have no
effect on whether the MBCNDD instruction branches or not. This is because the
flag modification occurs after the D2 phase of the MBCNDD instruction.
– These instructions must not be the following: MSTOP, MDEBUGSTOP, MBCNDD,
MCCNDD, or MRCNDD.
• I5, I6, and I7
– The three instructions following MBCNDD are always executed irrespective of
whether the branch is taken or not.
– These instructions must not be the following: MSTOP, MDEBUGSTOP, MBCNDD,
MCCNDD, or MRCNDD.

<Instruction 1> ; I1 Last instruction that can affect flags for

; the MBCNDD operation
<Instruction 2> ; I2 Cannot be stop, branch, call or return
<Instruction 3> ; I3 Cannot be stop, branch, call or return
<Instruction 4> ; I4 Cannot be stop, branch, call or return
MBCNDD _Skip, NEQ ; Branch to Skip if not eqal to zero
; Three instructions after MBCNDD are always
; executed whether the branch is taken or not
<Instruction 5> ; I5 Cannot be stop, branch, call or return
<Instruction 6> ; I6 Cannot be stop, branch, call or return
<Instruction 7> ; I7 Cannot be stop, branch, call or return
<Instruction 8> ; I8
<Instruction 9> ; I9
....
_Skip:
<Destination 1> ; d1 Can be any instruction
<Destination 2> ; d2
<Destination 3> ; d3
....
....
MSTOP
....

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MBCNDD 16BitDest {, CNDF} (continued)

Branch Conditional Delayed

Table 6-11. Pipeline Activity for MBCNDD, Branch Not Taken

Instruction F1 F2 D1 D2 R1 R2 E W
I1 I1
I2 I2 I1
I3 I3 I2 I1
I4 I4 I3 I2 I1
MBCNDD MBCNDD I4 I3 I2 I1
I5 I5 MBCNDD I4 I3 I2 I1
I6 I6 I5 MBCNDD I4 I3 I2 I1
I7 I7 I6 I5 MBCNDD I4 I3 I2
I8 I8 I7 I6 I5 - I4 I3
I9 I9 I8 I7 I6 I5 - I4
I10 I10 I9 I8 I7 I6 I5 -
I10 I9 I8 I7 I6 I5
I10 I9 I8 I7 I6
I10 I9 I8 I7
I10 I9 I8
I10 I9
I10

Table 6-12. Pipeline Activity for MBCNDD, Branch Taken

Instruction F1 F2 D1 D2 R1 R2 E W
I1 I1
I2 I2 I1
I3 I3 I2 I1
I4 I4 I3 I2 I1
MBCNDD MBCNDD I4 I3 I2 I1
I5 I5 MBCNDD I4 I3 I2 I1
I6 I6 I5 MBCNDD I4 I3 I2 I1
I7 I7 I6 I5 MBCNDD I4 I3 I2
d1 d1 I7 I6 I5 - I4 I3
d2 d2 d1 I7 I6 I5 - I4
d3 d3 d2 d1 I7 I6 I5 -
d3 d2 d1 I7 I6 I5
d3 d2 d1 I7 I6
d3 d2 d1 I7
d3 d2 d1
d3 d2
d3

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MBCNDD 16BitDest {, CNDF} (continued)

Branch Conditional Delayed

Example 1
; if (State == 0.1)
; RampState = RampState || RAMPMASK
; else if (State == 0.01)
; CoastState = CoastState || COASTMASK
; else
; SteadyState = SteadyState || STEADYMASK
;
_Cla1Task1:
MMOV32 MR0, @State
MCMPF32 MR0, #0.1 ; Affects flags for 1st MBCNDD (A)
MNOP
MNOP
MNOP
MBCNDD Skip1, NEQ ; (A) If State != 0.1, go to Skip1
MNOP ; Always executed
MNOP ; Always executed
MNOP ; Always executed
MMOV32 MR1, @RampState ; Execute if (A) branch not taken
MMOVXI MR2, #RAMPMASK ; Execute if (A) branch not taken
MOR32 MR1, MR2 ; Execute if (A) branch not taken
MMOV32 @RampState, MR1 ; Execute if (A) branch not taken
MSTOP ; end of task if (A) branch not taken
Skip1:
MCMPF32 MR0,#0.01 ; Affects flags for 2nd MBCNDD (B)
MNOP
MNOP
MNOP
MBCNDD Skip2,NEQ ; (B) If State != 0.01, go to Skip2
MNOP ; Always executed
MNOP ; Always executed
MNOP ; Always executed
MMOV32 MR1, @CoastState ; Execute if (B) branch not taken
MMOVXI MR2, #COASTMASK ; Execute if (B) branch not taken
MOR32 MR1, MR2 ; Execute if (B) branch not taken
MMOV32 @CoastState, MR1 ; Execute if (B) branch not taken
MSTOP
Skip2:
MMOV32 MR3, @SteadyState ; Executed if (B) branch taken
MMOVXI MR2, #STEADYMASK ; Executed if (B) branch taken
MOR32 MR3, MR2 ; Executed if (B) branch taken
MMOV32 @SteadyState, MR3 ; Executed if (B) branch taken
MSTOP

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MBCNDD 16BitDest {, CNDF} (continued)

Branch Conditional Delayed

Example 2
; This example is the same as Example 1, except
; the code is optimized to take advantage of delay slots
;
; if (State == 0.1)
; RampState = RampState || RAMPMASK
; else if (State == 0.01)
; CoastState = CoastState || COASTMASK
; else
; SteadyState = SteadyState || STEADYMASK
;
_Cla1Task2:
MMOV32 MR0, @State
MCMPF32 MR0, #0.1 ; Affects flags for 1st MBCNDD (A)
MCMPF32 MR0, #0.01 ; Check used by 2nd MBCNDD (B)
MTESTTF EQ ; Store EQ flag in TF for 2nd MBCNDD (B)
MNOP
MBCNDD Skip1, NEQ ; (A) If State != 0.1, go to Skip1
MMOV32 MR1, @RampState ; Always executed
MMOVXI MR2, #RAMPMASK ; Always executed
MOR32 MR1, MR2 ; Always executed
MMOV32 @RampState, MR1 ; Execute if (A) branch not taken
MSTOP ; end of task if (A) branch not taken
Skip1:
MMOV32 MR3, @SteadyState
MMOVXI MR2, #STEADYMASK
MOR32 MR3, MR2
MBCNDD Skip2, NTF ; (B) if State != .01, go to Skip2
MMOV32 MR1, @CoastState ; Always executed
MMOVXI MR2, #COASTMASK ; Always executed
MOR32 MR1, MR2 ; Always executed
MMOV32 @CoastState, MR1 ; Execute if (B) branch not taken
MSTOP ; end of task if (B) branch not taken
Skip2:
MMOV32 @SteadyState, MR3 ; Executed if (B) branch taken
MSTOP

See also
MCCNDD 16BitDest, CNDF
MRCNDD CNDF

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MCCNDD 16BitDest {, CNDF}

Call Conditional Delayed

Operands 16BitDest 16-bit destination if condition is true

CNDF Optional condition to be tested

Opcode
LSW: dest dest dest dest
MSW: 0111 1001 1001 cndf

Description
If the specified condition is true, then store the return address in the RPC field of MSTF
and make the call by adding the signed 16BitDest value to the MPC value. Otherwise,
continue code execution without making the call. If the address overflows, the address
wraps around. Therefore a value of "0xFFFE" puts the MPC back to the MCCNDD
instruction.
Refer to the Pipeline section for important information regarding this instruction.

if (CNDF == TRUE)
{
RPC = return address;
MPC += 16BitDest;
};

CNDF is one of the following conditions:

Encode(1) CNDF Description MSTF Flags Tested
0000 NEQ Not equal to zero ZF == 0
0001 EQ Equal to zero ZF == 1
0010 GT Greater than zero ZF == 0 AND NF == 0
0011 GEQ Greater than or equal NF == 0
to zero
0100 LT Less than zero NF == 1
0101 LEQ Less than or equal to ZF == 1 OR NF == 1
zero
1010 TF Test flag set TF == 1
1011 NTF Test flag not set TF == 0
1100 LU Latched underflow LUF == 1
1101 LV Latched overflow LVF == 1
1110 UNC Unconditional None
1111 UNCF(2) Unconditional with flag None
modification

(1) Values not shown are reserved.

(2) This is the default operation if no CNDF field is specified. This condition allows
the ZF and NF flags to be modified when a conditional operation is executed.
All other conditions do not modify these flags.

Restrictions
The MCCNDD instruction is not allowed three instructions before or after a MBCNDD,
MCCNDD, or MRCNDD instruction. Refer to the Pipeline section for more details.

Flags
This instruction does not modify flags in the MSTF register.

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MCCNDD 16BitDest {, CNDF} (continued)

Call Conditional Delayed

Flag TF ZF NF LUF LVF

Modified No No No No No

Pipeline
The MCCNDD instruction alone is a single-cycle instruction. As shown in Table 6-13, 6
instruction slots are executed for each call; 3 before the call instruction (I2-I4) and 3 after
the call instruction (I5-I7). The total number of cycles for a call taken or not taken depends
on the usage of these slots. That is, the number of cycles depends on how many slots are
filled with a MNOP as well as which slots are filled. The effective number of cycles for a
call can, therefore, range from 1 to 7 cycles. The number of cycles for a call taken cannot
be the same as for a call not taken.
Referring to the following code fragment and the pipeline diagrams in Table 6-13 and
Table 6-14, the instructions before and after MCCNDD have the following properties:
• I1
– I1 is the last instruction that can effect the CNDF flags for the MCCNDD instruction.
The CNDF flags are tested in the D2 phase of the pipeline. That is, a decision is
made whether to branch or not when MCCNDD is in the D2 phase.
– There are no restrictions on the type of instruction for I1.
• I2, I3, and I4
– The three instructions proceeding MCCNDD can change MSTF flags but have no
effect on whether the MCCNDD instruction makes the call or not. This is because
the flag modification occurs after the D2 phase of the MCCNDD instruction.
– These instructions must not be the following: MSTOP, MDEBUGSTOP, MBCNDD,
MCCNDD, or MRCNDD.
• I5, I6, and I7
– The three instructions following MBCNDD are always executed irrespective of
whether the branch is taken or not.
– These instructions must not be the following: MSTOP, MDEBUGSTOP, MBCNDD,
MCCNDD, or MRCNDD.

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MCCNDD 16BitDest {, CNDF} (continued)

Call Conditional Delayed

<Instruction 1> ; I1 Last instruction that can affect flags for

; the MCCNDD operation
<Instruction 2> ; I2 Cannot be stop, branch, call or return
<Instruction 3> ; I3 Cannot be stop, branch, call or return
<Instruction 4> ; I4 Cannot be stop, branch, call or return
MCCNDD _func, NEQ ; Call to func if not eqal to zero
; Three instructions after MCCNDD are always
; executed whether the call is taken or not
<Instruction 5> ; I5 Cannot be stop, branch, call or return
<Instruction 6> ; I6 Cannot be stop, branch, call or return
<Instruction 7> ; I7 Cannot be stop, branch, call or return
<Instruction 8> ; I8 The address of this instruction is saved
; in the RPC field of the MSTF register.
; Upon return this value is loaded into MPC
; and fetching continues from this point.
<Instruction 9> ; I9
....
_func:
<Destination 1> ; d1 Can be any instruction
<Destination 2> ; d2
<Destination 3> ; d3
<Destination 4> ; d4 Last instruction that can affect flags for
; the MRCNDD operation
<Destination 5> ; d5 Cannot be stop, branch, call or return
<Destination 6> ; d6 Cannot be stop, branch, call or return
<Destination 7> ; d7 Cannot be stop, branch, call or return
MRCNDD UNC ; Return to <Instruction 8>, unconditional
; Three instructions after MRCNDD are always
; executed whether the return is taken or not
<Destination 8> ; d8 Cannot be stop, branch, call or return
<Destination 9> ; d9 Cannot be stop, branch, call or return
<Destination 10> ; d10 Cannot be stop, branch, call or return
<Destination 11> ; d11
....
MSTOP

Table 6-13. Pipeline Activity for MCCNDD, Call Not Taken

Instruction F1 F2 D1 D2 R1 R2 E W
I1 I1
I2 I2 I1
I3 I3 I2 I1
I4 I4 I3 I2 I1
MCCNDD MCCNDD I4 I3 I2 I1
I5 I5 MCCNDD I4 I3 I2 I1
I6 I6 I5 MCCNDD I4 I3 I2 I1
I7 I7 I6 I5 MCCNDD I4 I3 I2
I8 I8 I7 I6 I5 - I4 I3
I9 I9 I8 I7 I6 I5 - I4
I10 I10 I9 I8 I7 I6 I5 -
etc .... I10 I9 I8 I7 I6 I5
.... I10 I9 I8 I7 I6
.... I10 I9 I8 I7
.... I10 I9 I8
I10 I9
I10

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MCCNDD 16BitDest {, CNDF} (continued)

Call Conditional Delayed

Table 6-14. Pipeline Activity for MCCNDD, Call Taken

Instruction F1 F2 D1 D2 R1 R2 E W
I1 I1
I2 I2 I1
I3 I3 I2 I1
I4 I4 I3 I2 I1
MCCNDD MCCNDD I4 I3 I2 I1
I5 I5 MCCNDD I4 I3 I2 I1
I6 I6 I5 MCCNDD I4 I3 I2 I1
I7 (1) I7 I6 I5 MCCNDD I4 I3 I2
d1 d1 I7 I6 I5 - I4 I3
d2 d2 d1 I7 I6 I5 - I4
d3 d3 d2 d1 I7 I6 I5 -
etc .... d3 d2 d1 I7 I6 I5
.... d3 d2 d1 I7 I6
.... d3 d2 d1 I7
.... d3 d2 d1
d3 d2
d3

(1) The RPC value in the MSTF register points to the instruction following I7 (instruction I8).

See also
MBCNDD #16BitDest, CNDF
MMOV32 mem32, MSTF
MMOV32 MSTF, mem32
MRCNDD CNDF

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MCMP32 MRa, MRb

32-Bit Integer Compare for Equal, Less Than or Greater Than

Operands MRa CLA floating-point source register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1111 0010 0000

Description
Set ZF and NF flags on the result of MRa - MRb where MRa and MRb are 32-bit integers.
For a floating-point compare, refer to MCMPF32.

Note
A known hardware issue exists in the MCMP32 instruction. Signed-integer
comparisons using MCMP32 alone set the status bits in a way that is not useful
for comparison when the difference between the two operands is too large,
such as when the inputs have opposite sign and are near the extreme 32-bit
signed values. This affects both signed and unsigned integer comparisons.
The compiler (version 18.1.5.LTS or higher) has implemented a workaround for
this issue. The compiler checks the upper bits of the operands by performing
a floating point comparison before proceeding to do the integer comparison or
subtraction.
The compiler flag --cla_signed_compare_workaround enables this workaround.

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified based on the integer results of the operation.

If(MRa == MRb) {ZF=1; NF=0;}

If(MRa > MRb) {ZF=0; NF=0;}
If(MRa < MRb) {ZF=0; NF=1;}

Pipeline
This is a single-cycle instruction.

Example
; Behavior of ZF and NF flags for different comparisons
;
; Given A = (int32)1
; B = (int32)2
; C = (int32)-7
;
MMOV32 MR0, @_A ; MR0 = 1 (0x00000001)
MMOV32 MR1, @_B ; MR1 = 2 (0x00000002)
MMOV32 MR2, @_C ; MR2 = -7 (0xFFFFFFF9)
MCMP32 MR2, MR2 ; NF = 0, ZF = 1
MCMP32 MR0, MR1 ; NF = 1, ZF = 0
MCMP32 MR1, MR0 ; NF = 0, ZF = 0

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MCMP32 MRa, MRb (continued)

32-Bit Integer Compare for Equal, Less Than or Greater Than

See also
MADD32 MRa, MRb, MRc
MSUB32 MRa, MRb, MRc

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MCMPF32 MRa, MRb

32-Bit Floating-Point Compare for Equal, Less Than or Greater Than

Operands MRa CLA floating-point source register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1101 0000 0000

Description
Set ZF and NF flags on the result of MRa - MRb. The MCMPF32 instruction is performed
as a logical compare operation. This is possible because of the IEEE format offsetting the
exponent. Basically the bigger the binary number, the bigger the floating-point value.
Special cases for inputs:
• Negative zero is treated as positive zero.
• A denormalized value is treated as positive zero.
• Not-a-Number (NaN) is treated as infinity.

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified as follows:

If(MRa == MRb) {ZF=1; NF=0;}

If(MRa > MRb) {ZF=0; NF=0;}
If(MRa < MRb) {ZF=0; NF=1;}

Pipeline
This is a single-cycle instruction.

Example
; Behavior of ZF and NF flags for different comparisons
MMOVIZ MR1, #-2.0 ; MR1 = -2.0 (0xC0000000)
MMOVIZ MR0, #5.0 ; MR0 = 5.0 (0x40A00000)
MCMPF32 MR1, MR0 ; ZF = 0, NF = 1
MCMPF32 MR0, MR1 ; ZF = 0, NF = 0
MCMPF32 MR0, MR0 ; ZF = 1, NF = 0

See also
MCMPF32 MRa, #16FHi
MMAXF32 MRa, #16FHi
MMAXF32 MRa, MRb
MMINF32 MRa, #16FHi
MMINF32 MRa, MRb

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MCMPF32 MRa, #16FHi

32-Bit Floating-Point Compare for Equal, Less Than or Greater Than

Operands MRa CLA floating-point source register (MR0 to MR3)

#16FHi A 16-bit immediate value that represents the upper 16-bits of an
IEEE 32-bit floating-point value. The low 16-bits of the mantissa
are assumed to be all 0.

Opcode
LSW: IIII IIII IIII IIII
MSW: 0111 1000 1100 00aa

Description
Compare the value in MRa with the floating-point value represented by the immediate
operand. Set the ZF and NF flags on (MRa - #16FHi:0).
#16FHi is a 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit
floating-point value. The low 16-bits of the mantissa are assumed to be all 0. This
addressing mode is most useful for constants where the lowest 16-bits of the mantissa
are 0. Some examples are 2.0 (0x40000000), 4.0 (0x40800000), 0.5 (0x3F000000), and
-1.5 (0xBFC00000). The assembler accepts either a hex or float as the immediate value.
That is, -1.5 can be represented as #-1.5 or #0xBFC0.
The MCMPF32 instruction is performed as a logical compare operation. This is possible
because of the IEEE floating-point format offsets the exponent. Basically the bigger the
binary number, the bigger the floating-point value.
Special cases for inputs:
• Negative zero is treated as positive zero.
• Denormalized value is treated as positive zero.
• Not-a-Number (NaN) is treated as infinity.

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified as follows:

If(MRa == #16FHi:0) {ZF=1, NF=0;}

If(MRa > #16FHi:0) {ZF=0, NF=0;}
If(MRa < #16FHi:0) {ZF=0, NF=1;}

Pipeline
This is a single-cycle instruction

Example 1
; Behavior of ZF and NF flags for different comparisons
MMOVIZ MR1, #-2.0 ; MR1 = -2.0 (0xC0000000)
MMOVIZ MR0, #5.0 ; MR0 = 5.0 (0x40A00000)
MCMPF32 MR1, #-2.2 ; ZF = 0, NF = 0
MCMPF32 MR0, #6.5 ; ZF = 0, NF = 1
MCMPF32 MR0, #5.0 ; ZF = 1, NF = 0

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MCMPF32 MRa, #16FHi (continued)

32-Bit Floating-Point Compare for Equal, Less Than or Greater Than

Example 2
; X is an array of 32-bit floating-point values
; and has length elements. Find the maximum value in
; the array and store the value in Result
;
; Note: MCMPF32 and MSWAPF can be replaced with MMAXF32
;
_Cla1Task1:
MMOVI16 MAR1,#_X ; Start address
MUI16TOF32 MR0, @_len ; Length of the array
MNOP ; delay for MAR1 load
MNOP ; delay for MAR1 load
MMOV32 MR1, *MAR1[2]++ ; MR1 = X0
LOOP
MMOV32 MR2, *MAR1[2]++ ; MR2 = next element
MCMPF32 MR2, MR1 ; Compare MR2 with MR1
MSWAPF MR1, MR2, GT ; MR1 = MAX(MR1, MR2)
MADDF32 MR0, MR0, #-1.0 ; Decrememt the counter
MCMPF32 MR0 #0.0 ; Set/clear flags for MBCNDD
MNOP
MNOP
MNOP
MBCNDD LOOP, NEQ ; Branch if not equal to zero
MMOV32 @_Result, MR1 ; Always executed
MNOP ; Always executed
MNOP ; Always executed
MSTOP ; End of task

See also
MCMPF32 MRa, MRb
MMAXF32 MRa, #16FHi
MMAXF32 MRa, MRb
MMINF32 MRa, #16FHi
MMINF32 MRa, MRb

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MDEBUGSTOP

Debug Stop Task

Operands none This instruction does not have any operands

Opcode
LSW: 0000 0000 0000 0000
MSW: 0111 1111 0110 0000

Description
When CLA breakpoints are enabled, the MDEBUGSTOP instruction is used to halt a task
so that the task can be debugged. That is, MDEBUGSTOP is the CLA breakpoint. If CLA
breakpoints are not enabled, the MDEBUGSTOP instruction behaves like a MNOP. Unlike
the MSTOP, the MIRUN flag is not cleared and an interrupt is not issued. A single-step or
run operation continues execution of the task.

Restrictions
The MDEBUGSTOP instruction cannot be placed 3 instructions before or after a
MBCNDD, MCCNDD, or MRCNDD instruction.

Flags
This instruction does not modify flags in the MSTF register.
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline
This is a single-cycle instruction.

See also
MSTOP

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MEALLOW

Enable CLA Write Access to EALLOW Protected Registers

Operands none This instruction does not have any operands

Opcode
LSW: 0000 0000 0000 0000
MSW: 0111 1111 1001 0000

Description
This instruction sets the MEALLOW bit in the CLA status register MSTF. When this bit
is set, the CLA is allowed write access to EALLOW protected registers. To again protect
against CLA writes to protected registers, use the MEDIS instruction.
MEALLOW and MEDIS only control CLA write access; reads are allowed even if
MEALLOW has not been executed. MEALLOW and MEDIS are also independent from
the main CPU's EALLOW/EDIS. This instruction does not modify the EALLOW bit in the
main CPU's status register. The MEALLOW bit in MSTF only controls access for the CLA
while the EALLOW bit in the ST1 register only controls access for the main CPU.
As with EALLOW, the MEALLOW bit is overridden using the JTAG port, allowing full
control of register accesses during debug from Code Composer Studio.

Flags
This instruction does not modify flags in the MSTF register.
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline
This is a single-cycle instruction.

Example
; C header file including definition of
; the EPwm1Regs structure
;
; The ePWM TZSEL register is EALLOW protected
;
.cdecls C,LIST,"CLAShared.h"
...
_Cla1Task1:
...
MEALLOW ; Allow CLA write access
MMOV16 @_EPwm1Regs.TZSEL.all, MR3 ; Write to TZSEL
MEDIS ; Disallow CLA write access
...
...
MSTOP

See also
MEDIS

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MEDIS

Disable CLA Write Access to EALLOW Protected Registers

Operands none This instruction does not have any operands

Opcode
LSW: 0000 0000 0000 0000
MSW: 0111 1111 1011 0000

Description
This instruction clears the MEALLOW bit in the CLA status register MSTF. When this bit is
clear, the CLA is not allowed write access to EALLOW-protected registers. To enable CLA
writes to protected registers, use the MEALLOW instruction.
MEALLOW and MEDIS only control CLA write access; reads are allowed even if
MEALLOW has not been executed. MEALLOW and MEDIS are also independent from
the main CPU's EALLOW/EDIS. This instruction does not modify the EALLOW bit in the
main CPU's status register. The MEALLOW bit in MSTF only controls access for the CLA
while the EALLOW bit in the ST1 register only controls access for the main CPU.
As with EALLOW, the MEALLOW bit is overridden using the JTAG port, allowing full
control of register accesses during debug from the Code Composer Studio™ IDE.

Flags
This instruction does not modify flags in the MSTF register.
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline
This is a single-cycle instruction.

Example
; C header file including definition of
; the EPwm1Regs structure
;
; The ePWM TZSEL register is EALLOW protected
;
.cdecls C,LIST,"CLAShared.h"
...
_Cla1Task1:
...
MEALLOW ; Allow CLA write access
MMOV16 @_EPwm1Regs.TZSEL.all, MR3 ; Write to TZSEL
MEDIS ; Disallow CLA write access
...
...
MSTOP

See also
MEALLOW

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MEINVF32 MRa, MRb

32-Bit Floating-Point Reciprocal Approximation

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1111 0000 0000

Description
This operation generates an estimate of 1/X in 32-bit floating-point format accurate to
approximately 8 bits. This value can be used in a Newton-Raphson algorithm to get a
more accurate answer. That is:

Ye = Estimate(1/X);
Ye = Ye*(2.0 - Ye*X);
Ye = Ye*(2.0 - Ye*X);

After two iterations of the Newton-Raphson algorithm, you get an exact answer
accurate to the 32-bit floating-point format. On each iteration, the mantissa bit accuracy
approximately doubles. The MEINVF32 operation does not generate a negative zero,
DeNorm, or NaN value.

MRa = Estimate of 1/MRb;

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MEINVF32 generates an underflow condition.
• LVF = 1 if MEINVF32 generates an overflow condition.

Pipeline
This is a single-cycle instruction.

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MEINVF32 MRa, MRb (continued)

32-Bit Floating-Point Reciprocal Approximation

Example
; Calculate Num/Den using a Newton-Raphson algorithum for 1/Den
; Ye = Estimate(1/X)
; Ye = Ye*(2.0 - Ye*X)
; Ye = Ye*(2.0 - Ye*X)
;
_Cla1Task1:
MMOV32 MR1, @_Den ; MR1 = Den
MEINVF32 MR2, MR1 ; MR2 = Ye = Estimate(1/Den)
MMPYF32 MR3, MR2, MR1 ; MR3 = Ye*Den
MSUBF32 MR3, #2.0, MR3 ; MR3 = 2.0 - Ye*Den
MMPYF32 MR2, MR2, MR3 ; MR2 = Ye = Ye*(2.0 - Ye*Den)
MMPYF32 MR3, MR2, MR1 ; MR3 = Ye*Den
|| MMOV32 MR0, @_Num ; MR0 = Num
MSUBF32 MR3, #2.0, MR3 ; MR3 = 2.0 - Ye*Den
MMPYF32 MR2, MR2, MR3 ; MR2 = Ye = Ye*(2.0 - Ye*Den)
|| MMOV32 MR1, @_Den ; Reload Den To Set Sign
MNEGF32 MR0, MR0, EQ ; if(Den == 0.0) Change Sign Of Num
MMPYF32 MR0, MR2, MR0 ; MR0 = Y = Ye*Num
MMOV32 @_Dest, MR0 ; Store result
MSTOP ; end of task

See also
MEISQRTF32 MRa, MRb

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MEISQRTF32 MRa, MRb

32-Bit Floating-Point Square-Root Reciprocal Approximation

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1110 0100 0000

Description
This operation generates an estimate of 1/sqrt(X) in 32-bit floating-point format accurate
to approximately 8 bits. This value can be used in a Newton-Raphson algorithm to get a
more accurate answer. That is:

Ye = Estimate(1/sqrt(X));
Ye = Ye*(1.5 - Ye*Ye*X/2.0);
Ye = Ye*(1.5 - Ye*Ye*X/2.0);

After 2 iterations of the Newton-Raphson algorithm, you get an exact answer accurate to
the 32-bit floating-point format. On each iteration, the mantissa bit accuracy approximately
doubles. The MEISQRTF32 operation does not generate a negative zero, DeNorm, or
NaN value.

MRa = Estimate of 1/sqrt (MRb);

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MEISQRTF32 generates an underflow condition.
• LVF = 1 if MEISQRTF32 generates an overflow condition.

Pipeline
This is a single-cycle instruction.

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MEISQRTF32 MRa, MRb (continued)

32-Bit Floating-Point Square-Root Reciprocal Approximation

Example
; Y = sqrt(X)
; Ye = Estimate(1/sqrt(X));
; Ye = Ye*(1.5 - Ye*Ye*X*0.5)
; Ye = Ye*(1.5 - Ye*Ye*X*0.5)
; Y = X*Ye
;
_Cla1Task3:
MMOV32 MR0, @_x ; MR0 = X
MEISQRTF32 MR1, MR0 ; MR1 = Ye = Estimate(1/sqrt(X))
MMOV32 MR1, @_x, EQ ; if(X == 0.0) Ye = 0.0
MMPYF32 MR3, MR0, #0.5 ; MR3 = X*0.5
MMPYF32 MR2, MR1, MR3 ; MR2 = Ye*X*0.5
MMPYF32 MR2, MR1, MR2 ; MR2 = Ye*Ye*X*0.5
MSUBF32 MR2, #1.5, MR2 ; MR2 = 1.5 - Ye*Ye*X*0.5
MMPYF32 MR1, MR1, MR2 ; MR1 = Ye = Ye*(1.5 - Ye*Ye*X*0.5)
MMPYF32 MR2, MR1, MR3 ; MR2 = Ye*X*0.5
MMPYF32 MR2, MR1, MR2 ; MR2 = Ye*Ye*X*0.5
MSUBF32 MR2, #1.5, MR2 ; MR2 = 1.5 - Ye*Ye*X*0.5
MMPYF32 MR1, MR1, MR2 ; MR1 = Ye = Ye*(1.5 - Ye*Ye*X*0.5)
MMPYF32 MR0, MR1, MR0 ; MR0 = Y = Ye*X
MMOV32 @_y, MR0 ; Store Y = sqrt(X)
MSTOP ; end of task

See also
MEINVF32 MRa, MRb

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MF32TOI16 MRa, MRb

Convert 32-Bit Floating-Point Value to 16-Bit Integer

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1101 1110 0000

Description
Convert a 32-bit floating point value in MRb to a 16-bit integer and truncate. The result is
stored in MRa.

MRa(15:0) = F32TOI16(MRb);
MRa(31:16) = sign extension of MRa(15);

Flags
This instruction does not affect any flags:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline
This is a single-cycle instruction.

Example
MMOVIZ MR0, #5.0 ; MR0 = 5.0 (0x40A00000)
MF32TOI16 MR1, MR0 ; MR1(15:0) = MF32TOI16(MR0) = 0x0005
; MR1(31:16) = Sign extension of MR1(15) = 0x0000
MMOVIZ MR2, #-5.0 ; MR2 = -5.0 (0xC0A00000)
MF32TOI16 MR3, MR2 ; MR3(15:0) = MF32TOI16(MR2) = -5 (0xFFFB)
; MR3(31:16) = Sign extension of MR3(15) = 0xFFFF

See also
MF32TOI16R MRa, MRb
MF32TOUI16 MRa, MRb
MF32TOUI16R MRa, MRb
MI16TOF32 MRa, MRb
MI16TOF32 MRa, mem16
MUI16TOF32 MRa, mem16
MUI16TOF32 MRa, MRb

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MF32TOI16R MRa, MRb

Convert 32-Bit Floating-Point Value to 16-Bit Integer and Round

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1110 0110 0000

Description
Convert the 32-bit floating point value in MRb to a 16-bit integer and round to the nearest
even value. The result is stored in MRa.

MRa(15:0) = F32TOI16round(MRb);
MRa(31:16) = sign extension of MRa(15);

Flags
This instruction does not affect any flags:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline
This is a single-cycle instruction.

Example
MMOVIZ MR0, #0x3FD9 ; MR0(31:16) = 0x3FD9
MMOVXI MR0, #0x999A ; MR0(15:0) = 0x999A
; MR0 = 1.7 (0x3FD9999A)
MF32TOI16R MR1, MR0 ; MR1(15:0) = MF32TOI16round (MR0) = 2 (0x0002)
; MR1(31:16) = Sign extension of MR1(15) = 0x0000
MMOVF32 MR2, #-1.7 ; MR2 = -1.7 (0xBFD9999A)
MF32TOI16R MR3, MR2 ; MR3(15:0) = MF32TOI16round (MR2) = -2 (0xFFFE)
; MR3(31:16) = Sign extension of MR2(15) = 0xFFFF

See also
MF32TOI16 MRa, MRb
MF32TOUI16 MRa, MRb
MF32TOUI16R MRa, MRb
MI16TOF32 MRa, MRb
MI16TOF32 MRa, mem16
MUI16TOF32 MRa, mem16
MUI16TOF32 MRa, MRb

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MF32TOI32 MRa, MRb

Convert 32-Bit Floating-Point Value to 32-Bit Integer

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1101 0110 0000

Description
Convert the 32-bit floating-point value in MRb to a 32-bit integer value and truncate. Store
the result in MRa.

MRa = F32TOI32(MRb);

Flags
This instruction does not affect any flags:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline
This is a single-cycle instruction.

Example 1
MMOVF32 MR2, #11204005.0 ; MR2 = 11204005.0 (0x4B2AF5A5)
MF32TOI32 MR3, MR2 ; MR3 = MF32TOI32(MR2) = 11204005 (0x00AAF5A5)
MMOVF32 MR0, #-11204005.0 ; MR0 = -11204005.0 (0xCB2AF5A5)
MF32TOI32 MR1, MR0 ; MR1 = MF32TOI32(MR0) = -11204005 (0xFF550A5B)

Example 2
; Given X, M and B are IQ24 numbers:
; X = IQ24(+2.5) = 0x02800000
; M = IQ24(+1.5) = 0x01800000
; B = IQ24(-0.5) = 0xFF800000
;
; Calculate Y = X * M + B
;
; Convert M, X, and B from IQ24 to float
;
_Cla1Task2:
MI32TOF32 MR0, @_M ; MR0 = 0x4BC00000
MI32TOF32 MR1, @_X ; MR1 = 0x4C200000
MI32TOF32 MR2, @_B ; MR2 = 0xCB000000
MMPYF32 MR0, MR0, #0x3380 ; M = 1/(1*2^24) * iqm = 1.5 (0x3FC00000)
MMPYF32 MR1, MR1, #0x3380 ; X = 1/(1*2^24) * iqx = 2.5 (0x40200000)
MMPYF32 MR2, MR2, #0x3380 ; B = 1/(1*2^24) * iqb = -.5 (0xBF000000)
MMPYF32 MR3, MR0, MR1 ; M*X
MADDF32 MR2, MR2, MR3 ; Y=MX+B = 3.25 (0x40500000)
; Convert Y from float32 to IQ24
MMPYF32 MR2, MR2, #0x4B80 ; Y * 1*2^24
MF32TOI32 MR2, MR2 ; IQ24(Y) = 0x03400000
MMOV32 @_Y, MR2 ; store result
MSTOP ; end of task

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MF32TOI32 MRa, MRb (continued)

Convert 32-Bit Floating-Point Value to 32-Bit Integer

See also
MF32TOUI32 MRa, MRb
MI32TOF32 MRa, MRb
MI32TOF32 MRa, mem32
MUI32TOF32 MRa, MRb
MUI32TOF32 MRa, mem32

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MF32TOUI16 MRa, MRb

Convert 32-Bit Floating-Point Value to 16-bit Unsigned Integer

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1110 1010 0000

Description
Convert the 32-bit floating point value in MRb to an unsigned 16-bit integer value and
truncate to zero. The result is stored in MRa. To instead round the integer to the nearest
even value, use the MF32TOUI16R instruction.

MRa(15:0) = F32TOUI16(MRb);
MRa(31:16) = 0x0000;

Flags
This instruction does not affect any flags:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline
This is a single-cycle instruction.

Example
MMOVIZ MR0, #9.0 ; MR0 = 9.0 (0x41100000)
MF32TOUI16 MR1, MR0 ; MR1(15:0) = MF32TOUI16(MR0) = 9 (0x0009)
; MR1(31:16) = 0x0000
MMOVIZ MR2, #-9.0 ; MR2 = -9.0 (0xC1100000)
MF32TOUI16 MR3, MR2 ; MR3(15:0) = MF32TOUI16(MR2) = 0 (0x0000)
; MR3(31:16) = 0x0000

See also
MF32TOI16 MRa, MRb
MF32TOUI16 MRa, MRb
MF32TOUI16R MRa, MRb
MI16TOF32 MRa, MRb
MI16TOF32 MRa, mem16
MUI16TOF32 MRa, mem16
MUI16TOF32 MRa, MRb

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MF32TOUI16R MRa, MRb

Convert 32-Bit Floating-Point Value to 16-bit Unsigned Integer and Round

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1110 1100 0000

Description
Convert the 32-bit floating-point value in MRb to an unsigned 16-bit integer and round to
the closest even value. The result is stored in MRa. To instead truncate the converted
value, use the MF32TOUI16 instruction.

MRa(15:0) = MF32TOUI16round(MRb);
MRa(31:16) = 0x0000;

Flags
This instruction does not affect any flags:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline
This is a single-cycle instruction.

Example
MMOVIZ MR0, #0x412C ; MR0 = 0x412C
MMOVXI MR0, #0xCCCD ; MR0 = 0xCCCD ; MR0 = 10.8 (0x412CCCCD)
MF32TOUI16R MR1, MR0 ; MR1(15:0) = MF32TOUI16round(MR0) = 11 (0x000B)
; MR1(31:16) = 0x0000
MMOVF32 MR2, #-10.8 ; MR2 = -10.8 (0x0xC12CCCCD)
MF32TOUI16R MR3, MR2 ; MR3(15:0) = MF32TOUI16round(MR2) = 0 (0x0000)
; MR3(31:16) = 0x0000

See also
MF32TOI16 MRa, MRb
MF32TOI16R MRa, MRb
MF32TOUI16 MRa, MRb
MI16TOF32 MRa, MRb
MI16TOF32 MRa, mem16
MUI16TOF32 MRa, mem16
MUI16TOF32 MRa, MRb

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MF32TOUI32 MRa, MRb

Convert 32-Bit Floating-Point Value to 32-Bit Unsigned Integer

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1101 1010 0000

Description
Convert the 32-bit floating-point value in MRb to an unsigned 32-bit integer and store the
result in MRa.

MRa = F32TOUI32(MRb);

Flags
This instruction does not affect any flags:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline
This is a single-cycle instruction.

Example
MMOVIZ MR0, #12.5 ; MR0 = 12.5 (0x41480000)
MF32TOUI32 MR0, MR0 ; MR0 = MF32TOUI32 (MR0) = 12 (0x0000000C)
MMOVIZ MR1, #-6.5 ; MR1 = -6.5 (0xC0D00000)
MF32TOUI32 MR2, MR1 ; MR2 = MF32TOUI32 (MR1) = 0.0 (0x00000000)

See also
MF32TOI32 MRa, MRb
MI32TOF32 MRa, MRb
MI32TOF32 MRa, mem32
MUI32TOF32 MRa, MRb
MUI32TOF32 MRa, mem32

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MFRACF32 MRa, MRb

Fractional Portion of a 32-Bit Floating-Point Value

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1110 0000 0000

Description
Returns in MRa the fractional portion of the 32-bit floating-point value in MRb

Flags
This instruction does not affect any flags:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline
This is a single-cycle instruction.

Example
MMOVIZ MR2, #19.625 ; MR2 = 19.625 (0x419D0000)
MFRACF32 MR3, MR2 ; MR3 = MFRACF32(MR2) = 0.625 (0x3F200000)0)

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MI16TOF32 MRa, MRb

Convert 16-Bit Integer to 32-Bit Floating-Point Value

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1110 1000 0000

Description
Convert the 16-bit signed integer in MRb to a 32-bit floating-point value and store the
result in MRa.

MRa = MI16TOF32(MRb);

Flags
This instruction does not affect any flags:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline
This is a single-cycle instruction.

Example
MMOVIZ MR0, #0x0000 ; MR0(31:16) = 0.0 (0x0000)
MMOVXI MR0, #0x0004 ; MR0(15:0) = 4.0 (0x0004)
MI16TOF32 MR1, MR0 ; MR1 = MI16TOF32 (MR0) = 4.0 (0x40800000)
MMOVIZ MR2, #0x0000 ; MR2(31:16) = 0.0 (0x0000)
MMOVXI MR2, #0xFFFC ; MR2(15:0) = -4.0 (0xFFFC)
MI16TOF32 MR3, MR2 ; MR3 = MI16TOF32 (MR2) = -4.0 (0xC0800000)
MSTOP

See also
MF32TOI16 MRa, MRb
MF32TOI16R MRa, MRb
MF32TOUI16 MRa, MRb
MF32TOUI16R MRa, MRb
MI16TOF32 MRa, mem16
MUI16TOF32 MRa, mem16
MUI16TOF32 MRa, MRb

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MI16TOF32 MRa, mem16

Convert 16-Bit Integer to 32-Bit Floating-Point Value

Operands MRa CLA floating-point destination register (MR0 to MR3)

mem16 16-bit source memory location to be converted

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0111 0101 00aa addr

Description
Convert the 16-bit signed integer indicated by the mem16 pointer to a 32-bit floating-point
value and store the result in MRa.

MRa = MI16TOF32[mem16];

Flags
This instruction does not affect any flags:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline
This is a single-cycle instruction:

Example
; Assume A = 4 (0x0004)
; B = -4 (0xFFFC)
MI16TOF32 MR0, @_A ; MR0 = MI16TOF32(A) = 4.0 (0x40800000)
MI16TOF32 MR1, @_B ; MR1 = MI16TOF32(B) = -4.0 (0xC0800000

See also
MF32TOI16 MRa, MRb
MF32TOI16R MRa, MRb
MF32TOUI16 MRa, MRb
MF32TOUI16R MRa, MRb
MI16TOF32 MRa, MRb
MUI16TOF32 MRa, mem16
MUI16TOF32 MRa, MRb

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MI32TOF32 MRa, mem32

Convert 32-Bit Integer to 32-Bit Floating-Point Value

Operands MRa CLA floating-point destination register (MR0 to MR3)

mem32 32-bit memory source for the MMOV32 operation.

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0111 0100 01aa addr

Description
Convert the 32-bit signed integer indicated by mem32 to a 32-bit floating-point value and
store the result in MRa.

MRa = MI32TOF32[mem32];

Flags
This instruction does not affect any flags:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline
This is a single-cycle instruction.

Example
; Given X, M and B are IQ24 numbers:
; X = IQ24(+2.5) = 0x02800000
; M = IQ24(+1.5) = 0x01800000
; B = IQ24(-0.5) = 0xFF800000
;
; Calculate Y = X * M + B
;
; Convert M, X, and B from IQ24 to float
;
_Cla1Task3:
MI32TOF32 MR0, @_M ; MR0 = 0x4BC00000
MI32TOF32 MR1, @_X ; MR1 = 0x4C200000
MI32TOF32 MR2, @_B ; MR2 = 0xCB000000
MMPYF32 MR0, MR0, #0x3380 ; M = 1/(1*2^24) * iqm = 1.5 (0x3FC00000)
MMPYF32 MR1, MR1, #0x3380 ; X = 1/(1*2^24) * iqx = 2.5 (0x40200000)
MMPYF32 MR2, MR2, #0x3380 ; B = 1/(1*2^24) * iqb = -.5 (0xBF000000)
MMPYF32 MR3, MR0, MR1 ; M*X
MADDF32 MR2, MR2, MR3 ; Y=MX+B = 3.25 (0x40500000)
; Convert Y from float32 to IQ24
MMPYF32 MR2, MR2, #0x4B80 ; Y * 1*2^24
MF32TOI32 MR2, MR2 ; IQ24(Y) = 0x03400000
MMOV32 @_Y, MR2 ; store result
MSTOP ; end of task

See also
MF32TOI32 MRa, MRb
MF32TOUI32 MRa, MRb
MI32TOF32 MRa, MRb
MUI32TOF32 MRa, MRb
MUI32TOF32 MRa, mem32

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MI32TOF32 MRa, MRb

Convert 32-Bit Integer to 32-Bit Floating-Point Value

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1101 1000 0000

Description
Convert the signed 32-bit integer in MRb to a 32-bit floating-point value and store the
result in MRa.

MRa = MI32TOF32(MRb);

Flags
This instruction does not affect any flags:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline
This is a single-cycle instruction.

Example
MMOVIZ MR2, #0x1111 ; MR2(31:16) = 4369 (0x1111)
MMOVXI MR2, #0x1111 ; MR2(15:0) = 4369 (0x1111)
; MR2 = +286331153 (0x11111111)
MI32TOF32 MR3, MR2 ; MR3 = MI32TOF32 (MR2) = 286331153.0 (0x4D888888)

See also
MF32TOI32 MRa, MRb
MF32TOUI32 MRa, MRb
MI32TOF32 MRa, mem32
MUI32TOF32 MRa, MRb
MUI32TOF32 MRa, mem32

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MLSL32 MRa, #SHIFT

Logical Shift Left

Operands MRa CLA floating-point source/destination register (MR0 to MR3)

#SHIFT Number of bits to shift (1 to 32)

Opcode
LSW: 0000 0000 0shi ftaa
MSW: 0111 1011 1100 0000

Description
Logical shift-left of MRa by the number of bits indicated. The number of bits can be 1 to
32.

MARa(31:0) = Logical Shift Left(MARa(31:0) by #SHIFT bits);

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified based on the integer results of the operation.

NF = MRa(31);
ZF = 0;
if(MRa(31:0) == 0) { ZF = 1; }

Pipeline
This is a single-cycle instruction.

Example
; Given m2 = (int32)32
; x2 = (int32)64
; b2 = (int32)-128
;
; Calculate:
; m2 = m2*2
; x2 = x2*4
; b2 = b2*8
;
_Cla1Task3:
MMOV32 MR0, @_m2 ; MR0 = 32 (0x00000020)
MMOV32 MR1, @_x2 ; MR1 = 64 (0x00000040)
MMOV32 MR2, @_b2 ; MR2 = -128 (0xFFFFFF80)
MLSL32 MR0, #1 ; MR0 = 64 (0x00000040)
MLSL32 MR1, #2 ; MR1 = 256 (0x00000100)
MLSL32 MR2, #3 ; MR2 = -1024 (0xFFFFFC00)
MMOV32 @_m2, MR0 ; Store results
MMOV32 @_x2, MR1
MMOV32 @_b2, MR2
MSTOP ; end of task

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MLSL32 MRa, #SHIFT (continued)

Logical Shift Left

See also
MADD32 MRa, MRb, MRc
MASR32 MRa, #SHIFT
MAND32 MRa, MRb, MRc
MLSR32 MRa, #SHIFT
MOR32 MRa, MRb, MRc
MXOR32 MRa, MRb, MRc
MSUB32 MRa, MRb, MRc

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MLSR32 MRa, #SHIFT

Logical Shift Right

Operands MRa CLA floating-point source/destination register (MR0 to MR3)

#SHIFT Number of bits to shift (1 to 32)

Opcode
LSW: 0000 0000 0shi ftaa
MSW: 0111 1011 1000 0000

Description
Logical shift-right of MRa by the number of bits indicated. The number of bits can be 1 to
32. Unlike the arithmetic shift (MASR32), the logical shift does not preserve the number's
sign bit. Every bit in the operand is moved the specified number of bit positions, and the
vacant bit positions are filled in with zeros.

MARa(31:0) = Logical Shift Right(MARa(31:0) by #SHIFT bits);

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified based on the integer results of the operation.

NF = MRa(31);
ZF = 0;
if(MRa(31:0) == 0) { ZF = 1;}

Pipeline
This is a single-cycle instruction.

Example
; Illustrate the difference between MASR32 and MLSR32
MMOVIZ MR0, #0xAAAA ; MR0 = 0xAAAA5555
MMOVXI MR0, #0x5555
MMOV32 MR1, MR0 ; MR1 = 0xAAAA5555
MMOV32 MR2, MR0 ; MR2 = 0xAAAA5555
MASR32 MR1, #1 ; MR1 = 0xD5552AAA
MLSR32 MR2, #1 ; MR2 = 0x55552AAA
MASR32 MR1, #1 ; MR1 = 0xEAAA9555
MLSR32 MR2, #1 ; MR2 = 0x2AAA9555
MASR32 MR1, #6 ; MR1 = 0xFFAAAA55
MLSR32 MR2, #6 ; MR2 = 0x00AAAA55

See also
MADD32 MRa, MRb, MRc
MASR32 MRa, #SHIFT
MAND32 MRa, MRb, MRc
MLSL32 MRa, #SHIFT
MOR32 MRa, MRb, MRc
MXOR32 MRa, MRb, MRc
MSUB32 MRa, MRb, MRc

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MMACF32 MR3, MR2, MRd, MRe, MRf ||MMOV32 MRa, mem32

32-Bit Floating-Point Multiply and Accumulate with Parallel Move

Operands MR3 floating-point destination/source register MR3 for the add

operation
MR2 CLA floating-point source register MR2 for the add operation
MRd CLA floating-point destination register (MR0 to MR3) for the
multiply operation
MRd cannot be the same register as MRa
MRe CLA floating-point source register (MR0 to MR3) for the multiply
operation
MRf CLA floating-point source register (MR0 to MR3) for the multiply
operation
MRa CLA floating-point destination register for the MMOV32 operation
(MR0 to MR3).
MRa cannot be MR3 or the same register as MRd.
mem32 32-bit source for the MMOV32 operation

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0011 ffee ddaa addr

Description
Multiply and accumulate the contents of floating-point registers and move from register to
memory. The destination register for the MMOV32 cannot be the same as the destination
registers for the MMACF32.

MR3 = MR3 + MR2;

MRd = MRe * MRf;
MRa = [mem32];

Restrictions
The destination registers for the MMACF32 and the MMOV32 must be unique. That is,
MRa cannot be MR3 and MRa cannot be the same register as MRd.

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MMACF32 (add or multiply) generates an underflow condition.
• LVF = 1 if MMACF32 (add or multiply) generates an overflow condition.
MMOV32 sets the NF and ZF flags as follows:

NF = MRa(31);
ZF = 0;
if(MRa(30:23) == 0) { ZF = 1; NF = 0; }

Pipeline
MMACF32 and MMOV32 complete in a single cycle.

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MMACF32 MR3, MR2, MRd, MRe, MRf ||MMOV32 MRa, mem32 (continued)

32-Bit Floating-Point Multiply and Accumulate with Parallel Move

Example 1
; Perform 5 multiply and accumulate operations:
;
; X and Y are 32-bit floating-point arrays
;
; 1st multiply: A = X0 * Y0
; 2nd multiply: B = X1 * Y1
; 3rd multiply: C = X2 * Y2
; 4th multiply: D = X3 * Y3
; 5th multiply: E = X3 * Y3
;
; Result = A + B + C + D + E
;
_Cla1Task1:
MMOVI16 MAR0, #_X ; MAR0 points to X array
MMOVI16 MAR1, #_Y ; MAR1 points to Y array
MNOP ; Delay for MAR0, MAR1 load
MNOP ; Delay for MAR0, MAR1 load
; <-- MAR0 valid
MMOV32 MR0, *MAR0[2]++ ; MR0 = X0, MAR0 += 2
; <-- MAR1 valid
MMOV32 MR1, *MAR1[2]++ ; MR1 = Y0, MAR1 += 2
MMPYF32 MR2, MR0, MR1 ; MR2 = A = X0 * Y0
|| MMOV32 MR0, *MAR0[2]++ ; In parallel MR0 = X1, MAR0 += 2
MMOV32 MR1, *MAR1[2]++ ; MR1 = Y1, MAR1 += 2
MMPYF32 MR3, MR0, MR1 ; MR3 = B = X1 * Y1
|| MMOV32 MR0, *MAR0[2]++ ; In parallel MR0 = X2, MAR0 += 2
MMOV32 MR1, *MAR1[2]++ ; MR1 = Y2, MAR2 += 2
MMACF32 MR3, MR2, MR2, MR0, MR1 ; MR3 = A + B, MR2 = C = X2 * Y2
|| MMOV32 MR0, *MAR0[2]++ ; In parallel MR0 = X3
MMOV32 MR1, *MAR1[2]++ ; MR1 = Y3 M
MACF32 MR3, MR2, MR2, MR0, MR1 ; MR3 = (A + B) + C, MR2 = D = X3 * Y3
|| MMOV32 MR0, *MAR0 ; In parallel MR0 = X4
MMOV32 MR1, *MAR1 ; MR1 = Y4
MMPYF32 MR2, MR0, MR1 ; MR2 = E = X4 * Y4
|| MADDF32 MR3, MR3, MR2 ; in parallel MR3 = (A + B + C) + D
MADDF32 MR3, MR3, MR2 ; MR3 = (A + B + C + D) + E
MMOV32 @_Result, MR3 ; Store the result
MSTOP ; end of task

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MMACF32 MR3, MR2, MRd, MRe, MRf ||MMOV32 MRa, mem32 (continued)

32-Bit Floating-Point Multiply and Accumulate with Parallel Move

Example 2
; sum = X0*B0 + X1*B1 + X2*B2 + Y1*A1 + Y2*B2
;
; X2 = X1
; X1 = X0
; Y2 = Y1 ; Y1 = sum
;
_ClaTask2:
MMOV32 MR0, @_B2 ; MR0 = B2
MMOV32 MR1, @_X2 ; MR1 = X2
MMPYF32 MR2, MR1, MR0 ; MR2 = X2*B2
|| MMOV32 MR0, @_B1 ; MR0 = B1
MMOVD32 MR1, @_X1 ; MR1 = X1, X2 = X1
MMPYF32 MR3, MR1, MR0 ; MR3 = X1*B1
|| MMOV32 MR0, @_B0 ; MR0 = B0
MMOVD32 MR1, @_X0 ; MR1 = X0, X1 = X0
; MR3 = X1*B1 + X2*B2, MR2 = X0*B0
; MR0 = A2
MMACF32 MR3, MR2, MR2, MR1, MR0
|| MMOV32 MR0, @_A2 M

MOV32 MR1, @_Y2 ; MR1 = Y2

; MR3 = X0*B0 + X1*B1 + X2*B2, MR2 = Y2*A2
; MR0 = A1
MMACF32 MR3, MR2, MR2, MR1, MR0
|| MMOV32 MR0, @_A1
MMOVD32 MR1,@_Y1 ; MR1 = Y1, Y2 = Y1
MADDF32 MR3, MR3, MR2 ; MR3 = Y2*A2 + X0*B0 + X1*B1 + X2*B2
|| MMPYF32 MR2, MR1, MR0 ; MR2 = Y1*A1
MADDF32 MR3, MR3, MR2 ; MR3 = Y1*A1 + Y2*A2 + X0*B0 + X1*B1 + X2*B2
MMOV32 @_Y1, MR3 ; Y1 = MR3
MSTOP ; end of task

See also
MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf

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MMAXF32 MRa, MRb

32-Bit Floating-Point Maximum

Operands MRa CLA floating-point source/destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1101 0010 0000

Description
if(MRa < MRb) MRa = MRb;

Special cases for the output from the MMAXF32 operation:

• NaN output is converted to infinity
• A denormalized output is converted to positive zero.

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The ZF and NF flags are configured on the result of the operation, not the result stored in
the destination register.

if(MRa == MRb) {ZF=1; NF=0;}

if(MRa > MRb) {ZF=0; NF=0;}
if(MRa < MRb) {ZF=0; NF=1;}

Pipeline
This is a single-cycle instruction.

Example 1
MMOVIZ MR0, #5.0 ; MR0 = 5.0 (0x40A00000)
MMOVIZ MR1, #-2.0 ; MR1 = -2.0 (0xC0000000)
MMOVIZ MR2, #-1.5 ; MR2 = -1.5 (0xBFC00000)
MMAXF32 MR2, MR1 ; MR2 = -1.5, ZF = NF = 0
MMAXF32 MR1, MR2 ; MR1 = -1.5, ZF = 0, NF = 1
MMAXF32 MR2, MR0 ; MR2 = 5.0, ZF = 0, NF = 1
MAXF32 MR0, MR2 ; MR2 = 5.0, ZF = 1, NF = 0

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MMAXF32 MRa, MRb (continued)

32-Bit Floating-Point Maximum

Example 2
; X is an array of 32-bit floating-point values
; Find the maximum value in an array X
; and store the value in Result
;
_Cla1Task1:
MMOVI16 MAR1,#_X ; Start address
MUI16TOF32 MR0, @_len ; Length of the array
MNOP ; delay for MAR1 load
MNOP ; delay for MAR1 load
MMOV32 MR1, *MAR1[2]++ ; MR1 = X0
LOOP
MMOV32 MR2, *MAR1[2]++ ; MR2 = next element
MMAXF32 MR1, MR2 ; MR1 = MAX(MR1, MR2)
MADDF32 MR0, MR0, #-1.0 ; Decrememt the counter
MCMPF32 MR0 #0.0 ; Set/clear flags for MBCNDD
MNOP
MNOP
MNOP
MBCNDD LOOP, NEQ ; Branch if not equal to zero
MMOV32 @_Result, MR1 ; Always executed
MNOP ; Always executed
MNOP ; Always executed
MSTOP ; End of task

See also
MCMPF32 MRa, MRb
MCMPF32 MRa, #16FHi
MMAXF32 MRa, #16FHi
MMINF32 MRa, MRb
MMINF32 MRa, #16FHi

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MMAXF32 MRa, #16FHi

32-Bit Floating-Point Maximum

Operands MRa CLA floating-point source/destination register (MR0 to MR3)

#16FHi A 16-bit immediate value that represents the upper 16-bits of an
IEEE 32-bit floating-point value. The low 16-bits of the mantissa
are assumed to be all 0.

Opcode
LSW: IIII IIII IIII IIII
MSW: 0111 1001 0000 00aa

Description
Compare MRa with the floating-point value represented by the immediate operand. If the
immediate value is larger, then load the value into MRa.

if(MRa < #16FHi:0) MRa = #16FHi:0;

#16FHi is a 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit
floating-point value. The low 16-bits of the mantissa are assumed to be all 0. This
addressing mode is most useful for constants where the lowest 16-bits of the mantissa
are 0. Some examples are 2.0 (0x40000000), 4.0 (0x40800000), 0.5 (0x3F000000), and
-1.5 (0xBFC00000). The assembler accepts either a hex or float as the immediate value.
That is, -1.5 can be represented as #-1.5 or #0xBFC0.
Special cases for the output from the MMAXF32 operation:
• NaN output is converted to infinity
• A denormalized output is converted to positive zero.

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The ZF and NF flags are configured on the result of the operation, not the result stored in
the destination register.

if(MRa == #16FHi:0) {ZF=1; NF=0;}

if(MRa > #16FHi:0) {ZF=0; NF=0;}
if(MRa < #16FHi:0) {ZF=0; NF=1;}

Pipeline
This is a single-cycle instruction.

Example
MMOVIZ MR0, #5.0 ; MR0 = 5.0 (0x40A00000)
MMOVIZ MR1, #4.0 ; MR1 = 4.0 (0x40800000)
MMOVIZ MR2, #-1.5 ; MR2 = -1.5 (0xBFC00000)
MMAXF32 MR0, #5.5 ; MR0 = 5.5, ZF = 0, NF = 1
MMAXF32 MR1, #2.5 ; MR1 = 4.0, ZF = 0, NF = 0
MMAXF32 MR2, #-1.0 ; MR2 = -1.0, ZF = 0, NF = 1
MMAXF32 MR2, #-1.0 ; MR2 = -1.5, ZF = 1, NF = 0

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MMAXF32 MRa, #16FHi (continued)

32-Bit Floating-Point Maximum

See also
MMAXF32 MRa, MRb
MMINF32 MRa, MRb
MMINF32 MRa, #16FHi

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MMINF32 MRa, MRb

32-Bit Floating-Point Minimum

Operands MRa CLA floating-point source/destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1101 0100 0000

Description
if(MRa > MRb) MRa = MRb;

Special cases for the output from the MMINF32 operation:

• NaN output is converted to infinity
• A denormalized output is converted to positive zero.

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The ZF and NF flags are configured on the result of the operation, not the result stored in
the destination register.

if(MRa == MRb) {ZF=1; NF=0;}

if(MRa > MRb) {ZF=0; NF=0;}
if(MRa < MRb) {ZF=0; NF=1;}

Pipeline
This is a single-cycle instruction.

Example 1
MMOVIZ MR0, #5.0 ; MR0 = 5.0 (0x40A00000)
MMOVIZ MR1, #4.0 ; MR1 = 4.0 (0x40800000)
MMOVIZ MR2, #-1.5 ; MR2 = -1.5 (0xBFC00000)
MMINF32 MR0, MR1 ; MR0 = 4.0, ZF = 0, NF = 0
MMINF32 MR1, MR2 ; MR1 = -1.5, ZF = 0, NF = 0
MMINF32 MR2, MR1 ; MR2 = -1.5, ZF = 1, NF = 0
MMINF32 MR1, MR0 ; MR2 = -1.5, ZF = 0, NF = 1

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MMINF32 MRa, MRb (continued)

32-Bit Floating-Point Minimum

Example 2
;
; X is an array of 32-bit floating-point values
; Find the minimum value in an array X
; and store the value in Result
;
_Cla1Task1:
MMOVI16 MAR1,#_X ; Start address
MUI16TOF32 MR0, @_len ; Length of the array
MNOP ; delay for MAR1 load
MNOP ; delay for MAR1 load
MMOV32 MR1, *MAR1[2]++ ; MR1 = X0
LOOP
MMOV32 MR2, *MAR1[2]++ ; MR2 = next element
MMINF32 MR1, MR2 ; MR1 = MAX(MR1, MR2)
MADDF32 MR0, MR0, #-1.0 ; Decrememt the counter
MCMPF32 MR0 #0.0 ; Set/clear flags for MBCNDD
MNOP
MNOP
MNOP
MBCNDD LOOP, NEQ ; Branch if not equal to zero
MMOV32 @_Result, MR1 ; Always executed
MNOP ; Always executed
MNOP ; Always executed
MSTOP ; End of task

See also
MMAXF32 MRa, MRb
MMAXF32 MRa, #16FHi
MMINF32 MRa, #16FHi

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MMINF32 MRa, #16FHi

32-Bit Floating-Point Minimum

Operands MRa floating-point source/destination register (MR0 to MR3)

#16FHi A 16-bit immediate value that represents the upper 16-bits of an
IEEE 32-bit floating-point value. The low 16-bits of the mantissa
are assumed to be all 0.

Opcode
LSW: IIII IIII IIII IIII
MSW: 0111 1001 0100 00aa

Description
Compare MRa with the floating-point value represented by the immediate operand. If the
immediate value is smaller, then load the value into MRa.

if(MRa > #16FHi:0) MRa = #16FHi:0;

#16FHi is a 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit
floating-point value. The low 16-bits of the mantissa are assumed to be all 0. This
addressing mode is most useful for constants where the lowest 16-bits of the mantissa
are 0. Some examples are 2.0 (0x40000000), 4.0 (0x40800000), 0.5 (0x3F000000), and
-1.5 (0xBFC00000). The assembler accepts either a hex or float as the immediate value.
That is, -1.5 can be represented as #-1.5 or #0xBFC0.
Special cases for the output from the MMINF32 operation:
• NaN output is converted to infinity
• A denormalized output is converted to positive zero.

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The ZF and NF flags are configured on the result of the operation, not the result stored in
the destination register.

if(MRa == #16FHi:0) {ZF=1; NF=0;}

if(MRa > #16FHi:0) {ZF=0; NF=0;}
if(MRa < #16FHi:0) {ZF=0; NF=1;}

Pipeline
This is a single-cycle instruction.

Example
MMOVIZ MR0, #5.0 ; MR0 = 5.0 (0x40A00000)
MMOVIZ MR1, #4.0 ; MR1 = 4.0 (0x40800000)
MMOVIZ MR2, #-1.5 ; MR2 = -1.5 (0xBFC00000)
MMINF32 MR0, #5.5 ; MR0 = 5.0, ZF = 0, NF = 1
MMINF32 MR1, #2.5 ; MR1 = 2.5, ZF = 0, NF = 0
MMINF32 MR2, #-1.0 ; MR2 = -1.5, ZF = 0, NF = 1
MMINF32 MR2, #-1.5 ; MR2 = -1.5, ZF = 1, NF = 0

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MMINF32 MRa, #16FHi (continued)

32-Bit Floating-Point Minimum

See also
MMAXF32 MRa, #16FHi
MMAXF32 MRa, MRb
MMINF32 MRa, MRb

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MMOV16 MARx, MRa, #16I

Load the Auxiliary Register with MRa + 16-bit Immediate Value

Operands MARx Auxiliary register MAR0 or MAR1

MRa CLA Floating-point register (MR0 to MR3)
#16I 16-bit immediate value

Opcode
LSW: IIII IIII IIII IIII (opcode of MMOV16 MAR0, MRa, #16I)
MSW: 0111 1111 1101 00AA
LSW: IIII IIII IIII IIII (opcode of MMOV16 MAR1, MRa, #16I)
MSW: 0111 1111 1111 00AA

Description
Load the auxiliary register, MAR0 or MAR1, with MRa(15:0) + 16-bit immediate value.
Refer to the Pipeline section for important information regarding this instruction.

MARx = MRa(15:0) + #16I;

Flags
This instruction does not modify flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline
This is a single-cycle instruction. The load of MAR0 or MAR1 occurs in the EXE phase
of the pipeline. Any post increment of MAR0 or MAR1 using indirect addressing occurs in
the D2 phase of the pipeline. Therefore, the following applies when loading the auxiliary
registers:
• I1 and I2
The two instructions following MMOV16 use MAR0 or MAR1 before the update occurs.
Thus, these two instructions use the old value of MAR0 or MAR1.
• I3
Loading of an auxiliary register occurs in the EXE phase while updates due to post-
increment addressing occur in the D2 phase. Thus, I3 cannot use the auxiliary register
or there is a conflict. In the case of a conflict, the update due to address-mode post
increment wins and the auxiliary register is not updated with #_X.
• I4
Starting with the 4th instruction, MAR0 or MAR1 is the new value loaded with
MMOVI16.

; Assume MAR0 is 50, MR0 is 10, and #_X is 20

MMOV16 MAR0, MR0, #_X ; Load MAR0 with address of X (20) + MR0 (10)
<Instruction 1> ; I1 Uses the old value of MAR0 (50)
<Instruction 2> ; I2 Uses the old value of MAR0 (50)
<Instruction 3> ; I3 Cannot use MAR0
<Instruction 4> ; I4 Uses the new value of MAR0 (30)
<Instruction 5> ; I5

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MMOV16 MARx, MRa, #16I (continued)

Load the Auxiliary Register with MRa + 16-bit Immediate Value

Table 6-15. Pipeline Activity for MMOV16 MARx, MRa , #16I

Instruction F1 F2 D1 D2 R1 R2 E W
MMOV16 MAR0, MR0,
MMOV16
#_X
I1 I1 MMOV16
I2 I2 I1 MMOV16
I3 I3 I2 I1 MMOV16
I4 I4 I3 I2 I1 MMOV16
I5 I5 I4 I3 I2 I1 MMOV16
I6 I6 I5 I4 I3 I2 I1 MMOV16

Example 1
; Calculate an offset into a sin/cos table
;
_Cla1Task1:
MMOV32 MR0,@_rad ; MR0 = rad
MMOV32 MR1,@_TABLE_SIZEDivTwoPi ; MR1 = TABLE_SIZE/(2*Pi)
MMPYF32 MR1,MR0,MR1 ; MR1 = rad* TABLE_SIZE/(2*Pi)
|| MMOV32 MR2,@_TABLE_MASK ; MR2 = TABLE_MASK
MF32TOI32 MR3,MR1 ; MR3 = K=int(rad*TABLE_SIZE/(2*Pi))
MAND32 MR3,MR3,MR2 ; MR3 = K & TABLE_MASK
MLSL32 MR3,#1 ; MR3 = K * 2
MMOV16 MAR0,MR3,#_Cos0 ; MAR0 K*2+addr of table.Cos0
MFRACF32 MR1,MR1 ; I1
MMOV32 MR0,@_TwoPiDivTABLE_SIZE ; I2
MMPYF32 MR1,MR1,MR0 ; I3
|| MMOV32 MR0,@_Coef3
MMOV32 MR2,*MAR0[#-64]++ ; MR2 = *MAR0, MAR0 += (-64)
...
...
MSTOP ; end of task

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MMOV16 MARx, MRa, #16I (continued)

Load the Auxiliary Register with MRa + 16-bit Immediate Value

Example 2
; This task logs the last NUM_DATA_POINTS
; ADCRESULT1 values in the array VoltageCLA
;
; When the last element in the array has been
; filled, the task goes back to the
; the first element.
;
; Before starting the ADC conversions, force
; Task 8 to initialize the ConversionCount to zero
;
; The ADC is set to sample (acquire) for 15 SYSCLK cycles
; or 75ns. After the capacitor has captured the analog
; value, the ADC triggers this task early.
; It takes 10.5 ADCCLKs to complete a conversion,
; the ADCCLK being SYSCLK/4
; T_sys = 1/200MHz = 5ns
; T_adc = 4*T_sys = 20ns
; The ADC takes 10.5 * 4 or 42 SYSCLK cycles to complete
; a conversion. The ADC result register can be read on the
; 36th instruction after the task begins.
;
_Cla1Task2:
.asg 0, N
.loop
MNOP ;I1 - I28 Wait till I36 to read
result
.eval N + 1, N
.break N = 28
.endloop
MMOVZ16 MR0, @_ConversionCount ;I29 Current Conversion
MMOV16 MAR1, MR0, #_VoltageCLA ;I30 Next array location
MUI16TOF32 MR0, MR0 ;I31 Convert count to float32
MADDF32 MR0, MR0, #1.0 ;I32 Add 1 to conversion count
MCMPF32 MR0, #NUM_DATA_POINTS.0 ;I33 Compare count to max
MF32TOUI16 MR0, MR0 ;I34 Convert count to Uint16
MNOP ;I35 Wait till I36 to read
result
MMOVZ16 MR2, @_AdcaResultRegs.ADCRESULT1 ;I36 Read ADCRESULT1
MMOV16 *MAR1, MR2 ; Store ADCRESULT1
MBCNDD _RestartCount, GEQ ; If count >= NUM_DATA_POINTS
MMOVIZ MR1, #0.0 ; Always executed: MR1=0
MNOP
MNOP
MMOV16 @_ConversionCount, MR0 ; If branch not taken
MSTOP ; store current count
_RestartCount
MMOV16 @_ConversionCount, MR1 ; If branch taken, restart
count
MSTOP ; end of task
; This task initializes the ConversionCount
; to zero
;
_Cla1Task8:
MMOVIZ MR0, #0.0
MMOV16 @_ConversionCount, MR0
MSTOP
_ClaT8End:

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MMOV16 MARx, mem16

Load MAR1 with 16-bit Value

Operands MARx CLA auxiliary register MAR0 or MAR1

mem16 16-bit destination memory accessed using one of the available
addressing modes

Opcode
LSW: mmmm mmmm mmmm mmmm (Opcode for MMOV16 MAR0, mem16)
MSW: 0111 0110 0000 addr
LSW: mmmm mmmm mmmm mmmm (Opcode for MMOV16 MAR1, mem16)
MSW: 0111 0110 0100 addr

Description
Load MAR0 or MAR1 with the 16-bit value pointed to by mem16. Refer to the Pipeline
section for important information regarding this instruction.

MAR1 = [mem16];

Flags
No flags MSTF flags are affected.
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline
This is a single-cycle instruction. The load of MAR0 or MAR1 occurs in the EXE phase
of the pipeline. Any post increment of MAR0 or MAR1 using indirect addressing occurs in
the D2 phase of the pipeline. Therefore, the following applies when loading the auxiliary
registers:
• I1 and I2
The two instructions following MMOV16 use MAR0 or MAR1 before the update occurs.
Thus, these two instructions use the old value of MAR0 or MAR1.
• I3
Loading of an auxiliary register occurs in the EXE phase while updates due to post-
increment addressing occur in the D2 phase. Thus, I3 cannot use the auxiliary register
or there is a conflict. In the case of a conflict, the update due to address-mode post
increment, the auxiliary register is not updated with #_X.
• I4
Starting with the 4th instruction, MAR0 or MAR1 is the new value loaded with
MMOV16.

; Assume MAR0 is 50 and @_X is 20

MMOV16 MAR0, @_X ; Load MAR0 with the contents of X (20)
<Instruction 1> ; I1 Uses the old value of MAR0 (50)
<Instruction 2> ; I2 Uses the old value of MAR0 (50)
<Instruction 3> ; I3 Cannot use MAR0
<Instruction 4> ; I4 Uses the new value of MAR0 (20)
<Instruction 5> ; I5
....

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MMOV16 MARx, mem16 (continued)

Load MAR1 with 16-bit Value

Table 6-16. Pipeline Activity for MMOV16 MAR0/MAR1, mem16

Instruction F1 F2 D1 D2 R1 R2 E W
MMOV16 MAR0, @_X MMOV16
I1 I1 MMOV16
I2 I2 I1 MMOV16
I3 I3 I2 I1 MMOV16
I4 I4 I3 I2 I1 MMOV16
I5 I5 I4 I3 I2 I1 MMOV16
I6 I6 I5 I4 I3 I2 I1 MMOV16

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MMOV16 MARx, mem16 (continued)

Load MAR1 with 16-bit Value

Example
; This task logs the last NUM_DATA_POINTS
; ADCRESULT1 values in the array VoltageCLA
;
; When the last element in the array has been
; filled, the task goes back to the
; the first element.
;
; Before starting the ADC conversions, force
; Task 8 to initialize the ConversionCount to zero
;
; The ADC is set to sample (acquire) for 15 SYSCLK cycles
; or 75ns. After the capacitor has captured the analog
; value, the ADC triggers this task early.
; It takes 10.5 ADCCLKs to complete a conversion,
; the ADCCLK being SYSCLK/4
; T_sys = 1/200MHz = 5ns
; T_adc = 4*T_sys = 20ns
; The ADC takes 10.5 * 4 or 42 SYSCLK cycles to complete
; a conversion. The ADC result register can be read on the
; 36th instruction after the task begins.
;
_Cla1Task2:
.asg 0, N
.loop
MNOP
;I1 - I28 Wait till I36 to read result
.eval N + 1, N
.break N = 28
.endloop
MMOVZ16 MR0, @_ConversionCount ;I29 Current Conversion
MMOV16 MAR1, MR0, #_VoltageCLA ;I30 Next array location
MUI16TOF32 MR0, MR0 ;I31 Convert count to float32
MADDF32 MR0, MR0, #1.0 ;I32 Add 1 to conversion count
MCMPF32 MR0, #NUM_DATA_POINTS.0 ;I33 Compare count to max
MF32TOUI16 MR0, MR0 ;I34 Convert count to Uint16
MNOP ;I35 Wait until I36 to read
result
MMOVZ16 MR2, @_AdcaResultRegs.ADCRESULT1 ;I36 Read ADCRESULT1
MMOV16 *MAR1, MR2 ; Store ADCRESULT1
MBCNDD _RestartCount, GEQ ; If count >= NUM_DATA_POINTS
MMOVIZ MR1, #0.0 ; Always executed: MR1=0
MNOP
MNOP
MMOV16 @_ConversionCount, MR0 ; If branch not taken
MSTOP ; store current count
_RestartCount
MMOV16 @_ConversionCount, MR1 ; If branch taken, restart
count
MSTOP ; end of task
; This task initializes the ConversionCount
; to zero
;
_Cla1Task8:
MMOVIZ MR0, #0.0
MMOV16 @_ConversionCount, MR0
MSTOP
_ClaT8End:

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MMOV16 mem16, MARx

Move 16-Bit Auxiliary Register Contents to Memory

Operands mem16 16-bit destination memory accessed using one of the available
addressing modes
MARx CLA auxiliary register MAR0 or MAR1

Opcode
LSW: mmmm mmmm mmmm mmmm (Opcode for MMOV16 mem16, MAR0)
MSW: 0111 0110 1000 addr
LSW: mmmm mmmm mmmm mmmm (Opcode for MMOV16 mem16, MAR1)
MSW: 0111 0110 1100 addr

Description
Store the contents of MAR0 or MAR1 in the 16-bit memory location pointed to by mem16.

[mem16] = MAR0;

Flags
No flags MSTF flags are affected.
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline
This is a single-cycle instruction.

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MMOV16 mem16, MRa

Move 16-Bit Floating-Point Register Contents to Memory

Operands mem16 16-bit destination memory accessed using one of the available
addressing modes
MRa CLA floating-point source register (MR0 to MR3)

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0111 0101 11aa addr

Description
Move 16-bit value from the lower 16-bits of the floating-point register (MRa(15:0)) to the
location pointed to by mem16.

[mem16] = MRa(15:0);

Flags
No flags MSTF flags are affected.
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline
This is a single-cycle instruction.

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MMOV16 mem16, MRa (continued)

Move 16-Bit Floating-Point Register Contents to Memory

Example
; This task logs the last NUM_DATA_POINTS
; ADCRESULT1 values in the array VoltageCLA
;
; When the last element in the array has been
; filled, the task goes back to the
; the first element.
;
; Before starting the ADC conversions, force
; Task 8 to initialize the ConversionCount to zero
;
; The ADC is set to sample (acquire) for 15 SYSCLK cycles
; or 75ns. After the capacitor has captured the analog
; value, the ADC triggers this task early.
; It takes 10.5 ADCCLKs to complete a conversion,
; the ADCCLK being SYSCLK/4
; T_sys = 1/200MHz = 5ns
; T_adc = 4*T_sys = 20ns
; The ADC takes 10.5 * 4 or 42 SYSCLK cycles to complete
; a conversion. The ADC result register can be read on the
; 36th instruction after the task begins.
;
_Cla1Task2:
.asg 0, N
.loop
MNOP
;I1 - I28 Wait till I36 to read result
.eval N + 1, N
.break N = 28
.endloop
MMOVZ16 MR0, @_ConversionCount ;I29 Current Conversion
MMOV16 MAR1, MR0, #_VoltageCLA ;I30 Next array location
MUI16TOF32 MR0, MR0 ;I31 Convert count to float32
MADDF32 MR0, MR0, #1.0 ;I32 Add 1 to conversion count
MCMPF32 MR0, #NUM_DATA_POINTS.0 ;I33 Compare count to max
MF32TOUI16 MR0, MR0 ;I34 Convert count to Uint16
MNOP ;I35 Wait till I36 to read
result
MMOVZ16 MR2, @_AdcaResultRegs.ADCRESULT1 ;I36 Read ADCRESULT1
MMOV16 *MAR1, MR2 ; Store ADCRESULT1
MBCNDD _RestartCount, GEQ ; If count >= NUM_DATA_POINTS
MMOVIZ MR1, #0.0 ; Always executed: MR1=0
MNOP
MNOP
MMOV16 @_ConversionCount, MR0 ; If branch not taken
MSTOP ; store current count
_RestartCount
MMOV16 @_ConversionCount, MR1 ; If branch taken, restart
count
MSTOP ; end of task
; This task initializes the ConversionCount
; to zero
;
_Cla1Task8:
MMOVIZ MR0, #0.0
MMOV16 @_ConversionCount, MR0
MSTOP
_ClaT8End:

See also
MMOVIZ MRa, #16FHi
MMOVXI MRa, #16FLoHex

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MMOV32 mem32, MRa

Move 32-Bit Floating-Point Register Contents to Memory

Operands MRa floating-point register (MR0 to MR3)

mem32 32-bit destination memory accessed using one of the available
addressing modes

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0111 0100 11aa addr

Description
Move from MRa to 32-bit memory location indicated by mem32.

[mem32] = MRa;

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No No No

No flags affected.

Pipeline
This is a single-cycle instruction.

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MMOV32 mem32, MRa (continued)

Move 32-Bit Floating-Point Register Contents to Memory

Example
; Perform 5 multiply and accumulate operations:
;
; X and Y are 32-bit floating-point arrays;
; 1st multiply: A = X0 * Y0
; 2nd multiply: B = X1 * Y1
; 3rd multiply: C = X2 * Y2
; 4th multiply: D = X3 * Y3
; 5th multiply: E = X3 * Y3;
; Result = A + B + C + D + E
;
_Cla1Task1:
MMOVI16 MAR0, #_X ; MAR0 points to X array
MMOVI16 MAR1, #_Y ; MAR1 points to Y array
MNOP ; Delay for MAR0, MAR1 load
MNOP ; Delay for MAR0, MAR1 load
; <-- MAR0 valid
MMOV32 MR0, *MAR0[2]++ ; MR0 = X0, MAR0 += 2
; <-- MAR1 valid
MMOV32 MR1, *MAR1[2]++ ; MR1 = Y0, MAR1 += 2
MMPYF32 MR2, MR0, MR1 ; MR2 = A = X0 * Y0
|| MMOV32 MR0, *MAR0[2]++ ; In parallel MR0 = X1, MAR0 += 2
MMOV32 MR1, *MAR1[2]++ ; MR1 = Y1, MAR1 += 2
MMPYF32 MR3, MR0, MR1 ; MR3 = B = X1 * Y1
|| MMOV32 MR0, *MAR0[2]++ ; In parallel MR0 = X2, MAR0 += 2
MMOV32 MR1, *MAR1[2]++ ; MR1 = Y2, MAR2 += 2
MMACF32 MR3, MR2, MR2, MR0, MR1 ; MR3 = A + B, MR2 = C = X2 * Y2
|| MMOV32 MR0, *MAR0[2]++ ; In parallel MR0 = X3
MMOV32 MR1, *MAR1[2]++ ; MR1 = Y3
MMACF32 MR3, MR2, MR2, MR0, MR1 ; MR3 = (A + B) + C, MR2 = D = X3 *
Y3
|| MMOV32 MR0, *MAR0 ; In parallel MR0 = X4
MMOV32 MR1, *MAR1 ; MR1 = Y4
MMPYF32 MR2, MR0, MR1 ; MR2 = E = X4 * Y4
|| MADDF32 MR3, MR3, MR2 ; in parallel MR3 = (A + B + C) + D
MADDF32 MR3, MR3, MR2 ; MR3 = (A + B + C + D) + E
MMOV32 @_Result, MR3 ; Store the result MSTOP ; end of task

See also
MMOV32 mem32, MSTF

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MMOV32 mem32, MSTF

Move 32-Bit MSTF Register to Memory

Operands MSTF Floating-point status register

mem32 32-bit destination memory

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0111 0111 0100 addr

Description
Copy the CLA floating-point status register, MSTF, to memory.

[mem32] = MSTF;

Flags
This instruction does not modify flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline
This is a single-cycle instruction.
One of the uses of this instruction is to save off the return PC (RPC) prior to calling a
function. The decision to jump to a function is made when the MCCNDD is in the decode2
(D2) phase of the pipeline; the RPC is also updated in this phase. The actual jump occurs
3 cycles later when MCCNDD enters the execution (E) phase. You must save the old RPC
before MCCNDD updates in the D2 phase; that is, save MSTF 3 instructions prior to the
function call.

Example
The following example illustrates the pipeline flow for the context save (of the flags and
RPC) prior to a function call. The first column in the comments shows the pipeline stages
for the MMOV32 instruction while the second column pertains to the MCCNDD instruction.

MMOV32 @_temp, MSTF ; D2| |

MNOP ; R1|F1| MCCNDD is fetched
MNOP ; R2|F2|
MNOP ; E |D1|
MCCNDD _bar, UNC ; W |D2| old RPC written to memory,
; | | RPC updated with MPC+1
MNOP ; |R1|
MNOP ; |R2|
MNOP ; |E | execution branches to _bar

See also
MMOV32 mem32, MRa

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MMOV32 MRa, mem32 {, CNDF}

Conditional 32-Bit Move

Operands MRa CLA floating-point destination register (MR0 to MR3)

mem32 32-bit memory location accessed using one of the available
addressing modes
CNDF Optional condition

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0111 00cn dfaa addr

Description
If the condition is true, then move the 32-bit value referenced by mem32 to the floating-
point register indicated by MRa.

if (CNDF == TRUE) MRa = [mem32];

CNDF is one of the following conditions:

Encode(1) CNDF Description MSTF Flags Tested
0000 NEQ Not equal to zero ZF == 0
0001 EQ Equal to zero ZF == 1
0010 GT Greater than zero ZF == 0 AND NF == 0
0011 GEQ Greater than or equal NF == 0
to zero
0100 LT Less than zero NF == 1
0101 LEQ Less than or equal to ZF == 1 OR NF == 1
zero
1010 TF Test flag set TF == 1
1011 NTF Test flag not set TF == 0
1100 LU Latched underflow LUF == 1
1101 LV Latched overflow LVF == 1
1110 UNC Unconditional None
1111 UNCF(2) Unconditional with flag None
modification

(1) Values not shown are reserved.

(2) This is the default operation, if no CNDF field is specified. This condition
allows the ZF and NF flags to be modified when a conditional operation is
executed. All other conditions do not modify these flags.

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

if(CNDF == UNCF)
{
NF = MRa(31);
ZF = 0;
if(MRa(30:23) == 0) { ZF = 1; NF = 0; }
}
else No flags modified;

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MMOV32 MRa, mem32 {, CNDF} (continued)

Conditional 32-Bit Move

Pipeline
This is a single-cycle instruction.

Example
; Given A, B, X, M1 and M2 are 32-bit floating-point numbers
;
; if(A == B) calculate Y = X*M1
; if(A! = B) calculate Y = X*M2
;
_Cla1Task5:
MMOV32 MR0, @_A
MMOV32 MR1, @_B
MCMPF32 MR0, MR1
MMOV32 MR2, @_M1, EQ ; if A == B, MR2 = M1
; Y = M1*X
MMOV32 MR2, @_M2, NEQ ; if A! = B, MR2 = M2
; Y = M2*X
MMOV32 MR3, @_X
MMPYF32 MR3, MR2, MR3 ; Calculate Y
MMOV32 @_Y, MR3 ; Store Y
MSTOP ; end of task

See also
MMOV32 MRa, MRb {, CNDF}
MMOVD32 MRa, mem32

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MMOV32 MRa, MRb {, CNDF}

Conditional 32-Bit Move

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)
CNDF Optional condition

Opcode
LSW: 0000 0000 cndf bbaa
MSW: 0111 1010 1100 0000

Description
If the condition is true, then move the 32-bit value in MRb to the floating-point register
indicated by MRa.

if (CNDF == TRUE) MRa = MRb;

CNDF is one of the following conditions:

Encode(1) CNDF Description MSTF Flags Tested
0000 NEQ Not equal to zero ZF == 0
0001 EQ Equal to zero ZF == 1
0010 GT Greater than zero ZF == 0 AND NF == 0
0011 GEQ Greater than or equal NF == 0
to zero
0100 LT Less than zero NF == 1
0101 LEQ Less than or equal to ZF == 1 OR NF == 1
zero
1010 TF Test flag set TF == 1
1011 NTF Test flag not set TF == 0
1100 LU Latched underflow LUF == 1
1101 LV Latched overflow LVF == 1
1110 UNC Unconditional None
1111 UNCF(2) Unconditional with flag None
modification

(1) Values not shown are reserved.

(2) This is the default operation, if no CNDF field is specified. This condition
allows the ZF, and NF flags to be modified when a conditional operation is
executed. All other conditions do not modify these flags.

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

if(CNDF == UNCF)
{
NF = MRa(31); ZF = 0;
if(MRa(30:23) == 0) {ZF = 1; NF = 0;}
}
else No flags modified;

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MMOV32 MRa, MRb {, CNDF} (continued)

Conditional 32-Bit Move

Pipeline
This is a single-cycle instruction.

Example
; Given: X = 8.0
; Y = 7.0
; A = 2.0
; B = 5.0
; _ClaTask1
MMOV32 MR3, @_X ; MR3 = X = 8.0
MMOV32 MR0, @_Y ; MR0 = Y = 7.0
MMAXF32 MR3, MR0 ; ZF = 0, NF = 0, MR3 = 8.0
MMOV32 MR1, @_A, GT ; true, MR1 = A = 2.0
MMOV32 MR1, @_B, LT ; false, does not load MR1
MMOV32 MR2, MR1, GT ; true, MR2 = MR1 = 2.0
MMOV32 MR2, MR0, LT ; false, does not load MR2
MSTOP

See also
MMOV32 MRa, mem32 {,CNDF}

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MMOV32 MSTF, mem32

Move 32-Bit Value from Memory to the MSTF Register

Operands MSTF CLA status register

mem32 32-bit source memory location

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0111 0111 0000 addr

Description
Move from memory to the CLA's status register MSTF. This instruction is most useful
when nesting function calls (using MCCNDD).

MSTF = [mem32];

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified Yes Yes Yes Yes Yes

Loading the status register can overwrite all flags and the RPC field. The MEALLOW field
is not affected.

Pipeline
This is a single-cycle instruction.

See also
MMOV32 mem32, MSTF

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MMOVD32 MRa, mem32

Move 32-Bit Value from Memory with Data Copy

Operands MRa CLA floating-point register (MR0 to MR3)

mem32 32-bit memory location accessed using one of the available
addressing modes

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0111 0100 00aa addr

Description
Move the 32-bit value referenced by mem32 to the floating-point register indicated by
MRa.

MRa = [mem32];
[mem32+2] = [mem32];

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

NF = MRa(31);
ZF = 0;
if(MRa(30:23) == 0){ ZF = 1; NF = 0; }

Pipeline
This is a single-cycle instruction.

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MMOVD32 MRa, mem32 (continued)

Move 32-Bit Value from Memory with Data Copy

Example
; sum = X0*B0 + X1*B1 + X2*B2 + Y1*A1 + Y2*B2
;
; X2 = X1
; X1 = X0
; Y2 = Y1
; Y1 = sum
;
_Cla1Task2:
MMOV32 MR0, @_B2 ; MR0 = B2
MMOV32 MR1, @_X2 ; MR1 = X2
MMPYF32 MR2, MR1, MR0 ; MR2 = X2*B2
|| MMOV32 MR0, @_B1 ; MR0 = B1
MMOVD32 MR1, @_X1 ; MR1 = X1, X2 = X1
MMPYF32 MR3, MR1, MR0 ; MR3 = X1*B1
|| MMOV32 MR0, @_B0 ; MR0 = B0
MMOVD32 MR1, @_X0 ; MR1 = X0, X1 = X0
; MR3 = X1*B1 + X2*B2, MR2 = X0*B0
; MR0 = A2
MMACF32 MR3, MR2, MR2, MR1, MR0
|| MMOV32 MR0, @_A2

MMOV32 MR1, @_Y2 ; MR1 = Y2

; MR3 = X0*B0 + X1*B1 + X2*B2, MR2 = Y2*A2
; MR0 = A1
MMACF32 MR3, MR2, MR2, MR1, MR0
|| MMOV32 MR0, @_A1
MMOVD32 MR1,@_Y1 ; MR1 = Y1, Y2 = Y1
MADDF32 MR3, MR3, MR2 ; MR3 = Y2*A2 + X0*B0 + X1*B1 + X2*B2
|| MMPYF32 MR2, MR1, MR0 ; MR2 = Y1*A1
MADDF32 MR3, MR3, MR2 ; MR3 = Y1*A1 + Y2*A2 + X0*B0 + X1*B1 + X2*B2
MMOV32 @_Y1, MR3 ; Y1 = MR3
MSTOP ; end of task

See also
MMOV32 MRa, mem32 {,CNDF}

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MMOVF32 MRa, #32F

Load the 32-Bits of a 32-Bit Floating-Point Register

Operands
This instruction is an alias for the MMOVIZ and MMOVXI instructions. The second
operand is translated by the assembler such that the instruction becomes:

MMOVIZ MRa, #16FHiHex MMOVXI MRa, #16FLoHex

MRa CLA floating-point destination register (MR0 to MR3)

#32F Immediate float value represented in floating-point representation

Opcode
LSW: IIII IIII IIII IIII (opcode of MMOVIZ MRa, #16FHiHex)
MSW: 0111 1000 0100 00aa
LSW: IIII IIII IIII IIII (opcode of MMOVXI MRa, #16FLoHex)
MSW: 0111 1000 1000 00aa

Description
This instruction accepts the immediate operand only in floating-point representation. To
specify the immediate value as a hex value (IEEE 32-bit floating- point format), use the
MOVI32 MRa, #32FHex instruction.
Load the 32-bits of MRa with the immediate float value represented by #32F.
#32F is a float value represented in floating-point representation. The assembler only
accepts a float value represented in floating-point representation. That is, 3.0 can only be
represented as #3.0 (#0x40400000 results in an error).

MRa = #32F;

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline
Depending on #32F, this instruction takes one or two cycles. If all of the lower 16-bits
of the IEEE 32-bit floating-point format of #32F are zeros, then the assembler converts
MMOVF32 into only an MMOVIZ instruction. If the lower 16-bits of the IEEE 32-bit
floating-point format of #32F are not zeros, then the assembler converts MMOVF32 into
MMOVIZ and MMOVXI instructions.

Example
MMOVF32 MR1, #3.0 ; MR1 = 3.0 (0x40400000)
; Assembler converts this instruction as
; MMOVIZ MR1, #0x4040
MMOVF32 MR2, #0.0 ; MR2 = 0.0 (0x00000000)
; Assembler converts this instruction as
; MMOVIZ MR2, #0x0
MMOVF32 MR3, #12.265 ; MR3 = 12.625 (0x41443D71)
; Assembler converts this instruction as
; MMOVIZ MR3, #0x4144
; MMOVXI MR3, #0x3D71

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MMOVF32 MRa, #32F (continued)

Load the 32-Bits of a 32-Bit Floating-Point Register

See also
MMOVIZ MRa, #16FHi
MMOVXI MRa, #16FLoHex
MMOVI32 MRa, #32FHex

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MMOVI16 MARx, #16I

Load the Auxiliary Register with the 16-Bit Immediate Value

Operands MARx Auxiliary register MAR0 or MAR1

#16I 16-bit immediate value

Opcode
LSW: IIII IIII IIII IIII (opcode of MMOVI16 MAR0, #16I)
MSW: 0111 1111 1100 0000
LSW: IIII IIII IIII IIII (opcode of MMOVI16 MAR1, #16I)
MSW: 0111 1111 1110 0000

Description
Load the auxiliary register, MAR0 or MAR1, with a 16-bit immediate value. Refer to the
Pipeline section for important information regarding this instruction.

MARx = #16I;

Flags
This instruction does not modify flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline
This is a single-cycle instruction. The immediate load of MAR0 or MAR1 occurs in
the EXE phase of the pipeline. Any post increment of MAR0 or MAR1 using indirect
addressing occurs in the D2 phase of the pipeline. Therefore, the following applies when
loading the auxiliary registers:
• I1 and I2
The two instructions following MMOVI16 use MAR0 or MAR1 before the update
occurs. Thus, these two instructions use the old value of MAR0 or MAR1.
• I3
Loading of an auxiliary register occurs in the EXE phase while updates due to post-
increment addressing occur in the D2 phase. Thus, I3 cannot use the auxiliary register
or there is a conflict. In the case of a conflict, the update due to address-mode post
increment, the auxiliary register is not updated with #_X.
• I4
Starting with the 4th instruction, MAR0 or MAR1 is the new value loaded with
MMOVI16.

; Assume MAR0 is 50 and #_X is 20

MMOVI16 MAR0, #_X ; Load MAR0 with address of X (20)
<Instruction 1> ; I1 Uses the old value of MAR0 (50)
<Instruction 2> ; I2 Uses the old value of MAR0 (50)
<Instruction 3> ; I3 Cannot use MAR0
<Instruction 4> ; I4 Uses the new value of MAR0 (20)
<Instruction 5> ; I5
....

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MMOVI16 MARx, #16I (continued)

Load the Auxiliary Register with the 16-Bit Immediate Value

Table 6-17. Pipeline Activity for MMOVI16 MAR0/MAR1, #16I

Instruction F1 F2 D1 D2 R1 R2 E W
MMOVI16 MAR0, #_X MMOVI16
I1 I1 MMOVI16
I2 I2 I1 MMOVI16
I3 I3 I2 I1 MMOVI16
I4 I4 I3 I2 I1 MMOVI16
I5 I5 I4 I3 I2 I1 MMOVI16
I6 I6 I5 I4 I3 I2 I1 MMOVI16

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MMOVI32 MRa, #32FHex

Load the 32-Bits of a 32-Bit Floating-Point Register with the Immediate

Operands MRa Floating-point register (MR0 to MR3)

#32FHex A 32-bit immediate value that represents an IEEE 32-bit floating-
point value.

This instruction is an alias for the MMOVIZ and MMOVXI instructions. The second
operand is translated by the assembler such that the instruction becomes:

MMOVIZ MRa, #16FHiHex

MMOVXI MRa, #16FLoHex

Opcode
LSW: IIII IIII IIII IIII (opcode of MMOVIZ MRa, #16FHiHex)
MSW: 0111 1000 0100 00aa
LSW: IIII IIII IIII IIII (opcode of MMOVXI MRa, #16FLoHex)
MSW: 0111 1000 1000 00aa

Description
This instruction only accepts a hex value as the immediate operand. To specify the
immediate value with a floating-point representation, use the MMOVF32 MRa, #32F
instruction.
Load the 32-bits of MRa with the immediate 32-bit hex value represented by #32FHex.
#32FHex is a 32-bit immediate hex value that represents the IEEE 32-bit floating-point
value of a floating-point number. The assembler only accepts a hex immediate value. That
is, 3.0 can only be represented as #0x40400000 (#3.0 results in an error).

MRa = #32FHex;

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline
Depending on #32FHex, this instruction takes one or two cycles. If all of the lower 16-bits
of #32FHex are zeros, then the assembler converts MOVI32 to an MMOVIZ instruction.
If the lower 16-bits of #32FHex are not zeros, then the assembler converts MOVI32 to
MMOVIZ and MMOVXI instructions.

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MMOVI32 MRa, #32FHex (continued)

Load the 32-Bits of a 32-Bit Floating-Point Register with the Immediate

Example
MOVI32 MR1, #0x40400000 ; MR1 = 0x40400000
; Assembler converts this instruction as
; MMOVIZ MR1, #0x4040
MOVI32 MR2, #0x00000000 ; MR2 = 0x00000000
; Assembler converts this instruction as
; MMOVIZ MR2, #0x0
MOVI32 MR3, #0x40004001 ; MR3 = 0x40004001
; Assembler converts this instruction as
; MMOVIZ MR3, #0x4000
; MMOVXI MR3, #0x4001
MOVI32 MR0, #0x00004040 ; MR0 = 0x00004040
; Assembler converts this instruction as
; MMOVIZ MR0, #0x0000
; MMOVXI MR0, #0x4040

See also
MMOVIZ MRa, #16FHi
MMOVXI MRa, #16FLoHex
MMOVF32 MRa, #32F

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MMOVIZ MRa, #16FHi

Load the Upper 16-Bits of a 32-Bit Floating-Point Register

Operands MRa Floating-point register (MR0 to MR3)

#16FHi A 16-bit immediate value that represents the upper 16-bits of an
IEEE 32-bit floating-point value. The low 16-bits of the mantissa
are assumed to be all 0.

Opcode
LSW: IIII IIII IIII IIII
MSW: 0111 1000 0100 00aa

Description
Load the upper 16-bits of MRa with the immediate value #16FHi and clear the low 16-bits
of MRa.
#16FHi is a 16-bit immediate value that represents the upper 16-bits of an IEEE
32-bit floating-point value. The low 16-bits of the mantissa are assumed to be all 0.
The assembler only accepts a decimal or hex immediate value. That is, -1.5 can be
represented as #-1.5 or #0xBFC0.
MMOVIZ is useful for loading a floating-point register with a constant in which the lowest
16-bits of the mantissa are 0. Some examples are 2.0 (0x40000000), 4.0 (0x40800000),
0.5 (0x3F000000), and -1.5 (0xBFC00000). If a constant requires all 32-bits of a floating-
point register to be initialized, then use MMOVIZ along with the MMOVXI instruction.

MRa(31:16) = #16FHi;
MRa(15:0) = 0;

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline
This is a single-cycle instruction.

Example
; Load MR0 and MR1 with -1.5 (0xBFC00000)
MMOVIZ MR0, #0xBFC0 ; MR0 = 0xBFC00000 (1.5)
MMOVIZ MR1, #-1.5 ; MR1 = -1.5 (0xBFC00000)
; Load MR2 with pi = 3.141593 (0x40490FDB)
MMOVIZ MR2, #0x4049 ; MR2 = 0x40490000
MMOVXI MR2, #0x0FDB ; MR2 = 0x40490FDB

See also
MMOVF32 MRa, #32F
MMOVI32 MRa, #32FHex
MMOVXI MRa, #16FLoHex

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MMOVZ16 MRa, mem16

Load MRx with 16-Bit Value

Operands MRa CLA floating-point destination register (MR0 to MR3)

mem16 16-bit source memory location

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0111 0101 10aa addr

Description
Move the 16-bit value referenced by mem16 to the floating-point register indicated by
MRa.

MRa(31:16) = 0;
MRa(15:0) = [mem16];

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified based on the integer results of the operation.

NF = 0;
if (MRa(31:0)== 0) { ZF = 1; }

Pipeline
This is a single-cycle instruction.

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MMOVXI MRa, #16FLoHex

Move Immediate Value to the Lower 16-Bits of a Floating-Point Register

Operands MRa CLA floating-point register (MR0 to MR3)

#16FLoHex A 16-bit immediate hex value that represents the lower 16-bits
of an IEEE 32-bit floating-point value. The upper 16-bits are not
modified.

Opcode
LSW: IIII IIII IIII IIII
MSW: 0111 1000 1000 00aa

Description
Load the lower 16-bits of MRa with the immediate value #16FLoHex. #16FLoHex
represents the lower 16-bits of an IEEE 32-bit floating-point value. The upper 16-bits of
MRa are not modified. MMOVXI can be combined with the MMOVIZ instruction to initialize
all 32-bits of a MRa register.

MRa(15:0) = #16FLoHex;
MRa(31:16) = Unchanged;

Flags Flag TF ZF NF LUF LVF

Modified No No No No No

Pipeline
This is a single-cycle instruction.

Example
; Load MR0 with pi = 3.141593 (0x40490FDB)
MMOVIZ MR0,#0x4049 ; MR0 = 0x40490000
MMOVXI MR0,#0x0FDB ; MR0 = 0x40490FDB

See also
MMOVIZ MRa, #16FHi

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MMPYF32 MRa, MRb, MRc

32-Bit Floating-Point Multiply

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)
MRc CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 00cc bbaa
MSW: 0111 1100 0000 0000

Description
Multiply the contents of two floating-point registers.

MRa = MRb * MRc;

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MMPYF32 generates an underflow condition.
• LVF = 1 if MMPYF32 generates an overflow condition.

Pipeline
This is a single-cycle instruction.

Example
; Calculate Num/Den using a Newton-Raphson algorithum for 1/Den
; Ye = Estimate(1/X)
; Ye = Ye*(2.0 - Ye*X)
; Ye = Ye*(2.0 - Ye*X)
;
_Cla1Task1:
MMOV32 MR1, @_Den ; MR1 = Den
MEINVF32 MR2, MR1 ; MR2 = Ye = Estimate(1/Den)
MMPYF32 MR3, MR2, MR1 ; MR3 = Ye*Den
MSUBF32 MR3, #2.0, MR3 ; MR3 = 2.0 - Ye*Den
MMPYF32 MR2, MR2, MR3 ; MR2 = Ye = Ye*(2.0 - Ye*Den)
MMPYF32 MR3, MR2, MR1 ; MR3 = Ye*Den
|| MMOV32 MR0, @_Num ; MR0 = Num
MSUBF32 MR3, #2.0, MR3 ; MR3 = 2.0 - Ye*Den
MMPYF32 MR2, MR2, MR3 ; MR2 = Ye = Ye*(2.0 - Ye*Den)
|| MMOV32 MR1, @_Den ; Reload Den To Set Sign
MNEGF32 MR0, MR0, EQ ; if(Den == 0.0) Change Sign Of Num
MMPYF32 MR0, MR2, MR0 ; MR0 = Y = Ye*Num
MMOV32 @_Dest, MR0 ; Store result
MSTOP ; end of task

See also
MMPYF32 MRa, #16FHi, MRb
MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf
MMPYF32 MRd, MRe, MRf || MMOV32 MRa, mem32
MMPYF32 MRd, MRe, MRf || MMOV32 mem32, MRa
MMPYF32 MRa, MRb, MRc || MSUBF32 MRd, MRe, MRf
MMACF32 MR3, MR2, MRd, MRe, MRf || MMOV32 MRa, mem32

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MMPYF32 MRa, #16FHi, MRb

32-Bit Floating-Point Multiply

Operands MRa CLA floating-point destination register (MR0 to MR3)

#16FHi A 16-bit immediate value that represents the upper 16-bits of an
IEEE 32-bit floating-point value. The lower 16-bits of the mantissa
are assumed to be all 0.
MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: IIII IIII IIII IIII
MSW: 0111 0111 1000 bbaa

Description
Multiply MRb with the floating-point value represented by the immediate operand. Store
the result of the addition in MRa.
#16FHi is a 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit
floating-point value. The lower 16-bits of the mantissa are assumed to be all 0. #16FHi
is most useful for representing constants where the lowest 16-bits of the mantissa are
0. Some examples are 2.0 (0x40000000), 4.0 (0x40800000), 0.5 (0x3F000000), and -1.5
(0xBFC00000). The assembler accepts either a hex or float as the immediate value. That
is, the value -1.5 can be represented as #-1.5 or #0xBFC0.

MRa = MRb * #16FHi:0;

This instruction can also be written as MMPYF32 MRa, MRb, #16FHi.

Flags
This instruction modifies the following flags in the MSTF register:.
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MMPYF32 generates an underflow condition.
• LVF = 1 if MMPYF32 generates an overflow condition.

Pipeline
This is a single-cycle instruction.

Example 1
; Same as example 2 but #16FHi is represented in float
MMOVIZ MR3, #2.0 ; MR3 = 2.0 (0x40000000)
MMPYF32 MR0, #3.0, MR3 ; MR0 = 3.0 * MR3 = 6.0 (0x40C00000)
MMOV32 @_X, MR0 ; Save the result in variable X

Example 2
; Same as example 1 but #16FHi is represented in Hex
MMOVIZ MR3, #2.0 ; MR3 = 2.0 (0x40000000)
MMPYF32 MR0, #0x4040, MR3 ; MR0 = 0x4040 * MR3 = 6.0 (0x40C00000)
MMOV32 @_X, MR0 ; Save the result in variable X

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MMPYF32 MRa, #16FHi, MRb (continued)

32-Bit Floating-Point Multiply

Example 3
; Given X, M, and B are IQ24 numbers:
; X = IQ24(+2.5) = 0x02800000
; M = IQ24(+1.5) = 0x01800000
; B = IQ24(-0.5) = 0xFF800000
;
; Calculate Y = X * M + B
;
;
_Cla1Task2:
;
; Convert M, X, and B from IQ24 to float
MI32TOF32 MR0, @_M ; MR0 = 0x4BC00000
MI32TOF32 MR1, @_X ; MR1 = 0x4C200000
MI32TOF32 MR2, @_B ; MR2 = 0xCB000000
MMPYF32 MR0, MR0, #0x3380 ; M = 1/(1*2^24) * iqm = 1.5 (0x3FC00000)
MMPYF32 MR1, MR1, #0x3380 ; X = 1/(1*2^24) * iqx = 2.5 (0x40200000)
MMPYF32 MR2, MR2, #0x3380 ; B = 1/(1*2^24) * iqb = -.5 (0xBF000000)
MMPYF32 MR3, MR0, MR1 ; M*X
MADDF32 MR2, MR2, MR3 ; Y=MX+B = 3.25 (0x40500000)
; Convert Y from float32 to IQ24
MMPYF32 MR2, MR2, #0x4B80 ; Y * 1*2^24
MF32TOI32 MR2, MR2 ; IQ24(Y) = 0x03400000
MMOV32 @_Y, MR2 ; store result
MSTOP ; end of task

See also
MMPYF32 MRa, MRb, #16FHi
MMPYF32 MRa, MRb, MRc
MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf

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MMPYF32 MRa, MRb, #16FHi

32-Bit Floating-Point Multiply

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)
#16FHi A 16-bit immediate value that represents the upper 16-bits of an
IEEE 32-bit floating-point value. The lower 16-bits of the mantissa
are assumed to be all 0.

Opcode
LSW: IIII IIII IIII IIII
MSW: 0111 0111 1000 bbaa

Description
Multiply MRb with the floating-point value represented by the immediate operand. Store
the result of the addition in MRa.
#16FHi is a 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit
floating-point value. The low 16-bits of the mantissa are assumed to be all 0. #16FHi is
most useful for representing constants where the lowest 16-bits of the mantissa are 0.
Some examples are 2.0 (0x40000000), 4.0 (0x40800000), 0.5 (0x3F000000), and -1.5
(0xBFC00000). The assembler accepts either a hex or float as the immediate value. That
is, the value -1.5 can be represented as #-1.5 or #0xBFC0.

MRa = MRb * #16FHi:0;

This instruction can also be written as MMPYF32 MRa, #16FHi, MRb.

Flags
This instruction modifies the following flags in the MSTF register:.
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MMPYF32 generates an underflow condition.
• LVF = 1 if MMPYF32 generates an overflow condition.

Pipeline
This is a single-cycle instruction.

Example 1
;Same as example 2 but #16FHi is represented in float
MMOVIZ MR3, #2.0 ; MR3 = 2.0 (0x40000000)
MMPYF32 MR0, MR3, #3.0 ; MR0 = MR3 * 3.0 = 6.0 (0x40C00000)
MMOV32 @_X, MR0 ; Save the result in variable X

Example 2
;Same as example 1 but #16FHi is represented in Hex
MMOVIZ MR3, #2.0 ; MR3 = 2.0 (0x40000000)
MMPYF32 MR0, MR3, #0x4040 ; MR0 = MR3 * 0x4040 = 6.0 (0x40C00000)
MMOV32 @_X, MR0 ; Save the result in variable X

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MMPYF32 MRa, MRb, #16FHi (continued)

32-Bit Floating-Point Multiply

Example 3
; Given X, M, and B are IQ24 numbers:
; X = IQ24(+2.5) = 0x02800000
; M = IQ24(+1.5) = 0x01800000
; B = IQ24(-0.5) = 0xFF800000
;
; Calculate Y = X * M + B
;
_Cla1Task2:
;
; Convert M, X, and B from IQ24 to float
MI32TOF32 MR0, @_M ; MR0 = 0x4BC00000
MI32TOF32 MR1, @_X ; MR1 = 0x4C200000
MI32TOF32 MR2, @_B ; MR2 = 0xCB000000
MMPYF32 MR0, #0x3380, MR0 ; M = 1/(1*2^24) * iqm = 1.5 (0x3FC00000)
MMPYF32 MR1, #0x3380, MR1 ; X = 1/(1*2^24) * iqx = 2.5 (0x40200000)
MMPYF32 MR2, #0x3380, MR2 ; B = 1/(1*2^24) * iqb = -.5 (0xBF000000)
MMPYF32 MR3, MR0, MR1 ; M*X
MADDF32 MR2, MR2, MR3 ; Y=MX+B = 3.25 (0x40500000)
; Convert Y from float32 to IQ24
MMPYF32 MR2, #0x4B80, MR2 ; Y * 1*2^24
MF32TOI32 MR2, MR2 ; IQ24(Y) = 0x03400000
MMOV32 @_Y, MR2 ; store result
MSTOP ; end of task

See also
MMPYF32 MRa, #16FHi, MRb
MMPYF32 MRa, MRb, MRc

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MMPYF32 MRa, MRb, MRc||MADDF32 MRd, MRe, MRf

32-Bit Floating-Point Multiply with Parallel Add

Operands MRa CLA floating-point destination register for MMPYF32 (MR0 to MR3)
MRa cannot be the same register as MRd
MRb CLA floating-point source register for MMPYF32 (MR0 to MR3)
MRc CLA floating-point source register for MMPYF32 (MR0 to MR3)
MRd CLA floating-point destination register for MADDF32 (MR0 to MR3)
MRd cannot be the same register as MRa
MRe CLA floating-point source register for MADDF32 (MR0 to MR3)
MRf CLA floating-point source register for MADDF32 (MR0 to MR3)

Opcode
LSW: 0000 ffee ddcc bbaa
MSW: 0111 1010 0000 0000

Description
Multiply the contents of two floating-point registers with parallel addition of two registers.

MRa = MRb * MRc;

MRd = MRe + MRf;

Restrictions
The destination register for the MMPYF32 and the MADDF32 must be unique. That is,
MRa cannot be the same register as MRd.

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MMPYF32 or MADDF32 generates an underflow condition.
• LVF = 1 if MMPYF32 or MADDF32 generates an overflow condition.

Pipeline
Both MMPYF32 and MADDF32 complete in a single cycle.

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MMPYF32 MRa, MRb, MRc||MADDF32 MRd, MRe, MRf (continued)

32-Bit Floating-Point Multiply with Parallel Add

Example
; Perform 5 multiply and accumulate operations:
;
; X and Y are 32-bit floating-point arrays
;
; 1st multiply: A = X0 * Y0
; 2nd multiply: B = X1 * Y1
; 3rd multiply: C = X2 * Y2
; 4th multiply: D = X3 * Y3
; 5th multiply: E = X3 * Y3
;
; Result = A + B + C + D + E
;
_Cla1Task1:
MMOVI16 MAR0, #_X ; MAR0 points to X array
MMOVI16 MAR1, #_Y ; MAR1 points to Y array
MNOP ; Delay for MAR0, MAR1 load
MNOP ; Delay for MAR0, MAR1 load
; <-- MAR0 valid
MMOV32 MR0, *MAR0[2]++ ; MR0 = X0, MAR0 += 2
; <-- MAR1 valid
MMOV32 MR1, *MAR1[2]++ ; MR1 = Y0, MAR1 += 2
MMPYF32 MR2, MR0, MR1 ; MR2 = A = X0 * Y0
|| MMOV32 MR0, *MAR0[2]++ ; In parallel MR0 = X1, MAR0 += 2
MMOV32 MR1, *MAR1[2]++ ; MR1 = Y1, MAR1 += 2
MMPYF32 MR3, MR0, MR1 ; MR3 = B = X1 * Y1
|| MMOV32 MR0, *MAR0[2]++ ; In parallel MR0 = X2, MAR0 += 2
MMOV32 MR1, *MAR1[2]++ ; MR1 = Y2, MAR2 += 2
MMACF32 MR3, MR2, MR2, MR0, MR1 ; MR3 = A + B, MR2 = C = X2 * Y2
|| MMOV32 MR0, *MAR0[2]++ ; In parallel MR0 = X3
MMOV32 MR1, *MAR1[2]++ ; MR1 = Y3
MMACF32 MR3, MR2, MR2, MR0, MR1 ; MR3 = (A + B) + C, MR2 = D = X3 * Y3
|| MMOV32 MR0, *MAR0 ; In parallel MR0 = X4
MMOV32 MR1, *MAR1 ; MR1 = Y4
MMPYF32 MR2, MR0, MR1 ; MR2 = E = X4 * Y4
|| MADDF32 MR3, MR3, MR2 ; in parallel MR3 = (A + B + C) + D

MADDF32 MR3, MR3, MR2 ; MR3 = (A + B + C + D) + E

MMOV32 @_Result, MR3 ; Store the result
MSTOP ; end of task

See also
MMACF32 MR3, MR2, MRd, MRe, MRf || MMOV32 MRa, mem32

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MMPYF32 MRd, MRe, MRf ||MMOV32 MRa, mem32

32-Bit Floating-Point Multiply with Parallel Move

Operands MRd CLA floating-point destination register for MMPYF32 (MR0 to MR3)
MRd cannot be the same register as MRa
MRe CLA floating-point source register for MMPYF32 (MR0 to MR3)
MRf CLA floating-point source register for MMPYF32 (MR0 to MR3)
MRa CLA floating-point destination register for MMOV32 (MR0 to MR3)
MRa cannot be the same register as MRd
mem32 32-bit memory location accessed using one of the available
addressing modes. This is the source of MMOV32.

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0000 ffee ddaa addr

Description
Multiply the contents of two floating-point registers and load another.

MRd = MRe * MRf;

MRa = [mem32];

Restrictions
The destination register for the MMPYF32 and the MMOV32 must be unique. That is,
MRa cannot be the same register as MRd.

Flags
This instruction modifies the following flags in the MSTF register:.
Flag TF ZF NF LUF LVF
Modified No Yes Yes Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MMPYF32 generates an underflow condition.
• LVF = 1 if MMPYF32 generates an overflow condition.
The MMOV32 instruction sets the NF and ZF flags as follows:

NF = MRa(31);
ZF = 0;
if(MRa(30:23) == 0) { ZF = 1; NF = 0; }

Pipeline
Both MMPYF32 and MMOV32 complete in a single cycle.

Example 1
; Given M1, X1, and B1 are 32-bit floating point
; Calculate Y1 = M1*X1+B1
;
_Cla1Task1:
MMOV32 MR0, @M1 ; Load MR0 with M1
MMOV32 MR1, @X1 ; Load MR1 with X1
MMPYF32 MR1, MR1, MR0 ; Multiply M1*X1
|| MMOV32 MR0, @B1 ; and in parallel load MR0 with B1
MADDF32 MR1, MR1, MR0 ; Add M*X1 to B1 and store in MR1
MMOV32 @Y1, MR1 ; Store the result
MSTOP ; end of task

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MMPYF32 MRd, MRe, MRf ||MMOV32 MRa, mem32 (continued)

32-Bit Floating-Point Multiply with Parallel Move

Example 2
; Given A, B, and C are 32-bit floating-point numbers
; Calculate Y2 = (A * B)
; Y3 = (A * B) * C
;
_Cla1Task2:
MMOV32 MR0, @A ; Load MR0 with A
MMOV32 MR1, @B ; Load MR1 with B
MMPYF32 MR1, MR1, MR0 ; Multiply A*B
|| MMOV32 MR0, @C ; and in parallel load MR0 with C
MMPYF32 MR1, MR1, MR0 ; Multiply (A*B) by C
|| MMOV32 @Y2, MR1 ; and in parallel store A*B
MMOV32 @Y3, MR1 ; Store the result
MSTOP ; end of task

See also
MMPYF32 MRd, MRe, MRf || MMOV32 mem32, MRa
MMACF32 MR3, MR2, MRd, MRe, MRf || MMOV32 MRa, mem32

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MMPYF32 MRd, MRe, MRf ||MMOV32 mem32, MRa

32-Bit Floating-Point Multiply with Parallel Move

Operands MRd CLA floating-point destination register for MMPYF32 (MR0 to MR3)
MRe CLA floating-point source register for MMPYF32 (MR0 to MR3)
MRf CLA floating-point source register for MMPYF32 (MR0 to MR3)
mem32 32-bit memory location accessed using one of the available
addressing modes. This is the destination of MMOV32.
MRa CLA floating-point source register for MMOV32 (MR0 to MR3)

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0100 ffee ddaa addr

Description
Multiply the contents of two floating-point registers and move from memory to register.

MRd = MRe * MRf;

[mem32] = MRa;

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MMPYF32 generates an underflow condition.
• LVF = 1 if MMPYF32 generates an overflow condition.

Pipeline
MMPYF32 and MMOV32 both complete in a single cycle.

Example
; Given A, B, and C are 32-bit floating-point numbers
; Calculate Y2 = (A * B)
; Y3 = (A * B) * C
;
_Cla1Task2:
MMOV32 MR0, @A ; Load MR0 with A
MMOV32 MR1, @B ; Load MR1 with B
MMPYF32 MR1, MR1, MR0 ; Multiply A*B
|| MMOV32 MR0, @C ; and in parallel load MR0 with C
MMPYF32 MR1, MR1, MR0 ; Multiply (A*B) by C
|| MMOV32 @Y2, MR1 ; and in parallel store A*B
MMOV32 @Y3, MR1 ; Store the result
MSTOP ; end of task

See also
MMPYF32 MRd, MRe, MRf || MMOV32 MRa, mem32
MMACF32 MR3, MR2, MRd, MRe, MRf || MMOV32 MRa, mem32

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MMPYF32 MRa, MRb, MRc ||MSUBF32 MRd, MRe, MRf

32-Bit Floating-Point Multiply with Parallel Subtract

Operands MRa CLA floating-point destination register for MMPYF32 (MR0 to MR3)
MRa cannot be the same register as MRd
MRb CLA floating-point source register for MMPYF32 (MR0 to MR3)
MRc CLA floating-point source register for MMPYF32 (MR0 to MR3)
MRd CLA floating-point destination register for MSUBF32 (MR0 to MR3)
MRd cannot be the same register as MRa
MRe CLA floating-point source register for MSUBF32 (MR0 to MR3)
MRf CLA floating-point source register for MSUBF32 (MR0 to MR3)

Opcode
LSW: 0000 ffee ddcc bbaa
MSW: 0111 1010 0100 0000

Description
Multiply the contents of two floating-point registers with parallel subtraction of two
registers.

MRa = MRb * MRc;

MRd = MRe - MRf;

Restrictions
The destination register for the MMPYF32 and the MSUBF32 must be unique. That is,
MRa cannot be the same register as MRd.

Flags
This instruction modifies the following flags in the MSTF register:.
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MMPYF32 or MSUBF32 generates an underflow condition.
• LVF = 1 if MMPYF32 or MSUBF32 generates an overflow condition.
Pipeline
MMPYF32 and MSUBF32 both complete in a single cycle.

Example
; Given A, B, and C are 32-bit floating-point numbers
; Calculate Y2 = (A * B)
; Y3 = (A - B)
;
_Cla1Task2:
MMOV32 MR0, @A ; Load MR0 with A
MMOV32 MR1, @B ; Load MR1 with B
MMPYF32 MR2, MR0, MR1 ; Multiply (A*B)
|| MSUBF32 MR3, MR0, MR1 ; and in parallel Sub (A-B)
MMOV32 @Y2, MR2 ; Store A*B
MMOV32 @Y3, MR3 ; Store A-B
MSTOP ; end of task

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MMPYF32 MRa, MRb, MRc ||MSUBF32 MRd, MRe, MRf (continued)

32-Bit Floating-Point Multiply with Parallel Subtract

See also
MSUBF32 MRa, MRb, MRc
MSUBF32 MRd, MRe, MRf || MMOV32 MRa, mem32
MSUBF32 MRd, MRe, MRf || MMOV32 mem32, MRa

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MNEGF32 MRa, MRb{, CNDF}

Conditional Negation

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)
CNDF Condition tested

Opcode
LSW: 0000 0000 cndf bbaa
MSW: 0111 1010 1000 0000

Description
if (CNDF == true) {MRa = - MRb; }
else {MRa = MRb; }

CNDF is one of the following conditions:

Encode(1) CNDF Description MSTF Flags Tested
0000 NEQ Not equal to zero ZF == 0
0001 EQ Equal to zero ZF == 1
0010 GT Greater than zero ZF == 0 AND NF == 0
0011 GEQ Greater than or equal NF == 0
to zero
0100 LT Less than zero NF == 1
0101 LEQ Less than or equal to ZF == 1 OR NF == 1
zero
1010 TF Test flag set TF == 1
1011 NTF Test flag not set TF == 0
1100 LU Latched underflow LUF == 1
1101 LV Latched overflow LVF == 1
1110 UNC Unconditional None
1111 UNCF(2) Unconditional with flag None
modification

(1) Values not shown are reserved.

(2) This is the default operation, if no CNDF field is specified. This condition
allows the ZF, and NF flags to be modified when a conditional operation is
executed. All other conditions do not modify these flags.

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

Pipeline
This is a single-cycle instruction.

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MNEGF32 MRa, MRb{, CNDF} (continued)

Conditional Negation

Example 1
; Show the basic operation of MNEGF32
;
MMOVIZ MR0, #5.0 ; MR0 = 5.0 (0x40A00000)
MMOVIZ MR1, #4.0 ; MR1 = 4.0 (0x40800000)
MMOVIZ MR2, #-1.5 ; MR2 = -1.5 (0xBFC00000)
MMPYF32 MR3, MR1, MR2 ; MR3 = -6.0
MMPYF32 MR0, MR0, MR1 ; MR0 = 20.0
MMOVIZ MR1, #0.0
MCMPF32 MR3, MR1 ; NF = 1
MNEGF32 MR3, MR3, LT ; if NF = 1, MR3 = 6.0
MCMPF32 MR0, MR1 ; NF = 0
MNEGF32 MR0, MR0, GEQ ; if NF = 0, MR0 = -20.0

Example 2
; Calculate Num/Den using a Newton-Raphson algorithum for 1/Den
; Ye = Estimate(1/X)
; Ye = Ye*(2.0 - Ye*X)
; Ye = Ye*(2.0 - Ye*X)
;
_Cla1Task1:
MMOV32 MR1, @_Den ; MR1 = Den
MEINVF32 MR2, MR1 ; MR2 = Ye = Estimate(1/Den)
MMPYF32 MR3, MR2, MR1 ; MR3 = Ye*Den
MSUBF32 MR3, #2.0, MR3 ; MR3 = 2.0 - Ye*Den
MMPYF32 MR2, MR2, MR3 ; MR2 = Ye = Ye*(2.0 - Ye*Den)
MMPYF32 MR3, MR2, MR1 ; MR3 = Ye*Den
|| MMOV32 MR0, @_Num ; MR0 = Num
MSUBF32 MR3, #2.0, MR3 ; MR3 = 2.0 - Ye*Den
MMPYF32 MR2, MR2, MR3 ; MR2 = Ye = Ye*(2.0 - Ye*Den)
|| MMOV32 MR1, @_Den ; Reload Den To Set Sign
MNEGF32 MR0, MR0, EQ ; if(Den == 0.0) Change Sign Of Num
MMPYF32 MR0, MR2, MR0 ; MR0 = Y = Ye*Num
MMOV32 @_Dest, MR0 ; Store result
MSTOP ; end of task

See also
MABSF32 MRa, MRb

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MNOP

No Operation

Operands none This instruction does not have any operands

Opcode
LSW: 0000 0000 0000 0000
MSW: 0111 1111 1010 0000

Description
Do nothing. This instruction is used to fill required pipeline delay slots when other
instructions are not available to fill the slots.

Flags
This instruction does not modify flags in the MSTF register.
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline
This is a single-cycle instruction.

Example
; X is an array of 32-bit floating-point values
; Find the maximum value in an array X
; and store the value in Result
;
_Cla1Task1:
MMOVI16 MAR1,#_X ; Start address
MUI16TOF32 MR0, @_len ; Length of the array
MNOP ; delay for MAR1 load
MNOP ; delay for MAR1 load
MMOV32 MR1, *MAR1[2]++ ; MR1 = X0
LOOP
MMOV32 MR2, *MAR1[2]++ ; MR2 = next element
MMAXF32 MR1, MR2 ; MR1 = MAX(MR1, MR2)
MADDF32 MR0, MR0, #-1.0 ; Decrememt the counter
MCMPF32 MR0 #0.0 ; Set/clear flags for MBCNDD
MNOP ; Too late to affect MBCNDD
MNOP ; Too late to affect MBCNDD
MNOP ; Too late to affect MBCNDD
MBCNDD LOOP, NEQ ; Branch if not equal to zero
MMOV32 @_Result, MR1 ; Always executed
MNOP ; Pad to seperate MBCNDD and MSTOP
MNOP ; Pad to seperate MBCNDD and MSTOP
MSTOP ; End of task

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MOR32 MRa, MRb, MRc

Bitwise OR

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)
MRc CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 00cc bbaa
MSW: 0111 1100 1000 0000

Description
Bitwise OR of MRb with MRc.

MARa(31:0) = MARb(31:0) OR MRc(31:0);

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified based on the integer results of the operation.

NF = MRa(31);
ZF = 0;
if(MRa(31:0) == 0) { ZF = 1; }

Pipeline
This is a single-cycle instruction.

Example
MMOVIZ MR0,
#0x5555 ; MR0 = 0x5555AAAA
MMOVXI MR0,
#0xAAAA
MMOVIZ MR1,
#0x5432 ; MR1 = 0x5432FEDC
MMOVXI MR1,
#0xFEDC
; 0101 OR 0101 = 0101 (5)
; 0101 OR 0100 = 0101 (5)
; 0101 OR 0011 = 0111 (7)
; 0101 OR 0010 = 0111 (7)
; 1010 OR 1111 = 1111 (F)
; 1010 OR 1110 = 1110 (E)
; 1010 OR 1101 = 1111 (F)
; 1010 OR 1100 = 1110 (E)
MOR32 MR2, MR1, MR0 ; MR3 = 0x5555FEFE

See also
MAND32 MRa, MRb, MRc
MXOR32 MRa, MRb, MRc

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MRCNDD {CNDF}

Return Conditional Delayed

Operands CNDF Optional condition

Opcode
LSW: 0000 0000 0000 0000
MSW: 0111 1001 1010 cndf

Description
If the specified condition is true, then the RPC field of MSTF is loaded into MPC and
fetching continues from that location. Otherwise, program fetches continue without the
return.
Refer to the Pipeline section for important information regarding this instruction.

if (CNDF == TRUE) MPC = RPC;

CNDF is one of the following conditions:

Encode(1) CNDF Description MSTF Flags Tested
0000 NEQ Not equal to zero ZF == 0
0001 EQ Equal to zero ZF == 1
0010 GT Greater than zero ZF == 0 AND NF == 0
0011 GEQ Greater than or equal NF == 0
to zero
0100 LT Less than zero NF == 1
0101 LEQ Less than or equal to ZF == 1 OR NF == 1
zero
1010 TF Test flag set TF == 1
1011 NTF Test flag not set TF == 0
1100 LU Latched underflow LUF == 1
1101 LV Latched overflow LVF == 1
1110 UNC Unconditional None
1111 UNCF(2) Unconditional with flag None
modification

(1) Values not shown are reserved.

(2) This is the default operation, if no CNDF field is specified. This condition
allows the ZF and NF flags to be modified when a conditional operation is
executed. All other conditions do not modify these flags.

Flags
This instruction does not modify flags in the MSTF register.
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline
The MRCNDD instruction is a single-cycle instruction. As shown in Table 6-18, 6
instruction slots are executed for each return; 3 slots before the return instruction (d5-d7)
and 3 slots after the return instruction (d8-d10). The total number of cycles for a return
taken or not taken depends on the usage of these slots. That is, the number of cycles
depends on how many slots are filled with a MNOP as well as which slots are filled.

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MRCNDD {CNDF} (continued)

Return Conditional Delayed

The effective number of cycles for a return can, therefore, range from 1 to 7 cycles. The
number of cycles for a return taken cannot be the same as for a return not taken.
Referring to the following code fragment and the pipeline diagrams in Table 6-18 and
Table 6-19, the instructions before and after MRCNDD have the following properties:

;
;
<Instruction 1> ; I1 Last instruction that can affect flags for
; the MCCNDD operation
<Instruction 2> ; I2 Cannot be stop, branch, call or return
<Instruction 3> ; I3 Cannot be stop, branch, call or return
<Instruction 4> ; I4 Cannot be stop, branch, call or return
MCCNDD _func, NEQ ; Call to func if not eqal to zero
; Three instructions after MCCNDD are always
; executed whether the call is taken or not
<Instruction 5> ; I5 Cannot be stop, branch, call or return
<Instruction 6> ; I6 Cannot be stop, branch, call or return
<Instruction 7> ; I7 Cannot be stop, branch, call or return
<Instruction 8> ; I8 The address of this instruction is saved
; in the RPC field of the MSTF register.
; Upon return this value is loaded into MPC
; and fetching continues from this point.
<Instruction 9> ; I9
<Instruction 10> ; I10
....
....
_func:
<Destination 1> ; d1 Can be any instruction
<Destination 2> ; d2
<Destination 3> ; d3
<Destination 4> ; d4 Last instruction that can affect flags for
; the MRCNDD operation
<Destination 5> ; d5 Cannot be stop, branch, call or return
<Destination 6> ; d6 Cannot be stop, branch, call or return
<Destination 7> ; d7 Cannot be stop, branch, call or return
MRCNDD NEQ ; Return to <Instruction 8> if not equal to zero
; Three instructions after MRCNDD are always
; executed whether the return is taken or not
<Destination 8> ; d8 Cannot be stop, branch, call or return
<Destination 9> ; d9 Cannot be stop, branch, call or return
<Destination 10> ; d10 Cannot be stop, branch, call or return
<Destination 11> ; d11
<Destination 12> ; d12
....
....
MSTOP
....

• d4
– d4 is the last instruction that can effect the CNDF flags for the MRCNDD instruction.
The CNDF flags are tested in the D2 phase of the pipeline. That is, a decision is
made whether to return or not when MRCNDD is in the D2 phase.
– There are no restrictions on the type of instruction for d4.
• d5, d6, and d7
– The three instructions proceeding MRCNDD can change MSTF flags but have no
effect on whether the MRCNDD instruction makes the return or not. This is because
the flag modification occurs after the D2 phase of the MRCNDD instruction.
– These instructions must not be the following: MSTOP, MDEBUGSTOP, MBCNDD,
MCCNDD, or MRCNDD.
• d8, d9, and d10
– The three instructions following MRCNDD are always executed irrespective of
whether the return is taken or not.

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MRCNDD {CNDF} (continued)

Return Conditional Delayed

– These instructions must not be the following: MSTOP, MDEBUGSTOP, MBCNDD,

MCCNDD, or MRCNDD.
Table 6-18. Pipeline Activity for MRCNDD, Return Not Taken
Instruction F1 F2 D1 D2 R1 R2 E W
d4 d4 d3 d2 d1 I7 I6 I5
d5 d5 d4 d3 d2 d1 I7 I6
d6 d6 d5 d4 d3 d2 d1 i7
d7 d7 d6 d5 d4 d3 d2 d1
MRCNDD MRCNDD d7 d6 d5 d4 d3 d2
d8 d8 MRCNDD d7 d6 d5 d4 d3
d9 d9 d8 MRCNDD d7 d6 d5 d4
d10 d10 d9 d8 MRCNDD d7 d6 d5
d11 d11 d10 d9 d8 - d7 d6
d12 d12 d11 d10 d9 d8 - d7
etc.... .... d12 d11 d10 d9 d8 -
.... .... .... d12 d11 d10 d9 d8
.... .... .... .... d12 d11 d10 d9
d12 d11 d10
d12 d11
d12

Table 6-19. Pipeline Activity for MRCNDD, Return Taken

Instruction F1 F2 D1 D2 R1 R2 E W
d4 d4 d3 d2 d1 I7 I6 I5
d5 d5 d4 d3 d2 d1 I7 I6
d6 d6 d5 d4 d3 d2 d1 i7
d7 d7 d6 d5 d4 d3 d2 d1
MRCNDD MRCNDD d7 d6 d5 d4 d3 d2
d8 d8 MRCNDD d7 d6 d5 d4 d3
d9 d9 d8 MRCNDD d7 d6 d5 d4
d10 d10 d9 d8 MRCNDD d7 d6 d5
I8 I8 d10 d9 d8 - d7 d6
I9 I9 I8 d10 d9 d8 - d7
I10 I10 I9 I8 d10 d9 d8 -
etc.... .... I10 I9 I8 d10 d9 d8
.... .... I10 I9 I8 d10 d9
.... .... I10 I9 I8 d10
I10 I9 I8
I10 I9
I10

See also
MBCNDD #16BitDest, CNDF
MCCNDD 16BitDest, CNDF
MMOV32 mem32, MSTF
MMOV32 MSTF, mem32

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MSETFLG FLAG, VALUE

Set or Clear Selected Floating-Point Status Flags

Operands FLAG 8-bit mask indicating which floating-point status flags to change.
VALUE 8-bit mask indicating the flag value: 0 or 1.

Opcode
LSW: FFFF FFFF VVVV VVVV
MSW: 0111 1001 1100 0000

Description
The MSETFLG instruction is used to set or clear selected floating-point status flags in the
MSTF register. The FLAG field is an 11-bit value that indicates which flags are changed.
That is, if a FLAG bit is set to 1, that flag is changed; all other flags are not modified. The
bit mapping of the FLAG field is:
9 8 7 6 5 4 3 2 1 0
RNDF Reserved TF Reserved ZF NF LUF LVF
32

The VALUE field indicates the value the flag can be set to: 0 or 1.

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified Yes Yes Yes Yes Yes

Any flag can be modified by this instruction. The MEALLOW and RPC fields cannot be
modified with this instruction.

Pipeline
This is a single-cycle instruction.

Example
To make it easier and legible, the assembler accepts a FLAG=VALUE syntax for the
MSTFLG operation as:

MSETFLG RNDF32=0, TF=0, NF=1; FLAG = 11000100; VALUE = 00XXX1XX;

See also
MMOV32 mem32, MSTF
MMOV32 MSTF, mem32

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MSTOP

Stop Task

Operands none This instruction does not have any operands

Opcode
LSW: 0000 0000 0000 0000
MSW: 0111 1111 1000 0000

Description
The MSTOP instruction must be placed to indicate the end of each task. In addition,
placing MSTOP in unused memory locations within the CLA program RAM can be useful
for debugging and preventing run away CLA code. When MSTOP enters the D2 phase of
the pipeline, the MIRUN flag for the task is cleared and the associated interrupt is flagged
in the PIE vector table.
There are three special cases that can occur when single-stepping a task such that the
MPC reaches the MSTOP instruction.
1. If you are single-stepping or halted in "task A" and "task B" comes in before the MPC
reaches the MSTOP, then "task B" starts if you continue to step through the MSTOP
instruction. Basically, if "task B" is pending before the MPC reaches MSTOP in "task
A" then there is no issue in "task B" starting and no special action is required.
2. In this case, you have single-stepped or halted in "task A" and the MPC has reached
the MSTOP with no tasks pending. If "task B" comes in at this point, "task B" is
flagged in the MIFR register but "task B" can or cannot start if you continue to
single-step through the MSTOP instruction of "task A". It depends on exactly when the
new task comes in. To reliably start "task B", perform a soft reset and reconfigure the
MIER bits. Once this is done, you can start single-stepping "task B".
3. Case 2 can be handled slightly differently if there is control over when "task B" comes
in (for example using the IACK instruction to start the task). In this case you have
single-stepped or halted in "task A" and the MPC has reached the MSTOP with no
tasks pending. Before forcing "task B", run free to force the CLA out of the debug
state. Once this is done you can force "task B" and continue debugging.

Restrictions
The MSTOP instruction cannot be placed 3 instructions before or after a MBCNDD,
MCCNDD, or MRCNDD instruction.

Flags
This instruction does not modify flags in the MSTF register.
Flag TF ZF NF LUF LVF
Modified No No No No No

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MSTOP (continued)

Stop Task

Pipeline
This is a single-cycle instruction. Table 6-20 shows the pipeline behavior of the MSTOP
instruction. The MSTOP instruction cannot be placed with 3 instructions of a MBCNDD,
MCCNDD, or MRCNDD instruction.
Table 6-20. Pipeline Activity for MSTOP
Instruction F1 F2 D1 D2 R1 R2 E W
I1 I1
I2 I2 I1
I3 I3 I2 I1
MSTOP MSTOP I3 I2 I1
I4 I4 MSTOP I3 I2 I1
I5 I5 I4 MSTOP I3 I2 I1
I6 I6 I5 I4 MSTOP I3 I2 I1
New Task Arbitrated and
- - - - - I3 I2
Prioritized
New Task Arbitrated and
- - - - - - I3
Prioritized
I1 I1 - - - - - -
I2 I2 I1 - - - - -
I3 I3 I2 I1 - - - -
I4 I4 I3 I2 I1 - - -
I5 I5 I4 I3 I2 I1 - -
I6 I6 I5 I4 I3 I2 I1 -
I7 I7 I6 I5 I4 I3 I2 I1
....

Example
; Given A = (int32)1
; B = (int32)2
; C = (int32)-7
;
; Calculate Y2 = A - B - C
_Cla1Task3:
MMOV32 MR0, @_A ; MR0 = 1 (0x00000001)
MMOV32 MR1, @_B ; MR1 = 2 (0x00000002)
MMOV32 MR2, @_C ; MR2 = -7 (0xFFFFFFF9)
MSUB32 MR3, MR0, MR1 ; A + B
MSUB32 MR3, MR3, MR2 ; A + B + C = 6 (0x0000006)
MMOV32 @_y2, MR3 ; Store y2
MSTOP ; End of task

See also
MDEBUGSTOP

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MSUB32 MRa, MRb, MRc

32-Bit Integer Subtraction

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point destination register (MR0 to MR3)
MRc CLA floating-point destination register (MR0 to MR3)

Opcode
LSW: 0000 0000 00cc bbaa
MSW: 0111 1100 1110 0000

Description
32-bit integer addition of MRb and MRc.

MARa(31:0) = MARb(31:0) - MRc(31:0);

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified as follows:

NF = MRa(31);
ZF = 0;
if(MRa(31:0) == 0) { ZF = 1; }

Pipeline
This is a single-cycle instruction.

Example
; Given A = (int32)1
; B = (int32)2
; C = (int32)-7
;
;
Calculate Y2 = A - B - C
;
_Cla1Task3:
MMOV32 MR0, @_A ; MR0 = 1 (0x00000001)
MMOV32 MR1, @_B ; MR1 = 2 (0x00000002)
MMOV32 MR2, @_C ; MR2 = -7 (0xFFFFFFF9)
MSUB32 MR3, MR0, MR1 ; A + B
MSUB32 MR3, MR3, MR2 ; A + B + C = 6 (0x0000006)
MMOV32 @_y2, MR3 ; Store y2
MSTOP ; End of task

See also
MADD32 MRa, MRb, MRc
MAND32 MRa, MRb, MRc
MASR32 MRa, #SHIFT
MLSL32 MRa, #SHIFT
MLSR32 MRa, #SHIFT
MOR32 MRa, MRb, MRc
MXOR32 MRa, MRb, MRc

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MSUBF32 MRa, MRb, MRc

32-Bit Floating-Point Subtraction

Operands MRa CLA floating-point destination register (MR0 to R1)

MRb CLA floating-point source register (MR0 to R1)
MRc CLA floating-point source register (MR0 to R1)

Opcode
LSW: 0000 0000 00cc bbaa
MSW: 0111 1100 0100 0000

Description
Subtract the contents of two floating-point registers

MRa = MRb - MRc;

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MSUBF32 generates an underflow condition.
• LVF = 1 if MSUBF32 generates an overflow condition.

Pipeline
This is a single-cycle instruction.

Example
; Given A, B, and C are 32-bit floating-point numbers
; Calculate Y2 = A + B - C
;
_Cla1Task5:
MMOV32 MR0, @_A ; Load MR0 with A
MMOV32 MR1, @_B ; Load MR1 with B
MADDF32 MR0, MR1, MR0 ; Add A + B
|| MMOV32 MR1, @_C ; and in parallel load C
MSUBF32 MR0, MR0, MR1 ; Subtract C from (A + B)
MMOV32 @Y, MR0 ; (A+B) - C
MSTOP ; end of task

See also
MSUBF32 MRa, #16FHi, MRb
MSUBF32 MRd, MRe, MRf || MMOV32 MRa, mem32
MSUBF32 MRd, MRe, MRf || MMOV32 mem32, MRa
MMPYF32 MRa, MRb, MRc || MSUBF32 MRd, MRe, MRf

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MSUBF32 MRa, #16FHi, MRb

32-Bit Floating-Point Subtraction

Operands MRa CLA floating-point destination register (MR0 to R1)

#16FHi A 16-bit immediate value that represents the upper 16-bits of an
IEEE 32-bit floating-point value. The lower 16-bits of the mantissa
are assumed to be all 0.
MRb CLA floating-point source register (MR0 to R1)

Opcode
LSW: IIII IIII IIII IIII
MSW: 0111 1000 0000 baaa

Description
Subtract MRb from the floating-point value represented by the immediate operand. Store
the result of the addition in MRa.
#16FHi is a 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit
floating-point value. The lower 16-bits of the mantissa are assumed to be all 0. #16FHi
is most useful for representing constants where the lowest 16-bits of the mantissa are
0. Some examples are 2.0 (0x40000000), 4.0 (0x40800000), 0.5 (0x3F000000), and -1.5
(0xBFC00000). The assembler accepts either a hex or float as the immediate value. That
is, the value -1.5 can be represented as #-1.5 or #0xBFC0.

MRa = #16FHi:0 - MRb;

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MSUBF32 generates an underflow condition.
• LVF = 1 if MSUBF32 generates an overflow condition.

Pipeline
This is a single-cycle instruction.

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MSUBF32 MRa, #16FHi, MRb (continued)

32-Bit Floating-Point Subtraction

Example
; Y = sqrt(X)
; Ye = Estimate(1/sqrt(X));
; Ye = Ye*(1.5 - Ye*Ye*X*0.5)
; Ye = Ye*(1.5 - Ye*Ye*X*0.5)
; Y = X*Ye
;
_Cla1Task3:
MMOV32 MR0, @_x ; MR0 = X
MEISQRTF32 MR1, MR0 ; MR1 = Ye = Estimate(1/sqrt(X))
MMOV32 MR1, @_x, EQ ; if(X == 0.0) Ye = 0.0
MMPYF32 MR3, MR0, #0.5 ; MR3 = X*0.5
MMPYF32 MR2, MR1, MR3 ; MR2 = Ye*X*0.5
MMPYF32 MR2, MR1, MR2 ; MR2 = Ye*Ye*X*0.5
MSUBF32 MR2, #1.5, MR2 ; MR2 = 1.5 - Ye*Ye*X*0.5
MMPYF32 MR1, MR1, MR2 ; MR1 = Ye = Ye*(1.5 - Ye*Ye*X*0.5)
MMPYF32 MR2, MR1, MR3 ; MR2 = Ye*X*0.5
MMPYF32 MR2, MR1, MR2 ; MR2 = Ye*Ye*X*0.5
MSUBF32 MR2, #1.5, MR2 ; MR2 = 1.5 - Ye*Ye*X*0.5
MMPYF32 MR1, MR1, MR2 ; MR1 = Ye = Ye*(1.5 - Ye*Ye*X*0.5)
MMPYF32 MR0, MR1, MR0 ; MR0 = Y = Ye*X
MMOV32 @_y, MR0 ; Store Y = sqrt(X)
MSTOP ; end of task

See also
MSUBF32 MRa, MRb, MRc
MSUBF32 MRd, MRe, MRf || MMOV32 MRa, mem32
MSUBF32 MRd, MRe, MRf || MMOV32 mem32, MRa
MMPYF32 MRa, MRb, MRc || MSUBF32 MRd, MRe, MRf

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MSUBF32 MRd, MRe, MRf ||MMOV32 MRa, mem32

32-Bit Floating-Point Subtraction with Parallel Move

Operands MRd CLA floating-point destination register (MR0 to MR3) for the
MSUBF32 operation
MRd cannot be the same register as MRa
MRe CLA floating-point source register (MR0 to MR3) for the MSUBF32
operation
MRf CLA floating-point source register (MR0 to MR3) for the MSUBF32
operation
MRa CLA floating-point destination register (MR0 to MR3) for the
MMOV32 operation
MRa cannot be the same register as MRd
mem32 32-bit memory location accessed using one of the available
addressing modes. Source for the MMOV32 operation.

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0010 ffee ddaa addr

Description
Subtract the contents of two floating-point registers and move from memory to a floating-
point register.

MRd = MRe - MRf;

MRa = [mem32];

Restrictions
The destination register for the MSUBF32 and the MMOV32 must be unique. That is,
MRa cannot be the same register as MRd.

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MSUBF32 generates an underflow condition.
• LVF = 1 if MSUBF32 generates an overflow condition.
The MMOV32 instruction sets the NF and ZF flags.

Pipeline
Both MSUBF32 and MMOV32 complete in a single cycle.

Example
NF = MRa(31);
ZF = 0;
if(MRa(30:23) == 0) { ZF = 1; NF = 0; }

See also
MSUBF32 MRa, MRb, MRc
MSUBF32 MRa, #16FHi, MRb
MMPYF32 MRa, MRb, MRc || MSUBF32 MRd, MRe, MRf

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MSUBF32 MRd, MRe, MRf ||MMOV32 mem32, MRa

32-Bit Floating-Point Subtraction with Parallel Move

Operands MRd CLA floating-point destination register (MR0 to MR3) for the
MSUBF32 operation
MRe CLA floating-point source register (MR0 to MR3) for the MSUBF32
operation
MRf CLA floating-point source register (MR0 to MR3) for the MSUBF32
operation
mem32 32-bit destination memory location for the MMOV32 operation
MRa CLA floating-point source register (MR0 to MR3) for the MMOV32
operation

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0110 ffee ddaa addr

Description
Subtract the contents of two floating-point registers and move from a floating-point
register to memory.

MRd = MRe - MRf;

[mem32] = MRa;

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MSUBF32 generates an underflow condition.
• LVF = 1 if MSUBF32 generates an overflow condition.

Pipeline
Both MSUBF32 and MMOV32 complete in a single cycle.

See also
MSUBF32 MRa, MRb, MRc
MSUBF32 MRa, #16FHi, MRb
MSUBF32 MRd, MRe, MRf || MMOV32 MRa, mem32
MMPYF32 MRa, MRb, MRc || MSUBF32 MRd, MRe, MRf

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MSWAPF MRa, MRb {, CNDF}

Conditional Swap

Operands MRa CLA floating-point register (MR0 to MR3)

MRb CLA floating-point register (MR0 to MR3)
CNDF Optional condition tested based on the MSTF flags

Opcode
LSW: 0000 0000 CNDF bbaa
MSW: 0111 1011 0000 0000

Description
Conditional swap of MRa and MRb.

if (CNDF == true) swap MRa and MRb;

CNDF is one of the following conditions:

Encode(1) CNDF Description MSTF Flags Tested
0000 NEQ Not equal to zero ZF == 0
0001 EQ Equal to zero ZF == 1
0010 GT Greater than zero ZF == 0 AND NF == 0
0011 GEQ Greater than or equal NF == 0
to zero
0100 LT Less than zero NF == 1
0101 LEQ Less than or equal to ZF == 1 OR NF == 1
zero
1010 TF Test flag set TF == 1
1011 NTF Test flag not set TF == 0
1100 LU Latched underflow LUF == 1
1101 LV Latched overflow LVF == 1
1110 UNC Unconditional None
1111 UNCF(2) Unconditional with flag None
modification

(1) Values not shown are reserved.

(2) This is the default operation, if no CNDF field is specified. This condition
allows the ZF and NF flags to be modified when a conditional operation is
executed. All other conditions do not modify these flags.

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No No No

No flags affected

Pipeline
This is a single-cycle instruction.

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MSWAPF MRa, MRb {, CNDF} (continued)

Conditional Swap

Example
; X is an array of 32-bit floating-point values
; and has length elements. Find the maximum value in
; the array and store the value in Result
;
; Note: MCMPF32 and MSWAPF can be replaced by MMAXF32
;
_Cla1Task1:
MMOVI16 MAR1,#_X ; Start address
MUI16TOF32 MR0, @_len ; Length of the array
MNOP ; delay for MAR1 load
MNOP ; delay for MAR1 load
MMOV32 MR1, *MAR1[2]++ ; MR1 = X0
LOOP
MMOV32 MR2, *MAR1[2]++ ; MR2 = next element
MCMPF32 MR2, MR1 ; Compare MR2 with MR1
MSWAPF MR1, MR2, GT ; MR1 = MAX(MR1, MR2)
MADDF32 MR0, MR0, #-1.0 ; Decrememt the counter
MCMPF32 MR0 #0.0 ; Set/clear flags for MBCNDD
MNOP
MNOP
MNOP
MBCNDD LOOP, NEQ ; Branch if not equal to zero
MMOV32 @_Result, MR1 ; Always executed
MNOP ; Always executed
MNOP ; Always executed
MSTOP ; End of task

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MTESTTF CNDF

Test MSTF Register Flag Condition

Operands CNDF Condition to test based on MSTF flags

Opcode
LSW: 0000 0000 0000 cndf
MSW: 0111 1111 0100 0000

Description
Test the CLA floating-point condition and if true, set the MSTF[TF] flag. If the condition is
false, clear the MSTF[TF] flag. This is useful for temporarily storing a condition for later
use.

if (CNDF == true) TF = 1;
else TF = 0;

CNDF is one of the following conditions:

Encode(1) CNDF Description MSTF Flags Tested
0000 NEQ Not equal to zero ZF == 0
0001 EQ Equal to zero ZF == 1
0010 GT Greater than zero ZF == 0 AND NF == 0
0011 GEQ Greater than or equal NF == 0
to zero
0100 LT Less than zero NF == 1
0101 LEQ Less than or equal to ZF == 1 OR NF == 1
zero
1010 TF Test flag set TF == 1
1011 NTF Test flag not set TF == 0
1100 LU Latched underflow LUF == 1
1101 LV Latched overflow LVF == 1
1110 UNC Unconditional None
1111 UNCF(2) Unconditional with flag None
modification

(1) Values not shown are reserved.

(2) This is the default operation, if no CNDF field is specified. This condition
allows the ZF and NF flags to be modified when a conditional operation is
executed. All other conditions do not modify these flags.

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified Yes No No No No

TF = 0;
if (CNDF == true) TF = 1;

Note: If (CNDF == UNC or UNCF), the TF flag is set to 1.

Pipeline
This is a single-cycle instruction.

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MTESTTF CNDF (continued)

Test MSTF Register Flag Condition

Example
; if (State == 0.1)
; RampState = RampState || RAMPMASK
; else if (State == 0.01)
; CoastState = CoastState || COASTMASK
; else
; SteadyState = SteadyState || STEADYMASK
;
_Cla1Task2:
MMOV32 MR0, @_State
MCMPF32 MR0, #0.1 ; Affects flags for 1st MBCNDD (A)
MCMPF32 MR0, #0.01 ; Check used by 2nd MBCNDD (B)
MTESTTF EQ ; Store EQ flag in TF for 2nd MBCNDD (B)
MNOP
MBCNDD _Skip1, NEQ ; (A) If State != 0.1, go to Skip1
MMOV32 MR1, @_RampState ; Always executed
MMOVXI MR2, #RAMPMASK ; Always executed
MOR32 MR1, MR2 ; Always executed
MMOV32 @_RampState, MR1 ; Execute if (A) branch not taken
MSTOP ; end of task if (A) branch not taken
_Skip1:
MMOV32 MR3, @_SteadyState
MMOVXI MR2, #STEADYMASK
MOR32 MR3, MR2
MBCNDD _Skip2, NTF ; (B) if State != .01, go to Skip2
MMOV32 MR1, @_CoastState ; Always executed
MMOVXI MR2, #COASTMASK ; Always executed
MOR32 MR1, MR2 ; Always executed
MMOV32 @_CoastState, MR1 ; Execute if (B) branch not taken
MSTOP ; end of task if (B) branch not taken
_Skip2:
MMOV32 @_SteadyState, MR3 ; Executed if (B) branch taken
MSTOP

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MUI16TOF32 MRa, mem16

Convert Unsigned 16-Bit Integer to 32-Bit Floating-Point Value

Operands MRa CLA floating-point destination register (MR0 to MR3)

mem16 16-bit source memory location

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0111 0101 01aa addr

Description
When converting F32 to I16/UI16 data format, the MF32TOI16/UI16 operation truncates to
zero while the MF32TOI16R/UI16R operation rounds to the nearest (even) value.

MRa = UI16TOF32[mem16];

Flags
This instruction does not affect any flags:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline
This is a single-cycle instruction.

See also
MF32TOI16 MRa, MRb
MF32TOI16R MRa, MRb
MF32TOUI16 MRa, MRb
MF32TOUI16R MRa, MRb
MI16TOF32 MRa, MRb
MI16TOF32 MRa, mem16
MUI16TOF32 MRa, MRb

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MUI16TOF32 MRa, MRb

Convert Unsigned 16-Bit Integer to 32-Bit Floating-Point Value

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1110 1110 0000

Description
Convert an unsigned 16-bit integer to a 32-bit floating-point value. When converting
float32 to I16/UI16 data format, the MF32TOI16/UI16 operation truncates to zero while
the MF32TOI16R/UI16R operation rounds to the nearest (even) value.

MRa = UI16TOF32[MRb];

Flags
This instruction does not affect any flags:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline
This is a single-cycle instruction.

Example
MMOVXI MR1, #0x800F ; MR1(15:0) = 32783 (0x800F)
MUI16TOF32 MR0, MR1 ; MR0 = UI16TOF32 (MR1(15:0))
; = 32783.0 (0x47000F00)

See also
MF32TOI16 MRa, MRb
MF32TOI16R MRa, MRb
MF32TOUI16 MRa, MRb
MF32TOUI16R MRa, MRb
MI16TOF32 MRa, MRb
MI16TOF32 MRa, mem16
MUI16TOF32 MRa, mem16

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MUI32TOF32 MRa, mem32

Convert Unsigned 32-Bit Integer to 32-Bit Floating-Point Value

Operands MRa CLA floating-point destination register (MR0 to MR3)

mem32 32-bit memory location accessed using one of the available
addressing modes

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0111 0100 10aa addr

Description
MRa = UI32TOF32[mem32];

Flags
This instruction does not affect any flags:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline
This is a single-cycle instruction.

Example
; Given x2, m2, and b2 are Uint32 numbers:
;
; x2 = Uint32(2) = 0x00000002
; m2 = Uint32(1) = 0x00000001
; b2 = Uint32(3) = 0x00000003
;
; Calculate y2 = x2 * m2 + b2
;
_Cla1Task1:
MUI32TOF32 MR0, @_m2 ; MR0 = 1.0 (0x3F800000)
MUI32TOF32 MR1, @_x2 ; MR1 = 2.0 (0x40000000)
MUI32TOF32 MR2, @_b2 ; MR2 = 3.0 (0x40400000)
MMPYF32 MR3, MR0, MR1 ; M*X
MADDF32 MR3, MR2, MR3 ; Y=MX+B = 5.0 (0x40A00000)
MF32TOUI32 MR3, MR3 ; Y = Uint32(5.0) = 0x00000005
MMOV32 @_y2, MR3 ; store result
MSTOP ; end of task

See also
MF32TOI32 MRa, MRb
MF32TOUI32 MRa, MRb
MI32TOF32 MRa, mem32
MI32TOF32 MRa, MRb
MUI32TOF32 MRa, MRb

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MUI32TOF32 MRa, MRb

Convert Unsigned 32-Bit Integer to 32-Bit Floating-Point Value

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1101 1100 0000

Description
MRa = UI32TOF32 [MRb];

Flags
This instruction does not affect any flags:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline
This is a single-cycle instruction.

Example
MMOVIZ MR3, #0x8000 ; MR3(31:16) = 0x8000
MMOVXI MR3, #0x1111 ; MR3(15:0) = 0x1111
; MR3 = 2147488017
MUI32TOF32 MR3, MR3 ; MR3 = MUI32TOF32 (MR3) = 2147488017.0 (0x4F000011)

See also
MF32TOI32 MRa, MRb
MF32TOUI32 MRa, MRb
MI32TOF32 MRa, mem32
MI32TOF32 MRa, MRb
MUI32TOF32 MRa, mem32

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MXOR32 MRa, MRb, MRc

Bitwise Exclusive Or

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)
MRc CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 00cc bbaa
MSW: 0111 1100 1010 0000

Description
Bitwise XOR of MRb with MRc.

MARa(31:0) = MARb(31:0) XOR MRc(31:0);

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified based on the integer results of the operation.

NF = MRa(31);
ZF = 0;
if(MRa(31:0) == 0) { ZF = 1; }

Pipeline
This is a single-cycle instruction.

Example
MMOVIZ MR0, #0x5555 ; MR0 = 0x5555AAAA
MMOVXI MR0, #0xAAAA
MMOVIZ MR1, #0x5432 ; MR1 = 0x5432FEDC
MMOVXI MR1, #0xFEDC
; 0101 XOR 0101 = 0000 (0)
; 0101 XOR 0100 = 0001 (1)
; 0101 XOR 0011 = 0110 (6)
; 0101 XOR 0010 = 0111 (7)
; 1010 XOR 1111 = 0101 (5)
; 1010 XOR 1110 = 0100 (4)
; 1010 XOR 1101 = 0111 (7)
; 1010 XOR 1100 = 0110 (6)
MXOR32 MR2, MR1, MR0 ; MR3 = 0x01675476

See also
MAND32 MRa, MRb, MRc
MOR32 MRa, MRb, MRc

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6.8 CLA Registers

This section describes the Control Law Accelerator registers.
6.8.1 CLA Base Addresses
Table 6-21. CLA Base Address Table
Device Register Register Name Start Address End Address
Cla1Regs CLA_REGS 0x0000_1400 0x0000_147F
Cla1SoftIntRegs(1) CLA_SOFTINT_REGS 0x0000_0CE0 0x0000_0CFF

(1) This register is only accessible from the CLA.

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6.8.2 CLA_REGS Registers

Table 6-22 lists the memory-mapped registers for the CLA_REGS registers. All register offset addresses not
listed in Table 6-22 should be considered as reserved locations and the register contents should not be modified.
Table 6-22. CLA_REGS Registers
Offset Acronym Register Name Write Protection Section
0h MVECT1 Task Interrupt Vector EALLOW Go
1h MVECT2 Task Interrupt Vector EALLOW Go
2h MVECT3 Task Interrupt Vector EALLOW Go
3h MVECT4 Task Interrupt Vector EALLOW Go
4h MVECT5 Task Interrupt Vector EALLOW Go
5h MVECT6 Task Interrupt Vector EALLOW Go
6h MVECT7 Task Interrupt Vector EALLOW Go
7h MVECT8 Task Interrupt Vector EALLOW Go
10h MCTL Control Register EALLOW Go
20h MIFR Interrupt Flag Register EALLOW Go
21h MIOVF Interrupt Overflow Flag Register EALLOW Go
22h MIFRC Interrupt Force Register EALLOW Go
23h MICLR Interrupt Flag Clear Register EALLOW Go
24h MICLROVF Interrupt Overflow Flag Clear Register EALLOW Go
25h MIER Interrupt Enable Register EALLOW Go
26h MIRUN Interrupt Run Status Register EALLOW Go
28h _MPC CLA Program Counter Go
2Ah _MAR0 CLA Auxiliary Register 0 Go
2Bh _MAR1 CLA Auxiliary Register 1 Go
2Eh _MSTF CLA Floating-Point Status Register Go
30h _MR0 CLA Floating-Point Result Register 0 Go
34h _MR1 CLA Floating-Point Result Register 1 Go
38h _MR2 CLA Floating-Point Result Register 2 Go
3Ch _MR3 CLA Floating-Point Result Register 3 Go

Complex bit access types are encoded to fit into small table cells. Table 6-23 shows the codes that are used for
access types in this section.
Table 6-23. CLA_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1S W Write
1S 1 to set
Reset or Default Value
-n Value after reset or the default value
Register Array Variables

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Table 6-23. CLA_REGS Access Type Codes (continued)

Access Type Code Description
i,j,k,l,m,n When these variables are used in a register name,
an offset, or an address, they refer to the value of a
register array where the register is part of a group
of repeating registers. The register groups form a
hierarchical structure and the array is represented
with a formula.
y When this variable is used in a register name, an
offset, or an address it refers to the value of a
register array.

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6.8.2.1 MVECT1 Register (Offset = 0h) [Reset = 0000h]

MVECT1 is shown in Figure 6-2 and described in Table 6-24.
Return to the Summary Table.
Each CLA interrupt has its own interrupt vector (MVECT1 to MVECT8). This interrupt vector points to the
first instruction of the associated task. When a task begins, the CLA will start fetching instructions at the
location indicated by the appropriate MVECT register .
Figure 6-2. MVECT1 Register
15 14 13 12 11 10 9 8
MVECT
R/W-0h

7 6 5 4 3 2 1 0
MVECT
R/W-0h

Table 6-24. MVECT1 Register Field Descriptions

Bit Field Type Reset Description
15-0 MVECT R/W 0h MPC Start Address: These bits specify the start address for the
given interrupt (task). The address range of the CLA with a 16-bit
MVECT is 64Kx16 words or 32K CLA instructions.
There is one MVECT register per interrupt (task). Interrupt 1 uses
MVECT1, interrupt 2 uses MVECT2 and so forth.
Note: While the CLA is running or executing a task, the CPU can
change the MVECT values..
Reset type: SYSRSn

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6.8.2.2 MVECT2 Register (Offset = 1h) [Reset = 0000h]

MVECT2 is shown in Figure 6-3 and described in Table 6-25.
Return to the Summary Table.
Each CLA interrupt has its own interrupt vector (MVECT1 to MVECT8). This interrupt vector points to the
first instruction of the associated task. When a task begins, the CLA will start fetching instructions at the
location indicated by the appropriate MVECT register .
Figure 6-3. MVECT2 Register
15 14 13 12 11 10 9 8
MVECT
R/W-0h

7 6 5 4 3 2 1 0
MVECT
R/W-0h

Table 6-25. MVECT2 Register Field Descriptions

Bit Field Type Reset Description
15-0 MVECT R/W 0h MPC Start Address: These bits specify the start address for the
given interrupt (task). The address range of the CLA with a 16-bit
MVECT is 64Kx16 words or 32K CLA instructions.
There is one MVECT register per interrupt (task). Interrupt 1 uses
MVECT1, interrupt 2 uses MVECT2 and so forth.
Note: While the CLA is running or executing a task, the CPU can
change the MVECT values..
Reset type: SYSRSn

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6.8.2.3 MVECT3 Register (Offset = 2h) [Reset = 0000h]

MVECT3 is shown in Figure 6-4 and described in Table 6-26.
Return to the Summary Table.
Each CLA interrupt has its own interrupt vector (MVECT1 to MVECT8). This interrupt vector points to the
first instruction of the associated task. When a task begins, the CLA will start fetching instructions at the
location indicated by the appropriate MVECT register .
Figure 6-4. MVECT3 Register
15 14 13 12 11 10 9 8
MVECT
R/W-0h

7 6 5 4 3 2 1 0
MVECT
R/W-0h

Table 6-26. MVECT3 Register Field Descriptions

Bit Field Type Reset Description
15-0 MVECT R/W 0h MPC Start Address: These bits specify the start address for the
given interrupt (task). The address range of the CLA with a 16-bit
MVECT is 64Kx16 words or 32K CLA instructions.
There is one MVECT register per interrupt (task). Interrupt 1 uses
MVECT1, interrupt 2 uses MVECT2 and so forth.
Note: While the CLA is running or executing a task, the CPU can
change the MVECT values..
Reset type: SYSRSn

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6.8.2.4 MVECT4 Register (Offset = 3h) [Reset = 0000h]

MVECT4 is shown in Figure 6-5 and described in Table 6-27.
Return to the Summary Table.
Each CLA interrupt has its own interrupt vector (MVECT1 to MVECT8). This interrupt vector points to the
first instruction of the associated task. When a task begins, the CLA will start fetching instructions at the
location indicated by the appropriate MVECT register .
Figure 6-5. MVECT4 Register
15 14 13 12 11 10 9 8
MVECT
R/W-0h

7 6 5 4 3 2 1 0
MVECT
R/W-0h

Table 6-27. MVECT4 Register Field Descriptions

Bit Field Type Reset Description
15-0 MVECT R/W 0h MPC Start Address: These bits specify the start address for the
given interrupt (task). The address range of the CLA with a 16-bit
MVECT is 64Kx16 words or 32K CLA instructions.
There is one MVECT register per interrupt (task). Interrupt 1 uses
MVECT1, interrupt 2 uses MVECT2 and so forth.
Note: While the CLA is running or executing a task, the CPU can
change the MVECT values..
Reset type: SYSRSn

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6.8.2.5 MVECT5 Register (Offset = 4h) [Reset = 0000h]

MVECT5 is shown in Figure 6-6 and described in Table 6-28.
Return to the Summary Table.
Each CLA interrupt has its own interrupt vector (MVECT1 to MVECT8). This interrupt vector points to the
first instruction of the associated task. When a task begins, the CLA will start fetching instructions at the
location indicated by the appropriate MVECT register .
Figure 6-6. MVECT5 Register
15 14 13 12 11 10 9 8
MVECT
R/W-0h

7 6 5 4 3 2 1 0
MVECT
R/W-0h

Table 6-28. MVECT5 Register Field Descriptions

Bit Field Type Reset Description
15-0 MVECT R/W 0h MPC Start Address: These bits specify the start address for the
given interrupt (task). The address range of the CLA with a 16-bit
MVECT is 64Kx16 words or 32K CLA instructions.
There is one MVECT register per interrupt (task). Interrupt 1 uses
MVECT1, interrupt 2 uses MVECT2 and so forth.
Note: While the CLA is running or executing a task, the CPU can
change the MVECT values..
Reset type: SYSRSn

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6.8.2.6 MVECT6 Register (Offset = 5h) [Reset = 0000h]

MVECT6 is shown in Figure 6-7 and described in Table 6-29.
Return to the Summary Table.
Each CLA interrupt has its own interrupt vector (MVECT1 to MVECT8). This interrupt vector points to the
first instruction of the associated task. When a task begins, the CLA will start fetching instructions at the
location indicated by the appropriate MVECT register .
Figure 6-7. MVECT6 Register
15 14 13 12 11 10 9 8
MVECT
R/W-0h

7 6 5 4 3 2 1 0
MVECT
R/W-0h

Table 6-29. MVECT6 Register Field Descriptions

Bit Field Type Reset Description
15-0 MVECT R/W 0h MPC Start Address: These bits specify the start address for the
given interrupt (task). The address range of the CLA with a 16-bit
MVECT is 64Kx16 words or 32K CLA instructions.
There is one MVECT register per interrupt (task). Interrupt 1 uses
MVECT1, interrupt 2 uses MVECT2 and so forth.
Note: While the CLA is running or executing a task, the CPU can
change the MVECT values..
Reset type: SYSRSn

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6.8.2.7 MVECT7 Register (Offset = 6h) [Reset = 0000h]

MVECT7 is shown in Figure 6-8 and described in Table 6-30.
Return to the Summary Table.
Each CLA interrupt has its own interrupt vector (MVECT1 to MVECT8). This interrupt vector points to the
first instruction of the associated task. When a task begins, the CLA will start fetching instructions at the
location indicated by the appropriate MVECT register .
Figure 6-8. MVECT7 Register
15 14 13 12 11 10 9 8
MVECT
R/W-0h

7 6 5 4 3 2 1 0
MVECT
R/W-0h

Table 6-30. MVECT7 Register Field Descriptions

Bit Field Type Reset Description
15-0 MVECT R/W 0h MPC Start Address: These bits specify the start address for the
given interrupt (task). The address range of the CLA with a 16-bit
MVECT is 64Kx16 words or 32K CLA instructions.
There is one MVECT register per interrupt (task). Interrupt 1 uses
MVECT1, interrupt 2 uses MVECT2 and so forth.
Note: While the CLA is running or executing a task, the CPU can
change the MVECT values..
Reset type: SYSRSn

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6.8.2.8 MVECT8 Register (Offset = 7h) [Reset = 0000h]

MVECT8 is shown in Figure 6-9 and described in Table 6-31.
Return to the Summary Table.
Each CLA interrupt has its own interrupt vector (MVECT1 to MVECT8). This interrupt vector points to the
first instruction of the associated task. When a task begins, the CLA will start fetching instructions at the
location indicated by the appropriate MVECT register .
Figure 6-9. MVECT8 Register
15 14 13 12 11 10 9 8
MVECT
R/W-0h

7 6 5 4 3 2 1 0
MVECT
R/W-0h

Table 6-31. MVECT8 Register Field Descriptions

Bit Field Type Reset Description
15-0 MVECT R/W 0h MPC Start Address: These bits specify the start address for the
given interrupt (task). The address range of the CLA with a 16-bit
MVECT is 64Kx16 words or 32K CLA instructions.
There is one MVECT register per interrupt (task). Interrupt 1 uses
MVECT1, interrupt 2 uses MVECT2 and so forth.
Note: While the CLA is running or executing a task, the CPU can
change the MVECT values..
Reset type: SYSRSn

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6.8.2.9 MCTL Register (Offset = 10h) [Reset = 0000h]

MCTL is shown in Figure 6-10 and described in Table 6-32.
Return to the Summary Table.
Control Register
Figure 6-10. MCTL Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED IACKE SOFTRESET HARDRESET
R-0h R/W-0h R-0/W1S-0h R-0/W1S-0h

Table 6-32. MCTL Register Field Descriptions

Bit Field Type Reset Description
15-3 RESERVED R 0h Reserved
2 IACKE R/W 0h IACK Operation Enable Bit: Writing a '1' to this bit will enable the
IACK operation for setting the MIFR bits in the same manner as the
MIFRC register (write of '1' will set respective MIFR bit). At reset, this
feature is disabled.
This feature enables the C28 CPU to efficiently trigger a task.
Note: IACK operation should ignore EALLOW status of C28 core
when accessing the MIFRC register.
Reset type: SYSRSn
0h (R/W) = The CLA ignores the IACK instruction. (default)
1h (R/W) = Enable the main CPU to use the IACK #16bit instruction
to set MIFR bits in the same manner as writing to the MIFRC
register. Each bit in the operand, #16bit, corresponds to a bit in the
MIFRC register. Using IACK has the advantage of not having to first
set the EALLOW bit. This allows the main CPU to efficiently trigger a
CLA task through software.
Examples IACK #0x0001 Write a 1 to MIFRC bit 0 to force task 1
IACK #0x0003 Write a 1 to MIFRC bit 0 and 1 to force task 1 and
task 2
1 SOFTRESET R-0/W1S 0h Soft Reset Bit: Writing a '1' to this bit will stop a current task, clear
the RUN flag and also clear all bits in the MIER register. Writes of '0'
are ignored and reads always return a '0'.
Note: After issuing SOFTRESET command, user should wait at least
1 clock cycle before attempting to write to MIER register.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 are ignored.
1h (R/W) = Writing a 1 will cause a soft reset of the CLA. This
will stop the current task, clear the MIRUN flag and clear all bits
in the MIER register. After a soft reset you must wait at least 1
SYSCLKOUT cycle before reconfiguring the MIER bits. If these two
operations are done back-to-back then the MIER bits will not get set.
0 HARDRESET R-0/W1S 0h Hard Reset Bit: Writing a '1' to this bit will cause a HARD reset on the
CLA. The behavior of a HARD reset is the same as a system reset
SYSRSn on the CLA. Writes of '0' are ignored and reads always
return a '0'.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 are ignored.
1h (R/W) = Writing a 1 will cause a hard reset of the CLA. This will
set all CLA registers to their default state.

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6.8.2.10 MIFR Register (Offset = 20h) [Reset = 0000h]

MIFR is shown in Figure 6-11 and described in Table 6-33.
Return to the Summary Table.
Each bit in the interrupt flag register corresponds to a CLA task. The corresponding bit is automatically set
when the task request is received from the peripheral interrupt. The bit can also be set by the main CPU
writing to the MIFRC register or using the IACK instruction to start the task. To use the IACK instruction to
begin a task first enable this feature in the MCTL register. If the bit is already set when a new peripheral
interrupt is received, then the corresponding overflow bit will be set in the MIOVF register.
The corresponding MIFR bit is automatically cleared when the task begins execution. This will occur if the
interrupt is enabled in the MIER register and no other higher priority task is pending. The bits can also be
cleared manually by writing to the MICLR register. Writes to the MIFR register are ignored.
Figure 6-11. MIFR Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
INT8 INT7 INT6 INT5 INT4 INT3 INT2 INT1
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 6-33. MIFR Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R 0h Reserved
7 INT8 R 0h These bits, when set to '1', indicate a valid peripheral interrupt has
been latched by the CLA. Writes to this register are ignored.
The IFR flag bit is automatically cleared if the respective interrupt is
enabled in the MIER register and the respective task starts running.
If a new peripheral interrupt attempts to set the bit to '1' while on the
same cycle the task tries to clear it, then the peripheral interrupt will
have priority.
The IFR flag bits can also be set and cleared by the MIFRC and
MICLR registers.
If the MIFRC register is trying to set the respective bit while a new
task tries to clear it, then the MIFRC event has priority.
If the MICLR register is trying to clear the respective bit and a
peripheral interrupt occurs on the same cycle, then the peripheral
interrupt has priority. The respective overflow flag in the MIOVF
register will not be set under this condition.
Reset type: SYSRSn
0h (R/W) = TASK_FLAG_DISABLE
Task 8 interrupt is currently not flagged (default)
1h (R/W) = TASK_FLAG_ENABLE
Task 8 interrupt has been received and is pending execution

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Table 6-33. MIFR Register Field Descriptions (continued)

Bit Field Type Reset Description
6 INT7 R 0h These bits, when set to '1', indicate a valid peripheral interrupt has
been latched by the CLA. Writes to this register are ignored.
The IFR flag bit is automatically cleared if the respective interrupt is
enabled in the MIER register and the respective task starts running.
If a new peripheral interrupt attempts to set the bit to '1' while on the
same cycle the task tries to clear it, then the peripheral interrupt will
have priority.
The IFR flag bits can also be set and cleared by the MIFRC and
MICLR registers.
If the MIFRC register is trying to set the respective bit while a new
task tries to clear it, then the MIFRC event has priority.
If the MICLR register is trying to clear the respective bit and a
peripheral interrupt occurs on the same cycle, then the peripheral
interrupt has priority. The respective overflow flag in the MIOVF
register will not be set under this condition.
Reset type: SYSRSn
0h (R/W) = TASK_FLAG_DISABLE
Task 7 interrupt is currently not flagged (default)
1h (R/W) = TASK_FLAG_ENABLE
Task 7 interrupt has been received and is pending execution
5 INT6 R 0h These bits, when set to '1', indicate a valid peripheral interrupt has
been latched by the CLA. Writes to this register are ignored.
The IFR flag bit is automatically cleared if the respective interrupt is
enabled in the MIER register and the respective task starts running.
If a new peripheral interrupt attempts to set the bit to '1' while on the
same cycle the task tries to clear it, then the peripheral interrupt will
have priority.
The IFR flag bits can also be set and cleared by the MIFRC and
MICLR registers.
If the MIFRC register is trying to set the respective bit while a new
task tries to clear it, then the MIFRC event has priority.
If the MICLR register is trying to clear the respective bit and a
peripheral interrupt occurs on the same cycle, then the peripheral
interrupt has priority. The respective overflow flag in the MIOVF
register will not be set under this condition.
Reset type: SYSRSn
0h (R/W) = TASK_FLAG_DISABLE
Task 6 interrupt is currently not flagged (default)
1h (R/W) = TASK_FLAG_ENABLE
Task 6 interrupt has been received and is pending execution
4 INT5 R 0h These bits, when set to '1', indicate a valid peripheral interrupt has
been latched by the CLA. Writes to this register are ignored.
The IFR flag bit is automatically cleared if the respective interrupt is
enabled in the MIER register and the respective task starts running.
If a new peripheral interrupt attempts to set the bit to '1' while on the
same cycle the task tries to clear it, then the peripheral interrupt will
have priority.
The IFR flag bits can also be set and cleared by the MIFRC and
MICLR registers.
If the MIFRC register is trying to set the respective bit while a new
task tries to clear it, then the MIFRC event has priority.
If the MICLR register is trying to clear the respective bit and a
peripheral interrupt occurs on the same cycle, then the peripheral
interrupt has priority. The respective overflow flag in the MIOVF
register will not be set under this condition.
Reset type: SYSRSn
0h (R/W) = TASK_FLAG_DISABLE
Task 5 interrupt is currently not flagged (default)
1h (R/W) = TASK_FLAG_ENABLE
Task 5 interrupt has been received and is pending execution

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Table 6-33. MIFR Register Field Descriptions (continued)

Bit Field Type Reset Description
3 INT4 R 0h These bits, when set to '1', indicate a valid peripheral interrupt has
been latched by the CLA. Writes to this register are ignored.
The IFR flag bit is automatically cleared if the respective interrupt is
enabled in the MIER register and the respective task starts running.
If a new peripheral interrupt attempts to set the bit to '1' while on the
same cycle the task tries to clear it, then the peripheral interrupt will
have priority.
The IFR flag bits can also be set and cleared by the MIFRC and
MICLR registers.
If the MIFRC register is trying to set the respective bit while a new
task tries to clear it, then the MIFRC event has priority.
If the MICLR register is trying to clear the respective bit and a
peripheral interrupt occurs on the same cycle, then the peripheral
interrupt has priority. The respective overflow flag in the MIOVF
register will not be set under this condition.
Reset type: SYSRSn
0h (R/W) = TASK_FLAG_DISABLE
Task 4 interrupt is currently not flagged (default)
1h (R/W) = TASK_FLAG_ENABLE
Task 4 interrupt has been received and is pending execution
2 INT3 R 0h These bits, when set to '1', indicate a valid peripheral interrupt has
been latched by the CLA. Writes to this register are ignored.
The IFR flag bit is automatically cleared if the respective interrupt is
enabled in the MIER register and the respective task starts running.
If a new peripheral interrupt attempts to set the bit to '1' while on the
same cycle the task tries to clear it, then the peripheral interrupt will
have priority.
The IFR flag bits can also be set and cleared by the MIFRC and
MICLR registers.
If the MIFRC register is trying to set the respective bit while a new
task tries to clear it, then the MIFRC event has priority.
If the MICLR register is trying to clear the respective bit and a
peripheral interrupt occurs on the same cycle, then the peripheral
interrupt has priority. The respective overflow flag in the MIOVF
register will not be set under this condition.
Reset type: SYSRSn
0h (R/W) = TASK_FLAG_DISABLE
Task 3 interrupt is currently not flagged (default)
1h (R/W) = TASK_FLAG_ENABLE
Task 3 interrupt has been received and is pending execution
1 INT2 R 0h These bits, when set to '1', indicate a valid peripheral interrupt has
been latched by the CLA. Writes to this register are ignored.
The IFR flag bit is automatically cleared if the respective interrupt is
enabled in the MIER register and the respective task starts running.
If a new peripheral interrupt attempts to set the bit to '1' while on the
same cycle the task tries to clear it, then the peripheral interrupt will
have priority.
The IFR flag bits can also be set and cleared by the MIFRC and
MICLR registers.
If the MIFRC register is trying to set the respective bit while a new
task tries to clear it, then the MIFRC event has priority.
If the MICLR register is trying to clear the respective bit and a
peripheral interrupt occurs on the same cycle, then the peripheral
interrupt has priority. The respective overflow flag in the MIOVF
register will not be set under this condition.
Reset type: SYSRSn
0h (R/W) = TASK_FLAG_DISABLE
Task 2 interrupt is currently not flagged (default)
1h (R/W) = TASK_FLAG_ENABLE
Task 2 interrupt has been received and is pending execution

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Table 6-33. MIFR Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INT1 R 0h These bits, when set to '1', indicate a valid peripheral interrupt has
been latched by the CLA. Writes to this register are ignored.
The IFR flag bit is automatically cleared if the respective interrupt is
enabled in the MIER register and the respective task starts running.
If a new peripheral interrupt attempts to set the bit to '1' while on the
same cycle the task tries to clear it, then the peripheral interrupt will
have priority.
The IFR flag bits can also be set and cleared by the MIFRC and
MICLR registers.
If the MIFRC register is trying to set the respective bit while a new
task tries to clear it, then the MIFRC event has priority.
If the MICLR register is trying to clear the respective bit and a
peripheral interrupt occurs on the same cycle, then the peripheral
interrupt has priority. The respective overflow flag in the MIOVF
register will not be set under this condition.
Reset type: SYSRSn
0h (R/W) = TASK_FLAG_DISABLE
Task 1 interrupt is currently not flagged (default)
1h (R/W) = TASK_FLAG_ENABLE
Task 1 interrupt has been received and is pending execution

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6.8.2.11 MIOVF Register (Offset = 21h) [Reset = 0000h]

MIOVF is shown in Figure 6-12 and described in Table 6-34.
Return to the Summary Table.
Each bit in the overflow flag register corresponds to a CLA task. The bit is set when an interrupt overflow
event has occurred for the specific task. An overflow event occurs when the MIFR register bit is already
set when a new interrupt is received from a peripheral source. The MIOVF bits are only affected by
peripheral interrupt events. They do not respond to a task request by the main CPU IACK instruction or by
directly setting MIFR bits. The overflow flag will remain latched and can only be cleared by writing to the
overflow flag clear (MICLROVF) register. Writes to the MIOVF register are ignored.
Figure 6-12. MIOVF Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
INT8 INT7 INT6 INT5 INT4 INT3 INT2 INT1
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 6-34. MIOVF Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R 0h Reserved
7 INT8 R 0h These bits, when set to '1', indicate an interrupt overflow event
occurred. Such an event occurs when the IFR bit is already set.
An overflow event remains latched and respective bits can only be
cleared by writing to the MICLROVF register.
If the MIFR bit is being cleared by a new task on the same cycle as a
new peripheral interrupt occurs, the overflow flag will not be affected
and the respective MIFR bit will be set.
If the MIOVF bit is being cleared by the MICLROVF register on the
same cycle as the overflow bit is being set by hardware, then the
hardware will have priority.
Notes: [1] The MIOVF bits are only affected by peripheral interrupt
events. Forcing an interrupt using the MIFRC or IACK operation will
not set the overflow flag even if the MIFR bit is set.
Reset type: SYSRSn
0h (R/W) = A task 8 interrupt overflow has not occurred (default)
1h (R/W) = A task 8 interrupt overflow has occurred
6 INT7 R 0h These bits, when set to '1', indicate an interrupt overflow event
occurred. Such an event occurs when the IFR bit is already set.
An overflow event remains latched and respective bits can only be
cleared by writing to the MICLROVF register.
If the MIFR bit is being cleared by a new task on the same cycle as a
new peripheral interrupt occurs, the overflow flag will not be affected
and the respective MIFR bit will be set.
If the MIOVF bit is being cleared by the MICLROVF register on the
same cycle as the overflow bit is being set by hardware, then the
hardware will have priority.
Notes: [1] The MIOVF bits are only affected by peripheral interrupt
events. Forcing an interrupt using the MIFRC or IACK operation will
not set the overflow flag even if the MIFR bit is set.
Reset type: SYSRSn
0h (R/W) = A task 7 interrupt overflow has not occurred (default)
1h (R/W) = A task 7 interrupt overflow has occurred

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Table 6-34. MIOVF Register Field Descriptions (continued)

Bit Field Type Reset Description
5 INT6 R 0h These bits, when set to '1', indicate an interrupt overflow event
occurred. Such an event occurs when the IFR bit is already set.
An overflow event remains latched and respective bits can only be
cleared by writing to the MICLROVF register.
If the MIFR bit is being cleared by a new task on the same cycle as a
new peripheral interrupt occurs, the overflow flag will not be affected
and the respective MIFR bit will be set.
If the MIOVF bit is being cleared by the MICLROVF register on the
same cycle as the overflow bit is being set by hardware, then the
hardware will have priority.
Notes: [1] The MIOVF bits are only affected by peripheral interrupt
events. Forcing an interrupt using the MIFRC or IACK operation will
not set the overflow flag even if the MIFR bit is set.
Reset type: SYSRSn
0h (R/W) = A task 6 interrupt overflow has not occurred (default)
1h (R/W) = A task 6 interrupt overflow has occurred
4 INT5 R 0h These bits, when set to '1', indicate an interrupt overflow event
occurred. Such an event occurs when the IFR bit is already set.
An overflow event remains latched and respective bits can only be
cleared by writing to the MICLROVF register.
If the MIFR bit is being cleared by a new task on the same cycle as a
new peripheral interrupt occurs, the overflow flag will not be affected
and the respective MIFR bit will be set.
If the MIOVF bit is being cleared by the MICLROVF register on the
same cycle as the overflow bit is being set by hardware, then the
hardware will have priority.
Notes: [1] The MIOVF bits are only affected by peripheral interrupt
events. Forcing an interrupt using the MIFRC or IACK operation will
not set the overflow flag even if the MIFR bit is set.
Reset type: SYSRSn
0h (R/W) = A task 5 interrupt overflow has not occurred (default)
1h (R/W) = A task 5 interrupt overflow has occurred
3 INT4 R 0h These bits, when set to '1', indicate an interrupt overflow event
occurred. Such an event occurs when the IFR bit is already set.
An overflow event remains latched and respective bits can only be
cleared by writing to the MICLROVF register.
If the MIFR bit is being cleared by a new task on the same cycle as a
new peripheral interrupt occurs, the overflow flag will not be affected
and the respective MIFR bit will be set.
If the MIOVF bit is being cleared by the MICLROVF register on the
same cycle as the overflow bit is being set by hardware, then the
hardware will have priority.
Notes: [1] The MIOVF bits are only affected by peripheral interrupt
events. Forcing an interrupt using the MIFRC or IACK operation will
not set the overflow flag even if the MIFR bit is set.
Reset type: SYSRSn
0h (R/W) = A task 4 interrupt overflow has not occurred (default)
1h (R/W) = A task 4 interrupt overflow has occurred

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Table 6-34. MIOVF Register Field Descriptions (continued)

Bit Field Type Reset Description
2 INT3 R 0h These bits, when set to '1', indicate an interrupt overflow event
occurred. Such an event occurs when the IFR bit is already set.
An overflow event remains latched and respective bits can only be
cleared by writing to the MICLROVF register.
If the MIFR bit is being cleared by a new task on the same cycle as a
new peripheral interrupt occurs, the overflow flag will not be affected
and the respective MIFR bit will be set.
If the MIOVF bit is being cleared by the MICLROVF register on the
same cycle as the overflow bit is being set by hardware, then the
hardware will have priority.
Notes: [1] The MIOVF bits are only affected by peripheral interrupt
events. Forcing an interrupt using the MIFRC or IACK operation will
not set the overflow flag even if the MIFR bit is set.
Reset type: SYSRSn
0h (R/W) = A task 3 interrupt overflow has not occurred (default)
1h (R/W) = A task 3 interrupt overflow has occurred
1 INT2 R 0h These bits, when set to '1', indicate an interrupt overflow event
occurred. Such an event occurs when the IFR bit is already set.
An overflow event remains latched and respective bits can only be
cleared by writing to the MICLROVF register.
If the MIFR bit is being cleared by a new task on the same cycle as a
new peripheral interrupt occurs, the overflow flag will not be affected
and the respective MIFR bit will be set.
If the MIOVF bit is being cleared by the MICLROVF register on the
same cycle as the overflow bit is being set by hardware, then the
hardware will have priority.
Notes: [1] The MIOVF bits are only affected by peripheral interrupt
events. Forcing an interrupt using the MIFRC or IACK operation will
not set the overflow flag even if the MIFR bit is set.
Reset type: SYSRSn
0h (R/W) = A task 2 interrupt overflow has not occurred (default)
1h (R/W) = A task 2 interrupt overflow has occurred
0 INT1 R 0h These bits, when set to '1', indicate an interrupt overflow event
occurred. Such an event occurs when the IFR bit is already set.
An overflow event remains latched and respective bits can only be
cleared by writing to the MICLROVF register.
If the MIFR bit is being cleared by a new task on the same cycle as a
new peripheral interrupt occurs, the overflow flag will not be affected
and the respective MIFR bit will be set.
If the MIOVF bit is being cleared by the MICLROVF register on the
same cycle as the overflow bit is being set by hardware, then the
hardware will have priority.
Notes: [1] The MIOVF bits are only affected by peripheral interrupt
events. Forcing an interrupt using the MIFRC or IACK operation will
not set the overflow flag even if the MIFR bit is set.
Reset type: SYSRSn
0h (R/W) = A task 1 interrupt overflow has not occurred (default)
1h (R/W) = A task 1 interrupt overflow has occurred

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6.8.2.12 MIFRC Register (Offset = 22h) [Reset = 0000h]

MIFRC is shown in Figure 6-13 and described in Table 6-35.
Return to the Summary Table.
The interrupt force register can be used by the main CPU to start tasks through software. Writing a 1 to a
MIFRC bit will set the corresponding bit in the MIFR register. Writes of 0 are ignored and reads always
return 0. The IACK #16bit operation can also be used to start tasks and has the same effect as the
MIFRC register. To enable IACK to set MIFR bits you must first set the MCTL[IACKE] bit. Using IACK has
the advantage of not having to first set the EALLOW bit. This allows the main CPU to efficiently trigger
CLA tasks through software.
Figure 6-13. MIFRC Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
INT8 INT7 INT6 INT5 INT4 INT3 INT2 INT1
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 6-35. MIFRC Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R 0h Reserved
7 INT8 R-0/W1S 0h Writing a '1' to any of the bits will set the corresponding MIFR bit.
Writes of '0' are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to force the task 8 interrupt
6 INT7 R-0/W1S 0h Writing a '1' to any of the bits will set the corresponding MIFR bit.
Writes of '0' are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to force the task 7 interrupt
5 INT6 R-0/W1S 0h Writing a '1' to any of the bits will set the corresponding MIFR bit.
Writes of '0' are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to force the task 6 interrupt
4 INT5 R-0/W1S 0h Writing a '1' to any of the bits will set the corresponding MIFR bit.
Writes of '0' are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to force the task 5 interrupt

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Table 6-35. MIFRC Register Field Descriptions (continued)

Bit Field Type Reset Description
3 INT4 R-0/W1S 0h Writing a '1' to any of the bits will set the corresponding MIFR bit.
Writes of '0' are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to force the task 4 interrupt
2 INT3 R-0/W1S 0h Writing a '1' to any of the bits will set the corresponding MIFR bit.
Writes of '0' are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to force the task 3 interrupt
1 INT2 R-0/W1S 0h Writing a '1' to any of the bits will set the corresponding MIFR bit.
Writes of '0' are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to force the task 2 interrupt
0 INT1 R-0/W1S 0h Writing a '1' to any of the bits will set the corresponding MIFR bit.
Writes of '0' are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to force the task 1 interrupt

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6.8.2.13 MICLR Register (Offset = 23h) [Reset = 0000h]

MICLR is shown in Figure 6-14 and described in Table 6-36.
Return to the Summary Table.
Normally bits in the MIFR register are automatically cleared when a task begins. The interrupt flag clear
register can be used to instead manually clear bits in the interrupt flag (MIFR) register. Writing a 1 to a
MICLR bit will clear the corresponding bit in the MIFR register. Writes of 0 are ignored and reads always
return 0.
Figure 6-14. MICLR Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
INT8 INT7 INT6 INT5 INT4 INT3 INT2 INT1
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 6-36. MICLR Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R 0h Reserved
7 INT8 R-0/W1S 0h Writing a '1' to any of the bits will clear the corresponding MIFR bit.
Writes of '0' are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 8 interrupt flag
6 INT7 R-0/W1S 0h Writing a '1' to any of the bits will clear the corresponding MIFR bit.
Writes of '0' are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 7 interrupt flag
5 INT6 R-0/W1S 0h Writing a '1' to any of the bits will clear the corresponding MIFR bit.
Writes of '0' are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 6 interrupt flag
4 INT5 R-0/W1S 0h Writing a '1' to any of the bits will clear the corresponding MIFR bit.
Writes of '0' are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 5 interrupt flag

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Table 6-36. MICLR Register Field Descriptions (continued)

Bit Field Type Reset Description
3 INT4 R-0/W1S 0h Writing a '1' to any of the bits will clear the corresponding MIFR bit.
Writes of '0' are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 4 interrupt flag
2 INT3 R-0/W1S 0h Writing a '1' to any of the bits will clear the corresponding MIFR bit.
Writes of '0' are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 3 interrupt flag
1 INT2 R-0/W1S 0h Writing a '1' to any of the bits will clear the corresponding MIFR bit.
Writes of '0' are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 2 interrupt flag
0 INT1 R-0/W1S 0h Writing a '1' to any of the bits will clear the corresponding MIFR bit.
Writes of '0' are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 1 interrupt flag

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6.8.2.14 MICLROVF Register (Offset = 24h) [Reset = 0000h]

MICLROVF is shown in Figure 6-15 and described in Table 6-37.
Return to the Summary Table.
Overflow flag bits in the MIOVF register are latched until manually cleared using the MICLROVF register.
Writing a 1 to a MICLROVF bit will clear the corresponding bit in the MIOVF register. Writes of 0 are
ignored and reads always return 0.
Figure 6-15. MICLROVF Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
INT8 INT7 INT6 INT5 INT4 INT3 INT2 INT1
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 6-37. MICLROVF Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R 0h Reserved
7 INT8 R-0/W1S 0h Writing a '1' to any of the bits will clear the corresponding MIOVF bit.
Writes of '0' are ignored. Reads always return 0.
Notes: [1] Refer to MIOVF register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 8 interrupt overflow flag
6 INT7 R-0/W1S 0h Writing a '1' to any of the bits will clear the corresponding MIOVF bit.
Writes of '0' are ignored. Reads always return 0.
Notes: [1] Refer to MIOVF register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 7 interrupt overflow flag
5 INT6 R-0/W1S 0h Writing a '1' to any of the bits will clear the corresponding MIOVF bit.
Writes of '0' are ignored. Reads always return 0.
Notes: [1] Refer to MIOVF register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 6 interrupt overflow flag
4 INT5 R-0/W1S 0h Writing a '1' to any of the bits will clear the corresponding MIOVF bit.
Writes of '0' are ignored. Reads always return 0.
Notes: [1] Refer to MIOVF register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 5 interrupt overflow flag

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Table 6-37. MICLROVF Register Field Descriptions (continued)

Bit Field Type Reset Description
3 INT4 R-0/W1S 0h Writing a '1' to any of the bits will clear the corresponding MIOVF bit.
Writes of '0' are ignored. Reads always return 0.
Notes: [1] Refer to MIOVF register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 4 interrupt overflow flag
2 INT3 R-0/W1S 0h Writing a '1' to any of the bits will clear the corresponding MIOVF bit.
Writes of '0' are ignored. Reads always return 0.
Notes: [1] Refer to MIOVF register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 3 interrupt overflow flag
1 INT2 R-0/W1S 0h Writing a '1' to any of the bits will clear the corresponding MIOVF bit.
Writes of '0' are ignored. Reads always return 0.
Notes: [1] Refer to MIOVF register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 2 interrupt overflow flag
0 INT1 R-0/W1S 0h Writing a '1' to any of the bits will clear the corresponding MIOVF bit.
Writes of '0' are ignored. Reads always return 0.
Notes: [1] Refer to MIOVF register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 1 interrupt overflow flag

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6.8.2.15 MIER Register (Offset = 25h) [Reset = 0000h]

MIER is shown in Figure 6-16 and described in Table 6-38.
Return to the Summary Table.
Setting the bits in the interrupt enable register (MIER) allow an incoming interrupt or main CPU software to
start the corresponding CLA task. Writing a 0 will block the task, but the interrupt request will still be
latched in the flag register (MIFLG). Setting the MIER register bit to 0 while the corresponding task is
executing will have no effect on the task. The task will continue to run until it hits the MSTOP instruction.
When a soft reset is issued, the MIER bits are cleared. There should always be at least a 1 SYSCLKOUT
delay between issuing the soft reset and reconfiguring the MIER bits.
Figure 6-16. MIER Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
INT8 INT7 INT6 INT5 INT4 INT3 INT2 INT1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 6-38. MIER Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R 0h Reserved
7 INT8 R/W 0h Setting any of the bits to '1' enables the corresponding interrupt
from triggering a corresponding CLA task. Writing a '0' blocks the
interrupt, but the interrupt can still be latched by the MIFR register.
When an interrupt is enabled and the corresponding MIFR bit is
set to '1', the CLA will start executing the corresponding task and
automatically clear the corresponding MIFR bit.
Interrupts are be serviced in normal priority order.
Notes: [1] If a task is currently executing and the corresponding
MIER bit is cleared to '0', it will have no effect on the task. The task
will run until it hits the STOP instruction.
Reset type: SYSRSn
0h (R/W) = TASK_INT_DISABLE
Task 8 interrupt is disabled (default)
1h (R/W) = TASK_INT_ENABLE
Task 8 interrupt is enabled
6 INT7 R/W 0h Setting any of the bits to '1' enables the corresponding interrupt
from triggering a corresponding CLA task. Writing a '0' blocks the
interrupt, but the interrupt can still be latched by the MIFR register.
When an interrupt is enabled and the corresponding MIFR bit is
set to '1', the CLA will start executing the corresponding task and
automatically clear the corresponding MIFR bit.
Interrupts are be serviced in normal priority order.
Notes: [1] If a task is currently executing and the corresponding
MIER bit is cleared to '0', it will have no effect on the task. The task
will run until it hits the STOP instruction.
Reset type: SYSRSn
0h (R/W) = TASK_INT_DISABLE
Task 7 interrupt is disabled (default)
1h (R/W) = TASK_INT_ENABLE
Task 7 interrupt is enabled

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Table 6-38. MIER Register Field Descriptions (continued)

Bit Field Type Reset Description
5 INT6 R/W 0h Setting any of the bits to '1' enables the corresponding interrupt
from triggering a corresponding CLA task. Writing a '0' blocks the
interrupt, but the interrupt can still be latched by the MIFR register.
When an interrupt is enabled and the corresponding MIFR bit is
set to '1', the CLA will start executing the corresponding task and
automatically clear the corresponding MIFR bit.
Interrupts are be serviced in normal priority order.
Notes: [1] If a task is currently executing and the corresponding
MIER bit is cleared to '0', it will have no effect on the task. The task
will run until it hits the STOP instruction.
Reset type: SYSRSn
0h (R/W) = TASK_INT_DISABLE
Task 6 interrupt is disabled (default)
1h (R/W) = TASK_INT_ENABLE
Task 6 interrupt is enabled
4 INT5 R/W 0h Setting any of the bits to '1' enables the corresponding interrupt
from triggering a corresponding CLA task. Writing a '0' blocks the
interrupt, but the interrupt can still be latched by the MIFR register.
When an interrupt is enabled and the corresponding MIFR bit is
set to '1', the CLA will start executing the corresponding task and
automatically clear the corresponding MIFR bit.
Interrupts are be serviced in normal priority order.
Notes: [1] If a task is currently executing and the corresponding
MIER bit is cleared to '0', it will have no effect on the task. The task
will run until it hits the STOP instruction.
Reset type: SYSRSn
0h (R/W) = TASK_INT_DISABLE
Task 5 interrupt is disabled (default)
1h (R/W) = TASK_INT_ENABLE
Task 5 interrupt is enabled
3 INT4 R/W 0h Setting any of the bits to '1' enables the corresponding interrupt
from triggering a corresponding CLA task. Writing a '0' blocks the
interrupt, but the interrupt can still be latched by the MIFR register.
When an interrupt is enabled and the corresponding MIFR bit is
set to '1', the CLA will start executing the corresponding task and
automatically clear the corresponding MIFR bit.
Interrupts are be serviced in normal priority order.
Notes: [1] If a task is currently executing and the corresponding
MIER bit is cleared to '0', it will have no effect on the task. The task
will run until it hits the STOP instruction.
Reset type: SYSRSn
0h (R/W) = TASK_INT_DISABLE
Task 4 interrupt is disabled (default)
1h (R/W) = TASK_INT_ENABLE
Task 4 interrupt is enabled
2 INT3 R/W 0h Setting any of the bits to '1' enables the corresponding interrupt
from triggering a corresponding CLA task. Writing a '0' blocks the
interrupt, but the interrupt can still be latched by the MIFR register.
When an interrupt is enabled and the corresponding MIFR bit is
set to '1', the CLA will start executing the corresponding task and
automatically clear the corresponding MIFR bit.
Interrupts are be serviced in normal priority order.
Notes: [1] If a task is currently executing and the corresponding
MIER bit is cleared to '0', it will have no effect on the task. The task
will run until it hits the STOP instruction.
Reset type: SYSRSn
0h (R/W) = TASK_INT_DISABLE
Task 3 interrupt is disabled (default)
1h (R/W) = TASK_INT_ENABLE
Task 3 interrupt is enabled

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Table 6-38. MIER Register Field Descriptions (continued)

Bit Field Type Reset Description
1 INT2 R/W 0h Setting any of the bits to '1' enables the corresponding interrupt
from triggering a corresponding CLA task. Writing a '0' blocks the
interrupt, but the interrupt can still be latched by the MIFR register.
When an interrupt is enabled and the corresponding MIFR bit is
set to '1', the CLA will start executing the corresponding task and
automatically clear the corresponding MIFR bit.
Interrupts are be serviced in normal priority order.
Notes: [1] If a task is currently executing and the corresponding
MIER bit is cleared to '0', it will have no effect on the task. The task
will run until it hits the STOP instruction.
Reset type: SYSRSn
0h (R/W) = TASK_INT_DISABLE
Task 2 interrupt is disabled (default)
1h (R/W) = TASK_INT_ENABLE
Task 2 interrupt is enabled
0 INT1 R/W 0h Setting any of the bits to '1' enables the corresponding interrupt
from triggering a corresponding CLA task. Writing a '0' blocks the
interrupt, but the interrupt can still be latched by the MIFR register.
When an interrupt is enabled and the corresponding MIFR bit is
set to '1', the CLA will start executing the corresponding task and
automatically clear the corresponding MIFR bit.
Interrupts are be serviced in normal priority order.
Notes: [1] If a task is currently executing and the corresponding
MIER bit is cleared to '0', it will have no effect on the task. The task
will run until it hits the STOP instruction.
Reset type: SYSRSn
0h (R/W) = TASK_INT_DISABLE
Task 1 interrupt is disabled (default)
1h (R/W) = TASK_INT_ENABLE
Task 1 interrupt is enabled

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6.8.2.16 MIRUN Register (Offset = 26h) [Reset = 0000h]

MIRUN is shown in Figure 6-17 and described in Table 6-39.
Return to the Summary Table.
The interrupt run status register (MIRUN) indicates which task is currently executing. Only one MIRUN bit
will ever be set to a 1 at any given time. The bit is automatically cleared when the task competes and the
respective interrupt is fed to the peripheral interrupt expansion (PIE) block of the device. This lets the main
CPU know when a task has completed. The main CPU can stop a currently running task by writing to the
MCTL[SOFTRESET] bit. This will clear the MIRUN flag and stop the task. In this case no interrupt will be
generated to the PIE.
Figure 6-17. MIRUN Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
INT8 INT7 INT6 INT5 INT4 INT3 INT2 INT1
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 6-39. MIRUN Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R 0h Reserved
7 INT8 R 0h These bits indicate which task is currently active. Only one bit can be
set to '1' at any one time. The bit is automatically cleared to '0' when
the task completes and the respective CLAINTxn line is toggled to
indicate task completion. The CLAINTxn interrupt line can be fed to
the PIE of the CPU so the CPU knows when a task has completed.
A currently running task can be stopped by a SOFTRESET. The
RUN flag is cleared, the task is stopped, but no CLAINTxn interrupt
is generated.
Reset type: SYSRSn
0h (R/W) = Task 8 is not executing (default)
1h (R/W) = Task 8 is executing
6 INT7 R 0h These bits indicate which task is currently active. Only one bit can be
set to '1' at any one time. The bit is automatically cleared to '0' when
the task completes and the respective CLAINTxn line is toggled to
indicate task completion. The CLAINTxn interrupt line can be fed to
the PIE of the CPU so the CPU knows when a task has completed.
A currently running task can be stopped by a SOFTRESET. The
RUN flag is cleared, the task is stopped, but no CLAINTxn interrupt
is generated.
Reset type: SYSRSn
0h (R/W) = Task 7 is not executing (default)
1h (R/W) = Task 7 is executing
5 INT6 R 0h These bits indicate which task is currently active. Only one bit can be
set to '1' at any one time. The bit is automatically cleared to '0' when
the task completes and the respective CLAINTxn line is toggled to
indicate task completion. The CLAINTxn interrupt line can be fed to
the PIE of the CPU so the CPU knows when a task has completed.
A currently running task can be stopped by a SOFTRESET. The
RUN flag is cleared, the task is stopped, but no CLAINTxn interrupt
is generated.
Reset type: SYSRSn
0h (R/W) = Task 6 is not executing (default)
1h (R/W) = Task 6 is executing

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Table 6-39. MIRUN Register Field Descriptions (continued)

Bit Field Type Reset Description
4 INT5 R 0h These bits indicate which task is currently active. Only one bit can be
set to '1' at any one time. The bit is automatically cleared to '0' when
the task completes and the respective CLAINTxn line is toggled to
indicate task completion. The CLAINTxn interrupt line can be fed to
the PIE of the CPU so the CPU knows when a task has completed.
A currently running task can be stopped by a SOFTRESET. The
RUN flag is cleared, the task is stopped, but no CLAINTxn interrupt
is generated.
Reset type: SYSRSn
0h (R/W) = Task 5 is not executing (default)
1h (R/W) = Task 5 is executing
3 INT4 R 0h These bits indicate which task is currently active. Only one bit can be
set to '1' at any one time. The bit is automatically cleared to '0' when
the task completes and the respective CLAINTxn line is toggled to
indicate task completion. The CLAINTxn interrupt line can be fed to
the PIE of the CPU so the CPU knows when a task has completed.
A currently running task can be stopped by a SOFTRESET. The
RUN flag is cleared, the task is stopped, but no CLAINTxn interrupt
is generated.
Reset type: SYSRSn
0h (R/W) = Task 4 is not executing (default)
1h (R/W) = Task 4 is executing
2 INT3 R 0h These bits indicate which task is currently active. Only one bit can be
set to '1' at any one time. The bit is automatically cleared to '0' when
the task completes and the respective CLAINTxn line is toggled to
indicate task completion. The CLAINTxn interrupt line can be fed to
the PIE of the CPU so the CPU knows when a task has completed.
A currently running task can be stopped by a SOFTRESET. The
RUN flag is cleared, the task is stopped, but no CLAINTxn interrupt
is generated.
Reset type: SYSRSn
0h (R/W) = Task 3 is not executing (default)
1h (R/W) = Task 3 is executing
1 INT2 R 0h These bits indicate which task is currently active. Only one bit can be
set to '1' at any one time. The bit is automatically cleared to '0' when
the task completes and the respective CLAINTxn line is toggled to
indicate task completion. The CLAINTxn interrupt line can be fed to
the PIE of the CPU so the CPU knows when a task has completed.
A currently running task can be stopped by a SOFTRESET. The
RUN flag is cleared, the task is stopped, but no CLAINTxn interrupt
is generated.
Reset type: SYSRSn
0h (R/W) = Task 2 is not executing (default)
1h (R/W) = Task 2 is executing
0 INT1 R 0h These bits indicate which task is currently active. Only one bit can be
set to '1' at any one time. The bit is automatically cleared to '0' when
the task completes and the respective CLAINTxn line is toggled to
indicate task completion. The CLAINTxn interrupt line can be fed to
the PIE of the CPU so the CPU knows when a task has completed.
A currently running task can be stopped by a SOFTRESET. The
RUN flag is cleared, the task is stopped, but no CLAINTxn interrupt
is generated.
Reset type: SYSRSn
0h (R/W) = Task 1 is not executing (default)
1h (R/W) = Task 1 is executing

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6.8.2.17 _MPC Register (Offset = 28h) [Reset = 0000h]

_MPC is shown in Figure 6-18 and described in Table 6-40.
Return to the Summary Table.
CLA Program Counter
Figure 6-18. _MPC Register
15 14 13 12 11 10 9 8
_MPC
R-0h

7 6 5 4 3 2 1 0
_MPC
R-0h

Table 6-40. _MPC Register Field Descriptions

Bit Field Type Reset Description
15-0 _MPC R 0h Program Counter: The PC value is initialized by the appropriate
MVECTx register when an interrupt (task) is serviced.
The MPC register address 16-bits and not 32-bits. Hence the
address range of the CLA with a 16-bit MPC is 64Kx16 words or
32K CLA instructions.
Notes: [1] To be consistent with C28 core implementation, the PC
value points to the instruction in D2 stage of pipeline.
[2] After a STOP operation, and with no other task pending, the PC
will remain pointing to the STOP operation.
Reset type: SYSRSn

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6.8.2.18 _MAR0 Register (Offset = 2Ah) [Reset = 0000h]

_MAR0 is shown in Figure 6-19 and described in Table 6-41.
Return to the Summary Table.
CLA Auxiliary Register 0
Figure 6-19. _MAR0 Register
15 14 13 12 11 10 9 8
_MAR0
R-0h

7 6 5 4 3 2 1 0
_MAR0
R-0h

Table 6-41. _MAR0 Register Field Descriptions

Bit Field Type Reset Description
15-0 _MAR0 R 0h CLA Auxillary Register 0
Reset type: SYSRSn

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6.8.2.19 _MAR1 Register (Offset = 2Bh) [Reset = 0000h]

_MAR1 is shown in Figure 6-20 and described in Table 6-42.
Return to the Summary Table.
CLA Auxiliary Register 1
Figure 6-20. _MAR1 Register
15 14 13 12 11 10 9 8
_MAR1
R-0h

7 6 5 4 3 2 1 0
_MAR1
R-0h

Table 6-42. _MAR1 Register Field Descriptions

Bit Field Type Reset Description
15-0 _MAR1 R 0h CLA Auxillary Register 1
Reset type: SYSRSn

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6.8.2.20 _MSTF Register (Offset = 2Eh) [Reset = 00000000h]

_MSTF is shown in Figure 6-21 and described in Table 6-43.
Return to the Summary Table.
The CLA status register (MSTF) reflects the results of different operations. These are the basic rules for
the flags:
- Zero and negative flags are cleared or set based on:
- floating-point moves to registers
- the result of compare, minimum, maximum, negative and absolute value operations
- the integer result of operations such as MMOV16, MAND32, MOR32, MXOR32, MCMP32,
MASR32, MLSR32
- Overflow and underflow flags are set by floating-point math instructions such as multiply, add, subtract
and 1/x. These flags may also be connected to the peripheral interrupt expansion (PIE) block on your
device. This can be useful for debugging underflow and overflow conditions within an application.
Figure 6-21. _MSTF Register
31 30 29 28 27 26 25 24
RESERVED _RPC
R-0h R-0h

23 22 21 20 19 18 17 16
_RPC
R-0h

15 14 13 12 11 10 9 8
_RPC MEALLOW RESERVED RNDF32 RESERVED
R-0h R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
RESERVED TF RESERVED ZF NF LUF LVF
R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 6-43. _MSTF Register Field Descriptions

Bit Field Type Reset Description
31-28 RESERVED R 0h Reserved
27-12 _RPC R 0h Return program counter
The _RPC is used to save and restore the MPC address by the
MCCNDD and MRCNDD operations
Reset type: SYSRSn
11 MEALLOW R 0h MEALLOW Status
This bit enables and disables CLA write access to EALLOW
protected registers This is independent of the state of the EALLOW
bit in the main CPU status register This status bit can be saved and
restored by the MMOV32 STF, mem32 instruction
Reset type: SYSRSn
0h (R/W) = The CLA cannot write to EALLOW protected registers.
This bit is cleared by the CLA instruction, MEDIS.
1h (R/W) = The CLA is allowed to write to EALLOW protected
registers. This bit is set by the CLA instruction, MEALLOW.
10 RESERVED R 0h Reserved

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Table 6-43. _MSTF Register Field Descriptions (continued)

Bit Field Type Reset Description
9 RNDF32 R 0h Round 32-bit Floating-Point Mode
Use the MSETFLG and MMOV32 MSTF, mem32 instructions to
change the rounding mode
Reset type: SYSRSn
0h (R/W) = If this bit is zero, the MMPYF32, MADDF32 and
MSUBF32 instructions will round to zero (truncate).
1h (R/W) = If this bit is one, the MMPYF32, MADDF32 and
MSUBF32 instructions will round to the nearest even value.
8-7 RESERVED R 0h Reserved
6 TF R 0h Test Flag
The MTESTTF instruction can modify this flag based on the
condition tested The MSETFLG and MMOV32 MSTF, mem32
instructions can also be used to modify this flag
Reset type: SYSRSn
0h (R/W) = The condition tested with the MTESTTF instruction is
false.
1h (R/W) = The condition tested with the MTESTTF instruction is
true.
5-4 RESERVED R 0h Reserved
3 ZF R 0h Zero Flag
- Instructions that modify this flag based on the floating-point value
stored in the destination register:
MMOV32, MMOVD32, MABSF32, MNEGF32
- Instructions that modify this flag based on the floating-point result of
the operation:
MCMPF32, MMAXF32, and MMINF32
- Instructions that modify this flag based on the integer result of the
operation:
MMOV16, MAND32, MOR32, MXOR32, MCMP32, MASR32,
MLSR32 and
MLSL32
The MSETFLG and MMOV32 MSTF, mem32 instructions can also
be used to modify this flag
Reset type: SYSRSn
0h (R/W) = The value is not zero
1h (R/W) = The value is zero
2 NF R 0h Negative Flag
- Instructions that modify this flag based on the floating-point value
stored in the destination register:
MMOV32, MMOVD32, MABSF32, MNEGF32
- Instructions that modify this flag based on the floating-point result of
the operation:
MCMPF32, MMAXF32, and MMINF32
- Instructions that modify this flag based on the integer result of the
operation:
MMOV16, MAND32, MOR32, MXOR32, MCMP32, MASR32,
MLSR32 and
MLSL32
The MSETFLG and MMOV32 MSTF, mem32 instructions can also
be used to modify this flag
Reset type: SYSRSn
0h (R/W) = The value is not negative
1h (R/W) = The value is negative

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Table 6-43. _MSTF Register Field Descriptions (continued)

Bit Field Type Reset Description
1 LUF R 0h Latched Underflow Flag
The following instructions will set this flag to 1 if an underflow occurs:
MMPYF32, MADDF32,
MSUBF32, MMACF32, MEINVF32, MEISQRTF32
The MSETFLG and MMOV32 MSTF, mem32 instructions can also
be used to modify this flag
Reset type: SYSRSn
0h (R/W) = An underflow condition has not been latched
1h (R/W) = An underflow condition has been latched
0 LVF R 0h Latched Overflow Flag
The following instructions will set this flag to 1 if an overflow
occurs: MMPYF32, MADDF32, MSUBF32, MMACF32, MEINVF32,
MEISQRTF32
The MSETFLG and MMOV32 MSTF, mem32 instructions can also
be used to modify this flag
Reset type: SYSRSn
0h (R/W) = An overflow condition has not been latched
1h (R/W) = An overflow condition has been latched

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6.8.2.21 _MR0 Register (Offset = 30h) [Reset = 00000000h]

_MR0 is shown in Figure 6-22 and described in Table 6-44.
Return to the Summary Table.
CLA Floating-Point Result Register 0
Figure 6-22. _MR0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
i32
R-0h

Table 6-44. _MR0 Register Field Descriptions

Bit Field Type Reset Description
31-0 i32 R 0h CLA Result Register 0
Reset type: SYSRSn

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6.8.2.22 _MR1 Register (Offset = 34h) [Reset = 00000000h]

_MR1 is shown in Figure 6-23 and described in Table 6-45.
Return to the Summary Table.
CLA Floating-Point Result Register 1
Figure 6-23. _MR1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
i32
R-0h

Table 6-45. _MR1 Register Field Descriptions

Bit Field Type Reset Description
31-0 i32 R 0h CLA Result Register 1
Reset type: SYSRSn

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6.8.2.23 _MR2 Register (Offset = 38h) [Reset = 00000000h]

_MR2 is shown in Figure 6-24 and described in Table 6-46.
Return to the Summary Table.
CLA Floating-Point Result Register 2
Figure 6-24. _MR2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
i32
R-0h

Table 6-46. _MR2 Register Field Descriptions

Bit Field Type Reset Description
31-0 i32 R 0h CLA Result Register 2
Reset type: SYSRSn

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6.8.2.24 _MR3 Register (Offset = 3Ch) [Reset = 00000000h]

_MR3 is shown in Figure 6-25 and described in Table 6-47.
Return to the Summary Table.
CLA Floating-Point Result Register 3
Figure 6-25. _MR3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
i32
R-0h

Table 6-47. _MR3 Register Field Descriptions

Bit Field Type Reset Description
31-0 i32 R 0h CLA Result Register 3
Reset type: SYSRSn

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6.8.3 CLA_SOFTINT_REGS Registers

Table 6-48 lists the memory-mapped registers for the CLA_SOFTINT_REGS registers. All register offset
addresses not listed in Table 6-48 should be considered as reserved locations and the register contents should
not be modified.
Table 6-48. CLA_SOFTINT_REGS Registers
Offset Acronym Register Name Write Protection Section
0h SOFTINTEN CLA Software Interrupt Enable Register Go
2h SOFTINTFRC CLA Software Interrupt Force Register Go

Complex bit access types are encoded to fit into small table cells. Table 6-49 shows the codes that are used for
access types in this section.
Table 6-49. CLA_SOFTINT_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1S W Write
1S 1 to set
Reset or Default Value
-n Value after reset or the default value
Register Array Variables
i,j,k,l,m,n When these variables are used in a register name,
an offset, or an address, they refer to the value of a
register array where the register is part of a group
of repeating registers. The register groups form a
hierarchical structure and the array is represented
with a formula.
y When this variable is used in a register name, an
offset, or an address it refers to the value of a
register array.

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6.8.3.1 SOFTINTEN Register (Offset = 0h) [Reset = 0000h]

SOFTINTEN is shown in Figure 6-26 and described in Table 6-50.
Return to the Summary Table.
Enables the ability to generate CLA task interrupt from within the task, by writing to SOFTINTFRC register.
SOFTINTFRC register can only be written from CLA.
Figure 6-26. SOFTINTEN Register
15 14 13 12 11 10 9 8
RESERVED
R/W-0h

7 6 5 4 3 2 1 0
TASK8 TASK7 TASK6 TASK5 TASK4 TASK3 TASK2 TASK1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 6-50. SOFTINTEN Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R/W 0h Reserved
7 TASK8 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
6 TASK7 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
5 TASK6 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
4 TASK5 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
3 TASK4 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
2 TASK3 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
1 TASK2 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn

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Table 6-50. SOFTINTEN Register Field Descriptions (continued)

Bit Field Type Reset Description
0 TASK1 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn

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6.8.3.2 SOFTINTFRC Register (Offset = 2h) [Reset = 0000h]

SOFTINTFRC is shown in Figure 6-27 and described in Table 6-51.
Return to the Summary Table.
Writing a value of 1 in a bit will generate the corresponding task interrupt.This register is only accessible by the
CLA (not the CPU).
Figure 6-27. SOFTINTFRC Register
15 14 13 12 11 10 9 8
RESERVED
R/W-0h

7 6 5 4 3 2 1 0
TASK8 TASK7 TASK6 TASK5 TASK4 TASK3 TASK2 TASK1
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 6-51. SOFTINTFRC Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R/W 0h Reserved
7 TASK8 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
6 TASK7 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
5 TASK6 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
4 TASK5 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
3 TASK4 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
2 TASK3 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
1 TASK2 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
0 TASK1 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn

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6.8.4 CLA Registers to Driverlib Functions

Table 6-52. CLA Registers to Driverlib Functions
File Driverlib Function
MVECT1
cla.h CLA_mapTaskVector
MVECT2
- See MVECT1
MVECT3
- See MVECT1
MVECT4
- See MVECT1
MVECT5
- See MVECT1
MVECT6
- See MVECT1
MVECT7
- See MVECT1
MVECT8
- See MVECT1
MCTL
cla.h CLA_performHardReset
cla.h CLA_performSoftReset
cla.h CLA_enableIACK
cla.h CLA_disableIACK
MIFR
cla.h CLA_getPendingTaskFlag
cla.h CLA_getAllPendingTaskFlags
cla.h CLA_forceTasks
MIOVF
cla.h CLA_getTaskOverflowFlag
cla.h CLA_getAllTaskOverflowFlags
MIFRC
cla.h CLA_forceTasks
MICLR
cla.h CLA_clearTaskFlags
MICLROVF
-
MIER
cla.h CLA_enableTasks
cla.h CLA_disableTasks
MIRUN
cla.h CLA_getTaskRunStatus
cla.h CLA_getAllTaskRunStatus
MPC
-
MAR0

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Table 6-52. CLA Registers to Driverlib Functions (continued)

File Driverlib Function
-
MAR1
-
MSTF
-
MR0
-
MR1
-
MR2
-
MR3
-
SOFTINTEN
cla.h CLA_enableSoftwareInterrupt
cla.h CLA_disableSoftwareInterrupt
SOFTINTFRC
cla.h CLA_forceSoftwareInterrupt

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Interprocessor Communication (IPC) www.ti.com

Chapter 7
Interprocessor Communication (IPC)

The Interprocessor Communications (IPC) module allows communication between the two CPU subsystems.

7.1 Introduction...............................................................................................................................................................917
7.2 Message RAMs......................................................................................................................................................... 918
7.3 IPC Flags and Interrupts.......................................................................................................................................... 918
7.4 IPC Command Registers..........................................................................................................................................918
7.5 Free-Running Counter..............................................................................................................................................918
7.6 IPC Communication Protocol..................................................................................................................................919
7.7 IPC Registers............................................................................................................................................................ 920

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7.1 Introduction
This section details the IPC features that each CPU can use to request and share information. The IPC features
are:
• Message RAMs
• IPC flags and interrupts
• IPC command registers
• Flash pump semaphore
• Clock configuration semaphore
• Free-running counter
All IPC features are independent of each other, and most do not require any specific data format.
There are also two registers for boot mode and status communication. Please refer to the boot ROM chapter for
more information on these registers.
Figure 7-1 shows the design structure of the IPC module.
SET31
CLR31 ACK31
FLG31

R=0/W=1 IPCSET[31:0] SET0

R=0/W=1 IPCCLR[31:0] CLR0 ACK0 IPCACK[31:0] R=0/W=1
FLG0

Gen Int Pulse

C1TOC2IPCINT1/2/3/4
CPU2.
(on FLG 0->1) ePIE

R IPCFLG[31:0] IPCSTS[31:0] R

R/W IPCSENDCOM[31:0] C1TOC2IPCCOM[31:0] IPCRECVCOM[31:0] R

R/W IPCSENDADDR[31:0] C1TOC2IPCADDR[31:0] IPCRECVADDR[31:0] R

R/W IPCSENDDATA[31:0] C1TOC2IPCDATAW[31:0] IPCRECVDATA[31:0] R

R IPCREMOTEREPLY[31:0] C1TOC2IPCDATAR[31:0] IPCLOCALREPLY[31:0] R/W

R/W IPCBOOTMODE[31:0] R

R IPCBOOTSTS[31:0] R/W

CPU1.EmulationHalt CPU2.EmulationHalt
64-bit Free Run Counter
CPU1 PLLSYSCLK CPU2
R IPCCOUNTERH/L[31:0] R

SET31
ACK31 CLR31
FLG31

SET0 IPCSET[31:0] R=0/W=1

R=0/W=1 IPCACK[31:0] ACK0 CLR0 IPCCLR[31:0] R=0/W=1
FLG0

CPU1. C2TOC1IPCINT1/2/3/4
Gen Int Pulse
ePIE (on FLG 0->1)

R IPCSTS[31:0] IPCFLG[31:0] R

R IPCRECVCOM[31:0] C2TOC1IPCCOM[31:0] IPCSENDCOM[31:0] R/W

R IPCRECVADDR[31:0] C2TOC1IPCADDR[31:0] IPCSENDADDR[31:0] R/W

R IPCRECVDATA[31:0] C2TOC1IPCDATAW[31:0] IPCSENDDATA[31:0] R/W

R/W IPCLOCALREPLY[31:0] C2TOC1IPCDATAR[31:0] IPCREMOTEREPLY[31:0] R

Figure 7-1. IPC Module Architecture

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7.2 Message RAMs

There are two dedicated 2-kB blocks of message RAM. Each CPU and the DMA have read and write access to
one RAM and read-only access to the other RAM, as shown in Table 7-1..
Reading or writing a message RAM does not trigger any events on the remote CPU.
Table 7-1. IPC Message RAM Read/Write Access
CPU1 CPU2 CPU1 DMA CPU2 DMA
CPU1 to CPU2 (1K x 16, address 0x03FC00) R/W R R/W R
CPU2 to CPU1 (1K x 16, address 0x03F800) R R/W R R/W

7.3 IPC Flags and Interrupts

There are 32 IPC event signals in each direction between the CPU pairs. These signals can be used for
flag-based event polling. With the C28x core, four of them (IPC0 - IPC3) can be configured to generate IPC
interrupts on the remote CPU.
7.4 IPC Command Registers
The IPC command registers provide a simple and flexible way for the CPUs to exchange more complex
messages. Each CPU has eight dedicated registers; four for sending messages and four for receiving
messages. The register names were chosen to support a simple command/response protocol, but can be
used for any purpose. Only the read/write permissions are determined by hardware; the data format is entirely
software-defined.
For sending messages, each CPU has three writable registers and one read-only register. Those same registers
are accessible on the remote CPU as three read-only registers and one writable register. Table 7-2 shows the
command registers.
Table 7-2. IPC Command Registers
Local Register Name Local CPU Remote CPU Remote Register Name
IPCSENDCOM R/W R IPCRECVCOM
IPCSENDADDR R/W R IPCRECVADDR
IPCSENDDATA R/W R IPCRECVDATA
IPCREMOTEREPLY R R/W IPCLOCALREPLY

7.5 Free-Running Counter

A 64-bit free-running counter is present in the device and can be used to timestamp IPC events between
processors. The counter is clocked by PLLSYSCLK and reset by SYSRSn. The counter is implemented
as two 32-bit registers, IPCCOUNTERH and IPCCOUNTERL. When IPCCOUNTERL is read, the value of
IPCCOUNTERH is saved. A subsequent read to IPCCOUNTERH returns this saved value. Therefore, the user
must always read IPCCOUNTERL first then read IPCCOUNTERH next. This design prevents race conditions
due to IPCCOUNTERL overflowing between reads of the two registers.
The free-running counter stops only when emulation is suspended (when debugger hits a breakpoint) on all
CPUs. If any core is executing, the counter runs.

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7.6 IPC Communication Protocol

This section describes the hardware support options for IPC communication between the two CPUs. These
options can be used independently or in combination. All flag definitions and data formats are entirely user-
defined.
• The flag system supports event-based communication via interrupts and register polling.
– CPUx can raise an IPC event by writing to any of the 32 bits of the IPCSET register. This sets the
corresponding bits in the CPUx IPCFLG register and CPUy IPCSTS register.
– CPUy can signal the response to the event by setting the appropriate bit in the IPCACK register. This
clears the corresponding bits in the CPUx IPCFLG register and the CPUy IPCSTS register.
– If CPUx needs to cancel an event, CPUx can set the appropriate bit in the IPCCLR register. This has the
same effect as CPUy writing to IPCACK.
– Flags 0–3 (set using IPCSET[3:0]) fire interrupts to the remote CPU. The remote CPU must configure the
ePIE module properly to receive an IPC interrupt. Flags 4–31 (set using IPCSET[31:4]) do not produce
interrupts. Multiple flags can be set, acknowledged, and cleared simultaneously.
• The command registers support sending several distinct pieces of information and are named COM, ADDR,
DATA, and REPLY for convenience only and can hold whatever data the application needs.
– CPUx can write data to the IPCSENDCOM, IPCSENDADDR, and IPCSENDDATA registers. CPUy
receives these in the IPCRECVCOM, IPCRECVADDR, and IPCRECVDATA registers.
– CPUy can respond by writing to its IPCLOCALREPLY register. CPUx receives this data in its
ownIPCREMOTEREPLY register.
• There is an additional pair of command-like registers offered for boot-time IPC or any other convenient
use — IPCBOOTMODE and IPCBOOTSTS. Both CPUs can read these registers. CPUx can only write to
IPCBOOTMODE, and CPUy can only write to IPCBOOTSTS.
• There are two shared memories for passing large amounts of data between the CPUs. Each CPU has a
writable memory for sending data and a read-only memory for receiving data.
• Here is an example of how to use these features together. CPUx needs some data from CPUy's LS RAM.
The data is at CPUy address 0x9400 and is 0x80 16-bit words long. The protocol can be implemented like
this:
– CPUx writes 0x1 to IPCSENDCOM, defined in software to mean "copy data from address". CPUx writes
the address (0x9400) to IPCSENDADDR and the data length (0x80) to IPCSENDDATA.
– CPUx writes to IPCSET[3] and IPCSET[16]. Here, IPC flag 3 is configured to send an interrupt and
IPCSET[16] is defined in software to indicate an incoming command. CPUx begins polling for IPCFLG[3]
to go low.
– CPUy receives the interrupt. In the interrupt handler, CPUy checks IPCSTS, finds that flag 16 is set, and
runs a command processor.
– CPUy reads the command (0x1) from IPCRECVCOM, the address (0x9400) from IPCRECVADDR, and
the data length (0x80) from IPCRECVDATA. CPUy then copies the LS RAM data to an empty space in the
writable shared memory starting at offset 0x210.
– CPUy writes the shared memory address (0x210) to the IPCLOCALREPLY register. CPUy then writes to
IPCACK[16] and IPCACK[3] to clear the flags and indicate completion of the command. CPUy's work is
done.
– CPUx sees IPCFLG[3] go low. CPUx reads IPCREMOTEREPLY to get the shared memory offset of the
copied data (0x210).

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7.7 IPC Registers

This section describes the Interprocessor Communication Registers.
7.7.1 IPC Base Addresses
Table 7-3. IPC Base Addresses
Device Registers Register Name Start Address End Address
IpcRegs (CPU1) IPC_REGS_CPU1 0x0005_0000 0x0005_0023
IpcRegs (CPU2) IPC_REGS_CPU2 0x0005_0000 0x0005_0023

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7.7.2 IPC_REGS_CPU1 Registers

Table 7-4 lists the memory-mapped registers for the IPC_REGS_CPU1 registers. All register offset addresses
not listed in Table 7-4 should be considered as reserved locations and the register contents should not be
modified.
Table 7-4. IPC_REGS_CPU1 Registers
Offset Acronym Register Name Write Protection Section
0h IPCACK IPC incoming flag clear (acknowledge) register Go
2h IPCSTS IPC incoming flag status register Go
4h IPCSET IPC remote flag set register Go
6h IPCCLR IPC remote flag clear register Go
8h IPCFLG IPC remote flag status register Go
Ch IPCCOUNTERL IPC Counter Low Register Go
Eh IPCCOUNTERH IPC Counter High Register Go
10h IPCSENDCOM Local to Remote IPC Command Register Go
12h IPCSENDADDR Local to Remote IPC Address Register Go
14h IPCSENDDATA Local to Remote IPC Data Register Go
16h IPCREMOTEREPLY Remote to Local IPC Reply Data Register Go
18h IPCRECVCOM Remote to Local IPC Command Register Go
1Ah IPCRECVADDR Remote to Local IPC Address Register Go
1Ch IPCRECVDATA Remote to Local IPC Data Register Go
1Eh IPCLOCALREPLY Local to Remote IPC Reply Data Register Go
20h IPCBOOTSTS CPU2 to CPU1 IPC Boot Status Register Go
22h IPCBOOTMODE CPU1 to CPU2 IPC Boot Mode Register Go

Complex bit access types are encoded to fit into small table cells. Table 7-5 shows the codes that are used for
access types in this section.
Table 7-5. IPC_REGS_CPU1 Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1S W Write
1S 1 to set
Reset or Default Value
-n Value after reset or the default value
Register Array Variables
i,j,k,l,m,n When these variables are used in a register name,
an offset, or an address, they refer to the value of a
register array where the register is part of a group
of repeating registers. The register groups form a
hierarchical structure and the array is represented
with a formula.
y When this variable is used in a register name, an
offset, or an address it refers to the value of a
register array.

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7.7.2.1 IPCACK Register (Offset = 0h) [Reset = 00000000h]

IPCACK is shown in Figure 7-2 and described in Table 7-6.
Return to the Summary Table.
IPC incoming flag clear (acknowledge) register
Figure 7-2. IPCACK Register
31 30 29 28 27 26 25 24
IPC31 IPC30 IPC29 IPC28 IPC27 IPC26 IPC25 IPC24
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

23 22 21 20 19 18 17 16
IPC23 IPC22 IPC21 IPC20 IPC19 IPC18 IPC17 IPC16
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

15 14 13 12 11 10 9 8
IPC15 IPC14 IPC13 IPC12 IPC11 IPC10 IPC9 IPC8
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

7 6 5 4 3 2 1 0
IPC7 IPC6 IPC5 IPC4 IPC3 IPC2 IPC1 IPC0
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 7-6. IPCACK Register Field Descriptions

Bit Field Type Reset Description
31 IPC31 R-0/W1S 0h Writing 1 to this bit clears the IPC31 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn
30 IPC30 R-0/W1S 0h Writing 1 to this bit clears the IPC30 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn
29 IPC29 R-0/W1S 0h Writing 1 to this bit clears the IPC29 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn
28 IPC28 R-0/W1S 0h Writing 1 to this bit clears the IPC28 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn
27 IPC27 R-0/W1S 0h Writing 1 to this bit clears the IPC27 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn
26 IPC26 R-0/W1S 0h Writing 1 to this bit clears the IPC26 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn
25 IPC25 R-0/W1S 0h Writing 1 to this bit clears the IPC25 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

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Table 7-6. IPCACK Register Field Descriptions (continued)

Bit Field Type Reset Description
24 IPC24 R-0/W1S 0h Writing 1 to this bit clears the IPC24 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn
23 IPC23 R-0/W1S 0h Writing 1 to this bit clears the IPC23 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn
22 IPC22 R-0/W1S 0h Writing 1 to this bit clears the IPC22 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn
21 IPC21 R-0/W1S 0h Writing 1 to this bit clears the IPC21 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn
20 IPC20 R-0/W1S 0h Writing 1 to this bit clears the IPC20 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn
19 IPC19 R-0/W1S 0h Writing 1 to this bit clears the IPC19 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn
18 IPC18 R-0/W1S 0h Writing 1 to this bit clears the IPC18 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn
17 IPC17 R-0/W1S 0h Writing 1 to this bit clears the IPC17 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn
16 IPC16 R-0/W1S 0h Writing 1 to this bit clears the IPC16 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn
15 IPC15 R-0/W1S 0h Writing 1 to this bit clears the IPC15 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn
14 IPC14 R-0/W1S 0h Writing 1 to this bit clears the IPC14 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn
13 IPC13 R-0/W1S 0h Writing 1 to this bit clears the IPC13 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn
12 IPC12 R-0/W1S 0h Writing 1 to this bit clears the IPC12 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn
11 IPC11 R-0/W1S 0h Writing 1 to this bit clears the IPC11 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

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Table 7-6. IPCACK Register Field Descriptions (continued)

Bit Field Type Reset Description
10 IPC10 R-0/W1S 0h Writing 1 to this bit clears the IPC10 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn
9 IPC9 R-0/W1S 0h Writing 1 to this bit clears the IPC9 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn
8 IPC8 R-0/W1S 0h Writing 1 to this bit clears the IPC8 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn
7 IPC7 R-0/W1S 0h Writing 1 to this bit clears the IPC7 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn
6 IPC6 R-0/W1S 0h Writing 1 to this bit clears the IPC6 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn
5 IPC5 R-0/W1S 0h Writing 1 to this bit clears the IPC5 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn
4 IPC4 R-0/W1S 0h Writing 1 to this bit clears the IPC4 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn
3 IPC3 R-0/W1S 0h Writing 1 to this bit clears the IPC3 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn
2 IPC2 R-0/W1S 0h Writing 1 to this bit clears the IPC2 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn
1 IPC1 R-0/W1S 0h Writing 1 to this bit clears the IPC1 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn
0 IPC0 R-0/W1S 0h Writing 1 to this bit clears the IPC0 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

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7.7.2.2 IPCSTS Register (Offset = 2h) [Reset = 00000000h]

IPCSTS is shown in Figure 7-3 and described in Table 7-7.
Return to the Summary Table.
IPC incoming flag status register
Figure 7-3. IPCSTS Register
31 30 29 28 27 26 25 24
IPC31 IPC30 IPC29 IPC28 IPC27 IPC26 IPC25 IPC24
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

23 22 21 20 19 18 17 16
IPC23 IPC22 IPC21 IPC20 IPC19 IPC18 IPC17 IPC16
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

15 14 13 12 11 10 9 8
IPC15 IPC14 IPC13 IPC12 IPC11 IPC10 IPC9 IPC8
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
IPC7 IPC6 IPC5 IPC4 IPC3 IPC2 IPC1 IPC0
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 7-7. IPCSTS Register Field Descriptions

Bit Field Type Reset Description
31 IPC31 R 0h Indicates to the local CPU if the IPC31 event flag was set by the
remote CPU.
0: No IPC31 event was set by the remote CPU
1: An IPC31 event was set by the remote CPU
Reset type: SYSRSn
30 IPC30 R 0h Indicates to the local CPU if the IPC30 event flag was set by the
remote CPU.
0: No IPC30 event was set by the remote CPU
1: An IPC30 event was set by the remote CPU
Reset type: SYSRSn
29 IPC29 R 0h Indicates to the local CPU if the IPC29 event flag was set by the
remote CPU.
0: No IPC29 event was set by the remote CPU
1: An IPC29 event was set by the remote CPU
Reset type: SYSRSn
28 IPC28 R 0h Indicates to the local CPU if the IPC28 event flag was set by the
remote CPU.
0: No IPC28 event was set by the remote CPU
1: An IPC28 event was set by the remote CPU
Reset type: SYSRSn
27 IPC27 R 0h Indicates to the local CPU if the IPC27 event flag was set by the
remote CPU.
0: No IPC27 event was set by the remote CPU
1: An IPC27 event was set by the remote CPU
Reset type: SYSRSn
26 IPC26 R 0h Indicates to the local CPU if the IPC26 event flag was set by the
remote CPU.
0: No IPC26 event was set by the remote CPU
1: An IPC26 event was set by the remote CPU
Reset type: SYSRSn

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Table 7-7. IPCSTS Register Field Descriptions (continued)

Bit Field Type Reset Description
25 IPC25 R 0h Indicates to the local CPU if the IPC25 event flag was set by the
remote CPU.
0: No IPC25 event was set by the remote CPU
1: An IPC25 event was set by the remote CPU
Reset type: SYSRSn
24 IPC24 R 0h Indicates to the local CPU if the IPC24 event flag was set by the
remote CPU.
0: No IPC24 event was set by the remote CPU
1: An IPC24 event was set by the remote CPU
Reset type: SYSRSn
23 IPC23 R 0h Indicates to the local CPU if the IPC23 event flag was set by the
remote CPU.
0: No IPC23 event was set by the remote CPU
1: An IPC23 event was set by the remote CPU
Reset type: SYSRSn
22 IPC22 R 0h Indicates to the local CPU if the IPC22 event flag was set by the
remote CPU.
0: No IPC22 event was set by the remote CPU
1: An IPC22 event was set by the remote CPU
Reset type: SYSRSn
21 IPC21 R 0h Indicates to the local CPU if the IPC21 event flag was set by the
remote CPU.
0: No IPC21 event was set by the remote CPU
1: An IPC21 event was set by the remote CPU
Reset type: SYSRSn
20 IPC20 R 0h Indicates to the local CPU if the IPC20 event flag was set by the
remote CPU.
0: No IPC20 event was set by the remote CPU
1: An IPC20 event was set by the remote CPU
Reset type: SYSRSn
19 IPC19 R 0h Indicates to the local CPU if the IPC19 event flag was set by the
remote CPU.
0: No IPC19 event was set by the remote CPU
1: An IPC19 event was set by the remote CPU
Reset type: SYSRSn
18 IPC18 R 0h Indicates to the local CPU if the IPC18 event flag was set by the
remote CPU.
0: No IPC18 event was set by the remote CPU
1: An IPC18 event was set by the remote CPU
Reset type: SYSRSn
17 IPC17 R 0h Indicates to the local CPU if the IPC17 event flag was set by the
remote CPU.
0: No IPC17 event was set by the remote CPU
1: An IPC17 event was set by the remote CPU
Reset type: SYSRSn
16 IPC16 R 0h Indicates to the local CPU if the IPC16 event flag was set by the
remote CPU.
0: No IPC16 event was set by the remote CPU
1: An IPC16 event was set by the remote CPU
Reset type: SYSRSn
15 IPC15 R 0h Indicates to the local CPU if the IPC15 event flag was set by the
remote CPU.
0: No IPC15 event was set by the remote CPU
1: An IPC15 event was set by the remote CPU
Reset type: SYSRSn

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Table 7-7. IPCSTS Register Field Descriptions (continued)

Bit Field Type Reset Description
14 IPC14 R 0h Indicates to the local CPU if the IPC14 event flag was set by the
remote CPU.
0: No IPC14 event was set by the remote CPU
1: An IPC14 event was set by the remote CPU
Reset type: SYSRSn
13 IPC13 R 0h Indicates to the local CPU if the IPC13 event flag was set by the
remote CPU.
0: No IPC13 event was set by the remote CPU
1: An IPC13 event was set by the remote CPU
Reset type: SYSRSn
12 IPC12 R 0h Indicates to the local CPU if the IPC12 event flag was set by the
remote CPU.
0: No IPC12 event was set by the remote CPU
1: An IPC12 event was set by the remote CPU
Reset type: SYSRSn
11 IPC11 R 0h Indicates to the local CPU if the IPC11 event flag was set by the
remote CPU.
0: No IPC11 event was set by the remote CPU
1: An IPC11 event was set by the remote CPU
Reset type: SYSRSn
10 IPC10 R 0h Indicates to the local CPU if the IPC10 event flag was set by the
remote CPU.
0: No IPC10 event was set by the remote CPU
1: An IPC10 event was set by the remote CPU
Reset type: SYSRSn
9 IPC9 R 0h Indicates to the local CPU if the IPC9 event flag was set by the
remote CPU.
0: No IPC9 event was set by the remote CPU
1: An IPC9 event was set by the remote CPU
Reset type: SYSRSn
8 IPC8 R 0h Indicates to the local CPU if the IPC8 event flag was set by the
remote CPU.
0: No IPC8 event was set by the remote CPU
1: An IPC8 event was set by the remote CPU
Reset type: SYSRSn
7 IPC7 R 0h Indicates to the local CPU if the IPC7 event flag was set by the
remote CPU.
0: No IPC7 event was set by the remote CPU
1: An IPC7 event was set by the remote CPU
Reset type: SYSRSn
6 IPC6 R 0h Indicates to the local CPU if the IPC6 event flag was set by the
remote CPU.
0: No IPC6 event was set by the remote CPU
1: An IPC6 event was set by the remote CPU
Reset type: SYSRSn
5 IPC5 R 0h Indicates to the local CPU if the IPC5 event flag was set by the
remote CPU.
0: No IPC5 event was set by the remote CPU
1: An IPC5 event was set by the remote CPU
Reset type: SYSRSn
4 IPC4 R 0h Indicates to the local CPU if the IPC4 event flag was set by the
remote CPU.
0: No IPC4 event was set by the remote CPU
1: An IPC4 event was set by the remote CPU
Reset type: SYSRSn

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Table 7-7. IPCSTS Register Field Descriptions (continued)

Bit Field Type Reset Description
3 IPC3 R 0h Indicates to the local CPU if the IPC3 event flag was set by the
remote CPU.
0: No IPC3 event was set by the remote CPU
1: An IPC3 event was set by the remote CPU
Notes
[1] IPC event flags 0-3 will trigger interrupts in the receiving CPU via
the ePIE.
Reset type: SYSRSn
2 IPC2 R 0h Indicates to the local CPU if the IPC2 event flag was set by the
remote CPU.
0: No IPC2 event was set by the remote CPU
1: An IPC2 event was set by the remote CPU
Notes
[1] IPC event flags 0-3 will trigger interrupts in the receiving CPU via
the ePIE.
Reset type: SYSRSn
1 IPC1 R 0h Indicates to the local CPU if the IPC1 event flag was set by the
remote CPU.
0: No IPC1 event was set by the remote CPU
1: An IPC1 event was set by the remote CPU
Notes
[1] IPC event flags 0-3 will trigger interrupts in the receiving CPU via
the ePIE.
Reset type: SYSRSn
0 IPC0 R 0h Indicates to the local CPU if the IPC0 event flag was set by the
remote CPU.
0: No IPC0 event was set by the remote CPU
1: An IPC0 event was set by the remote CPU
Notes
[1] IPC event flags 0-3 will trigger interrupts in the receiving CPU via
the ePIE.
Reset type: SYSRSn

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7.7.2.3 IPCSET Register (Offset = 4h) [Reset = 00000000h]

IPCSET is shown in Figure 7-4 and described in Table 7-8.
Return to the Summary Table.
IPC remote flag set register
Figure 7-4. IPCSET Register
31 30 29 28 27 26 25 24
IPC31 IPC30 IPC29 IPC28 IPC27 IPC26 IPC25 IPC24
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

23 22 21 20 19 18 17 16
IPC23 IPC22 IPC21 IPC20 IPC19 IPC18 IPC17 IPC16
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

15 14 13 12 11 10 9 8
IPC15 IPC14 IPC13 IPC12 IPC11 IPC10 IPC9 IPC8
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

7 6 5 4 3 2 1 0
IPC7 IPC6 IPC5 IPC4 IPC3 IPC2 IPC1 IPC0
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 7-8. IPCSET Register Field Descriptions

Bit Field Type Reset Description
31 IPC31 R-0/W1S 0h Writing 1 to this bit sets the IPC31 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn
30 IPC30 R-0/W1S 0h Writing 1 to this bit sets the IPC30 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn
29 IPC29 R-0/W1S 0h Writing 1 to this bit sets the IPC29 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn
28 IPC28 R-0/W1S 0h Writing 1 to this bit sets the IPC28 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn
27 IPC27 R-0/W1S 0h Writing 1 to this bit sets the IPC27 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn
26 IPC26 R-0/W1S 0h Writing 1 to this bit sets the IPC26 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn
25 IPC25 R-0/W1S 0h Writing 1 to this bit sets the IPC25 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn
24 IPC24 R-0/W1S 0h Writing 1 to this bit sets the IPC24 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn
23 IPC23 R-0/W1S 0h Writing 1 to this bit sets the IPC23 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn
22 IPC22 R-0/W1S 0h Writing 1 to this bit sets the IPC22 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn

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Table 7-8. IPCSET Register Field Descriptions (continued)

Bit Field Type Reset Description
21 IPC21 R-0/W1S 0h Writing 1 to this bit sets the IPC21 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn
20 IPC20 R-0/W1S 0h Writing 1 to this bit sets the IPC20 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn
19 IPC19 R-0/W1S 0h Writing 1 to this bit sets the IPC19 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn
18 IPC18 R-0/W1S 0h Writing 1 to this bit sets the IPC18 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn
17 IPC17 R-0/W1S 0h Writing 1 to this bit sets the IPC17 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn
16 IPC16 R-0/W1S 0h Writing 1 to this bit sets the IPC16 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn
15 IPC15 R-0/W1S 0h Writing 1 to this bit sets the IPC15 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn
14 IPC14 R-0/W1S 0h Writing 1 to this bit sets the IPC14 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn
13 IPC13 R-0/W1S 0h Writing 1 to this bit sets the IPC13 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn
12 IPC12 R-0/W1S 0h Writing 1 to this bit sets the IPC12 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn
11 IPC11 R-0/W1S 0h Writing 1 to this bit sets the IPC11 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn
10 IPC10 R-0/W1S 0h Writing 1 to this bit sets the IPC10 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn
9 IPC9 R-0/W1S 0h Writing 1 to this bit sets the IPC9 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn
8 IPC8 R-0/W1S 0h Writing 1 to this bit sets the IPC8 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn
7 IPC7 R-0/W1S 0h Writing 1 to this bit sets the IPC7 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn
6 IPC6 R-0/W1S 0h Writing 1 to this bit sets the IPC6 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn
5 IPC5 R-0/W1S 0h Writing 1 to this bit sets the IPC5 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn

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Table 7-8. IPCSET Register Field Descriptions (continued)

Bit Field Type Reset Description
4 IPC4 R-0/W1S 0h Writing 1 to this bit sets the IPC4 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn
3 IPC3 R-0/W1S 0h Writing 1 to this bit sets the IPC3 event flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] IPC event flags 0-3 will trigger interrupts in the receiving CPU via
the ePIE.
Reset type: SYSRSn
2 IPC2 R-0/W1S 0h Writing 1 to this bit sets the IPC2 event flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] IPC event flags 0-3 will trigger interrupts in the receiving CPU via
the ePIE.
Reset type: SYSRSn
1 IPC1 R-0/W1S 0h Writing 1 to this bit sets the IPC1 event flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] IPC event flags 0-3 will trigger interrupts in the receiving CPU via
the ePIE.
Reset type: SYSRSn
0 IPC0 R-0/W1S 0h Writing 1 to this bit sets the IPC0 event flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] IPC event flags 0-3 will trigger interrupts in the receiving CPU via
the ePIE.
Reset type: SYSRSn

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7.7.2.4 IPCCLR Register (Offset = 6h) [Reset = 00000000h]

IPCCLR is shown in Figure 7-5 and described in Table 7-9.
Return to the Summary Table.
IPC remote flag clear register
Figure 7-5. IPCCLR Register
31 30 29 28 27 26 25 24
IPC31 IPC30 IPC29 IPC28 IPC27 IPC26 IPC25 IPC24
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

23 22 21 20 19 18 17 16
IPC23 IPC22 IPC21 IPC20 IPC19 IPC18 IPC17 IPC16
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

15 14 13 12 11 10 9 8
IPC15 IPC14 IPC13 IPC12 IPC11 IPC10 IPC9 IPC8
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

7 6 5 4 3 2 1 0
IPC7 IPC6 IPC5 IPC4 IPC3 IPC2 IPC1 IPC0
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 7-9. IPCCLR Register Field Descriptions

Bit Field Type Reset Description
31 IPC31 R-0/W1S 0h Writing 1 to this bit clears the IPC31 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn
30 IPC30 R-0/W1S 0h Writing 1 to this bit clears the IPC30 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn
29 IPC29 R-0/W1S 0h Writing 1 to this bit clears the IPC29 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn
28 IPC28 R-0/W1S 0h Writing 1 to this bit clears the IPC28 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn

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Table 7-9. IPCCLR Register Field Descriptions (continued)

Bit Field Type Reset Description
27 IPC27 R-0/W1S 0h Writing 1 to this bit clears the IPC27 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn
26 IPC26 R-0/W1S 0h Writing 1 to this bit clears the IPC26 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn
25 IPC25 R-0/W1S 0h Writing 1 to this bit clears the IPC25 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn
24 IPC24 R-0/W1S 0h Writing 1 to this bit clears the IPC24 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn
23 IPC23 R-0/W1S 0h Writing 1 to this bit clears the IPC23 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn
22 IPC22 R-0/W1S 0h Writing 1 to this bit clears the IPC22 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn
21 IPC21 R-0/W1S 0h Writing 1 to this bit clears the IPC21 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn
20 IPC20 R-0/W1S 0h Writing 1 to this bit clears the IPC20 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn

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Table 7-9. IPCCLR Register Field Descriptions (continued)

Bit Field Type Reset Description
19 IPC19 R-0/W1S 0h Writing 1 to this bit clears the IPC19 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn
18 IPC18 R-0/W1S 0h Writing 1 to this bit clears the IPC18 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn
17 IPC17 R-0/W1S 0h Writing 1 to this bit clears the IPC17 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn
16 IPC16 R-0/W1S 0h Writing 1 to this bit clears the IPC16 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn
15 IPC15 R-0/W1S 0h Writing 1 to this bit clears the IPC15 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn
14 IPC14 R-0/W1S 0h Writing 1 to this bit clears the IPC14 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn
13 IPC13 R-0/W1S 0h Writing 1 to this bit clears the IPC13 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn
12 IPC12 R-0/W1S 0h Writing 1 to this bit clears the IPC12 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn

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Table 7-9. IPCCLR Register Field Descriptions (continued)

Bit Field Type Reset Description
11 IPC11 R-0/W1S 0h Writing 1 to this bit clears the IPC11 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn
10 IPC10 R-0/W1S 0h Writing 1 to this bit clears the IPC10 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn
9 IPC9 R-0/W1S 0h Writing 1 to this bit clears the IPC9 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn
8 IPC8 R-0/W1S 0h Writing 1 to this bit clears the IPC8 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn
7 IPC7 R-0/W1S 0h Writing 1 to this bit clears the IPC7 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn
6 IPC6 R-0/W1S 0h Writing 1 to this bit clears the IPC6 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn
5 IPC5 R-0/W1S 0h Writing 1 to this bit clears the IPC5 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn
4 IPC4 R-0/W1S 0h Writing 1 to this bit clears the IPC4 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn

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Table 7-9. IPCCLR Register Field Descriptions (continued)

Bit Field Type Reset Description
3 IPC3 R-0/W1S 0h Writing 1 to this bit clears the IPC3 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn
2 IPC2 R-0/W1S 0h Writing 1 to this bit clears the IPC2 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn
1 IPC1 R-0/W1S 0h Writing 1 to this bit clears the IPC1 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn
0 IPC0 R-0/W1S 0h Writing 1 to this bit clears the IPC0 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn

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7.7.2.5 IPCFLG Register (Offset = 8h) [Reset = 00000000h]

IPCFLG is shown in Figure 7-6 and described in Table 7-10.
Return to the Summary Table.
IPC remote flag status register
Figure 7-6. IPCFLG Register
31 30 29 28 27 26 25 24
IPC31 IPC30 IPC29 IPC28 IPC27 IPC26 IPC25 IPC24
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

23 22 21 20 19 18 17 16
IPC23 IPC22 IPC21 IPC20 IPC19 IPC18 IPC17 IPC16
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

15 14 13 12 11 10 9 8
IPC15 IPC14 IPC13 IPC12 IPC11 IPC10 IPC9 IPC8
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
IPC7 IPC6 IPC5 IPC4 IPC3 IPC2 IPC1 IPC0
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 7-10. IPCFLG Register Field Descriptions

Bit Field Type Reset Description
31 IPC31 R 0h Indicates to the local CPU whether the remote IPC31 event flag is
set.
0: The remote IPC31 event flag is not set
1: The remote IPC31 event flag is set
Reset type: SYSRSn
30 IPC30 R 0h Indicates to the local CPU whether the remote IPC30 event flag is
set.
0: The remote IPC30 event flag is not set
1: The remote IPC30 event flag is set
Reset type: SYSRSn
29 IPC29 R 0h Indicates to the local CPU whether the remote IPC29 event flag is
set.
0: The remote IPC29 event flag is not set
1: The remote IPC29 event flag is set
Reset type: SYSRSn
28 IPC28 R 0h Indicates to the local CPU whether the remote IPC28 event flag is
set.
0: The remote IPC28 event flag is not set
1: The remote IPC28 event flag is set
Reset type: SYSRSn
27 IPC27 R 0h Indicates to the local CPU whether the remote IPC27 event flag is
set.
0: The remote IPC27 event flag is not set
1: The remote IPC27 event flag is set
Reset type: SYSRSn
26 IPC26 R 0h Indicates to the local CPU whether the remote IPC26 event flag is
set.
0: The remote IPC26 event flag is not set
1: The remote IPC26 event flag is set
Reset type: SYSRSn

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Table 7-10. IPCFLG Register Field Descriptions (continued)

Bit Field Type Reset Description
25 IPC25 R 0h Indicates to the local CPU whether the remote IPC25 event flag is
set.
0: The remote IPC25 event flag is not set
1: The remote IPC25 event flag is set
Reset type: SYSRSn
24 IPC24 R 0h Indicates to the local CPU whether the remote IPC24 event flag is
set.
0: The remote IPC24 event flag is not set
1: The remote IPC24 event flag is set
Reset type: SYSRSn
23 IPC23 R 0h Indicates to the local CPU whether the remote IPC23 event flag is
set.
0: The remote IPC23 event flag is not set
1: The remote IPC23 event flag is set
Reset type: SYSRSn
22 IPC22 R 0h Indicates to the local CPU whether the remote IPC22 event flag is
set.
0: The remote IPC22 event flag is not set
1: The remote IPC22 event flag is set
Reset type: SYSRSn
21 IPC21 R 0h Indicates to the local CPU whether the remote IPC21 event flag is
set.
0: The remote IPC21 event flag is not set
1: The remote IPC21 event flag is set
Reset type: SYSRSn
20 IPC20 R 0h Indicates to the local CPU whether the remote IPC20 event flag is
set.
0: The remote IPC20 event flag is not set
1: The remote IPC20 event flag is set
Reset type: SYSRSn
19 IPC19 R 0h Indicates to the local CPU whether the remote IPC19 event flag is
set.
0: The remote IPC19 event flag is not set
1: The remote IPC19 event flag is set
Reset type: SYSRSn
18 IPC18 R 0h Indicates to the local CPU whether the remote IPC18 event flag is
set.
0: The remote IPC18 event flag is not set
1: The remote IPC18 event flag is set
Reset type: SYSRSn
17 IPC17 R 0h Indicates to the local CPU whether the remote IPC17 event flag is
set.
0: The remote IPC17 event flag is not set
1: The remote IPC17 event flag is set
Reset type: SYSRSn
16 IPC16 R 0h Indicates to the local CPU whether the remote IPC16 event flag is
set.
0: The remote IPC16 event flag is not set
1: The remote IPC16 event flag is set
Reset type: SYSRSn
15 IPC15 R 0h Indicates to the local CPU whether the remote IPC15 event flag is
set.
0: The remote IPC15 event flag is not set
1: The remote IPC15 event flag is set
Reset type: SYSRSn

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Table 7-10. IPCFLG Register Field Descriptions (continued)

Bit Field Type Reset Description
14 IPC14 R 0h Indicates to the local CPU whether the remote IPC14 event flag is
set.
0: The remote IPC14 event flag is not set
1: The remote IPC14 event flag is set
Reset type: SYSRSn
13 IPC13 R 0h Indicates to the local CPU whether the remote IPC13 event flag is
set.
0: The remote IPC13 event flag is not set
1: The remote IPC13 event flag is set
Reset type: SYSRSn
12 IPC12 R 0h Indicates to the local CPU whether the remote IPC12 event flag is
set.
0: The remote IPC12 event flag is not set
1: The remote IPC12 event flag is set
Reset type: SYSRSn
11 IPC11 R 0h Indicates to the local CPU whether the remote IPC11 event flag is
set.
0: The remote IPC11 event flag is not set
1: The remote IPC11 event flag is set
Reset type: SYSRSn
10 IPC10 R 0h Indicates to the local CPU whether the remote IPC10 event flag is
set.
0: The remote IPC10 event flag is not set
1: The remote IPC10 event flag is set
Reset type: SYSRSn
9 IPC9 R 0h Indicates to the local CPU whether the remote IPC9 event flag is set.
0: The remote IPC9 event flag is not set
1: The remote IPC9 event flag is set
Reset type: SYSRSn
8 IPC8 R 0h Indicates to the local CPU whether the remote IPC8 event flag is set.
0: The remote IPC8 event flag is not set
1: The remote IPC8 event flag is set
Reset type: SYSRSn
7 IPC7 R 0h Indicates to the local CPU whether the remote IPC7 event flag is set.
0: The remote IPC7 event flag is not set
1: The remote IPC7 event flag is set
Reset type: SYSRSn
6 IPC6 R 0h Indicates to the local CPU whether the remote IPC6 event flag is set.
0: The remote IPC6 event flag is not set
1: The remote IPC6 event flag is set
Reset type: SYSRSn
5 IPC5 R 0h Indicates to the local CPU whether the remote IPC5 event flag is set.
0: The remote IPC5 event flag is not set
1: The remote IPC5 event flag is set
Reset type: SYSRSn
4 IPC4 R 0h Indicates to the local CPU whether the remote IPC4 event flag is set.
0: The remote IPC4 event flag is not set
1: The remote IPC4 event flag is set
Reset type: SYSRSn
3 IPC3 R 0h Indicates to the local CPU whether the remote IPC3 event flag is set.
0: The remote IPC3 event flag is not set
1: The remote IPC3 event flag is set
Notes:
[1] IPC event flags 0-3 will trigger interrupts in the receiving CPU via
the ePIE.
Reset type: SYSRSn

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Table 7-10. IPCFLG Register Field Descriptions (continued)

Bit Field Type Reset Description
2 IPC2 R 0h Indicates to the local CPU whether the remote IPC2 event flag is set.
0: The remote IPC2 event flag is not set
1: The remote IPC2 event flag is set
Notes:
[1] IPC event flags 0-3 will trigger interrupts in the receiving CPU via
the ePIE.
Reset type: SYSRSn
1 IPC1 R 0h Indicates to the local CPU whether the remote IPC1 event flag is set.
0: The remote IPC1 event flag is not set
1: The remote IPC1 event flag is set
Notes:
[1] IPC event flags 0-3 will trigger interrupts in the receiving CPU via
the ePIE.
Reset type: SYSRSn
0 IPC0 R 0h Indicates to the local CPU whether the remote IPC0 event flag is set.
0: The remote IPC0 event flag is not set
1: The remote IPC0 event flag is set
Notes:
[1] IPC event flags 0-3 will trigger interrupts in the receiving CPU via
the ePIE.
Reset type: SYSRSn

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7.7.2.6 IPCCOUNTERL Register (Offset = Ch) [Reset = 00000000h]

IPCCOUNTERL is shown in Figure 7-7 and described in Table 7-11.
Return to the Summary Table.
IPC Counter Low Register
Figure 7-7. IPCCOUNTERL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COUNT
R-0h

Table 7-11. IPCCOUNTERL Register Field Descriptions

Bit Field Type Reset Description
31-0 COUNT R 0h This is the lower 32-bits of free running 64 bit timestamp counter
clocked by the PLLSYSCLK.
Reset type: CPU1.SYSRSn

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7.7.2.7 IPCCOUNTERH Register (Offset = Eh) [Reset = 00000000h]

IPCCOUNTERH is shown in Figure 7-8 and described in Table 7-12.
Return to the Summary Table.
IPC Counter High Register
Figure 7-8. IPCCOUNTERH Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COUNT
R-0h

Table 7-12. IPCCOUNTERH Register Field Descriptions

Bit Field Type Reset Description
31-0 COUNT R 0h This is the upper 32-bits of free running 64 bit timestamp counter
clocked by the PLLSYSCLK.
Reset type: CPU1.SYSRSn

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7.7.2.8 IPCSENDCOM Register (Offset = 10h) [Reset = 00000000h]

IPCSENDCOM is shown in Figure 7-9 and described in Table 7-13.
Return to the Summary Table.
Local to Remote IPC Command Register
Figure 7-9. IPCSENDCOM Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMMAND
R/W-0h

Table 7-13. IPCSENDCOM Register Field Descriptions

Bit Field Type Reset Description
31-0 COMMAND R/W 0h This is a general purpose register used to send software-defined
commands to the remote CPU. It can only be written by the local
CPU.
Notes
[1] The local CPU's IPCSENDCOM is the same physical register
as the remote CPU's IPCRECVCOM, and is located at the same
address in both CPUs.
Reset type: SYSRSn

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7.7.2.9 IPCSENDADDR Register (Offset = 12h) [Reset = 00000000h]

IPCSENDADDR is shown in Figure 7-10 and described in Table 7-14.
Return to the Summary Table.
Local to Remote IPC Address Register
Figure 7-10. IPCSENDADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDRESS
R/W-0h

Table 7-14. IPCSENDADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 ADDRESS R/W 0h This is a general purpose register used to send software-defined
addresses to the remote CPU. It can only be written by the local
CPU.
Notes
[1] The local CPU's IPCSENDADDR is the same physical register
as the remote CPU's IPCRECVDATA, and is located at the same
address in both CPUs.
Reset type: SYSRSn

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7.7.2.10 IPCSENDDATA Register (Offset = 14h) [Reset = 00000000h]

IPCSENDDATA is shown in Figure 7-11 and described in Table 7-15.
Return to the Summary Table.
Local to Remote IPC Data Register
Figure 7-11. IPCSENDDATA Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
R/W-0h

Table 7-15. IPCSENDDATA Register Field Descriptions

Bit Field Type Reset Description
31-0 WDATA R/W 0h This is a general purpose register used to send software-defined
data to the remote CPU. It can only be written by the local CPU.
Notes
[1] The local CPU's IPCSENDDATA is the same physical register
as the remote CPU's IPCRECVDATA, and is located at the same
address in both CPUs.
Reset type: SYSRSn

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7.7.2.11 IPCREMOTEREPLY Register (Offset = 16h) [Reset = 00000000h]

IPCREMOTEREPLY is shown in Figure 7-12 and described in Table 7-16.
Return to the Summary Table.
Remote to Local IPC Reply Data Register
Figure 7-12. IPCREMOTEREPLY Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
R-0h

Table 7-16. IPCREMOTEREPLY Register Field Descriptions

Bit Field Type Reset Description
31-0 RDATA R 0h This is a general purpose register used to receive software-defined
data from the remote CPU's response to a command. It can only be
written by the remote CPU.
Notes
[1] The local CPU's IPCREMOTEREPLY is the same physical
register as the remote CPU's IPCLOCALREPLY, and is located at
the same address in both CPUs.
[2] This register is reset by a SYRSn of the remote CPU
Reset type: CPUx.SYSRSn

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7.7.2.12 IPCRECVCOM Register (Offset = 18h) [Reset = 00000000h]

IPCRECVCOM is shown in Figure 7-13 and described in Table 7-17.
Return to the Summary Table.
Remote to Local IPC Command Register
Figure 7-13. IPCRECVCOM Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMMAND
R-0h

Table 7-17. IPCRECVCOM Register Field Descriptions

Bit Field Type Reset Description
31-0 COMMAND R 0h This is a general purpose register used to receive software-defined
commands from the remote CPU. It can only be written by the
remote CPU.
Notes
[1] The local CPU's IPCRECVCOM is the same physical register
as the remote CPU's IPCSENDCOM, and is located at the same
address in both CPUs.
[2] This register is reset by a SYRSn of the remote CPU
Reset type: CPUx.SYSRSn

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7.7.2.13 IPCRECVADDR Register (Offset = 1Ah) [Reset = 00000000h]

IPCRECVADDR is shown in Figure 7-14 and described in Table 7-18.
Return to the Summary Table.
Remote to Local IPC Address Register
Figure 7-14. IPCRECVADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDRESS
R-0h

Table 7-18. IPCRECVADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 ADDRESS R 0h This is a general purpose register used to receive software-defined
addresses from the remote CPU. It can only be written by the remote
CPU.
Notes
[1] The local CPU's IPCRECVADDR is the same physical register
as the remote CPU's IPCSENDADDR, and is located at the same
address in both CPUs.
[2] This register is reset by a SYRSn of the remote CPU
Reset type: CPUx.SYSRSn

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7.7.2.14 IPCRECVDATA Register (Offset = 1Ch) [Reset = 00000000h]

IPCRECVDATA is shown in Figure 7-15 and described in Table 7-19.
Return to the Summary Table.
Remote to Local IPC Data Register
Figure 7-15. IPCRECVDATA Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
R-0h

Table 7-19. IPCRECVDATA Register Field Descriptions

Bit Field Type Reset Description
31-0 WDATA R 0h This is a general purpose register used to receive software-defined
data from the remote CPU. It can only be written by the remote CPU.
Notes
[1] The local CPU's IPCRECVDATA is the same physical register
as the remote CPU's IPCSENDDATA, and is located at the same
address in both CPUs.
[2] This register is reset by a SYRSn of the remote CPU
Reset type: CPUx.SYSRSn

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7.7.2.15 IPCLOCALREPLY Register (Offset = 1Eh) [Reset = 00000000h]

IPCLOCALREPLY is shown in Figure 7-16 and described in Table 7-20.
Return to the Summary Table.
Local to Remote IPC Reply Data Register
Figure 7-16. IPCLOCALREPLY Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
R/W-0h

Table 7-20. IPCLOCALREPLY Register Field Descriptions

Bit Field Type Reset Description
31-0 RDATA R/W 0h This is a general purpose register used to send software-defined
data to the remote CPU in response to a command. It can only be
written by the local CPU.
Notes
[1] The local CPU's IPCLOCALREPLY is the same physical register
as the remote CPU's IPCREMOTEREPLY, and is located at the
same address in both CPUs.
Reset type: SYSRSn

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7.7.2.16 IPCBOOTSTS Register (Offset = 20h) [Reset = 00000000h]

IPCBOOTSTS is shown in Figure 7-17 and described in Table 7-21.
Return to the Summary Table.
CPU2 to CPU1 IPC Boot Status Register
Figure 7-17. IPCBOOTSTS Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOOTSTS
R/W-0h

Table 7-21. IPCBOOTSTS Register Field Descriptions

Bit Field Type Reset Description
31-0 BOOTSTS R/W 0h This register is used by CPU2 to pass the boot Status to CPU1. The
data format is software-defined. It can only be written by CPU2.
Reset type: CPU2.SYSRSn

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7.7.2.17 IPCBOOTMODE Register (Offset = 22h) [Reset = 00000000h]

IPCBOOTMODE is shown in Figure 7-18 and described in Table 7-22.
Return to the Summary Table.
CPU1 to CPU2 IPC Boot Mode Register
Figure 7-18. IPCBOOTMODE Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOOTMODE
R/W-0h

Table 7-22. IPCBOOTMODE Register Field Descriptions

Bit Field Type Reset Description
31-0 BOOTMODE R/W 0h This register is used by CPU1 to pass a boot mode information to
CPU2. The data format is software-defined. It can only be written by
CPU1.
Reset type: CPU1.SYSRSn

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7.7.3 IPC_REGS_CPU2 Registers

Table 7-23 lists the memory-mapped registers for the IPC_REGS_CPU2 registers. All register offset addresses
not listed in Table 7-23 should be considered as reserved locations and the register contents should not be
modified.
Table 7-23. IPC_REGS_CPU2 Registers
Offset Acronym Register Name Write Protection Section
0h IPCACK IPC incoming flag clear (acknowledge) register Go
2h IPCSTS IPC incoming flag status register Go
4h IPCSET IPC remote flag set register Go
6h IPCCLR IPC remote flag clear register Go
8h IPCFLG IPC remote flag status register Go
Ch IPCCOUNTERL IPC Counter Low Register Go
Eh IPCCOUNTERH IPC Counter High Register Go
10h IPCRECVCOM Remote to Local IPC Command Register Go
12h IPCRECVADDR Remote to Local IPC Address Register Go
14h IPCRECVDATA Remote to Local IPC Data Register Go
16h IPCLOCALREPLY Local to Remote IPC Reply Data Register Go
18h IPCSENDCOM Local to Remote IPC Command Register Go
1Ah IPCSENDADDR Local to Remote IPC Address Register Go
1Ch IPCSENDDATA Local to Remote IPC Data Register Go
1Eh IPCREMOTEREPLY Remote to Local IPC Reply Data Register Go
20h IPCBOOTSTS CPU2 to CPU1 IPC Boot Status Register Go
22h IPCBOOTMODE CPU1 to CPU2 IPC Boot Mode Register Go

Complex bit access types are encoded to fit into small table cells. Table 7-24 shows the codes that are used for
access types in this section.
Table 7-24. IPC_REGS_CPU2 Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1S W Write
1S 1 to set
Reset or Default Value
-n Value after reset or the default value
Register Array Variables
i,j,k,l,m,n When these variables are used in a register name,
an offset, or an address, they refer to the value of a
register array where the register is part of a group
of repeating registers. The register groups form a
hierarchical structure and the array is represented
with a formula.
y When this variable is used in a register name, an
offset, or an address it refers to the value of a
register array.

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7.7.3.1 IPCACK Register (Offset = 0h) [Reset = 00000000h]

IPCACK is shown in Figure 7-19 and described in Table 7-25.
Return to the Summary Table.
IPC incoming flag clear (acknowledge) register
Figure 7-19. IPCACK Register
31 30 29 28 27 26 25 24
IPC31 IPC30 IPC29 IPC28 IPC27 IPC26 IPC25 IPC24
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

23 22 21 20 19 18 17 16
IPC23 IPC22 IPC21 IPC20 IPC19 IPC18 IPC17 IPC16
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

15 14 13 12 11 10 9 8
IPC15 IPC14 IPC13 IPC12 IPC11 IPC10 IPC9 IPC8
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

7 6 5 4 3 2 1 0
IPC7 IPC6 IPC5 IPC4 IPC3 IPC2 IPC1 IPC0
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 7-25. IPCACK Register Field Descriptions

Bit Field Type Reset Description
31 IPC31 R-0/W1S 0h Writing 1 to this bit clears the IPC31 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn
30 IPC30 R-0/W1S 0h Writing 1 to this bit clears the IPC30 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn
29 IPC29 R-0/W1S 0h Writing 1 to this bit clears the IPC29 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn
28 IPC28 R-0/W1S 0h Writing 1 to this bit clears the IPC28 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn
27 IPC27 R-0/W1S 0h Writing 1 to this bit clears the IPC27 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn
26 IPC26 R-0/W1S 0h Writing 1 to this bit clears the IPC26 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn
25 IPC25 R-0/W1S 0h Writing 1 to this bit clears the IPC25 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

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Table 7-25. IPCACK Register Field Descriptions (continued)

Bit Field Type Reset Description
24 IPC24 R-0/W1S 0h Writing 1 to this bit clears the IPC24 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn
23 IPC23 R-0/W1S 0h Writing 1 to this bit clears the IPC23 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn
22 IPC22 R-0/W1S 0h Writing 1 to this bit clears the IPC22 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn
21 IPC21 R-0/W1S 0h Writing 1 to this bit clears the IPC21 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn
20 IPC20 R-0/W1S 0h Writing 1 to this bit clears the IPC20 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn
19 IPC19 R-0/W1S 0h Writing 1 to this bit clears the IPC19 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn
18 IPC18 R-0/W1S 0h Writing 1 to this bit clears the IPC18 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn
17 IPC17 R-0/W1S 0h Writing 1 to this bit clears the IPC17 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn
16 IPC16 R-0/W1S 0h Writing 1 to this bit clears the IPC16 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn
15 IPC15 R-0/W1S 0h Writing 1 to this bit clears the IPC15 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn
14 IPC14 R-0/W1S 0h Writing 1 to this bit clears the IPC14 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn
13 IPC13 R-0/W1S 0h Writing 1 to this bit clears the IPC13 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn
12 IPC12 R-0/W1S 0h Writing 1 to this bit clears the IPC12 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn
11 IPC11 R-0/W1S 0h Writing 1 to this bit clears the IPC11 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

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Table 7-25. IPCACK Register Field Descriptions (continued)

Bit Field Type Reset Description
10 IPC10 R-0/W1S 0h Writing 1 to this bit clears the IPC10 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn
9 IPC9 R-0/W1S 0h Writing 1 to this bit clears the IPC9 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn
8 IPC8 R-0/W1S 0h Writing 1 to this bit clears the IPC8 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn
7 IPC7 R-0/W1S 0h Writing 1 to this bit clears the IPC7 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn
6 IPC6 R-0/W1S 0h Writing 1 to this bit clears the IPC6 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn
5 IPC5 R-0/W1S 0h Writing 1 to this bit clears the IPC5 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn
4 IPC4 R-0/W1S 0h Writing 1 to this bit clears the IPC4 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn
3 IPC3 R-0/W1S 0h Writing 1 to this bit clears the IPC3 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn
2 IPC2 R-0/W1S 0h Writing 1 to this bit clears the IPC2 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn
1 IPC1 R-0/W1S 0h Writing 1 to this bit clears the IPC1 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn
0 IPC0 R-0/W1S 0h Writing 1 to this bit clears the IPC0 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

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7.7.3.2 IPCSTS Register (Offset = 2h) [Reset = 00000000h]

IPCSTS is shown in Figure 7-20 and described in Table 7-26.
Return to the Summary Table.
IPC incoming flag status register
Figure 7-20. IPCSTS Register
31 30 29 28 27 26 25 24
IPC31 IPC30 IPC29 IPC28 IPC27 IPC26 IPC25 IPC24
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

23 22 21 20 19 18 17 16
IPC23 IPC22 IPC21 IPC20 IPC19 IPC18 IPC17 IPC16
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

15 14 13 12 11 10 9 8
IPC15 IPC14 IPC13 IPC12 IPC11 IPC10 IPC9 IPC8
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
IPC7 IPC6 IPC5 IPC4 IPC3 IPC2 IPC1 IPC0
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 7-26. IPCSTS Register Field Descriptions

Bit Field Type Reset Description
31 IPC31 R 0h Indicates to the local CPU if the IPC31 event flag was set by the
remote CPU.
0: No IPC31 event was set by the remote CPU
1: An IPC31 event was set by the remote CPU
Reset type: SYSRSn
30 IPC30 R 0h Indicates to the local CPU if the IPC30 event flag was set by the
remote CPU.
0: No IPC30 event was set by the remote CPU
1: An IPC30 event was set by the remote CPU
Reset type: SYSRSn
29 IPC29 R 0h Indicates to the local CPU if the IPC29 event flag was set by the
remote CPU.
0: No IPC29 event was set by the remote CPU
1: An IPC29 event was set by the remote CPU
Reset type: SYSRSn
28 IPC28 R 0h Indicates to the local CPU if the IPC28 event flag was set by the
remote CPU.
0: No IPC28 event was set by the remote CPU
1: An IPC28 event was set by the remote CPU
Reset type: SYSRSn
27 IPC27 R 0h Indicates to the local CPU if the IPC27 event flag was set by the
remote CPU.
0: No IPC27 event was set by the remote CPU
1: An IPC27 event was set by the remote CPU
Reset type: SYSRSn
26 IPC26 R 0h Indicates to the local CPU if the IPC26 event flag was set by the
remote CPU.
0: No IPC26 event was set by the remote CPU
1: An IPC26 event was set by the remote CPU
Reset type: SYSRSn

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Table 7-26. IPCSTS Register Field Descriptions (continued)

Bit Field Type Reset Description
25 IPC25 R 0h Indicates to the local CPU if the IPC25 event flag was set by the
remote CPU.
0: No IPC25 event was set by the remote CPU
1: An IPC25 event was set by the remote CPU
Reset type: SYSRSn
24 IPC24 R 0h Indicates to the local CPU if the IPC24 event flag was set by the
remote CPU.
0: No IPC24 event was set by the remote CPU
1: An IPC24 event was set by the remote CPU
Reset type: SYSRSn
23 IPC23 R 0h Indicates to the local CPU if the IPC23 event flag was set by the
remote CPU.
0: No IPC23 event was set by the remote CPU
1: An IPC23 event was set by the remote CPU
Reset type: SYSRSn
22 IPC22 R 0h Indicates to the local CPU if the IPC22 event flag was set by the
remote CPU.
0: No IPC22 event was set by the remote CPU
1: An IPC22 event was set by the remote CPU
Reset type: SYSRSn
21 IPC21 R 0h Indicates to the local CPU if the IPC21 event flag was set by the
remote CPU.
0: No IPC21 event was set by the remote CPU
1: An IPC21 event was set by the remote CPU
Reset type: SYSRSn
20 IPC20 R 0h Indicates to the local CPU if the IPC20 event flag was set by the
remote CPU.
0: No IPC20 event was set by the remote CPU
1: An IPC20 event was set by the remote CPU
Reset type: SYSRSn
19 IPC19 R 0h Indicates to the local CPU if the IPC19 event flag was set by the
remote CPU.
0: No IPC19 event was set by the remote CPU
1: An IPC19 event was set by the remote CPU
Reset type: SYSRSn
18 IPC18 R 0h Indicates to the local CPU if the IPC18 event flag was set by the
remote CPU.
0: No IPC18 event was set by the remote CPU
1: An IPC18 event was set by the remote CPU
Reset type: SYSRSn
17 IPC17 R 0h Indicates to the local CPU if the IPC17 event flag was set by the
remote CPU.
0: No IPC17 event was set by the remote CPU
1: An IPC17 event was set by the remote CPU
Reset type: SYSRSn
16 IPC16 R 0h Indicates to the local CPU if the IPC16 event flag was set by the
remote CPU.
0: No IPC16 event was set by the remote CPU
1: An IPC16 event was set by the remote CPU
Reset type: SYSRSn
15 IPC15 R 0h Indicates to the local CPU if the IPC15 event flag was set by the
remote CPU.
0: No IPC15 event was set by the remote CPU
1: An IPC15 event was set by the remote CPU
Reset type: SYSRSn

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Table 7-26. IPCSTS Register Field Descriptions (continued)

Bit Field Type Reset Description
14 IPC14 R 0h Indicates to the local CPU if the IPC14 event flag was set by the
remote CPU.
0: No IPC14 event was set by the remote CPU
1: An IPC14 event was set by the remote CPU
Reset type: SYSRSn
13 IPC13 R 0h Indicates to the local CPU if the IPC13 event flag was set by the
remote CPU.
0: No IPC13 event was set by the remote CPU
1: An IPC13 event was set by the remote CPU
Reset type: SYSRSn
12 IPC12 R 0h Indicates to the local CPU if the IPC12 event flag was set by the
remote CPU.
0: No IPC12 event was set by the remote CPU
1: An IPC12 event was set by the remote CPU
Reset type: SYSRSn
11 IPC11 R 0h Indicates to the local CPU if the IPC11 event flag was set by the
remote CPU.
0: No IPC11 event was set by the remote CPU
1: An IPC11 event was set by the remote CPU
Reset type: SYSRSn
10 IPC10 R 0h Indicates to the local CPU if the IPC10 event flag was set by the
remote CPU.
0: No IPC10 event was set by the remote CPU
1: An IPC10 event was set by the remote CPU
Reset type: SYSRSn
9 IPC9 R 0h Indicates to the local CPU if the IPC9 event flag was set by the
remote CPU.
0: No IPC9 event was set by the remote CPU
1: An IPC9 event was set by the remote CPU
Reset type: SYSRSn
8 IPC8 R 0h Indicates to the local CPU if the IPC8 event flag was set by the
remote CPU.
0: No IPC8 event was set by the remote CPU
1: An IPC8 event was set by the remote CPU
Reset type: SYSRSn
7 IPC7 R 0h Indicates to the local CPU if the IPC7 event flag was set by the
remote CPU.
0: No IPC7 event was set by the remote CPU
1: An IPC7 event was set by the remote CPU
Reset type: SYSRSn
6 IPC6 R 0h Indicates to the local CPU if the IPC6 event flag was set by the
remote CPU.
0: No IPC6 event was set by the remote CPU
1: An IPC6 event was set by the remote CPU
Reset type: SYSRSn
5 IPC5 R 0h Indicates to the local CPU if the IPC5 event flag was set by the
remote CPU.
0: No IPC5 event was set by the remote CPU
1: An IPC5 event was set by the remote CPU
Reset type: SYSRSn
4 IPC4 R 0h Indicates to the local CPU if the IPC4 event flag was set by the
remote CPU.
0: No IPC4 event was set by the remote CPU
1: An IPC4 event was set by the remote CPU
Reset type: SYSRSn

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Table 7-26. IPCSTS Register Field Descriptions (continued)

Bit Field Type Reset Description
3 IPC3 R 0h Indicates to the local CPU if the IPC3 event flag was set by the
remote CPU.
0: No IPC3 event was set by the remote CPU
1: An IPC3 event was set by the remote CPU
Notes
[1] IPC event flags 0-3 will trigger interrupts in the receiving CPU via
the ePIE.
Reset type: SYSRSn
2 IPC2 R 0h Indicates to the local CPU if the IPC2 event flag was set by the
remote CPU.
0: No IPC2 event was set by the remote CPU
1: An IPC2 event was set by the remote CPU
Notes
[1] IPC event flags 0-3 will trigger interrupts in the receiving CPU via
the ePIE.
Reset type: SYSRSn
1 IPC1 R 0h Indicates to the local CPU if the IPC1 event flag was set by the
remote CPU.
0: No IPC1 event was set by the remote CPU
1: An IPC1 event was set by the remote CPU
Notes
[1] IPC event flags 0-3 will trigger interrupts in the receiving CPU via
the ePIE.
Reset type: SYSRSn
0 IPC0 R 0h Indicates to the local CPU if the IPC0 event flag was set by the
remote CPU.
0: No IPC0 event was set by the remote CPU
1: An IPC0 event was set by the remote CPU
Notes
[1] IPC event flags 0-3 will trigger interrupts in the receiving CPU via
the ePIE.
Reset type: SYSRSn

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7.7.3.3 IPCSET Register (Offset = 4h) [Reset = 00000000h]

IPCSET is shown in Figure 7-21 and described in Table 7-27.
Return to the Summary Table.
IPC remote flag set register
Figure 7-21. IPCSET Register
31 30 29 28 27 26 25 24
IPC31 IPC30 IPC29 IPC28 IPC27 IPC26 IPC25 IPC24
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

23 22 21 20 19 18 17 16
IPC23 IPC22 IPC21 IPC20 IPC19 IPC18 IPC17 IPC16
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

15 14 13 12 11 10 9 8
IPC15 IPC14 IPC13 IPC12 IPC11 IPC10 IPC9 IPC8
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

7 6 5 4 3 2 1 0
IPC7 IPC6 IPC5 IPC4 IPC3 IPC2 IPC1 IPC0
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 7-27. IPCSET Register Field Descriptions

Bit Field Type Reset Description
31 IPC31 R-0/W1S 0h Writing 1 to this bit sets the IPC31 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn
30 IPC30 R-0/W1S 0h Writing 1 to this bit sets the IPC30 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn
29 IPC29 R-0/W1S 0h Writing 1 to this bit sets the IPC29 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn
28 IPC28 R-0/W1S 0h Writing 1 to this bit sets the IPC28 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn
27 IPC27 R-0/W1S 0h Writing 1 to this bit sets the IPC27 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn
26 IPC26 R-0/W1S 0h Writing 1 to this bit sets the IPC26 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn
25 IPC25 R-0/W1S 0h Writing 1 to this bit sets the IPC25 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn
24 IPC24 R-0/W1S 0h Writing 1 to this bit sets the IPC24 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn
23 IPC23 R-0/W1S 0h Writing 1 to this bit sets the IPC23 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn
22 IPC22 R-0/W1S 0h Writing 1 to this bit sets the IPC22 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn

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Table 7-27. IPCSET Register Field Descriptions (continued)

Bit Field Type Reset Description
21 IPC21 R-0/W1S 0h Writing 1 to this bit sets the IPC21 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn
20 IPC20 R-0/W1S 0h Writing 1 to this bit sets the IPC20 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn
19 IPC19 R-0/W1S 0h Writing 1 to this bit sets the IPC19 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn
18 IPC18 R-0/W1S 0h Writing 1 to this bit sets the IPC18 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn
17 IPC17 R-0/W1S 0h Writing 1 to this bit sets the IPC17 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn
16 IPC16 R-0/W1S 0h Writing 1 to this bit sets the IPC16 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn
15 IPC15 R-0/W1S 0h Writing 1 to this bit sets the IPC15 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn
14 IPC14 R-0/W1S 0h Writing 1 to this bit sets the IPC14 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn
13 IPC13 R-0/W1S 0h Writing 1 to this bit sets the IPC13 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn
12 IPC12 R-0/W1S 0h Writing 1 to this bit sets the IPC12 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn
11 IPC11 R-0/W1S 0h Writing 1 to this bit sets the IPC11 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn
10 IPC10 R-0/W1S 0h Writing 1 to this bit sets the IPC10 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn
9 IPC9 R-0/W1S 0h Writing 1 to this bit sets the IPC9 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn
8 IPC8 R-0/W1S 0h Writing 1 to this bit sets the IPC8 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn
7 IPC7 R-0/W1S 0h Writing 1 to this bit sets the IPC7 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn
6 IPC6 R-0/W1S 0h Writing 1 to this bit sets the IPC6 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn
5 IPC5 R-0/W1S 0h Writing 1 to this bit sets the IPC5 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn

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Table 7-27. IPCSET Register Field Descriptions (continued)

Bit Field Type Reset Description
4 IPC4 R-0/W1S 0h Writing 1 to this bit sets the IPC4 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn
3 IPC3 R-0/W1S 0h Writing 1 to this bit sets the IPC3 event flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] IPC event flags 0-3 will trigger interrupts in the receiving CPU via
the ePIE.
Reset type: SYSRSn
2 IPC2 R-0/W1S 0h Writing 1 to this bit sets the IPC2 event flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] IPC event flags 0-3 will trigger interrupts in the receiving CPU via
the ePIE.
Reset type: SYSRSn
1 IPC1 R-0/W1S 0h Writing 1 to this bit sets the IPC1 event flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] IPC event flags 0-3 will trigger interrupts in the receiving CPU via
the ePIE.
Reset type: SYSRSn
0 IPC0 R-0/W1S 0h Writing 1 to this bit sets the IPC0 event flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] IPC event flags 0-3 will trigger interrupts in the receiving CPU via
the ePIE.
Reset type: SYSRSn

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7.7.3.4 IPCCLR Register (Offset = 6h) [Reset = 00000000h]

IPCCLR is shown in Figure 7-22 and described in Table 7-28.
Return to the Summary Table.
IPC remote flag clear register
Figure 7-22. IPCCLR Register
31 30 29 28 27 26 25 24
IPC31 IPC30 IPC29 IPC28 IPC27 IPC26 IPC25 IPC24
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

23 22 21 20 19 18 17 16
IPC23 IPC22 IPC21 IPC20 IPC19 IPC18 IPC17 IPC16
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

15 14 13 12 11 10 9 8
IPC15 IPC14 IPC13 IPC12 IPC11 IPC10 IPC9 IPC8
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

7 6 5 4 3 2 1 0
IPC7 IPC6 IPC5 IPC4 IPC3 IPC2 IPC1 IPC0
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 7-28. IPCCLR Register Field Descriptions

Bit Field Type Reset Description
31 IPC31 R-0/W1S 0h Writing 1 to this bit clears the IPC31 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn
30 IPC30 R-0/W1S 0h Writing 1 to this bit clears the IPC30 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn
29 IPC29 R-0/W1S 0h Writing 1 to this bit clears the IPC29 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn
28 IPC28 R-0/W1S 0h Writing 1 to this bit clears the IPC28 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn

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Table 7-28. IPCCLR Register Field Descriptions (continued)

Bit Field Type Reset Description
27 IPC27 R-0/W1S 0h Writing 1 to this bit clears the IPC27 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn
26 IPC26 R-0/W1S 0h Writing 1 to this bit clears the IPC26 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn
25 IPC25 R-0/W1S 0h Writing 1 to this bit clears the IPC25 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn
24 IPC24 R-0/W1S 0h Writing 1 to this bit clears the IPC24 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn
23 IPC23 R-0/W1S 0h Writing 1 to this bit clears the IPC23 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn
22 IPC22 R-0/W1S 0h Writing 1 to this bit clears the IPC22 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn
21 IPC21 R-0/W1S 0h Writing 1 to this bit clears the IPC21 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn
20 IPC20 R-0/W1S 0h Writing 1 to this bit clears the IPC20 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn

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Table 7-28. IPCCLR Register Field Descriptions (continued)

Bit Field Type Reset Description
19 IPC19 R-0/W1S 0h Writing 1 to this bit clears the IPC19 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn
18 IPC18 R-0/W1S 0h Writing 1 to this bit clears the IPC18 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn
17 IPC17 R-0/W1S 0h Writing 1 to this bit clears the IPC17 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn
16 IPC16 R-0/W1S 0h Writing 1 to this bit clears the IPC16 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn
15 IPC15 R-0/W1S 0h Writing 1 to this bit clears the IPC15 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn
14 IPC14 R-0/W1S 0h Writing 1 to this bit clears the IPC14 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn
13 IPC13 R-0/W1S 0h Writing 1 to this bit clears the IPC13 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn
12 IPC12 R-0/W1S 0h Writing 1 to this bit clears the IPC12 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn

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Table 7-28. IPCCLR Register Field Descriptions (continued)

Bit Field Type Reset Description
11 IPC11 R-0/W1S 0h Writing 1 to this bit clears the IPC11 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn
10 IPC10 R-0/W1S 0h Writing 1 to this bit clears the IPC10 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn
9 IPC9 R-0/W1S 0h Writing 1 to this bit clears the IPC9 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn
8 IPC8 R-0/W1S 0h Writing 1 to this bit clears the IPC8 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn
7 IPC7 R-0/W1S 0h Writing 1 to this bit clears the IPC7 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn
6 IPC6 R-0/W1S 0h Writing 1 to this bit clears the IPC6 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn
5 IPC5 R-0/W1S 0h Writing 1 to this bit clears the IPC5 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn
4 IPC4 R-0/W1S 0h Writing 1 to this bit clears the IPC4 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn

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Table 7-28. IPCCLR Register Field Descriptions (continued)

Bit Field Type Reset Description
3 IPC3 R-0/W1S 0h Writing 1 to this bit clears the IPC3 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn
2 IPC2 R-0/W1S 0h Writing 1 to this bit clears the IPC2 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn
1 IPC1 R-0/W1S 0h Writing 1 to this bit clears the IPC1 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn
0 IPC0 R-0/W1S 0h Writing 1 to this bit clears the IPC0 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is non-
responsive.
Reset type: SYSRSn

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7.7.3.5 IPCFLG Register (Offset = 8h) [Reset = 00000000h]

IPCFLG is shown in Figure 7-23 and described in Table 7-29.
Return to the Summary Table.
IPC remote flag status register
Figure 7-23. IPCFLG Register
31 30 29 28 27 26 25 24
IPC31 IPC30 IPC29 IPC28 IPC27 IPC26 IPC25 IPC24
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

23 22 21 20 19 18 17 16
IPC23 IPC22 IPC21 IPC20 IPC19 IPC18 IPC17 IPC16
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

15 14 13 12 11 10 9 8
IPC15 IPC14 IPC13 IPC12 IPC11 IPC10 IPC9 IPC8
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
IPC7 IPC6 IPC5 IPC4 IPC3 IPC2 IPC1 IPC0
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 7-29. IPCFLG Register Field Descriptions

Bit Field Type Reset Description
31 IPC31 R 0h Indicates to the local CPU whether the remote IPC31 event flag is
set.
0: The remote IPC31 event flag is not set
1: The remote IPC31 event flag is set
Reset type: SYSRSn
30 IPC30 R 0h Indicates to the local CPU whether the remote IPC30 event flag is
set.
0: The remote IPC30 event flag is not set
1: The remote IPC30 event flag is set
Reset type: SYSRSn
29 IPC29 R 0h Indicates to the local CPU whether the remote IPC29 event flag is
set.
0: The remote IPC29 event flag is not set
1: The remote IPC29 event flag is set
Reset type: SYSRSn
28 IPC28 R 0h Indicates to the local CPU whether the remote IPC28 event flag is
set.
0: The remote IPC28 event flag is not set
1: The remote IPC28 event flag is set
Reset type: SYSRSn
27 IPC27 R 0h Indicates to the local CPU whether the remote IPC27 event flag is
set.
0: The remote IPC27 event flag is not set
1: The remote IPC27 event flag is set
Reset type: SYSRSn
26 IPC26 R 0h Indicates to the local CPU whether the remote IPC26 event flag is
set.
0: The remote IPC26 event flag is not set
1: The remote IPC26 event flag is set
Reset type: SYSRSn

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Table 7-29. IPCFLG Register Field Descriptions (continued)

Bit Field Type Reset Description
25 IPC25 R 0h Indicates to the local CPU whether the remote IPC25 event flag is
set.
0: The remote IPC25 event flag is not set
1: The remote IPC25 event flag is set
Reset type: SYSRSn
24 IPC24 R 0h Indicates to the local CPU whether the remote IPC24 event flag is
set.
0: The remote IPC24 event flag is not set
1: The remote IPC24 event flag is set
Reset type: SYSRSn
23 IPC23 R 0h Indicates to the local CPU whether the remote IPC23 event flag is
set.
0: The remote IPC23 event flag is not set
1: The remote IPC23 event flag is set
Reset type: SYSRSn
22 IPC22 R 0h Indicates to the local CPU whether the remote IPC22 event flag is
set.
0: The remote IPC22 event flag is not set
1: The remote IPC22 event flag is set
Reset type: SYSRSn
21 IPC21 R 0h Indicates to the local CPU whether the remote IPC21 event flag is
set.
0: The remote IPC21 event flag is not set
1: The remote IPC21 event flag is set
Reset type: SYSRSn
20 IPC20 R 0h Indicates to the local CPU whether the remote IPC20 event flag is
set.
0: The remote IPC20 event flag is not set
1: The remote IPC20 event flag is set
Reset type: SYSRSn
19 IPC19 R 0h Indicates to the local CPU whether the remote IPC19 event flag is
set.
0: The remote IPC19 event flag is not set
1: The remote IPC19 event flag is set
Reset type: SYSRSn
18 IPC18 R 0h Indicates to the local CPU whether the remote IPC18 event flag is
set.
0: The remote IPC18 event flag is not set
1: The remote IPC18 event flag is set
Reset type: SYSRSn
17 IPC17 R 0h Indicates to the local CPU whether the remote IPC17 event flag is
set.
0: The remote IPC17 event flag is not set
1: The remote IPC17 event flag is set
Reset type: SYSRSn
16 IPC16 R 0h Indicates to the local CPU whether the remote IPC16 event flag is
set.
0: The remote IPC16 event flag is not set
1: The remote IPC16 event flag is set
Reset type: SYSRSn
15 IPC15 R 0h Indicates to the local CPU whether the remote IPC15 event flag is
set.
0: The remote IPC15 event flag is not set
1: The remote IPC15 event flag is set
Reset type: SYSRSn

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Table 7-29. IPCFLG Register Field Descriptions (continued)

Bit Field Type Reset Description
14 IPC14 R 0h Indicates to the local CPU whether the remote IPC14 event flag is
set.
0: The remote IPC14 event flag is not set
1: The remote IPC14 event flag is set
Reset type: SYSRSn
13 IPC13 R 0h Indicates to the local CPU whether the remote IPC13 event flag is
set.
0: The remote IPC13 event flag is not set
1: The remote IPC13 event flag is set
Reset type: SYSRSn
12 IPC12 R 0h Indicates to the local CPU whether the remote IPC12 event flag is
set.
0: The remote IPC12 event flag is not set
1: The remote IPC12 event flag is set
Reset type: SYSRSn
11 IPC11 R 0h Indicates to the local CPU whether the remote IPC11 event flag is
set.
0: The remote IPC11 event flag is not set
1: The remote IPC11 event flag is set
Reset type: SYSRSn
10 IPC10 R 0h Indicates to the local CPU whether the remote IPC10 event flag is
set.
0: The remote IPC10 event flag is not set
1: The remote IPC10 event flag is set
Reset type: SYSRSn
9 IPC9 R 0h Indicates to the local CPU whether the remote IPC9 event flag is set.
0: The remote IPC9 event flag is not set
1: The remote IPC9 event flag is set
Reset type: SYSRSn
8 IPC8 R 0h Indicates to the local CPU whether the remote IPC8 event flag is set.
0: The remote IPC8 event flag is not set
1: The remote IPC8 event flag is set
Reset type: SYSRSn
7 IPC7 R 0h Indicates to the local CPU whether the remote IPC7 event flag is set.
0: The remote IPC7 event flag is not set
1: The remote IPC7 event flag is set
Reset type: SYSRSn
6 IPC6 R 0h Indicates to the local CPU whether the remote IPC6 event flag is set.
0: The remote IPC6 event flag is not set
1: The remote IPC6 event flag is set
Reset type: SYSRSn
5 IPC5 R 0h Indicates to the local CPU whether the remote IPC5 event flag is set.
0: The remote IPC5 event flag is not set
1: The remote IPC5 event flag is set
Reset type: SYSRSn
4 IPC4 R 0h Indicates to the local CPU whether the remote IPC4 event flag is set.
0: The remote IPC4 event flag is not set
1: The remote IPC4 event flag is set
Reset type: SYSRSn
3 IPC3 R 0h Indicates to the local CPU whether the remote IPC3 event flag is set.
0: The remote IPC3 event flag is not set
1: The remote IPC3 event flag is set
Notes:
[1] IPC event flags 0-3 will trigger interrupts in the receiving CPU via
the ePIE.
Reset type: SYSRSn

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Table 7-29. IPCFLG Register Field Descriptions (continued)

Bit Field Type Reset Description
2 IPC2 R 0h Indicates to the local CPU whether the remote IPC2 event flag is set.
0: The remote IPC2 event flag is not set
1: The remote IPC2 event flag is set
Notes:
[1] IPC event flags 0-3 will trigger interrupts in the receiving CPU via
the ePIE.
Reset type: SYSRSn
1 IPC1 R 0h Indicates to the local CPU whether the remote IPC1 event flag is set.
0: The remote IPC1 event flag is not set
1: The remote IPC1 event flag is set
Notes:
[1] IPC event flags 0-3 will trigger interrupts in the receiving CPU via
the ePIE.
Reset type: SYSRSn
0 IPC0 R 0h Indicates to the local CPU whether the remote IPC0 event flag is set.
0: The remote IPC0 event flag is not set
1: The remote IPC0 event flag is set
Notes:
[1] IPC event flags 0-3 will trigger interrupts in the receiving CPU via
the ePIE.
Reset type: SYSRSn

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7.7.3.6 IPCCOUNTERL Register (Offset = Ch) [Reset = 00000000h]

IPCCOUNTERL is shown in Figure 7-24 and described in Table 7-30.
Return to the Summary Table.
IPC Counter Low Register
Figure 7-24. IPCCOUNTERL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COUNT
R-0h

Table 7-30. IPCCOUNTERL Register Field Descriptions

Bit Field Type Reset Description
31-0 COUNT R 0h This is the lower 32-bits of free running 64 bit timestamp counter
clocked by the PLLSYSCLK.
Reset type: CPU1.SYSRSn

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7.7.3.7 IPCCOUNTERH Register (Offset = Eh) [Reset = 00000000h]

IPCCOUNTERH is shown in Figure 7-25 and described in Table 7-31.
Return to the Summary Table.
IPC Counter High Register
Figure 7-25. IPCCOUNTERH Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COUNT
R-0h

Table 7-31. IPCCOUNTERH Register Field Descriptions

Bit Field Type Reset Description
31-0 COUNT R 0h This is the upper 32-bits of free running 64 bit timestamp counter
clocked by the PLLSYSCLK.
Reset type: CPU1.SYSRSn

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7.7.3.8 IPCRECVCOM Register (Offset = 10h) [Reset = 00000000h]

IPCRECVCOM is shown in Figure 7-26 and described in Table 7-32.
Return to the Summary Table.
Remote to Local IPC Command Register
Figure 7-26. IPCRECVCOM Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMMAND
R-0h

Table 7-32. IPCRECVCOM Register Field Descriptions

Bit Field Type Reset Description
31-0 COMMAND R 0h This is a general purpose register used to receive software-defined
commands from the remote CPU. It can only be written by the
remote CPU.
Notes
[1] The local CPU's IPCRECVCOM is the same physical register
as the remote CPU's IPCSENDCOM, and is located at the same
address in both CPUs.
[2] This register is reset by a SYRSn of the remote CPU
Reset type: CPUx.SYSRSn

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7.7.3.9 IPCRECVADDR Register (Offset = 12h) [Reset = 00000000h]

IPCRECVADDR is shown in Figure 7-27 and described in Table 7-33.
Return to the Summary Table.
Remote to Local IPC Address Register
Figure 7-27. IPCRECVADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDRESS
R-0h

Table 7-33. IPCRECVADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 ADDRESS R 0h This is a general purpose register used to receive software-defined
addresses from the remote CPU. It can only be written by the remote
CPU.
Notes
[1] The local CPU's IPCRECVADDR is the same physical register
as the remote CPU's IPCSENDADDR, and is located at the same
address in both CPUs.
[2] This register is reset by a SYRSn of the remote CPU
Reset type: CPUx.SYSRSn

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7.7.3.10 IPCRECVDATA Register (Offset = 14h) [Reset = 00000000h]

IPCRECVDATA is shown in Figure 7-28 and described in Table 7-34.
Return to the Summary Table.
Remote to Local IPC Data Register
Figure 7-28. IPCRECVDATA Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
R-0h

Table 7-34. IPCRECVDATA Register Field Descriptions

Bit Field Type Reset Description
31-0 WDATA R 0h This is a general purpose register used to receive software-defined
data from the remote CPU. It can only be written by the remote CPU.
Notes
[1] The local CPU's IPCRECVDATA is the same physical register
as the remote CPU's IPCSENDDATA, and is located at the same
address in both CPUs.
[2] This register is reset by a SYRSn of the remote CPU
Reset type: CPUx.SYSRSn

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7.7.3.11 IPCLOCALREPLY Register (Offset = 16h) [Reset = 00000000h]

IPCLOCALREPLY is shown in Figure 7-29 and described in Table 7-35.
Return to the Summary Table.
Local to Remote IPC Reply Data Register
Figure 7-29. IPCLOCALREPLY Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
R/W-0h

Table 7-35. IPCLOCALREPLY Register Field Descriptions

Bit Field Type Reset Description
31-0 RDATA R/W 0h This is a general purpose register used to send software-defined
data to the remote CPU in response to a command. It can only be
written by the local CPU.
Notes
[1] The local CPU's IPCLOCALREPLY is the same physical register
as the remote CPU's IPCREMOTEREPLY, and is located at the
same address in both CPUs.
Reset type: SYSRSn

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7.7.3.12 IPCSENDCOM Register (Offset = 18h) [Reset = 00000000h]

IPCSENDCOM is shown in Figure 7-30 and described in Table 7-36.
Return to the Summary Table.
Local to Remote IPC Command Register
Figure 7-30. IPCSENDCOM Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMMAND
R/W-0h

Table 7-36. IPCSENDCOM Register Field Descriptions

Bit Field Type Reset Description
31-0 COMMAND R/W 0h This is a general purpose register used to send software-defined
commands to the remote CPU. It can only be written by the local
CPU.
Notes
[1] The local CPU's IPCSENDCOM is the same physical register
as the remote CPU's IPCRECVCOM, and is located at the same
address in both CPUs.
Reset type: SYSRSn

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7.7.3.13 IPCSENDADDR Register (Offset = 1Ah) [Reset = 00000000h]

IPCSENDADDR is shown in Figure 7-31 and described in Table 7-37.
Return to the Summary Table.
Local to Remote IPC Address Register
Figure 7-31. IPCSENDADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDRESS
R/W-0h

Table 7-37. IPCSENDADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 ADDRESS R/W 0h This is a general purpose register used to send software-defined
addresses to the remote CPU. It can only be written by the local
CPU.
Notes
[1] The local CPU's IPCSENDADDR is the same physical register
as the remote CPU's IPCRECVDATA, and is located at the same
address in both CPUs.
Reset type: SYSRSn

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7.7.3.14 IPCSENDDATA Register (Offset = 1Ch) [Reset = 00000000h]

IPCSENDDATA is shown in Figure 7-32 and described in Table 7-38.
Return to the Summary Table.
Local to Remote IPC Data Register
Figure 7-32. IPCSENDDATA Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
R/W-0h

Table 7-38. IPCSENDDATA Register Field Descriptions

Bit Field Type Reset Description
31-0 WDATA R/W 0h This is a general purpose register used to send software-defined
data to the remote CPU. It can only be written by the local CPU.
Notes
[1] The local CPU's IPCSENDDATA is the same physical register
as the remote CPU's IPCRECVDATA, and is located at the same
address in both CPUs.
Reset type: SYSRSn

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7.7.3.15 IPCREMOTEREPLY Register (Offset = 1Eh) [Reset = 00000000h]

IPCREMOTEREPLY is shown in Figure 7-33 and described in Table 7-39.
Return to the Summary Table.
Remote to Local IPC Reply Data Register
Figure 7-33. IPCREMOTEREPLY Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
R-0h

Table 7-39. IPCREMOTEREPLY Register Field Descriptions

Bit Field Type Reset Description
31-0 RDATA R 0h This is a general purpose register used to receive software-defined
data from the remote CPU's response to a command. It can only be
written by the remote CPU.
Notes
[1] The local CPU's IPCREMOTEREPLY is the same physical
register as the remote CPU's IPCLOCALREPLY, and is located at
the same address in both CPUs.
[2] This register is reset by a SYRSn of the remote CPU
Reset type: CPUx.SYSRSn

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7.7.3.16 IPCBOOTSTS Register (Offset = 20h) [Reset = 00000000h]

IPCBOOTSTS is shown in Figure 7-34 and described in Table 7-40.
Return to the Summary Table.
CPU2 to CPU1 IPC Boot Status Register
Figure 7-34. IPCBOOTSTS Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOOTSTS
R/W-0h

Table 7-40. IPCBOOTSTS Register Field Descriptions

Bit Field Type Reset Description
31-0 BOOTSTS R/W 0h This register is used by CPU2 to pass the boot Status to CPU1. The
data format is software-defined. It can only be written by CPU2.
Reset type: CPU2.SYSRSn

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7.7.3.17 IPCBOOTMODE Register (Offset = 22h) [Reset = 00000000h]

IPCBOOTMODE is shown in Figure 7-35 and described in Table 7-41.
Return to the Summary Table.
CPU1 to CPU2 IPC Boot Mode Register
Figure 7-35. IPCBOOTMODE Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOOTMODE
R/W-0h

Table 7-41. IPCBOOTMODE Register Field Descriptions

Bit Field Type Reset Description
31-0 BOOTMODE R/W 0h This register is used by CPU1 to pass a boot mode information to
CPU2. The data format is software-defined. It can only be written by
CPU1.
Reset type: CPU1.SYSRSn

7.7.4 IPC Registers to Driverlib Functions

Table 7-42. IPC Registers to Driverlib Functions
File Driverlib Function
ACK
-
STS
-
SET
-
CLR
-
FLG
-
COUNTERL
-
COUNTERH
-
SENDCOM
-
SENDADDR
-
SENDDATA
-
REMOTEREPLY
-
RECVCOM
-
RECVADDR
-
RECVDATA
-

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Table 7-42. IPC Registers to Driverlib Functions (continued)

File Driverlib Function
LOCALREPLY
-
RECVCOM
-
RECVADDR
-
RECVDATA
-
LOCALREPLY
-
SENDCOM
-
SENDADDR
-
SENDDATA
-
REMOTEREPLY
-
BOOTSTS
-
BOOTMODE
-

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Chapter 8
General-Purpose Input/Output (GPIO)

The GPIO module controls the device's digital multiplexing, which uses shared pins to maximize application
flexibility. The pins are named by the general-purpose I/O name (for example, GPIO0, GPIO25, GPIO58). These
pins can be individually selected to operate as digital I/O (also called GPIO mode), or connected to one of
several peripheral I/O signals. The input signals can be qualified to remove unwanted noise.

8.1 Introduction...............................................................................................................................................................987
8.2 Configuration Overview........................................................................................................................................... 989
8.3 Digital General-Purpose I/O Control....................................................................................................................... 990
8.4 Input Qualification.................................................................................................................................................... 991
8.5 USB Signals.............................................................................................................................................................. 995
8.6 SPI Signals................................................................................................................................................................ 995
8.7 GPIO and Peripheral Muxing................................................................................................................................... 996
8.8 Internal Pullup Configuration Requirements....................................................................................................... 1004
8.9 Software.................................................................................................................................................................. 1005
8.10 GPIO Registers..................................................................................................................................................... 1006

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8.1 Introduction
Up to twelve independent peripheral signals are multiplexed on a single GPIO-enabled pin in addition to the
CPU-controlled I/O capability. Each pin output can be controlled by either a peripheral or one of the four CPU
masters.
• CPU1
• CPU1.CLA
• CPU2
• CPU2.CLA
There are up to 8 possible I/O ports:
• Port A consists of GPIO0-GPIO31
• Port B consists of GPIO32-GPIO63
• Port C consists of GPIO64-GPIO95
• Port D consists of GPIO96-GPIO127
• Port E consists of GPIO128-GPIO159
• Port F consists of GPIO160-GPIO191
• Port G consists of GPIO192-GPIO223
• Port H consists of GPIO224-GPIO255

Note
Some GPIO and I/O ports can be unavailable on particular devices. See the GPIO Registers section
for available GPIO and I/O ports.

Figure 8-1 shows the GPIO logic for a single pin.

Note
The USB PHY pin muxing is not shown in Figure 8-1. For more details on USB pins, see Section 8.5.

There are two key features to note in Figure 8-1. The first is that the input and output paths are entirely separate,
connecting only at the pin. The second is that peripheral muxing takes place far from the pin. As a result, for
both CPUs and CLAs to read the physical state of the pin independent of CPU mastering and peripheral muxing
is possible. Likewise, external interrupts can be generated from peripheral activity. All pin options such as input
qualification and open-drain output are valid for all masters and peripherals. However, the peripheral muxing,
CPU muxing, and pin options can only be configured by CPU1.
A separate configuration is required for the USB signals. See Section 8.5 for details.

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Input
XBAR
CPU1 00:00 Unused
00:01 Peripheral A
GPyPUD Pull-Up 00:10 Peripheral B
Low Power CPU1 00:11 Peripheral C
Mode Control
CPU1 GPyCTRL GPyQSEL1-2
CPU1/CPU1.CLA/ 01:00 Unused
CPU2/CPU2.CLA GPyINV SYSCLK 01:01 Peripheral D
01:10 Peripheral E
GPyDAT (R) 00 01:11
Sync Peripheral F
3-sample 01
0 6-sample 10 10:xx Peripherals G-I
Async 11
GPIOx 1 11:xx Peripherals J-L

CPU1 CPU1.CLA CPU2 CPU2.CLA

GPyGMUX1-2 GPySET GPySET GPySET GPySET
GPyMUX1-2 GPyCLEAR GPyCLEAR GPyCLEAR GPyCLEAR
GPyDIR GPyTOGGLE GPyTOGGLE GPyTOGGLE GPyTOGGLE
Hibernate GPyCSEL1-4 GPyDAT (W) GPyDAT (W) GPyDAT (W) GPyDAT (W)
Isola on Latches

Direcon 00
01
10
11
Data
00:00
00:01 Peripheral A
00:10 Peripheral B
Data 00:11 Peripheral C

01:00 GPIO (same as 00:00)

01:01 Peripheral D
CPU1 Enable and 01:10 Peripheral E
GPyODR Open Drain Direc
on 01:11 Peripheral F
Logic
10:xx GPIO and Peripherals G-I

11:xx GPIO and Peripherals J-L

Figure 8-1. GPIO Logic for a Single Pin

8.1.1 GPIO Related Collateral

Foundational Materials
• C2000 Academy - GPIO

Getting Started Materials

• How to Maximize GPIO Usage in C2000 Devices Application Report
• [FAQ] C2000 GPIO FAQ

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8.2 Configuration Overview

I/O pin configuration consists of several steps:
1. Plan the device pin-out: Make a list of all required peripherals for the application. Using the peripheral mux
information in the device data sheet, choose which GPIOs to use for the peripheral signals. Decide which of
the remaining GPIOs to use as inputs and outputs for each CPU and CLA.
Once the peripheral muxing has been chosen, implement the mux by writing the appropriate values to
the GPyMUX1/2 and GPyGMUX1/2 registers. When changing the GPyGMUX value for a pin, always set
the corresponding GPyMUX bits to zero first to avoid glitching in the muxes. By default, all pins are general-
purpose I/Os, not peripheral signals.
2. (Optional) Enable internal pullup resistors: To enable or disable the pullup resistors, write to the
appropriate bits in the GPIO pullup disable registers (GPyPUD). All pullups are disabled by default. Pullups
can be used to keep input pins in a known state when there is no external signal driving them.
3. Select input qualification: If the pin is used as an input, specify the required input qualification, if any.
The input qualification sampling period is selected in the GPyCTRL registers, while the type of qualification
is selected in the GPyQSEL1 and GPyQSEL2 registers. By default, all qualification is synchronous with a
sampling period equal to PLLSYSCLK. For an explanation of input qualification, see Section 8.4.
4. Select the direction of any general-purpose I/O pins: For each pin configured as a GPIO, specify the
direction of the pin as either input or output using the GPyDIR registers. By default, all GPIO pins are inputs.
Before changing a pin to an output, load the output latch with the value to be driven by writing that value to
the GPySET, GPyCLEAR, or GPyDAT registers. Once the latch is loaded, write to GPyDIR to change the pin
direction. By default, all output latches are zero.
5. Select low-power mode wake-up sources: GPIOs 0-63 can be used to wake the system up from low
power modes. To select one or more GPIOs for wake-up, write to the appropriate bits in the GPIOLPMSEL0
and GPIOLPMSEL1 registers. These registers are part of the CPU system register space. In Hibernate
mode, GPIO 41 is the only wake-up pin. For more information on low-power modes and GPIO wake-up, see
the Low-Power Modes section in the System Control and Interrupts chapter.
6. Select external interrupt sources: Configuring external interrupts is a two-step process. First, the
interrupts themselves must be enabled and the polarity must be configured using the XINTnCR registers.
Second, the XINT1-5 GPIO pins must be set by selecting the sources for Input X-BAR signals 4, 5, 6,
13, and 14, respectively. For more information on the Input X-BAR architecture, see the Crossbar (X-BAR)
chapter.

Note
Configure the GPIO registers GPxMUX1, GPxMUX2, GPxINV, GPxGMUX1, and GPxGMUX2 as per
Section 8.7 before a peripheral starts using the respective GPIOs. The configuration is expected to be
static during runtime.

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8.3 Digital General-Purpose I/O Control

The values on the pins that are configured as GPIO can be changed by using the following registers.
• GPyDAT Registers
Each I/O port has one data register. Each bit in the data register corresponds to one GPIO pin. No matter
how the pin is configured (GPIO or peripheral function), the corresponding bit in the data register reflects the
current state of the pin after qualification. Writing to the GPyDAT register clears or sets the corresponding
output latch and if the pin is enabled as a general-purpose output (GPIO output), the pin is also driven either
low or high. If the pin is not configured as a GPIO output, then the value is latched but the pin is not driven.
Only if the pin is later configured as a GPIO output is the latched value driven onto the pin.
When using the GPyDAT register to change the level of an output pin, be cautious to not accidentally change
the level of another pin. For example, to change the output latch level of GPIOA1 by writing to the GPADAT
register bit 0 using a read-modify-write instruction, a problem can occur if another I/O port A signal changes
level between the read and the write stage of the instruction. Following is an analysis of why this happens:
The GPyDAT registers reflect the state of the pin, not the latch. This means the register reflects the actual
pin value. However, there is a lag between when the register is written to when the new pin value is reflected
back in the register. This can pose a problem when this register is used in subsequent program statements to
alter the state of GPIO pins. An example is shown below where two program statements attempt to drive two
different GPIO pins that are currently low to a high state.
If Read-Modify-Write operations are used on the GPyDAT registers, because of the delay between the output
and the input of the first instruction (I1), the second instruction (I2) reads the old value and writes the value
back.

GpioDataRegs.GPADAT.bit.GPIO1 = 1; //I1 performs read-modify-write of GPADAT

GpioDataRegs.GPADAT.bit.GPIO2 = 1; //I2 also a read-modify-write of GPADAT
//GPADAT gets the old value of GPIO1 due to the delay

The second instruction waits for the first to finish the write due to the write-followed-by-read protection on this
peripheral frame. There is some lag, however, between the write of (I1) and the GPyDAT bit reflecting the
new value (1) on the pin. During this lag, the second instruction reads the old value of GPIO1 (0) and writes
the value back along with the new value of GPIO2 (1). Therefore, GPIO1 pin stays low.
One answer is to put some NOPs between instructions. A better answer is to use the GPySET/GPyCLEAR/
GPyTOGGLE registers instead of the GPyDAT registers. These registers always read back a 0 and writes of
0 have no effect. Only bits that need to be changed can be specified without disturbing any other bits that are
currently in the process of changing.
• GPySET Registers
The set registers are used to drive specified GPIO pins high without disturbing other pins. Each I/O port has
one set register and each bit corresponds to one GPIO pin. The set registers always read back 0. If the
corresponding pin is configured as an output, then writing a 1 to that bit in the set register sets the output
latch high and the corresponding pin is driven high. If the pin is not configured as a GPIO output, then the
value is latched but the pin is not driven. Only if the pin is later configured as a GPIO output is the latched
value driven onto the pin. Writing a 0 to any bit in the set registers has no effect.
• GPyCLEAR Registers
The clear registers are used to drive specified GPIO pins low without disturbing other pins. Each I/O port
has one clear register. The clear registers always read back 0. If the corresponding pin is configured as a
general-purpose output, then writing a 1 to the corresponding bit in the clear register clears the output latch
and the pin is driven low. If the pin is not configured as a GPIO output, then the value is latched but the pin is
not driven. Only if the pin is later configured as a GPIO output is the latched value driven onto the pin. Writing
a 0 to any bit in the clear registers has no effect.

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• GPyTOGGLE Registers
The toggle registers are used to drive specified GPIO pins to the opposite level without disturbing other pins.
Each I/O port has one toggle register. The toggle registers always read back 0. If the corresponding pin is
configured as an output, then writing a 1 to that bit in the toggle register flips the output latch and pulls the
corresponding pin in the opposite direction. That is, if the output pin is driven low, then writing a 1 to the
corresponding bit in the toggle register pulls the pin high. Likewise, if the output pin is high, then writing a 1
to the corresponding bit in the toggle register pulls the pin low. If the pin is not configured as a GPIO output,
then the value is latched but the pin is not driven. Only if the pin is later configured as a GPIO output is the
latched value driven onto the pin. Writing a 0 to any bit in the toggle registers has no effect.

8.4 Input Qualification

The input qualification scheme has been designed to be very flexible. Select the type of input qualification for
each GPIO pin by configuring the GPyQSEL1 and GPyQSEL2 registers. In the case of a GPIO input pin, the
qualification can be specified as only synchronized to SYSCLKOUT or qualification by a sampling window. For
pins that are configured as peripheral inputs, the input can also be asynchronous in addition to synchronized to
SYSCLKOUT or qualified by a sampling window. The remainder of this section describes the options available.
8.4.1 No Synchronization (Asynchronous Input)
This mode is used for peripherals where input synchronization is not required or the peripheral performs the
synchronization. Examples include communication ports McBSP, SCI, SPI, and I2C. In addition, the ePWM trip
zone (TZn) signals can function independent of the presence of SYSCLKOUT.

Note
Using input synchronization when the peripheral performs the synchronization can cause unexpected
results. The user must make sure that the GPIO pin is configured for asynchronous in this case.

8.4.2 Synchronization to SYSCLKOUT Only

This is the default qualification mode of all the pins at reset. In this mode, the input signal is only synchronized to
the system clock (SYSCLKOUT). Because the incoming signal is asynchronous, a SYSCLKOUT period of delay
is needed for the input to the device to be changed. No further qualification is performed on the signal.

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8.4.3 Qualification Using a Sampling Window

In this mode, the signal is first synchronized to the system clock (SYSCLKOUT) and then qualified by a
specified number of cycles before the input is allowed to change. Figure 8-2 and Figure 8-3 show how the input
qualification is performed to eliminate unwanted noise. Two parameters are specified by the user for this type
of qualification: 1) the sampling period, or how often the signal is sampled, and 2) the number of samples to be
taken.
Time between samples

GPxCTRL Reg

GPIOx SYNC Qualification Input Signal

Qualified By 3
or 6 Samples

GPxQSEL1/2
SYSCLKOUT
Number of Samples

Figure 8-2. Input Qualification Using a Sampling Window

Time between samples (sampling period):

To qualify the signal, the input signal is sampled at a regular period. The sampling period is specified by the user
and determines the time duration between samples, or how often the signal is sampled, relative to the CPU clock
(SYSCLKOUT).
The sampling period is specified by the qualification period (QUALPRDn) bits in the GPxCTRL register.
The sampling period is configurable in groups of 8 input signals. For example, GPIO0 to GPIO7 use
GPACTRL[QUALPRD0] setting and GPIO8 to GPIO15 use GPACTRL[QUALPRD1]. Table 8-1 and Table 8-2
show the relationship between the sampling period or sampling frequency and the GPxCTRL[QUALPRDn]
setting.
Table 8-1. Sampling Period
Sampling Period
If GPxCTRL[QUALPRDn] = 0 1 × TSYSCLKOUT
If GPxCTRL[QUALPRDn] ≠ 0 2 × GPxCTRL[QUALPRDn] × TSYSCLKOUT
Where TSYSCLKOUT is the period in time of SYSCLKOUT

Table 8-2. Sampling Frequency

Sampling Frequency
If GPxCTRL[QUALPRDn] = 0 fSYSCLKOUT
If GPxCTRL[QUALPRDn] ≠ 0 fSYSCLKOUT × 1 ÷ (2 × GPxCTRL[QUALPRDn])
Where fSYSCLKOUT is the frequency of SYSCLKOUT

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From these equations, the minimum and maximum time between samples can be calculated for a given
SYSCLKOUT frequency:

Example: Maximum Sampling Frequency:

If GPxCTRL[QUALPRDn] = 0
then the sampling frequency is fSYSCLKOUT
If, for example, fSYSCLKOUT = 60MHz
then the signal is sampled at 60MHz or one sample every 16.67ns.

Example: Minimum Sampling Frequency:

If GPxCTRL[QUALPRDn] = 0xFF (255)
then the sampling frequency is fSYSCLKOUT × 1 ÷ (2 × GPxCTRL[QUALPRDn])
If, for example, fSYSCLKOUT = 60MHz
then the signal is sampled at 60MHz × 1 ÷ (2 × 255) (117.647kHz) or one sample every 8.5μs.

Number of samples:
The number of times the signal is sampled is either three samples or six samples as specified in the qualification
selection (GPAQSEL1, GPAQSEL2, GPBQSEL1, and GPBQSEL2) registers. When three or six consecutive
cycles are the same, then the input change is passed through to the device.
Total Sampling-Window Width:
The sampling window is the time during which the input signal is sampled as shown in Figure 8-3. By using the
equation for the sampling period, along with the number of samples to be taken, the total width of the window
can be determined.
For the input qualifier to detect a change in the input, the level of the signal must be stable for the duration of the
sampling-window width or longer.
The number of sampling periods within the window is always one less than the number of samples taken. For
a three-sample window, the sampling-window width is two sampling-periods wide where the sampling period
is defined in Table 8-1. Likewise, for a six-sample window, the sampling-window width is five sampling-periods
wide. Table 8-3 and Table 8-4 show the calculations used to determine the total sampling-window width based
on GPxCTRL[QUALPRDn] and the number of samples taken.
Table 8-3. Case 1: Three-Sample Sampling-Window Width
Total Sampling-Window Width
If GPxCTRL[QUALPRDn] = 0 2 × TSYSCLKOUT
If GPxCTRL[QUALPRDn] ≠ 0 2 × 2 × GPxCTRL[QUALPRDn] × TSYSCLKOUT
Where TSYSCLKOUT is the period in time of SYSCLKOUT

Table 8-4. Case 2: Six-Sample Sampling-Window Width

Total Sampling-Window Width
If GPxCTRL[QUALPRDn] = 0 5 × TSYSCLKOUT
If GPxCTRL[QUALPRDn] ≠ 0 5 × 2 × GPxCTRL[QUALPRDn] × TSYSCLKOUT
Where TSYSCLKOUT is the period in time of SYSCLKOUT

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Note
The external signal change is asynchronous with respect to both the sampling period and
SYSCLKOUT. Due to the asynchronous nature of the external signal, the input must be held stable for
a time greater than the sampling-window width to make sure the logic detects a change in the signal.
The extra time required can be up to an additional sampling period + TSYSCLKOUT.
The required duration for an input signal to be stable for the qualification logic to detect a change is
described in the data sheet.

Example Qualification Window:

For the example shown in Figure 8-3, the input qualification has been configured as follows:
• GPxQSEL1/2 = 1,0. This indicates a six-sample qualification.
• GPxCTRL[QUALPRDn] = 1. The sampling period is tw(SP) = 2 × GPxCTRL[QUALPRDn] × TSYSCLKOUT = 2 x
TSYSCLKOUT.
This configuration results in the following:
• The width of the sampling window is:
tw(IQSW) = 5 × tw(SP) = 5 × 2 × GPxCTRL[QUALPRDn] × TSYSCLKOUT = 5 × 2 × TSYSCLKOUT
• If, for example, TSYSCLKOUT = 16.67ns, then the duration of the sampling window is:
Sampling period, tw(SP) = 2 x TSYSCLKOUT = 2 x 16.67ns = 33.3ns
Sampling window, tw(IQSW) = 5 × tw(SP) = 5 × 33.3ns = 166.7ns
• To account for the asynchronous nature of the input relative to the sampling period and SYSCLKOUT, up to
a single additional sampling period and SYSCLK period is required to detect a change in the input signal. For
this example:
tw(IQSW) + tw(SP) + TSYSCLKOUT = 166.7ns + 33.3ns + 16.67ns = 216.7ns
• In Figure 8-3, the glitch (A) is shorter then the qualification window and is ignored by the input qualifier.

Figure 8-3. Input Qualifier Clock Cycles

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8.5 USB Signals

The USB module on this device has an internal physical layer transceiver (PHY). The I/O signals are not normal
digital signals, and as a result, the signals do not connect to the pins through the normal GPIO mux path.
Instead, a special analog mux is used. To connect the USB signals to the device pins, set the GPyAMSEL bits
appropriately as shown in Table 8-5. Do not enable pullups or any other special pin option when using the USB
signals.
Table 8-5. USB I/O Signal Muxing
Signal GPIO AMSEL
USBDM 42 GPBAMSEL[10]
USBDP 43 GPBAMSEL[11]

8.6 SPI Signals

The SPI module on this device has a high-speed mode that enables 40 Mbps communication. To achieve the
highest possible speed, a special GPIO configuration is used on a single GPIO mux option for each SPI. These
GPIOs can also be used by the SPI when not in high-speed mode (HS_MODE = 0). Table 8-6 shows which
GPIOs have the special mux option to allow SPI high-speed mode.
To select these mux options, configure the GPyGMUX and GPyMUX registers as shown in Table 8-6.
Table 8-6. GPIO Configuration for High-Speed SPI
GPIO SPI Signal Mux Configuration
GPIO58 SPISIMOA GPBGMUX2[21:20]=11 GPBMUX2[21:20]=11
GPIO59 SPISOMIA GPBGMUX2[23:22]=11 GPBMUX2[23:22]=11
GPIO60 SPICLKA GPBGMUX2[25:24]=11 GPBMUX2[25:24]=11
GPIO61 SPISTEA GPBGMUX2[27:26]=11 GPBMUX2[27:26]=11

GPIO63 SPISIMOB GPBGMUX2[31:30]=11 GPBMUX2[31:30]=11

GPIO64 SPISOMIB GPCGMUX1[1:0]=11 GPCMUX1[1:0]=11
GPIO65 SPICLKB GPCGMUX1[3:2]=11 GPCMUX1[3:2]=11
GPIO66 SPISTEB GPCGMUX1[5:4]=11 GPCMUX1[5:4]=11

GPIO69 SPISIMOC GPCGMUX1[11:10]=11 GPCMUX1[11:10]=11

GPIO70 SPISOMIC GPCGMUX1[13:12]=11 GPCMUX1[13:12]=11
GPIO71 SPICLKC GPCGMUX1[15:14]=11 GPCMUX1[15:14]=11
GPIO72 SPISTEC GPCGMUX1[17:16]=11 GPCMUX1[17:16]=11

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8.7 GPIO and Peripheral Muxing

8.7.1 GPIO Muxing
Up to twelve different peripheral functions are multiplexed to each pin along with a general-purpose input/output (GPIO) function. This allows you to
choose the peripheral mix and pinout that works best for your particular application. Refer to Table 8-7 for muxing combinations and definitions.

Table 8-7. GPIO Muxed Pins

GPIO Mux Selection (1) (2)
GPIO Index 0, 4, 8, 12 1 2 3 5 6 7 15
GPyGMUXn. 00b, 01b, 10b,
00b 01b 11b
GPIOz = 11b
GPyMUXn.
00b 01b 10b 11b 01b 10b 11b 11b
GPIOz =
GPIO0 EPWM1A (O) SDAA (I/OD)
GPIO1 EPWM1B (O) MFSRB (I/O) SCLA (I/OD)
GPIO2 EPWM2A (O) OUTPUTXBAR1 (O) SDAB (I/OD)
GPIO3 EPWM2B (O) OUTPUTXBAR2 (O) MCLKRB (I/O) OUTPUTXBAR2 (O) SCLB (I/OD)
GPIO4 EPWM3A (O) OUTPUTXBAR3 (O) CANTXA (O)
GPIO5 EPWM3B (O) MFSRA (I/O) OUTPUTXBAR3 (O) CANRXA (I)
GPIO6 EPWM4A (O) OUTPUTXBAR4 (O) EXTSYNCOUT (O) EQEP3A (I) CANTXB (O)
GPIO7 EPWM4B (O) MCLKRA (I/O) OUTPUTXBAR5 (O) EQEP3B (I) CANRXB (I)
GPIO8 EPWM5A (O) CANTXB (O) ADCSOCAO (O) EQEP3S (I/O) SCITXDA (O)
GPIO9 EPWM5B (O) SCITXDB (O) OUTPUTXBAR6 (O) EQEP3I (I/O) SCIRXDA (I)
GPIO10 EPWM6A (O) CANRXB (I) ADCSOCBO (O) EQEP1A (I) SCITXDB (O) UPP-WAIT (I/O)
GPIO11 EPWM6B (O) SCIRXDB (I) OUTPUTXBAR7 (O) EQEP1B (I) SCIRXDB (I) UPP-START (I/O)
GPIO12 EPWM7A (O) CANTXB (O) MDXB (O) EQEP1S (I/O) SCITXDC (O) UPP-ENA (I/O)
GPIO13 EPWM7B (O) CANRXB (I) MDRB (I) EQEP1I (I/O) SCIRXDC (I) UPP-D7 (I/O)
GPIO14 EPWM8A (O) SCITXDB (O) MCLKXB (I/O) OUTPUTXBAR3 (O) UPP-D6 (I/O)
GPIO15 EPWM8B (O) SCIRXDB (I) MFSXB (I/O) OUTPUTXBAR4 (O) UPP-D5 (I/O)
GPIO16 SPISIMOA (I/O) CANTXB (O) OUTPUTXBAR7 (O) EPWM9A (O) SD1_D1 (I) UPP-D4 (I/O)
GPIO17 SPISOMIA (I/O) CANRXB (I) OUTPUTXBAR8 (O) EPWM9B (O) SD1_C1 (I) UPP-D3 (I/O)
GPIO18 SPICLKA (I/O) SCITXDB (O) CANRXA (I) EPWM10A (O) SD1_D2 (I) UPP-D2 (I/O)
GPIO19 SPISTEA (I/O) SCIRXDB (I) CANTXA (O) EPWM10B (O) SD1_C2 (I) UPP-D1 (I/O)
GPIO20 EQEP1A (I) MDXA (O) CANTXB (O) EPWM11A (O) SD1_D3 (I) UPP-D0 (I/O)
GPIO21 EQEP1B (I) MDRA (I) CANRXB (I) EPWM11B (O) SD1_C3 (I) UPP-CLK (I/O)
GPIO22 EQEP1S (I/O) MCLKXA (I/O) SCITXDB (O) EPWM12A (O) SPICLKB (I/O) SD1_D4 (I)
GPIO23 EQEP1I (I/O) MFSXA (I/O) SCIRXDB (I) EPWM12B (O) SPISTEB (I/O) SD1_C4 (I)
GPIO24 OUTPUTXBAR1 (O) EQEP2A (I) MDXB (O) SPISIMOB (I/O) SD2_D1 (I)

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Table 8-7. GPIO Muxed Pins (continued)

GPIO Mux Selection (1) (2)
GPIO Index 0, 4, 8, 12 1 2 3 5 6 7 15
GPyGMUXn. 00b, 01b, 10b,
00b 01b 11b
GPIOz = 11b
GPyMUXn.
00b 01b 10b 11b 01b 10b 11b 11b
GPIOz =
GPIO25 OUTPUTXBAR2 (O) EQEP2B (I) MDRB (I) SPISOMIB (I/O) SD2_C1 (I)
GPIO26 OUTPUTXBAR3 (O) EQEP2I (I/O) MCLKXB (I/O) OUTPUTXBAR3 (O) SPICLKB (I/O) SD2_D2 (I)
GPIO27 OUTPUTXBAR4 (O) EQEP2S (I/O) MFSXB (I/O) OUTPUTXBAR4 (O) SPISTEB (I/O) SD2_C2 (I)
GPIO28 SCIRXDA (I) EM1CS4 (O) OUTPUTXBAR5 (O) EQEP3A (I) SD2_D3 (I)
GPIO29 SCITXDA (O) EM1SDCKE (O) OUTPUTXBAR6 (O) EQEP3B (I) SD2_C3 (I)
GPIO30 CANRXA (I) EM1CLK (O) OUTPUTXBAR7 (O) EQEP3S (I/O) SD2_D4 (I)
GPIO31 CANTXA (O) EM1WE (O) OUTPUTXBAR8 (O) EQEP3I (I/O) SD2_C4 (I)
GPIO32 SDAA (I/OD) EM1CS0 (O)
GPIO33 SCLA (I/OD) EM1RNW (O)
GPIO34 OUTPUTXBAR1 (O) EM1CS2 (O) SDAB (I/OD)
GPIO35 SCIRXDA (I) EM1CS3 (O) SCLB (I/OD)
GPIO36 SCITXDA (O) EM1WAIT (I) CANRXA (I)
GPIO37 OUTPUTXBAR2 (O) EM1OE (O) CANTXA (O)
GPIO38 EM1A0 (O) SCITXDC (O) CANTXB (O)
GPIO39 EM1A1 (O) SCIRXDC (I) CANRXB (I)
GPIO40 EM1A2 (O) SDAB (I/OD)
GPIO41 EM1A3 (O) SCLB (I/OD)
GPIO42 SDAA (I/OD) SCITXDA (O)
GPIO43 SCLA (I/OD) SCIRXDA (I)
GPIO44 EM1A4 (O)
GPIO45 EM1A5 (O)
GPIO46 EM1A6 (O) SCIRXDD (I)
GPIO47 EM1A7 (O) SCITXDD (O)
GPIO48 OUTPUTXBAR3 (O) EM1A8 (O) SCITXDA (O) SD1_D1 (I)
GPIO49 OUTPUTXBAR4 (O) EM1A9 (O) SCIRXDA (I) SD1_C1 (I)
GPIO50 EQEP1A (I) EM1A10 (O) SPISIMOC (I/O) SD1_D2 (I)
GPIO51 EQEP1B (I) EM1A11 (O) SPISOMIC (I/O) SD1_C2 (I)
GPIO52 EQEP1S (I/O) EM1A12 (O) SPICLKC (I/O) SD1_D3 (I)
GPIO53 EQEP1I (I/O) EM1D31 (I/O) EM2D15 (I/O) SPISTEC (I/O) SD1_C3 (I)
GPIO54 SPISIMOA (I/O) EM1D30 (I/O) EM2D14 (I/O) EQEP2A (I) SCITXDB (O) SD1_D4 (I)
GPIO55 SPISOMIA (I/O) EM1D29 (I/O) EM2D13 (I/O) EQEP2B (I) SCIRXDB (I) SD1_C4 (I)

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Table 8-7. GPIO Muxed Pins (continued)

GPIO Mux Selection (1) (2)
GPIO Index 0, 4, 8, 12 1 2 3 5 6 7 15
GPyGMUXn. 00b, 01b, 10b,
00b 01b 11b
GPIOz = 11b
GPyMUXn.
00b 01b 10b 11b 01b 10b 11b 11b
GPIOz =
GPIO56 SPICLKA (I/O) EM1D28 (I/O) EM2D12 (I/O) EQEP2S (I/O) SCITXDC (O) SD2_D1 (I)
GPIO57 SPISTEA (I/O) EM1D27 (I/O) EM2D11 (I/O) EQEP2I (I/O) SCIRXDC (I) SD2_C1 (I)
GPIO58 MCLKRA (I/O) EM1D26 (I/O) EM2D10 (I/O) OUTPUTXBAR1 (O) SPICLKB (I/O) SD2_D2 (I) SPISIMOA(3) (I/O)
GPIO59 MFSRA (I/O) EM1D25 (I/O) EM2D9 (I/O) OUTPUTXBAR2 (O) SPISTEB (I/O) SD2_C2 (I) SPISOMIA(3) (I/O)
GPIO60 MCLKRB (I/O) EM1D24 (I/O) EM2D8 (I/O) OUTPUTXBAR3 (O) SPISIMOB (I/O) SD2_D3 (I) SPICLKA(3) (I/O)
GPIO61 MFSRB (I/O) EM1D23 (I/O) EM2D7 (I/O) OUTPUTXBAR4 (O) SPISOMIB (I/O) SD2_C3 (I) SPISTEA (3) (I/O)
GPIO62 SCIRXDC (I) EM1D22 (I/O) EM2D6 (I/O) EQEP3A (I) CANRXA (I) SD2_D4 (I)
GPIO63 SCITXDC (O) EM1D21 (I/O) EM2D5 (I/O) EQEP3B (I) CANTXA (O) SD2_C4 (I) SPISIMOB(3) (I/O)
GPIO64 EM1D20 (I/O) EM2D4 (I/O) EQEP3S (I/O) SCIRXDA (I) SPISOMIB(3) (I/O)
GPIO65 EM1D19 (I/O) EM2D3 (I/O) EQEP3I (I/O) SCITXDA (O) SPICLKB(3) (I/O)
GPIO66 EM1D18 (I/O) EM2D2 (I/O) SDAB (I/OD) SPISTEB (3) (I/O)
GPIO67 EM1D17 (I/O) EM2D1 (I/O)
GPIO68 EM1D16 (I/O) EM2D0 (I/O)
GPIO69 EM1D15 (I/O) SCLB (I/OD) SPISIMOC(3) (I/O)
GPIO70 EM1D14 (I/O) CANRXA (I) SCITXDB (O) SPISOMIC(3) (I/O)
GPIO71 EM1D13 (I/O) CANTXA (O) SCIRXDB (I) SPICLKC(3) (I/O)
GPIO72 EM1D12 (I/O) CANTXB (O) SCITXDC (O) SPISTEC (3) (I/O)
GPIO73 EM1D11 (I/O) XCLKOUT (O) CANRXB (I) SCIRXDC (I)
GPIO74 EM1D10 (I/O)
GPIO75 EM1D9 (I/O)
GPIO76 EM1D8 (I/O) SCITXDD (O)
GPIO77 EM1D7 (I/O) SCIRXDD (I)
GPIO78 EM1D6 (I/O) EQEP2A (I)
GPIO79 EM1D5 (I/O) EQEP2B (I)
GPIO80 EM1D4 (I/O) EQEP2S (I/O)
GPIO81 EM1D3 (I/O) EQEP2I (I/O)
GPIO82 EM1D2 (I/O)
GPIO83 EM1D1 (I/O)
GPIO84 SCITXDA (O) MDXB (O) MDXA (O)
GPIO85 EM1D0 (I/O) SCIRXDA (I) MDRB (I) MDRA (I)
GPIO86 EM1A13 (O) EM1CAS (O) SCITXDB (O) MCLKXB (I/O) MCLKXA (I/O)

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Table 8-7. GPIO Muxed Pins (continued)

GPIO Mux Selection (1) (2)
GPIO Index 0, 4, 8, 12 1 2 3 5 6 7 15
GPyGMUXn. 00b, 01b, 10b,
00b 01b 11b
GPIOz = 11b
GPyMUXn.
00b 01b 10b 11b 01b 10b 11b 11b
GPIOz =
GPIO87 EM1A14 (O) EM1RAS (O) SCIRXDB (I) MFSXB (I/O) MFSXA (I/O)
GPIO88 EM1A15 (O) EM1DQM0 (O)
GPIO89 EM1A16 (O) EM1DQM1 (O) SCITXDC (O)
GPIO90 EM1A17 (O) EM1DQM2 (O) SCIRXDC (I)
GPIO91 EM1A18 (O) EM1DQM3 (O) SDAA (I/OD)
GPIO92 EM1A19 (O) EM1BA1 (O) SCLA (I/OD)
GPIO93 EM1BA0 (O) SCITXDD (O)
GPIO94 SCIRXDD (I)
GPIO95
GPIO96 EM2DQM1 (O) EQEP1A (I)
GPIO97 EM2DQM0 (O) EQEP1B (I)
GPIO98 EM2A0 (O) EQEP1S (I/O)
GPIO99 EM2A1 (O) EQEP1I (I/O)
GPIO100 EM2A2 (O) EQEP2A (I) SPISIMOC (I/O)
GPIO101 EM2A3 (O) EQEP2B (I) SPISOMIC (I/O)
GPIO102 EM2A4 (O) EQEP2S (I/O) SPICLKC (I/O)
GPIO103 EM2A5 (O) EQEP2I (I/O) SPISTEC (I/O)
GPIO104 SDAA (I/OD) EM2A6 (O) EQEP3A (I) SCITXDD (O)
GPIO105 SCLA (I/OD) EM2A7 (O) EQEP3B (I) SCIRXDD (I)
GPIO106 EM2A8 (O) EQEP3S (I/O) SCITXDC (O)
GPIO107 EM2A9 (O) EQEP3I (I/O) SCIRXDC (I)
GPIO108 EM2A10 (O)
GPIO109 EM2A11 (O)
GPIO110 EM2WAIT (I)
GPIO111 EM2BA0 (O)
GPIO112 EM2BA1 (O)
GPIO113 EM2CAS (O)
GPIO114 EM2RAS (O)
GPIO115 EM2CS0 (O)
GPIO116 EM2CS2 (O)
GPIO117 EM2SDCKE (O)

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Table 8-7. GPIO Muxed Pins (continued)

GPIO Mux Selection (1) (2)
GPIO Index 0, 4, 8, 12 1 2 3 5 6 7 15
GPyGMUXn. 00b, 01b, 10b,
00b 01b 11b
GPIOz = 11b
GPyMUXn.
00b 01b 10b 11b 01b 10b 11b 11b
GPIOz =
GPIO118 EM2CLK (O)
GPIO119 EM2RNW (O)
GPIO120 EM2WE (O) USB0PFLT
GPIO121 EM2OE (O) USB0EPEN
GPIO122 SPISIMOC (I/O) SD1_D1 (I)
GPIO123 SPISOMIC (I/O) SD1_C1 (I)
GPIO124 SPICLKC (I/O) SD1_D2 (I)
GPIO125 SPISTEC (I/O) SD1_C2 (I)
GPIO126 SD1_D3 (I)
GPIO127 SD1_C3 (I)
GPIO128 SD1_D4 (I)
GPIO129 SD1_C4 (I)
GPIO130 SD2_D1 (I)
GPIO131 SD2_C1 (I)
GPIO132 SD2_D2 (I)
GPIO133/
SD2_C2 (I)
AUXCLKIN
GPIO134 SD2_D3 (I)
GPIO135 SCITXDA (O) SD2_C3 (I)
GPIO136 SCIRXDA (I) SD2_D4 (I)
GPIO137 SCITXDB (O) SD2_C4 (I)
GPIO138 SCIRXDB (I)
GPIO139 SCIRXDC (I)
GPIO140 SCITXDC (O)
GPIO141 SCIRXDD (I)
GPIO142 SCITXDD (O)
GPIO143
GPIO144
GPIO145 EPWM1A (O)
GPIO146 EPWM1B (O)
GPIO147 EPWM2A (O)

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Table 8-7. GPIO Muxed Pins (continued)

GPIO Mux Selection (1) (2)
GPIO Index 0, 4, 8, 12 1 2 3 5 6 7 15
GPyGMUXn. 00b, 01b, 10b,
00b 01b 11b
GPIOz = 11b
GPyMUXn.
00b 01b 10b 11b 01b 10b 11b 11b
GPIOz =
GPIO148 EPWM2B (O)
GPIO149 EPWM3A (O)
GPIO150 EPWM3B (O)
GPIO151 EPWM4A (O)
GPIO152 EPWM4B (O)
GPIO153 EPWM5A (O)
GPIO154 EPWM5B (O)
GPIO155 EPWM6A (O)
GPIO156 EPWM6B (O)
GPIO157 EPWM7A (O)
GPIO158 EPWM7B (O)
GPIO159 EPWM8A (O)
GPIO160 EPWM8B (O)
GPIO161 EPWM9A (O)
GPIO162 EPWM9B (O)
GPIO163 EPWM10A (O)
GPIO164 EPWM10B (O)
GPIO165 EPWM11A (O)
GPIO166 EPWM11B (O)
GPIO167 EPWM12A (O)
GPIO168 EPWM12B (O)

(1) (I) = Input, (O) = Output, (OD) = Open Drain

(2) GPIO Index settings of 9, 10, 11, 13, and 14 are reserved.
(3) High-Speed SPI-enabled GPIO mux option. This pin mux option is required when using the SPI in High-Speed Mode (HS_MODE = 1 in SPICCR). This mux option is still available when
not using the SPI in High-Speed Mode (HS_MODE = 0 in SPICCR).

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8.7.2 Peripheral Muxing

For example, multiplexing for the GPIO6 pin is controlled by writing to GPAGMUX[13:12] and GPAMUX[13:12].
By writing to these bits, GPIO6 is configured as either a general-purpose digital I/O or one of several different
peripheral functions. An example of GPyGMUX and GPyMUX selection and options for a single GPIO are shown
in Table 8-8.

Note
The following table is for example only. Refer to the device data sheet to check the availability of
GPIO6 on this device. If GPIO6 is available, the functions mentioned in the table may not match the
actual functions available. See Section 8.7.1 for correct list of GPIOs and corresponding mux options
for this device.

Table 8-8. GPIO and Peripheral Muxing

GPAGMUX1[13:12] GPAMUX1[13:12] Pin Functionality
00 00 GPIO6
00 01 Peripheral 1
00 10 Peripheral 2
00 11 Peripheral 3
01 00 GPIO6
01 01 Peripheral 4
01 10 Peripheral 5
01 11
10 00 GPIO6
10 01
10 10 Peripheral 6
10 11 Peripheral 7
11 00 GPIO6
11 01 Peripheral 8
11 10 Peripheral 9
11 11 Peripheral 10

The devices have different multiplexing schemes. If a peripheral is not available on a particular device, that mux
selection is reserved on that device and must not be used.

CAUTION
If a reserved GPIO mux configuration that is not mapped to either a peripheral or GPIO mode is
selected, the state of the pin is undefined and the pin is driven. Unimplemented configurations are
for future expansion and must not be selected. In the device mux table (see the data sheet), these
options are indicated as Reserved or left blank.

Some peripherals can be assigned to more than one pin by way of the mux registers. For example,
OUTPUTXBAR1 can be assigned to GPIOs p, q, or r (where p, q, and r are example GPIO numbers), depending
on individual system requirements. An example of this is shown in Table 8-9.

Note
The following table is for example only. Bit ranges cannot correspond to OUTPUTXBAR1 on this
device. See Section 8.7.1 for correct list of GPIOs and corresponding mux options for this device.

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If none or more then one of the GPIO pins is configured as peripheral input pins, then that GPIO is set to a
hard-wired default value.
Table 8-9. Peripheral Muxing (Multiple Pins Assigned)
GMUX Configuration MUX Configuration
Choice 1: GPIOp GPyGMUX1[5:4]=01 GPyMUX1[5:4]=01
or Choice 2: GPIOq GPyGMUX2[17:16]=00 GPyMUX2[17:16]=01
or Choice 3: GPIOr GPyGMUX1[7:6]=01 GPyMUX1[7:6]=01

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8.8 Internal Pullup Configuration Requirements

On reset, GPIOs are in input mode and have the internal pullups disabled. An un-driven input can float to a
mid-rail voltage and cause wasted shoot-through current on the input buffer. The user must always put each
GPIO in one of these configurations:
• Input mode and driven on the board by another component to a level above Vih or below Vil
• Input mode with GPIO internal pullup enabled
• Output mode
On devices with lesser pin count packages, pull-ups on unbonded GPIOs are by default enabled to prevent
floating inputs. The user must take care to avoid disabling these pullups in the application code.
On devices with larger pin count packages, the pullups for any internally unbonded GPIO must be enabled
to prevent floating inputs. TI has provided functions in controlSUITE/C2000Ware that users can call to enable
the pullup on any unbonded GPIO for the package in use. This function, GPIO_EnabledUnbondedIOPullups(),
resides in the (Device)_Sysctrl.c file and is called by default from InitSysCtrl(). The user must take care to avoid
disabling these pullups in the application code.

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8.9 Software
8.9.1 GPIO Examples
NOTE: These examples are located in the C2000Ware installation at the following location:
C2000Ware_VERSION#/driverlib/DEVICE_GPN/examples/CORE_IF_MULTICORE/gpio
Cloud access to these examples is available at the following link: dev.ti.com C2000Ware Examples.
8.9.1.1 Device GPIO Setup
FILE: gpio_ex1_setup.c
Configures the device GPIO into two different configurations This code is verbose to illustrate how the GPIO
could be setup. In a real application, lines of code can be combined for improved code size and efficiency.
This example only sets-up the GPIO. Nothing is actually done with the pins after setup.
In general:
• All pullup resistors are enabled. For ePWMs this may not be desired.
• Input qual for communication ports (CAN, SPI, SCI, I2C) is asynchronous
• Input qual for Trip pins (TZ) is asynchronous
• Input qual for eCAP and eQEP signals is synch to SYSCLKOUT
• Input qual for some I/O's and __interrupts may have a sampling window
8.9.1.2 Device GPIO Toggle
FILE: gpio_ex2_toggle.c
Configures the device GPIO through the sysconfig file. The GPIO pin is toggled in the infinite loop. In order to
migrate the project within syscfg to any device, click the swtich button under the device view and select your
corresponding device to migrate, saving the project will auto-migrate your project settings.
: This example project has support for migration across our C2000 device families. If you are wanting to build
this project from launchpad or controlCARD, please specify in the .syscfg file the board you're using. At any time
you can select another device to migrate this example.
8.9.1.3 Device GPIO Interrupt
FILE: gpio_ex3_interrupt.c
Configures the device GPIOs through the sysconfig file. One GPIO output pin, and one GPIO input pin is
configured. The example then configures the GPIO input pin to be the source of an external interrupt which
toggles the GPIO output pin.
8.9.2 LED Examples
NOTE: These examples are located in the C2000Ware installation at the following location:
C2000Ware_VERSION#/driverlib/DEVICE_GPN/examples/CORE_IF_MULTICORE/led
Cloud access to these examples is available at the following link: dev.ti.com C2000Ware Examples.

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8.10 GPIO Registers

This section describes the General-Purpose Input/Output Registers.
Table 8-10 provides both specific and generic terms for registers described in this section and throughout this
chapter.
Table 8-10. Specific versus Generic Terminology for Registers
Specific Term Generic Term Used in the Document
GPAQSEL1, GPAQSEL2, GPBQSEL1, GPBQSEL2, GPCQSEL1, GPCQSEL2,
GPxQSEL
GPDQSEL1, GPDQSEL2, GPEQSEL1, GPEQSEL2, GPFQSEL1, GPFQSEL2
GPACTRL, GPBCTRL, GPCCTRL, GPDCTRL, GPECTRL, GPFCTRL GPxCTRL
GPADIR, GPBDIR, GPCDIR, GPDDIR, GPEDIR, GPFDIR GPxDIR
GPAPUD, GPBPUD, GPCPUD, GPDPUD, GPEPUD, GPFPUD GPxPUD
GPAINV, GPBINV, GPCINV, GPDINV, GPEINV, GPFINV GPxINV
GPAODR, GPBODR, GPCODR, GPDODR, GPEODR, GPFODR, GPxODR GPxODR
GPALOCK, GPBLOCK, GPCLOCK, GPDLOCK, GPELOCK, GPFLOCK GPxLOCK
GPACR, GPBCR, GPCCR, GPDCR, GPECR, GPFCR GPxCR
GPAMUX1, GPAMUX2, GPBMUX1, GPBMUX2, GPCMUX1, GPCMUX2,
GPxMUX
GPDMUX1, GPDMUX2, GPEMUX1, GPEMUX2, GPFMUX1, GPFMUX2
GPAGMUX1, GPAGMUX2, GPBGMUX1, GPBGMUX2, GPCGMUX1,
GPCGMUX2, GPDGMUX1, GPDGMUX2, GPEGMUX1, GPEGMUX2, GPxGMUX
GPFGMUX1, GPFGMUX2
GPADAT, GPBDAT, GPCDAT, GPDDAT, GPEDAT, GPFDAT GPxDAT

8.10.1 GPIO Base Addresses

Table 8-11. GPIO Base Address Table
Device Registers Register Name Start Address End Address
GpioCtrlRegs(1) GPIO_CTRL_REGS 0x0000_7C00 0x0000_7D7F
GpioDataRegs GPIO_DATA_REGS 0x0000_7F00 0x0000_7F2F

(1) Only available on CPU1.

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8.10.2 GPIO_CTRL_REGS Registers

Table 8-12 lists the memory-mapped registers for the GPIO_CTRL_REGS registers. All register offset addresses
not listed in Table 8-12 should be considered as reserved locations and the register contents should not be
modified.
Table 8-12. GPIO_CTRL_REGS Registers
Offset Acronym Register Name Write Protection Section
0h GPACTRL GPIO A Qualification Sampling Period Control EALLOW Go
(GPIO0 to 31)
2h GPAQSEL1 GPIO A Qualifier Select 1 Register (GPIO0 to 15) EALLOW Go
4h GPAQSEL2 GPIO A Qualifier Select 2 Register (GPIO16 to EALLOW Go
31)
6h GPAMUX1 GPIO A Mux 1 Register (GPIO0 to 15) EALLOW Go
8h GPAMUX2 GPIO A Mux 2 Register (GPIO16 to 31) EALLOW Go
Ah GPADIR GPIO A Direction Register (GPIO0 to 31) EALLOW Go
Ch GPAPUD GPIO A Pull Up Disable Register (GPIO0 to 31) EALLOW Go
10h GPAINV GPIO A Input Polarity Invert Registers (GPIO0 to EALLOW Go
31)
12h GPAODR GPIO A Open Drain Output Register (GPIO0 to EALLOW Go
GPIO31)
20h GPAGMUX1 GPIO A Peripheral Group Mux (GPIO0 to 15) EALLOW Go
22h GPAGMUX2 GPIO A Peripheral Group Mux (GPIO16 to 31) EALLOW Go
28h GPACSEL1 GPIO A Core Select Register (GPIO0 to 7) EALLOW Go
2Ah GPACSEL2 GPIO A Core Select Register (GPIO8 to 15) EALLOW Go
2Ch GPACSEL3 GPIO A Core Select Register (GPIO16 to 23) EALLOW Go
2Eh GPACSEL4 GPIO A Core Select Register (GPIO24 to 31) EALLOW Go
3Ch GPALOCK GPIO A Lock Configuration Register (GPIO0 to EALLOW Go
31)
3Eh GPACR GPIO A Lock Commit Register (GPIO0 to 31) EALLOW Go
40h GPBCTRL GPIO B Qualification Sampling Period Control EALLOW Go
(GPIO32 to 63)
42h GPBQSEL1 GPIO B Qualifier Select 1 Register (GPIO32 to EALLOW Go
47)
44h GPBQSEL2 GPIO B Qualifier Select 2 Register (GPIO48 to EALLOW Go
63)
46h GPBMUX1 GPIO B Mux 1 Register (GPIO32 to 47) EALLOW Go
48h GPBMUX2 GPIO B Mux 2 Register (GPIO48 to 63) EALLOW Go
4Ah GPBDIR GPIO B Direction Register (GPIO32 to 63) EALLOW Go
4Ch GPBPUD GPIO B Pull Up Disable Register (GPIO32 to 63) EALLOW Go
50h GPBINV GPIO B Input Polarity Invert Registers (GPIO32 EALLOW Go
to 63)
52h GPBODR GPIO B Open Drain Output Register (GPIO32 to EALLOW Go
GPIO63)
54h GPBAMSEL GPIO B Analog Mode Select register (GPIO32 to EALLOW Go
GPIO63)
60h GPBGMUX1 GPIO B Peripheral Group Mux (GPIO32 to 47) EALLOW Go
62h GPBGMUX2 GPIO B Peripheral Group Mux (GPIO48 to 63) EALLOW Go
68h GPBCSEL1 GPIO B Core Select Register (GPIO32 to 39) EALLOW Go
6Ah GPBCSEL2 GPIO B Core Select Register (GPIO40 to 47) EALLOW Go
6Ch GPBCSEL3 GPIO B Core Select Register (GPIO48 to 55) EALLOW Go
6Eh GPBCSEL4 GPIO B Core Select Register (GPIO56 to 63) EALLOW Go

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Table 8-12. GPIO_CTRL_REGS Registers (continued)

Offset Acronym Register Name Write Protection Section
7Ch GPBLOCK GPIO B Lock Configuration Register (GPIO32 to EALLOW Go
63)
7Eh GPBCR GPIO B Lock Commit Register (GPIO32 to 63) EALLOW Go
80h GPCCTRL GPIO C Qualification Sampling Period Control EALLOW Go
(GPIO64 to 95)
82h GPCQSEL1 GPIO C Qualifier Select 1 Register (GPIO64 to EALLOW Go
79)
84h GPCQSEL2 GPIO C Qualifier Select 2 Register (GPIO80 to EALLOW Go
95)
86h GPCMUX1 GPIO C Mux 1 Register (GPIO64 to 79) EALLOW Go
88h GPCMUX2 GPIO C Mux 2 Register (GPIO80 to 95) EALLOW Go
8Ah GPCDIR GPIO C Direction Register (GPIO64 to 95) EALLOW Go
8Ch GPCPUD GPIO C Pull Up Disable Register (GPIO64 to 95) EALLOW Go
90h GPCINV GPIO C Input Polarity Invert Registers (GPIO64 EALLOW Go
to 95)
92h GPCODR GPIO C Open Drain Output Register (GPIO64 to EALLOW Go
GPIO95)
A0h GPCGMUX1 GPIO C Peripheral Group Mux (GPIO64 to 79) EALLOW Go
A2h GPCGMUX2 GPIO C Peripheral Group Mux (GPIO80 to 95) EALLOW Go
A8h GPCCSEL1 GPIO C Core Select Register (GPIO64 to 71) EALLOW Go
AAh GPCCSEL2 GPIO C Core Select Register (GPIO72 to 79) EALLOW Go
ACh GPCCSEL3 GPIO C Core Select Register (GPIO80 to 87) EALLOW Go
AEh GPCCSEL4 GPIO C Core Select Register (GPIO88 to 95) EALLOW Go
BCh GPCLOCK GPIO C Lock Configuration Register (GPIO64 to EALLOW Go
95)
BEh GPCCR GPIO C Lock Commit Register (GPIO64 to 95) EALLOW Go
C0h GPDCTRL GPIO D Qualification Sampling Period Control EALLOW Go
(GPIO96 to 127)
C2h GPDQSEL1 GPIO D Qualifier Select 1 Register (GPIO96 to EALLOW Go
111)
C4h GPDQSEL2 GPIO D Qualifier Select 2 Register (GPIO112 to EALLOW Go
127)
C6h GPDMUX1 GPIO D Mux 1 Register (GPIO96 to 111) EALLOW Go
C8h GPDMUX2 GPIO D Mux 2 Register (GPIO112 to 127) EALLOW Go
CAh GPDDIR GPIO D Direction Register (GPIO96 to 127) EALLOW Go
CCh GPDPUD GPIO D Pull Up Disable Register (GPIO96 to EALLOW Go
127)
D0h GPDINV GPIO D Input Polarity Invert Registers (GPIO96 EALLOW Go
to 127)
D2h GPDODR GPIO D Open Drain Output Register (GPIO96 to EALLOW Go
GPIO127)
E0h GPDGMUX1 GPIO D Peripheral Group Mux (GPIO96 to 111) EALLOW Go
E2h GPDGMUX2 GPIO D Peripheral Group Mux (GPIO112 to 127) EALLOW Go
E8h GPDCSEL1 GPIO D Core Select Register (GPIO96 to 103) EALLOW Go
EAh GPDCSEL2 GPIO D Core Select Register (GPIO104 to 111) EALLOW Go
ECh GPDCSEL3 GPIO D Core Select Register (GPIO112 to 119) EALLOW Go
EEh GPDCSEL4 GPIO D Core Select Register (GPIO120 to 127) EALLOW Go
FCh GPDLOCK GPIO D Lock Configuration Register (GPIO96 to EALLOW Go
127)

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Table 8-12. GPIO_CTRL_REGS Registers (continued)

Offset Acronym Register Name Write Protection Section
FEh GPDCR GPIO D Lock Commit Register (GPIO96 to 127) EALLOW Go
100h GPECTRL GPIO E Qualification Sampling Period Control EALLOW Go
(GPIO128 to 159)
102h GPEQSEL1 GPIO E Qualifier Select 1 Register (GPIO128 to EALLOW Go
143)
104h GPEQSEL2 GPIO E Qualifier Select 2 Register (GPIO144 to EALLOW Go
159)
106h GPEMUX1 GPIO E Mux 1 Register (GPIO128 to 143) EALLOW Go
108h GPEMUX2 GPIO E Mux 2 Register (GPIO144 to 159) EALLOW Go
10Ah GPEDIR GPIO E Direction Register (GPIO128 to 159) EALLOW Go
10Ch GPEPUD GPIO E Pull Up Disable Register (GPIO128 to EALLOW Go
159)
110h GPEINV GPIO E Input Polarity Invert Registers (GPIO128 EALLOW Go
to 159)
112h GPEODR GPIO E Open Drain Output Register (GPIO128 to EALLOW Go
GPIO159)
120h GPEGMUX1 GPIO E Peripheral Group Mux (GPIO128 to 143) EALLOW Go
122h GPEGMUX2 GPIO E Peripheral Group Mux (GPIO144 to 159) EALLOW Go
128h GPECSEL1 GPIO E Core Select Register (GPIO128 to 135) EALLOW Go
12Ah GPECSEL2 GPIO E Core Select Register (GPIO136 to 143) EALLOW Go
12Ch GPECSEL3 GPIO E Core Select Register (GPIO144 to 151) EALLOW Go
12Eh GPECSEL4 GPIO E Core Select Register (GPIO152 to 159) EALLOW Go
13Ch GPELOCK GPIO E Lock Configuration Register (GPIO128 to EALLOW Go
159)
13Eh GPECR GPIO E Lock Commit Register (GPIO128 to 159) EALLOW Go
140h GPFCTRL GPIO F Qualification Sampling Period Control EALLOW Go
(GPIO160 to 168)
142h GPFQSEL1 GPIO F Qualifier Select 1 Register (GPIO160 to EALLOW Go
168)
146h GPFMUX1 GPIO F Mux 1 Register (GPIO160 to 168) EALLOW Go
14Ah GPFDIR GPIO F Direction Register (GPIO160 to 168) EALLOW Go
14Ch GPFPUD GPIO F Pull Up Disable Register (GPIO160 to EALLOW Go
168)
150h GPFINV GPIO F Input Polarity Invert Registers (GPIO160 EALLOW Go
to 168)
152h GPFODR GPIO F Open Drain Output Register (GPIO160 to EALLOW Go
GPIO168)
160h GPFGMUX1 GPIO F Peripheral Group Mux (GPIO160 to 168) EALLOW Go
168h GPFCSEL1 GPIO F Core Select Register (GPIO160 to 167) EALLOW Go
16Ah GPFCSEL2 GPIO F Core Select Register (GPIO168) EALLOW Go
17Ch GPFLOCK GPIO F Lock Configuration Register (GPIO160 to EALLOW Go
168)
17Eh GPFCR GPIO F Lock Commit Register (GPIO160 to 168) EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 8-13 shows the codes that are used for
access types in this section.
Table 8-13. GPIO_CTRL_REGS Access Type Codes
Access Type Code Description
Read Type

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Table 8-13. GPIO_CTRL_REGS Access Type Codes (continued)

Access Type Code Description
R R Read
Write Type
W W Write
WOnce W Write
Once Write once
Reset or Default Value
-n Value after reset or the default value
Register Array Variables
i,j,k,l,m,n When these variables are used in a register name,
an offset, or an address, they refer to the value of a
register array where the register is part of a group
of repeating registers. The register groups form a
hierarchical structure and the array is represented
with a formula.
y When this variable is used in a register name, an
offset, or an address it refers to the value of a
register array.

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8.10.2.1 GPACTRL Register (Offset = 0h) [Reset = 00000000h]

GPACTRL is shown in Figure 8-4 and described in Table 8-14.
Return to the Summary Table.
GPIO A Qualification Sampling Period Control (GPIO0 to 31)
Figure 8-4. GPACTRL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
QUALPRD3 QUALPRD2 QUALPRD1 QUALPRD0
R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-14. GPACTRL Register Field Descriptions

Bit Field Type Reset Description
31-24 QUALPRD3 R/W 0h Qualification sampling period for GPIO24 to GPIO31:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn
23-16 QUALPRD2 R/W 0h Qualification sampling period for GPIO16 to GPIO23:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn
15-8 QUALPRD1 R/W 0h Qualification sampling period for GPIO8 to GPIO15:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn
7-0 QUALPRD0 R/W 0h Qualification sampling period for GPIO0 to GPIO7:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn

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8.10.2.2 GPAQSEL1 Register (Offset = 2h) [Reset = 00000000h]

GPAQSEL1 is shown in Figure 8-5 and described in Table 8-15.
Return to the Summary Table.
GPIO A Qualifier Select 1 Register (GPIO0 to 15)
Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)
Figure 8-5. GPAQSEL1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-15. GPAQSEL1 Register Field Descriptions

Bit Field Type Reset Description
31-30 GPIO15 R/W 0h Input qualification type
Reset type: SYSRSn
29-28 GPIO14 R/W 0h Input qualification type
Reset type: SYSRSn
27-26 GPIO13 R/W 0h Input qualification type
Reset type: SYSRSn
25-24 GPIO12 R/W 0h Input qualification type
Reset type: SYSRSn
23-22 GPIO11 R/W 0h Input qualification type
Reset type: SYSRSn
21-20 GPIO10 R/W 0h Input qualification type
Reset type: SYSRSn
19-18 GPIO9 R/W 0h Input qualification type
Reset type: SYSRSn
17-16 GPIO8 R/W 0h Input qualification type
Reset type: SYSRSn
15-14 GPIO7 R/W 0h Input qualification type
Reset type: SYSRSn
13-12 GPIO6 R/W 0h Input qualification type
Reset type: SYSRSn
11-10 GPIO5 R/W 0h Input qualification type
Reset type: SYSRSn
9-8 GPIO4 R/W 0h Input qualification type
Reset type: SYSRSn
7-6 GPIO3 R/W 0h Input qualification type
Reset type: SYSRSn
5-4 GPIO2 R/W 0h Input qualification type
Reset type: SYSRSn
3-2 GPIO1 R/W 0h Input qualification type
Reset type: SYSRSn

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Table 8-15. GPAQSEL1 Register Field Descriptions (continued)

Bit Field Type Reset Description
1-0 GPIO0 R/W 0h Input qualification type
Reset type: SYSRSn

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8.10.2.3 GPAQSEL2 Register (Offset = 4h) [Reset = 00000000h]

GPAQSEL2 is shown in Figure 8-6 and described in Table 8-16.
Return to the Summary Table.
GPIO A Qualifier Select 2 Register (GPIO16 to 31)
Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)
Figure 8-6. GPAQSEL2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO31 GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-16. GPAQSEL2 Register Field Descriptions

Bit Field Type Reset Description
31-30 GPIO31 R/W 0h Input qualification type
Reset type: SYSRSn
29-28 GPIO30 R/W 0h Input qualification type
Reset type: SYSRSn
27-26 GPIO29 R/W 0h Input qualification type
Reset type: SYSRSn
25-24 GPIO28 R/W 0h Input qualification type
Reset type: SYSRSn
23-22 GPIO27 R/W 0h Input qualification type
Reset type: SYSRSn
21-20 GPIO26 R/W 0h Input qualification type
Reset type: SYSRSn
19-18 GPIO25 R/W 0h Input qualification type
Reset type: SYSRSn
17-16 GPIO24 R/W 0h Input qualification type
Reset type: SYSRSn
15-14 GPIO23 R/W 0h Input qualification type
Reset type: SYSRSn
13-12 GPIO22 R/W 0h Input qualification type
Reset type: SYSRSn
11-10 GPIO21 R/W 0h Input qualification type
Reset type: SYSRSn
9-8 GPIO20 R/W 0h Input qualification type
Reset type: SYSRSn
7-6 GPIO19 R/W 0h Input qualification type
Reset type: SYSRSn
5-4 GPIO18 R/W 0h Input qualification type
Reset type: SYSRSn
3-2 GPIO17 R/W 0h Input qualification type
Reset type: SYSRSn

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Table 8-16. GPAQSEL2 Register Field Descriptions (continued)

Bit Field Type Reset Description
1-0 GPIO16 R/W 0h Input qualification type
Reset type: SYSRSn

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8.10.2.4 GPAMUX1 Register (Offset = 6h) [Reset = 00000000h]

GPAMUX1 is shown in Figure 8-7 and described in Table 8-17.
Return to the Summary Table.
GPIO A Mux 1 Register (GPIO0 to 15)
Defines pin-muxing selection for GPIO.
Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate peripheral
selects being mapped to the GPIO.
Figure 8-7. GPAMUX1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-17. GPAMUX1 Register Field Descriptions

Bit Field Type Reset Description
31-30 GPIO15 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
29-28 GPIO14 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
27-26 GPIO13 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
25-24 GPIO12 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
23-22 GPIO11 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
21-20 GPIO10 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
19-18 GPIO9 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
17-16 GPIO8 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
15-14 GPIO7 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
13-12 GPIO6 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
11-10 GPIO5 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
9-8 GPIO4 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
7-6 GPIO3 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
5-4 GPIO2 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
3-2 GPIO1 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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Table 8-17. GPAMUX1 Register Field Descriptions (continued)

Bit Field Type Reset Description
1-0 GPIO0 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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8.10.2.5 GPAMUX2 Register (Offset = 8h) [Reset = 00000000h]

GPAMUX2 is shown in Figure 8-8 and described in Table 8-18.
Return to the Summary Table.
GPIO A Mux 2 Register (GPIO16 to 31)
Defines pin-muxing selection for GPIO.
Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate peripheral
selects being mapped to the GPIO.
Figure 8-8. GPAMUX2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO31 GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-18. GPAMUX2 Register Field Descriptions

Bit Field Type Reset Description
31-30 GPIO31 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
29-28 GPIO30 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
27-26 GPIO29 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
25-24 GPIO28 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
23-22 GPIO27 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
21-20 GPIO26 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
19-18 GPIO25 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
17-16 GPIO24 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
15-14 GPIO23 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
13-12 GPIO22 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
11-10 GPIO21 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
9-8 GPIO20 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
7-6 GPIO19 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
5-4 GPIO18 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
3-2 GPIO17 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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Table 8-18. GPAMUX2 Register Field Descriptions (continued)

Bit Field Type Reset Description
1-0 GPIO16 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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8.10.2.6 GPADIR Register (Offset = Ah) [Reset = 00000000h]

GPADIR is shown in Figure 8-9 and described in Table 8-19.
Return to the Summary Table.
GPIO A Direction Register (GPIO0 to 31)
Controls direction of GPIO pins when the specified pin is configured in GPIO mode.
0: Configures pin as input.
1: Configures pin as output.
Reading the register returns the current value of the register setting.
Figure 8-9. GPADIR Register
31 30 29 28 27 26 25 24
GPIO31 GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-19. GPADIR Register Field Descriptions

Bit Field Type Reset Description
31 GPIO31 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
30 GPIO30 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
29 GPIO29 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
28 GPIO28 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
27 GPIO27 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
26 GPIO26 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
25 GPIO25 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
24 GPIO24 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
23 GPIO23 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
22 GPIO22 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
21 GPIO21 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn

1020 TMS320F2837xD Dual-Core Real-Time Microcontrollers SPRUHM8K – DECEMBER 2013 – REVISED MAY 2024
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Table 8-19. GPADIR Register Field Descriptions (continued)

Bit Field Type Reset Description
20 GPIO20 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
19 GPIO19 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
18 GPIO18 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
17 GPIO17 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
16 GPIO16 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
15 GPIO15 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
14 GPIO14 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
13 GPIO13 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
12 GPIO12 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
11 GPIO11 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
10 GPIO10 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
9 GPIO9 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
8 GPIO8 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
7 GPIO7 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
6 GPIO6 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
5 GPIO5 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
4 GPIO4 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
3 GPIO3 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
2 GPIO2 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
1 GPIO1 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
0 GPIO0 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn

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8.10.2.7 GPAPUD Register (Offset = Ch) [Reset = FFFFFFFFh]

GPAPUD is shown in Figure 8-10 and described in Table 8-20.
Return to the Summary Table.
GPIO A Pull Up Disable Register (GPIO0 to 31)
Disables the Pull-Up on GPIO.
0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Figure 8-10. GPAPUD Register
31 30 29 28 27 26 25 24
GPIO31 GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

23 22 21 20 19 18 17 16
GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

15 14 13 12 11 10 9 8
GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

7 6 5 4 3 2 1 0
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

Table 8-20. GPAPUD Register Field Descriptions

Bit Field Type Reset Description
31 GPIO31 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
30 GPIO30 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
29 GPIO29 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
28 GPIO28 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
27 GPIO27 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
26 GPIO26 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
25 GPIO25 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
24 GPIO24 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
23 GPIO23 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
22 GPIO22 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
21 GPIO21 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn

1022 TMS320F2837xD Dual-Core Real-Time Microcontrollers SPRUHM8K – DECEMBER 2013 – REVISED MAY 2024
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Table 8-20. GPAPUD Register Field Descriptions (continued)

Bit Field Type Reset Description
20 GPIO20 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
19 GPIO19 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
18 GPIO18 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
17 GPIO17 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
16 GPIO16 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
15 GPIO15 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
14 GPIO14 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
13 GPIO13 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
12 GPIO12 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
11 GPIO11 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
10 GPIO10 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
9 GPIO9 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
8 GPIO8 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
7 GPIO7 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
6 GPIO6 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
5 GPIO5 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
4 GPIO4 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
3 GPIO3 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
2 GPIO2 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
1 GPIO1 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
0 GPIO0 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn

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8.10.2.8 GPAINV Register (Offset = 10h) [Reset = 00000000h]

GPAINV is shown in Figure 8-11 and described in Table 8-21.
Return to the Summary Table.
GPIO A Input Polarity Invert Registers (GPIO0 to 31)
Selects between non-inverted and inverted GPIO input to the device.
0: selects non-inverted GPIO input
1: selects inverted GPIO input
Reading the register returns the current value of the register setting.
Figure 8-11. GPAINV Register
31 30 29 28 27 26 25 24
GPIO31 GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-21. GPAINV Register Field Descriptions

Bit Field Type Reset Description
31 GPIO31 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
30 GPIO30 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
29 GPIO29 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
28 GPIO28 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
27 GPIO27 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
26 GPIO26 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
25 GPIO25 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
24 GPIO24 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
23 GPIO23 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
22 GPIO22 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
21 GPIO21 R/W 0h Input inversion control for this pin
Reset type: SYSRSn

1024 TMS320F2837xD Dual-Core Real-Time Microcontrollers SPRUHM8K – DECEMBER 2013 – REVISED MAY 2024
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Table 8-21. GPAINV Register Field Descriptions (continued)

Bit Field Type Reset Description
20 GPIO20 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
19 GPIO19 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
18 GPIO18 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
17 GPIO17 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
16 GPIO16 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
15 GPIO15 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
14 GPIO14 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
13 GPIO13 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
12 GPIO12 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
11 GPIO11 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
10 GPIO10 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
9 GPIO9 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
8 GPIO8 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
7 GPIO7 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
6 GPIO6 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
5 GPIO5 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
4 GPIO4 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
3 GPIO3 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
2 GPIO2 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
1 GPIO1 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
0 GPIO0 R/W 0h Input inversion control for this pin
Reset type: SYSRSn

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8.10.2.9 GPAODR Register (Offset = 12h) [Reset = 00000000h]

GPAODR is shown in Figure 8-12 and described in Table 8-22.
Return to the Summary Table.
GPIO A Open Drain Output Register (GPIO0 to GPIO31)
Selects between normal and open-drain output for the GPIO pin.
0: Normal Output
1: Open Drain Output
Reading the register returns the current value of the register setting.
Note:
[1] In the Open Drain output mode, if the buffer is configured for output mode, a 0 value to be driven out comes
out on the on the PAD while a 1 value to be driven out tri-states the buffer.
Figure 8-12. GPAODR Register
31 30 29 28 27 26 25 24
GPIO31 GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-22. GPAODR Register Field Descriptions

Bit Field Type Reset Description
31 GPIO31 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
30 GPIO30 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
29 GPIO29 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
28 GPIO28 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
27 GPIO27 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
26 GPIO26 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
25 GPIO25 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
24 GPIO24 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
23 GPIO23 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
22 GPIO22 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn

1026 TMS320F2837xD Dual-Core Real-Time Microcontrollers SPRUHM8K – DECEMBER 2013 – REVISED MAY 2024
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Table 8-22. GPAODR Register Field Descriptions (continued)

Bit Field Type Reset Description
21 GPIO21 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
20 GPIO20 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
19 GPIO19 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
18 GPIO18 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
17 GPIO17 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
16 GPIO16 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
15 GPIO15 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
14 GPIO14 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
13 GPIO13 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
12 GPIO12 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
11 GPIO11 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
10 GPIO10 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
9 GPIO9 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
8 GPIO8 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
7 GPIO7 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
6 GPIO6 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
5 GPIO5 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
4 GPIO4 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
3 GPIO3 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
2 GPIO2 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
1 GPIO1 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
0 GPIO0 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn

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8.10.2.10 GPAGMUX1 Register (Offset = 20h) [Reset = 00000000h]

GPAGMUX1 is shown in Figure 8-13 and described in Table 8-23.
Return to the Summary Table.
GPIO A Peripheral Group Mux (GPIO0 to 15)
Defines pin-muxing selection for GPIO.
Note: For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.
Figure 8-13. GPAGMUX1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-23. GPAGMUX1 Register Field Descriptions

Bit Field Type Reset Description
31-30 GPIO15 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
29-28 GPIO14 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
27-26 GPIO13 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
25-24 GPIO12 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
23-22 GPIO11 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
21-20 GPIO10 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
19-18 GPIO9 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
17-16 GPIO8 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
15-14 GPIO7 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
13-12 GPIO6 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
11-10 GPIO5 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
9-8 GPIO4 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
7-6 GPIO3 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
5-4 GPIO2 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
3-2 GPIO1 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
1-0 GPIO0 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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8.10.2.11 GPAGMUX2 Register (Offset = 22h) [Reset = 00000000h]

GPAGMUX2 is shown in Figure 8-14 and described in Table 8-24.
Return to the Summary Table.
GPIO A Peripheral Group Mux (GPIO16 to 31)
Defines pin-muxing selection for GPIO.
Note: For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.
Figure 8-14. GPAGMUX2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO31 GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-24. GPAGMUX2 Register Field Descriptions

Bit Field Type Reset Description
31-30 GPIO31 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
29-28 GPIO30 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
27-26 GPIO29 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
25-24 GPIO28 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
23-22 GPIO27 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
21-20 GPIO26 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
19-18 GPIO25 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
17-16 GPIO24 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
15-14 GPIO23 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
13-12 GPIO22 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
11-10 GPIO21 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
9-8 GPIO20 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
7-6 GPIO19 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
5-4 GPIO18 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
3-2 GPIO17 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
1-0 GPIO16 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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8.10.2.12 GPACSEL1 Register (Offset = 28h) [Reset = 00000000h]

GPACSEL1 is shown in Figure 8-15 and described in Table 8-25.
Return to the Summary Table.
GPIO A Core Select Register (GPIO0 to 7)
Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
xx00: CPU1 selected
xx01: CPU1.CLA1 selected
xx10: CPU2 selected
xx11: CPU2.CLA1 selected
Figure 8-15. GPACSEL1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO7 GPIO6 GPIO5 GPIO4
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO3 GPIO2 GPIO1 GPIO0
R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-25. GPACSEL1 Register Field Descriptions

Bit Field Type Reset Description
31-28 GPIO7 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
27-24 GPIO6 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
23-20 GPIO5 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
19-16 GPIO4 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
15-12 GPIO3 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
11-8 GPIO2 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
7-4 GPIO1 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
3-0 GPIO0 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

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8.10.2.13 GPACSEL2 Register (Offset = 2Ah) [Reset = 00000000h]

GPACSEL2 is shown in Figure 8-16 and described in Table 8-26.
Return to the Summary Table.
GPIO A Core Select Register (GPIO8 to 15)
Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
xx00: CPU1 selected
xx01: CPU1.CLA1 selected
xx10: CPU2 selected
xx11: CPU2.CLA1 selected
Figure 8-16. GPACSEL2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO15 GPIO14 GPIO13 GPIO12
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO11 GPIO10 GPIO9 GPIO8
R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-26. GPACSEL2 Register Field Descriptions

Bit Field Type Reset Description
31-28 GPIO15 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
27-24 GPIO14 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
23-20 GPIO13 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
19-16 GPIO12 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
15-12 GPIO11 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
11-8 GPIO10 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
7-4 GPIO9 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
3-0 GPIO8 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

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8.10.2.14 GPACSEL3 Register (Offset = 2Ch) [Reset = 00000000h]

GPACSEL3 is shown in Figure 8-17 and described in Table 8-27.
Return to the Summary Table.
GPIO A Core Select Register (GPIO16 to 23)
Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
xx00: CPU1 selected
xx01: CPU1.CLA1 selected
xx10: CPU2 selected
xx11: CPU2.CLA1 selected
Figure 8-17. GPACSEL3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO23 GPIO22 GPIO21 GPIO20
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO19 GPIO18 GPIO17 GPIO16
R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-27. GPACSEL3 Register Field Descriptions

Bit Field Type Reset Description
31-28 GPIO23 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
27-24 GPIO22 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
23-20 GPIO21 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
19-16 GPIO20 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
15-12 GPIO19 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
11-8 GPIO18 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
7-4 GPIO17 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
3-0 GPIO16 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

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8.10.2.15 GPACSEL4 Register (Offset = 2Eh) [Reset = 00000000h]

GPACSEL4 is shown in Figure 8-18 and described in Table 8-28.
Return to the Summary Table.
GPIO A Core Select Register (GPIO24 to 31)
Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
xx00: CPU1 selected
xx01: CPU1.CLA1 selected
xx10: CPU2 selected
xx11: CPU2.CLA1 selected
Figure 8-18. GPACSEL4 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO31 GPIO30 GPIO29 GPIO28
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO27 GPIO26 GPIO25 GPIO24
R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-28. GPACSEL4 Register Field Descriptions

Bit Field Type Reset Description
31-28 GPIO31 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
27-24 GPIO30 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
23-20 GPIO29 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
19-16 GPIO28 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
15-12 GPIO27 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
11-8 GPIO26 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
7-4 GPIO25 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
3-0 GPIO24 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

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8.10.2.16 GPALOCK Register (Offset = 3Ch) [Reset = 00000000h]

GPALOCK is shown in Figure 8-19 and described in Table 8-29.
Return to the Summary Table.
GPIO A Lock Configuration Register (GPIO0 to 31)
GPIO Configuration Lock for GPIO.
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx register which control the same pin can be changed
1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1,
GPyGMUX2 and GPyCSELx registers which control the same pin
Figure 8-19. GPALOCK Register
31 30 29 28 27 26 25 24
GPIO31 GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-29. GPALOCK Register Field Descriptions

Bit Field Type Reset Description
31 GPIO31 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
30 GPIO30 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
29 GPIO29 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
28 GPIO28 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
27 GPIO27 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
26 GPIO26 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
25 GPIO25 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
24 GPIO24 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
23 GPIO23 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
22 GPIO22 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
21 GPIO21 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn

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Table 8-29. GPALOCK Register Field Descriptions (continued)

Bit Field Type Reset Description
20 GPIO20 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
19 GPIO19 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
18 GPIO18 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
17 GPIO17 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
16 GPIO16 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
15 GPIO15 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
14 GPIO14 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
13 GPIO13 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
12 GPIO12 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
11 GPIO11 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
10 GPIO10 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
9 GPIO9 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
8 GPIO8 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
7 GPIO7 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
6 GPIO6 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
5 GPIO5 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
4 GPIO4 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
3 GPIO3 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
2 GPIO2 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
1 GPIO1 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
0 GPIO0 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn

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8.10.2.17 GPACR Register (Offset = 3Eh) [Reset = 00000000h]

GPACR is shown in Figure 8-20 and described in Table 8-30.
Return to the Summary Table.
GPIO A Lock Commit Register (GPIO0 to 31)
GPIO Configuration Lock Commit for GPIO:
1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed
Figure 8-20. GPACR Register
31 30 29 28 27 26 25 24
GPIO31 GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24
R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h

23 22 21 20 19 18 17 16
GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16
R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h

15 14 13 12 11 10 9 8
GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8
R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h

7 6 5 4 3 2 1 0
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h

Table 8-30. GPACR Register Field Descriptions

Bit Field Type Reset Description
31 GPIO31 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
30 GPIO30 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
29 GPIO29 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
28 GPIO28 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
27 GPIO27 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
26 GPIO26 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
25 GPIO25 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
24 GPIO24 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
23 GPIO23 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
22 GPIO22 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
21 GPIO21 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
20 GPIO20 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn

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Table 8-30. GPACR Register Field Descriptions (continued)

Bit Field Type Reset Description
19 GPIO19 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
18 GPIO18 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
17 GPIO17 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
16 GPIO16 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
15 GPIO15 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
14 GPIO14 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
13 GPIO13 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
12 GPIO12 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
11 GPIO11 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
10 GPIO10 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
9 GPIO9 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
8 GPIO8 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
7 GPIO7 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
6 GPIO6 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
5 GPIO5 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
4 GPIO4 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
3 GPIO3 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
2 GPIO2 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
1 GPIO1 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
0 GPIO0 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn

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8.10.2.18 GPBCTRL Register (Offset = 40h) [Reset = 00000000h]

GPBCTRL is shown in Figure 8-21 and described in Table 8-31.
Return to the Summary Table.
GPIO B Qualification Sampling Period Control (GPIO32 to 63)
Figure 8-21. GPBCTRL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
QUALPRD3 QUALPRD2 QUALPRD1 QUALPRD0
R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-31. GPBCTRL Register Field Descriptions

Bit Field Type Reset Description
31-24 QUALPRD3 R/W 0h Qualification sampling period for GPIO56 to GPIO63:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn
23-16 QUALPRD2 R/W 0h Qualification sampling period for GPIO48 to GPIO55:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn
15-8 QUALPRD1 R/W 0h Qualification sampling period for GPIO40 to GPIO47:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn
7-0 QUALPRD0 R/W 0h Qualification sampling period for GPIO32 to GPIO39:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn

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8.10.2.19 GPBQSEL1 Register (Offset = 42h) [Reset = 00000000h]

GPBQSEL1 is shown in Figure 8-22 and described in Table 8-32.
Return to the Summary Table.
GPIO B Qualifier Select 1 Register (GPIO32 to 47)
Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)
Figure 8-22. GPBQSEL1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO47 GPIO46 GPIO45 GPIO44 GPIO43 GPIO42 GPIO41 GPIO40
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO39 GPIO38 GPIO37 GPIO36 GPIO35 GPIO34 GPIO33 GPIO32
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-32. GPBQSEL1 Register Field Descriptions

Bit Field Type Reset Description
31-30 GPIO47 R/W 0h Input qualification type
Reset type: SYSRSn
29-28 GPIO46 R/W 0h Input qualification type
Reset type: SYSRSn
27-26 GPIO45 R/W 0h Input qualification type
Reset type: SYSRSn
25-24 GPIO44 R/W 0h Input qualification type
Reset type: SYSRSn
23-22 GPIO43 R/W 0h Input qualification type
Reset type: SYSRSn
21-20 GPIO42 R/W 0h Input qualification type
Reset type: SYSRSn
19-18 GPIO41 R/W 0h Input qualification type
Reset type: SYSRSn
17-16 GPIO40 R/W 0h Input qualification type
Reset type: SYSRSn
15-14 GPIO39 R/W 0h Input qualification type
Reset type: SYSRSn
13-12 GPIO38 R/W 0h Input qualification type
Reset type: SYSRSn
11-10 GPIO37 R/W 0h Input qualification type
Reset type: SYSRSn
9-8 GPIO36 R/W 0h Input qualification type
Reset type: SYSRSn
7-6 GPIO35 R/W 0h Input qualification type
Reset type: SYSRSn
5-4 GPIO34 R/W 0h Input qualification type
Reset type: SYSRSn
3-2 GPIO33 R/W 0h Input qualification type
Reset type: SYSRSn

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Table 8-32. GPBQSEL1 Register Field Descriptions (continued)

Bit Field Type Reset Description
1-0 GPIO32 R/W 0h Input qualification type
Reset type: SYSRSn

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8.10.2.20 GPBQSEL2 Register (Offset = 44h) [Reset = 00000000h]

GPBQSEL2 is shown in Figure 8-23 and described in Table 8-33.
Return to the Summary Table.
GPIO B Qualifier Select 2 Register (GPIO48 to 63)
Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)
Figure 8-23. GPBQSEL2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO63 GPIO62 GPIO61 GPIO60 GPIO59 GPIO58 GPIO57 GPIO56
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO55 GPIO54 GPIO53 GPIO52 GPIO51 GPIO50 GPIO49 GPIO48
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-33. GPBQSEL2 Register Field Descriptions

Bit Field Type Reset Description
31-30 GPIO63 R/W 0h Input qualification type
Reset type: SYSRSn
29-28 GPIO62 R/W 0h Input qualification type
Reset type: SYSRSn
27-26 GPIO61 R/W 0h Input qualification type
Reset type: SYSRSn
25-24 GPIO60 R/W 0h Input qualification type
Reset type: SYSRSn
23-22 GPIO59 R/W 0h Input qualification type
Reset type: SYSRSn
21-20 GPIO58 R/W 0h Input qualification type
Reset type: SYSRSn
19-18 GPIO57 R/W 0h Input qualification type
Reset type: SYSRSn
17-16 GPIO56 R/W 0h Input qualification type
Reset type: SYSRSn
15-14 GPIO55 R/W 0h Input qualification type
Reset type: SYSRSn
13-12 GPIO54 R/W 0h Input qualification type
Reset type: SYSRSn
11-10 GPIO53 R/W 0h Input qualification type
Reset type: SYSRSn
9-8 GPIO52 R/W 0h Input qualification type
Reset type: SYSRSn
7-6 GPIO51 R/W 0h Input qualification type
Reset type: SYSRSn
5-4 GPIO50 R/W 0h Input qualification type
Reset type: SYSRSn
3-2 GPIO49 R/W 0h Input qualification type
Reset type: SYSRSn

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Table 8-33. GPBQSEL2 Register Field Descriptions (continued)

Bit Field Type Reset Description
1-0 GPIO48 R/W 0h Input qualification type
Reset type: SYSRSn

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8.10.2.21 GPBMUX1 Register (Offset = 46h) [Reset = 00000000h]

GPBMUX1 is shown in Figure 8-24 and described in Table 8-34.
Return to the Summary Table.
GPIO B Mux 1 Register (GPIO32 to 47)
Defines pin-muxing selection for GPIO.
Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate peripheral
selects being mapped to the GPIO.
Figure 8-24. GPBMUX1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO47 GPIO46 GPIO45 GPIO44 GPIO43 GPIO42 GPIO41 GPIO40
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO39 GPIO38 GPIO37 GPIO36 GPIO35 GPIO34 GPIO33 GPIO32
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-34. GPBMUX1 Register Field Descriptions

Bit Field Type Reset Description
31-30 GPIO47 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
29-28 GPIO46 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
27-26 GPIO45 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
25-24 GPIO44 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
23-22 GPIO43 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
21-20 GPIO42 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
19-18 GPIO41 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
17-16 GPIO40 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
15-14 GPIO39 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
13-12 GPIO38 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
11-10 GPIO37 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
9-8 GPIO36 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
7-6 GPIO35 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
5-4 GPIO34 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
3-2 GPIO33 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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Table 8-34. GPBMUX1 Register Field Descriptions (continued)

Bit Field Type Reset Description
1-0 GPIO32 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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8.10.2.22 GPBMUX2 Register (Offset = 48h) [Reset = 00000000h]

GPBMUX2 is shown in Figure 8-25 and described in Table 8-35.
Return to the Summary Table.
GPIO B Mux 2 Register (GPIO48 to 63)
Defines pin-muxing selection for GPIO.
Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate peripheral
selects being mapped to the GPIO.
Figure 8-25. GPBMUX2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO63 GPIO62 GPIO61 GPIO60 GPIO59 GPIO58 GPIO57 GPIO56
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO55 GPIO54 GPIO53 GPIO52 GPIO51 GPIO50 GPIO49 GPIO48
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-35. GPBMUX2 Register Field Descriptions

Bit Field Type Reset Description
31-30 GPIO63 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
29-28 GPIO62 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
27-26 GPIO61 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
25-24 GPIO60 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
23-22 GPIO59 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
21-20 GPIO58 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
19-18 GPIO57 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
17-16 GPIO56 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
15-14 GPIO55 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
13-12 GPIO54 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
11-10 GPIO53 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
9-8 GPIO52 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
7-6 GPIO51 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
5-4 GPIO50 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
3-2 GPIO49 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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Table 8-35. GPBMUX2 Register Field Descriptions (continued)

Bit Field Type Reset Description
1-0 GPIO48 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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8.10.2.23 GPBDIR Register (Offset = 4Ah) [Reset = 00000000h]

GPBDIR is shown in Figure 8-26 and described in Table 8-36.
Return to the Summary Table.
GPIO B Direction Register (GPIO32 to 63)
Controls direction of GPIO pins when the specified pin is configured in GPIO mode.
0: Configures pin as input.
1: Configures pin as output.
Reading the register returns the current value of the register setting.
Figure 8-26. GPBDIR Register
31 30 29 28 27 26 25 24
GPIO63 GPIO62 GPIO61 GPIO60 GPIO59 GPIO58 GPIO57 GPIO56
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO55 GPIO54 GPIO53 GPIO52 GPIO51 GPIO50 GPIO49 GPIO48
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO47 GPIO46 GPIO45 GPIO44 GPIO43 GPIO42 GPIO41 GPIO40
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO39 GPIO38 GPIO37 GPIO36 GPIO35 GPIO34 GPIO33 GPIO32
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-36. GPBDIR Register Field Descriptions

Bit Field Type Reset Description
31 GPIO63 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
30 GPIO62 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
29 GPIO61 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
28 GPIO60 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
27 GPIO59 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
26 GPIO58 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
25 GPIO57 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
24 GPIO56 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
23 GPIO55 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
22 GPIO54 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
21 GPIO53 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn

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Table 8-36. GPBDIR Register Field Descriptions (continued)

Bit Field Type Reset Description
20 GPIO52 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
19 GPIO51 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
18 GPIO50 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
17 GPIO49 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
16 GPIO48 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
15 GPIO47 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
14 GPIO46 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
13 GPIO45 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
12 GPIO44 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
11 GPIO43 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
10 GPIO42 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
9 GPIO41 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
8 GPIO40 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
7 GPIO39 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
6 GPIO38 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
5 GPIO37 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
4 GPIO36 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
3 GPIO35 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
2 GPIO34 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
1 GPIO33 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
0 GPIO32 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn

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8.10.2.24 GPBPUD Register (Offset = 4Ch) [Reset = FFFFFFFFh]

GPBPUD is shown in Figure 8-27 and described in Table 8-37.
Return to the Summary Table.
GPIO B Pull Up Disable Register (GPIO32 to 63)
Disables the Pull-Up on GPIO.
0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Figure 8-27. GPBPUD Register
31 30 29 28 27 26 25 24
GPIO63 GPIO62 GPIO61 GPIO60 GPIO59 GPIO58 GPIO57 GPIO56
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

23 22 21 20 19 18 17 16
GPIO55 GPIO54 GPIO53 GPIO52 GPIO51 GPIO50 GPIO49 GPIO48
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

15 14 13 12 11 10 9 8
GPIO47 GPIO46 GPIO45 GPIO44 GPIO43 GPIO42 GPIO41 GPIO40
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

7 6 5 4 3 2 1 0
GPIO39 GPIO38 GPIO37 GPIO36 GPIO35 GPIO34 GPIO33 GPIO32
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

Table 8-37. GPBPUD Register Field Descriptions

Bit Field Type Reset Description
31 GPIO63 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
30 GPIO62 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
29 GPIO61 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
28 GPIO60 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
27 GPIO59 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
26 GPIO58 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
25 GPIO57 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
24 GPIO56 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
23 GPIO55 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
22 GPIO54 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
21 GPIO53 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn

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Table 8-37. GPBPUD Register Field Descriptions (continued)

Bit Field Type Reset Description
20 GPIO52 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
19 GPIO51 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
18 GPIO50 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
17 GPIO49 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
16 GPIO48 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
15 GPIO47 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
14 GPIO46 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
13 GPIO45 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
12 GPIO44 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
11 GPIO43 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
10 GPIO42 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
9 GPIO41 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
8 GPIO40 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
7 GPIO39 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
6 GPIO38 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
5 GPIO37 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
4 GPIO36 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
3 GPIO35 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
2 GPIO34 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
1 GPIO33 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
0 GPIO32 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn

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8.10.2.25 GPBINV Register (Offset = 50h) [Reset = 00000000h]

GPBINV is shown in Figure 8-28 and described in Table 8-38.
Return to the Summary Table.
GPIO B Input Polarity Invert Registers (GPIO32 to 63)
Selects between non-inverted and inverted GPIO input to the device.
0: selects non-inverted GPIO input
1: selects inverted GPIO input
Reading the register returns the current value of the register setting.
Figure 8-28. GPBINV Register
31 30 29 28 27 26 25 24
GPIO63 GPIO62 GPIO61 GPIO60 GPIO59 GPIO58 GPIO57 GPIO56
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO55 GPIO54 GPIO53 GPIO52 GPIO51 GPIO50 GPIO49 GPIO48
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO47 GPIO46 GPIO45 GPIO44 GPIO43 GPIO42 GPIO41 GPIO40
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO39 GPIO38 GPIO37 GPIO36 GPIO35 GPIO34 GPIO33 GPIO32
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-38. GPBINV Register Field Descriptions

Bit Field Type Reset Description
31 GPIO63 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
30 GPIO62 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
29 GPIO61 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
28 GPIO60 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
27 GPIO59 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
26 GPIO58 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
25 GPIO57 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
24 GPIO56 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
23 GPIO55 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
22 GPIO54 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
21 GPIO53 R/W 0h Input inversion control for this pin
Reset type: SYSRSn

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Table 8-38. GPBINV Register Field Descriptions (continued)

Bit Field Type Reset Description
20 GPIO52 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
19 GPIO51 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
18 GPIO50 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
17 GPIO49 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
16 GPIO48 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
15 GPIO47 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
14 GPIO46 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
13 GPIO45 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
12 GPIO44 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
11 GPIO43 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
10 GPIO42 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
9 GPIO41 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
8 GPIO40 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
7 GPIO39 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
6 GPIO38 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
5 GPIO37 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
4 GPIO36 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
3 GPIO35 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
2 GPIO34 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
1 GPIO33 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
0 GPIO32 R/W 0h Input inversion control for this pin
Reset type: SYSRSn

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8.10.2.26 GPBODR Register (Offset = 52h) [Reset = 00000000h]

GPBODR is shown in Figure 8-29 and described in Table 8-39.
Return to the Summary Table.
GPIO B Open Drain Output Register (GPIO32 to GPIO63)
Selects between normal and open-drain output for the GPIO pin.
0: Normal Output
1: Open Drain Output
Reading the register returns the current value of the register setting.
Note:
[1] In the Open Drain output mode, if the buffer is configured for output mode, a 0 value to be driven out comes
out on the on the PAD while a 1 value to be driven out tri-states the buffer.
Figure 8-29. GPBODR Register
31 30 29 28 27 26 25 24
GPIO63 GPIO62 GPIO61 GPIO60 GPIO59 GPIO58 GPIO57 GPIO56
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO55 GPIO54 GPIO53 GPIO52 GPIO51 GPIO50 GPIO49 GPIO48
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO47 GPIO46 GPIO45 GPIO44 GPIO43 GPIO42 GPIO41 GPIO40
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO39 GPIO38 GPIO37 GPIO36 GPIO35 GPIO34 GPIO33 GPIO32
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-39. GPBODR Register Field Descriptions

Bit Field Type Reset Description
31 GPIO63 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
30 GPIO62 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
29 GPIO61 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
28 GPIO60 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
27 GPIO59 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
26 GPIO58 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
25 GPIO57 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
24 GPIO56 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
23 GPIO55 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
22 GPIO54 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn

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Table 8-39. GPBODR Register Field Descriptions (continued)

Bit Field Type Reset Description
21 GPIO53 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
20 GPIO52 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
19 GPIO51 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
18 GPIO50 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
17 GPIO49 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
16 GPIO48 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
15 GPIO47 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
14 GPIO46 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
13 GPIO45 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
12 GPIO44 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
11 GPIO43 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
10 GPIO42 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
9 GPIO41 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
8 GPIO40 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
7 GPIO39 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
6 GPIO38 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
5 GPIO37 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
4 GPIO36 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
3 GPIO35 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
2 GPIO34 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
1 GPIO33 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
0 GPIO32 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn

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8.10.2.27 GPBAMSEL Register (Offset = 54h) [Reset = 00000000h]

GPBAMSEL is shown in Figure 8-30 and described in Table 8-40.
Return to the Summary Table.
GPIO B Analog Mode Select register
Selects between digital and analog functionality for GPIO pins.
0: The pin is configured to digital functions according to the other GPIO configuration registers
1: The analog function of the pin is enabled
Figure 8-30. GPBAMSEL Register
31 30 29 28 27 26 25 24
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED GPIO43 GPIO42 RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-40. GPBAMSEL Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R/W 0h Reserved
30 RESERVED R/W 0h Reserved
29 RESERVED R/W 0h Reserved
28 RESERVED R/W 0h Reserved
27 RESERVED R/W 0h Reserved
26 RESERVED R/W 0h Reserved
25 RESERVED R/W 0h Reserved
24 RESERVED R/W 0h Reserved
23 RESERVED R/W 0h Reserved
22 RESERVED R/W 0h Reserved
21 RESERVED R/W 0h Reserved
20 RESERVED R/W 0h Reserved
19 RESERVED R/W 0h Reserved
18 RESERVED R/W 0h Reserved
17 RESERVED R/W 0h Reserved
16 RESERVED R/W 0h Reserved
15 RESERVED R/W 0h Reserved
14 RESERVED R/W 0h Reserved
13 RESERVED R/W 0h Reserved
12 RESERVED R/W 0h Reserved
11 GPIO43 R/W 0h Selects the USB0DP function
Reset type: SYSRSn

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Table 8-40. GPBAMSEL Register Field Descriptions (continued)

Bit Field Type Reset Description
10 GPIO42 R/W 0h Selects the USB0DM function
Reset type: SYSRSn
9 RESERVED R/W 0h Reserved
8 RESERVED R/W 0h Reserved
7 RESERVED R/W 0h Reserved
6 RESERVED R/W 0h Reserved
5 RESERVED R/W 0h Reserved
4 RESERVED R/W 0h Reserved
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 RESERVED R/W 0h Reserved
0 RESERVED R/W 0h Reserved

1056 TMS320F2837xD Dual-Core Real-Time Microcontrollers SPRUHM8K – DECEMBER 2013 – REVISED MAY 2024
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8.10.2.28 GPBGMUX1 Register (Offset = 60h) [Reset = 00000000h]

GPBGMUX1 is shown in Figure 8-31 and described in Table 8-41.
Return to the Summary Table.
GPIO B Peripheral Group Mux (GPIO32 to 47)
Defines pin-muxing selection for GPIO.
Note: For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.
Figure 8-31. GPBGMUX1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO47 GPIO46 GPIO45 GPIO44 GPIO43 GPIO42 GPIO41 GPIO40
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO39 GPIO38 GPIO37 GPIO36 GPIO35 GPIO34 GPIO33 GPIO32
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-41. GPBGMUX1 Register Field Descriptions

Bit Field Type Reset Description
31-30 GPIO47 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
29-28 GPIO46 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
27-26 GPIO45 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
25-24 GPIO44 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
23-22 GPIO43 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
21-20 GPIO42 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
19-18 GPIO41 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
17-16 GPIO40 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
15-14 GPIO39 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
13-12 GPIO38 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
11-10 GPIO37 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
9-8 GPIO36 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
7-6 GPIO35 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
5-4 GPIO34 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
3-2 GPIO33 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
1-0 GPIO32 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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8.10.2.29 GPBGMUX2 Register (Offset = 62h) [Reset = 00000000h]

GPBGMUX2 is shown in Figure 8-32 and described in Table 8-42.
Return to the Summary Table.
GPIO B Peripheral Group Mux (GPIO48 to 63)
Defines pin-muxing selection for GPIO.
Note: For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.
Figure 8-32. GPBGMUX2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO63 GPIO62 GPIO61 GPIO60 GPIO59 GPIO58 GPIO57 GPIO56
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO55 GPIO54 GPIO53 GPIO52 GPIO51 GPIO50 GPIO49 GPIO48
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-42. GPBGMUX2 Register Field Descriptions

Bit Field Type Reset Description
31-30 GPIO63 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
29-28 GPIO62 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
27-26 GPIO61 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
25-24 GPIO60 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
23-22 GPIO59 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
21-20 GPIO58 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
19-18 GPIO57 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
17-16 GPIO56 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
15-14 GPIO55 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
13-12 GPIO54 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
11-10 GPIO53 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
9-8 GPIO52 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
7-6 GPIO51 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
5-4 GPIO50 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
3-2 GPIO49 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
1-0 GPIO48 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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8.10.2.30 GPBCSEL1 Register (Offset = 68h) [Reset = 00000000h]

GPBCSEL1 is shown in Figure 8-33 and described in Table 8-43.
Return to the Summary Table.
GPIO B Core Select Register (GPIO32 to 39)
Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
xx00: CPU1 selected
xx01: CPU1.CLA1 selected
xx10: CPU2 selected
xx11: CPU2.CLA1 selected
Figure 8-33. GPBCSEL1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO39 GPIO38 GPIO37 GPIO36
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO35 GPIO34 GPIO33 GPIO32
R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-43. GPBCSEL1 Register Field Descriptions

Bit Field Type Reset Description
31-28 GPIO39 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
27-24 GPIO38 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
23-20 GPIO37 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
19-16 GPIO36 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
15-12 GPIO35 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
11-8 GPIO34 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
7-4 GPIO33 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
3-0 GPIO32 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

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8.10.2.31 GPBCSEL2 Register (Offset = 6Ah) [Reset = 00000000h]

GPBCSEL2 is shown in Figure 8-34 and described in Table 8-44.
Return to the Summary Table.
GPIO B Core Select Register (GPIO40 to 47)
Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
xx00: CPU1 selected
xx01: CPU1.CLA1 selected
xx10: CPU2 selected
xx11: CPU2.CLA1 selected
Figure 8-34. GPBCSEL2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO47 GPIO46 GPIO45 GPIO44
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO43 GPIO42 GPIO41 GPIO40
R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-44. GPBCSEL2 Register Field Descriptions

Bit Field Type Reset Description
31-28 GPIO47 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
27-24 GPIO46 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
23-20 GPIO45 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
19-16 GPIO44 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
15-12 GPIO43 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
11-8 GPIO42 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
7-4 GPIO41 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
3-0 GPIO40 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

1060 TMS320F2837xD Dual-Core Real-Time Microcontrollers SPRUHM8K – DECEMBER 2013 – REVISED MAY 2024
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8.10.2.32 GPBCSEL3 Register (Offset = 6Ch) [Reset = 00000000h]

GPBCSEL3 is shown in Figure 8-35 and described in Table 8-45.
Return to the Summary Table.
GPIO B Core Select Register (GPIO48 to 55)
Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
xx00: CPU1 selected
xx01: CPU1.CLA1 selected
xx10: CPU2 selected
xx11: CPU2.CLA1 selected
Figure 8-35. GPBCSEL3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO55 GPIO54 GPIO53 GPIO52
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO51 GPIO50 GPIO49 GPIO48
R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-45. GPBCSEL3 Register Field Descriptions

Bit Field Type Reset Description
31-28 GPIO55 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
27-24 GPIO54 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
23-20 GPIO53 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
19-16 GPIO52 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
15-12 GPIO51 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
11-8 GPIO50 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
7-4 GPIO49 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
3-0 GPIO48 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

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8.10.2.33 GPBCSEL4 Register (Offset = 6Eh) [Reset = 00000000h]

GPBCSEL4 is shown in Figure 8-36 and described in Table 8-46.
Return to the Summary Table.
GPIO B Core Select Register (GPIO56 to 63)
Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
xx00: CPU1 selected
xx01: CPU1.CLA1 selected
xx10: CPU2 selected
xx11: CPU2.CLA1 selected
Figure 8-36. GPBCSEL4 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO63 GPIO62 GPIO61 GPIO60
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO59 GPIO58 GPIO57 GPIO56
R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-46. GPBCSEL4 Register Field Descriptions

Bit Field Type Reset Description
31-28 GPIO63 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
27-24 GPIO62 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
23-20 GPIO61 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
19-16 GPIO60 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
15-12 GPIO59 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
11-8 GPIO58 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
7-4 GPIO57 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
3-0 GPIO56 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

1062 TMS320F2837xD Dual-Core Real-Time Microcontrollers SPRUHM8K – DECEMBER 2013 – REVISED MAY 2024
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8.10.2.34 GPBLOCK Register (Offset = 7Ch) [Reset = 00000000h]

GPBLOCK is shown in Figure 8-37 and described in Table 8-47.
Return to the Summary Table.
GPIO B Lock Configuration Register (GPIO32 to 63)
GPIO Configuration Lock for GPIO.
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx register which control the same pin can be changed
1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1,
GPyGMUX2 and GPyCSELx registers which control the same pin
Figure 8-37. GPBLOCK Register
31 30 29 28 27 26 25 24
GPIO63 GPIO62 GPIO61 GPIO60 GPIO59 GPIO58 GPIO57 GPIO56
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO55 GPIO54 GPIO53 GPIO52 GPIO51 GPIO50 GPIO49 GPIO48
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO47 GPIO46 GPIO45 GPIO44 GPIO43 GPIO42 GPIO41 GPIO40
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO39 GPIO38 GPIO37 GPIO36 GPIO35 GPIO34 GPIO33 GPIO32
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-47. GPBLOCK Register Field Descriptions

Bit Field Type Reset Description
31 GPIO63 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
30 GPIO62 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
29 GPIO61 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
28 GPIO60 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
27 GPIO59 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
26 GPIO58 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
25 GPIO57 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
24 GPIO56 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
23 GPIO55 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
22 GPIO54 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
21 GPIO53 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn

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Table 8-47. GPBLOCK Register Field Descriptions (continued)

Bit Field Type Reset Description
20 GPIO52 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
19 GPIO51 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
18 GPIO50 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
17 GPIO49 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
16 GPIO48 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
15 GPIO47 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
14 GPIO46 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
13 GPIO45 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
12 GPIO44 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
11 GPIO43 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
10 GPIO42 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
9 GPIO41 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
8 GPIO40 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
7 GPIO39 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
6 GPIO38 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
5 GPIO37 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
4 GPIO36 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
3 GPIO35 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
2 GPIO34 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
1 GPIO33 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
0 GPIO32 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn

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8.10.2.35 GPBCR Register (Offset = 7Eh) [Reset = 00000000h]

GPBCR is shown in Figure 8-38 and described in Table 8-48.
Return to the Summary Table.
GPIO B Lock Commit Register (GPIO32 to 63)
GPIO Configuration Lock Commit for GPIO:
1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed
Figure 8-38. GPBCR Register
31 30 29 28 27 26 25 24
GPIO63 GPIO62 GPIO61 GPIO60 GPIO59 GPIO58 GPIO57 GPIO56
R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h

23 22 21 20 19 18 17 16
GPIO55 GPIO54 GPIO53 GPIO52 GPIO51 GPIO50 GPIO49 GPIO48
R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h

15 14 13 12 11 10 9 8
GPIO47 GPIO46 GPIO45 GPIO44 GPIO43 GPIO42 GPIO41 GPIO40
R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h

7 6 5 4 3 2 1 0
GPIO39 GPIO38 GPIO37 GPIO36 GPIO35 GPIO34 GPIO33 GPIO32
R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h

Table 8-48. GPBCR Register Field Descriptions

Bit Field Type Reset Description
31 GPIO63 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
30 GPIO62 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
29 GPIO61 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
28 GPIO60 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
27 GPIO59 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
26 GPIO58 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
25 GPIO57 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
24 GPIO56 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
23 GPIO55 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
22 GPIO54 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
21 GPIO53 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
20 GPIO52 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn

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Table 8-48. GPBCR Register Field Descriptions (continued)

Bit Field Type Reset Description
19 GPIO51 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
18 GPIO50 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
17 GPIO49 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
16 GPIO48 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
15 GPIO47 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
14 GPIO46 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
13 GPIO45 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
12 GPIO44 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
11 GPIO43 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
10 GPIO42 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
9 GPIO41 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
8 GPIO40 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
7 GPIO39 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
6 GPIO38 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
5 GPIO37 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
4 GPIO36 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
3 GPIO35 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
2 GPIO34 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
1 GPIO33 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
0 GPIO32 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn

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8.10.2.36 GPCCTRL Register (Offset = 80h) [Reset = 00000000h]

GPCCTRL is shown in Figure 8-39 and described in Table 8-49.
Return to the Summary Table.
GPIO C Qualification Sampling Period Control (GPIO64 to 95)
Figure 8-39. GPCCTRL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
QUALPRD3 QUALPRD2 QUALPRD1 QUALPRD0
R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-49. GPCCTRL Register Field Descriptions

Bit Field Type Reset Description
31-24 QUALPRD3 R/W 0h Qualification sampling period for GPIO88 to GPIO95:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn
23-16 QUALPRD2 R/W 0h Qualification sampling period for GPIO80 to GPIO87:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn
15-8 QUALPRD1 R/W 0h Qualification sampling period for GPIO72 to GPIO79:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn
7-0 QUALPRD0 R/W 0h Qualification sampling period for GPIO64 to GPIO71:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn

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8.10.2.37 GPCQSEL1 Register (Offset = 82h) [Reset = 00000000h]

GPCQSEL1 is shown in Figure 8-40 and described in Table 8-50.
Return to the Summary Table.
GPIO C Qualifier Select 1 Register (GPIO64 to 79)
Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)
Figure 8-40. GPCQSEL1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO79 GPIO78 GPIO77 GPIO76 GPIO75 GPIO74 GPIO73 GPIO72
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO71 GPIO70 GPIO69 GPIO68 GPIO67 GPIO66 GPIO65 GPIO64
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-50. GPCQSEL1 Register Field Descriptions

Bit Field Type Reset Description
31-30 GPIO79 R/W 0h Input qualification type
Reset type: SYSRSn
29-28 GPIO78 R/W 0h Input qualification type
Reset type: SYSRSn
27-26 GPIO77 R/W 0h Input qualification type
Reset type: SYSRSn
25-24 GPIO76 R/W 0h Input qualification type
Reset type: SYSRSn
23-22 GPIO75 R/W 0h Input qualification type
Reset type: SYSRSn
21-20 GPIO74 R/W 0h Input qualification type
Reset type: SYSRSn
19-18 GPIO73 R/W 0h Input qualification type
Reset type: SYSRSn
17-16 GPIO72 R/W 0h Input qualification type
Reset type: SYSRSn
15-14 GPIO71 R/W 0h Input qualification type
Reset type: SYSRSn
13-12 GPIO70 R/W 0h Input qualification type
Reset type: SYSRSn
11-10 GPIO69 R/W 0h Input qualification type
Reset type: SYSRSn
9-8 GPIO68 R/W 0h Input qualification type
Reset type: SYSRSn
7-6 GPIO67 R/W 0h Input qualification type
Reset type: SYSRSn
5-4 GPIO66 R/W 0h Input qualification type
Reset type: SYSRSn
3-2 GPIO65 R/W 0h Input qualification type
Reset type: SYSRSn

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Table 8-50. GPCQSEL1 Register Field Descriptions (continued)

Bit Field Type Reset Description
1-0 GPIO64 R/W 0h Input qualification type
Reset type: SYSRSn

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8.10.2.38 GPCQSEL2 Register (Offset = 84h) [Reset = 00000000h]

GPCQSEL2 is shown in Figure 8-41 and described in Table 8-51.
Return to the Summary Table.
GPIO C Qualifier Select 2 Register (GPIO80 to 95)
Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)
Figure 8-41. GPCQSEL2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO95 GPIO94 GPIO93 GPIO92 GPIO91 GPIO90 GPIO89 GPIO88
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO87 GPIO86 GPIO85 GPIO84 GPIO83 GPIO82 GPIO81 GPIO80
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-51. GPCQSEL2 Register Field Descriptions

Bit Field Type Reset Description
31-30 GPIO95 R/W 0h Input qualification type
Reset type: SYSRSn
29-28 GPIO94 R/W 0h Input qualification type
Reset type: SYSRSn
27-26 GPIO93 R/W 0h Input qualification type
Reset type: SYSRSn
25-24 GPIO92 R/W 0h Input qualification type
Reset type: SYSRSn
23-22 GPIO91 R/W 0h Input qualification type
Reset type: SYSRSn
21-20 GPIO90 R/W 0h Input qualification type
Reset type: SYSRSn
19-18 GPIO89 R/W 0h Input qualification type
Reset type: SYSRSn
17-16 GPIO88 R/W 0h Input qualification type
Reset type: SYSRSn
15-14 GPIO87 R/W 0h Input qualification type
Reset type: SYSRSn
13-12 GPIO86 R/W 0h Input qualification type
Reset type: SYSRSn
11-10 GPIO85 R/W 0h Input qualification type
Reset type: SYSRSn
9-8 GPIO84 R/W 0h Input qualification type
Reset type: SYSRSn
7-6 GPIO83 R/W 0h Input qualification type
Reset type: SYSRSn
5-4 GPIO82 R/W 0h Input qualification type
Reset type: SYSRSn
3-2 GPIO81 R/W 0h Input qualification type
Reset type: SYSRSn

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Table 8-51. GPCQSEL2 Register Field Descriptions (continued)

Bit Field Type Reset Description
1-0 GPIO80 R/W 0h Input qualification type
Reset type: SYSRSn

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8.10.2.39 GPCMUX1 Register (Offset = 86h) [Reset = 00000000h]

GPCMUX1 is shown in Figure 8-42 and described in Table 8-52.
Return to the Summary Table.
GPIO C Mux 1 Register (GPIO64 to 79)
Defines pin-muxing selection for GPIO.
Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate peripheral
selects being mapped to the GPIO.
Figure 8-42. GPCMUX1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO79 GPIO78 GPIO77 GPIO76 GPIO75 GPIO74 GPIO73 GPIO72
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO71 GPIO70 GPIO69 GPIO68 GPIO67 GPIO66 GPIO65 GPIO64
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-52. GPCMUX1 Register Field Descriptions

Bit Field Type Reset Description
31-30 GPIO79 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
29-28 GPIO78 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
27-26 GPIO77 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
25-24 GPIO76 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
23-22 GPIO75 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
21-20 GPIO74 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
19-18 GPIO73 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
17-16 GPIO72 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
15-14 GPIO71 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
13-12 GPIO70 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
11-10 GPIO69 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
9-8 GPIO68 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
7-6 GPIO67 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
5-4 GPIO66 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
3-2 GPIO65 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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Table 8-52. GPCMUX1 Register Field Descriptions (continued)

Bit Field Type Reset Description
1-0 GPIO64 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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8.10.2.40 GPCMUX2 Register (Offset = 88h) [Reset = 00000000h]

GPCMUX2 is shown in Figure 8-43 and described in Table 8-53.
Return to the Summary Table.
GPIO C Mux 2 Register (GPIO80 to 95)
Defines pin-muxing selection for GPIO.
Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate peripheral
selects being mapped to the GPIO.
Figure 8-43. GPCMUX2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO95 GPIO94 GPIO93 GPIO92 GPIO91 GPIO90 GPIO89 GPIO88
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO87 GPIO86 GPIO85 GPIO84 GPIO83 GPIO82 GPIO81 GPIO80
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-53. GPCMUX2 Register Field Descriptions

Bit Field Type Reset Description
31-30 GPIO95 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
29-28 GPIO94 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
27-26 GPIO93 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
25-24 GPIO92 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
23-22 GPIO91 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
21-20 GPIO90 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
19-18 GPIO89 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
17-16 GPIO88 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
15-14 GPIO87 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
13-12 GPIO86 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
11-10 GPIO85 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
9-8 GPIO84 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
7-6 GPIO83 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
5-4 GPIO82 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
3-2 GPIO81 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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Table 8-53. GPCMUX2 Register Field Descriptions (continued)

Bit Field Type Reset Description
1-0 GPIO80 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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8.10.2.41 GPCDIR Register (Offset = 8Ah) [Reset = 00000000h]

GPCDIR is shown in Figure 8-44 and described in Table 8-54.
Return to the Summary Table.
GPIO C Direction Register (GPIO64 to 95)
Controls direction of GPIO pins when the specified pin is configured in GPIO mode.
0: Configures pin as input.
1: Configures pin as output.
Reading the register returns the current value of the register setting.
Figure 8-44. GPCDIR Register
31 30 29 28 27 26 25 24
GPIO95 GPIO94 GPIO93 GPIO92 GPIO91 GPIO90 GPIO89 GPIO88
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO87 GPIO86 GPIO85 GPIO84 GPIO83 GPIO82 GPIO81 GPIO80
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO79 GPIO78 GPIO77 GPIO76 GPIO75 GPIO74 GPIO73 GPIO72
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO71 GPIO70 GPIO69 GPIO68 GPIO67 GPIO66 GPIO65 GPIO64
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-54. GPCDIR Register Field Descriptions

Bit Field Type Reset Description
31 GPIO95 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
30 GPIO94 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
29 GPIO93 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
28 GPIO92 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
27 GPIO91 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
26 GPIO90 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
25 GPIO89 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
24 GPIO88 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
23 GPIO87 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
22 GPIO86 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
21 GPIO85 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn

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Table 8-54. GPCDIR Register Field Descriptions (continued)

Bit Field Type Reset Description
20 GPIO84 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
19 GPIO83 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
18 GPIO82 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
17 GPIO81 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
16 GPIO80 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
15 GPIO79 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
14 GPIO78 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
13 GPIO77 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
12 GPIO76 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
11 GPIO75 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
10 GPIO74 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
9 GPIO73 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
8 GPIO72 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
7 GPIO71 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
6 GPIO70 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
5 GPIO69 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
4 GPIO68 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
3 GPIO67 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
2 GPIO66 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
1 GPIO65 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
0 GPIO64 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn

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8.10.2.42 GPCPUD Register (Offset = 8Ch) [Reset = FFFFFFFFh]

GPCPUD is shown in Figure 8-45 and described in Table 8-55.
Return to the Summary Table.
GPIO C Pull Up Disable Register (GPIO64 to 95)
Disables the Pull-Up on GPIO.
0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Figure 8-45. GPCPUD Register
31 30 29 28 27 26 25 24
GPIO95 GPIO94 GPIO93 GPIO92 GPIO91 GPIO90 GPIO89 GPIO88
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

23 22 21 20 19 18 17 16
GPIO87 GPIO86 GPIO85 GPIO84 GPIO83 GPIO82 GPIO81 GPIO80
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

15 14 13 12 11 10 9 8
GPIO79 GPIO78 GPIO77 GPIO76 GPIO75 GPIO74 GPIO73 GPIO72
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

7 6 5 4 3 2 1 0
GPIO71 GPIO70 GPIO69 GPIO68 GPIO67 GPIO66 GPIO65 GPIO64
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

Table 8-55. GPCPUD Register Field Descriptions

Bit Field Type Reset Description
31 GPIO95 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
30 GPIO94 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
29 GPIO93 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
28 GPIO92 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
27 GPIO91 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
26 GPIO90 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
25 GPIO89 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
24 GPIO88 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
23 GPIO87 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
22 GPIO86 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
21 GPIO85 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn

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Table 8-55. GPCPUD Register Field Descriptions (continued)

Bit Field Type Reset Description
20 GPIO84 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
19 GPIO83 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
18 GPIO82 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
17 GPIO81 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
16 GPIO80 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
15 GPIO79 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
14 GPIO78 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
13 GPIO77 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
12 GPIO76 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
11 GPIO75 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
10 GPIO74 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
9 GPIO73 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
8 GPIO72 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
7 GPIO71 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
6 GPIO70 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
5 GPIO69 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
4 GPIO68 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
3 GPIO67 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
2 GPIO66 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
1 GPIO65 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
0 GPIO64 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn

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8.10.2.43 GPCINV Register (Offset = 90h) [Reset = 00000000h]

GPCINV is shown in Figure 8-46 and described in Table 8-56.
Return to the Summary Table.
GPIO C Input Polarity Invert Registers (GPIO64 to 95)
Selects between non-inverted and inverted GPIO input to the device.
0: selects non-inverted GPIO input
1: selects inverted GPIO input
Reading the register returns the current value of the register setting.
Figure 8-46. GPCINV Register
31 30 29 28 27 26 25 24
GPIO95 GPIO94 GPIO93 GPIO92 GPIO91 GPIO90 GPIO89 GPIO88
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO87 GPIO86 GPIO85 GPIO84 GPIO83 GPIO82 GPIO81 GPIO80
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO79 GPIO78 GPIO77 GPIO76 GPIO75 GPIO74 GPIO73 GPIO72
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO71 GPIO70 GPIO69 GPIO68 GPIO67 GPIO66 GPIO65 GPIO64
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-56. GPCINV Register Field Descriptions

Bit Field Type Reset Description
31 GPIO95 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
30 GPIO94 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
29 GPIO93 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
28 GPIO92 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
27 GPIO91 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
26 GPIO90 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
25 GPIO89 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
24 GPIO88 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
23 GPIO87 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
22 GPIO86 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
21 GPIO85 R/W 0h Input inversion control for this pin
Reset type: SYSRSn

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Table 8-56. GPCINV Register Field Descriptions (continued)

Bit Field Type Reset Description
20 GPIO84 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
19 GPIO83 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
18 GPIO82 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
17 GPIO81 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
16 GPIO80 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
15 GPIO79 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
14 GPIO78 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
13 GPIO77 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
12 GPIO76 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
11 GPIO75 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
10 GPIO74 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
9 GPIO73 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
8 GPIO72 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
7 GPIO71 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
6 GPIO70 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
5 GPIO69 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
4 GPIO68 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
3 GPIO67 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
2 GPIO66 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
1 GPIO65 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
0 GPIO64 R/W 0h Input inversion control for this pin
Reset type: SYSRSn

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8.10.2.44 GPCODR Register (Offset = 92h) [Reset = 00000000h]

GPCODR is shown in Figure 8-47 and described in Table 8-57.
Return to the Summary Table.
GPIO C Open Drain Output Register (GPIO64 to GPIO95)
Selects between normal and open-drain output for the GPIO pin.
0: Normal Output
1: Open Drain Output
Reading the register returns the current value of the register setting.
Note:
[1] In the Open Drain output mode, if the buffer is configured for output mode, a 0 value to be driven out comes
out on the on the PAD while a 1 value to be driven out tri-states the buffer.
Figure 8-47. GPCODR Register
31 30 29 28 27 26 25 24
GPIO95 GPIO94 GPIO93 GPIO92 GPIO91 GPIO90 GPIO89 GPIO88
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO87 GPIO86 GPIO85 GPIO84 GPIO83 GPIO82 GPIO81 GPIO80
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO79 GPIO78 GPIO77 GPIO76 GPIO75 GPIO74 GPIO73 GPIO72
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO71 GPIO70 GPIO69 GPIO68 GPIO67 GPIO66 GPIO65 GPIO64
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-57. GPCODR Register Field Descriptions

Bit Field Type Reset Description
31 GPIO95 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
30 GPIO94 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
29 GPIO93 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
28 GPIO92 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
27 GPIO91 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
26 GPIO90 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
25 GPIO89 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
24 GPIO88 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
23 GPIO87 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
22 GPIO86 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn

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Table 8-57. GPCODR Register Field Descriptions (continued)

Bit Field Type Reset Description
21 GPIO85 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
20 GPIO84 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
19 GPIO83 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
18 GPIO82 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
17 GPIO81 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
16 GPIO80 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
15 GPIO79 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
14 GPIO78 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
13 GPIO77 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
12 GPIO76 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
11 GPIO75 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
10 GPIO74 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
9 GPIO73 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
8 GPIO72 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
7 GPIO71 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
6 GPIO70 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
5 GPIO69 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
4 GPIO68 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
3 GPIO67 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
2 GPIO66 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
1 GPIO65 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
0 GPIO64 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn

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8.10.2.45 GPCGMUX1 Register (Offset = A0h) [Reset = 00000000h]

GPCGMUX1 is shown in Figure 8-48 and described in Table 8-58.
Return to the Summary Table.
GPIO C Peripheral Group Mux (GPIO64 to 79)
Defines pin-muxing selection for GPIO.
Note: For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.
Figure 8-48. GPCGMUX1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO79 GPIO78 GPIO77 GPIO76 GPIO75 GPIO74 GPIO73 GPIO72
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO71 GPIO70 GPIO69 GPIO68 GPIO67 GPIO66 GPIO65 GPIO64
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-58. GPCGMUX1 Register Field Descriptions

Bit Field Type Reset Description
31-30 GPIO79 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
29-28 GPIO78 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
27-26 GPIO77 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
25-24 GPIO76 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
23-22 GPIO75 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
21-20 GPIO74 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
19-18 GPIO73 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
17-16 GPIO72 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
15-14 GPIO71 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
13-12 GPIO70 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
11-10 GPIO69 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
9-8 GPIO68 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
7-6 GPIO67 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
5-4 GPIO66 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
3-2 GPIO65 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
1-0 GPIO64 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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8.10.2.46 GPCGMUX2 Register (Offset = A2h) [Reset = 00000000h]

GPCGMUX2 is shown in Figure 8-49 and described in Table 8-59.
Return to the Summary Table.
GPIO C Peripheral Group Mux (GPIO80 to 95)
Defines pin-muxing selection for GPIO.
Note: For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.
Figure 8-49. GPCGMUX2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO95 GPIO94 GPIO93 GPIO92 GPIO91 GPIO90 GPIO89 GPIO88
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO87 GPIO86 GPIO85 GPIO84 GPIO83 GPIO82 GPIO81 GPIO80
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-59. GPCGMUX2 Register Field Descriptions

Bit Field Type Reset Description
31-30 GPIO95 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
29-28 GPIO94 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
27-26 GPIO93 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
25-24 GPIO92 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
23-22 GPIO91 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
21-20 GPIO90 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
19-18 GPIO89 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
17-16 GPIO88 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
15-14 GPIO87 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
13-12 GPIO86 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
11-10 GPIO85 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
9-8 GPIO84 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
7-6 GPIO83 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
5-4 GPIO82 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
3-2 GPIO81 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
1-0 GPIO80 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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8.10.2.47 GPCCSEL1 Register (Offset = A8h) [Reset = 00000000h]

GPCCSEL1 is shown in Figure 8-50 and described in Table 8-60.
Return to the Summary Table.
GPIO C Core Select Register (GPIO64 to 71)
Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
xx00: CPU1 selected
xx01: CPU1.CLA1 selected
xx10: CPU2 selected
xx11: CPU2.CLA1 selected
Figure 8-50. GPCCSEL1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO71 GPIO70 GPIO69 GPIO68
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO67 GPIO66 GPIO65 GPIO64
R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-60. GPCCSEL1 Register Field Descriptions

Bit Field Type Reset Description
31-28 GPIO71 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
27-24 GPIO70 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
23-20 GPIO69 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
19-16 GPIO68 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
15-12 GPIO67 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
11-8 GPIO66 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
7-4 GPIO65 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
3-0 GPIO64 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

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8.10.2.48 GPCCSEL2 Register (Offset = AAh) [Reset = 00000000h]

GPCCSEL2 is shown in Figure 8-51 and described in Table 8-61.
Return to the Summary Table.
GPIO C Core Select Register (GPIO72 to 79)
Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
xx00: CPU1 selected
xx01: CPU1.CLA1 selected
xx10: CPU2 selected
xx11: CPU2.CLA1 selected
Figure 8-51. GPCCSEL2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO79 GPIO78 GPIO77 GPIO76
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO75 GPIO74 GPIO73 GPIO72
R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-61. GPCCSEL2 Register Field Descriptions

Bit Field Type Reset Description
31-28 GPIO79 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
27-24 GPIO78 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
23-20 GPIO77 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
19-16 GPIO76 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
15-12 GPIO75 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
11-8 GPIO74 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
7-4 GPIO73 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
3-0 GPIO72 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

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8.10.2.49 GPCCSEL3 Register (Offset = ACh) [Reset = 00000000h]

GPCCSEL3 is shown in Figure 8-52 and described in Table 8-62.
Return to the Summary Table.
GPIO C Core Select Register (GPIO80 to 87)
Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
xx00: CPU1 selected
xx01: CPU1.CLA1 selected
xx10: CPU2 selected
xx11: CPU2.CLA1 selected
Figure 8-52. GPCCSEL3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO87 GPIO86 GPIO85 GPIO84
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO83 GPIO82 GPIO81 GPIO80
R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-62. GPCCSEL3 Register Field Descriptions

Bit Field Type Reset Description
31-28 GPIO87 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
27-24 GPIO86 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
23-20 GPIO85 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
19-16 GPIO84 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
15-12 GPIO83 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
11-8 GPIO82 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
7-4 GPIO81 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
3-0 GPIO80 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

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8.10.2.50 GPCCSEL4 Register (Offset = AEh) [Reset = 00000000h]

GPCCSEL4 is shown in Figure 8-53 and described in Table 8-63.
Return to the Summary Table.
GPIO C Core Select Register (GPIO88 to 95)
Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
xx00: CPU1 selected
xx01: CPU1.CLA1 selected
xx10: CPU2 selected
xx11: CPU2.CLA1 selected
Figure 8-53. GPCCSEL4 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO95 GPIO94 GPIO93 GPIO92
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO91 GPIO90 GPIO89 GPIO88
R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-63. GPCCSEL4 Register Field Descriptions

Bit Field Type Reset Description
31-28 GPIO95 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
27-24 GPIO94 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
23-20 GPIO93 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
19-16 GPIO92 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
15-12 GPIO91 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
11-8 GPIO90 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
7-4 GPIO89 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
3-0 GPIO88 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

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8.10.2.51 GPCLOCK Register (Offset = BCh) [Reset = 00000000h]

GPCLOCK is shown in Figure 8-54 and described in Table 8-64.
Return to the Summary Table.
GPIO C Lock Configuration Register (GPIO64 to 95)
GPIO Configuration Lock for GPIO.
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx register which control the same pin can be changed
1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1,
GPyGMUX2 and GPyCSELx registers which control the same pin
Figure 8-54. GPCLOCK Register
31 30 29 28 27 26 25 24
GPIO95 GPIO94 GPIO93 GPIO92 GPIO91 GPIO90 GPIO89 GPIO88
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO87 GPIO86 GPIO85 GPIO84 GPIO83 GPIO82 GPIO81 GPIO80
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO79 GPIO78 GPIO77 GPIO76 GPIO75 GPIO74 GPIO73 GPIO72
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO71 GPIO70 GPIO69 GPIO68 GPIO67 GPIO66 GPIO65 GPIO64
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-64. GPCLOCK Register Field Descriptions

Bit Field Type Reset Description
31 GPIO95 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
30 GPIO94 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
29 GPIO93 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
28 GPIO92 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
27 GPIO91 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
26 GPIO90 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
25 GPIO89 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
24 GPIO88 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
23 GPIO87 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
22 GPIO86 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
21 GPIO85 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn

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Table 8-64. GPCLOCK Register Field Descriptions (continued)

Bit Field Type Reset Description
20 GPIO84 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
19 GPIO83 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
18 GPIO82 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
17 GPIO81 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
16 GPIO80 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
15 GPIO79 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
14 GPIO78 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
13 GPIO77 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
12 GPIO76 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
11 GPIO75 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
10 GPIO74 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
9 GPIO73 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
8 GPIO72 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
7 GPIO71 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
6 GPIO70 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
5 GPIO69 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
4 GPIO68 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
3 GPIO67 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
2 GPIO66 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
1 GPIO65 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
0 GPIO64 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn

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8.10.2.52 GPCCR Register (Offset = BEh) [Reset = 00000000h]

GPCCR is shown in Figure 8-55 and described in Table 8-65.
Return to the Summary Table.
GPIO C Lock Commit Register (GPIO64 to 95)
GPIO Configuration Lock Commit for GPIO:
1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed
Figure 8-55. GPCCR Register
31 30 29 28 27 26 25 24
GPIO95 GPIO94 GPIO93 GPIO92 GPIO91 GPIO90 GPIO89 GPIO88
R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h

23 22 21 20 19 18 17 16
GPIO87 GPIO86 GPIO85 GPIO84 GPIO83 GPIO82 GPIO81 GPIO80
R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h

15 14 13 12 11 10 9 8
GPIO79 GPIO78 GPIO77 GPIO76 GPIO75 GPIO74 GPIO73 GPIO72
R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h

7 6 5 4 3 2 1 0
GPIO71 GPIO70 GPIO69 GPIO68 GPIO67 GPIO66 GPIO65 GPIO64
R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h

Table 8-65. GPCCR Register Field Descriptions

Bit Field Type Reset Description
31 GPIO95 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
30 GPIO94 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
29 GPIO93 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
28 GPIO92 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
27 GPIO91 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
26 GPIO90 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
25 GPIO89 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
24 GPIO88 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
23 GPIO87 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
22 GPIO86 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
21 GPIO85 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
20 GPIO84 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn

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Table 8-65. GPCCR Register Field Descriptions (continued)

Bit Field Type Reset Description
19 GPIO83 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
18 GPIO82 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
17 GPIO81 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
16 GPIO80 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
15 GPIO79 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
14 GPIO78 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
13 GPIO77 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
12 GPIO76 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
11 GPIO75 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
10 GPIO74 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
9 GPIO73 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
8 GPIO72 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
7 GPIO71 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
6 GPIO70 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
5 GPIO69 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
4 GPIO68 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
3 GPIO67 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
2 GPIO66 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
1 GPIO65 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
0 GPIO64 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn

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8.10.2.53 GPDCTRL Register (Offset = C0h) [Reset = 00000000h]

GPDCTRL is shown in Figure 8-56 and described in Table 8-66.
Return to the Summary Table.
GPIO D Qualification Sampling Period Control (GPIO96 to 127)
Figure 8-56. GPDCTRL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
QUALPRD3 QUALPRD2 QUALPRD1 QUALPRD0
R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-66. GPDCTRL Register Field Descriptions

Bit Field Type Reset Description
31-24 QUALPRD3 R/W 0h Qualification sampling period for GPIO120 to GPIO127:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn
23-16 QUALPRD2 R/W 0h Qualification sampling period for GPIO112 to GPIO119:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn
15-8 QUALPRD1 R/W 0h Qualification sampling period for GPIO104 to GPIO111:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn
7-0 QUALPRD0 R/W 0h Qualification sampling period for GPIO96 to GPIO103:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn

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8.10.2.54 GPDQSEL1 Register (Offset = C2h) [Reset = 00000000h]

GPDQSEL1 is shown in Figure 8-57 and described in Table 8-67.
Return to the Summary Table.
GPIO D Qualifier Select 1 Register (GPIO96 to 111)
Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)
Figure 8-57. GPDQSEL1 Register
31 30 29 28 27 26 25 24
GPIO111 GPIO110 GPIO109 GPIO108
R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO107 GPIO106 GPIO105 GPIO104
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO103 GPIO102 GPIO101 GPIO100
R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO99 GPIO98 GPIO97 GPIO96
R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-67. GPDQSEL1 Register Field Descriptions

Bit Field Type Reset Description
31-30 GPIO111 R/W 0h Input qualification type
Reset type: SYSRSn
29-28 GPIO110 R/W 0h Input qualification type
Reset type: SYSRSn
27-26 GPIO109 R/W 0h Input qualification type
Reset type: SYSRSn
25-24 GPIO108 R/W 0h Input qualification type
Reset type: SYSRSn
23-22 GPIO107 R/W 0h Input qualification type
Reset type: SYSRSn
21-20 GPIO106 R/W 0h Input qualification type
Reset type: SYSRSn
19-18 GPIO105 R/W 0h Input qualification type
Reset type: SYSRSn
17-16 GPIO104 R/W 0h Input qualification type
Reset type: SYSRSn
15-14 GPIO103 R/W 0h Input qualification type
Reset type: SYSRSn
13-12 GPIO102 R/W 0h Input qualification type
Reset type: SYSRSn
11-10 GPIO101 R/W 0h Input qualification type
Reset type: SYSRSn

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Table 8-67. GPDQSEL1 Register Field Descriptions (continued)

Bit Field Type Reset Description
9-8 GPIO100 R/W 0h Input qualification type
Reset type: SYSRSn
7-6 GPIO99 R/W 0h Input qualification type
Reset type: SYSRSn
5-4 GPIO98 R/W 0h Input qualification type
Reset type: SYSRSn
3-2 GPIO97 R/W 0h Input qualification type
Reset type: SYSRSn
1-0 GPIO96 R/W 0h Input qualification type
Reset type: SYSRSn

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8.10.2.55 GPDQSEL2 Register (Offset = C4h) [Reset = 00000000h]

GPDQSEL2 is shown in Figure 8-58 and described in Table 8-68.
Return to the Summary Table.
GPIO D Qualifier Select 2 Register (GPIO112 to 127)
Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)
Figure 8-58. GPDQSEL2 Register
31 30 29 28 27 26 25 24
GPIO127 GPIO126 GPIO125 GPIO124
R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO123 GPIO122 GPIO121 GPIO120
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO119 GPIO118 GPIO117 GPIO116
R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO115 GPIO114 GPIO113 GPIO112
R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-68. GPDQSEL2 Register Field Descriptions

Bit Field Type Reset Description
31-30 GPIO127 R/W 0h Input qualification type
Reset type: SYSRSn
29-28 GPIO126 R/W 0h Input qualification type
Reset type: SYSRSn
27-26 GPIO125 R/W 0h Input qualification type
Reset type: SYSRSn
25-24 GPIO124 R/W 0h Input qualification type
Reset type: SYSRSn
23-22 GPIO123 R/W 0h Input qualification type
Reset type: SYSRSn
21-20 GPIO122 R/W 0h Input qualification type
Reset type: SYSRSn
19-18 GPIO121 R/W 0h Input qualification type
Reset type: SYSRSn
17-16 GPIO120 R/W 0h Input qualification type
Reset type: SYSRSn
15-14 GPIO119 R/W 0h Input qualification type
Reset type: SYSRSn
13-12 GPIO118 R/W 0h Input qualification type
Reset type: SYSRSn
11-10 GPIO117 R/W 0h Input qualification type
Reset type: SYSRSn

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Table 8-68. GPDQSEL2 Register Field Descriptions (continued)

Bit Field Type Reset Description
9-8 GPIO116 R/W 0h Input qualification type
Reset type: SYSRSn
7-6 GPIO115 R/W 0h Input qualification type
Reset type: SYSRSn
5-4 GPIO114 R/W 0h Input qualification type
Reset type: SYSRSn
3-2 GPIO113 R/W 0h Input qualification type
Reset type: SYSRSn
1-0 GPIO112 R/W 0h Input qualification type
Reset type: SYSRSn

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8.10.2.56 GPDMUX1 Register (Offset = C6h) [Reset = 00000000h]

GPDMUX1 is shown in Figure 8-59 and described in Table 8-69.
Return to the Summary Table.
GPIO D Mux 1 Register (GPIO96 to 111)
Defines pin-muxing selection for GPIO.
Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate peripheral
selects being mapped to the GPIO.
Figure 8-59. GPDMUX1 Register
31 30 29 28 27 26 25 24
GPIO111 GPIO110 GPIO109 GPIO108
R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO107 GPIO106 GPIO105 GPIO104
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO103 GPIO102 GPIO101 GPIO100
R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO99 GPIO98 GPIO97 GPIO96
R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-69. GPDMUX1 Register Field Descriptions

Bit Field Type Reset Description
31-30 GPIO111 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
29-28 GPIO110 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
27-26 GPIO109 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
25-24 GPIO108 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
23-22 GPIO107 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
21-20 GPIO106 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
19-18 GPIO105 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
17-16 GPIO104 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
15-14 GPIO103 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
13-12 GPIO102 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
11-10 GPIO101 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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Table 8-69. GPDMUX1 Register Field Descriptions (continued)

Bit Field Type Reset Description
9-8 GPIO100 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
7-6 GPIO99 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
5-4 GPIO98 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
3-2 GPIO97 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
1-0 GPIO96 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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8.10.2.57 GPDMUX2 Register (Offset = C8h) [Reset = 00000000h]

GPDMUX2 is shown in Figure 8-60 and described in Table 8-70.
Return to the Summary Table.
GPIO D Mux 2 Register (GPIO112 to 127)
Defines pin-muxing selection for GPIO.
Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate peripheral
selects being mapped to the GPIO.
Figure 8-60. GPDMUX2 Register
31 30 29 28 27 26 25 24
GPIO127 GPIO126 GPIO125 GPIO124
R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO123 GPIO122 GPIO121 GPIO120
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO119 GPIO118 GPIO117 GPIO116
R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO115 GPIO114 GPIO113 GPIO112
R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-70. GPDMUX2 Register Field Descriptions

Bit Field Type Reset Description
31-30 GPIO127 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
29-28 GPIO126 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
27-26 GPIO125 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
25-24 GPIO124 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
23-22 GPIO123 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
21-20 GPIO122 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
19-18 GPIO121 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
17-16 GPIO120 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
15-14 GPIO119 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
13-12 GPIO118 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
11-10 GPIO117 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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Table 8-70. GPDMUX2 Register Field Descriptions (continued)

Bit Field Type Reset Description
9-8 GPIO116 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
7-6 GPIO115 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
5-4 GPIO114 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
3-2 GPIO113 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
1-0 GPIO112 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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8.10.2.58 GPDDIR Register (Offset = CAh) [Reset = 00000000h]

GPDDIR is shown in Figure 8-61 and described in Table 8-71.
Return to the Summary Table.
GPIO D Direction Register (GPIO96 to 127)
Controls direction of GPIO pins when the specified pin is configured in GPIO mode.
0: Configures pin as input.
1: Configures pin as output.
Reading the register returns the current value of the register setting.
Figure 8-61. GPDDIR Register
31 30 29 28 27 26 25 24
GPIO127 GPIO126 GPIO125 GPIO124 GPIO123 GPIO122 GPIO121 GPIO120
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO119 GPIO118 GPIO117 GPIO116 GPIO115 GPIO114 GPIO113 GPIO112
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO111 GPIO110 GPIO109 GPIO108 GPIO107 GPIO106 GPIO105 GPIO104
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO103 GPIO102 GPIO101 GPIO100 GPIO99 GPIO98 GPIO97 GPIO96
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-71. GPDDIR Register Field Descriptions

Bit Field Type Reset Description
31 GPIO127 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
30 GPIO126 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
29 GPIO125 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
28 GPIO124 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
27 GPIO123 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
26 GPIO122 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
25 GPIO121 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
24 GPIO120 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
23 GPIO119 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
22 GPIO118 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
21 GPIO117 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn

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Table 8-71. GPDDIR Register Field Descriptions (continued)

Bit Field Type Reset Description
20 GPIO116 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
19 GPIO115 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
18 GPIO114 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
17 GPIO113 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
16 GPIO112 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
15 GPIO111 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
14 GPIO110 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
13 GPIO109 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
12 GPIO108 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
11 GPIO107 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
10 GPIO106 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
9 GPIO105 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
8 GPIO104 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
7 GPIO103 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
6 GPIO102 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
5 GPIO101 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
4 GPIO100 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
3 GPIO99 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
2 GPIO98 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
1 GPIO97 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
0 GPIO96 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn

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8.10.2.59 GPDPUD Register (Offset = CCh) [Reset = FFFFFFFFh]

GPDPUD is shown in Figure 8-62 and described in Table 8-72.
Return to the Summary Table.
GPIO D Pull Up Disable Register (GPIO96 to 127)
Disables the Pull-Up on GPIO.
0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Figure 8-62. GPDPUD Register
31 30 29 28 27 26 25 24
GPIO127 GPIO126 GPIO125 GPIO124 GPIO123 GPIO122 GPIO121 GPIO120
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

23 22 21 20 19 18 17 16
GPIO119 GPIO118 GPIO117 GPIO116 GPIO115 GPIO114 GPIO113 GPIO112
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

15 14 13 12 11 10 9 8
GPIO111 GPIO110 GPIO109 GPIO108 GPIO107 GPIO106 GPIO105 GPIO104
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

7 6 5 4 3 2 1 0
GPIO103 GPIO102 GPIO101 GPIO100 GPIO99 GPIO98 GPIO97 GPIO96
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

Table 8-72. GPDPUD Register Field Descriptions

Bit Field Type Reset Description
31 GPIO127 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
30 GPIO126 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
29 GPIO125 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
28 GPIO124 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
27 GPIO123 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
26 GPIO122 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
25 GPIO121 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
24 GPIO120 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
23 GPIO119 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
22 GPIO118 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
21 GPIO117 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn

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Table 8-72. GPDPUD Register Field Descriptions (continued)

Bit Field Type Reset Description
20 GPIO116 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
19 GPIO115 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
18 GPIO114 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
17 GPIO113 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
16 GPIO112 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
15 GPIO111 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
14 GPIO110 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
13 GPIO109 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
12 GPIO108 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
11 GPIO107 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
10 GPIO106 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
9 GPIO105 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
8 GPIO104 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
7 GPIO103 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
6 GPIO102 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
5 GPIO101 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
4 GPIO100 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
3 GPIO99 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
2 GPIO98 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
1 GPIO97 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
0 GPIO96 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn

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8.10.2.60 GPDINV Register (Offset = D0h) [Reset = 00000000h]

GPDINV is shown in Figure 8-63 and described in Table 8-73.
Return to the Summary Table.
GPIO D Input Polarity Invert Registers (GPIO96 to 127)
Selects between non-inverted and inverted GPIO input to the device.
0: selects non-inverted GPIO input
1: selects inverted GPIO input
Reading the register returns the current value of the register setting.
Figure 8-63. GPDINV Register
31 30 29 28 27 26 25 24
GPIO127 GPIO126 GPIO125 GPIO124 GPIO123 GPIO122 GPIO121 GPIO120
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO119 GPIO118 GPIO117 GPIO116 GPIO115 GPIO114 GPIO113 GPIO112
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO111 GPIO110 GPIO109 GPIO108 GPIO107 GPIO106 GPIO105 GPIO104
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO103 GPIO102 GPIO101 GPIO100 GPIO99 GPIO98 GPIO97 GPIO96
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-73. GPDINV Register Field Descriptions

Bit Field Type Reset Description
31 GPIO127 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
30 GPIO126 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
29 GPIO125 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
28 GPIO124 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
27 GPIO123 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
26 GPIO122 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
25 GPIO121 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
24 GPIO120 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
23 GPIO119 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
22 GPIO118 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
21 GPIO117 R/W 0h Input inversion control for this pin
Reset type: SYSRSn

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Table 8-73. GPDINV Register Field Descriptions (continued)

Bit Field Type Reset Description
20 GPIO116 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
19 GPIO115 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
18 GPIO114 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
17 GPIO113 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
16 GPIO112 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
15 GPIO111 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
14 GPIO110 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
13 GPIO109 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
12 GPIO108 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
11 GPIO107 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
10 GPIO106 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
9 GPIO105 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
8 GPIO104 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
7 GPIO103 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
6 GPIO102 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
5 GPIO101 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
4 GPIO100 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
3 GPIO99 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
2 GPIO98 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
1 GPIO97 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
0 GPIO96 R/W 0h Input inversion control for this pin
Reset type: SYSRSn

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8.10.2.61 GPDODR Register (Offset = D2h) [Reset = 00000000h]

GPDODR is shown in Figure 8-64 and described in Table 8-74.
Return to the Summary Table.
GPIO D Open Drain Output Register (GPIO96 to GPIO127)
Selects between normal and open-drain output for the GPIO pin.
0: Normal Output
1: Open Drain Output
Reading the register returns the current value of the register setting.
Note:
[1] In the Open Drain output mode, if the buffer is configured for output mode, a 0 value to be driven out comes
out on the on the PAD while a 1 value to be driven out tri-states the buffer.
Figure 8-64. GPDODR Register
31 30 29 28 27 26 25 24
GPIO127 GPIO126 GPIO125 GPIO124 GPIO123 GPIO122 GPIO121 GPIO120
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO119 GPIO118 GPIO117 GPIO116 GPIO115 GPIO114 GPIO113 GPIO112
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO111 GPIO110 GPIO109 GPIO108 GPIO107 GPIO106 GPIO105 GPIO104
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO103 GPIO102 GPIO101 GPIO100 GPIO99 GPIO98 GPIO97 GPIO96
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-74. GPDODR Register Field Descriptions

Bit Field Type Reset Description
31 GPIO127 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
30 GPIO126 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
29 GPIO125 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
28 GPIO124 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
27 GPIO123 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
26 GPIO122 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
25 GPIO121 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
24 GPIO120 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
23 GPIO119 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
22 GPIO118 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn

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Table 8-74. GPDODR Register Field Descriptions (continued)

Bit Field Type Reset Description
21 GPIO117 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
20 GPIO116 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
19 GPIO115 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
18 GPIO114 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
17 GPIO113 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
16 GPIO112 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
15 GPIO111 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
14 GPIO110 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
13 GPIO109 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
12 GPIO108 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
11 GPIO107 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
10 GPIO106 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
9 GPIO105 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
8 GPIO104 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
7 GPIO103 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
6 GPIO102 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
5 GPIO101 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
4 GPIO100 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
3 GPIO99 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
2 GPIO98 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
1 GPIO97 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
0 GPIO96 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn

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8.10.2.62 GPDGMUX1 Register (Offset = E0h) [Reset = 00000000h]

GPDGMUX1 is shown in Figure 8-65 and described in Table 8-75.
Return to the Summary Table.
GPIO D Peripheral Group Mux (GPIO96 to 111)
Defines pin-muxing selection for GPIO.
Note: For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.
Figure 8-65. GPDGMUX1 Register
31 30 29 28 27 26 25 24
GPIO111 GPIO110 GPIO109 GPIO108
R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO107 GPIO106 GPIO105 GPIO104
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO103 GPIO102 GPIO101 GPIO100
R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO99 GPIO98 GPIO97 GPIO96
R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-75. GPDGMUX1 Register Field Descriptions

Bit Field Type Reset Description
31-30 GPIO111 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
29-28 GPIO110 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
27-26 GPIO109 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
25-24 GPIO108 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
23-22 GPIO107 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
21-20 GPIO106 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
19-18 GPIO105 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
17-16 GPIO104 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
15-14 GPIO103 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
13-12 GPIO102 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
11-10 GPIO101 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
9-8 GPIO100 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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Table 8-75. GPDGMUX1 Register Field Descriptions (continued)

Bit Field Type Reset Description
7-6 GPIO99 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
5-4 GPIO98 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
3-2 GPIO97 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
1-0 GPIO96 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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8.10.2.63 GPDGMUX2 Register (Offset = E2h) [Reset = 00000000h]

GPDGMUX2 is shown in Figure 8-66 and described in Table 8-76.
Return to the Summary Table.
GPIO D Peripheral Group Mux (GPIO112 to 127)
Defines pin-muxing selection for GPIO.
Note: For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.
Figure 8-66. GPDGMUX2 Register
31 30 29 28 27 26 25 24
GPIO127 GPIO126 GPIO125 GPIO124
R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO123 GPIO122 GPIO121 GPIO120
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO119 GPIO118 GPIO117 GPIO116
R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO115 GPIO114 GPIO113 GPIO112
R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-76. GPDGMUX2 Register Field Descriptions

Bit Field Type Reset Description
31-30 GPIO127 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
29-28 GPIO126 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
27-26 GPIO125 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
25-24 GPIO124 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
23-22 GPIO123 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
21-20 GPIO122 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
19-18 GPIO121 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
17-16 GPIO120 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
15-14 GPIO119 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
13-12 GPIO118 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
11-10 GPIO117 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
9-8 GPIO116 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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Table 8-76. GPDGMUX2 Register Field Descriptions (continued)

Bit Field Type Reset Description
7-6 GPIO115 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
5-4 GPIO114 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
3-2 GPIO113 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
1-0 GPIO112 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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8.10.2.64 GPDCSEL1 Register (Offset = E8h) [Reset = 00000000h]

GPDCSEL1 is shown in Figure 8-67 and described in Table 8-77.
Return to the Summary Table.
GPIO D Core Select Register (GPIO96 to 103)
Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
xx00: CPU1 selected
xx01: CPU1.CLA1 selected
xx10: CPU2 selected
xx11: CPU2.CLA1 selected
Figure 8-67. GPDCSEL1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO103 GPIO102 GPIO101 GPIO100
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO99 GPIO98 GPIO97 GPIO96
R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-77. GPDCSEL1 Register Field Descriptions

Bit Field Type Reset Description
31-28 GPIO103 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
27-24 GPIO102 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
23-20 GPIO101 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
19-16 GPIO100 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
15-12 GPIO99 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
11-8 GPIO98 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
7-4 GPIO97 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
3-0 GPIO96 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

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8.10.2.65 GPDCSEL2 Register (Offset = EAh) [Reset = 00000000h]

GPDCSEL2 is shown in Figure 8-68 and described in Table 8-78.
Return to the Summary Table.
GPIO D Core Select Register (GPIO104 to 111)
Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
xx00: CPU1 selected
xx01: CPU1.CLA1 selected
xx10: CPU2 selected
xx11: CPU2.CLA1 selected
Figure 8-68. GPDCSEL2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO111 GPIO110 GPIO109 GPIO108
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO107 GPIO106 GPIO105 GPIO104
R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-78. GPDCSEL2 Register Field Descriptions

Bit Field Type Reset Description
31-28 GPIO111 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
27-24 GPIO110 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
23-20 GPIO109 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
19-16 GPIO108 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
15-12 GPIO107 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
11-8 GPIO106 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
7-4 GPIO105 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
3-0 GPIO104 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

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8.10.2.66 GPDCSEL3 Register (Offset = ECh) [Reset = 00000000h]

GPDCSEL3 is shown in Figure 8-69 and described in Table 8-79.
Return to the Summary Table.
GPIO D Core Select Register (GPIO112 to 119)
Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
xx00: CPU1 selected
xx01: CPU1.CLA1 selected
xx10: CPU2 selected
xx11: CPU2.CLA1 selected
Figure 8-69. GPDCSEL3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO119 GPIO118 GPIO117 GPIO116
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO115 GPIO114 GPIO113 GPIO112
R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-79. GPDCSEL3 Register Field Descriptions

Bit Field Type Reset Description
31-28 GPIO119 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
27-24 GPIO118 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
23-20 GPIO117 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
19-16 GPIO116 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
15-12 GPIO115 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
11-8 GPIO114 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
7-4 GPIO113 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
3-0 GPIO112 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

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8.10.2.67 GPDCSEL4 Register (Offset = EEh) [Reset = 00000000h]

GPDCSEL4 is shown in Figure 8-70 and described in Table 8-80.
Return to the Summary Table.
GPIO D Core Select Register (GPIO120 to 127)
Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
xx00: CPU1 selected
xx01: CPU1.CLA1 selected
xx10: CPU2 selected
xx11: CPU2.CLA1 selected
Figure 8-70. GPDCSEL4 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO127 GPIO126 GPIO125 GPIO124
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO123 GPIO122 GPIO121 GPIO120
R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-80. GPDCSEL4 Register Field Descriptions

Bit Field Type Reset Description
31-28 GPIO127 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
27-24 GPIO126 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
23-20 GPIO125 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
19-16 GPIO124 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
15-12 GPIO123 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
11-8 GPIO122 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
7-4 GPIO121 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
3-0 GPIO120 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

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8.10.2.68 GPDLOCK Register (Offset = FCh) [Reset = 00000000h]

GPDLOCK is shown in Figure 8-71 and described in Table 8-81.
Return to the Summary Table.
GPIO D Lock Configuration Register (GPIO96 to 127)
GPIO Configuration Lock for GPIO.
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx register which control the same pin can be changed
1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1,
GPyGMUX2 and GPyCSELx registers which control the same pin
Figure 8-71. GPDLOCK Register
31 30 29 28 27 26 25 24
GPIO127 GPIO126 GPIO125 GPIO124 GPIO123 GPIO122 GPIO121 GPIO120
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO119 GPIO118 GPIO117 GPIO116 GPIO115 GPIO114 GPIO113 GPIO112
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO111 GPIO110 GPIO109 GPIO108 GPIO107 GPIO106 GPIO105 GPIO104
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO103 GPIO102 GPIO101 GPIO100 GPIO99 GPIO98 GPIO97 GPIO96
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-81. GPDLOCK Register Field Descriptions

Bit Field Type Reset Description
31 GPIO127 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
30 GPIO126 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
29 GPIO125 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
28 GPIO124 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
27 GPIO123 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
26 GPIO122 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
25 GPIO121 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
24 GPIO120 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
23 GPIO119 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
22 GPIO118 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
21 GPIO117 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn

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Table 8-81. GPDLOCK Register Field Descriptions (continued)

Bit Field Type Reset Description
20 GPIO116 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
19 GPIO115 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
18 GPIO114 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
17 GPIO113 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
16 GPIO112 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
15 GPIO111 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
14 GPIO110 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
13 GPIO109 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
12 GPIO108 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
11 GPIO107 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
10 GPIO106 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
9 GPIO105 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
8 GPIO104 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
7 GPIO103 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
6 GPIO102 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
5 GPIO101 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
4 GPIO100 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
3 GPIO99 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
2 GPIO98 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
1 GPIO97 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
0 GPIO96 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn

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8.10.2.69 GPDCR Register (Offset = FEh) [Reset = 00000000h]

GPDCR is shown in Figure 8-72 and described in Table 8-82.
Return to the Summary Table.
GPIO D Lock Commit Register (GPIO96 to 127)
GPIO Configuration Lock Commit for GPIO:
1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed
Figure 8-72. GPDCR Register
31 30 29 28 27 26 25 24
GPIO127 GPIO126 GPIO125 GPIO124 GPIO123 GPIO122 GPIO121 GPIO120
R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h

23 22 21 20 19 18 17 16
GPIO119 GPIO118 GPIO117 GPIO116 GPIO115 GPIO114 GPIO113 GPIO112
R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h

15 14 13 12 11 10 9 8
GPIO111 GPIO110 GPIO109 GPIO108 GPIO107 GPIO106 GPIO105 GPIO104
R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h

7 6 5 4 3 2 1 0
GPIO103 GPIO102 GPIO101 GPIO100 GPIO99 GPIO98 GPIO97 GPIO96
R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h

Table 8-82. GPDCR Register Field Descriptions

Bit Field Type Reset Description
31 GPIO127 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
30 GPIO126 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
29 GPIO125 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
28 GPIO124 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
27 GPIO123 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
26 GPIO122 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
25 GPIO121 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
24 GPIO120 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
23 GPIO119 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
22 GPIO118 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
21 GPIO117 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
20 GPIO116 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn

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Table 8-82. GPDCR Register Field Descriptions (continued)

Bit Field Type Reset Description
19 GPIO115 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
18 GPIO114 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
17 GPIO113 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
16 GPIO112 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
15 GPIO111 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
14 GPIO110 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
13 GPIO109 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
12 GPIO108 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
11 GPIO107 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
10 GPIO106 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
9 GPIO105 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
8 GPIO104 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
7 GPIO103 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
6 GPIO102 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
5 GPIO101 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
4 GPIO100 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
3 GPIO99 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
2 GPIO98 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
1 GPIO97 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
0 GPIO96 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn

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8.10.2.70 GPECTRL Register (Offset = 100h) [Reset = 00000000h]

GPECTRL is shown in Figure 8-73 and described in Table 8-83.
Return to the Summary Table.
GPIO E Qualification Sampling Period Control (GPIO128 to 159)
Figure 8-73. GPECTRL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
QUALPRD3 QUALPRD2 QUALPRD1 QUALPRD0
R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-83. GPECTRL Register Field Descriptions

Bit Field Type Reset Description
31-24 QUALPRD3 R/W 0h Qualification sampling period for GPIO152 to GPIO159:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn
23-16 QUALPRD2 R/W 0h Qualification sampling period for GPIO144 to GPIO151:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn
15-8 QUALPRD1 R/W 0h Qualification sampling period for GPIO136 to GPIO143:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn
7-0 QUALPRD0 R/W 0h Qualification sampling period for GPIO128 to GPIO135:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn

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8.10.2.71 GPEQSEL1 Register (Offset = 102h) [Reset = 00000000h]

GPEQSEL1 is shown in Figure 8-74 and described in Table 8-84.
Return to the Summary Table.
GPIO E Qualifier Select 1 Register (GPIO128 to 143)
Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)
Figure 8-74. GPEQSEL1 Register
31 30 29 28 27 26 25 24
GPIO143 GPIO142 GPIO141 GPIO140
R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO139 GPIO138 GPIO137 GPIO136
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO135 GPIO134 GPIO133 GPIO132
R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO131 GPIO130 GPIO129 GPIO128
R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-84. GPEQSEL1 Register Field Descriptions

Bit Field Type Reset Description
31-30 GPIO143 R/W 0h Input qualification type
Reset type: SYSRSn
29-28 GPIO142 R/W 0h Input qualification type
Reset type: SYSRSn
27-26 GPIO141 R/W 0h Input qualification type
Reset type: SYSRSn
25-24 GPIO140 R/W 0h Input qualification type
Reset type: SYSRSn
23-22 GPIO139 R/W 0h Input qualification type
Reset type: SYSRSn
21-20 GPIO138 R/W 0h Input qualification type
Reset type: SYSRSn
19-18 GPIO137 R/W 0h Input qualification type
Reset type: SYSRSn
17-16 GPIO136 R/W 0h Input qualification type
Reset type: SYSRSn
15-14 GPIO135 R/W 0h Input qualification type
Reset type: SYSRSn
13-12 GPIO134 R/W 0h Input qualification type
Reset type: SYSRSn
11-10 GPIO133 R/W 0h Input qualification type
Reset type: SYSRSn

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Table 8-84. GPEQSEL1 Register Field Descriptions (continued)

Bit Field Type Reset Description
9-8 GPIO132 R/W 0h Input qualification type
Reset type: SYSRSn
7-6 GPIO131 R/W 0h Input qualification type
Reset type: SYSRSn
5-4 GPIO130 R/W 0h Input qualification type
Reset type: SYSRSn
3-2 GPIO129 R/W 0h Input qualification type
Reset type: SYSRSn
1-0 GPIO128 R/W 0h Input qualification type
Reset type: SYSRSn

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8.10.2.72 GPEQSEL2 Register (Offset = 104h) [Reset = 00000000h]

GPEQSEL2 is shown in Figure 8-75 and described in Table 8-85.
Return to the Summary Table.
GPIO E Qualifier Select 2 Register (GPIO144 to 159)
Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)
Figure 8-75. GPEQSEL2 Register
31 30 29 28 27 26 25 24
GPIO159 GPIO158 GPIO157 GPIO156
R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO155 GPIO154 GPIO153 GPIO152
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO151 GPIO150 GPIO149 GPIO148
R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO147 GPIO146 GPIO145 GPIO144
R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-85. GPEQSEL2 Register Field Descriptions

Bit Field Type Reset Description
31-30 GPIO159 R/W 0h Input qualification type
Reset type: SYSRSn
29-28 GPIO158 R/W 0h Input qualification type
Reset type: SYSRSn
27-26 GPIO157 R/W 0h Input qualification type
Reset type: SYSRSn
25-24 GPIO156 R/W 0h Input qualification type
Reset type: SYSRSn
23-22 GPIO155 R/W 0h Input qualification type
Reset type: SYSRSn
21-20 GPIO154 R/W 0h Input qualification type
Reset type: SYSRSn
19-18 GPIO153 R/W 0h Input qualification type
Reset type: SYSRSn
17-16 GPIO152 R/W 0h Input qualification type
Reset type: SYSRSn
15-14 GPIO151 R/W 0h Input qualification type
Reset type: SYSRSn
13-12 GPIO150 R/W 0h Input qualification type
Reset type: SYSRSn
11-10 GPIO149 R/W 0h Input qualification type
Reset type: SYSRSn

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Table 8-85. GPEQSEL2 Register Field Descriptions (continued)

Bit Field Type Reset Description
9-8 GPIO148 R/W 0h Input qualification type
Reset type: SYSRSn
7-6 GPIO147 R/W 0h Input qualification type
Reset type: SYSRSn
5-4 GPIO146 R/W 0h Input qualification type
Reset type: SYSRSn
3-2 GPIO145 R/W 0h Input qualification type
Reset type: SYSRSn
1-0 GPIO144 R/W 0h Input qualification type
Reset type: SYSRSn

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8.10.2.73 GPEMUX1 Register (Offset = 106h) [Reset = 00000000h]

GPEMUX1 is shown in Figure 8-76 and described in Table 8-86.
Return to the Summary Table.
GPIO E Mux 1 Register (GPIO128 to 143)
Defines pin-muxing selection for GPIO.
Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate peripheral
selects being mapped to the GPIO.
Figure 8-76. GPEMUX1 Register
31 30 29 28 27 26 25 24
GPIO143 GPIO142 GPIO141 GPIO140
R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO139 GPIO138 GPIO137 GPIO136
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO135 GPIO134 GPIO133 GPIO132
R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO131 GPIO130 GPIO129 GPIO128
R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-86. GPEMUX1 Register Field Descriptions

Bit Field Type Reset Description
31-30 GPIO143 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
29-28 GPIO142 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
27-26 GPIO141 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
25-24 GPIO140 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
23-22 GPIO139 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
21-20 GPIO138 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
19-18 GPIO137 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
17-16 GPIO136 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
15-14 GPIO135 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
13-12 GPIO134 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
11-10 GPIO133 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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Table 8-86. GPEMUX1 Register Field Descriptions (continued)

Bit Field Type Reset Description
9-8 GPIO132 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
7-6 GPIO131 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
5-4 GPIO130 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
3-2 GPIO129 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
1-0 GPIO128 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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8.10.2.74 GPEMUX2 Register (Offset = 108h) [Reset = 00000000h]

GPEMUX2 is shown in Figure 8-77 and described in Table 8-87.
Return to the Summary Table.
GPIO E Mux 2 Register (GPIO144 to 159)
Defines pin-muxing selection for GPIO.
Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate peripheral
selects being mapped to the GPIO.
Figure 8-77. GPEMUX2 Register
31 30 29 28 27 26 25 24
GPIO159 GPIO158 GPIO157 GPIO156
R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO155 GPIO154 GPIO153 GPIO152
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO151 GPIO150 GPIO149 GPIO148
R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO147 GPIO146 GPIO145 GPIO144
R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-87. GPEMUX2 Register Field Descriptions

Bit Field Type Reset Description
31-30 GPIO159 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
29-28 GPIO158 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
27-26 GPIO157 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
25-24 GPIO156 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
23-22 GPIO155 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
21-20 GPIO154 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
19-18 GPIO153 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
17-16 GPIO152 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
15-14 GPIO151 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
13-12 GPIO150 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
11-10 GPIO149 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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Table 8-87. GPEMUX2 Register Field Descriptions (continued)

Bit Field Type Reset Description
9-8 GPIO148 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
7-6 GPIO147 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
5-4 GPIO146 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
3-2 GPIO145 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
1-0 GPIO144 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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8.10.2.75 GPEDIR Register (Offset = 10Ah) [Reset = 00000000h]

GPEDIR is shown in Figure 8-78 and described in Table 8-88.
Return to the Summary Table.
GPIO E Direction Register (GPIO128 to 159)
Controls direction of GPIO pins when the specified pin is configured in GPIO mode.
0: Configures pin as input.
1: Configures pin as output.
Reading the register returns the current value of the register setting.
Figure 8-78. GPEDIR Register
31 30 29 28 27 26 25 24
GPIO159 GPIO158 GPIO157 GPIO156 GPIO155 GPIO154 GPIO153 GPIO152
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO151 GPIO150 GPIO149 GPIO148 GPIO147 GPIO146 GPIO145 GPIO144
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO143 GPIO142 GPIO141 GPIO140 GPIO139 GPIO138 GPIO137 GPIO136
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO135 GPIO134 GPIO133 GPIO132 GPIO131 GPIO130 GPIO129 GPIO128
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-88. GPEDIR Register Field Descriptions

Bit Field Type Reset Description
31 GPIO159 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
30 GPIO158 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
29 GPIO157 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
28 GPIO156 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
27 GPIO155 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
26 GPIO154 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
25 GPIO153 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
24 GPIO152 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
23 GPIO151 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
22 GPIO150 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
21 GPIO149 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn

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Table 8-88. GPEDIR Register Field Descriptions (continued)

Bit Field Type Reset Description
20 GPIO148 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
19 GPIO147 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
18 GPIO146 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
17 GPIO145 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
16 GPIO144 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
15 GPIO143 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
14 GPIO142 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
13 GPIO141 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
12 GPIO140 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
11 GPIO139 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
10 GPIO138 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
9 GPIO137 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
8 GPIO136 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
7 GPIO135 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
6 GPIO134 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
5 GPIO133 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
4 GPIO132 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
3 GPIO131 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
2 GPIO130 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
1 GPIO129 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
0 GPIO128 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn

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8.10.2.76 GPEPUD Register (Offset = 10Ch) [Reset = FFFFFFFFh]

GPEPUD is shown in Figure 8-79 and described in Table 8-89.
Return to the Summary Table.
GPIO E Pull Up Disable Register (GPIO128 to 159)
Disables the Pull-Up on GPIO.
0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Figure 8-79. GPEPUD Register
31 30 29 28 27 26 25 24
GPIO159 GPIO158 GPIO157 GPIO156 GPIO155 GPIO154 GPIO153 GPIO152
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

23 22 21 20 19 18 17 16
GPIO151 GPIO150 GPIO149 GPIO148 GPIO147 GPIO146 GPIO145 GPIO144
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

15 14 13 12 11 10 9 8
GPIO143 GPIO142 GPIO141 GPIO140 GPIO139 GPIO138 GPIO137 GPIO136
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

7 6 5 4 3 2 1 0
GPIO135 GPIO134 GPIO133 GPIO132 GPIO131 GPIO130 GPIO129 GPIO128
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

Table 8-89. GPEPUD Register Field Descriptions

Bit Field Type Reset Description
31 GPIO159 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
30 GPIO158 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
29 GPIO157 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
28 GPIO156 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
27 GPIO155 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
26 GPIO154 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
25 GPIO153 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
24 GPIO152 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
23 GPIO151 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
22 GPIO150 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
21 GPIO149 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn

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Table 8-89. GPEPUD Register Field Descriptions (continued)

Bit Field Type Reset Description
20 GPIO148 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
19 GPIO147 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
18 GPIO146 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
17 GPIO145 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
16 GPIO144 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
15 GPIO143 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
14 GPIO142 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
13 GPIO141 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
12 GPIO140 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
11 GPIO139 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
10 GPIO138 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
9 GPIO137 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
8 GPIO136 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
7 GPIO135 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
6 GPIO134 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
5 GPIO133 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
4 GPIO132 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
3 GPIO131 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
2 GPIO130 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
1 GPIO129 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
0 GPIO128 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn

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8.10.2.77 GPEINV Register (Offset = 110h) [Reset = 00000000h]

GPEINV is shown in Figure 8-80 and described in Table 8-90.
Return to the Summary Table.
GPIO E Input Polarity Invert Registers (GPIO128 to 159)
Selects between non-inverted and inverted GPIO input to the device.
0: selects non-inverted GPIO input
1: selects inverted GPIO input
Reading the register returns the current value of the register setting.
Figure 8-80. GPEINV Register
31 30 29 28 27 26 25 24
GPIO159 GPIO158 GPIO157 GPIO156 GPIO155 GPIO154 GPIO153 GPIO152
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO151 GPIO150 GPIO149 GPIO148 GPIO147 GPIO146 GPIO145 GPIO144
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO143 GPIO142 GPIO141 GPIO140 GPIO139 GPIO138 GPIO137 GPIO136
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO135 GPIO134 GPIO133 GPIO132 GPIO131 GPIO130 GPIO129 GPIO128
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-90. GPEINV Register Field Descriptions

Bit Field Type Reset Description
31 GPIO159 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
30 GPIO158 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
29 GPIO157 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
28 GPIO156 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
27 GPIO155 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
26 GPIO154 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
25 GPIO153 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
24 GPIO152 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
23 GPIO151 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
22 GPIO150 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
21 GPIO149 R/W 0h Input inversion control for this pin
Reset type: SYSRSn

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Table 8-90. GPEINV Register Field Descriptions (continued)

Bit Field Type Reset Description
20 GPIO148 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
19 GPIO147 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
18 GPIO146 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
17 GPIO145 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
16 GPIO144 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
15 GPIO143 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
14 GPIO142 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
13 GPIO141 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
12 GPIO140 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
11 GPIO139 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
10 GPIO138 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
9 GPIO137 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
8 GPIO136 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
7 GPIO135 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
6 GPIO134 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
5 GPIO133 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
4 GPIO132 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
3 GPIO131 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
2 GPIO130 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
1 GPIO129 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
0 GPIO128 R/W 0h Input inversion control for this pin
Reset type: SYSRSn

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8.10.2.78 GPEODR Register (Offset = 112h) [Reset = 00000000h]

GPEODR is shown in Figure 8-81 and described in Table 8-91.
Return to the Summary Table.
GPIO E Open Drain Output Register (GPIO128 to GPIO159)
Selects between normal and open-drain output for the GPIO pin.
0: Normal Output
1: Open Drain Output
Reading the register returns the current value of the register setting.
Note:
[1] In the Open Drain output mode, if the buffer is configured for output mode, a 0 value to be driven out comes
out on the on the PAD while a 1 value to be driven out tri-states the buffer.
Figure 8-81. GPEODR Register
31 30 29 28 27 26 25 24
GPIO159 GPIO158 GPIO157 GPIO156 GPIO155 GPIO154 GPIO153 GPIO152
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO151 GPIO150 GPIO149 GPIO148 GPIO147 GPIO146 GPIO145 GPIO144
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO143 GPIO142 GPIO141 GPIO140 GPIO139 GPIO138 GPIO137 GPIO136
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO135 GPIO134 GPIO133 GPIO132 GPIO131 GPIO130 GPIO129 GPIO128
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-91. GPEODR Register Field Descriptions

Bit Field Type Reset Description
31 GPIO159 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
30 GPIO158 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
29 GPIO157 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
28 GPIO156 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
27 GPIO155 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
26 GPIO154 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
25 GPIO153 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
24 GPIO152 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
23 GPIO151 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
22 GPIO150 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn

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Table 8-91. GPEODR Register Field Descriptions (continued)

Bit Field Type Reset Description
21 GPIO149 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
20 GPIO148 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
19 GPIO147 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
18 GPIO146 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
17 GPIO145 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
16 GPIO144 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
15 GPIO143 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
14 GPIO142 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
13 GPIO141 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
12 GPIO140 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
11 GPIO139 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
10 GPIO138 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
9 GPIO137 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
8 GPIO136 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
7 GPIO135 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
6 GPIO134 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
5 GPIO133 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
4 GPIO132 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
3 GPIO131 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
2 GPIO130 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
1 GPIO129 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
0 GPIO128 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn

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8.10.2.79 GPEGMUX1 Register (Offset = 120h) [Reset = 00000000h]

GPEGMUX1 is shown in Figure 8-82 and described in Table 8-92.
Return to the Summary Table.
GPIO E Peripheral Group Mux (GPIO128 to 143)
Defines pin-muxing selection for GPIO.
Note: For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.
Figure 8-82. GPEGMUX1 Register
31 30 29 28 27 26 25 24
GPIO143 GPIO142 GPIO141 GPIO140
R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO139 GPIO138 GPIO137 GPIO136
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO135 GPIO134 GPIO133 GPIO132
R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO131 GPIO130 GPIO129 GPIO128
R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-92. GPEGMUX1 Register Field Descriptions

Bit Field Type Reset Description
31-30 GPIO143 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
29-28 GPIO142 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
27-26 GPIO141 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
25-24 GPIO140 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
23-22 GPIO139 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
21-20 GPIO138 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
19-18 GPIO137 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
17-16 GPIO136 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
15-14 GPIO135 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
13-12 GPIO134 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
11-10 GPIO133 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
9-8 GPIO132 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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Table 8-92. GPEGMUX1 Register Field Descriptions (continued)

Bit Field Type Reset Description
7-6 GPIO131 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
5-4 GPIO130 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
3-2 GPIO129 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
1-0 GPIO128 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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8.10.2.80 GPEGMUX2 Register (Offset = 122h) [Reset = 00000000h]

GPEGMUX2 is shown in Figure 8-83 and described in Table 8-93.
Return to the Summary Table.
GPIO E Peripheral Group Mux (GPIO144 to 159)
Defines pin-muxing selection for GPIO.
Note: For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.
Figure 8-83. GPEGMUX2 Register
31 30 29 28 27 26 25 24
GPIO159 GPIO158 GPIO157 GPIO156
R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO155 GPIO154 GPIO153 GPIO152
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO151 GPIO150 GPIO149 GPIO148
R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO147 GPIO146 GPIO145 GPIO144
R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-93. GPEGMUX2 Register Field Descriptions

Bit Field Type Reset Description
31-30 GPIO159 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
29-28 GPIO158 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
27-26 GPIO157 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
25-24 GPIO156 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
23-22 GPIO155 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
21-20 GPIO154 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
19-18 GPIO153 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
17-16 GPIO152 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
15-14 GPIO151 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
13-12 GPIO150 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
11-10 GPIO149 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
9-8 GPIO148 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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Table 8-93. GPEGMUX2 Register Field Descriptions (continued)

Bit Field Type Reset Description
7-6 GPIO147 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
5-4 GPIO146 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
3-2 GPIO145 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
1-0 GPIO144 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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8.10.2.81 GPECSEL1 Register (Offset = 128h) [Reset = 00000000h]

GPECSEL1 is shown in Figure 8-84 and described in Table 8-94.
Return to the Summary Table.
GPIO E Core Select Register (GPIO128 to 135)
Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
xx00: CPU1 selected
xx01: CPU1.CLA1 selected
xx10: CPU2 selected
xx11: CPU2.CLA1 selected
Figure 8-84. GPECSEL1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO135 GPIO134 GPIO133 GPIO132
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO131 GPIO130 GPIO129 GPIO128
R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-94. GPECSEL1 Register Field Descriptions

Bit Field Type Reset Description
31-28 GPIO135 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
27-24 GPIO134 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
23-20 GPIO133 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
19-16 GPIO132 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
15-12 GPIO131 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
11-8 GPIO130 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
7-4 GPIO129 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
3-0 GPIO128 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

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8.10.2.82 GPECSEL2 Register (Offset = 12Ah) [Reset = 00000000h]

GPECSEL2 is shown in Figure 8-85 and described in Table 8-95.
Return to the Summary Table.
GPIO E Core Select Register (GPIO136 to 143)
Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
xx00: CPU1 selected
xx01: CPU1.CLA1 selected
xx10: CPU2 selected
xx11: CPU2.CLA1 selected
Figure 8-85. GPECSEL2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO143 GPIO142 GPIO141 GPIO140
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO139 GPIO138 GPIO137 GPIO136
R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-95. GPECSEL2 Register Field Descriptions

Bit Field Type Reset Description
31-28 GPIO143 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
27-24 GPIO142 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
23-20 GPIO141 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
19-16 GPIO140 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
15-12 GPIO139 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
11-8 GPIO138 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
7-4 GPIO137 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
3-0 GPIO136 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

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8.10.2.83 GPECSEL3 Register (Offset = 12Ch) [Reset = 00000000h]

GPECSEL3 is shown in Figure 8-86 and described in Table 8-96.
Return to the Summary Table.
GPIO E Core Select Register (GPIO144 to 151)
Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
xx00: CPU1 selected
xx01: CPU1.CLA1 selected
xx10: CPU2 selected
xx11: CPU2.CLA1 selected
Figure 8-86. GPECSEL3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO151 GPIO150 GPIO149 GPIO148
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO147 GPIO146 GPIO145 GPIO144
R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-96. GPECSEL3 Register Field Descriptions

Bit Field Type Reset Description
31-28 GPIO151 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
27-24 GPIO150 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
23-20 GPIO149 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
19-16 GPIO148 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
15-12 GPIO147 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
11-8 GPIO146 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
7-4 GPIO145 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
3-0 GPIO144 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

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8.10.2.84 GPECSEL4 Register (Offset = 12Eh) [Reset = 00000000h]

GPECSEL4 is shown in Figure 8-87 and described in Table 8-97.
Return to the Summary Table.
GPIO E Core Select Register (GPIO152 to 159)
Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
xx00: CPU1 selected
xx01: CPU1.CLA1 selected
xx10: CPU2 selected
xx11: CPU2.CLA1 selected
Figure 8-87. GPECSEL4 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO159 GPIO158 GPIO157 GPIO156
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO155 GPIO154 GPIO153 GPIO152
R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-97. GPECSEL4 Register Field Descriptions

Bit Field Type Reset Description
31-28 GPIO159 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
27-24 GPIO158 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
23-20 GPIO157 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
19-16 GPIO156 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
15-12 GPIO155 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
11-8 GPIO154 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
7-4 GPIO153 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
3-0 GPIO152 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

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8.10.2.85 GPELOCK Register (Offset = 13Ch) [Reset = 00000000h]

GPELOCK is shown in Figure 8-88 and described in Table 8-98.
Return to the Summary Table.
GPIO E Lock Configuration Register (GPIO128 to 159)
GPIO Configuration Lock for GPIO.
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx register which control the same pin can be changed
1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1,
GPyGMUX2 and GPyCSELx registers which control the same pin
Figure 8-88. GPELOCK Register
31 30 29 28 27 26 25 24
GPIO159 GPIO158 GPIO157 GPIO156 GPIO155 GPIO154 GPIO153 GPIO152
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO151 GPIO150 GPIO149 GPIO148 GPIO147 GPIO146 GPIO145 GPIO144
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO143 GPIO142 GPIO141 GPIO140 GPIO139 GPIO138 GPIO137 GPIO136
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO135 GPIO134 GPIO133 GPIO132 GPIO131 GPIO130 GPIO129 GPIO128
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-98. GPELOCK Register Field Descriptions

Bit Field Type Reset Description
31 GPIO159 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
30 GPIO158 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
29 GPIO157 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
28 GPIO156 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
27 GPIO155 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
26 GPIO154 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
25 GPIO153 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
24 GPIO152 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
23 GPIO151 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
22 GPIO150 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
21 GPIO149 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn

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Table 8-98. GPELOCK Register Field Descriptions (continued)

Bit Field Type Reset Description
20 GPIO148 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
19 GPIO147 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
18 GPIO146 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
17 GPIO145 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
16 GPIO144 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
15 GPIO143 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
14 GPIO142 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
13 GPIO141 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
12 GPIO140 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
11 GPIO139 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
10 GPIO138 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
9 GPIO137 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
8 GPIO136 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
7 GPIO135 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
6 GPIO134 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
5 GPIO133 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
4 GPIO132 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
3 GPIO131 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
2 GPIO130 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
1 GPIO129 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
0 GPIO128 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn

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8.10.2.86 GPECR Register (Offset = 13Eh) [Reset = 00000000h]

GPECR is shown in Figure 8-89 and described in Table 8-99.
Return to the Summary Table.
GPIO E Lock Commit Register (GPIO128 to 159)
GPIO Configuration Lock Commit for GPIO:
1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed
Figure 8-89. GPECR Register
31 30 29 28 27 26 25 24
GPIO159 GPIO158 GPIO157 GPIO156 GPIO155 GPIO154 GPIO153 GPIO152
R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h

23 22 21 20 19 18 17 16
GPIO151 GPIO150 GPIO149 GPIO148 GPIO147 GPIO146 GPIO145 GPIO144
R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h

15 14 13 12 11 10 9 8
GPIO143 GPIO142 GPIO141 GPIO140 GPIO139 GPIO138 GPIO137 GPIO136
R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h

7 6 5 4 3 2 1 0
GPIO135 GPIO134 GPIO133 GPIO132 GPIO131 GPIO130 GPIO129 GPIO128
R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h

Table 8-99. GPECR Register Field Descriptions

Bit Field Type Reset Description
31 GPIO159 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
30 GPIO158 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
29 GPIO157 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
28 GPIO156 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
27 GPIO155 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
26 GPIO154 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
25 GPIO153 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
24 GPIO152 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
23 GPIO151 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
22 GPIO150 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
21 GPIO149 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
20 GPIO148 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn

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Table 8-99. GPECR Register Field Descriptions (continued)

Bit Field Type Reset Description
19 GPIO147 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
18 GPIO146 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
17 GPIO145 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
16 GPIO144 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
15 GPIO143 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
14 GPIO142 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
13 GPIO141 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
12 GPIO140 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
11 GPIO139 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
10 GPIO138 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
9 GPIO137 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
8 GPIO136 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
7 GPIO135 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
6 GPIO134 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
5 GPIO133 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
4 GPIO132 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
3 GPIO131 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
2 GPIO130 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
1 GPIO129 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
0 GPIO128 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn

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8.10.2.87 GPFCTRL Register (Offset = 140h) [Reset = 00000000h]

GPFCTRL is shown in Figure 8-90 and described in Table 8-100.
Return to the Summary Table.
GPIO F Qualification Sampling Period Control (GPIO160 to 168)
Figure 8-90. GPFCTRL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RESERVED QUALPRD1 QUALPRD0
R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-100. GPFCTRL Register Field Descriptions

Bit Field Type Reset Description
31-24 RESERVED R/W 0h Reserved
23-16 RESERVED R/W 0h Reserved
15-8 QUALPRD1 R/W 0h Qualification sampling period for GPIO168:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn
7-0 QUALPRD0 R/W 0h Qualification sampling period for GPIO160 to GPIO167:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn

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8.10.2.88 GPFQSEL1 Register (Offset = 142h) [Reset = 00000000h]

GPFQSEL1 is shown in Figure 8-91 and described in Table 8-101.
Return to the Summary Table.
GPIO F Qualifier Select 1 Register (GPIO160 to 168)
Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)
Figure 8-91. GPFQSEL1 Register
31 30 29 28 27 26 25 24
RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED GPIO168
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO167 GPIO166 GPIO165 GPIO164
R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO163 GPIO162 GPIO161 GPIO160
R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-101. GPFQSEL1 Register Field Descriptions

Bit Field Type Reset Description
31-30 RESERVED R/W 0h Reserved
29-28 RESERVED R/W 0h Reserved
27-26 RESERVED R/W 0h Reserved
25-24 RESERVED R/W 0h Reserved
23-22 RESERVED R/W 0h Reserved
21-20 RESERVED R/W 0h Reserved
19-18 RESERVED R/W 0h Reserved
17-16 GPIO168 R/W 0h Input qualification type
Reset type: SYSRSn
15-14 GPIO167 R/W 0h Input qualification type
Reset type: SYSRSn
13-12 GPIO166 R/W 0h Input qualification type
Reset type: SYSRSn
11-10 GPIO165 R/W 0h Input qualification type
Reset type: SYSRSn
9-8 GPIO164 R/W 0h Input qualification type
Reset type: SYSRSn
7-6 GPIO163 R/W 0h Input qualification type
Reset type: SYSRSn
5-4 GPIO162 R/W 0h Input qualification type
Reset type: SYSRSn

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Table 8-101. GPFQSEL1 Register Field Descriptions (continued)

Bit Field Type Reset Description
3-2 GPIO161 R/W 0h Input qualification type
Reset type: SYSRSn
1-0 GPIO160 R/W 0h Input qualification type
Reset type: SYSRSn

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8.10.2.89 GPFMUX1 Register (Offset = 146h) [Reset = 00000000h]

GPFMUX1 is shown in Figure 8-92 and described in Table 8-102.
Return to the Summary Table.
GPIO F Mux 1 Register (GPIO160 to 168)
Defines pin-muxing selection for GPIO.
Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate peripheral
selects being mapped to the GPIO.
Figure 8-92. GPFMUX1 Register
31 30 29 28 27 26 25 24
RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED GPIO168
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO167 GPIO166 GPIO165 GPIO164
R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO163 GPIO162 GPIO161 GPIO160
R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-102. GPFMUX1 Register Field Descriptions

Bit Field Type Reset Description
31-30 RESERVED R/W 0h Reserved
29-28 RESERVED R/W 0h Reserved
27-26 RESERVED R/W 0h Reserved
25-24 RESERVED R/W 0h Reserved
23-22 RESERVED R/W 0h Reserved
21-20 RESERVED R/W 0h Reserved
19-18 RESERVED R/W 0h Reserved
17-16 GPIO168 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
15-14 GPIO167 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
13-12 GPIO166 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
11-10 GPIO165 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
9-8 GPIO164 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
7-6 GPIO163 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
5-4 GPIO162 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
3-2 GPIO161 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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Table 8-102. GPFMUX1 Register Field Descriptions (continued)

Bit Field Type Reset Description
1-0 GPIO160 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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8.10.2.90 GPFDIR Register (Offset = 14Ah) [Reset = 00000000h]

GPFDIR is shown in Figure 8-93 and described in Table 8-103.
Return to the Summary Table.
GPIO F Direction Register (GPIO160 to 168)
Controls direction of GPIO pins when the specified pin is configured in GPIO mode.
0: Configures pin as input.
1: Configures pin as output.
Reading the register returns the current value of the register setting.
Figure 8-93. GPFDIR Register
31 30 29 28 27 26 25 24
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED GPIO168
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO167 GPIO166 GPIO165 GPIO164 GPIO163 GPIO162 GPIO161 GPIO160
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-103. GPFDIR Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R/W 0h Reserved
30 RESERVED R/W 0h Reserved
29 RESERVED R/W 0h Reserved
28 RESERVED R/W 0h Reserved
27 RESERVED R/W 0h Reserved
26 RESERVED R/W 0h Reserved
25 RESERVED R/W 0h Reserved
24 RESERVED R/W 0h Reserved
23 RESERVED R/W 0h Reserved
22 RESERVED R/W 0h Reserved
21 RESERVED R/W 0h Reserved
20 RESERVED R/W 0h Reserved
19 RESERVED R/W 0h Reserved
18 RESERVED R/W 0h Reserved
17 RESERVED R/W 0h Reserved
16 RESERVED R/W 0h Reserved
15 RESERVED R/W 0h Reserved
14 RESERVED R/W 0h Reserved
13 RESERVED R/W 0h Reserved
12 RESERVED R/W 0h Reserved
11 RESERVED R/W 0h Reserved
10 RESERVED R/W 0h Reserved

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Table 8-103. GPFDIR Register Field Descriptions (continued)

Bit Field Type Reset Description
9 RESERVED R/W 0h Reserved
8 GPIO168 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
7 GPIO167 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
6 GPIO166 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
5 GPIO165 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
4 GPIO164 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
3 GPIO163 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
2 GPIO162 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
1 GPIO161 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
0 GPIO160 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn

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8.10.2.91 GPFPUD Register (Offset = 14Ch) [Reset = FFFFFFFFh]

GPFPUD is shown in Figure 8-94 and described in Table 8-104.
Return to the Summary Table.
GPIO F Pull Up Disable Register (GPIO160 to 168)
Disables the Pull-Up on GPIO.
0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Figure 8-94. GPFPUD Register
31 30 29 28 27 26 25 24
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED GPIO168
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

7 6 5 4 3 2 1 0
GPIO167 GPIO166 GPIO165 GPIO164 GPIO163 GPIO162 GPIO161 GPIO160
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

Table 8-104. GPFPUD Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R/W 1h Reserved
30 RESERVED R/W 1h Reserved
29 RESERVED R/W 1h Reserved
28 RESERVED R/W 1h Reserved
27 RESERVED R/W 1h Reserved
26 RESERVED R/W 1h Reserved
25 RESERVED R/W 1h Reserved
24 RESERVED R/W 1h Reserved
23 RESERVED R/W 1h Reserved
22 RESERVED R/W 1h Reserved
21 RESERVED R/W 1h Reserved
20 RESERVED R/W 1h Reserved
19 RESERVED R/W 1h Reserved
18 RESERVED R/W 1h Reserved
17 RESERVED R/W 1h Reserved
16 RESERVED R/W 1h Reserved
15 RESERVED R/W 1h Reserved
14 RESERVED R/W 1h Reserved
13 RESERVED R/W 1h Reserved
12 RESERVED R/W 1h Reserved
11 RESERVED R/W 1h Reserved
10 RESERVED R/W 1h Reserved

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Table 8-104. GPFPUD Register Field Descriptions (continued)

Bit Field Type Reset Description
9 RESERVED R/W 1h Reserved
8 GPIO168 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
7 GPIO167 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
6 GPIO166 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
5 GPIO165 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
4 GPIO164 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
3 GPIO163 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
2 GPIO162 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
1 GPIO161 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
0 GPIO160 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn

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8.10.2.92 GPFINV Register (Offset = 150h) [Reset = 00000000h]

GPFINV is shown in Figure 8-95 and described in Table 8-105.
Return to the Summary Table.
GPIO F Input Polarity Invert Registers (GPIO160 to 168)
Selects between non-inverted and inverted GPIO input to the device.
0: selects non-inverted GPIO input
1: selects inverted GPIO input
Reading the register returns the current value of the register setting.
Figure 8-95. GPFINV Register
31 30 29 28 27 26 25 24
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED GPIO168
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO167 GPIO166 GPIO165 GPIO164 GPIO163 GPIO162 GPIO161 GPIO160
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-105. GPFINV Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R/W 0h Reserved
30 RESERVED R/W 0h Reserved
29 RESERVED R/W 0h Reserved
28 RESERVED R/W 0h Reserved
27 RESERVED R/W 0h Reserved
26 RESERVED R/W 0h Reserved
25 RESERVED R/W 0h Reserved
24 RESERVED R/W 0h Reserved
23 RESERVED R/W 0h Reserved
22 RESERVED R/W 0h Reserved
21 RESERVED R/W 0h Reserved
20 RESERVED R/W 0h Reserved
19 RESERVED R/W 0h Reserved
18 RESERVED R/W 0h Reserved
17 RESERVED R/W 0h Reserved
16 RESERVED R/W 0h Reserved
15 RESERVED R/W 0h Reserved
14 RESERVED R/W 0h Reserved
13 RESERVED R/W 0h Reserved
12 RESERVED R/W 0h Reserved
11 RESERVED R/W 0h Reserved
10 RESERVED R/W 0h Reserved

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Table 8-105. GPFINV Register Field Descriptions (continued)

Bit Field Type Reset Description
9 RESERVED R/W 0h Reserved
8 GPIO168 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
7 GPIO167 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
6 GPIO166 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
5 GPIO165 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
4 GPIO164 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
3 GPIO163 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
2 GPIO162 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
1 GPIO161 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
0 GPIO160 R/W 0h Input inversion control for this pin
Reset type: SYSRSn

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8.10.2.93 GPFODR Register (Offset = 152h) [Reset = 00000000h]

GPFODR is shown in Figure 8-96 and described in Table 8-106.
Return to the Summary Table.
GPIO F Open Drain Output Register (GPIO160 to GPIO168)
Selects between normal and open-drain output for the GPIO pin.
0: Normal Output
1: Open Drain Output
Reading the register returns the current value of the register setting.
Note:
[1] In the Open Drain output mode, if the buffer is configured for output mode, a 0 value to be driven out comes
out on the on the PAD while a 1 value to be driven out tri-states the buffer.
Figure 8-96. GPFODR Register
31 30 29 28 27 26 25 24
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED GPIO168
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO167 GPIO166 GPIO165 GPIO164 GPIO163 GPIO162 GPIO161 GPIO160
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-106. GPFODR Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R/W 0h Reserved
30 RESERVED R/W 0h Reserved
29 RESERVED R/W 0h Reserved
28 RESERVED R/W 0h Reserved
27 RESERVED R/W 0h Reserved
26 RESERVED R/W 0h Reserved
25 RESERVED R/W 0h Reserved
24 RESERVED R/W 0h Reserved
23 RESERVED R/W 0h Reserved
22 RESERVED R/W 0h Reserved
21 RESERVED R/W 0h Reserved
20 RESERVED R/W 0h Reserved
19 RESERVED R/W 0h Reserved
18 RESERVED R/W 0h Reserved
17 RESERVED R/W 0h Reserved
16 RESERVED R/W 0h Reserved
15 RESERVED R/W 0h Reserved
14 RESERVED R/W 0h Reserved
13 RESERVED R/W 0h Reserved

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Table 8-106. GPFODR Register Field Descriptions (continued)

Bit Field Type Reset Description
12 RESERVED R/W 0h Reserved
11 RESERVED R/W 0h Reserved
10 RESERVED R/W 0h Reserved
9 RESERVED R/W 0h Reserved
8 GPIO168 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
7 GPIO167 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
6 GPIO166 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
5 GPIO165 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
4 GPIO164 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
3 GPIO163 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
2 GPIO162 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
1 GPIO161 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
0 GPIO160 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn

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8.10.2.94 GPFGMUX1 Register (Offset = 160h) [Reset = 00000000h]

GPFGMUX1 is shown in Figure 8-97 and described in Table 8-107.
Return to the Summary Table.
GPIO F Peripheral Group Mux (GPIO160 to 168)
Defines pin-muxing selection for GPIO.
Note: For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.
Figure 8-97. GPFGMUX1 Register
31 30 29 28 27 26 25 24
RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED GPIO168
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO167 GPIO166 GPIO165 GPIO164
R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO163 GPIO162 GPIO161 GPIO160
R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-107. GPFGMUX1 Register Field Descriptions

Bit Field Type Reset Description
31-30 RESERVED R/W 0h Reserved
29-28 RESERVED R/W 0h Reserved
27-26 RESERVED R/W 0h Reserved
25-24 RESERVED R/W 0h Reserved
23-22 RESERVED R/W 0h Reserved
21-20 RESERVED R/W 0h Reserved
19-18 RESERVED R/W 0h Reserved
17-16 GPIO168 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
15-14 GPIO167 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
13-12 GPIO166 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
11-10 GPIO165 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
9-8 GPIO164 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
7-6 GPIO163 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
5-4 GPIO162 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
3-2 GPIO161 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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Table 8-107. GPFGMUX1 Register Field Descriptions (continued)

Bit Field Type Reset Description
1-0 GPIO160 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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8.10.2.95 GPFCSEL1 Register (Offset = 168h) [Reset = 00000000h]

GPFCSEL1 is shown in Figure 8-98 and described in Table 8-108.
Return to the Summary Table.
GPIO F Core Select Register (GPIO160 to 167)
Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
xx00: CPU1 selected
xx01: CPU1.CLA1 selected
xx10: CPU2 selected
xx11: CPU2.CLA1 selected
Figure 8-98. GPFCSEL1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO167 GPIO166 GPIO165 GPIO164
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO163 GPIO162 GPIO161 GPIO160
R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-108. GPFCSEL1 Register Field Descriptions

Bit Field Type Reset Description
31-28 GPIO167 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
27-24 GPIO166 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
23-20 GPIO165 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
19-16 GPIO164 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
15-12 GPIO163 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
11-8 GPIO162 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
7-4 GPIO161 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
3-0 GPIO160 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

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8.10.2.96 GPFCSEL2 Register (Offset = 16Ah) [Reset = 00000000h]

GPFCSEL2 is shown in Figure 8-99 and described in Table 8-109.
Return to the Summary Table.
GPIO F Core Select Register (GPIO168)
Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
xx00: CPU1 selected
xx01: CPU1.CLA1 selected
xx10: CPU2 selected
xx11: CPU2.CLA1 selected
Figure 8-99. GPFCSEL2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED GPIO168
R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-109. GPFCSEL2 Register Field Descriptions

Bit Field Type Reset Description
31-28 RESERVED R/W 0h Reserved
27-24 RESERVED R/W 0h Reserved
23-20 RESERVED R/W 0h Reserved
19-16 RESERVED R/W 0h Reserved
15-12 RESERVED R/W 0h Reserved
11-8 RESERVED R/W 0h Reserved
7-4 RESERVED R/W 0h Reserved
3-0 GPIO168 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

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8.10.2.97 GPFLOCK Register (Offset = 17Ch) [Reset = 00000000h]

GPFLOCK is shown in Figure 8-100 and described in Table 8-110.
Return to the Summary Table.
GPIO F Lock Configuration Register (GPIO160 to 168)
GPIO Configuration Lock for GPIO.
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx register which control the same pin can be changed
1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1,
GPyGMUX2 and GPyCSELx registers which control the same pin
Figure 8-100. GPFLOCK Register
31 30 29 28 27 26 25 24
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED GPIO168
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO167 GPIO166 GPIO165 GPIO164 GPIO163 GPIO162 GPIO161 GPIO160
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-110. GPFLOCK Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R/W 0h Reserved
30 RESERVED R/W 0h Reserved
29 RESERVED R/W 0h Reserved
28 RESERVED R/W 0h Reserved
27 RESERVED R/W 0h Reserved
26 RESERVED R/W 0h Reserved
25 RESERVED R/W 0h Reserved
24 RESERVED R/W 0h Reserved
23 RESERVED R/W 0h Reserved
22 RESERVED R/W 0h Reserved
21 RESERVED R/W 0h Reserved
20 RESERVED R/W 0h Reserved
19 RESERVED R/W 0h Reserved
18 RESERVED R/W 0h Reserved
17 RESERVED R/W 0h Reserved
16 RESERVED R/W 0h Reserved
15 RESERVED R/W 0h Reserved
14 RESERVED R/W 0h Reserved
13 RESERVED R/W 0h Reserved
12 RESERVED R/W 0h Reserved
11 RESERVED R/W 0h Reserved

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Table 8-110. GPFLOCK Register Field Descriptions (continued)

Bit Field Type Reset Description
10 RESERVED R/W 0h Reserved
9 RESERVED R/W 0h Reserved
8 GPIO168 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
7 GPIO167 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
6 GPIO166 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
5 GPIO165 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
4 GPIO164 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
3 GPIO163 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
2 GPIO162 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
1 GPIO161 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
0 GPIO160 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn

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8.10.2.98 GPFCR Register (Offset = 17Eh) [Reset = 00000000h]

GPFCR is shown in Figure 8-101 and described in Table 8-111.
Return to the Summary Table.
GPIO F Lock Commit Register (GPIO160 to 168)
GPIO Configuration Lock Commit for GPIO:
1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed
Figure 8-101. GPFCR Register
31 30 29 28 27 26 25 24
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED GPIO168
R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h

7 6 5 4 3 2 1 0
GPIO167 GPIO166 GPIO165 GPIO164 GPIO163 GPIO162 GPIO161 GPIO160
R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h R/WOnce-0h

Table 8-111. GPFCR Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R/WOnce 0h Reserved
30 RESERVED R/WOnce 0h Reserved
29 RESERVED R/WOnce 0h Reserved
28 RESERVED R/WOnce 0h Reserved
27 RESERVED R/WOnce 0h Reserved
26 RESERVED R/WOnce 0h Reserved
25 RESERVED R/WOnce 0h Reserved
24 RESERVED R/WOnce 0h Reserved
23 RESERVED R/WOnce 0h Reserved
22 RESERVED R/WOnce 0h Reserved
21 RESERVED R/WOnce 0h Reserved
20 RESERVED R/WOnce 0h Reserved
19 RESERVED R/WOnce 0h Reserved
18 RESERVED R/WOnce 0h Reserved
17 RESERVED R/WOnce 0h Reserved
16 RESERVED R/WOnce 0h Reserved
15 RESERVED R/WOnce 0h Reserved
14 RESERVED R/WOnce 0h Reserved
13 RESERVED R/WOnce 0h Reserved
12 RESERVED R/WOnce 0h Reserved
11 RESERVED R/WOnce 0h Reserved
10 RESERVED R/WOnce 0h Reserved
9 RESERVED R/WOnce 0h Reserved

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Table 8-111. GPFCR Register Field Descriptions (continued)

Bit Field Type Reset Description
8 GPIO168 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
7 GPIO167 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
6 GPIO166 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
5 GPIO165 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
4 GPIO164 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
3 GPIO163 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
2 GPIO162 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
1 GPIO161 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
0 GPIO160 R/WOnce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn

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8.10.3 GPIO_DATA_REGS Registers

Table 8-112 lists the memory-mapped registers for the GPIO_DATA_REGS registers. All register offset
addresses not listed in Table 8-112 should be considered as reserved locations and the register contents should
not be modified.
Table 8-112. GPIO_DATA_REGS Registers
Offset Acronym Register Name Write Protection Section
0h GPADAT GPIO A Data Register (GPIO0 to 31) Go
2h GPASET GPIO A Data Set Register (GPIO0 to 31) Go
4h GPACLEAR GPIO A Data Clear Register (GPIO0 to 31) Go
6h GPATOGGLE GPIO A Data Toggle Register (GPIO0 to 31) Go
8h GPBDAT GPIO B Data Register (GPIO32 to 63) Go
Ah GPBSET GPIO B Data Set Register (GPIO32 to 63) Go
Ch GPBCLEAR GPIO B Data Clear Register (GPIO32 to 63) Go
Eh GPBTOGGLE GPIO B Data Toggle Register (GPIO32 to 63) Go
10h GPCDAT GPIO C Data Register (GPIO64 to 95) Go
12h GPCSET GPIO C Data Set Register (GPIO64 to 95) Go
14h GPCCLEAR GPIO C Data Clear Register (GPIO64 to 95) Go
16h GPCTOGGLE GPIO C Data Toggle Register (GPIO64 to 95) Go
18h GPDDAT GPIO D Data Register (GPIO96 to 127) Go
1Ah GPDSET GPIO D Data Set Register (GPIO96 to 127) Go
1Ch GPDCLEAR GPIO D Data Clear Register (GPIO96 to 127) Go
1Eh GPDTOGGLE GPIO D Data Toggle Register (GPIO96 to 127) Go
20h GPEDAT GPIO E Data Register (GPIO128 to 159) Go
22h GPESET GPIO E Data Set Register (GPIO128 to 159) Go
24h GPECLEAR GPIO E Data Clear Register (GPIO128 to 159) Go
26h GPETOGGLE GPIO E Data Toggle Register (GPIO128 to 159) Go
28h GPFDAT GPIO F Data Register (GPIO160 to 168) Go
2Ah GPFSET GPIO F Data Set Register (GPIO160 to 168) Go
2Ch GPFCLEAR GPIO F Data Clear Register (GPIO160 to 168) Go
2Eh GPFTOGGLE GPIO F Data Toggle Register (GPIO160 to 168) Go

Complex bit access types are encoded to fit into small table cells. Table 8-113 shows the codes that are used for
access types in this section.
Table 8-113. GPIO_DATA_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default value
Register Array Variables
i,j,k,l,m,n When these variables are used in a register name,
an offset, or an address, they refer to the value of a
register array where the register is part of a group
of repeating registers. The register groups form a
hierarchical structure and the array is represented
with a formula.

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Table 8-113. GPIO_DATA_REGS Access Type Codes (continued)

Access Type Code Description
y When this variable is used in a register name, an
offset, or an address it refers to the value of a
register array.

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8.10.3.1 GPADAT Register (Offset = 0h) [Reset = 00000000h]

GPADAT is shown in Figure 8-102 and described in Table 8-114.
Return to the Summary Table.
GPIO A Data Register (GPIO0 to 31)
Reading this register reflects the current state of the GPIO pin regardless of which mode the GPIO is in.
Writing to this register will set the GPIO pin high or low if the pin is enabled for GPIO output mode. If the GPIO is
not in output mode the value written is latched but will not be reflected on the GPIO pin or reads of the GPxDAT
register. The written value latched will become active when the GPIO is put into GPIO Output mode
A system reset will clear all bits and latched values to zero.
NOTE: Bit-wise read-modify-write operations should not be performed on this register. For bit-wise operations
the GPxSET, GPxCLEAR, or GPxTOGGLE registers should be used instead. If direct writes to GPxDAT are
necessary, the entire register should be written at one time.
Figure 8-102. GPADAT Register
31 30 29 28 27 26 25 24
GPIO31 GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-114. GPADAT Register Field Descriptions

Bit Field Type Reset Description
31 GPIO31 R/W 0h Data Register for this pin
Reset type: SYSRSn
30 GPIO30 R/W 0h Data Register for this pin
Reset type: SYSRSn
29 GPIO29 R/W 0h Data Register for this pin
Reset type: SYSRSn
28 GPIO28 R/W 0h Data Register for this pin
Reset type: SYSRSn
27 GPIO27 R/W 0h Data Register for this pin
Reset type: SYSRSn
26 GPIO26 R/W 0h Data Register for this pin
Reset type: SYSRSn
25 GPIO25 R/W 0h Data Register for this pin
Reset type: SYSRSn
24 GPIO24 R/W 0h Data Register for this pin
Reset type: SYSRSn
23 GPIO23 R/W 0h Data Register for this pin
Reset type: SYSRSn
22 GPIO22 R/W 0h Data Register for this pin
Reset type: SYSRSn

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Table 8-114. GPADAT Register Field Descriptions (continued)

Bit Field Type Reset Description
21 GPIO21 R/W 0h Data Register for this pin
Reset type: SYSRSn
20 GPIO20 R/W 0h Data Register for this pin
Reset type: SYSRSn
19 GPIO19 R/W 0h Data Register for this pin
Reset type: SYSRSn
18 GPIO18 R/W 0h Data Register for this pin
Reset type: SYSRSn
17 GPIO17 R/W 0h Data Register for this pin
Reset type: SYSRSn
16 GPIO16 R/W 0h Data Register for this pin
Reset type: SYSRSn
15 GPIO15 R/W 0h Data Register for this pin
Reset type: SYSRSn
14 GPIO14 R/W 0h Data Register for this pin
Reset type: SYSRSn
13 GPIO13 R/W 0h Data Register for this pin
Reset type: SYSRSn
12 GPIO12 R/W 0h Data Register for this pin
Reset type: SYSRSn
11 GPIO11 R/W 0h Data Register for this pin
Reset type: SYSRSn
10 GPIO10 R/W 0h Data Register for this pin
Reset type: SYSRSn
9 GPIO9 R/W 0h Data Register for this pin
Reset type: SYSRSn
8 GPIO8 R/W 0h Data Register for this pin
Reset type: SYSRSn
7 GPIO7 R/W 0h Data Register for this pin
Reset type: SYSRSn
6 GPIO6 R/W 0h Data Register for this pin
Reset type: SYSRSn
5 GPIO5 R/W 0h Data Register for this pin
Reset type: SYSRSn
4 GPIO4 R/W 0h Data Register for this pin
Reset type: SYSRSn
3 GPIO3 R/W 0h Data Register for this pin
Reset type: SYSRSn
2 GPIO2 R/W 0h Data Register for this pin
Reset type: SYSRSn
1 GPIO1 R/W 0h Data Register for this pin
Reset type: SYSRSn
0 GPIO0 R/W 0h Data Register for this pin
Reset type: SYSRSn

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8.10.3.2 GPASET Register (Offset = 2h) [Reset = 00000000h]

GPASET is shown in Figure 8-103 and described in Table 8-115.
Return to the Summary Table.
GPIO A Data Set Register (GPIO0 to 31)
Writing a 1 will force GPIO output data latch to 1.
Writes of 0 are ignored.
Always reads back a 0.
Figure 8-103. GPASET Register
31 30 29 28 27 26 25 24
GPIO31 GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-115. GPASET Register Field Descriptions

Bit Field Type Reset Description
31 GPIO31 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
30 GPIO30 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
29 GPIO29 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
28 GPIO28 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
27 GPIO27 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
26 GPIO26 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
25 GPIO25 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
24 GPIO24 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
23 GPIO23 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
22 GPIO22 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
21 GPIO21 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
20 GPIO20 R/W 0h Output Set bit for this pin
Reset type: SYSRSn

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Table 8-115. GPASET Register Field Descriptions (continued)

Bit Field Type Reset Description
19 GPIO19 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
18 GPIO18 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
17 GPIO17 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
16 GPIO16 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
15 GPIO15 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
14 GPIO14 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
13 GPIO13 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
12 GPIO12 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
11 GPIO11 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
10 GPIO10 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
9 GPIO9 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
8 GPIO8 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
7 GPIO7 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
6 GPIO6 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
5 GPIO5 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
4 GPIO4 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
3 GPIO3 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
2 GPIO2 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
1 GPIO1 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
0 GPIO0 R/W 0h Output Set bit for this pin
Reset type: SYSRSn

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8.10.3.3 GPACLEAR Register (Offset = 4h) [Reset = 00000000h]

GPACLEAR is shown in Figure 8-104 and described in Table 8-116.
Return to the Summary Table.
GPIO A Data Clear Register (GPIO0 to 31)
Writing a 1 will force GPIO0 output data latch to 0.
Writes of 0 are ignored.
Always reads back a 0.
Figure 8-104. GPACLEAR Register
31 30 29 28 27 26 25 24
GPIO31 GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-116. GPACLEAR Register Field Descriptions

Bit Field Type Reset Description
31 GPIO31 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
30 GPIO30 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
29 GPIO29 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
28 GPIO28 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
27 GPIO27 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
26 GPIO26 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
25 GPIO25 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
24 GPIO24 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
23 GPIO23 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
22 GPIO22 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
21 GPIO21 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
20 GPIO20 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn

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Table 8-116. GPACLEAR Register Field Descriptions (continued)

Bit Field Type Reset Description
19 GPIO19 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
18 GPIO18 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
17 GPIO17 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
16 GPIO16 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
15 GPIO15 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
14 GPIO14 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
13 GPIO13 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
12 GPIO12 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
11 GPIO11 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
10 GPIO10 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
9 GPIO9 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
8 GPIO8 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
7 GPIO7 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
6 GPIO6 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
5 GPIO5 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
4 GPIO4 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
3 GPIO3 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
2 GPIO2 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
1 GPIO1 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
0 GPIO0 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn

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8.10.3.4 GPATOGGLE Register (Offset = 6h) [Reset = 00000000h]

GPATOGGLE is shown in Figure 8-105 and described in Table 8-117.
Return to the Summary Table.
GPIO A Data Toggle Register (GPIO0 to 31)
Writing a 1 will toggle GPIO0 output data latch 1 to 0 or 0 to 1.
Writes of 0 are ignored.
Always reads back a 0.
Figure 8-105. GPATOGGLE Register
31 30 29 28 27 26 25 24
GPIO31 GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-117. GPATOGGLE Register Field Descriptions

Bit Field Type Reset Description
31 GPIO31 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
30 GPIO30 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
29 GPIO29 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
28 GPIO28 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
27 GPIO27 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
26 GPIO26 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
25 GPIO25 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
24 GPIO24 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
23 GPIO23 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
22 GPIO22 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
21 GPIO21 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
20 GPIO20 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn

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Table 8-117. GPATOGGLE Register Field Descriptions (continued)

Bit Field Type Reset Description
19 GPIO19 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
18 GPIO18 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
17 GPIO17 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
16 GPIO16 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
15 GPIO15 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
14 GPIO14 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
13 GPIO13 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
12 GPIO12 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
11 GPIO11 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
10 GPIO10 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
9 GPIO9 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
8 GPIO8 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
7 GPIO7 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
6 GPIO6 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
5 GPIO5 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
4 GPIO4 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
3 GPIO3 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
2 GPIO2 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
1 GPIO1 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
0 GPIO0 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn

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8.10.3.5 GPBDAT Register (Offset = 8h) [Reset = 00000000h]

GPBDAT is shown in Figure 8-106 and described in Table 8-118.
Return to the Summary Table.
GPIO B Data Register (GPIO32 to 63)
Reading this register reflects the current state of the GPIO pin regardless of which mode the GPIO is in.
Writing to this register will set the GPIO pin high or low if the pin is enabled for GPIO output mode. If the GPIO is
not in output mode the value written is latched but will not be reflected on the GPIO pin or reads of the GPxDAT
register. The written value latched will become active when the GPIO is put into GPIO Output mode
A system reset will clear all bits and latched values to zero.
NOTE: Bit-wise read-modify-write operations should not be performed on this register. For bit-wise operations
the GPxSET, GPxCLEAR, or GPxTOGGLE registers should be used instead. If direct writes to GPxDAT are
necessary, the entire register should be written at one time.
Figure 8-106. GPBDAT Register
31 30 29 28 27 26 25 24
GPIO63 GPIO62 GPIO61 GPIO60 GPIO59 GPIO58 GPIO57 GPIO56
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO55 GPIO54 GPIO53 GPIO52 GPIO51 GPIO50 GPIO49 GPIO48
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO47 GPIO46 GPIO45 GPIO44 GPIO43 GPIO42 GPIO41 GPIO40
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO39 GPIO38 GPIO37 GPIO36 GPIO35 GPIO34 GPIO33 GPIO32
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-118. GPBDAT Register Field Descriptions

Bit Field Type Reset Description
31 GPIO63 R/W 0h Data Register for this pin
Reset type: SYSRSn
30 GPIO62 R/W 0h Data Register for this pin
Reset type: SYSRSn
29 GPIO61 R/W 0h Data Register for this pin
Reset type: SYSRSn
28 GPIO60 R/W 0h Data Register for this pin
Reset type: SYSRSn
27 GPIO59 R/W 0h Data Register for this pin
Reset type: SYSRSn
26 GPIO58 R/W 0h Data Register for this pin
Reset type: SYSRSn
25 GPIO57 R/W 0h Data Register for this pin
Reset type: SYSRSn
24 GPIO56 R/W 0h Data Register for this pin
Reset type: SYSRSn
23 GPIO55 R/W 0h Data Register for this pin
Reset type: SYSRSn
22 GPIO54 R/W 0h Data Register for this pin
Reset type: SYSRSn

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Table 8-118. GPBDAT Register Field Descriptions (continued)

Bit Field Type Reset Description
21 GPIO53 R/W 0h Data Register for this pin
Reset type: SYSRSn
20 GPIO52 R/W 0h Data Register for this pin
Reset type: SYSRSn
19 GPIO51 R/W 0h Data Register for this pin
Reset type: SYSRSn
18 GPIO50 R/W 0h Data Register for this pin
Reset type: SYSRSn
17 GPIO49 R/W 0h Data Register for this pin
Reset type: SYSRSn
16 GPIO48 R/W 0h Data Register for this pin
Reset type: SYSRSn
15 GPIO47 R/W 0h Data Register for this pin
Reset type: SYSRSn
14 GPIO46 R/W 0h Data Register for this pin
Reset type: SYSRSn
13 GPIO45 R/W 0h Data Register for this pin
Reset type: SYSRSn
12 GPIO44 R/W 0h Data Register for this pin
Reset type: SYSRSn
11 GPIO43 R/W 0h Data Register for this pin
Reset type: SYSRSn
10 GPIO42 R/W 0h Data Register for this pin
Reset type: SYSRSn
9 GPIO41 R/W 0h Data Register for this pin
Reset type: SYSRSn
8 GPIO40 R/W 0h Data Register for this pin
Reset type: SYSRSn
7 GPIO39 R/W 0h Data Register for this pin
Reset type: SYSRSn
6 GPIO38 R/W 0h Data Register for this pin
Reset type: SYSRSn
5 GPIO37 R/W 0h Data Register for this pin
Reset type: SYSRSn
4 GPIO36 R/W 0h Data Register for this pin
Reset type: SYSRSn
3 GPIO35 R/W 0h Data Register for this pin
Reset type: SYSRSn
2 GPIO34 R/W 0h Data Register for this pin
Reset type: SYSRSn
1 GPIO33 R/W 0h Data Register for this pin
Reset type: SYSRSn
0 GPIO32 R/W 0h Data Register for this pin
Reset type: SYSRSn

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8.10.3.6 GPBSET Register (Offset = Ah) [Reset = 00000000h]

GPBSET is shown in Figure 8-107 and described in Table 8-119.
Return to the Summary Table.
GPIO B Data Set Register (GPIO32 to 63)
Writing a 1 will force GPIO output data latch to 1.
Writes of 0 are ignored.
Always reads back a 0.
Figure 8-107. GPBSET Register
31 30 29 28 27 26 25 24
GPIO63 GPIO62 GPIO61 GPIO60 GPIO59 GPIO58 GPIO57 GPIO56
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO55 GPIO54 GPIO53 GPIO52 GPIO51 GPIO50 GPIO49 GPIO48
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO47 GPIO46 GPIO45 GPIO44 GPIO43 GPIO42 GPIO41 GPIO40
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO39 GPIO38 GPIO37 GPIO36 GPIO35 GPIO34 GPIO33 GPIO32
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-119. GPBSET Register Field Descriptions

Bit Field Type Reset Description
31 GPIO63 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
30 GPIO62 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
29 GPIO61 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
28 GPIO60 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
27 GPIO59 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
26 GPIO58 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
25 GPIO57 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
24 GPIO56 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
23 GPIO55 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
22 GPIO54 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
21 GPIO53 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
20 GPIO52 R/W 0h Output Set bit for this pin
Reset type: SYSRSn

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Table 8-119. GPBSET Register Field Descriptions (continued)

Bit Field Type Reset Description
19 GPIO51 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
18 GPIO50 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
17 GPIO49 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
16 GPIO48 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
15 GPIO47 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
14 GPIO46 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
13 GPIO45 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
12 GPIO44 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
11 GPIO43 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
10 GPIO42 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
9 GPIO41 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
8 GPIO40 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
7 GPIO39 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
6 GPIO38 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
5 GPIO37 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
4 GPIO36 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
3 GPIO35 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
2 GPIO34 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
1 GPIO33 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
0 GPIO32 R/W 0h Output Set bit for this pin
Reset type: SYSRSn

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8.10.3.7 GPBCLEAR Register (Offset = Ch) [Reset = 00000000h]

GPBCLEAR is shown in Figure 8-108 and described in Table 8-120.
Return to the Summary Table.
GPIO B Data Clear Register (GPIO32 to 63)
Writing a 1 will force GPIO0 output data latch to 0.
Writes of 0 are ignored.
Always reads back a 0.
Figure 8-108. GPBCLEAR Register
31 30 29 28 27 26 25 24
GPIO63 GPIO62 GPIO61 GPIO60 GPIO59 GPIO58 GPIO57 GPIO56
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO55 GPIO54 GPIO53 GPIO52 GPIO51 GPIO50 GPIO49 GPIO48
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO47 GPIO46 GPIO45 GPIO44 GPIO43 GPIO42 GPIO41 GPIO40
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO39 GPIO38 GPIO37 GPIO36 GPIO35 GPIO34 GPIO33 GPIO32
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-120. GPBCLEAR Register Field Descriptions

Bit Field Type Reset Description
31 GPIO63 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
30 GPIO62 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
29 GPIO61 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
28 GPIO60 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
27 GPIO59 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
26 GPIO58 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
25 GPIO57 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
24 GPIO56 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
23 GPIO55 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
22 GPIO54 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
21 GPIO53 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
20 GPIO52 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn

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Table 8-120. GPBCLEAR Register Field Descriptions (continued)

Bit Field Type Reset Description
19 GPIO51 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
18 GPIO50 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
17 GPIO49 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
16 GPIO48 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
15 GPIO47 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
14 GPIO46 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
13 GPIO45 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
12 GPIO44 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
11 GPIO43 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
10 GPIO42 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
9 GPIO41 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
8 GPIO40 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
7 GPIO39 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
6 GPIO38 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
5 GPIO37 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
4 GPIO36 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
3 GPIO35 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
2 GPIO34 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
1 GPIO33 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
0 GPIO32 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn

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8.10.3.8 GPBTOGGLE Register (Offset = Eh) [Reset = 00000000h]

GPBTOGGLE is shown in Figure 8-109 and described in Table 8-121.
Return to the Summary Table.
GPIO B Data Toggle Register (GPIO32 to 63)
Writing a 1 will toggle GPIO0 output data latch 1 to 0 or 0 to 1.
Writes of 0 are ignored.
Always reads back a 0.
Figure 8-109. GPBTOGGLE Register
31 30 29 28 27 26 25 24
GPIO63 GPIO62 GPIO61 GPIO60 GPIO59 GPIO58 GPIO57 GPIO56
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO55 GPIO54 GPIO53 GPIO52 GPIO51 GPIO50 GPIO49 GPIO48
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO47 GPIO46 GPIO45 GPIO44 GPIO43 GPIO42 GPIO41 GPIO40
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO39 GPIO38 GPIO37 GPIO36 GPIO35 GPIO34 GPIO33 GPIO32
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-121. GPBTOGGLE Register Field Descriptions

Bit Field Type Reset Description
31 GPIO63 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
30 GPIO62 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
29 GPIO61 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
28 GPIO60 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
27 GPIO59 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
26 GPIO58 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
25 GPIO57 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
24 GPIO56 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
23 GPIO55 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
22 GPIO54 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
21 GPIO53 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
20 GPIO52 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn

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Table 8-121. GPBTOGGLE Register Field Descriptions (continued)

Bit Field Type Reset Description
19 GPIO51 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
18 GPIO50 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
17 GPIO49 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
16 GPIO48 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
15 GPIO47 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
14 GPIO46 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
13 GPIO45 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
12 GPIO44 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
11 GPIO43 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
10 GPIO42 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
9 GPIO41 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
8 GPIO40 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
7 GPIO39 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
6 GPIO38 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
5 GPIO37 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
4 GPIO36 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
3 GPIO35 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
2 GPIO34 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
1 GPIO33 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
0 GPIO32 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn

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8.10.3.9 GPCDAT Register (Offset = 10h) [Reset = 00000000h]

GPCDAT is shown in Figure 8-110 and described in Table 8-122.
Return to the Summary Table.
GPIO C Data Register (GPIO64 to 95)
Reading this register reflects the current state of the GPIO pin regardless of which mode the GPIO is in.
Writing to this register will set the GPIO pin high or low if the pin is enabled for GPIO output mode. If the GPIO is
not in output mode the value written is latched but will not be reflected on the GPIO pin or reads of the GPxDAT
register. The written value latched will become active when the GPIO is put into GPIO Output mode
A system reset will clear all bits and latched values to zero.
NOTE: Bit-wise read-modify-write operations should not be performed on this register. For bit-wise operations
the GPxSET, GPxCLEAR, or GPxTOGGLE registers should be used instead. If direct writes to GPxDAT are
necessary, the entire register should be written at one time.
Figure 8-110. GPCDAT Register
31 30 29 28 27 26 25 24
GPIO95 GPIO94 GPIO93 GPIO92 GPIO91 GPIO90 GPIO89 GPIO88
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO87 GPIO86 GPIO85 GPIO84 GPIO83 GPIO82 GPIO81 GPIO80
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO79 GPIO78 GPIO77 GPIO76 GPIO75 GPIO74 GPIO73 GPIO72
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO71 GPIO70 GPIO69 GPIO68 GPIO67 GPIO66 GPIO65 GPIO64
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-122. GPCDAT Register Field Descriptions

Bit Field Type Reset Description
31 GPIO95 R/W 0h Data Register for this pin
Reset type: SYSRSn
30 GPIO94 R/W 0h Data Register for this pin
Reset type: SYSRSn
29 GPIO93 R/W 0h Data Register for this pin
Reset type: SYSRSn
28 GPIO92 R/W 0h Data Register for this pin
Reset type: SYSRSn
27 GPIO91 R/W 0h Data Register for this pin
Reset type: SYSRSn
26 GPIO90 R/W 0h Data Register for this pin
Reset type: SYSRSn
25 GPIO89 R/W 0h Data Register for this pin
Reset type: SYSRSn
24 GPIO88 R/W 0h Data Register for this pin
Reset type: SYSRSn
23 GPIO87 R/W 0h Data Register for this pin
Reset type: SYSRSn
22 GPIO86 R/W 0h Data Register for this pin
Reset type: SYSRSn

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Table 8-122. GPCDAT Register Field Descriptions (continued)

Bit Field Type Reset Description
21 GPIO85 R/W 0h Data Register for this pin
Reset type: SYSRSn
20 GPIO84 R/W 0h Data Register for this pin
Reset type: SYSRSn
19 GPIO83 R/W 0h Data Register for this pin
Reset type: SYSRSn
18 GPIO82 R/W 0h Data Register for this pin
Reset type: SYSRSn
17 GPIO81 R/W 0h Data Register for this pin
Reset type: SYSRSn
16 GPIO80 R/W 0h Data Register for this pin
Reset type: SYSRSn
15 GPIO79 R/W 0h Data Register for this pin
Reset type: SYSRSn
14 GPIO78 R/W 0h Data Register for this pin
Reset type: SYSRSn
13 GPIO77 R/W 0h Data Register for this pin
Reset type: SYSRSn
12 GPIO76 R/W 0h Data Register for this pin
Reset type: SYSRSn
11 GPIO75 R/W 0h Data Register for this pin
Reset type: SYSRSn
10 GPIO74 R/W 0h Data Register for this pin
Reset type: SYSRSn
9 GPIO73 R/W 0h Data Register for this pin
Reset type: SYSRSn
8 GPIO72 R/W 0h Data Register for this pin
Reset type: SYSRSn
7 GPIO71 R/W 0h Data Register for this pin
Reset type: SYSRSn
6 GPIO70 R/W 0h Data Register for this pin
Reset type: SYSRSn
5 GPIO69 R/W 0h Data Register for this pin
Reset type: SYSRSn
4 GPIO68 R/W 0h Data Register for this pin
Reset type: SYSRSn
3 GPIO67 R/W 0h Data Register for this pin
Reset type: SYSRSn
2 GPIO66 R/W 0h Data Register for this pin
Reset type: SYSRSn
1 GPIO65 R/W 0h Data Register for this pin
Reset type: SYSRSn
0 GPIO64 R/W 0h Data Register for this pin
Reset type: SYSRSn

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8.10.3.10 GPCSET Register (Offset = 12h) [Reset = 00000000h]

GPCSET is shown in Figure 8-111 and described in Table 8-123.
Return to the Summary Table.
GPIO C Data Set Register (GPIO64 to 95)
Writing a 1 will force GPIO output data latch to 1.
Writes of 0 are ignored.
Always reads back a 0.
Figure 8-111. GPCSET Register
31 30 29 28 27 26 25 24
GPIO95 GPIO94 GPIO93 GPIO92 GPIO91 GPIO90 GPIO89 GPIO88
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO87 GPIO86 GPIO85 GPIO84 GPIO83 GPIO82 GPIO81 GPIO80
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO79 GPIO78 GPIO77 GPIO76 GPIO75 GPIO74 GPIO73 GPIO72
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO71 GPIO70 GPIO69 GPIO68 GPIO67 GPIO66 GPIO65 GPIO64
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-123. GPCSET Register Field Descriptions

Bit Field Type Reset Description
31 GPIO95 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
30 GPIO94 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
29 GPIO93 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
28 GPIO92 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
27 GPIO91 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
26 GPIO90 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
25 GPIO89 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
24 GPIO88 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
23 GPIO87 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
22 GPIO86 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
21 GPIO85 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
20 GPIO84 R/W 0h Output Set bit for this pin
Reset type: SYSRSn

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Table 8-123. GPCSET Register Field Descriptions (continued)

Bit Field Type Reset Description
19 GPIO83 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
18 GPIO82 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
17 GPIO81 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
16 GPIO80 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
15 GPIO79 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
14 GPIO78 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
13 GPIO77 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
12 GPIO76 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
11 GPIO75 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
10 GPIO74 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
9 GPIO73 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
8 GPIO72 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
7 GPIO71 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
6 GPIO70 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
5 GPIO69 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
4 GPIO68 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
3 GPIO67 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
2 GPIO66 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
1 GPIO65 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
0 GPIO64 R/W 0h Output Set bit for this pin
Reset type: SYSRSn

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8.10.3.11 GPCCLEAR Register (Offset = 14h) [Reset = 00000000h]

GPCCLEAR is shown in Figure 8-112 and described in Table 8-124.
Return to the Summary Table.
GPIO C Data Clear Register (GPIO64 to 95)
Writing a 1 will force GPIO0 output data latch to 0.
Writes of 0 are ignored.
Always reads back a 0.
Figure 8-112. GPCCLEAR Register
31 30 29 28 27 26 25 24
GPIO95 GPIO94 GPIO93 GPIO92 GPIO91 GPIO90 GPIO89 GPIO88
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO87 GPIO86 GPIO85 GPIO84 GPIO83 GPIO82 GPIO81 GPIO80
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO79 GPIO78 GPIO77 GPIO76 GPIO75 GPIO74 GPIO73 GPIO72
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO71 GPIO70 GPIO69 GPIO68 GPIO67 GPIO66 GPIO65 GPIO64
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-124. GPCCLEAR Register Field Descriptions

Bit Field Type Reset Description
31 GPIO95 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
30 GPIO94 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
29 GPIO93 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
28 GPIO92 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
27 GPIO91 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
26 GPIO90 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
25 GPIO89 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
24 GPIO88 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
23 GPIO87 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
22 GPIO86 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
21 GPIO85 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
20 GPIO84 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn

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Table 8-124. GPCCLEAR Register Field Descriptions (continued)

Bit Field Type Reset Description
19 GPIO83 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
18 GPIO82 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
17 GPIO81 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
16 GPIO80 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
15 GPIO79 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
14 GPIO78 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
13 GPIO77 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
12 GPIO76 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
11 GPIO75 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
10 GPIO74 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
9 GPIO73 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
8 GPIO72 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
7 GPIO71 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
6 GPIO70 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
5 GPIO69 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
4 GPIO68 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
3 GPIO67 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
2 GPIO66 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
1 GPIO65 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
0 GPIO64 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn

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8.10.3.12 GPCTOGGLE Register (Offset = 16h) [Reset = 00000000h]

GPCTOGGLE is shown in Figure 8-113 and described in Table 8-125.
Return to the Summary Table.
GPIO C Data Toggle Register (GPIO64 to 95)
Writing a 1 will toggle GPIO0 output data latch 1 to 0 or 0 to 1.
Writes of 0 are ignored.
Always reads back a 0.
Figure 8-113. GPCTOGGLE Register
31 30 29 28 27 26 25 24
GPIO95 GPIO94 GPIO93 GPIO92 GPIO91 GPIO90 GPIO89 GPIO88
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO87 GPIO86 GPIO85 GPIO84 GPIO83 GPIO82 GPIO81 GPIO80
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO79 GPIO78 GPIO77 GPIO76 GPIO75 GPIO74 GPIO73 GPIO72
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO71 GPIO70 GPIO69 GPIO68 GPIO67 GPIO66 GPIO65 GPIO64
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-125. GPCTOGGLE Register Field Descriptions

Bit Field Type Reset Description
31 GPIO95 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
30 GPIO94 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
29 GPIO93 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
28 GPIO92 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
27 GPIO91 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
26 GPIO90 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
25 GPIO89 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
24 GPIO88 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
23 GPIO87 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
22 GPIO86 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
21 GPIO85 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
20 GPIO84 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn

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Table 8-125. GPCTOGGLE Register Field Descriptions (continued)

Bit Field Type Reset Description
19 GPIO83 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
18 GPIO82 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
17 GPIO81 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
16 GPIO80 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
15 GPIO79 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
14 GPIO78 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
13 GPIO77 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
12 GPIO76 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
11 GPIO75 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
10 GPIO74 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
9 GPIO73 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
8 GPIO72 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
7 GPIO71 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
6 GPIO70 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
5 GPIO69 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
4 GPIO68 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
3 GPIO67 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
2 GPIO66 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
1 GPIO65 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
0 GPIO64 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn

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8.10.3.13 GPDDAT Register (Offset = 18h) [Reset = 00000000h]

GPDDAT is shown in Figure 8-114 and described in Table 8-126.
Return to the Summary Table.
GPIO D Data Register (GPIO96 to 127)
Reading this register reflects the current state of the GPIO pin regardless of which mode the GPIO is in.
Writing to this register will set the GPIO pin high or low if the pin is enabled for GPIO output mode. If the GPIO is
not in output mode the value written is latched but will not be reflected on the GPIO pin or reads of the GPxDAT
register. The written value latched will become active when the GPIO is put into GPIO Output mode
A system reset will clear all bits and latched values to zero.
NOTE: Bit-wise read-modify-write operations should not be performed on this register. For bit-wise operations
the GPxSET, GPxCLEAR, or GPxTOGGLE registers should be used instead. If direct writes to GPxDAT are
necessary, the entire register should be written at one time.
Figure 8-114. GPDDAT Register
31 30 29 28 27 26 25 24
GPIO127 GPIO126 GPIO125 GPIO124 GPIO123 GPIO122 GPIO121 GPIO120
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO119 GPIO118 GPIO117 GPIO116 GPIO115 GPIO114 GPIO113 GPIO112
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO111 GPIO110 GPIO109 GPIO108 GPIO107 GPIO106 GPIO105 GPIO104
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO103 GPIO102 GPIO101 GPIO100 GPIO99 GPIO98 GPIO97 GPIO96
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-126. GPDDAT Register Field Descriptions

Bit Field Type Reset Description
31 GPIO127 R/W 0h Data Register for this pin
Reset type: SYSRSn
30 GPIO126 R/W 0h Data Register for this pin
Reset type: SYSRSn
29 GPIO125 R/W 0h Data Register for this pin
Reset type: SYSRSn
28 GPIO124 R/W 0h Data Register for this pin
Reset type: SYSRSn
27 GPIO123 R/W 0h Data Register for this pin
Reset type: SYSRSn
26 GPIO122 R/W 0h Data Register for this pin
Reset type: SYSRSn
25 GPIO121 R/W 0h Data Register for this pin
Reset type: SYSRSn
24 GPIO120 R/W 0h Data Register for this pin
Reset type: SYSRSn
23 GPIO119 R/W 0h Data Register for this pin
Reset type: SYSRSn
22 GPIO118 R/W 0h Data Register for this pin
Reset type: SYSRSn

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Table 8-126. GPDDAT Register Field Descriptions (continued)

Bit Field Type Reset Description
21 GPIO117 R/W 0h Data Register for this pin
Reset type: SYSRSn
20 GPIO116 R/W 0h Data Register for this pin
Reset type: SYSRSn
19 GPIO115 R/W 0h Data Register for this pin
Reset type: SYSRSn
18 GPIO114 R/W 0h Data Register for this pin
Reset type: SYSRSn
17 GPIO113 R/W 0h Data Register for this pin
Reset type: SYSRSn
16 GPIO112 R/W 0h Data Register for this pin
Reset type: SYSRSn
15 GPIO111 R/W 0h Data Register for this pin
Reset type: SYSRSn
14 GPIO110 R/W 0h Data Register for this pin
Reset type: SYSRSn
13 GPIO109 R/W 0h Data Register for this pin
Reset type: SYSRSn
12 GPIO108 R/W 0h Data Register for this pin
Reset type: SYSRSn
11 GPIO107 R/W 0h Data Register for this pin
Reset type: SYSRSn
10 GPIO106 R/W 0h Data Register for this pin
Reset type: SYSRSn
9 GPIO105 R/W 0h Data Register for this pin
Reset type: SYSRSn
8 GPIO104 R/W 0h Data Register for this pin
Reset type: SYSRSn
7 GPIO103 R/W 0h Data Register for this pin
Reset type: SYSRSn
6 GPIO102 R/W 0h Data Register for this pin
Reset type: SYSRSn
5 GPIO101 R/W 0h Data Register for this pin
Reset type: SYSRSn
4 GPIO100 R/W 0h Data Register for this pin
Reset type: SYSRSn
3 GPIO99 R/W 0h Data Register for this pin
Reset type: SYSRSn
2 GPIO98 R/W 0h Data Register for this pin
Reset type: SYSRSn
1 GPIO97 R/W 0h Data Register for this pin
Reset type: SYSRSn
0 GPIO96 R/W 0h Data Register for this pin
Reset type: SYSRSn

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8.10.3.14 GPDSET Register (Offset = 1Ah) [Reset = 00000000h]

GPDSET is shown in Figure 8-115 and described in Table 8-127.
Return to the Summary Table.
GPIO D Data Set Register (GPIO96 to 127)
Writing a 1 will force GPIO output data latch to 1.
Writes of 0 are ignored.
Always reads back a 0.
Figure 8-115. GPDSET Register
31 30 29 28 27 26 25 24
GPIO127 GPIO126 GPIO125 GPIO124 GPIO123 GPIO122 GPIO121 GPIO120
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO119 GPIO118 GPIO117 GPIO116 GPIO115 GPIO114 GPIO113 GPIO112
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO111 GPIO110 GPIO109 GPIO108 GPIO107 GPIO106 GPIO105 GPIO104
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO103 GPIO102 GPIO101 GPIO100 GPIO99 GPIO98 GPIO97 GPIO96
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-127. GPDSET Register Field Descriptions

Bit Field Type Reset Description
31 GPIO127 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
30 GPIO126 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
29 GPIO125 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
28 GPIO124 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
27 GPIO123 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
26 GPIO122 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
25 GPIO121 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
24 GPIO120 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
23 GPIO119 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
22 GPIO118 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
21 GPIO117 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
20 GPIO116 R/W 0h Output Set bit for this pin
Reset type: SYSRSn

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Table 8-127. GPDSET Register Field Descriptions (continued)

Bit Field Type Reset Description
19 GPIO115 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
18 GPIO114 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
17 GPIO113 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
16 GPIO112 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
15 GPIO111 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
14 GPIO110 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
13 GPIO109 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
12 GPIO108 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
11 GPIO107 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
10 GPIO106 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
9 GPIO105 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
8 GPIO104 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
7 GPIO103 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
6 GPIO102 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
5 GPIO101 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
4 GPIO100 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
3 GPIO99 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
2 GPIO98 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
1 GPIO97 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
0 GPIO96 R/W 0h Output Set bit for this pin
Reset type: SYSRSn

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8.10.3.15 GPDCLEAR Register (Offset = 1Ch) [Reset = 00000000h]

GPDCLEAR is shown in Figure 8-116 and described in Table 8-128.
Return to the Summary Table.
GPIO D Data Clear Register (GPIO96 to 127)
Writing a 1 will force GPIO0 output data latch to 0.
Writes of 0 are ignored.
Always reads back a 0.
Figure 8-116. GPDCLEAR Register
31 30 29 28 27 26 25 24
GPIO127 GPIO126 GPIO125 GPIO124 GPIO123 GPIO122 GPIO121 GPIO120
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO119 GPIO118 GPIO117 GPIO116 GPIO115 GPIO114 GPIO113 GPIO112
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO111 GPIO110 GPIO109 GPIO108 GPIO107 GPIO106 GPIO105 GPIO104
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO103 GPIO102 GPIO101 GPIO100 GPIO99 GPIO98 GPIO97 GPIO96
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-128. GPDCLEAR Register Field Descriptions

Bit Field Type Reset Description
31 GPIO127 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
30 GPIO126 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
29 GPIO125 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
28 GPIO124 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
27 GPIO123 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
26 GPIO122 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
25 GPIO121 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
24 GPIO120 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
23 GPIO119 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
22 GPIO118 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
21 GPIO117 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
20 GPIO116 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn

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Table 8-128. GPDCLEAR Register Field Descriptions (continued)

Bit Field Type Reset Description
19 GPIO115 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
18 GPIO114 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
17 GPIO113 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
16 GPIO112 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
15 GPIO111 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
14 GPIO110 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
13 GPIO109 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
12 GPIO108 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
11 GPIO107 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
10 GPIO106 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
9 GPIO105 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
8 GPIO104 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
7 GPIO103 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
6 GPIO102 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
5 GPIO101 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
4 GPIO100 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
3 GPIO99 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
2 GPIO98 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
1 GPIO97 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
0 GPIO96 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn

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8.10.3.16 GPDTOGGLE Register (Offset = 1Eh) [Reset = 00000000h]

GPDTOGGLE is shown in Figure 8-117 and described in Table 8-129.
Return to the Summary Table.
GPIO D Data Toggle Register (GPIO96 to 127)
Writing a 1 will toggle GPIO0 output data latch 1 to 0 or 0 to 1.
Writes of 0 are ignored.
Always reads back a 0.
Figure 8-117. GPDTOGGLE Register
31 30 29 28 27 26 25 24
GPIO127 GPIO126 GPIO125 GPIO124 GPIO123 GPIO122 GPIO121 GPIO120
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO119 GPIO118 GPIO117 GPIO116 GPIO115 GPIO114 GPIO113 GPIO112
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO111 GPIO110 GPIO109 GPIO108 GPIO107 GPIO106 GPIO105 GPIO104
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO103 GPIO102 GPIO101 GPIO100 GPIO99 GPIO98 GPIO97 GPIO96
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-129. GPDTOGGLE Register Field Descriptions

Bit Field Type Reset Description
31 GPIO127 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
30 GPIO126 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
29 GPIO125 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
28 GPIO124 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
27 GPIO123 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
26 GPIO122 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
25 GPIO121 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
24 GPIO120 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
23 GPIO119 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
22 GPIO118 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
21 GPIO117 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
20 GPIO116 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn

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Table 8-129. GPDTOGGLE Register Field Descriptions (continued)

Bit Field Type Reset Description
19 GPIO115 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
18 GPIO114 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
17 GPIO113 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
16 GPIO112 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
15 GPIO111 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
14 GPIO110 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
13 GPIO109 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
12 GPIO108 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
11 GPIO107 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
10 GPIO106 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
9 GPIO105 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
8 GPIO104 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
7 GPIO103 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
6 GPIO102 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
5 GPIO101 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
4 GPIO100 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
3 GPIO99 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
2 GPIO98 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
1 GPIO97 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
0 GPIO96 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn

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8.10.3.17 GPEDAT Register (Offset = 20h) [Reset = 00000000h]

GPEDAT is shown in Figure 8-118 and described in Table 8-130.
Return to the Summary Table.
GPIO E Data Register (GPIO128 to 159)
Reading this register reflects the current state of the GPIO pin regardless of which mode the GPIO is in.
Writing to this register will set the GPIO pin high or low if the pin is enabled for GPIO output mode. If the GPIO is
not in output mode the value written is latched but will not be reflected on the GPIO pin or reads of the GPxDAT
register. The written value latched will become active when the GPIO is put into GPIO Output mode
A system reset will clear all bits and latched values to zero.
NOTE: Bit-wise read-modify-write operations should not be performed on this register. For bit-wise operations
the GPxSET, GPxCLEAR, or GPxTOGGLE registers should be used instead. If direct writes to GPxDAT are
necessary, the entire register should be written at one time.
Figure 8-118. GPEDAT Register
31 30 29 28 27 26 25 24
GPIO159 GPIO158 GPIO157 GPIO156 GPIO155 GPIO154 GPIO153 GPIO152
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO151 GPIO150 GPIO149 GPIO148 GPIO147 GPIO146 GPIO145 GPIO144
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO143 GPIO142 GPIO141 GPIO140 GPIO139 GPIO138 GPIO137 GPIO136
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO135 GPIO134 GPIO133 GPIO132 GPIO131 GPIO130 GPIO129 GPIO128
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-130. GPEDAT Register Field Descriptions

Bit Field Type Reset Description
31 GPIO159 R/W 0h Data Register for this pin
Reset type: SYSRSn
30 GPIO158 R/W 0h Data Register for this pin
Reset type: SYSRSn
29 GPIO157 R/W 0h Data Register for this pin
Reset type: SYSRSn
28 GPIO156 R/W 0h Data Register for this pin
Reset type: SYSRSn
27 GPIO155 R/W 0h Data Register for this pin
Reset type: SYSRSn
26 GPIO154 R/W 0h Data Register for this pin
Reset type: SYSRSn
25 GPIO153 R/W 0h Data Register for this pin
Reset type: SYSRSn
24 GPIO152 R/W 0h Data Register for this pin
Reset type: SYSRSn
23 GPIO151 R/W 0h Data Register for this pin
Reset type: SYSRSn
22 GPIO150 R/W 0h Data Register for this pin
Reset type: SYSRSn

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Table 8-130. GPEDAT Register Field Descriptions (continued)

Bit Field Type Reset Description
21 GPIO149 R/W 0h Data Register for this pin
Reset type: SYSRSn
20 GPIO148 R/W 0h Data Register for this pin
Reset type: SYSRSn
19 GPIO147 R/W 0h Data Register for this pin
Reset type: SYSRSn
18 GPIO146 R/W 0h Data Register for this pin
Reset type: SYSRSn
17 GPIO145 R/W 0h Data Register for this pin
Reset type: SYSRSn
16 GPIO144 R/W 0h Data Register for this pin
Reset type: SYSRSn
15 GPIO143 R/W 0h Data Register for this pin
Reset type: SYSRSn
14 GPIO142 R/W 0h Data Register for this pin
Reset type: SYSRSn
13 GPIO141 R/W 0h Data Register for this pin
Reset type: SYSRSn
12 GPIO140 R/W 0h Data Register for this pin
Reset type: SYSRSn
11 GPIO139 R/W 0h Data Register for this pin
Reset type: SYSRSn
10 GPIO138 R/W 0h Data Register for this pin
Reset type: SYSRSn
9 GPIO137 R/W 0h Data Register for this pin
Reset type: SYSRSn
8 GPIO136 R/W 0h Data Register for this pin
Reset type: SYSRSn
7 GPIO135 R/W 0h Data Register for this pin
Reset type: SYSRSn
6 GPIO134 R/W 0h Data Register for this pin
Reset type: SYSRSn
5 GPIO133 R/W 0h Data Register for this pin
Reset type: SYSRSn
4 GPIO132 R/W 0h Data Register for this pin
Reset type: SYSRSn
3 GPIO131 R/W 0h Data Register for this pin
Reset type: SYSRSn
2 GPIO130 R/W 0h Data Register for this pin
Reset type: SYSRSn
1 GPIO129 R/W 0h Data Register for this pin
Reset type: SYSRSn
0 GPIO128 R/W 0h Data Register for this pin
Reset type: SYSRSn

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8.10.3.18 GPESET Register (Offset = 22h) [Reset = 00000000h]

GPESET is shown in Figure 8-119 and described in Table 8-131.
Return to the Summary Table.
GPIO E Data Set Register (GPIO128 to 159)
Writing a 1 will force GPIO output data latch to 1.
Writes of 0 are ignored.
Always reads back a 0.
Figure 8-119. GPESET Register
31 30 29 28 27 26 25 24
GPIO159 GPIO158 GPIO157 GPIO156 GPIO155 GPIO154 GPIO153 GPIO152
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO151 GPIO150 GPIO149 GPIO148 GPIO147 GPIO146 GPIO145 GPIO144
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO143 GPIO142 GPIO141 GPIO140 GPIO139 GPIO138 GPIO137 GPIO136
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO135 GPIO134 GPIO133 GPIO132 GPIO131 GPIO130 GPIO129 GPIO128
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-131. GPESET Register Field Descriptions

Bit Field Type Reset Description
31 GPIO159 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
30 GPIO158 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
29 GPIO157 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
28 GPIO156 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
27 GPIO155 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
26 GPIO154 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
25 GPIO153 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
24 GPIO152 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
23 GPIO151 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
22 GPIO150 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
21 GPIO149 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
20 GPIO148 R/W 0h Output Set bit for this pin
Reset type: SYSRSn

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Table 8-131. GPESET Register Field Descriptions (continued)

Bit Field Type Reset Description
19 GPIO147 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
18 GPIO146 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
17 GPIO145 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
16 GPIO144 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
15 GPIO143 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
14 GPIO142 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
13 GPIO141 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
12 GPIO140 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
11 GPIO139 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
10 GPIO138 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
9 GPIO137 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
8 GPIO136 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
7 GPIO135 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
6 GPIO134 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
5 GPIO133 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
4 GPIO132 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
3 GPIO131 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
2 GPIO130 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
1 GPIO129 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
0 GPIO128 R/W 0h Output Set bit for this pin
Reset type: SYSRSn

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8.10.3.19 GPECLEAR Register (Offset = 24h) [Reset = 00000000h]

GPECLEAR is shown in Figure 8-120 and described in Table 8-132.
Return to the Summary Table.
GPIO E Data Clear Register (GPIO128 to 159)
Writing a 1 will force GPIO0 output data latch to 0.
Writes of 0 are ignored.
Always reads back a 0.
Figure 8-120. GPECLEAR Register
31 30 29 28 27 26 25 24
GPIO159 GPIO158 GPIO157 GPIO156 GPIO155 GPIO154 GPIO153 GPIO152
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO151 GPIO150 GPIO149 GPIO148 GPIO147 GPIO146 GPIO145 GPIO144
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO143 GPIO142 GPIO141 GPIO140 GPIO139 GPIO138 GPIO137 GPIO136
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO135 GPIO134 GPIO133 GPIO132 GPIO131 GPIO130 GPIO129 GPIO128
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-132. GPECLEAR Register Field Descriptions

Bit Field Type Reset Description
31 GPIO159 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
30 GPIO158 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
29 GPIO157 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
28 GPIO156 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
27 GPIO155 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
26 GPIO154 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
25 GPIO153 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
24 GPIO152 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
23 GPIO151 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
22 GPIO150 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
21 GPIO149 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
20 GPIO148 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn

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Table 8-132. GPECLEAR Register Field Descriptions (continued)

Bit Field Type Reset Description
19 GPIO147 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
18 GPIO146 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
17 GPIO145 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
16 GPIO144 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
15 GPIO143 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
14 GPIO142 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
13 GPIO141 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
12 GPIO140 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
11 GPIO139 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
10 GPIO138 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
9 GPIO137 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
8 GPIO136 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
7 GPIO135 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
6 GPIO134 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
5 GPIO133 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
4 GPIO132 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
3 GPIO131 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
2 GPIO130 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
1 GPIO129 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
0 GPIO128 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn

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8.10.3.20 GPETOGGLE Register (Offset = 26h) [Reset = 00000000h]

GPETOGGLE is shown in Figure 8-121 and described in Table 8-133.
Return to the Summary Table.
GPIO E Data Toggle Register (GPIO128 to 159)
Writing a 1 will toggle GPIO0 output data latch 1 to 0 or 0 to 1.
Writes of 0 are ignored.
Always reads back a 0.
Figure 8-121. GPETOGGLE Register
31 30 29 28 27 26 25 24
GPIO159 GPIO158 GPIO157 GPIO156 GPIO155 GPIO154 GPIO153 GPIO152
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO151 GPIO150 GPIO149 GPIO148 GPIO147 GPIO146 GPIO145 GPIO144
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO143 GPIO142 GPIO141 GPIO140 GPIO139 GPIO138 GPIO137 GPIO136
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO135 GPIO134 GPIO133 GPIO132 GPIO131 GPIO130 GPIO129 GPIO128
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-133. GPETOGGLE Register Field Descriptions

Bit Field Type Reset Description
31 GPIO159 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
30 GPIO158 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
29 GPIO157 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
28 GPIO156 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
27 GPIO155 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
26 GPIO154 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
25 GPIO153 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
24 GPIO152 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
23 GPIO151 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
22 GPIO150 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
21 GPIO149 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
20 GPIO148 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn

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Table 8-133. GPETOGGLE Register Field Descriptions (continued)

Bit Field Type Reset Description
19 GPIO147 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
18 GPIO146 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
17 GPIO145 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
16 GPIO144 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
15 GPIO143 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
14 GPIO142 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
13 GPIO141 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
12 GPIO140 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
11 GPIO139 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
10 GPIO138 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
9 GPIO137 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
8 GPIO136 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
7 GPIO135 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
6 GPIO134 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
5 GPIO133 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
4 GPIO132 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
3 GPIO131 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
2 GPIO130 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
1 GPIO129 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
0 GPIO128 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn

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8.10.3.21 GPFDAT Register (Offset = 28h) [Reset = 00000000h]

GPFDAT is shown in Figure 8-122 and described in Table 8-134.
Return to the Summary Table.
GPIO F Data Register (GPIO160 to 168)
Reading this register reflects the current state of the GPIO pin regardless of which mode the GPIO is in.
Writing to this register will set the GPIO pin high or low if the pin is enabled for GPIO output mode. If the GPIO is
not in output mode the value written is latched but will not be reflected on the GPIO pin or reads of the GPxDAT
register. The written value latched will become active when the GPIO is put into GPIO Output mode
A system reset will clear all bits and latched values to zero.
NOTE: Bit-wise read-modify-write operations should not be performed on this register. For bit-wise operations
the GPxSET, GPxCLEAR, or GPxTOGGLE registers should be used instead. If direct writes to GPxDAT are
necessary, the entire register should be written at one time.
Figure 8-122. GPFDAT Register
31 30 29 28 27 26 25 24
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED GPIO168
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO167 GPIO166 GPIO165 GPIO164 GPIO163 GPIO162 GPIO161 GPIO160
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-134. GPFDAT Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R/W 0h Reserved
30 RESERVED R/W 0h Reserved
29 RESERVED R/W 0h Reserved
28 RESERVED R/W 0h Reserved
27 RESERVED R/W 0h Reserved
26 RESERVED R/W 0h Reserved
25 RESERVED R/W 0h Reserved
24 RESERVED R/W 0h Reserved
23 RESERVED R/W 0h Reserved
22 RESERVED R/W 0h Reserved
21 RESERVED R/W 0h Reserved
20 RESERVED R/W 0h Reserved
19 RESERVED R/W 0h Reserved
18 RESERVED R/W 0h Reserved
17 RESERVED R/W 0h Reserved
16 RESERVED R/W 0h Reserved
15 RESERVED R/W 0h Reserved
14 RESERVED R/W 0h Reserved

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Table 8-134. GPFDAT Register Field Descriptions (continued)

Bit Field Type Reset Description
13 RESERVED R/W 0h Reserved
12 RESERVED R/W 0h Reserved
11 RESERVED R/W 0h Reserved
10 RESERVED R/W 0h Reserved
9 RESERVED R/W 0h Reserved
8 GPIO168 R/W 0h Data Register for this pin
Reset type: SYSRSn
7 GPIO167 R/W 0h Data Register for this pin
Reset type: SYSRSn
6 GPIO166 R/W 0h Data Register for this pin
Reset type: SYSRSn
5 GPIO165 R/W 0h Data Register for this pin
Reset type: SYSRSn
4 GPIO164 R/W 0h Data Register for this pin
Reset type: SYSRSn
3 GPIO163 R/W 0h Data Register for this pin
Reset type: SYSRSn
2 GPIO162 R/W 0h Data Register for this pin
Reset type: SYSRSn
1 GPIO161 R/W 0h Data Register for this pin
Reset type: SYSRSn
0 GPIO160 R/W 0h Data Register for this pin
Reset type: SYSRSn

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8.10.3.22 GPFSET Register (Offset = 2Ah) [Reset = 00000000h]

GPFSET is shown in Figure 8-123 and described in Table 8-135.
Return to the Summary Table.
GPIO F Data Set Register (GPIO160 to 168)
Writing a 1 will force GPIO output data latch to 1.
Writes of 0 are ignored.
Always reads back a 0.
Figure 8-123. GPFSET Register
31 30 29 28 27 26 25 24
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED GPIO168
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO167 GPIO166 GPIO165 GPIO164 GPIO163 GPIO162 GPIO161 GPIO160
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-135. GPFSET Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R/W 0h Reserved
30 RESERVED R/W 0h Reserved
29 RESERVED R/W 0h Reserved
28 RESERVED R/W 0h Reserved
27 RESERVED R/W 0h Reserved
26 RESERVED R/W 0h Reserved
25 RESERVED R/W 0h Reserved
24 RESERVED R/W 0h Reserved
23 RESERVED R/W 0h Reserved
22 RESERVED R/W 0h Reserved
21 RESERVED R/W 0h Reserved
20 RESERVED R/W 0h Reserved
19 RESERVED R/W 0h Reserved
18 RESERVED R/W 0h Reserved
17 RESERVED R/W 0h Reserved
16 RESERVED R/W 0h Reserved
15 RESERVED R/W 0h Reserved
14 RESERVED R/W 0h Reserved
13 RESERVED R/W 0h Reserved
12 RESERVED R/W 0h Reserved
11 RESERVED R/W 0h Reserved
10 RESERVED R/W 0h Reserved
9 RESERVED R/W 0h Reserved

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Table 8-135. GPFSET Register Field Descriptions (continued)

Bit Field Type Reset Description
8 GPIO168 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
7 GPIO167 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
6 GPIO166 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
5 GPIO165 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
4 GPIO164 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
3 GPIO163 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
2 GPIO162 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
1 GPIO161 R/W 0h Output Set bit for this pin
Reset type: SYSRSn
0 GPIO160 R/W 0h Output Set bit for this pin
Reset type: SYSRSn

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8.10.3.23 GPFCLEAR Register (Offset = 2Ch) [Reset = 00000000h]

GPFCLEAR is shown in Figure 8-124 and described in Table 8-136.
Return to the Summary Table.
GPIO F Data Clear Register (GPIO160 to 168)
Writing a 1 will force GPIO0 output data latch to 0.
Writes of 0 are ignored.
Always reads back a 0.
Figure 8-124. GPFCLEAR Register
31 30 29 28 27 26 25 24
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED GPIO168
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO167 GPIO166 GPIO165 GPIO164 GPIO163 GPIO162 GPIO161 GPIO160
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-136. GPFCLEAR Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R/W 0h Reserved
30 RESERVED R/W 0h Reserved
29 RESERVED R/W 0h Reserved
28 RESERVED R/W 0h Reserved
27 RESERVED R/W 0h Reserved
26 RESERVED R/W 0h Reserved
25 RESERVED R/W 0h Reserved
24 RESERVED R/W 0h Reserved
23 RESERVED R/W 0h Reserved
22 RESERVED R/W 0h Reserved
21 RESERVED R/W 0h Reserved
20 RESERVED R/W 0h Reserved
19 RESERVED R/W 0h Reserved
18 RESERVED R/W 0h Reserved
17 RESERVED R/W 0h Reserved
16 RESERVED R/W 0h Reserved
15 RESERVED R/W 0h Reserved
14 RESERVED R/W 0h Reserved
13 RESERVED R/W 0h Reserved
12 RESERVED R/W 0h Reserved
11 RESERVED R/W 0h Reserved
10 RESERVED R/W 0h Reserved
9 RESERVED R/W 0h Reserved

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Table 8-136. GPFCLEAR Register Field Descriptions (continued)

Bit Field Type Reset Description
8 GPIO168 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
7 GPIO167 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
6 GPIO166 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
5 GPIO165 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
4 GPIO164 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
3 GPIO163 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
2 GPIO162 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
1 GPIO161 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn
0 GPIO160 R/W 0h Output Clear bit for this pin
Reset type: SYSRSn

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8.10.3.24 GPFTOGGLE Register (Offset = 2Eh) [Reset = 00000000h]

GPFTOGGLE is shown in Figure 8-125 and described in Table 8-137.
Return to the Summary Table.
GPIO F Data Toggle Register (GPIO160 to 168)
Writing a 1 will toggle GPIO0 output data latch 1 to 0 or 0 to 1.
Writes of 0 are ignored.
Always reads back a 0.
Figure 8-125. GPFTOGGLE Register
31 30 29 28 27 26 25 24
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED GPIO168
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO167 GPIO166 GPIO165 GPIO164 GPIO163 GPIO162 GPIO161 GPIO160
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-137. GPFTOGGLE Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R/W 0h Reserved
30 RESERVED R/W 0h Reserved
29 RESERVED R/W 0h Reserved
28 RESERVED R/W 0h Reserved
27 RESERVED R/W 0h Reserved
26 RESERVED R/W 0h Reserved
25 RESERVED R/W 0h Reserved
24 RESERVED R/W 0h Reserved
23 RESERVED R/W 0h Reserved
22 RESERVED R/W 0h Reserved
21 RESERVED R/W 0h Reserved
20 RESERVED R/W 0h Reserved
19 RESERVED R/W 0h Reserved
18 RESERVED R/W 0h Reserved
17 RESERVED R/W 0h Reserved
16 RESERVED R/W 0h Reserved
15 RESERVED R/W 0h Reserved
14 RESERVED R/W 0h Reserved
13 RESERVED R/W 0h Reserved
12 RESERVED R/W 0h Reserved
11 RESERVED R/W 0h Reserved
10 RESERVED R/W 0h Reserved
9 RESERVED R/W 0h Reserved

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Table 8-137. GPFTOGGLE Register Field Descriptions (continued)

Bit Field Type Reset Description
8 GPIO168 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
7 GPIO167 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
6 GPIO166 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
5 GPIO165 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
4 GPIO164 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
3 GPIO163 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
2 GPIO162 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
1 GPIO161 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
0 GPIO160 R/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn

8.10.4 GPIO Registers to Driverlib Functions

Table 8-138. GPIO Registers to Driverlib Functions
File Driverlib Function
GPACTRL
gpio.c GPIO_setQualificationPeriod
GPAQSEL1
gpio.c GPIO_setQualificationMode
gpio.c GPIO_getQualificationMode
GPAQSEL2
- See GPAQSEL1
GPAMUX1
gpio.c GPIO_setPinConfig
GPAMUX2
- See GPAMUX1
GPADIR
gpio.c GPIO_setDirectionMode
gpio.c GPIO_getDirectionMode
GPAPUD
gpio.c GPIO_setPadConfig
gpio.c GPIO_getPadConfig
GPAINV
gpio.c GPIO_setPadConfig
gpio.c GPIO_getPadConfig
GPAODR
gpio.c GPIO_setPadConfig
gpio.c GPIO_getPadConfig
GPAGMUX1

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Table 8-138. GPIO Registers to Driverlib Functions (continued)

File Driverlib Function
gpio.c GPIO_setPinConfig
GPAGMUX2
- See GPAGMUX1
GPACSEL1
gpio.c GPIO_setControllerCore
GPACSEL2
- See GPACSEL1
GPACSEL3
- See GPACSEL1
GPACSEL4
- See GPACSEL1
GPALOCK
gpio.h GPIO_lockPortConfig
gpio.h GPIO_unlockPortConfig
GPACR
gpio.h GPIO_commitPortConfig
GPBCTRL
- See GPACTRL
GPBQSEL1
- See GPAQSEL1
GPBQSEL2
- See GPAQSEL1
GPBMUX1
- See GPAMUX1
GPBMUX2
- See GPAMUX1
GPBDIR
- See GPADIR
GPBPUD
- See GPAPUD
GPBINV
- See GPAINV
GPBODR
- See GPAODR
GPBAMSEL
gpio.c GPIO_setAnalogMode
GPBGMUX1
- See GPAGMUX1
GPBGMUX2
- See GPAGMUX1
GPBCSEL1
- See GPACSEL1
GPBCSEL2
- See GPACSEL1
GPBCSEL3

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Table 8-138. GPIO Registers to Driverlib Functions (continued)

File Driverlib Function
- See GPACSEL1
GPBCSEL4
- See GPACSEL1
GPBLOCK
- See GPALOCK
GPBCR
- See GPACR
GPCCTRL
- See GPACTRL
GPCQSEL1
- See GPAQSEL1
GPCQSEL2
- See GPAQSEL1
GPCMUX1
- See GPAMUX1
GPCMUX2
- See GPAMUX1
GPCDIR
- See GPADIR
GPCPUD
- See GPAPUD
GPCINV
- See GPAINV
GPCODR
- See GPAODR
GPCGMUX1
- See GPAGMUX1
GPCGMUX2
- See GPAGMUX1
GPCCSEL1
- See GPACSEL1
GPCCSEL2
- See GPACSEL1
GPCCSEL3
- See GPACSEL1
GPCCSEL4
- See GPACSEL1
GPCLOCK
- See GPALOCK
GPCCR
- See GPACR
GPDCTRL
- See GPACTRL
GPDQSEL1
- See GPAQSEL1

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Table 8-138. GPIO Registers to Driverlib Functions (continued)

File Driverlib Function
GPDQSEL2
- See GPAQSEL1
GPDMUX1
- See GPAMUX1
GPDMUX2
- See GPAMUX1
GPDDIR
- See GPADIR
GPDPUD
- See GPAPUD
GPDINV
- See GPAINV
GPDODR
- See GPAODR
GPDGMUX1
- See GPAGMUX1
GPDGMUX2
- See GPAGMUX1
GPDCSEL1
- See GPACSEL1
GPDCSEL2
- See GPACSEL1
GPDCSEL3
- See GPACSEL1
GPDCSEL4
- See GPACSEL1
GPDLOCK
- See GPALOCK
GPDCR
- See GPACR
GPECTRL
- See GPACTRL
GPEQSEL1
- See GPAQSEL1
GPEQSEL2
- See GPAQSEL1
GPEMUX1
- See GPAMUX1
GPEMUX2
- See GPAMUX1
GPEDIR
- See GPADIR
GPEPUD
- See GPAPUD
GPEINV

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Table 8-138. GPIO Registers to Driverlib Functions (continued)

File Driverlib Function
- See GPAINV
GPEODR
- See GPAODR
GPEGMUX1
- See GPAGMUX1
GPEGMUX2
- See GPAGMUX1
GPECSEL1
- See GPACSEL1
GPECSEL2
- See GPACSEL1
GPECSEL3
- See GPACSEL1
GPECSEL4
- See GPACSEL1
GPELOCK
- See GPALOCK
GPECR
- See GPACR
GPFCTRL
- See GPACTRL
GPFQSEL1
- See GPAQSEL1
GPFMUX1
- See GPAMUX1
GPFDIR
- See GPADIR
GPFPUD
- See GPAPUD
GPFINV
- See GPAINV
GPFODR
- See GPAODR
GPFGMUX1
- See GPAGMUX1
GPFCSEL1
- See GPACSEL1
GPFCSEL2
- See GPACSEL1
GPFLOCK
- See GPALOCK
GPFCR
- See GPACR
GPADAT
gpio.h GPIO_readPin

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Table 8-138. GPIO Registers to Driverlib Functions (continued)

File Driverlib Function
gpio.h GPIO_readPortData
gpio.h GPIO_writePortData
GPASET
gpio.h GPIO_writePin
gpio.h GPIO_setPortPins
GPACLEAR
gpio.h GPIO_writePin
gpio.h GPIO_clearPortPins
GPATOGGLE
gpio.h GPIO_togglePin
gpio.h GPIO_togglePortPins
GPBDAT
- See GPADAT
GPBSET
- See GPASET
GPBCLEAR
- See GPACLEAR
GPBTOGGLE
- See GPATOGGLE
GPCDAT
- See GPADAT
GPCSET
- See GPASET
GPCCLEAR
- See GPACLEAR
GPCTOGGLE
- See GPATOGGLE
GPDDAT
- See GPADAT
GPDSET
- See GPASET
GPDCLEAR
- See GPACLEAR
GPDTOGGLE
- See GPATOGGLE
GPEDAT
- See GPADAT
GPESET
- See GPASET
GPECLEAR
- See GPACLEAR
GPETOGGLE
- See GPATOGGLE
GPFDAT
- See GPADAT

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Table 8-138. GPIO Registers to Driverlib Functions (continued)

File Driverlib Function
GPFSET
- See GPASET
GPFCLEAR
- See GPACLEAR
GPFTOGGLE
- See GPATOGGLE

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www.ti.com Crossbar (X-BAR)

Chapter 9
Crossbar (X-BAR)

The crossbars (referred to as X-BAR throughout this chapter) provide flexibility to connect device inputs, outputs,
and internal resources in a variety of configurations.
The device contains a total of four X-BARs:
• Input X-BAR
• Output X-BAR
• CLB X-BAR
• ePWM X-BAR
Each of the X-BARs is named according to where the X-BAR takes signals. For example, the Input X-BAR
brings external signals “in” to the device. The Output X-BAR takes internal signals “out” of the device to a GPIO.
The CLB X-BAR and ePWM X-BAR take signals to the CLB and ePWM modules, respectively.

9.1 Input X-BAR ............................................................................................................................................................1230

9.2 ePWM, CLB, and GPIO Output X-BAR..................................................................................................................1233
9.3 XBAR Registers...................................................................................................................................................... 1241

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9.1 Input X-BAR

On this device, the Input X-BAR is used to route signals from a GPIO to many different IP blocks such as the ADC, eCAP, ePWM, and external interrupts.
The input of each Input X-BAR instance (INPUTx) can be any GPIO, while the output of each instance connects to various IP blocks in the device. The
digital input of AIOs are also available as inputs to the Input X-BAR. This flexibility relieves some of the constraints on peripheral muxing by allowing the
user to connect any GPIO to the specified outputs of each Input X-BAR instance. Note that the GPIO selected by the Input X-BAR can be configured
as either an input or an output. The Input X-BAR simply connects the signal on the input buffer to the output of the selected Input X-BAR instance.
Therefore, you can do things such as route the output of an ePWM to the eCAP module for a frequency test).
The Input X-BAR is configured by way of the INPUTxSELECT registers. The destinations for each INPUTx are shown in Figure 9-1 and Table 9-1.
For additional details on how each Input X-BAR connects to other IP blocks throughout the device, look for references to Input X-BAR in the chapter
associated with that IP. Note that the destinations of each INPUTx are fixed and are not user-configurable. For more information on configuring the Input
X-BAR, see the INPUT_XBAR_REGS register definitions in the XBAR Registers section.

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INPUT7 eCAP1
GPIO0 INPUT8 eCAP2
Asynchronous INPUT9 eCAP3
Synchronous Input X-BAR
INPUT10 eCAP4
GPIOx Sync. + Qual.
INPUT11 eCAP5
INPUT12 eCAP6

INPUT14
INPUT13
INPUT6
INPUT5
INPUT4
INPUT3
INPUT2
INPUT1
TZ1,TRIP1
XINT5 TZ2,TRIP2
XINT4 TZ3,TRIP3
CPU PIE
XINT3
CLA XINT2 TRIP4
XINT1 TRIP5
TRIP7 ePWM
ePWM TRIP8 Modules
X-BAR TRIP9
TRIP10
TRIP11
TRIP12

TRIP6
ADC ADCEXTSOC
EXTSYNCIN1 ePWM and eCAP
EXTSYNCIN2 Sync Chain

INPUTXBAR [1-6] CLB X-BAR

Output X-BAR

Figure 9-1. Input X-BAR

Note
INPUTXBARx, INPUTXBAR_INPUTx, and INPUTx (when referenced in the context of Input X-BAR) are equivalent in all C2000 software and
documentation.

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Table 9-1. Input X-BAR Destinations

ADC START OF EPWM / ECAP
INPUT ECAP / HRCAP EPWM X-BAR CLB X-BAR OUTPUT X-BAR CPU XINT EPWM TRIP
CONVERSION SYNC
1 - Yes Yes Yes - TZ1,TRIP1 - -
2 - Yes Yes Yes - TZ2,TRIP2 - -
3 - Yes Yes Yes - TZ3,TRIP3 - -
4 - Yes Yes Yes XINT1 - - -
5 - Yes Yes Yes XINT2 - ADCEXTSOC EXTSYNCIN1
6 - Yes Yes Yes XINT3 TRIP6 - EXTSYNCIN2
7 ECAP1 - - - - - - -
8 ECAP2 - - - - - - -
9 ECAP3 - - - - - - -
10 ECAP4 - - - - - - -
11 ECAP5 - - - - - - -
12 ECAP6 - - - - - - -
13 - - - - XINT4 - - -
14 - - - - XINT5 - - -

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9.2 ePWM, CLB, and GPIO Output X-BAR

This section describes the ePWM, CLB, and GPIO Output X-BAR. .
9.2.1 ePWM X-BAR
The ePWM X-BAR brings signals to the ePWM modules. Specifically, the ePWM X-BAR is connected to the
Digital Compare (DC) submodule of each ePWM module for actions such as tripzones and syncing. Refer to the
Enhanced Pulse Width Modulator (ePWM) chapter for more information on additional ways the DC submodule
can be used. Figure 9-2 shows the architecture of the ePWM X-BAR. Note that the architecture of the ePWM
X-BAR is identical to the architecture of the GPIO Output X-BAR (with the exception of the output latch).
9.2.1.1 ePWM X-BAR Architecture
The ePWM X-BAR has eight outputs that are routed to each ePWM module. Figure 9-2 represents the
architecture of a single output, but this output is identical to the architecture of all of the other outputs.
First, determine the signals that can be passed to the ePWM by referencing Table 9-2. Select up to one
signal per mux for each TRIPx output. Select the inputs to ePWM X-BAR using the TRIPxMUX0TO15CFG
and TRIPxMUX16TO31CFG registers. To pass any signal through to the ePWM, enable the signal using the
TRIPxMUXENABLE register. All signals that are enabled are logically ORed before being passed on to the
respective TRIPx signal on the ePWM. To optionally invert the signal, use the TRIPOUTINV register.

0.0
0.1 0
0.2
0.3
TRIPxMUXENABLE
(32 bits)
TRIPxMUX0TO15CFG.MUX0

1.0
1.1 1
1.2
1.3

TRIPxMUX0TO15CFG.MUX1

31.0
31.1 TRIPOUTINV
31 (1 bit)
31.2
31.3

TRIPxMUX16TO31CFG.MUX31

Figure 9-2. ePWM X-BAR Architecture - Single Output

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Note
Do not use "Reserved" signals in your application.

Table 9-2. EPWM X-BAR Mux Configuration Table

Mux 0 1 2 3

G0 CMPSS1_CTRIPH CMPSS1_CTRIPH_OR_CTRIPL ADCAEVT1 ECAP1_OUT

G1 CMPSS1_CTRIPL INPUTXBAR1 CLB1_OUT12 ADCCEVT1

G2 CMPSS2_CTRIPH CMPSS2_CTRIPH_OR_CTRIPL ADCAEVT2 ECAP2_OUT

G3 CMPSS2_CTRIPL INPUTXBAR2 CLB1_OUT13 ADCCEVT2

G4 CMPSS3_CTRIPH CMPSS3_CTRIPH_OR_CTRIPL ADCAEVT3 ECAP3_OUT

G5 CMPSS3_CTRIPL INPUTXBAR3 CLB2_OUT12 ADCCEVT3

G6 CMPSS4_CTRIPH CMPSS4_CTRIPH_OR_CTRIPL ADCAEVT4 ECAP4_OUT

G7 CMPSS4_CTRIPL INPUTXBAR4 CLB2_OUT13 ADCCEVT4

G8 CMPSS5_CTRIPH CMPSS5_CTRIPH_OR_CTRIPL ADCBEVT1 ECAP5_OUT

G9 CMPSS5_CTRIPL INPUTXBAR5 CLB3_OUT12 ADCDEVT1

G10 CMPSS6_CTRIPH CMPSS6_CTRIPH_OR_CTRIPL ADCBEVT2 ECAP6_OUT

G11 CMPSS6_CTRIPL INPUTXBAR6 CLB3_OUT13 ADCDEVT2

G12 CMPSS7_CTRIPH CMPSS7_CTRIPH_OR_CTRIPL ADCBEVT3 Reserved

G13 CMPSS7_CTRIPL ADCSOCAO CLB4_OUT12 ADCDEVT3

G14 CMPSS8_CTRIPH CMPSS8_CTRIPH_OR_CTRIPL ADCBEVT4 EXTSYNCOUT

G15 CMPSS8_CTRIPL ADCSOCBO CLB4_OUT13 ADCDEVT4

G16 SD1FLT1_COMPH SD1FLT1_COMPH_OR_COMPL Reserved Reserved

G17 SD1FLT1_COMPL Reserved Reserved Reserved

G18 SD1FLT2_COMPH SD1FLT2_COMPH_OR_COMPL Reserved Reserved

G19 SD1FLT2_COMPL Reserved Reserved Reserved

G20 SD1FLT3_COMPH SD1FLT3_COMPH_OR_COMPL Reserved Reserved

G21 SD1FLT3_COMPL Reserved Reserved Reserved

G22 SD1FLT4_COMPH SD1FLT4_COMPH_OR_COMPL Reserved Reserved

G23 SD1FLT4_COMPL Reserved Reserved Reserved

G24 SD2FLT1_COMPH SD2FLT1_COMPH_OR_COMPL Reserved Reserved

G25 SD2FLT1_COMPL Reserved Reserved Reserved

G26 SD2FLT2_COMPH SD2FLT2_COMPH_OR_COMPL Reserved Reserved

G27 SD2FLT2_COMPL Reserved Reserved Reserved

G28 SD2FLT3_COMPH SD2FLT3_COMPH_OR_COMPL Reserved Reserved

G29 SD2FLT3_COMPL Reserved Reserved Reserved

G30 SD2FLT4_COMPH SD2FLT4_COMPH_OR_COMPL Reserved Reserved

G31 SD2FLT4_COMPL Reserved Reserved Reserved

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9.2.2 CLB X-BAR

The CLB X-BAR brings signals to the CLB modules. Figure 9-3 shows the architecture of the CLB X-BAR. Note
that the architecture of the CLB X-BAR is identical to the architecture of the GPIO Output X-BAR (with the
exception of the output latch).
9.2.2.1 CLB X-BAR Architecture
The CLB X-BAR has eight outputs that are routed to each CLB module. Figure 9-3 represents the architecture of
a single output, but the output is identical to the architecture of all of the other outputs.
First, determine the signals that can be passed to the CLB by referencing Table 9-3. Select up to one
signal per mux (31 total muxes) for each AUXSIGx output. Select the inputs to each mux using the
AUXSIGxMUX0TO15CFG and AUXSIGxMUX16TO31CFG registers. To pass any signal through to the CLB,
enable the mux in the AUXSIGxMUXENABLE register. All muxes that are enabled are logically ORed before
being passed on to the respective AUXSIGx signal on the CLB. To optionally invert the signal, use the
AUXSIGOUTINV register.

0.0
0.1 0
0.2
0.3 AUXSIGxMUXENABLE
(32 bits)

AUXSIGxMUX0TO15CFG.MUX0

1.0
1.1 1
1.2
1.3

AUXSIGx
AUXSIGxMUX0TO15CFG.MUX1

31.0
31.1 AUXSIGOUTINV
31 (1 bits)
31.2
31.3

AUXSIGxMUX16TO31CFG.MUX31

Figure 9-3. CLB X-BAR Architecture - Single Output

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GPIO0 Asynchronous
to Synchronous Input X-BAR
GPIOx Sync. + Qual

INPUT1
O t he r to
Pe r i ph e ral s INPUT6

CLBx T ILE
CLB X-BAR OU T 4 / 5

AU XSI G 0 to AU XSIG7

T R M Tabl e :
G l o bal Si gn a l s an d CLB TILE1
M ux S e l e c
o n
CLB Global GPREG CELL
Signals IN0-7

Local OUT 0-7

Signals
. CLB T i l e O ut p u t s
.
. Inte rs e c t ot h er
Pe r i p h e ral s
CLB TILEx O U T P U T X-BA R
E P W M X- BAR
GPREG CELL
IN0-7

Local OUT 0-7

Signals
CLB
Figure 9-4. GPIO to CLB Tile Connections

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Table 9-3. CLB X-BAR Mux Configuration Table

Mux 0 1 2 3

G0 CMPSS1_CTRIPH CMPSS1_CTRIPH_OR_CTRIPL ADCAEVT1 ECAP1_OUT

G1 CMPSS1_CTRIPL INPUTXBAR1 CLB1_OUT12 ADCCEVT1

G2 CMPSS2_CTRIPH CMPSS2_CTRIPH_OR_CTRIPL ADCAEVT2 ECAP2_OUT

G3 CMPSS2_CTRIPL INPUTXBAR2 CLB1_OUT13 ADCCEVT2

G4 CMPSS3_CTRIPH CMPSS3_CTRIPH_OR_CTRIPL ADCAEVT3 ECAP3_OUT

G5 CMPSS3_CTRIPL INPUTXBAR3 CLB2_OUT12 ADCCEVT3

G6 CMPSS4_CTRIPH CMPSS4_CTRIPH_OR_CTRIPL ADCAEVT4 ECAP4_OUT

G7 CMPSS4_CTRIPL INPUTXBAR4 CLB2_OUT13 ADCCEVT4

G8 CMPSS5_CTRIPH CMPSS5_CTRIPH_OR_CTRIPL ADCBEVT1 ECAP5_OUT

G9 CMPSS5_CTRIPL INPUTXBAR5 CLB3_OUT12 ADCDEVT1

G10 CMPSS6_CTRIPH CMPSS6_CTRIPH_OR_CTRIPL ADCBEVT2 ECAP6_OUT

G11 CMPSS6_CTRIPL INPUTXBAR6 CLB3_OUT13 ADCDEVT2

G12 CMPSS7_CTRIPH CMPSS7_CTRIPH_OR_CTRIPL ADCBEVT3 Reserved

G13 CMPSS7_CTRIPL ADCSOCAO CLB4_OUT12 ADCDEVT3

G14 CMPSS8_CTRIPH CMPSS8_CTRIPH_OR_CTRIPL ADCBEVT4 EXTSYNCOUT

G15 CMPSS8_CTRIPL ADCSOCBO CLB4_OUT13 ADCDEVT4

G16 SD1FLT1_COMPH SD1FLT1_COMPH_OR_COMPL Reserved Reserved

G17 SD1FLT1_COMPL Reserved Reserved Reserved

G18 SD1FLT2_COMPH SD1FLT2_COMPH_OR_COMPL Reserved Reserved

G19 SD1FLT2_COMPL Reserved Reserved Reserved

G20 SD1FLT3_COMPH SD1FLT3_COMPH_OR_COMPL Reserved Reserved

G21 SD1FLT3_COMPL Reserved Reserved Reserved

G22 SD1FLT4_COMPH SD1FLT4_COMPH_OR_COMPL Reserved Reserved

G23 SD1FLT4_COMPL Reserved Reserved Reserved

G24 SD2FLT1_COMPH SD2FLT1_COMPH_OR_COMPL Reserved Reserved

G25 SD2FLT1_COMPL Reserved Reserved Reserved

G26 SD2FLT2_COMPH SD2FLT2_COMPH_OR_COMPL Reserved Reserved

G27 SD2FLT2_COMPL Reserved Reserved Reserved

G28 SD2FLT3_COMPH SD2FLT3_COMPH_OR_COMPL Reserved Reserved

G29 SD2FLT3_COMPL Reserved Reserved Reserved

G30 SD2FLT4_COMPH SD2FLT4_COMPH_OR_COMPL Reserved Reserved

G31 SD2FLT4_COMPL Reserved Reserved Reserved

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9.2.3 GPIO Output X-BAR

The GPIO Output X-BAR takes signals from inside the device and brings them out to a GPIO. Figure 9-5 shows
the architecture of the GPIO Output X-BAR. The X-BAR contains eight outputs and each contains at least one
position on the GPIO mux, denoted as OUTPUTXBARx. The X-BAR allows the selection of a single input or a
logical-OR of many inputs.
9.2.3.1 GPIO Output X-BAR Architecture
The GPIO Output X-BAR has eight outputs that are routed to the GPIO module. Figure 9-5 represents the
architecture of a single output, but this output is identical to the architecture of all of the other outputs. Note that
the architecture of the Output X-BAR (with the exception of the output latch) is similar to the architecture of the
ePWM X-BAR.
First, determine the signals that can be passed to the GPIO by referencing Table 9-4. Select up to one
signal per mux (32 total muxes) for each OUTPUTXBARx output. Select the inputs to each mux using the
OUTPUTxMUX0TO15CFG and OUTPUTxMUX16TO31CFG registers. To pass any signal through to the GPIO,
enable the mux in the OUTPUTxMUXENABLE register. All muxes that are enabled are logically ORed before
being passed on to the respective OUTPUTx signal on the GPIO module. To optionally invert the signal, use the
OUTPUTINV register. The final output is only recognized on the GPIO if the proper OUTPUTx muxing options
are selected using the GPIO registers.

0.0
0.1 0
0.2
0.3
OUTPUTxMUXENABLE
(32 bits)
OUTPUTxMUX0TO15CFG.MUX0

1.0
1.1 1
1.2
1.3

OUTPUTx
OUTPUTxMUX0TO15CFG.MUX1

OUTPUTLATCHENABLE
31.0
D Q
31.1 31
31.2 OLAT OUTPUTINV
31.3
Q

OUTPUTxMUX16TO31CFG.MUX31 OUTPUTLATCHFRC OUTPUTLATCHCLR

Figure 9-5. GPIO Output X-BAR Architecture

Note
Do not use "Reserved" signals in your application.
The ADCSOCAO and ADCSOCBO signals are active-high when routed through the X-BAR. The
signal can be inverted by the respective OUTPUTINV bit depending on the application.

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Table 9-4. Output X-BAR Mux Configuration Table

Mux 0 1 2 3

CMPSS1_CTRIPOUTOUTH_OR_CTRIPOU
G0 CMPSS1_CTRIPOUTH ADCAEVT1 ECAP1_OUT
TOUTL

G1 CMPSS1_CTRIPOUTL INPUTXBAR1 CLB1_OUT12 ADCCEVT1

CMPSS2_CTRIPOUTOUTH_OR_CTRIPOU
G2 CMPSS2_CTRIPOUTH ADCAEVT2 ECAP2_OUT
TOUTL

G3 CMPSS2_CTRIPOUTL INPUTXBAR2 CLB1_OUT13 ADCCEVT2

CMPSS3_CTRIPOUTOUTH_OR_CTRIPOU
G4 CMPSS3_CTRIPOUTH ADCAEVT3 ECAP3_OUT
TOUTL

G5 CMPSS3_CTRIPOUTL INPUTXBAR3 CLB2_OUT12 ADCCEVT3

CMPSS4_CTRIPOUTOUTH_OR_CTRIPOU
G6 CMPSS4_CTRIPOUTH ADCAEVT4 ECAP4_OUT
TOUTL

G7 CMPSS4_CTRIPOUTL INPUTXBAR4 CLB2_OUT13 ADCCEVT4

CMPSS5_CTRIPOUTOUTH_OR_CTRIPOU
G8 CMPSS5_CTRIPOUTH ADCBEVT1 ECAP5_OUT
TOUTL

G9 CMPSS5_CTRIPOUTL INPUTXBAR5 CLB3_OUT12 ADCDEVT1

CMPSS6_CTRIPOUTOUTH_OR_CTRIPOU
G10 CMPSS6_CTRIPOUTH ADCBEVT2 ECAP6_OUT
TOUTL

G11 CMPSS6_CTRIPOUTL INPUTXBAR6 CLB3_OUT13 ADCDEVT2

CMPSS7_CTRIPOUTOUTH_OR_CTRIPOU
G12 CMPSS7_CTRIPOUTH ADCBEVT3 Reserved
TOUTL

G13 CMPSS7_CTRIPOUTL ADCSOCAO CLB4_OUT12 ADCDEVT3

CMPSS8_CTRIPOUTOUTH_OR_CTRIPOU
G14 CMPSS8_CTRIPOUTH ADCBEVT4 EXTSYNCOUT
TOUTL

G15 CMPSS8_CTRIPOUTL ADCSOCBO CLB4_OUT13 ADCDEVT4

G16 SD1FLT1_COMPH SD1FLT1_COMPH_OR_COMPL Reserved Reserved

G17 SD1FLT1_COMPL Reserved Reserved Reserved

G18 SD1FLT2_COMPH SD1FLT2_COMPH_OR_COMPL Reserved Reserved

G19 SD1FLT2_COMPL Reserved Reserved Reserved

G20 SD1FLT3_COMPH SD1FLT3_COMPH_OR_COMPL Reserved Reserved

G21 SD1FLT3_COMPL Reserved Reserved Reserved

G22 SD1FLT4_COMPH SD1FLT4_COMPH_OR_COMPL Reserved Reserved

G23 SD1FLT4_COMPL Reserved Reserved Reserved

G24 SD2FLT1_COMPH SD2FLT1_COMPH_OR_COMPL Reserved Reserved

G25 SD2FLT1_COMPL Reserved Reserved Reserved

G26 SD2FLT2_COMPH SD2FLT2_COMPH_OR_COMPL Reserved Reserved

G27 SD2FLT2_COMPL Reserved Reserved Reserved

G28 SD2FLT3_COMPH SD2FLT3_COMPH_OR_COMPL Reserved Reserved

G29 SD2FLT3_COMPL Reserved Reserved Reserved

G30 SD2FLT4_COMPH SD2FLT4_COMPH_OR_COMPL Reserved Reserved

G31 SD2FLT4_COMPL Reserved Reserved Reserved

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9.2.4 X-BAR Flags

With the exception of the CMPSS signals, the ePWM X-BAR and the Output X-BAR have all of the same input
signals. Due to the inputs being similar between the ePWM X-BAR, CLB X-BAR, and Output X-BAR, all X-BAR
modules leverage a single set of input flags to indicate which input signals have been triggered. This allows
software to check the input flags when an event occurs. See Figure 9-6 for more information. There is a bit
allocated for each input signal in one of the XBARFLGx registers. The flag remains set until cleared through the
appropriate XBARCLRx register.

Note
Not all input sources are routed to all X-BAR modules. Refer to the X-BAR specific configuration
tables for exact connections.

CTRIPOUTH
CTRIPOUTL AUXSIG1
AUXSIG2
CMPSSx AUXSIG3
CTRIPH CLB AUXSIG4
CLB
CTRIPL X-BAR AUXSIG5 Global
AUXSIG6 Mux
AUXSIG7
AUXSIG8

Input X-BAR INPUT1-6

TRIP4
ePWM and eCAP TRIP5
EXTSYNCOUT
Sync Chain TRIP7
ePWM TRIP8
ADCSOCA0 X-BAR TRIP9
ADCSOCAO TRIP10 All
Select Circuit
TRIP11 ePWM
TRIP12 Modules
ADCSOCB0
ADCSOCBO
Select Circuit

eCAPx ECAPxOUT OUTPUTXBAR1

OUTPUTXBAR2
EVT1 OUTPUTXBAR3 GPIO
ADCx EVT2 Output OUTPUTXBAR4
EVT3 Mux
X-BAR OUTPUTXBAR5
EVT4 OUTPUTXBAR6
OUTPUTXBAR7
FLT1.COMPH OUTPUTXBAR8
FLT1.COMPL

SDFMx X-BAR Flags

FLT4.COMPH
(shared)
FLT4.COMPL

Figure 9-6. X-BAR Input Sources

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9.3 XBAR Registers

This section describes the Crossbar registers.
9.3.1 XBAR Base Addresses
Table 9-5. XBAR Base Address Table
Device Registers Register Name Start Address End Address
InputXbarRegs(1) INPUT_XBAR_REGS 0x0000_7900 0x0000_791F
XbarRegs(1) XBAR_REGS 0x0000 7920 0x0000_793F
EPwmXbarRegs(1) ePWM_XBAR_REGS 0x0000_7A00 0x0000_7A3F
ClbXbarRegs(1) CLB_XBAR_REGS 0x0000_7A40 0x0000_7A7F
OutputXbarRegs(1) OUTPUT_XBAR_REGS 0x0000_7A80 0x0000_7ABF

(1) Only available on CPU1.

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9.3.2 INPUT_XBAR_REGS Registers

Table 9-6 lists the memory-mapped registers for the INPUT_XBAR_REGS registers. All register offset addresses
not listed in Table 9-6 should be considered as reserved locations and the register contents should not be
modified.
Table 9-6. INPUT_XBAR_REGS Registers
Offset Acronym Register Name Write Protection Section
0h INPUT1SELECT INPUT1 Input Select Register (GPIO0 to x) EALLOW Go
1h INPUT2SELECT INPUT2 Input Select Register (GPIO0 to x) EALLOW Go
2h INPUT3SELECT INPUT3 Input Select Register (GPIO0 to x) EALLOW Go
3h INPUT4SELECT INPUT4 Input Select Register (GPIO0 to x) EALLOW Go
4h INPUT5SELECT INPUT5 Input Select Register (GPIO0 to x) EALLOW Go
5h INPUT6SELECT INPUT6 Input Select Register (GPIO0 to x) EALLOW Go
6h INPUT7SELECT INPUT7 Input Select Register (GPIO0 to x) EALLOW Go
7h INPUT8SELECT INPUT8 Input Select Register (GPIO0 to x) EALLOW Go
8h INPUT9SELECT INPUT9 Input Select Register (GPIO0 to x) EALLOW Go
9h INPUT10SELECT INPUT10 Input Select Register (GPIO0 to x) EALLOW Go
Ah INPUT11SELECT INPUT11 Input Select Register (GPIO0 to x) EALLOW Go
Bh INPUT12SELECT INPUT12 Input Select Register (GPIO0 to x) EALLOW Go
Ch INPUT13SELECT INPUT13 Input Select Register (GPIO0 to x) EALLOW Go
Dh INPUT14SELECT INPUT14 Input Select Register (GPIO0 to x) EALLOW Go
1Eh INPUTSELECTLOCK Input Select Lock Register EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 9-7 shows the codes that are used for
access types in this section.
Table 9-7. INPUT_XBAR_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
WSonce W Write
Sonce Set once
Reset or Default Value
-n Value after reset or the default value
Register Array Variables
i,j,k,l,m,n When these variables are used in a register name,
an offset, or an address, they refer to the value of a
register array where the register is part of a group
of repeating registers. The register groups form a
hierarchical structure and the array is represented
with a formula.
y When this variable is used in a register name, an
offset, or an address it refers to the value of a
register array.

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9.3.2.1 INPUT1SELECT Register (Offset = 0h) [Reset = 0000h]

INPUT1SELECT is shown in Figure 9-7 and described in Table 9-8.
Return to the Summary Table.
INPUT1 Input Select Register (GPIO0 to x)
Figure 9-7. INPUT1SELECT Register
15 14 13 12 11 10 9 8
SELECT
R/W-0h

7 6 5 4 3 2 1 0
SELECT
R/W-0h

Table 9-8. INPUT1SELECT Register Field Descriptions

Bit Field Type Reset Description
15-0 SELECT R/W 0h Select GPIO for INPUT1 signal:
0x0 : Select GPIO0
0x1 : Select GPIO1
0x2 : Select GPIO2
...
0xn : Select GPIOn
Reset type: CPU1.SYSRSn

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9.3.2.2 INPUT2SELECT Register (Offset = 1h) [Reset = 0000h]

INPUT2SELECT is shown in Figure 9-8 and described in Table 9-9.
Return to the Summary Table.
INPUT2 Input Select Register (GPIO0 to x)
Figure 9-8. INPUT2SELECT Register
15 14 13 12 11 10 9 8
SELECT
R/W-0h

7 6 5 4 3 2 1 0
SELECT
R/W-0h

Table 9-9. INPUT2SELECT Register Field Descriptions

Bit Field Type Reset Description
15-0 SELECT R/W 0h Select GPIO for INPUT2 signal:
0x0 : Select GPIO0
0x1 : Select GPIO1
0x2 : Select GPIO2
...
0xn : Select GPIOn
Reset type: CPU1.SYSRSn

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9.3.2.3 INPUT3SELECT Register (Offset = 2h) [Reset = 0000h]

INPUT3SELECT is shown in Figure 9-9 and described in Table 9-10.
Return to the Summary Table.
INPUT3 Input Select Register (GPIO0 to x)
Figure 9-9. INPUT3SELECT Register
15 14 13 12 11 10 9 8
SELECT
R/W-0h

7 6 5 4 3 2 1 0
SELECT
R/W-0h

Table 9-10. INPUT3SELECT Register Field Descriptions

Bit Field Type Reset Description
15-0 SELECT R/W 0h Select GPIO for INPUT3 signal:
0x0 : Select GPIO0
0x1 : Select GPIO1
0x2 : Select GPIO2
...
0xn : Select GPIOn
Reset type: CPU1.SYSRSn

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9.3.2.4 INPUT4SELECT Register (Offset = 3h) [Reset = 0000h]

INPUT4SELECT is shown in Figure 9-10 and described in Table 9-11.
Return to the Summary Table.
INPUT4 Input Select Register (GPIO0 to x)
Figure 9-10. INPUT4SELECT Register
15 14 13 12 11 10 9 8
SELECT
R/W-0h

7 6 5 4 3 2 1 0
SELECT
R/W-0h

Table 9-11. INPUT4SELECT Register Field Descriptions

Bit Field Type Reset Description
15-0 SELECT R/W 0h Select GPIO for INPUT4 signal:
0x0 : Select GPIO0
0x1 : Select GPIO1
0x2 : Select GPIO2
...
0xn : Select GPIOn
Reset type: CPU1.SYSRSn

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9.3.2.5 INPUT5SELECT Register (Offset = 4h) [Reset = 0000h]

INPUT5SELECT is shown in Figure 9-11 and described in Table 9-12.
Return to the Summary Table.
INPUT5 Input Select Register (GPIO0 to x)
Figure 9-11. INPUT5SELECT Register
15 14 13 12 11 10 9 8
SELECT
R/W-0h

7 6 5 4 3 2 1 0
SELECT
R/W-0h

Table 9-12. INPUT5SELECT Register Field Descriptions

Bit Field Type Reset Description
15-0 SELECT R/W 0h Select GPIO for INPUT5 signal:
0x0 : Select GPIO0
0x1 : Select GPIO1
0x2 : Select GPIO2
...
0xn : Select GPIOn
Reset type: CPU1.SYSRSn

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9.3.2.6 INPUT6SELECT Register (Offset = 5h) [Reset = 0000h]

INPUT6SELECT is shown in Figure 9-12 and described in Table 9-13.
Return to the Summary Table.
INPUT6 Input Select Register (GPIO0 to x)
Figure 9-12. INPUT6SELECT Register
15 14 13 12 11 10 9 8
SELECT
R/W-0h

7 6 5 4 3 2 1 0
SELECT
R/W-0h

Table 9-13. INPUT6SELECT Register Field Descriptions

Bit Field Type Reset Description
15-0 SELECT R/W 0h Select GPIO for INPUT6 signal:
0x0 : Select GPIO0
0x1 : Select GPIO1
0x2 : Select GPIO2
...
0xn : Select GPIOn
Reset type: CPU1.SYSRSn

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9.3.2.7 INPUT7SELECT Register (Offset = 6h) [Reset = 0000h]

INPUT7SELECT is shown in Figure 9-13 and described in Table 9-14.
Return to the Summary Table.
INPUT7 Input Select Register (GPIO0 to x)
Figure 9-13. INPUT7SELECT Register
15 14 13 12 11 10 9 8
SELECT
R/W-0h

7 6 5 4 3 2 1 0
SELECT
R/W-0h

Table 9-14. INPUT7SELECT Register Field Descriptions

Bit Field Type Reset Description
15-0 SELECT R/W 0h Select GPIO for INPUT7 signal:
0x0 : Select GPIO0
0x1 : Select GPIO1
0x2 : Select GPIO2
...
0xn : Select GPIOn
Reset type: CPU1.SYSRSn

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9.3.2.8 INPUT8SELECT Register (Offset = 7h) [Reset = 0000h]

INPUT8SELECT is shown in Figure 9-14 and described in Table 9-15.
Return to the Summary Table.
INPUT8 Input Select Register (GPIO0 to x)
Figure 9-14. INPUT8SELECT Register
15 14 13 12 11 10 9 8
SELECT
R/W-0h

7 6 5 4 3 2 1 0
SELECT
R/W-0h

Table 9-15. INPUT8SELECT Register Field Descriptions

Bit Field Type Reset Description
15-0 SELECT R/W 0h Select GPIO for INPUT8 signal:
0x0 : Select GPIO0
0x1 : Select GPIO1
0x2 : Select GPIO2
...
0xn : Select GPIOn
Reset type: CPU1.SYSRSn

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9.3.2.9 INPUT9SELECT Register (Offset = 8h) [Reset = 0000h]

INPUT9SELECT is shown in Figure 9-15 and described in Table 9-16.
Return to the Summary Table.
INPUT9 Input Select Register (GPIO0 to x)
Figure 9-15. INPUT9SELECT Register
15 14 13 12 11 10 9 8
SELECT
R/W-0h

7 6 5 4 3 2 1 0
SELECT
R/W-0h

Table 9-16. INPUT9SELECT Register Field Descriptions

Bit Field Type Reset Description
15-0 SELECT R/W 0h Select GPIO for INPUT9 signal:
0x0 : Select GPIO0
0x1 : Select GPIO1
0x2 : Select GPIO2
...
0xn : Select GPIOn
Reset type: CPU1.SYSRSn

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9.3.2.10 INPUT10SELECT Register (Offset = 9h) [Reset = 0000h]

INPUT10SELECT is shown in Figure 9-16 and described in Table 9-17.
Return to the Summary Table.
INPUT10 Input Select Register (GPIO0 to x)
Figure 9-16. INPUT10SELECT Register
15 14 13 12 11 10 9 8
SELECT
R/W-0h

7 6 5 4 3 2 1 0
SELECT
R/W-0h

Table 9-17. INPUT10SELECT Register Field Descriptions

Bit Field Type Reset Description
15-0 SELECT R/W 0h Select GPIO for INPUT10 signal:
0x0 : Select GPIO0
0x1 : Select GPIO1
0x2 : Select GPIO2
...
0xn : Select GPIOn
Reset type: CPU1.SYSRSn

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9.3.2.11 INPUT11SELECT Register (Offset = Ah) [Reset = 0000h]

INPUT11SELECT is shown in Figure 9-17 and described in Table 9-18.
Return to the Summary Table.
INPUT11 Input Select Register (GPIO0 to x)
Figure 9-17. INPUT11SELECT Register
15 14 13 12 11 10 9 8
SELECT
R/W-0h

7 6 5 4 3 2 1 0
SELECT
R/W-0h

Table 9-18. INPUT11SELECT Register Field Descriptions

Bit Field Type Reset Description
15-0 SELECT R/W 0h Select GPIO for INPUT11 signal:
0x0 : Select GPIO0
0x1 : Select GPIO1
0x2 : Select GPIO2
...
0xn : Select GPIOn
Reset type: CPU1.SYSRSn

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9.3.2.12 INPUT12SELECT Register (Offset = Bh) [Reset = 0000h]

INPUT12SELECT is shown in Figure 9-18 and described in Table 9-19.
Return to the Summary Table.
INPUT12 Input Select Register (GPIO0 to x)
Figure 9-18. INPUT12SELECT Register
15 14 13 12 11 10 9 8
SELECT
R/W-0h

7 6 5 4 3 2 1 0
SELECT
R/W-0h

Table 9-19. INPUT12SELECT Register Field Descriptions

Bit Field Type Reset Description
15-0 SELECT R/W 0h Select GPIO for INPUT12 signal:
0x0 : Select GPIO0
0x1 : Select GPIO1
0x2 : Select GPIO2
...
0xn : Select GPIOn
Reset type: CPU1.SYSRSn

1254 TMS320F2837xD Dual-Core Real-Time Microcontrollers SPRUHM8K – DECEMBER 2013 – REVISED MAY 2024
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9.3.2.13 INPUT13SELECT Register (Offset = Ch) [Reset = 0000h]

INPUT13SELECT is shown in Figure 9-19 and described in Table 9-20.
Return to the Summary Table.
INPUT13 Input Select Register (GPIO0 to x)
Figure 9-19. INPUT13SELECT Register
15 14 13 12 11 10 9 8
SELECT
R/W-0h

7 6 5 4 3 2 1 0
SELECT
R/W-0h

Table 9-20. INPUT13SELECT Register Field Descriptions

Bit Field Type Reset Description
15-0 SELECT R/W 0h Select GPIO for INPUT13 signal:
0x0 : Select GPIO0
0x1 : Select GPIO1
0x2 : Select GPIO2
...
0xn : Select GPIOn
Reset type: CPU1.SYSRSn

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9.3.2.14 INPUT14SELECT Register (Offset = Dh) [Reset = 0000h]

INPUT14SELECT is shown in Figure 9-20 and described in Table 9-21.
Return to the Summary Table.
INPUT14 Input Select Register (GPIO0 to x)
Figure 9-20. INPUT14SELECT Register
15 14 13 12 11 10 9 8
SELECT
R/W-0h

7 6 5 4 3 2 1 0
SELECT
R/W-0h

Table 9-21. INPUT14SELECT Register Field Descriptions

Bit Field Type Reset Description
15-0 SELECT R/W 0h Select GPIO for INPUT14 signal:
0x0 : Select GPIO0
0x1 : Select GPIO1
0x2 : Select GPIO2
...
0xn : Select GPIOn
Reset type: CPU1.SYSRSn

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9.3.2.15 INPUTSELECTLOCK Register (Offset = 1Eh) [Reset = 00000000h]

INPUTSELECTLOCK is shown in Figure 9-21 and described in Table 9-22.
Return to the Summary Table.
Input Select Lock Register.
Any bit in this register, once set can only be cleared through SYSRSn. Write of 0 to any bit of this register has no
effect. Reads to the registers which have LOCK protection are always allowed.
Figure 9-21. INPUTSELECTLOCK Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
INPUT16SELE INPUT15SELE INPUT14SELE INPUT13SELE INPUT12SELE INPUT11SELE INPUT10SELE INPUT9SELEC
CT CT CT CT CT CT CT T
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

7 6 5 4 3 2 1 0
INPUT8SELEC INPUT7SELEC INPUT6SELEC INPUT5SELEC INPUT4SELEC INPUT3SELEC INPUT2SELEC INPUT1SELEC
T T T T T T T T
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

Table 9-22. INPUTSELECTLOCK Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15 INPUT16SELECT R/WSonce 0h Lock bit for INPUT16SELECT Register
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn
14 INPUT15SELECT R/WSonce 0h Lock bit for INPUT15SELECT Register
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn
13 INPUT14SELECT R/WSonce 0h Lock bit for INPUT14SELECT Register
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn
12 INPUT13SELECT R/WSonce 0h Lock bit for INPUT13SELECT Register
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn
11 INPUT12SELECT R/WSonce 0h Lock bit for INPUT12SELECT Register
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn
10 INPUT11SELECT R/WSonce 0h Lock bit for INPUT11SELECT Register
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn

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Table 9-22. INPUTSELECTLOCK Register Field Descriptions (continued)

Bit Field Type Reset Description
9 INPUT10SELECT R/WSonce 0h Lock bit for INPUT10SELECT Register
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn
8 INPUT9SELECT R/WSonce 0h Lock bit for INPUT9SELECT Register
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn
7 INPUT8SELECT R/WSonce 0h Lock bit for INPUT8SELECT Register
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn
6 INPUT7SELECT R/WSonce 0h Lock bit for INPUT7SELECT Register
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn
5 INPUT6SELECT R/WSonce 0h Lock bit for INPUT6SELECT Register
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn
4 INPUT5SELECT R/WSonce 0h Lock bit for INPUT5SELECT Register
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn
3 INPUT4SELECT R/WSonce 0h Lock bit for INPUT4SELECT Register
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn
2 INPUT3SELECT R/WSonce 0h Lock bit for INPUT3SELECT Register
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn
1 INPUT2SELECT R/WSonce 0h Lock bit for INPUT2SELECT Register
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn
0 INPUT1SELECT R/WSonce 0h Lock bit for INPUT1SELECT Register
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn

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9.3.3 XBAR_REGS Registers

Table 9-23 lists the memory-mapped registers for the XBAR_REGS registers. All register offset addresses not
listed in Table 9-23 should be considered as reserved locations and the register contents should not be modified.
Table 9-23. XBAR_REGS Registers
Offset Acronym Register Name Write Protection Section
0h XBARFLG1 X-Bar Input Flag Register 1 Go
2h XBARFLG2 X-Bar Input Flag Register 2 Go
4h XBARFLG3 X-Bar Input Flag Register 3 Go
8h XBARCLR1 X-Bar Input Flag Clear Register 1 Go
Ah XBARCLR2 X-Bar Input Flag Clear Register 2 Go
Ch XBARCLR3 X-Bar Input Flag Clear Register 3 Go

Complex bit access types are encoded to fit into small table cells. Table 9-24 shows the codes that are used for
access types in this section.
Table 9-24. XBAR_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W1S W Write
1S 1 to set
Reset or Default Value
-n Value after reset or the default value
Register Array Variables
i,j,k,l,m,n When these variables are used in a register name,
an offset, or an address, they refer to the value of a
register array where the register is part of a group
of repeating registers. The register groups form a
hierarchical structure and the array is represented
with a formula.
y When this variable is used in a register name, an
offset, or an address it refers to the value of a
register array.

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9.3.3.1 XBARFLG1 Register (Offset = 0h) [Reset = 00000000h]

XBARFLG1 is shown in Figure 9-22 and described in Table 9-25.
Return to the Summary Table.
This register is used to flag the inputs of the X-Bars to provide software knowledge of the input sources which
got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Figure 9-22. XBARFLG1 Register
31 30 29 28 27 26 25 24
CMPSS8_CTRI CMPSS8_CTRI CMPSS7_CTRI CMPSS7_CTRI CMPSS6_CTRI CMPSS6_CTRI CMPSS5_CTRI CMPSS5_CTRI
POUTH POUTL POUTH POUTL POUTH POUTL POUTH POUTL
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

23 22 21 20 19 18 17 16
CMPSS4_CTRI CMPSS4_CTRI CMPSS3_CTRI CMPSS3_CTRI CMPSS2_CTRI CMPSS2_CTRI CMPSS1_CTRI CMPSS1_CTRI
POUTH POUTL POUTH POUTL POUTH POUTL POUTH POUTL
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

15 14 13 12 11 10 9 8
CMPSS8_CTRI CMPSS8_CTRI CMPSS7_CTRI CMPSS7_CTRI CMPSS6_CTRI CMPSS6_CTRI CMPSS5_CTRI CMPSS5_CTRI
PH PL PH PL PH PL PH PL
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
CMPSS4_CTRI CMPSS4_CTRI CMPSS3_CTRI CMPSS3_CTRI CMPSS2_CTRI CMPSS2_CTRI CMPSS1_CTRI CMPSS1_CTRI
PH PL PH PL PH PL PH PL
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 9-25. XBARFLG1 Register Field Descriptions

Bit Field Type Reset Description
31 CMPSS8_CTRIPOUTH R 0h CMPSS8_CTRIPOUTH X-BAR Flag
Reset type: CPU1.SYSRSn
30 CMPSS8_CTRIPOUTL R 0h CMPSS8_CTRIPOUTL X-BAR Flag
Reset type: CPU1.SYSRSn
29 CMPSS7_CTRIPOUTH R 0h CMPSS7_CTRIPOUTH X-BAR Flag
Reset type: CPU1.SYSRSn
28 CMPSS7_CTRIPOUTL R 0h CMPSS7_CTRIPOUTL X-BAR Flag
Reset type: CPU1.SYSRSn
27 CMPSS6_CTRIPOUTH R 0h CMPSS6_CTRIPOUTH X-BAR Flag
Reset type: CPU1.SYSRSn
26 CMPSS6_CTRIPOUTL R 0h CMPSS6_CTRIPOUTL X-BAR Flag
Reset type: CPU1.SYSRSn
25 CMPSS5_CTRIPOUTH R 0h CMPSS5_CTRIPOUTH X-BAR Flag
Reset type: CPU1.SYSRSn
24 CMPSS5_CTRIPOUTL R 0h CMPSS5_CTRIPOUTL X-BAR Flag
Reset type: CPU1.SYSRSn
23 CMPSS4_CTRIPOUTH R 0h CMPSS4_CTRIPOUTH X-BAR Flag
Reset type: CPU1.SYSRSn
22 CMPSS4_CTRIPOUTL R 0h CMPSS4_CTRIPOUTL X-BAR Flag
Reset type: CPU1.SYSRSn

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Table 9-25. XBARFLG1 Register Field Descriptions (continued)

Bit Field Type Reset Description
21 CMPSS3_CTRIPOUTH R 0h CMPSS3_CTRIPOUTH X-BAR Flag
Reset type: CPU1.SYSRSn
20 CMPSS3_CTRIPOUTL R 0h CMPSS3_CTRIPOUTL X-BAR Flag
Reset type: CPU1.SYSRSn
19 CMPSS2_CTRIPOUTH R 0h CMPSS2_CTRIPOUTH X-BAR Flag
Reset type: CPU1.SYSRSn
18 CMPSS2_CTRIPOUTL R 0h CMPSS2_CTRIPOUTL X-BAR Flag
Reset type: CPU1.SYSRSn
17 CMPSS1_CTRIPOUTH R 0h CMPSS1_CTRIPOUTH X-BAR Flag
Reset type: CPU1.SYSRSn
16 CMPSS1_CTRIPOUTL R 0h CMPSS1_CTRIPOUTL X-BAR Flag
Reset type: CPU1.SYSRSn
15 CMPSS8_CTRIPH R 0h CMPSS8_CTRIPH X-BAR Flag
Reset type: CPU1.SYSRSn
14 CMPSS8_CTRIPL R 0h CMPSS8_CTRIPL X-BAR Flag
Reset type: CPU1.SYSRSn
13 CMPSS7_CTRIPH R 0h CMPSS7_CTRIPH X-BAR Flag
Reset type: CPU1.SYSRSn
12 CMPSS7_CTRIPL R 0h CMPSS7_CTRIPL X-BAR Flag
Reset type: CPU1.SYSRSn
11 CMPSS6_CTRIPH R 0h CMPSS6_CTRIPH X-BAR Flag
Reset type: CPU1.SYSRSn
10 CMPSS6_CTRIPL R 0h CMPSS6_CTRIPL X-BAR Flag
Reset type: CPU1.SYSRSn
9 CMPSS5_CTRIPH R 0h CMPSS5_CTRIPH X-BAR Flag
Reset type: CPU1.SYSRSn
8 CMPSS5_CTRIPL R 0h CMPSS5_CTRIPL X-BAR Flag
Reset type: CPU1.SYSRSn
7 CMPSS4_CTRIPH R 0h CMPSS4_CTRIPH X-BAR Flag
Reset type: CPU1.SYSRSn
6 CMPSS4_CTRIPL R 0h CMPSS4_CTRIPL X-BAR Flag
Reset type: CPU1.SYSRSn
5 CMPSS3_CTRIPH R 0h CMPSS3_CTRIPH X-BAR Flag
Reset type: CPU1.SYSRSn
4 CMPSS3_CTRIPL R 0h CMPSS3_CTRIPL X-BAR Flag
Reset type: CPU1.SYSRSn
3 CMPSS2_CTRIPH R 0h CMPSS2_CTRIPH X-BAR Flag
Reset type: CPU1.SYSRSn
2 CMPSS2_CTRIPL R 0h CMPSS2_CTRIPL X-BAR Flag
Reset type: CPU1.SYSRSn
1 CMPSS1_CTRIPH R 0h CMPSS1_CTRIPH X-BAR Flag
Reset type: CPU1.SYSRSn
0 CMPSS1_CTRIPL R 0h CMPSS1_CTRIPL X-BAR Flag
Reset type: CPU1.SYSRSn

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9.3.3.2 XBARFLG2 Register (Offset = 2h) [Reset = 00000000h]

XBARFLG2 is shown in Figure 9-23 and described in Table 9-26.
Return to the Summary Table.
This register is used to flag the inputs of the X-Bars to provide software knowledge of the input sources which
got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Figure 9-23. XBARFLG2 Register
31 30 29 28 27 26 25 24
ADCCEVT1 ADCBEVT4 ADCBEVT3 ADCBEVT2 ADCBEVT1 ADCAEVT4 ADCAEVT3 ADCAEVT2
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

23 22 21 20 19 18 17 16
ADCAEVT1 EXTSYNCOUT ECAP6_OUT ECAP5_OUT ECAP4_OUT ECAP3_OUT ECAP2_OUT ECAP1_OUT
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

15 14 13 12 11 10 9 8
CLB4_OUT5 CLB4_OUT4 CLB3_OUT5 CLB3_OUT4 CLB2_OUT5 CLB2_OUT4 CLB1_OUT5 CLB1_OUT4
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
ADCSOCBO ADCSOCAO INPUT6 INPUT5 INPUT4 INPUT3 INPUT2 INPUT1
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 9-26. XBARFLG2 Register Field Descriptions

Bit Field Type Reset Description
31 ADCCEVT1 R 0h ADCCEVT1 X-BAR Flag
Reset type: CPU1.SYSRSn
30 ADCBEVT4 R 0h ADCBEVT4 X-BAR Flag
Reset type: CPU1.SYSRSn
29 ADCBEVT3 R 0h ADCBEVT3 X-BAR Flag
Reset type: CPU1.SYSRSn
28 ADCBEVT2 R 0h ADCBEVT2 X-BAR Flag
Reset type: CPU1.SYSRSn
27 ADCBEVT1 R 0h ADCBEVT1 X-BAR Flag
Reset type: CPU1.SYSRSn
26 ADCAEVT4 R 0h ADCAEVT4 X-BAR Flag
Reset type: CPU1.SYSRSn
25 ADCAEVT3 R 0h ADCAEVT3 X-BAR Flag
Reset type: CPU1.SYSRSn
24 ADCAEVT2 R 0h ADCAEVT2 X-BAR Flag
Reset type: CPU1.SYSRSn
23 ADCAEVT1 R 0h ADCAEVT1 X-BAR Flag
Reset type: CPU1.SYSRSn
22 EXTSYNCOUT R 0h EXTSYNCOUT X-BAR Flag
Reset type: CPU1.SYSRSn
21 ECAP6_OUT R 0h ECAP6_OUT X-BAR Flag
Reset type: CPU1.SYSRSn
20 ECAP5_OUT R 0h ECAP5_OUT X-BAR Flag
Reset type: CPU1.SYSRSn

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Table 9-26. XBARFLG2 Register Field Descriptions (continued)

Bit Field Type Reset Description
19 ECAP4_OUT R 0h ECAP4_OUT X-BAR Flag
Reset type: CPU1.SYSRSn
18 ECAP3_OUT R 0h ECAP3_OUT X-BAR Flag
Reset type: CPU1.SYSRSn
17 ECAP2_OUT R 0h ECAP2_OUT X-BAR Flag
Reset type: CPU1.SYSRSn
16 ECAP1_OUT R 0h ECAP1_OUT X-BAR Flag
Reset type: CPU1.SYSRSn
15 CLB4_OUT5 R 0h CLB4_OUT5 X-BAR Flag
Reset type: CPU1.SYSRSn
14 CLB4_OUT4 R 0h CLB4_OUT4 X-BAR Flag
Reset type: CPU1.SYSRSn
13 CLB3_OUT5 R 0h CLB3_OUT5 X-BAR Flag
Reset type: CPU1.SYSRSn
12 CLB3_OUT4 R 0h CLB3_OUT4 X-BAR Flag
Reset type: CPU1.SYSRSn
11 CLB2_OUT5 R 0h CLB2_OUT5 X-BAR Flag
Reset type: CPU1.SYSRSn
10 CLB2_OUT4 R 0h CLB2_OUT4 X-BAR Flag
Reset type: CPU1.SYSRSn
9 CLB1_OUT5 R 0h CLB1_OUT5 X-BAR Flag
Reset type: CPU1.SYSRSn
8 CLB1_OUT4 R 0h CLB1_OUT4 X-BAR Flag
Reset type: CPU1.SYSRSn
7 ADCSOCBO R 0h ADCSOCBO X-BAR Flag
Reset type: CPU1.SYSRSn
6 ADCSOCAO R 0h ADCSOCAO X-BAR Flag
Reset type: CPU1.SYSRSn
5 INPUT6 R 0h INPUT6 X-BAR Flag
Reset type: CPU1.SYSRSn
4 INPUT5 R 0h INPUT5 X-BAR Flag
Reset type: CPU1.SYSRSn
3 INPUT4 R 0h INPUT4 X-BAR Flag
Reset type: CPU1.SYSRSn
2 INPUT3 R 0h INPUT3 X-BAR Flag
Reset type: CPU1.SYSRSn
1 INPUT2 R 0h INPUT2 X-BAR Flag
Reset type: CPU1.SYSRSn
0 INPUT1 R 0h INPUT1 X-BAR Flag
Reset type: CPU1.SYSRSn

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9.3.3.3 XBARFLG3 Register (Offset = 4h) [Reset = 00000000h]

XBARFLG3 is shown in Figure 9-24 and described in Table 9-27.
Return to the Summary Table.
This register is used to flag the inputs of the X-Bars to provide software knowledge of the input sources which
got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Figure 9-24. XBARFLG3 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED SD2FLT4_COM SD2FLT4_COM SD2FLT3_COM SD2FLT3_COM SD2FLT2_COM SD2FLT2_COM SD2FLT1_COM
PH PL PH PL PH PL PH
R-0-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

15 14 13 12 11 10 9 8
SD2FLT1_COM SD1FLT4_COM SD1FLT4_COM SD1FLT3_COM SD1FLT3_COM SD1FLT2_COM SD1FLT2_COM SD1FLT1_COM
PL PH PL PH PL PH PL PH
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
SD1FLT1_COM ADCDEVT4 ADCDEVT3 ADCDEVT2 ADCDEVT1 ADCCEVT4 ADCCEVT3 ADCCEVT2
PL
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 9-27. XBARFLG3 Register Field Descriptions

Bit Field Type Reset Description
31-23 RESERVED R-0 0h Reserved
22 SD2FLT4_COMPH R 0h SD2FLT4_COMPH X-BAR Flag
Reset type: CPU1.SYSRSn
21 SD2FLT4_COMPL R 0h SD2FLT4_COMPL X-BAR Flag
Reset type: CPU1.SYSRSn
20 SD2FLT3_COMPH R 0h SD2FLT3_COMPH X-BAR Flag
Reset type: CPU1.SYSRSn
19 SD2FLT3_COMPL R 0h SD2FLT3_COMPL X-BAR Flag
Reset type: CPU1.SYSRSn
18 SD2FLT2_COMPH R 0h SD2FLT2_COMPH X-BAR Flag
Reset type: CPU1.SYSRSn
17 SD2FLT2_COMPL R 0h SD2FLT2_COMPL X-BAR Flag
Reset type: CPU1.SYSRSn
16 SD2FLT1_COMPH R 0h SD2FLT1_COMPH X-BAR Flag
Reset type: CPU1.SYSRSn
15 SD2FLT1_COMPL R 0h SD2FLT1_COMPL X-BAR Flag
Reset type: CPU1.SYSRSn
14 SD1FLT4_COMPH R 0h SD1FLT4_COMPH X-BAR Flag
Reset type: CPU1.SYSRSn
13 SD1FLT4_COMPL R 0h SD1FLT4_COMPL X-BAR Flag
Reset type: CPU1.SYSRSn

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Table 9-27. XBARFLG3 Register Field Descriptions (continued)

Bit Field Type Reset Description
12 SD1FLT3_COMPH R 0h SD1FLT3_COMPH X-BAR Flag
Reset type: CPU1.SYSRSn
11 SD1FLT3_COMPL R 0h SD1FLT3_COMPL X-BAR Flag
Reset type: CPU1.SYSRSn
10 SD1FLT2_COMPH R 0h SD1FLT2_COMPH X-BAR Flag
Reset type: CPU1.SYSRSn
9 SD1FLT2_COMPL R 0h SD1FLT2_COMPL X-BAR Flag
Reset type: CPU1.SYSRSn
8 SD1FLT1_COMPH R 0h SD1FLT1_COMPH X-BAR Flag
Reset type: CPU1.SYSRSn
7 SD1FLT1_COMPL R 0h SD1FLT1_COMPL X-BAR Flag
Reset type: CPU1.SYSRSn
6 ADCDEVT4 R 0h ADCDEVT4 X-BAR Flag
Reset type: CPU1.SYSRSn
5 ADCDEVT3 R 0h ADCDEVT3 X-BAR Flag
Reset type: CPU1.SYSRSn
4 ADCDEVT2 R 0h ADCDEVT2 X-BAR Flag
Reset type: CPU1.SYSRSn
3 ADCDEVT1 R 0h ADCDEVT1 X-BAR Flag
Reset type: CPU1.SYSRSn
2 ADCCEVT4 R 0h ADCCEVT4 X-BAR Flag
Reset type: CPU1.SYSRSn
1 ADCCEVT3 R 0h ADCCEVT3 X-BAR Flag
Reset type: CPU1.SYSRSn
0 ADCCEVT2 R 0h ADCCEVT2 X-BAR Flag
Reset type: CPU1.SYSRSn

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9.3.3.4 XBARCLR1 Register (Offset = 8h) [Reset = 00000000h]

XBARCLR1 is shown in Figure 9-25 and described in Table 9-28.
Return to the Summary Table.
This register is used to clear the flag(s) in the XBARFLG1 register.
1: Clears the corresponding bit in the XBARFLG1 register.
0: Writing 0 has no effect
Figure 9-25. XBARCLR1 Register
31 30 29 28 27 26 25 24
CMPSS8_CTRI CMPSS8_CTRI CMPSS7_CTRI CMPSS7_CTRI CMPSS6_CTRI CMPSS6_CTRI CMPSS5_CTRI CMPSS5_CTRI
POUTH POUTL POUTH POUTL POUTH POUTL POUTH POUTL
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

23 22 21 20 19 18 17 16
CMPSS4_CTRI CMPSS4_CTRI CMPSS3_CTRI CMPSS3_CTRI CMPSS2_CTRI CMPSS2_CTRI CMPSS1_CTRI CMPSS1_CTRI
POUTH POUTL POUTH POUTL POUTH POUTL POUTH POUTL
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

15 14 13 12 11 10 9 8
CMPSS8_CTRI CMPSS8_CTRI CMPSS7_CTRI CMPSS7_CTRI CMPSS6_CTRI CMPSS6_CTRI CMPSS5_CTRI CMPSS5_CTRI
PH PL PH PL PH PL PH PL
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

7 6 5 4 3 2 1 0
CMPSS4_CTRI CMPSS4_CTRI CMPSS3_CTRI CMPSS3_CTRI CMPSS2_CTRI CMPSS2_CTRI CMPSS1_CTRI CMPSS1_CTRI
PH PL PH PL PH PL PH PL
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 9-28. XBARCLR1 Register Field Descriptions

Bit Field Type Reset Description
31 CMPSS8_CTRIPOUTH R-0/W1S 0h CMPSS8_CTRIPOUTH X-BAR Flag Clear
Reset type: CPU1.SYSRSn
30 CMPSS8_CTRIPOUTL R-0/W1S 0h CMPSS8_CTRIPOUTL X-BAR Flag Clear
Reset type: CPU1.SYSRSn
29 CMPSS7_CTRIPOUTH R-0/W1S 0h CMPSS7_CTRIPOUTH X-BAR Flag Clear
Reset type: CPU1.SYSRSn
28 CMPSS7_CTRIPOUTL R-0/W1S 0h CMPSS7_CTRIPOUTL X-BAR Flag Clear
Reset type: CPU1.SYSRSn
27 CMPSS6_CTRIPOUTH R-0/W1S 0h CMPSS6_CTRIPOUTH X-BAR Flag Clear
Reset type: CPU1.SYSRSn
26 CMPSS6_CTRIPOUTL R-0/W1S 0h CMPSS6_CTRIPOUTL X-BAR Flag Clear
Reset type: CPU1.SYSRSn
25 CMPSS5_CTRIPOUTH R-0/W1S 0h CMPSS5_CTRIPOUTH X-BAR Flag Clear
Reset type: CPU1.SYSRSn
24 CMPSS5_CTRIPOUTL R-0/W1S 0h CMPSS5_CTRIPOUTL X-BAR Flag Clear
Reset type: CPU1.SYSRSn
23 CMPSS4_CTRIPOUTH R-0/W1S 0h CMPSS4_CTRIPOUTH X-BAR Flag Clear
Reset type: CPU1.SYSRSn
22 CMPSS4_CTRIPOUTL R-0/W1S 0h CMPSS4_CTRIPOUTL X-BAR Flag Clear
Reset type: CPU1.SYSRSn
21 CMPSS3_CTRIPOUTH R-0/W1S 0h CMPSS3_CTRIPOUTH X-BAR Flag Clear
Reset type: CPU1.SYSRSn

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Table 9-28. XBARCLR1 Register Field Descriptions (continued)

Bit Field Type Reset Description
20 CMPSS3_CTRIPOUTL R-0/W1S 0h CMPSS3_CTRIPOUTL X-BAR Flag Clear
Reset type: CPU1.SYSRSn
19 CMPSS2_CTRIPOUTH R-0/W1S 0h CMPSS2_CTRIPOUTH X-BAR Flag Clear
Reset type: CPU1.SYSRSn
18 CMPSS2_CTRIPOUTL R-0/W1S 0h CMPSS2_CTRIPOUTL X-BAR Flag Clear
Reset type: CPU1.SYSRSn
17 CMPSS1_CTRIPOUTH R-0/W1S 0h CMPSS1_CTRIPOUTH X-BAR Flag Clear
Reset type: CPU1.SYSRSn
16 CMPSS1_CTRIPOUTL R-0/W1S 0h CMPSS1_CTRIPOUTL X-BAR Flag Clear
Reset type: CPU1.SYSRSn
15 CMPSS8_CTRIPH R-0/W1S 0h CMPSS8_CTRIPH X-BAR Flag Clear
Reset type: CPU1.SYSRSn
14 CMPSS8_CTRIPL R-0/W1S 0h CMPSS8_CTRIPL X-BAR Flag Clear
Reset type: CPU1.SYSRSn
13 CMPSS7_CTRIPH R-0/W1S 0h CMPSS7_CTRIPH X-BAR Flag Clear
Reset type: CPU1.SYSRSn
12 CMPSS7_CTRIPL R-0/W1S 0h CMPSS7_CTRIPL X-BAR Flag Clear
Reset type: CPU1.SYSRSn
11 CMPSS6_CTRIPH R-0/W1S 0h CMPSS6_CTRIPH X-BAR Flag Clear
Reset type: CPU1.SYSRSn
10 CMPSS6_CTRIPL R-0/W1S 0h CMPSS6_CTRIPL X-BAR Flag Clear
Reset type: CPU1.SYSRSn
9 CMPSS5_CTRIPH R-0/W1S 0h CMPSS5_CTRIPH X-BAR Flag Clear
Reset type: CPU1.SYSRSn
8 CMPSS5_CTRIPL R-0/W1S 0h CMPSS5_CTRIPL X-BAR Flag Clear
Reset type: CPU1.SYSRSn
7 CMPSS4_CTRIPH R-0/W1S 0h CMPSS4_CTRIPH X-BAR Flag Clear
Reset type: CPU1.SYSRSn
6 CMPSS4_CTRIPL R-0/W1S 0h CMPSS4_CTRIPL X-BAR Flag Clear
Reset type: CPU1.SYSRSn
5 CMPSS3_CTRIPH R-0/W1S 0h CMPSS3_CTRIPH X-BAR Flag Clear
Reset type: CPU1.SYSRSn
4 CMPSS3_CTRIPL R-0/W1S 0h CMPSS3_CTRIPL X-BAR Flag Clear
Reset type: CPU1.SYSRSn
3 CMPSS2_CTRIPH R-0/W1S 0h CMPSS2_CTRIPH X-BAR Flag Clear
Reset type: CPU1.SYSRSn
2 CMPSS2_CTRIPL R-0/W1S 0h CMPSS2_CTRIPL X-BAR Flag Clear
Reset type: CPU1.SYSRSn
1 CMPSS1_CTRIPH R-0/W1S 0h CMPSS1_CTRIPH X-BAR Flag Clear
Reset type: CPU1.SYSRSn
0 CMPSS1_CTRIPL R-0/W1S 0h CMPSS1_CTRIPL X-BAR Flag Clear
Reset type: CPU1.SYSRSn

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9.3.3.5 XBARCLR2 Register (Offset = Ah) [Reset = 00000000h]

XBARCLR2 is shown in Figure 9-26 and described in Table 9-29.
Return to the Summary Table.
This register is used to clear the flag(s) in the XBARFLG2 register.
1: Clears the corresponding bit in the XBARFLG2 register.
0: Writing 0 has no effect
Figure 9-26. XBARCLR2 Register
31 30 29 28 27 26 25 24
ADCCEVT1 ADCBEVT4 ADCBEVT3 ADCBEVT2 ADCBEVT1 ADCAEVT4 ADCAEVT3 ADCAEVT2
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

23 22 21 20 19 18 17 16
ADCAEVT1 EXTSYNCOUT ECAP6_OUT ECAP5_OUT ECAP4_OUT ECAP3_OUT ECAP2_OUT ECAP1_OUT
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

15 14 13 12 11 10 9 8
CLB4_OUT5 CLB4_OUT4 CLB3_OUT5 CLB3_OUT4 CLB2_OUT5 CLB2_OUT4 CLB1_OUT5 CLB1_OUT4
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

7 6 5 4 3 2 1 0
ADCSOCBO ADCSOCAO INPUT6 INPUT5 INPUT4 INPUT3 INPUT2 INPUT1
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 9-29. XBARCLR2 Register Field Descriptions

Bit Field Type Reset Description
31 ADCCEVT1 R-0/W1S 0h ADCCEVT1 X-BAR Flag Clear
Reset type: CPU1.SYSRSn
30 ADCBEVT4 R-0/W1S 0h ADCBEVT4 X-BAR Flag Clear
Reset type: CPU1.SYSRSn
29 ADCBEVT3 R-0/W1S 0h ADCBEVT3 X-BAR Flag Clear
Reset type: CPU1.SYSRSn
28 ADCBEVT2 R-0/W1S 0h ADCBEVT2 X-BAR Flag Clear
Reset type: CPU1.SYSRSn
27 ADCBEVT1 R-0/W1S 0h ADCBEVT1 X-BAR Flag Clear
Reset type: CPU1.SYSRSn
26 ADCAEVT4 R-0/W1S 0h ADCAEVT4 X-BAR Flag Clear
Reset type: CPU1.SYSRSn
25 ADCAEVT3 R-0/W1S 0h ADCAEVT3 X-BAR Flag Clear
Reset type: CPU1.SYSRSn
24 ADCAEVT2 R-0/W1S 0h ADCAEVT2 X-BAR Flag Clear
Reset type: CPU1.SYSRSn
23 ADCAEVT1 R-0/W1S 0h ADCAEVT1 X-BAR Flag Clear
Reset type: CPU1.SYSRSn
22 EXTSYNCOUT R-0/W1S 0h EXTSYNCOUT X-BAR Flag Clear
Reset type: CPU1.SYSRSn
21 ECAP6_OUT R-0/W1S 0h ECAP6_OUT X-BAR Flag Clear
Reset type: CPU1.SYSRSn
20 ECAP5_OUT R-0/W1S 0h ECAP5_OUT X-BAR Flag Clear
Reset type: CPU1.SYSRSn

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Table 9-29. XBARCLR2 Register Field Descriptions (continued)

Bit Field Type Reset Description
19 ECAP4_OUT R-0/W1S 0h ECAP4_OUT X-BAR Flag Clear
Reset type: CPU1.SYSRSn
18 ECAP3_OUT R-0/W1S 0h ECAP3_OUT X-BAR Flag Clear
Reset type: CPU1.SYSRSn
17 ECAP2_OUT R-0/W1S 0h ECAP2_OUT X-BAR Flag Clear
Reset type: CPU1.SYSRSn
16 ECAP1_OUT R-0/W1S 0h ECAP1_OUT X-BAR Flag Clear
Reset type: CPU1.SYSRSn
15 CLB4_OUT5 R-0/W1S 0h CLB4_OUT5 X-BAR Flag Clear
Reset type: CPU1.SYSRSn
14 CLB4_OUT4 R-0/W1S 0h CLB4_OUT4 X-BAR Flag Clear
Reset type: CPU1.SYSRSn
13 CLB3_OUT5 R-0/W1S 0h CLB3_OUT5 X-BAR Flag Clear
Reset type: CPU1.SYSRSn
12 CLB3_OUT4 R-0/W1S 0h CLB3_OUT4 X-BAR Flag Clear
Reset type: CPU1.SYSRSn
11 CLB2_OUT5 R-0/W1S 0h CLB2_OUT5 X-BAR Flag Clear
Reset type: CPU1.SYSRSn
10 CLB2_OUT4 R-0/W1S 0h CLB2_OUT4 X-BAR Flag Clear
Reset type: CPU1.SYSRSn
9 CLB1_OUT5 R-0/W1S 0h CLB1_OUT5 X-BAR Flag Clear
Reset type: CPU1.SYSRSn
8 CLB1_OUT4 R-0/W1S 0h CLB1_OUT4 X-BAR Flag Clear
Reset type: CPU1.SYSRSn
7 ADCSOCBO R-0/W1S 0h ADCSOCBO X-BAR Flag Clear
Reset type: CPU1.SYSRSn
6 ADCSOCAO R-0/W1S 0h ADCSOCAO X-BAR Flag Clear
Reset type: CPU1.SYSRSn
5 INPUT6 R-0/W1S 0h INPUT6 X-BAR Flag Clear
Reset type: CPU1.SYSRSn
4 INPUT5 R-0/W1S 0h INPUT5 X-BAR Flag Clear
Reset type: CPU1.SYSRSn
3 INPUT4 R-0/W1S 0h INPUT4 X-BAR Flag Clear
Reset type: CPU1.SYSRSn
2 INPUT3 R-0/W1S 0h INPUT3 X-BAR Flag Clear
Reset type: CPU1.SYSRSn
1 INPUT2 R-0/W1S 0h INPUT2 X-BAR Flag Clear
Reset type: CPU1.SYSRSn
0 INPUT1 R-0/W1S 0h INPUT1 X-BAR Flag Clear
Reset type: CPU1.SYSRSn

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9.3.3.6 XBARCLR3 Register (Offset = Ch) [Reset = 00000000h]

XBARCLR3 is shown in Figure 9-27 and described in Table 9-30.
Return to the Summary Table.
This register is used to clear the flag(s) in the XBARFLG3 register.
1: Clears the corresponding bit in the XBARFLG3 register.
0: Writing 0 has no effect
Figure 9-27. XBARCLR3 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED SD2FLT4_COM SD2FLT4_COM SD2FLT3_COM SD2FLT3_COM SD2FLT2_COM SD2FLT2_COM SD2FLT1_COM
PH PL PH PL PH PL PH
R-0-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

15 14 13 12 11 10 9 8
SD2FLT1_COM SD1FLT4_COM SD1FLT4_COM SD1FLT3_COM SD1FLT3_COM SD1FLT2_COM SD1FLT2_COM SD1FLT1_COM
PL PH PL PH PL PH PL PH
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

7 6 5 4 3 2 1 0
SD1FLT1_COM ADCDEVT4 ADCDEVT3 ADCDEVT2 ADCDEVT1 ADCCEVT4 ADCCEVT3 ADCCEVT2
PL
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 9-30. XBARCLR3 Register Field Descriptions

Bit Field Type Reset Description
31-23 RESERVED R-0 0h Reserved
22 SD2FLT4_COMPH R-0/W1S 0h SD2FLT4_COMPH X-BAR Flag Clear
Reset type: CPU1.SYSRSn
21 SD2FLT4_COMPL R-0/W1S 0h SD2FLT4_COMPL X-BAR Flag Clear
Reset type: CPU1.SYSRSn
20 SD2FLT3_COMPH R-0/W1S 0h SD2FLT3_COMPH X-BAR Flag Clear
Reset type: CPU1.SYSRSn
19 SD2FLT3_COMPL R-0/W1S 0h SD2FLT3_COMPL X-BAR Flag Clear
Reset type: CPU1.SYSRSn
18 SD2FLT2_COMPH R-0/W1S 0h SD2FLT2_COMPH X-BAR Flag Clear
Reset type: CPU1.SYSRSn
17 SD2FLT2_COMPL R-0/W1S 0h SD2FLT2_COMPL X-BAR Flag Clear
Reset type: CPU1.SYSRSn
16 SD2FLT1_COMPH R-0/W1S 0h SD2FLT1_COMPH X-BAR Flag Clear
Reset type: CPU1.SYSRSn
15 SD2FLT1_COMPL R-0/W1S 0h SD2FLT1_COMPL X-BAR Flag Clear
Reset type: CPU1.SYSRSn
14 SD1FLT4_COMPH R-0/W1S 0h SD1FLT4_COMPH X-BAR Flag Clear
Reset type: CPU1.SYSRSn
13 SD1FLT4_COMPL R-0/W1S 0h SD1FLT4_COMPL X-BAR Flag Clear
Reset type: CPU1.SYSRSn
12 SD1FLT3_COMPH R-0/W1S 0h SD1FLT3_COMPH X-BAR Flag Clear
Reset type: CPU1.SYSRSn

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Table 9-30. XBARCLR3 Register Field Descriptions (continued)

Bit Field Type Reset Description
11 SD1FLT3_COMPL R-0/W1S 0h SD1FLT3_COMPL X-BAR Flag Clear
Reset type: CPU1.SYSRSn
10 SD1FLT2_COMPH R-0/W1S 0h SD1FLT2_COMPH X-BAR Flag Clear
Reset type: CPU1.SYSRSn
9 SD1FLT2_COMPL R-0/W1S 0h SD1FLT2_COMPL X-BAR Flag Clear
Reset type: CPU1.SYSRSn
8 SD1FLT1_COMPH R-0/W1S 0h SD1FLT1_COMPH X-BAR Flag Clear
Reset type: CPU1.SYSRSn
7 SD1FLT1_COMPL R-0/W1S 0h SD1FLT1_COMPL X-BAR Flag Clear
Reset type: CPU1.SYSRSn
6 ADCDEVT4 R-0/W1S 0h ADCDEVT4 X-BAR Flag Clear
Reset type: CPU1.SYSRSn
5 ADCDEVT3 R-0/W1S 0h ADCDEVT3 X-BAR Flag Clear
Reset type: CPU1.SYSRSn
4 ADCDEVT2 R-0/W1S 0h ADCDEVT2 X-BAR Flag Clear
Reset type: CPU1.SYSRSn
3 ADCDEVT1 R-0/W1S 0h ADCDEVT1 X-BAR Flag Clear
Reset type: CPU1.SYSRSn
2 ADCCEVT4 R-0/W1S 0h ADCCEVT4 X-BAR Flag Clear
Reset type: CPU1.SYSRSn
1 ADCCEVT3 R-0/W1S 0h ADCCEVT3 X-BAR Flag Clear
Reset type: CPU1.SYSRSn
0 ADCCEVT2 R-0/W1S 0h ADCCEVT2 X-BAR Flag Clear
Reset type: CPU1.SYSRSn

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9.3.4 EPWM_XBAR_REGS Registers

Table 9-31 lists the memory-mapped registers for the EPWM_XBAR_REGS registers. All register offset
addresses not listed in Table 9-31 should be considered as reserved locations and the register contents should
not be modified.
Table 9-31. EPWM_XBAR_REGS Registers
Offset Acronym Register Name Write Protection Section
0h TRIP4MUX0TO15CFG ePWM XBAR Mux Configuration for TRIP4 EALLOW Go
2h TRIP4MUX16TO31CFG ePWM XBAR Mux Configuration for TRIP4 EALLOW Go
4h TRIP5MUX0TO15CFG ePWM XBAR Mux Configuration for TRIP5 EALLOW Go
6h TRIP5MUX16TO31CFG ePWM XBAR Mux Configuration for TRIP5 EALLOW Go
8h TRIP7MUX0TO15CFG ePWM XBAR Mux Configuration for TRIP7 EALLOW Go
Ah TRIP7MUX16TO31CFG ePWM XBAR Mux Configuration for TRIP7 EALLOW Go
Ch TRIP8MUX0TO15CFG ePWM XBAR Mux Configuration for TRIP8 EALLOW Go
Eh TRIP8MUX16TO31CFG ePWM XBAR Mux Configuration for TRIP8 EALLOW Go
10h TRIP9MUX0TO15CFG ePWM XBAR Mux Configuration for TRIP9 EALLOW Go
12h TRIP9MUX16TO31CFG ePWM XBAR Mux Configuration for TRIP9 EALLOW Go
14h TRIP10MUX0TO15CFG ePWM XBAR Mux Configuration for TRIP10 EALLOW Go
16h TRIP10MUX16TO31CFG ePWM XBAR Mux Configuration for TRIP10 EALLOW Go
18h TRIP11MUX0TO15CFG ePWM XBAR Mux Configuration for TRIP11 EALLOW Go
1Ah TRIP11MUX16TO31CFG ePWM XBAR Mux Configuration for TRIP11 EALLOW Go
1Ch TRIP12MUX0TO15CFG ePWM XBAR Mux Configuration for TRIP12 EALLOW Go
1Eh TRIP12MUX16TO31CFG ePWM XBAR Mux Configuration for TRIP12 EALLOW Go
20h TRIP4MUXENABLE ePWM XBAR Mux Enable for TRIP4 EALLOW Go
22h TRIP5MUXENABLE ePWM XBAR Mux Enable for TRIP5 EALLOW Go
24h TRIP7MUXENABLE ePWM XBAR Mux Enable for TRIP7 EALLOW Go
26h TRIP8MUXENABLE ePWM XBAR Mux Enable for TRIP8 EALLOW Go
28h TRIP9MUXENABLE ePWM XBAR Mux Enable for TRIP9 EALLOW Go
2Ah TRIP10MUXENABLE ePWM XBAR Mux Enable for TRIP10 EALLOW Go
2Ch TRIP11MUXENABLE ePWM XBAR Mux Enable for TRIP11 EALLOW Go
2Eh TRIP12MUXENABLE ePWM XBAR Mux Enable for TRIP12 EALLOW Go
38h TRIPOUTINV ePWM XBAR Output Inversion Register EALLOW Go
3Eh TRIPLOCK ePWM XBAR Configuration Lock register EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 9-32 shows the codes that are used for
access types in this section.
Table 9-32. EPWM_XBAR_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
WSonce W Write
Sonce Set once
Reset or Default Value
-n Value after reset or the default value

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Table 9-32. EPWM_XBAR_REGS Access Type Codes (continued)

Access Type Code Description
Register Array Variables
i,j,k,l,m,n When these variables are used in a register name,
an offset, or an address, they refer to the value of a
register array where the register is part of a group
of repeating registers. The register groups form a
hierarchical structure and the array is represented
with a formula.
y When this variable is used in a register name, an
offset, or an address it refers to the value of a
register array.

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9.3.4.1 TRIP4MUX0TO15CFG Register (Offset = 0h) [Reset = 00000000h]

TRIP4MUX0TO15CFG is shown in Figure 9-28 and described in Table 9-33.
Return to the Summary Table.
ePWM XBAR Mux Configuration for TRIP4
Figure 9-28. TRIP4MUX0TO15CFG Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MUX15 MUX14 MUX13 MUX12 MUX11 MUX10 MUX9 MUX8
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX7 MUX6 MUX5 MUX4 MUX3 MUX2 MUX1 MUX0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 9-33. TRIP4MUX0TO15CFG Register Field Descriptions

Bit Field Type Reset Description
31-30 MUX15 R/W 0h Select Bits for EPWM-XBAR TRIP4 Mux15:
00 : Select .0 input for Mux15
01 : Select .1 input for Mux15
10 : Select .2 input for Mux15
11 : Select .3 input for Mux15
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
29-28 MUX14 R/W 0h Select Bits for EPWM-XBAR TRIP4 Mux14:
00 : Select .0 input for Mux14
01 : Select .1 input for Mux14
10 : Select .2 input for Mux14
11 : Select .3 input for Mux14
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
27-26 MUX13 R/W 0h Select Bits for EPWM-XBAR TRIP4 Mux13:
00 : Select .0 input for Mux13
01 : Select .1 input for Mux13
10 : Select .2 input for Mux13
11 : Select .3 input for Mux13
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
25-24 MUX12 R/W 0h Select Bits for EPWM-XBAR TRIP4 Mux12:
00 : Select .0 input for Mux12
01 : Select .1 input for Mux12
10 : Select .2 input for Mux12
11 : Select .3 input for Mux12
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
23-22 MUX11 R/W 0h Select Bits for EPWM-XBAR TRIP4 Mux11:
00 : Select .0 input for Mux11
01 : Select .1 input for Mux11
10 : Select .2 input for Mux11
11 : Select .3 input for Mux11
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
21-20 MUX10 R/W 0h Select Bits for EPWM-XBAR TRIP4 Mux10:
00 : Select .0 input for Mux10
01 : Select .1 input for Mux10
10 : Select .2 input for Mux10
11 : Select .3 input for Mux10
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

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Table 9-33. TRIP4MUX0TO15CFG Register Field Descriptions (continued)

Bit Field Type Reset Description
19-18 MUX9 R/W 0h Select Bits for EPWM-XBAR TRIP4 Mux9:
00 : Select .0 input for Mux9
01 : Select .1 input for Mux9
10 : Select .2 input for Mux9
11 : Select .3 input for Mux9
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
17-16 MUX8 R/W 0h Select Bits for EPWM-XBAR TRIP4 Mux8:
00 : Select .0 input for Mux8
01 : Select .1 input for Mux8
10 : Select .2 input for Mux8
11 : Select .3 input for Mux8
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
15-14 MUX7 R/W 0h Select Bits for EPWM-XBAR TRIP4 Mux7:
00 : Select .0 input for Mux7
01 : Select .1 input for Mux7
10 : Select .2 input for Mux7
11 : Select .3 input for Mux7
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
13-12 MUX6 R/W 0h Select Bits for EPWM-XBAR TRIP4 Mux6:
00 : Select .0 input for Mux6
01 : Select .1 input for Mux6
10 : Select .2 input for Mux6
11 : Select .3 input for Mux6
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
11-10 MUX5 R/W 0h Select Bits for EPWM-XBAR TRIP4 Mux5:
00 : Select .0 input for Mux5
01 : Select .1 input for Mux5
10 : Select .2 input for Mux5
11 : Select .3 input for Mux5
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
9-8 MUX4 R/W 0h Select Bits for EPWM-XBAR TRIP4 Mux4:
00 : Select .0 input for Mux4
01 : Select .1 input for Mux4
10 : Select .2 input for Mux4
11 : Select .3 input for Mux4
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
7-6 MUX3 R/W 0h Select Bits for EPWM-XBAR TRIP4 Mux3:
00 : Select .0 input for Mux3
01 : Select .1 input for Mux3
10 : Select .2 input for Mux3
11 : Select .3 input for Mux3
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
5-4 MUX2 R/W 0h Select Bits for EPWM-XBAR TRIP4 Mux2:
00 : Select .0 input for Mux2
01 : Select .1 input for Mux2
10 : Select .2 input for Mux2
11 : Select .3 input for Mux2
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

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Table 9-33. TRIP4MUX0TO15CFG Register Field Descriptions (continued)

Bit Field Type Reset Description
3-2 MUX1 R/W 0h Select Bits for EPWM-XBAR TRIP4 Mux1:
00 : Select .0 input for Mux1
01 : Select .1 input for Mux1
10 : Select .2 input for Mux1
11 : Select .3 input for Mux1
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
1-0 MUX0 R/W 0h Select Bits for EPWM-XBAR TRIP4 Mux0:
00 : Select .0 input for Mux0
01 : Select .1 input for Mux0
10 : Select .2 input for Mux0
11 : Select .3 input for Mux0
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

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9.3.4.2 TRIP4MUX16TO31CFG Register (Offset = 2h) [Reset = 00000000h]

TRIP4MUX16TO31CFG is shown in Figure 9-29 and described in Table 9-34.
Return to the Summary Table.
ePWM XBAR Mux Configuration for TRIP4
Figure 9-29. TRIP4MUX16TO31CFG Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MUX31 MUX30 MUX29 MUX28 MUX27 MUX26 MUX25 MUX24
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX23 MUX22 MUX21 MUX20 MUX19 MUX18 MUX17 MUX16
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 9-34. TRIP4MUX16TO31CFG Register Field Descriptions

Bit Field Type Reset Description
31-30 MUX31 R/W 0h Select Bits for EPWM-XBAR TRIP4 Mux31:
00 : Select .0 input for Mux31
01 : Select .1 input for Mux31
10 : Select .2 input for Mux31
11 : Select .3 input for Mux31
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
29-28 MUX30 R/W 0h Select Bits for EPWM-XBAR TRIP4 Mux30:
00 : Select .0 input for Mux30
01 : Select .1 input for Mux30
10 : Select .2 input for Mux30
11 : Select .3 input for Mux30
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
27-26 MUX29 R/W 0h Select Bits for EPWM-XBAR TRIP4 Mux29:
00 : Select .0 input for Mux29
01 : Select .1 input for Mux29
10 : Select .2 input for Mux29
11 : Select .3 input for Mux29
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
25-24 MUX28 R/W 0h Select Bits for EPWM-XBAR TRIP4 Mux28:
00 : Select .0 input for Mux28
01 : Select .1 input for Mux28
10 : Select .2 input for Mux28
11 : Select .3 input for Mux28
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
23-22 MUX27 R/W 0h Select Bits for EPWM-XBAR TRIP4 Mux27:
00 : Select .0 input for Mux27
01 : Select .1 input for Mux27
10 : Select .2 input for Mux27
11 : Select .3 input for Mux27
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
21-20 MUX26 R/W 0h Select Bits for EPWM-XBAR TRIP4 Mux26:
00 : Select .0 input for Mux26
01 : Select .1 input for Mux26
10 : Select .2 input for Mux26
11 : Select .3 input for Mux26
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

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Table 9-34. TRIP4MUX16TO31CFG Register Field Descriptions (continued)

Bit Field Type Reset Description
19-18 MUX25 R/W 0h Select Bits for EPWM-XBAR TRIP4 Mux25:
00 : Select .0 input for Mux25
01 : Select .1 input for Mux25
10 : Select .2 input for Mux25
11 : Select .3 input for Mux25
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
17-16 MUX24 R/W 0h Select Bits for EPWM-XBAR TRIP4 Mux24:
00 : Select .0 input for Mux24
01 : Select .1 input for Mux24
10 : Select .2 input for Mux24
11 : Select .3 input for Mux24
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
15-14 MUX23 R/W 0h Select Bits for EPWM-XBAR TRIP4 Mux23:
00 : Select .0 input for Mux23
01 : Select .1 input for Mux23
10 : Select .2 input for Mux23
11 : Select .3 input for Mux23
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
13-12 MUX22 R/W 0h Select Bits for EPWM-XBAR TRIP4 Mux22:
00 : Select .0 input for Mux22
01 : Select .1 input for Mux22
10 : Select .2 input for Mux22
11 : Select .3 input for Mux22
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
11-10 MUX21 R/W 0h Select Bits for EPWM-XBAR TRIP4 Mux21:
00 : Select .0 input for Mux21
01 : Select .1 input for Mux21
10 : Select .2 input for Mux21
11 : Select .3 input for Mux21
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
9-8 MUX20 R/W 0h Select Bits for EPWM-XBAR TRIP4 Mux20:
00 : Select .0 input for Mux20
01 : Select .1 input for Mux20
10 : Select .2 input for Mux20
11 : Select .3 input for Mux20
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
7-6 MUX19 R/W 0h Select Bits for EPWM-XBAR TRIP4 Mux19:
00 : Select .0 input for Mux19
01 : Select .1 input for Mux19
10 : Select .2 input for Mux19
11 : Select .3 input for Mux19
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
5-4 MUX18 R/W 0h Select Bits for EPWM-XBAR TRIP4 Mux18:
00 : Select .0 input for Mux18
01 : Select .1 input for Mux18
10 : Select .2 input for Mux18
11 : Select .3 input for Mux18
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

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Table 9-34. TRIP4MUX16TO31CFG Register Field Descriptions (continued)

Bit Field Type Reset Description
3-2 MUX17 R/W 0h Select Bits for EPWM-XBAR TRIP4 Mux17:
00 : Select .0 input for Mux17
01 : Select .1 input for Mux17
10 : Select .2 input for Mux17
11 : Select .3 input for Mux17
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
1-0 MUX16 R/W 0h Select Bits for EPWM-XBAR TRIP4 Mux16:
00 : Select .0 input for Mux16
01 : Select .1 input for Mux16
10 : Select .2 input for Mux16
11 : Select .3 input for Mux16
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

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9.3.4.3 TRIP5MUX0TO15CFG Register (Offset = 4h) [Reset = 00000000h]

TRIP5MUX0TO15CFG is shown in Figure 9-30 and described in Table 9-35.
Return to the Summary Table.
ePWM XBAR Mux Configuration for TRIP5
Figure 9-30. TRIP5MUX0TO15CFG Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MUX15 MUX14 MUX13 MUX12 MUX11 MUX10 MUX9 MUX8
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX7 MUX6 MUX5 MUX4 MUX3 MUX2 MUX1 MUX0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 9-35. TRIP5MUX0TO15CFG Register Field Descriptions

Bit Field Type Reset Description
31-30 MUX15 R/W 0h Select Bits for EPWM-XBAR TRIP5 Mux15:
00 : Select .0 input for Mux15
01 : Select .1 input for Mux15
10 : Select .2 input for Mux15
11 : Select .3 input for Mux15
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
29-28 MUX14 R/W 0h Select Bits for EPWM-XBAR TRIP5 Mux14:
00 : Select .0 input for Mux14
01 : Select .1 input for Mux14
10 : Select .2 input for Mux14
11 : Select .3 input for Mux14
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
27-26 MUX13 R/W 0h Select Bits for EPWM-XBAR TRIP5 Mux13:
00 : Select .0 input for Mux13
01 : Select .1 input for Mux13
10 : Select .2 input for Mux13
11 : Select .3 input for Mux13
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
25-24 MUX12 R/W 0h Select Bits for EPWM-XBAR TRIP5 Mux12:
00 : Select .0 input for Mux12
01 : Select .1 input for Mux12
10 : Select .2 input for Mux12
11 : Select .3 input for Mux12
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
23-22 MUX11 R/W 0h Select Bits for EPWM-XBAR TRIP5 Mux11:
00 : Select .0 input for Mux11
01 : Select .1 input for Mux11
10 : Select .2 input for Mux11
11 : Select .3 input for Mux11
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
21-20 MUX10 R/W 0h Select Bits for EPWM-XBAR TRIP5 Mux10:
00 : Select .0 input for Mux10
01 : Select .1 input for Mux10
10 : Select .2 input for Mux10
11 : Select .3 input for Mux10
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

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Table 9-35. TRIP5MUX0TO15CFG Register Field Descriptions (continued)

Bit Field Type Reset Description
19-18 MUX9 R/W 0h Select Bits for EPWM-XBAR TRIP5 Mux9:
00 : Select .0 input for Mux9
01 : Select .1 input for Mux9
10 : Select .2 input for Mux9
11 : Select .3 input for Mux9
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
17-16 MUX8 R/W 0h Select Bits for EPWM-XBAR TRIP5 Mux8:
00 : Select .0 input for Mux8
01 : Select .1 input for Mux8
10 : Select .2 input for Mux8
11 : Select .3 input for Mux8
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
15-14 MUX7 R/W 0h Select Bits for EPWM-XBAR TRIP5 Mux7:
00 : Select .0 input for Mux7
01 : Select .1 input for Mux7
10 : Select .2 input for Mux7
11 : Select .3 input for Mux7
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
13-12 MUX6 R/W 0h Select Bits for EPWM-XBAR TRIP5 Mux6:
00 : Select .0 input for Mux6
01 : Select .1 input for Mux6
10 : Select .2 input for Mux6
11 : Select .3 input for Mux6
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
11-10 MUX5 R/W 0h Select Bits for EPWM-XBAR TRIP5 Mux5:
00 : Select .0 input for Mux5
01 : Select .1 input for Mux5
10 : Select .2 input for Mux5
11 : Select .3 input for Mux5
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
9-8 MUX4 R/W 0h Select Bits for EPWM-XBAR TRIP5 Mux4:
00 : Select .0 input for Mux4
01 : Select .1 input for Mux4
10 : Select .2 input for Mux4
11 : Select .3 input for Mux4
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
7-6 MUX3 R/W 0h Select Bits for EPWM-XBAR TRIP5 Mux3:
00 : Select .0 input for Mux3
01 : Select .1 input for Mux3
10 : Select .2 input for Mux3
11 : Select .3 input for Mux3
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
5-4 MUX2 R/W 0h Select Bits for EPWM-XBAR TRIP5 Mux2:
00 : Select .0 input for Mux2
01 : Select .1 input for Mux2
10 : Select .2 input for Mux2
11 : Select .3 input for Mux2
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

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Table 9-35. TRIP5MUX0TO15CFG Register Field Descriptions (continued)

Bit Field Type Reset Description
3-2 MUX1 R/W 0h Select Bits for EPWM-XBAR TRIP5 Mux1:
00 : Select .0 input for Mux1
01 : Select .1 input for Mux1
10 : Select .2 input for Mux1
11 : Select .3 input for Mux1
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
1-0 MUX0 R/W 0h Select Bits for EPWM-XBAR TRIP5 Mux0:
00 : Select .0 input for Mux0
01 : Select .1 input for Mux0
10 : Select .2 input for Mux0
11 : Select .3 input for Mux0
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

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9.3.4.4 TRIP5MUX16TO31CFG Register (Offset = 6h) [Reset = 00000000h]

TRIP5MUX16TO31CFG is shown in Figure 9-31 and described in Table 9-36.
Return to the Summary Table.
ePWM XBAR Mux Configuration for TRIP5
Figure 9-31. TRIP5MUX16TO31CFG Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MUX31 MUX30 MUX29 MUX28 MUX27 MUX26 MUX25 MUX24
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX23 MUX22 MUX21 MUX20 MUX19 MUX18 MUX17 MUX16
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 9-36. TRIP5MUX16TO31CFG Register Field Descriptions

Bit Field Type Reset Description
31-30 MUX31 R/W 0h Select Bits for EPWM-XBAR TRIP5 Mux31:
00 : Select .0 input for Mux31
01 : Select .1 input for Mux31
10 : Select .2 input for Mux31
11 : Select .3 input for Mux31
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
29-28 MUX30 R/W 0h Select Bits for EPWM-XBAR TRIP5 Mux30:
00 : Select .0 input for Mux30
01 : Select .1 input for Mux30
10 : Select .2 input for Mux30
11 : Select .3 input for Mux30
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
27-26 MUX29 R/W 0h Select Bits for EPWM-XBAR TRIP5 Mux29:
00 : Select .0 input for Mux29
01 : Select .1 input for Mux29
10 : Select .2 input for Mux29
11 : Select .3 input for Mux29
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
25-24 MUX28 R/W 0h Select Bits for EPWM-XBAR TRIP5 Mux28:
00 : Select .0 input for Mux28
01 : Select .1 input for Mux28
10 : Select .2 input for Mux28
11 : Select .3 input for Mux28
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
23-22 MUX27 R/W 0h Select Bits for EPWM-XBAR TRIP5 Mux27:
00 : Select .0 input for Mux27
01 : Select .1 input for Mux27
10 : Select .2 input for Mux27
11 : Select .3 input for Mux27
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
21-20 MUX26 R/W 0h Select Bits for EPWM-XBAR TRIP5 Mux26:
00 : Select .0 input for Mux26
01 : Select .1 input for Mux26
10 : Select .2 input for Mux26
11 : Select .3 input for Mux26
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

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Table 9-36. TRIP5MUX16TO31CFG Register Field Descriptions (continued)

Bit Field Type Reset Description
19-18 MUX25 R/W 0h Select Bits for EPWM-XBAR TRIP5 Mux25:
00 : Select .0 input for Mux25
01 : Select .1 input for Mux25
10 : Select .2 input for Mux25
11 : Select .3 input for Mux25
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
17-16 MUX24 R/W 0h Select Bits for EPWM-XBAR TRIP5 Mux24:
00 : Select .0 input for Mux24
01 : Select .1 input for Mux24
10 : Select .2 input for Mux24
11 : Select .3 input for Mux24
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
15-14 MUX23 R/W 0h Select Bits for EPWM-XBAR TRIP5 Mux23:
00 : Select .0 input for Mux23
01 : Select .1 input for Mux23
10 : Select .2 input for Mux23
11 : Select .3 input for Mux23
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
13-12 MUX22 R/W 0h Select Bits for EPWM-XBAR TRIP5 Mux22:
00 : Select .0 input for Mux22
01 : Select .1 input for Mux22
10 : Select .2 input for Mux22
11 : Select .3 input for Mux22
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
11-10 MUX21 R/W 0h Select Bits for EPWM-XBAR TRIP5 Mux21:
00 : Select .0 input for Mux21
01 : Select .1 input for Mux21
10 : Select .2 input for Mux21
11 : Select .3 input for Mux21
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
9-8 MUX20 R/W 0h Select Bits for EPWM-XBAR TRIP5 Mux20:
00 : Select .0 input for Mux20
01 : Select .1 input for Mux20
10 : Select .2 input for Mux20
11 : Select .3 input for Mux20
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
7-6 MUX19 R/W 0h Select Bits for EPWM-XBAR TRIP5 Mux19:
00 : Select .0 input for Mux19
01 : Select .1 input for Mux19
10 : Select .2 input for Mux19
11 : Select .3 input for Mux19
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
5-4 MUX18 R/W 0h Select Bits for EPWM-XBAR TRIP5 Mux18:
00 : Select .0 input for Mux18
01 : Select .1 input for Mux18
10 : Select .2 input for Mux18
11 : Select .3 input for Mux18
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

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Table 9-36. TRIP5MUX16TO31CFG Register Field Descriptions (continued)

Bit Field Type Reset Description
3-2 MUX17 R/W 0h Select Bits for EPWM-XBAR TRIP5 Mux17:
00 : Select .0 input for Mux17
01 : Select .1 input for Mux17
10 : Select .2 input for Mux17
11 : Select .3 input for Mux17
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
1-0 MUX16 R/W 0h Select Bits for EPWM-XBAR TRIP5 Mux16:
00 : Select .0 input for Mux16
01 : Select .1 input for Mux16
10 : Select .2 input for Mux16
11 : Select .3 input for Mux16
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

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9.3.4.5 TRIP7MUX0TO15CFG Register (Offset = 8h) [Reset = 00000000h]

TRIP7MUX0TO15CFG is shown in Figure 9-32 and described in Table 9-37.
Return to the Summary Table.
ePWM XBAR Mux Configuration for TRIP7
Figure 9-32. TRIP7MUX0TO15CFG Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MUX15 MUX14 MUX13 MUX12 MUX11 MUX10 MUX9 MUX8
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX7 MUX6 MUX5 MUX4 MUX3 MUX2 MUX1 MUX0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 9-37. TRIP7MUX0TO15CFG Register Field Descriptions

Bit Field Type Reset Description
31-30 MUX15 R/W 0h Select Bits for EPWM-XBAR TRIP7 Mux15:
00 : Select .0 input for Mux15
01 : Select .1 input for Mux15
10 : Select .2 input for Mux15
11 : Select .3 input for Mux15
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
29-28 MUX14 R/W 0h Select Bits for EPWM-XBAR TRIP7 Mux14:
00 : Select .0 input for Mux14
01 : Select .1 input for Mux14
10 : Select .2 input for Mux14
11 : Select .3 input for Mux14
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
27-26 MUX13 R/W 0h Select Bits for EPWM-XBAR TRIP7 Mux13:
00 : Select .0 input for Mux13
01 : Select .1 input for Mux13
10 : Select .2 input for Mux13
11 : Select .3 input for Mux13
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
25-24 MUX12 R/W 0h Select Bits for EPWM-XBAR TRIP7 Mux12:
00 : Select .0 input for Mux12
01 : Select .1 input for Mux12
10 : Select .2 input for Mux12
11 : Select .3 input for Mux12
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
23-22 MUX11 R/W 0h Select Bits for EPWM-XBAR TRIP7 Mux11:
00 : Select .0 input for Mux11
01 : Select .1 input for Mux11
10 : Select .2 input for Mux11
11 : Select .3 input for Mux11
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
21-20 MUX10 R/W 0h Select Bits for EPWM-XBAR TRIP7 Mux10:
00 : Select .0 input for Mux10
01 : Select .1 input for Mux10
10 : Select .2 input for Mux10
11 : Select .3 input for Mux10
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

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Table 9-37. TRIP7MUX0TO15CFG Register Field Descriptions (continued)

Bit Field Type Reset Description
19-18 MUX9 R/W 0h Select Bits for EPWM-XBAR TRIP7 Mux9:
00 : Select .0 input for Mux9
01 : Select .1 input for Mux9
10 : Select .2 input for Mux9
11 : Select .3 input for Mux9
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
17-16 MUX8 R/W 0h Select Bits for EPWM-XBAR TRIP7 Mux8:
00 : Select .0 input for Mux8
01 : Select .1 input for Mux8
10 : Select .2 input for Mux8
11 : Select .3 input for Mux8
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
15-14 MUX7 R/W 0h Select Bits for EPWM-XBAR TRIP7 Mux7:
00 : Select .0 input for Mux7
01 : Select .1 input for Mux7
10 : Select .2 input for Mux7
11 : Select .3 input for Mux7
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
13-12 MUX6 R/W 0h Select Bits for EPWM-XBAR TRIP7 Mux6:
00 : Select .0 input for Mux6
01 : Select .1 input for Mux6
10 : Select .2 input for Mux6
11 : Select .3 input for Mux6
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
11-10 MUX5 R/W 0h Select Bits for EPWM-XBAR TRIP7 Mux5:
00 : Select .0 input for Mux5
01 : Select .1 input for Mux5
10 : Select .2 input for Mux5
11 : Select .3 input for Mux5
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
9-8 MUX4 R/W 0h Select Bits for EPWM-XBAR TRIP7 Mux4:
00 : Select .0 input for Mux4
01 : Select .1 input for Mux4
10 : Select .2 input for Mux4
11 : Select .3 input for Mux4
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
7-6 MUX3 R/W 0h Select Bits for EPWM-XBAR TRIP7 Mux3:
00 : Select .0 input for Mux3
01 : Select .1 input for Mux3
10 : Select .2 input for Mux3
11 : Select .3 input for Mux3
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
5-4 MUX2 R/W 0h Select Bits for EPWM-XBAR TRIP7 Mux2:
00 : Select .0 input for Mux2
01 : Select .1 input for Mux2
10 : Select .2 input for Mux2
11 : Select .3 input for Mux2
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

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Table 9-37. TRIP7MUX0TO15CFG Register Field Descriptions (continued)

Bit Field Type Reset Description
3-2 MUX1 R/W 0h Select Bits for EPWM-XBAR TRIP7 Mux1:
00 : Select .0 input for Mux1
01 : Select .1 input for Mux1
10 : Select .2 input for Mux1
11 : Select .3 input for Mux1
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
1-0 MUX0 R/W 0h Select Bits for EPWM-XBAR TRIP7 Mux0:
00 : Select .0 input for Mux0
01 : Select .1 input for Mux0
10 : Select .2 input for Mux0
11 : Select .3 input for Mux0
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

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9.3.4.6 TRIP7MUX16TO31CFG Register (Offset = Ah) [Reset = 00000000h]

TRIP7MUX16TO31CFG is shown in Figure 9-33 and described in Table 9-38.
Return to the Summary Table.
ePWM XBAR Mux Configuration for TRIP7
Figure 9-33. TRIP7MUX16TO31CFG Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MUX31 MUX30 MUX29 MUX28 MUX27 MUX26 MUX25 MUX24
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX23 MUX22 MUX21 MUX20 MUX19 MUX18 MUX17 MUX16
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 9-38. TRIP7MUX16TO31CFG Register Field Descriptions

Bit Field Type Reset Description
31-30 MUX31 R/W 0h Select Bits for EPWM-XBAR TRIP7 Mux31:
00 : Select .0 input for Mux31
01 : Select .1 input for Mux31
10 : Select .2 input for Mux31
11 : Select .3 input for Mux31
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
29-28 MUX30 R/W 0h Select Bits for EPWM-XBAR TRIP7 Mux30:
00 : Select .0 input for Mux30
01 : Select .1 input for Mux30
10 : Select .2 input for Mux30
11 : Select .3 input for Mux30
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
27-26 MUX29 R/W 0h Select Bits for EPWM-XBAR TRIP7 Mux29:
00 : Select .0 input for Mux29
01 : Select .1 input for Mux29
10 : Select .2 input for Mux29
11 : Select .3 input for Mux29
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
25-24 MUX28 R/W 0h Select Bits for EPWM-XBAR TRIP7 Mux28:
00 : Select .0 input for Mux28
01 : Select .1 input for Mux28
10 : Select .2 input for Mux28
11 : Select .3 input for Mux28
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
23-22 MUX27 R/W 0h Select Bits for EPWM-XBAR TRIP7 Mux27:
00 : Select .0 input for Mux27
01 : Select .1 input for Mux27
10 : Select .2 input for Mux27
11 : Select .3 input for Mux27
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
21-20 MUX26 R/W 0h Select Bits for EPWM-XBAR TRIP7 Mux26:
00 : Select .0 input for Mux26
01 : Select .1 input for Mux26
10 : Select .2 input for Mux26
11 : Select .3 input for Mux26
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

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Table 9-38. TRIP7MUX16TO31CFG Register Field Descriptions (continued)

Bit Field Type Reset Description
19-18 MUX25 R/W 0h Select Bits for EPWM-XBAR TRIP7 Mux25:
00 : Select .0 input for Mux25
01 : Select .1 input for Mux25
10 : Select .2 input for Mux25
11 : Select .3 input for Mux25
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
17-16 MUX24 R/W 0h Select Bits for EPWM-XBAR TRIP7 Mux24:
00 : Select .0 input for Mux24
01 : Select .1 input for Mux24
10 : Select .2 input for Mux24
11 : Select .3 input for Mux24
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
15-14 MUX23 R/W 0h Select Bits for EPWM-XBAR TRIP7 Mux23:
00 : Select .0 input for Mux23
01 : Select .1 input for Mux23
10 : Select .2 input for Mux23
11 : Select .3 input for Mux23
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
13-12 MUX22 R/W 0h Select Bits for EPWM-XBAR TRIP7 Mux22:
00 : Select .0 input for Mux22
01 : Select .1 input for Mux22
10 : Select .2 input for Mux22
11 : Select .3 input for Mux22
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
11-10 MUX21 R/W 0h Select Bits for EPWM-XBAR TRIP7 Mux21:
00 : Select .0 input for Mux21
01 : Select .1 input for Mux21
10 : Select .2 input for Mux21
11 : Select .3 input for Mux21
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
9-8 MUX20 R/W 0h Select Bits for EPWM-XBAR TRIP7 Mux20:
00 : Select .0 input for Mux20
01 : Select .1 input for Mux20
10 : Select .2 input for Mux20
11 : Select .3 input for Mux20
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
7-6 MUX19 R/W 0h Select Bits for EPWM-XBAR TRIP7 Mux19:
00 : Select .0 input for Mux19
01 : Select .1 input for Mux19
10 : Select .2 input for Mux19
11 : Select .3 input for Mux19
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
5-4 MUX18 R/W 0h Select Bits for EPWM-XBAR TRIP7 Mux18:
00 : Select .0 input for Mux18
01 : Select .1 input for Mux18
10 : Select .2 input for Mux18
11 : Select .3 input for Mux18
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

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Table 9-38. TRIP7MUX16TO31CFG Register Field Descriptions (continued)

Bit Field Type Reset Description
3-2 MUX17 R/W 0h Select Bits for EPWM-XBAR TRIP7 Mux17:
00 : Select .0 input for Mux17
01 : Select .1 input for Mux17
10 : Select .2 input for Mux17
11 : Select .3 input for Mux17
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
1-0 MUX16 R/W 0h Select Bits for EPWM-XBAR TRIP7 Mux16:
00 : Select .0 input for Mux16
01 : Select .1 input for Mux16
10 : Select .2 input for Mux16
11 : Select .3 input for Mux16
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

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9.3.4.7 TRIP8MUX0TO15CFG Register (Offset = Ch) [Reset = 00000000h]

TRIP8MUX0TO15CFG is shown in Figure 9-34 and described in Table 9-39.
Return to the Summary Table.
ePWM XBAR Mux Configuration for TRIP8
Figure 9-34. TRIP8MUX0TO15CFG Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MUX15 MUX14 MUX13 MUX12 MUX11 MUX10 MUX9 MUX8
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX7 MUX6 MUX5 MUX4 MUX3 MUX2 MUX1 MUX0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 9-39. TRIP8MUX0TO15CFG Register Field Descriptions

Bit Field Type Reset Description
31-30 MUX15 R/W 0h Select Bits for EPWM-XBAR TRIP8 Mux15:
00 : Select .0 input for Mux15
01 : Select .1 input for Mux15
10 : Select .2 input for Mux15
11 : Select .3 input for Mux15
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
29-28 MUX14 R/W 0h Select Bits for EPWM-XBAR TRIP8 Mux14:
00 : Select .0 input for Mux14
01 : Select .1 input for Mux14
10 : Select .2 input for Mux14
11 : Select .3 input for Mux14
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
27-26 MUX13 R/W 0h Select Bits for EPWM-XBAR TRIP8 Mux13:
00 : Select .0 input for Mux13
01 : Select .1 input for Mux13
10 : Select .2 input for Mux13
11 : Select .3 input for Mux13
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
25-24 MUX12 R/W 0h Select Bits for EPWM-XBAR TRIP8 Mux12:
00 : Select .0 input for Mux12
01 : Select .1 input for Mux12
10 : Select .2 input for Mux12
11 : Select .3 input for Mux12
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
23-22 MUX11 R/W 0h Select Bits for EPWM-XBAR TRIP8 Mux11:
00 : Select .0 input for Mux11
01 : Select .1 input for Mux11
10 : Select .2 input for Mux11
11 : Select .3 input for Mux11
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
21-20 MUX10 R/W 0h Select Bits for EPWM-XBAR TRIP8 Mux10:
00 : Select .0 input for Mux10
01 : Select .1 input for Mux10
10 : Select .2 input for Mux10
11 : Select .3 input for Mux10
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

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Table 9-39. TRIP8MUX0TO15CFG Register Field Descriptions (continued)

Bit Field Type Reset Description
19-18 MUX9 R/W 0h Select Bits for EPWM-XBAR TRIP8 Mux9:
00 : Select .0 input for Mux9
01 : Select .1 input for Mux9
10 : Select .2 input for Mux9
11 : Select .3 input for Mux9
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
17-16 MUX8 R/W 0h Select Bits for EPWM-XBAR TRIP8 Mux8:
00 : Select .0 input for Mux8
01 : Select .1 input for Mux8
10 : Select .2 input for Mux8
11 : Select .3 input for Mux8
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
15-14 MUX7 R/W 0h Select Bits for EPWM-XBAR TRIP8 Mux7:
00 : Select .0 input for Mux7
01 : Select .1 input for Mux7
10 : Select .2 input for Mux7
11 : Select .3 input for Mux7
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
13-12 MUX6 R/W 0h Select Bits for EPWM-XBAR TRIP8 Mux6:
00 : Select .0 input for Mux6
01 : Select .1 input for Mux6
10 : Select .2 input for Mux6
11 : Select .3 input for Mux6
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
11-10 MUX5 R/W 0h Select Bits for EPWM-XBAR TRIP8 Mux5:
00 : Select .0 input for Mux5
01 : Select .1 input for Mux5
10 : Select .2 input for Mux5
11 : Select .3 input for Mux5
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
9-8 MUX4 R/W 0h Select Bits for EPWM-XBAR TRIP8 Mux4:
00 : Select .0 input for Mux4
01 : Select .1 input for Mux4
10 : Select .2 input for Mux4
11 : Select .3 input for Mux4
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
7-6 MUX3 R/W 0h Select Bits for EPWM-XBAR TRIP8 Mux3:
00 : Select .0 input for Mux3
01 : Select .1 input for Mux3
10 : Select .2 input for Mux3
11 : Select .3 input for Mux3
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
5-4 MUX2 R/W 0h Select Bits for EPWM-XBAR TRIP8 Mux2:
00 : Select .0 input for Mux2
01 : Select .1 input for Mux2
10 : Select .2 input for Mux2
11 : Select .3 input for Mux2
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

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Table 9-39. TRIP8MUX0TO15CFG Register Field Descriptions (continued)

Bit Field Type Reset Description
3-2 MUX1 R/W 0h Select Bits for EPWM-XBAR TRIP8 Mux1:
00 : Select .0 input for Mux1
01 : Select .1 input for Mux1
10 : Select .2 input for Mux1
11 : Select .3 input for Mux1
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
1-0 MUX0 R/W 0h Select Bits for EPWM-XBAR TRIP8 Mux0:
00 : Select .0 input for Mux0
01 : Select .1 input for Mux0
10 : Select .2 input for Mux0
11 : Select .3 input for Mux0
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

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9.3.4.8 TRIP8MUX16TO31CFG Register (Offset = Eh) [Reset = 00000000h]

TRIP8MUX16TO31CFG is shown in Figure 9-35 and described in Table 9-40.
Return to the Summary Table.
ePWM XBAR Mux Configuration for TRIP8
Figure 9-35. TRIP8MUX16TO31CFG Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MUX31 MUX30 MUX29 MUX28 MUX27 MUX26 MUX25 MUX24
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX23 MUX22 MUX21 MUX20 MUX19 MUX18 MUX17 MUX16
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 9-40. TRIP8MUX16TO31CFG Register Field Descriptions

Bit Field Type Reset Description
31-30 MUX31 R/W 0h Select Bits for EPWM-XBAR TRIP8 Mux31:
00 : Select .0 input for Mux31
01 : Select .1 input for Mux31
10 : Select .2 input for Mux31
11 : Select .3 input for Mux31
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
29-28 MUX30 R/W 0h Select Bits for EPWM-XBAR TRIP8 Mux30:
00 : Select .0 input for Mux30
01 : Select .1 input for Mux30
10 : Select .2 input for Mux30
11 : Select .3 input for Mux30
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
27-26 MUX29 R/W 0h Select Bits for EPWM-XBAR TRIP8 Mux29:
00 : Select .0 input for Mux29
01 : Select .1 input for Mux29
10 : Select .2 input for Mux29
11 : Select .3 input for Mux29
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
25-24 MUX28 R/W 0h Select Bits for EPWM-XBAR TRIP8 Mux28:
00 : Select .0 input for Mux28
01 : Select .1 input for Mux28
10 : Select .2 input for Mux28
11 : Select .3 input for Mux28
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
23-22 MUX27 R/W 0h Select Bits for EPWM-XBAR TRIP8 Mux27:
00 : Select .0 input for Mux27
01 : Select .1 input for Mux27
10 : Select .2 input for Mux27
11 : Select .3 input for Mux27
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
21-20 MUX26 R/W 0h Select Bits for EPWM-XBAR TRIP8 Mux26:
00 : Select .0 input for Mux26
01 : Select .1 input for Mux26
10 : Select .2 input for Mux26
11 : Select .3 input for Mux26
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

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Table 9-40. TRIP8MUX16TO31CFG Register Field Descriptions (continued)

Bit Field Type Reset Description
19-18 MUX25 R/W 0h Select Bits for EPWM-XBAR TRIP8 Mux25:
00 : Select .0 input for Mux25
01 : Select .1 input for Mux25
10 : Select .2 input for Mux25
11 : Select .3 input for Mux25
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
17-16 MUX24 R/W 0h Select Bits for EPWM-XBAR TRIP8 Mux24:
00 : Select .0 input for Mux24
01 : Select .1 input for Mux24
10 : Select .2 input for Mux24
11 : Select .3 input for Mux24
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
15-14 MUX23 R/W 0h Select Bits for EPWM-XBAR TRIP8 Mux23:
00 : Select .0 input for Mux23
01 : Select .1 input for Mux23
10 : Select .2 input for Mux23
11 : Select .3 input for Mux23
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
13-12 MUX22 R/W 0h Select Bits for EPWM-XBAR TRIP8 Mux22:
00 : Select .0 input for Mux22
01 : Select .1 input for Mux22
10 : Select .2 input for Mux22
11 : Select .3 input for Mux22
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
11-10 MUX21 R/W 0h Select Bits for EPWM-XBAR TRIP8 Mux21:
00 : Select .0 input for Mux21
01 : Select .1 input for Mux21
10 : Select .2 input for Mux21
11 : Select .3 input for Mux21
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
9-8 MUX20 R/W 0h Select Bits for EPWM-XBAR TRIP8 Mux20:
00 : Select .0 input for Mux20
01 : Select .1 input for Mux20
10 : Select .2 input for Mux20
11 : Select .3 input for Mux20
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
7-6 MUX19 R/W 0h Select Bits for EPWM-XBAR TRIP8 Mux19:
00 : Select .0 input for Mux19
01 : Select .1 input for Mux19
10 : Select .2 input for Mux19
11 : Select .3 input for Mux19
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
5-4 MUX18 R/W 0h Select Bits for EPWM-XBAR TRIP8 Mux18:
00 : Select .0 input for Mux18
01 : Select .1 input for Mux18
10 : Select .2 input for Mux18
11 : Select .3 input for Mux18
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

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Table 9-40. TRIP8MUX16TO31CFG Register Field Descriptions (continued)

Bit Field Type Reset Description
3-2 MUX17 R/W 0h Select Bits for EPWM-XBAR TRIP8 Mux17:
00 : Select .0 input for Mux17
01 : Select .1 input for Mux17
10 : Select .2 input for Mux17
11 : Select .3 input for Mux17
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
1-0 MUX16 R/W 0h Select Bits for EPWM-XBAR TRIP8 Mux16:
00 : Select .0 input for Mux16
01 : Select .1 input for Mux16
10 : Select .2 input for Mux16
11 : Select .3 input for Mux16
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

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9.3.4.9 TRIP9MUX0TO15CFG Register (Offset = 10h) [Reset = 00000000h]

TRIP9MUX0TO15CFG is shown in Figure 9-36 and described in Table 9-41.
Return to the Summary Table.
ePWM XBAR Mux Configuration for TRIP9
Figure 9-36. TRIP9MUX0TO15CFG Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MUX15 MUX14 MUX13 MUX12 MUX11 MUX10 MUX9 MUX8
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX7 MUX6 MUX5 MUX4 MUX3 MUX2 MUX1 MUX0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 9-41. TRIP9MUX0TO15CFG Register Field Descriptions

Bit Field Type Reset Description
31-30 MUX15 R/W 0h Select Bits for EPWM-XBAR TRIP9 Mux15:
00 : Select .0 input for Mux15
01 : Select .1 input for Mux15
10 : Select .2 input for Mux15
11 : Select .3 input for Mux15
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
29-28 MUX14 R/W 0h Select Bits for EPWM-XBAR TRIP9 Mux14:
00 : Select .0 input for Mux14
01 : Select .1 input for Mux14
10 : Select .2 input for Mux14
11 : Select .3 input for Mux14
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
27-26 MUX13 R/W 0h Select Bits for EPWM-XBAR TRIP9 Mux13:
00 : Select .0 input for Mux13
01 : Select .1 input for Mux13
10 : Select .2 input for Mux13
11 : Select .3 input for Mux13
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
25-24 MUX12 R/W 0h Select Bits for EPWM-XBAR TRIP9 Mux12:
00 : Select .0 input for Mux12
01 : Select .1 input for Mux12
10 : Select .2 input for Mux12
11 : Select .3 input for Mux12
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
23-22 MUX11 R/W 0h Select Bits for EPWM-XBAR TRIP9 Mux11:
00 : Select .0 input for Mux11
01 : Select .1 input for Mux11
10 : Select .2 input for Mux11
11 : Select .3 input for Mux11
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
21-20 MUX10 R/W 0h Select Bits for EPWM-XBAR TRIP9 Mux10:
00 : Select .0 input for Mux10
01 : Select .1 input for Mux10
10 : Select .2 input for Mux10
11 : Select .3 input for Mux10
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

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Table 9-41. TRIP9MUX0TO15CFG Register Field Descriptions (continued)

Bit Field Type Reset Description
19-18 MUX9 R/W 0h Select Bits for EPWM-XBAR TRIP9 Mux9:
00 : Select .0 input for Mux9
01 : Select .1 input for Mux9
10 : Select .2 input for Mux9
11 : Select .3 input for Mux9
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
17-16 MUX8 R/W 0h Select Bits for EPWM-XBAR TRIP9 Mux8:
00 : Select .0 input for Mux8
01 : Select .1 input for Mux8
10 : Select .2 input for Mux8
11 : Select .3 input for Mux8
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
15-14 MUX7 R/W 0h Select Bits for EPWM-XBAR TRIP9 Mux7:
00 : Select .0 input for Mux7
01 : Select .1 input for Mux7
10 : Select .2 input for Mux7
11 : Select .3 input for Mux7
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
13-12 MUX6 R/W 0h Select Bits for EPWM-XBAR TRIP9 Mux6:
00 : Select .0 input for Mux6
01 : Select .1 input for Mux6
10 : Select .2 input for Mux6
11 : Select .3 input for Mux6
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
11-10 MUX5 R/W 0h Select Bits for EPWM-XBAR TRIP9 Mux5:
00 : Select .0 input for Mux5
01 : Select .1 input for Mux5
10 : Select .2 input for Mux5
11 : Select .3 input for Mux5
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
9-8 MUX4 R/W 0h Select Bits for EPWM-XBAR TRIP9 Mux4:
00 : Select .0 input for Mux4
01 : Select .1 input for Mux4
10 : Select .2 input for Mux4
11 : Select .3 input for Mux4
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
7-6 MUX3 R/W 0h Select Bits for EPWM-XBAR TRIP9 Mux3:
00 : Select .0 input for Mux3
01 : Select .1 input for Mux3
10 : Select .2 input for Mux3
11 : Select .3 input for Mux3
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
5-4 MUX2 R/W 0h Select Bits for EPWM-XBAR TRIP9 Mux2:
00 : Select .0 input for Mux2
01 : Select .1 input for Mux2
10 : Select .2 input for Mux2
11 : Select .3 input for Mux2
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

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Table 9-41. TRIP9MUX0TO15CFG Register Field Descriptions (continued)

Bit Field Type Reset Description
3-2 MUX1 R/W 0h Select Bits for EPWM-XBAR TRIP9 Mux1:
00 : Select .0 input for Mux1
01 : Select .1 input for Mux1
10 : Select .2 input for Mux1
11 : Select .3 input for Mux1
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
1-0 MUX0 R/W 0h Select Bits for EPWM-XBAR TRIP9 Mux0:
00 : Select .0 input for Mux0
01 : Select .1 input for Mux0
10 : Select .2 input for Mux0
11 : Select .3 input for Mux0
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

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9.3.4.10 TRIP9MUX16TO31CFG Register (Offset = 12h) [Reset = 00000000h]

TRIP9MUX16TO31CFG is shown in Figure 9-37 and described in Table 9-42.
Return to the Summary Table.
ePWM XBAR Mux Configuration for TRIP9
Figure 9-37. TRIP9MUX16TO31CFG Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MUX31 MUX30 MUX29 MUX28 MUX27 MUX26 MUX25 MUX24
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX23 MUX22 MUX21 MUX20 MUX19 MUX18 MUX17 MUX16
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 9-42. TRIP9MUX16TO31CFG Register Field Descriptions

Bit Field Type Reset Description
31-30 MUX31 R/W 0h Select Bits for EPWM-XBAR TRIP9 Mux31:
00 : Select .0 input for Mux31
01 : Select .1 input for Mux31
10 : Select .2 input for Mux31
11 : Select .3 input for Mux31
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
29-28 MUX30 R/W 0h Select Bits for EPWM-XBAR TRIP9 Mux30:
00 : Select .0 input for Mux30
01 : Select .1 input for Mux30
10 : Select .2 input for Mux30
11 : Select .3 input for Mux30
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
27-26 MUX29 R/W 0h Select Bits for EPWM-XBAR TRIP9 Mux29:
00 : Select .0 input for Mux29
01 : Select .1 input for Mux29
10 : Select .2 input for Mux29
11 : Select .3 input for Mux29
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
25-24 MUX28 R/W 0h Select Bits for EPWM-XBAR TRIP9 Mux28:
00 : Select .0 input for Mux28
01 : Select .1 input for Mux28
10 : Select .2 input for Mux28
11 : Select .3 input for Mux28
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
23-22 MUX27 R/W 0h Select Bits for EPWM-XBAR TRIP9 Mux27:
00 : Select .0 input for Mux27
01 : Select .1 input for Mux27
10 : Select .2 input for Mux27
11 : Select .3 input for Mux27
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
21-20 MUX26 R/W 0h Select Bits for EPWM-XBAR TRIP9 Mux26:
00 : Select .0 input for Mux26
01 : Select .1 input for Mux26
10 : Select .2 input for Mux26
11 : Select .3 input for Mux26
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

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Table 9-42. TRIP9MUX16TO31CFG Register Field Descriptions (continued)

Bit Field Type Reset Description
19-18 MUX25 R/W 0h Select Bits for EPWM-XBAR TRIP9 Mux25:
00 : Select .0 input for Mux25
01 : Select .1 input for Mux25
10 : Select .2 input for Mux25
11 : Select .3 input for Mux25
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
17-16 MUX24 R/W 0h Select Bits for EPWM-XBAR TRIP9 Mux24:
00 : Select .0 input for Mux24
01 : Select .1 input for Mux24
10 : Select .2 input for Mux24
11 : Select .3 input for Mux24
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
15-14 MUX23 R/W 0h Select Bits for EPWM-XBAR TRIP9 Mux23:
00 : Select .0 input for Mux23
01 : Select .1 input for Mux23
10 : Select .2 input for Mux23
11 : Select .3 input for Mux23
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
13-12 MUX22 R/W 0h Select Bits for EPWM-XBAR TRIP9 Mux22:
00 : Select .0 input for Mux22
01 : Select .1 input for Mux22
10 : Select .2 input for Mux22
11 : Select .3 input for Mux22
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
11-10 MUX21 R/W 0h Select Bits for EPWM-XBAR TRIP9 Mux21:
00 : Select .0 input for Mux21
01 : Select .1 input for Mux21
10 : Select .2 input for Mux21
11 : Select .3 input for Mux21
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
9-8 MUX20 R/W 0h Select Bits for EPWM-XBAR TRIP9 Mux20:
00 : Select .0 input for Mux20
01 : Select .1 input for Mux20
10 : Select .2 input for Mux20
11 : Select .3 input for Mux20
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
7-6 MUX19 R/W 0h Select Bits for EPWM-XBAR TRIP9 Mux19:
00 : Select .0 input for Mux19
01 : Select .1 input for Mux19
10 : Select .2 input for Mux19
11 : Select .3 input for Mux19
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
5-4 MUX18 R/W 0h Select Bits for EPWM-XBAR TRIP9 Mux18:
00 : Select .0 input for Mux18
01 : Select .1 input for Mux18
10 : Select .2 input for Mux18
11 : Select .3 input for Mux18
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1302 TMS320F2837xD Dual-Core Real-Time Microcontrollers SPRUHM8K – DECEMBER 2013 – REVISED MAY 2024
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Table 9-42. TRIP9MUX16TO31CFG Register Field Descriptions (continued)

Bit Field Type Reset Description
3-2 MUX17 R/W 0h Select Bits for EPWM-XBAR TRIP9 Mux17:
00 : Select .0 input for Mux17
01 : Select .1 input for Mux17
10 : Select .2 input for Mux17
11 : Select .3 input for Mux17
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
1-0 MUX16 R/W 0h Select Bits for EPWM-XBAR TRIP9 Mux16:
00 : Select .0 input for Mux16
01 : Select .1 input for Mux16
10 : Select .2 input for Mux16
11 : Select .3 input for Mux16
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

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9.3.4.11 TRIP10MUX0TO15CFG Register (Offset = 14h) [Reset = 00000000h]

TRIP10MUX0TO15CFG is shown in Figure 9-38 and described in Table 9-43.
Return to the Summary Table.
ePWM XBAR Mux Configuration for TRIP10
Figure 9-38. TRIP10MUX0TO15CFG Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MUX15 MUX14 MUX13 MUX12 MUX11 MUX10 MUX9 MUX8
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX7 MUX6 MUX5 MUX4 MUX3 MUX2 MUX1 MUX0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 9-43. TRIP10MUX0TO15CFG Register Field Descriptions

Bit Field Type Reset Description
31-30 MUX15 R/W 0h Select Bits for EPWM-XBAR TRIP10 Mux15:
00 : Select .0 input for Mux15
01 : Select .1 input for Mux15
10 : Select .2 input for Mux15
11 : Select .3 input for Mux15
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
29-28 MUX14 R/W 0h Select Bits for EPWM-XBAR TRIP10 Mux14:
00 : Select .0 input for Mux14
01 : Select .1 input for Mux14
10 : Select .2 input for Mux14
11 : Select .3 input for Mux14
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
27-26 MUX13 R/W 0h Select Bits for EPWM-XBAR TRIP10 Mux13:
00 : Select .0 input for Mux13
01 : Select .1 input for Mux13
10 : Select .2 input for Mux13
11 : Select .3 input for Mux13
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
25-24 MUX12 R/W 0h Select Bits for EPWM-XBAR TRIP10 Mux12:
00 : Select .0 input for Mux12
01 : Select .1 input for Mux12
10 : Select .2 input for Mux12
11 : Select .3 input for Mux12
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
23-22 MUX11 R/W 0h Select Bits for EPWM-XBAR TRIP10 Mux11:
00 : Select .0 input for Mux11
01 : Select .1 input for Mux11
10 : Select .2 input for Mux11
11 : Select .3 input for Mux11
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
21-20 MUX10 R/W 0h Select Bits for EPWM-XBAR TRIP10 Mux10:
00 : Select .0 input for Mux10
01 : Select .1 input for Mux10
10 : Select .2 input for Mux10
11 : Select .3 input for Mux10
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1304 TMS320F2837xD Dual-Core Real-Time Microcontrollers SPRUHM8K – DECEMBER 2013 – REVISED MAY 2024
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Table 9-43. TRIP10MUX0TO15CFG Register Field Descriptions (continued)

Bit Field Type Reset Description
19-18 MUX9 R/W 0h Select Bits for EPWM-XBAR TRIP10 Mux9:
00 : Select .0 input for Mux9
01 : Select .1 input for Mux9
10 : Select .2 input for Mux9
11 : Select .3 input for Mux9
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
17-16 MUX8 R/W 0h Select Bits for EPWM-XBAR TRIP10 Mux8:
00 : Select .0 input for Mux8
01 : Select .1 input for Mux8
10 : Select .2 input for Mux8
11 : Select .3 input for Mux8
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
15-14 MUX7 R/W 0h Select Bits for EPWM-XBAR TRIP10 Mux7:
00 : Select .0 input for Mux7
01 : Select .1 input for Mux7
10 : Select .2 input for Mux7
11 : Select .3 input for Mux7
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
13-12 MUX6 R/W 0h Select Bits for EPWM-XBAR TRIP10 Mux6:
00 : Select .0 input for Mux6
01 : Select .1 input for Mux6
10 : Select .2 input for Mux6
11 : Select .3 input for Mux6
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
11-10 MUX5 R/W 0h Select Bits for EPWM-XBAR TRIP10 Mux5:
00 : Select .0 input for Mux5
01 : Select .1 input for Mux5
10 : Select .2 input for Mux5
11 : Select .3 input for Mux5
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
9-8 MUX4 R/W 0h Select Bits for EPWM-XBAR TRIP10 Mux4:
00 : Select .0 input for Mux4
01 : Select .1 input for Mux4
10 : Select .2 input for Mux4
11 : Select .3 input for Mux4
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
7-6 MUX3 R/W 0h Select Bits for EPWM-XBAR TRIP10 Mux3:
00 : Select .0 input for Mux3
01 : Select .1 input for Mux3
10 : Select .2 input for Mux3
11 : Select .3 input for Mux3
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
5-4 MUX2 R/W 0h Select Bits for EPWM-XBAR TRIP10 Mux2:
00 : Select .0 input for Mux2
01 : Select .1 input for Mux2
10 : Select .2 input for Mux2
11 : Select .3 input for Mux2
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8K – DECEMBER 2