Von Neumann Computer - Term 2 - Grade 9 Edexcel - Computer Science

A model of computer which processes program instructions and data which are stored in the same memory.

Stored Prgram Concept

Program instructions are stored in momory along with the data it needs which are fetched in a sequence by the
CPU.

Components of a Von Neumann Computer

* CPU - Central Processing Unit

* Main memory - The RAM holds the program instructions and the data
* Input / Output devices - Used to supply the data and to show the results produced by the CPU.
* Bus - Wires which connects the components

Central Processing Unit (CPU)

It handles the processing of program instructions and data.

Components of the CPU

1. Arithmetic and Logic Unit(ALU) - Performs the arithmetic calculations and the logical operations.

2. Control Unit - Organises all the operations of the parts in a computer. It sends the necessary control
signals to every part involved in the processing and coordinates with each other. Also fetches each instruction
stored in the memory in a sequence and decodes them to the processor.

3. Registers - These are fast access memory locations within the CPU to help in the Fetch - Decode - Execute
cycle by storing memory addresses, program instructions and data.

Examples :

* Program Counter(PC) - Holds the memory address of the instruction which has to be fetched next.

* Memory Address Register(MAR) - Holds the address of the instruction which has to be processed
next, which is a copy of the address held in PC.

* Memory Data Register(MDR) - Holds the contents(instruction) of the address held in MAR.

* Current Instruction Register(CIR) - Holds the instruction which is currently being executed.
Which is also a copy of the content held in MDR.

* Accumulator(ACC) - It holds the results calculated by the ALU. All data which are input or output
to an from the CPU passes through Accumulator.

4. Bus - A communication channel that connects all the devices with the CPU and all its parts.
There are three types of bus :

1. Address bus - Carries memory address from CPU to the memory to identify a memory location. It
is unidirectional.

2. Data bus - Carries data value that has to be read from or written to the memory. It is bidirectional.

3. Control bus - Carries signals that determine when and where to write data or read data from
memory. It is bidirectional.
NOTE : Buswidth - The number of connections which are represented in binary. So greater the connections
means larger the number of values can be communicated to makes the data transfer faster.
(If the buswidth is using 8 bits means 28 - 256 possible addresses which store values can be comminicated)

5. Clock - It is an electronic device inside the CPU that ticks at regular time intervals and is used to
synchronise(the speed at which each component works) the activites of all the parts within the CPU. It is
measured in Hertz to understand how many millions of instructions can be processed per second by the CPU.

Main Memory(Primary Memory)

Is divided into :

1. RAM(Random Access Memory) -

* Which is the volatile part of the main memory(data held in it will be lost when the
computer is switched off).

* It stores the currently running part of the operating system, currently running application
programs and currently used data.

2. ROM(Read Only Memory) -

* Which is the non volatile part of the main memory(data held in it will not be lost when the
computer is switched off).

* It stores the firmware, which is the BIOS(Basic Input Output System) or now called as
UEFI(Unified Extensible Firmware Interface). It initialises the hardware components when the
computer is swirtched on and loads the operating system.

CACHE Memory

A fast access small memory space located within the CPU to store the most frequently needed data, so that
CPU can load it without searching from the RAM which works slower than the CPU. It helps during devices
with different speeds have to work togther(Eg : RAM and CPU)

VIRTUAL MEMORY

It is a memory space allocated from the secondary memory / physical memory which also called as the swap
space to move some of the data in RAM when multiple applications are opened simultaneously.

The least recently used data in RAM is usually swapped out.

Issues :
The HDD which works in a different way than RAM has to work swiftly by moving the read/write
heads very fast to locate data stored and to be swapped in and out whenever RAM needs. This makes “Disk
Thrashing”. When virtual memory is used extensively, the system starts to slow down the execution of
programs and performance of the computer drops too.
Solutions:
Install another RAM or change the secondary memory device to SSD.
 Multiple Cores

A single core processor has its own ALU, Control unit and registers. Multiple cores allow to perform many
fetch - decode - execute cycles sumultaneously with each core performs a cycle parallely.

A multi core system can be either :

* When many cores work on one program, it is called parallel processing

* When many cores work in different programs, it is called multitasking

NOTE : Programs that are made to execute sequentially cannot be split to work with multiple cores, as the
next instruction relies on the execution and the result of the previous statement’s execution.

FETCH - DECODE - EXECUTE CYCLE

This is known as the cycle of the CPU.

Fetch stage :

1. The Program Counter(PC) contains the address of next instruction to be fetched.

2. The address stored in PC is copied to Memory Address Register(MAR) through the Address bus.
3. The content of the address stored in MAR is copied to Memory Data Register(MDR) through the
Data bus.
4. The instruction in MDR will be copied to Current Instruction Register(CIR) to store the instruction
which is currently processed.
5. The valus in PC is incremented by 1 to point to the address of next instruction to be fetched.

Decode stage :
The instruction in CIR is conveted to a series of signals for the processor to start execution.

Execute stage :
The processor carries out the operation of the statement.

Memory Register

ADDRESS CONTENT / DATA PC

00000001 INPUT A MAR
00000010 INPUT B MDR
00000011 Total = A + B CIR
00000100 Avg = Total / 2
00000101 OUTPUT Avg
Variable values
A
B
Total
Avg

Screen
Questions

1. Underline the hardware component responsible for controlling the fetch-decode-execute cycle.
Cache, Central processing unit, ROM, Address bus
2. Von Neumann developed the stored program concept that permits two different types of item to reside in
memory.
Name these two types : ___________________________, ____________________________
3. Explain how virtual memory works.
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________________________________________________________________________________________
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4. Complete the diagram by:
• labelling the buses
• adding directional arrows to the dotted lines to show the flow of communication

5. The CPU includes an area of cache memory. Increasing the size of the cache will improve the performance
of the CPU. Explain how increasing the size of the cache improves the performance.
________________________________________________________________________________________
________________________________________________________________________________________
6. Some computers have more than one CPU. The CPUs work in parallel to execute instructions. Complete
the table to show how two CPUs working in parallel could execute the expression:
7. Describe the stored program concept.
________________________________________________________________________________________
________________________________________________________________________________________
8. The fetch-decode-execute cycle is the cycle the central processing unit (CPU) follows in order to process
instructions.
Name two registers used in the cycle: _______________________, ____________________________
9. Describe the role of the address bus and the data bus during the fetch part of the cycle.
________________________________________________________________________________________
________________________________________________________________________________________
10. Complete the table to show the effect on a computer system of increasing the width of a bus.

11. Complete the table by matching the component to the letters

12. One register is the program counter. Its function is to keep track of the next instruction to be fetched.
Describe how it does this :
________________________________________________________________________________________
________________________________________________________________________________________
13. Underline the signal that would be used during the fetch stage of the cycle.
Memory delete signal
Memory read signal
Memory store signal
Memory write signal
14. State how increasing the speed of the clock impacts on the fetch-decode-execute cycle.
________________________________________________________________________________________
________________________________________________________________________________________
15. State what is meant by the term program instruction.
________________________________________________________________________________________
________________________________________________________________________________________
16. State what is meant by the term memory address.
________________________________________________________________________________________
________________________________________________________________________________________
17. Identify the component of the CPU that provides temporary data storage:
Address bus, Data bus, Control unit, Register
18. Give one benefit of having a higher clock speed.
________________________________________________________________________________________
________________________________________________________________________________________
19. Give one drawback of having a higher clock speed.
________________________________________________________________________________________
________________________________________________________________________________________
20. Describe the role of the control unit, the data bus and the address bus when fetching an instruction from
memory.
* The control unit increments the program counter
* The control unit sends a signal along the control bus to the memory(MAR)
* The address of the memory location holding the instruction is loaded onto the address bus
* Load the instruction or contents of the memory location onto the data bus which is carried to
the MDR.
21. Describe the function of the component labelled A.

The Cache memory stores regularly accessed

instructions and data, it reduces the need to access
instructions or data from main memory. This
makes up the difference in speed of the CPU and
main memory.

22. Describe how the CPU and main memory work together.
Data and instructions are fetched from main memory from addresses requested by the CPU on the
address bus.
Data and instructions are sent using the data bus.
Data and instructions are then decoded and executed in the CPU.
Results of operations are sent back to the memory on the data bus.