FETs:

• JFETs
• MOSFETs [typically refers to a metal gate, oxide insulation, and
semiconductor (typically silicon)]
• MESFETs.

MOSFET: metal–oxide–semiconductor field-effect transistor

→based on operation
• depletion type
• enhancement type
 •
n-Channel depletion-type MOSFET A slab of p-type material is formed from a
silicon base and is referred to as the
substrate. (Foundation on which the device
is constructed)
• Substrate is internally connected to the
source terminal (three terminal) or
additional terminal SS is used (Four
terminal)
• The source and drain terminals are
connected through metallic contacts to
n-doped regions linked by an n-channel
• The gate is also connected to a metal
contact surface but remains insulated from
the n-channel by a very thin silicon dioxide
(SiO2) dielectric layer.
• It is the insulating layer of SiO2 in the
MOSFET construction that accounts for the
very desirable high input impedance of the
device.
• A slab of p-type material is formed from a silicon base and is referred to as the
substrate. (Foundation on which the device is constructed)
• Substrate is internally connected to the source terminal (three terminal) or
additional terminal SS is used (Four terminal)
• The source and drain terminals are connected through metallic contacts to n-
doped regions linked by an n-channel
• The gate is also connected to a metal contact surface but remains insulated
from the n-channel by a very thin silicon dioxide (SiO2) dielectric layer.
• It is the insulating layer of SiO2 in the MOSFET construction that accounts for
the very desirable high input impedance of the device.
• gate-to-source voltage is set to 0 V
• VDD is applied across the drain-to-source terminals

The result is an attraction of the

free electrons of the n-channel for
the positive voltage at the drain.
The result is a current similar to
that flowing in the channel of the
JFET
Reduction in free carriers in a channel due to a
negative potential at the gate terminal.
• VGS is set at a negative voltage such as (-1 V) The
negative potential at the gate will tend to
pressure electrons toward the p-type substrate
(like charges repel) and attract holes from the p-
type substrate

• When the magnitude of the negative bias

established by VGS, a level of recombination
between electrons and holes will occur that will
reduce the number of free electrons in the n-
channel available for conduction.

• The drain current is reduced with increasing

negative bias for VGS
• For positive values of VGS, the positive gate will draw additional electrons (free carriers)
from the p-type substrate due to the reverse leakage current and establish new carriers
through the collisions resulting between accelerating particles.

• When VGS continues to increase in the positive direction, drain current will increase at a
rapid rate for the reasons listed above.

• The rapid rise in VGS results a rapid rise in drain current and exceed the maximum drain
current rating (or power rating) of the device.

• The application of a positive VGS enhances the level of free carriers in the channel
compared to that encountered with VGS= 0 V.

• The positive gate voltages on the drain or transfer characteristics is often referred to as the
enhancement region, with the region between cutoff and the saturation level of IDSS
referred to as the depletion region.
Drain and transfer characteristics for an n-channel depletion-type MOSFET.
Drain and transfer characteristics for an n-channel depletion-type MOSFET.

𝑉𝑃 𝐼𝐷𝑆𝑆
When 𝑉𝐺𝑆 = ; 𝐼𝐷 =
2 4
𝐼𝐷𝑆𝑆
𝑊hen 𝑉𝐺𝑆 = 0.3 𝑉𝑃 ; 𝐼𝐷 =
2
 Shockley’s equation

𝑉𝑃 𝐼𝐷𝑆𝑆
When 𝑉𝐺𝑆 = ; 𝐼𝐷 =
2 4

𝐼𝐷𝑆𝑆
𝑊hen 𝑉𝐺𝑆 = 0.3 𝑉𝑃 ; 𝐼𝐷 =
2
p-Channel depletion-type MOSFET
Graphic symbols for: (a) n-channel depletion-type MOSFETs and (b) p-channel depletion-type
MOSFETs.
n-Channel enhancement-type MOSFET

The construction of an enhancement-

type MOSFET is quite similar to that
of the depletion-type MOSFET,
except for the absence of a channel
between the drain and source
terminals.

If 𝑽𝑮𝑺 is set at 0 V and with an applied 𝑽𝑫𝑺 in

the absence of an n-channel leads to 0 A
current
Channel formation in the n-channel
enhancement-type MOSFET.

• 𝑉𝐺𝑆 and 𝑉𝐷𝑆 are set at some positive voltage

greater than 0V, makes the drain and the gate at
a positive potential with respect to the source.
• Positive gate voltage pushes the holes in the p-
substrate along the edge of the SiO2 layer to
leave the area and enter deeper regions of the p-
substrate.
• Results in a depletion region near the SiO2
insulating layer void of holes.
• The electrons in the p-substrate (the minority
carriers) are attracted to the positive gate and
accumulate in the region near the surface of the
SiO2 layer.
• The SiO2 layer and its insulating qualities will
prevent the negative carriers from being
absorbed at the gate terminal
• 𝑉𝐺𝑆 and 𝑉𝐷𝑆 are set at some positive voltage greater than 0V, makes the drain and the gate at a positive
potential with respect to the source.
• Positive gate voltage pushes the holes in the p-substrate along the edge of the SiO2 layer to leave the area
and enter deeper regions of the p-substrate.
• Results in a depletion region near the SiO2 insulating layer void of holes.
• The electrons in the p-substrate (the minority carriers) are attracted to the positive gate and accumulate in
the region near the surface of the SiO2 layer.
• The SiO2 layer and its insulating qualities will prevent the negative carriers from being absorbed at the gate
terminal.
• When 𝑉𝐺𝑆 increases in magnitude, the concentration of electrons near the SiO2 surface increases until
eventually the induced n-type region can support a measurable flow between drain and source.
• The level of 𝑉𝐺𝑆 that result in the significant increase in drain current is called the threshold voltage and is
given the symbol 𝑉𝑇
• As 𝑽𝑮𝑺 is increased beyond the threshold
level, the density of free carriers in the induce
channel will increase, resulting in an
increased level of drain current.

• If 𝑽𝑮𝑺 held constant and increase the level

of 𝑽𝑫𝑺 , the drain current will eventually reach
a saturation level

• The leveling off of 𝑰𝑫 is due to a pinching-off

process depicted by the narrower channel at
the drain end of the induced channel
Drain characteristics of an n-channel enhancement-type
MOSFET
The transfer characteristics for an n-channel enhancement-type MOSFET from the drain
characteristics.
Functional Region of MOSFET
If a MOSFET’s gate and drain are shorted, it can function as a small-signal resistor. When
the Drain, Source, and bulk (body) of a MOSFET are shorted, this acts as one capacitor
plate, and the Gate acts as another capacitor plate. The three main functional regions of a
MOSFET are as follows:

• Cut-off Region: The MOSFET is regarded as being in its “OFF” state when it is in the
cut-off region. This means that no current passes through it when it is turned OFF.
• Saturation Region: Saturation is the state where the MOSFET’s current flow is
constant. It acts as a closed switch in this area, enabling current to flow freely.
• Linear/Ohmic Region: Increasing the voltage across the drain and source also
increases the current flowing through the MOSFET in the linear/ohmic zone

The MOSFET is considered the basic building block and the most frequently
manufactured device. It is also the most common semiconductor device in both analog
and digital circuits.
 𝑽𝑮𝑺 → 𝑮𝒂𝒕𝒆 𝒕𝒐 𝒔𝒐𝒖𝒓𝒄𝒆 𝒗𝒐𝒍𝒕𝒂𝒈𝒆
𝑽𝑫𝑺 → 𝑫𝒓𝒂𝒊𝒏 𝒕𝒐 𝒔𝒐𝒖𝒓𝒄𝒆 𝒗𝒐𝒍𝒕𝒂𝒈𝒆
𝑽𝑻 → 𝑻𝒉𝒓𝒆𝒔𝒉𝒐𝒍𝒅 𝒗𝒐𝒍𝒕𝒂𝒈𝒆
𝑰𝑫 → 𝑫𝒓𝒂𝒊𝒏 𝒄𝒖𝒓𝒓𝒆𝒏𝒕
𝝁𝒏 → 𝑬𝒍𝒆𝒄𝒕𝒓𝒐𝒏 𝒎𝒐𝒃𝒊𝒍𝒊𝒕𝒚
𝑪𝑶𝑿 → 𝑪𝒂𝒑𝒂𝒄𝒊𝒕𝒂𝒏𝒄𝒆 𝒐𝒇 𝒕𝒉𝒆 𝑮𝒂𝒕𝒆 𝒐𝒙𝒊𝒅𝒆 𝒍𝒂𝒚𝒆𝒓
𝑾
→ 𝑨𝒔𝒑𝒆𝒄𝒕 𝒓𝒂𝒕𝒊𝒐 𝒐𝒇 𝒕𝒉𝒆 𝑴𝑶𝑺𝑭𝑬𝑻
𝑳
The three regions of operation of MOSFET (NMOS)
Cut off region
It is the region where the device will be in the OFF condition
and there zero amount of current flow through it. Here, the
device functions as a basic switch and is so employed as
when they are necessary to operate as electrical switches.
𝑽𝑮𝑺 < 𝑽𝑻
𝑰𝑫 = 𝟎
Linear region/Ohmic/Triode region
It is the region where the current across the drain to source
terminal enhances with the increment in the voltage across the
drain to source path. When the MOSFET devices function in this
linear region, they perform amplifier functionality.
𝑽𝑮𝑺 > 𝑽𝑻
𝑽𝑫𝑺 < 𝑽𝑮𝑺 − 𝑽𝑻

𝑾 𝑽𝟐𝑫𝑺
𝑰𝑫 = 𝝁𝒏 𝑪𝑶𝑿 𝑽𝑮𝑺 − 𝑽𝑻 𝑽𝑫𝑺 −
𝑳 𝟐
• The triode region is the operating region where the inversion region
exists and current flows, but this region has begun to taper near the
source. The potential requirement here is, 𝑽𝑫𝑺 < 𝑽𝑮𝑺 − 𝑽𝑻

• Here, the drain source current has a parabolic relation ship with the
drain source potential. The MOSFET operates as a switch in this region.

• The linear region of a MOSFET can be considered as a special portion

of the triode region, where because of the very small value of the
applied drain-source potential, there is a roughly linear relationship
between Vds and Ids and the MOSFET behaves like a voltage
dependent resistor.
Saturation Region – In this region, the devices will have their drain to source
current value as constant without considering the enhancement in the voltage
across the drain to source. This happens only once when the voltage across the
drain to source terminal increases more than the pinch-off voltage value. In this
scenario, the device functions as a closed switch where a saturated level of
current across the drain to source terminals flows. Due to this, the saturation
region is selected when the devices are supposed to perform switching.
𝑽𝑮𝑺 ≥ 𝑽𝑻
𝑽𝑫𝑺 ≥ 𝑽𝑮𝑺 − 𝑽𝑻

𝟏 𝑾 𝟐 𝟐
𝑰𝑫 = 𝝁𝒏 𝑪𝑶𝑿 𝑽𝑮𝑺 − 𝑽𝑻 = 𝑲𝒏 𝑽𝑮𝑺 − 𝑽𝑻
𝟐 𝑳
𝑊
Where 𝐿
is the aspect ratio (width to length and the constant 𝑲𝒏 = 𝝁𝒏 𝑪𝑶𝑿 𝑾 Τ𝟐𝑳
𝝁𝒏 is the mobility of electrons and 𝑪𝑶𝑿 is the oxide capacitance per unit are
Important formulas NMOS transistors
 In this NMOS transistor circuit resistance 𝑹𝑫 is connected in series with 𝑽𝑫𝑫 , so
that 𝒗𝑫𝑺 = 𝑽𝑫𝑫 − 𝟏𝟎𝑰𝑫 . Use following parameters, 𝑉𝐷𝐷 = 4 𝑉 ,
𝜇𝑛 𝐶𝑜𝑥 = 115 𝑚𝐴/𝑉 2 (product of electron mobility and oxide capacitance), the
aspect ratio (the width to length ratio) is 20:2. Let 𝑉𝐺𝑆 = 1.2𝑉 so that transistor
operates in the edge saturation region. Determine 𝑰𝑫 , 𝑽𝑫𝑺 and 𝑽𝑻

we have 𝑽𝑫𝑺 = 𝑽𝑫𝑫 − 𝑰𝑫 𝑹𝑫

𝟏 𝑾 𝟐 𝟐
𝑰𝑫 = 𝝁𝒏 𝑪𝑶𝑿 𝑽𝑮𝑺 − 𝑽𝑻 = 𝑲𝒏 𝑽𝑮𝑺 − 𝑽𝑻
𝟐 𝑳
𝑲𝒏 = 𝝁𝒏 𝑪𝑶𝑿 𝑾 Τ𝟐𝑳 Given that, 𝑽𝑫𝑺 = 𝑽𝑫𝑫 − 𝟏𝟎𝑰𝑫
𝑾 𝟐𝟎 Given that, 𝑽𝑫𝑺 = 𝑽𝑫𝑫 − 𝟑𝟎 𝑲𝒏 𝑽𝑮𝑺 − 𝑽𝑻 𝟐
=
𝑳 𝟐

In the edge saturation region, 𝑽𝑫𝑺 = 𝑽𝑮𝑺 − 𝑽𝑻

𝑽𝑫𝑫 − 𝟏𝟎 𝑲𝒏 𝑽𝑮𝑺 − 𝑽𝑻 𝟐 = 𝑽𝑮𝑺 − 𝑽𝑻

Solve for 𝑽𝑻 using above equation, then find𝑰𝑫 and 𝑽𝑻
p-Channel enhancement-type MOSFET
Symbols for: (a) n-channel enhancement-type MOSFETs
(b) p-channel enhancement-type MOSFETs.
MOSFET can be used as a Voltage Controlled
capacitor: The gate and channel are separated by a thin
layer of SiO2. Therefore, they form a capacitance that
varies along with gate voltage. Here, MOSFET acts as a
MOS Capacitor. It is controlled by the input gate to
source voltage and hence, acts like a voltage-controlled
variable capacitor.
 MOS capacitor: The following are
modes of MOSFET as a capacitor:
1. Accumulation ( VGS < 0 V)
2. Depletion (0 < VGS < VT) Here
(VT = Threshold Voltage)
3. Inversion Region (VGS > VT).

Flat band is the condition where the energy band

(Ec and Ev) of the substrate is flat. This condition is
achieved by applying a negative voltage to the gate.
When the band is flat, the surface electric field in
the substrate is zero. Therefore the electric field in
the oxide is also zero.
Accumulation layer:
• In this case, applied voltage (Vgs) is less than flat band voltage. Voltage applied to gate (on metal
side) is negative

EC= conduction band energy level

Ei = intrinsic energy level
EF= Fermi energy level Vg=voltage applied on gate
Q = charge of electron
EV = valance band energy level Φs=surface voltage
• When voltage is applied, MOSFET no longer remains in equilibrium condition.
The Fermi energy level of metal changes by a factor equal to charge of an
electron multiplied by applied voltage. Voltage applied is negative and hence a
rise in Fermi level of metal takes place while Fermi level of semiconductor
remain constant
• Voltage applied to the gate is negative, hence negative charge develops near
the metal-oxide junction. As result of this, positively charged hole travel towards
the oxide junction thus creating positive charge near the oxide-semiconductor
junction.
• Due to accumulation of positive charge, surface voltage is developed near
oxide-semiconductor junction . This results in the energy band bending and the
value is charge of electron multiplied by surface voltage.
• Energy band bending changes the energy offset (level) of the semiconductor’s
2. Depletion layer: In depletion region, voltage applied to gate is greater than flat
band voltage and less than threshold voltage.
• In this case, voltage applied to gate is positive. Hence there is a fall
in the Fermi energy level of metal while a rise in the Fermi energy
level of the semiconductor.
• Since the applied voltage is positive, a collection of positive
charges develop near the metal-oxide junction. As a result, the
electrons travel towards the gate creating a collection of negative
charges near the oxide-semiconductor junction.
• Electrons recombine with the holes present near the oxide region
creating a depletion region.
• Surface voltage develops in the depletion region and hence energy
band bending takes place in the depletion region.
3. Inversion layer:
• In inversion layer, the applied voltage is greater than threshold voltage.
• As a result of this, the surface is inverted from p-type to n-type near the junction
and hence called as inversion layer
• Voltage applied is very high so that the Fermi level of metal goes further down.
• Since the voltage applied is positive to the gate, the electrons travel towards the
gate and accumulates near the semiconductor-oxide junction resulting the
development of surface potential. Due to surface potential energy, band bending
takes place.
From the diagram, p type substrate near semiconductor-oxide junction has intrinsic
energy level below Fermi energy level and this part of substrate behave as n-type
semiconductor and part above the Fermi level behave as p-type semiconductor. This
happens due to concentration of electrons exceeds concentration of holes near
semiconductor-oxide junction and this phenomenon is known as surface inversion
 MOSFET Scaling
• MOSFET scaling is the reduction in the parameters( like current,
voltage, electric field etc.) due to reduction in length of the
transistor with the advancement in technology.

• how the size of MOSFET have been reducing and due to which
other parameters are varying. For example:180 nanometers
technology, supply voltage can be roughly of value 1.8 volts.

• With newer technologies like 45 nanometers technology, supply

voltage is around 1 volt.
The design of high-density chips in MOS VLSI (Very Large Scale Integration) technology
requires that the packing density of MOSFETs used in the circuits is as high as possible and,
consequently, that the sizes of the transistors are as small as possible. The reduction of the
size, i.e., the dimensions of MOSFETs, is commonly referred to as scaling.

In order to meet the demand of high density chips in MOS technology, it is required that
MOSFET are scaled down i.e. reduction in the size of transistor, so that high packaging density
can be achieved.

Thus scaling of MOSFET transistor is concerned with systematic reduction of overall dimension
of the device as allowed by available technology, while preserving the geometric ratios found
in the larger devices.

A constant scaling factor ‘s’ is introduced. The scaled device is obtained by dividing all
horizontal and vertical dimensions of the large size transistor by this scaling factor.

It is expected that the operational characteristics of the MOS transistor will change with the
reduction of its dimension.