D-A AND A-D CONVERTERS

Most of the real-world physical quantities such as voltage, current, temperature, pressure etc. are
available in analog form.
1t is difficult to process, store or transmit the analog signal without introducing considerable error
because of the superim-position of noise as in the case of amplitude modulation. Therefore, for
processing, transmission, and storage purposes, it is often convenient to express these variables in
digital form.
It gives better accuracy and reduces noise.
The operation of any digital communication system is based upon analog to digital (A/D) and
digital to analog (D/A) conversion.

The analog signal obtained from the transducer is band limited by antialiasing filter.
The signal is then sampled at a frequency rate more than twice the maximum frequency of the band
limited signal. The sampled signal has to be held constant while conversion is taking place in A/D
converter. This requires that ADC should be preceded by a sample and hold (S/H) circuit.
The ADC output is a sequence in binary digit. The micro-computer or digital signal processor
performs the numerical calculations of the desired control algorithm.
The D/A converter is to convert digital signal into analog and hence the function of DAC is exactly
opposite to that of ADC. The D/A converter is usually operated at the same frequency as the ADC.

Both ADC and DAC are also known as data converters and are available in IC form.
The A -D conversion usually makes use of a D-A converter so we shall firs t discuss DAC
followed by ADC.
Basic DAC Techniques
The output of a DAC can be either a voltage or current.

For a voltage output DAC, the D/A converter 1s mathematically described as

V0 = K VFS (d12-1 + d22-2 + ... + dn 2-n)

where, V0 = output voltage

VFS = full scale output voltage
K = scaling factor usually adjusted to unity
d1d2 ... dn = n -bit binary fractional word with the decimal point located at the left
d1 = most significant bit (MSB) with a weight of VFS/2
dn = least significant bit (LSB) with a weight of VFS/2n

Types of DAC
1. Weighted resistor DAC
2. R-2Rladder
3. Inverted R-2R ladder
Weighted resistor DAC
It uses a summing amplifier with a binary weighted resistor network. I t h as n-electronic switches
d1, d2,.., dn controlled by binary input word.
If the binary input to a particular switch is 1, it connects the resistance to the reference voltage (-
VR). And if the input bit is 0, the switch connects the resistor to the ground. The output current I0
for an ideal op-amp can be written as
I0 = I1 + I2 + . . . + In
VR VR VR
¿ d 1+ d 2+ …+ dn
2R 22 R 2nR
VR
= (d12-1 + d22-2 + ... + dn 2-n)
R

The output voltage

RF
Vo = VR (d12-1 + d22-2 + ... + dn 2-n)
R
If Rf =R then K = 1 and VFS = VR.

The circuit uses a negative reference voltage. The analog output voltage is therefore positive
staircase
(i) Although the op-amp is connected in inverting mode , it can also be connected in non-inverting
mode.
(ii) The op-amp is simply working as a current to voltage converter.
(iii) The polarity of the reference voltage is chosen in a ccordance with the type of the switch used.
For example, for TTL compatible switches, t h e reference voltage should be + 5 V and the output
will be negative.
For a 3 bit DAC d1 d2 d3 Vo
0 0 0 0
V0 = VR (d1 2-1 + d2 2-2 + d32-3) 0 0 1 VR/8
0 1 0 VR/4
0 1 1 3/8VR
1 0 0 VR/2
1 0 1 5/8VR
1 1 0 6/8VR
1 1 1 7/8VR

Digitally Controlled SPDT Electronic Switches

A totem-pole MOSFET driver feeds each resistor connected to the inverting input terminal ‘a’. The
two complementary gate inputs Q and Q come from MOSFET S-R flip-flop. Assume a negative
logic, i.e. logic '1’ corresponds to - 10 V and logic ‘0’ corresponds to zero volt.

If there is '1’ in the bit line,S= 1 and R = 0 so that Q = 1 and Q = 0. This drives the transistor Q 1 on,
thus connecting the resistor R1 to the reference voltage -VR whereas the transistor Q2 remains off.
Similarly at '0' at the bit line connects the resistor R1 to the ground terminal.
Another SPDT switch consists of CMOS inverter feeding an op-amp voltage follower which drives
R1 from a very low output resistance.
The circuit is using a positive logic with V(1) = V R = +5 V and V(0) = 0 V. The complement Q of
the bit under consideration is applied at the input. Thus Q = 0 makes transistor Q1 off and Q2 on.
The output of the CMOS inverter is at logic 1, that is, 5 V is applied to resistor R 1 through the
voltage follower. If Q =1 the output of the CMOS inverter is 0 V connecting the resistance R 1 to
ground.

R-2R Ladder DAC

Wide range of resistors are required in binary weighted resistor type DAC.
For 3 bit 2R 4R 8R
Fer 4 bit 2R 4R 8R 16R
This can be avoided by using R-2R ladder type DAC where only two values of resistors are
required. It is well suited for integrated circuit realization. The typical value of R ranges from 2.5
kΩ to 10 kΩ.
Consider a 3-bit DAC where the switch position d1d2d3 corresponds to the binary word 100.
Apply KCL at Node ‘C’ VFS
−V R - V C V C V C
− − =0
2R 2R 2 R
VC = -VR/4
The switch position corresponding to the binary word 001 in 3 bit DAC is shown in fig(a). The
circuit can be simplified to the equivalent form of fig(b). The voltages at the nodes (A, B, C)
formed by resistor branches are easily calculated in a similar fashion and the output voltage
becomes:
−2 R −V R V R V FS
V o=( )( )= =
R 16 8 8
In a similar fashion, the output voltage for R-2R ladder type DAC corresponding to other 3-
bit binary words can be calculated.
Problem

Inverted R-2R Ladder

In weighted resistor type DAC and R-2R ladder type DAC , current flowing in the resistors changes
as the input data changes. More power dissipation causes heating, which in turn, creates non-
linearity in DAC. This is a serious problem and can be avoided completely in 1nverted R-2R ladder
type DAC’. A 3-bit Inverted R-2R ladder type DAC is shown in Fig. (a) where the position of MSB
and LSB is interchanged.

Here each input binary word connects the corresponding switch either to ground or to the inverting
input terminal of the op-amp which is also at virtual ground. Since both the terminals of switches d i
are at ground potential, current flowing in the resistances is constant and independent of switch
position, i.e. independent of input binary word.
The circuit has the important property that the current divides equally at each of the nodes. This is
because the equivalent resistance to the right or to the left of any node is exactly 2R. The division
of the current is shown in Fig.(b).
Consider a reference current of 2 mA. Just to the right of node A, the equivalent resistor is 2R. Thus
2 mA of reference input current divides equally to value 1 mA at node A. Similarly, to the right of
node B, the equivalent resistor is 2R. Thus 1 mA of current further divides to value 0 .5 mA at
node B. Similarly, current divides equally at node C to 0.25 mA.

The equal division of current in successive nodes remains the same in the 'inverted R-2R ladder'
irrespective of the input binary word. Thus, the currents remain constant in each branch of the
ladder.
For d1d2d3 = 100 For d1d2d3 = 111
Io = 1mA Io = 1mA + 0.5mA + 0.25mA
Vo = IoRf = 1.75mA
= (1mA) Rf Vo = (1.75 mA) Rf

Similarly calculate for other input combination.

Problem

Monolithic DAC: 1408 DAC

Monolithic DA Cs consisting of R-2R ladder, switches and the feedback resistor are available for 8,
10, 12 , 14 and 16 bit resolution from various manufacturers. The MC 14081 is a 8-bit DAC with a
current output. The SE/NE 5018 is also an 8-bit DAC but with a voltage output.
A typical 8-bit DAC 1408 compatible with TTL and CMOS logic with settling time around 300ns
is shown in Fig. (a).
It has eight input data lines d1 (MSB) through d8 (LSB). It requires 2 mA reference current for full
scale input and two power supplies Vcc = +5 V and VEE = - 5 V (VEE can range from - 5 V to -15
V).
The total reference current source is determined by resistor R14 and voltage reference VR and is
equal to VR/R14 = 5 V/2 .5 kΩ= 2 mA. The resistor R15 = R14 match the input impedance of the
reference source . The output current I0 is calculated as

( )
8
VR
I o=
R 14
∑ d i 2 -i ; d i= 0 or 1
i=1

I o=
VR d1 d 2
R 14 2 (
+ +. ..+
4
d8
256 )
For full scale input (i.e. d8 through d1 = 1) = (1111 1111)
 1 1 1
Io = 2mA ( + + .. .+ )
2 4 256
= 2mA(255/256) = 1.992 mA
The output is 1 LSB less than the full scale reference current of 2 mA. So, the output voltage V0 for
the full scale input is
Vo = 2 mA (255/256) x 5kΩ = 9.961 V

In general, the output voltage Vo is given by Rf

V o=
VR
R 14
Rf
2 (
d 1 d2
+ +. . .+
4
d8
256 )
Bipolar Operation
The 1408 DAC can be calibrated for bipolar range from -5 V to +5 V by adding resistor R B(5 kΩ)
between VR and output pin 4 as shown in fig. (b). The resistor R B supplies 1 mA (= VR/RB) current
to the output in the opposite direction of the current generated by the input signal. Therefore the
output current for the bipolar operation Io’ is

Problems
A-D Converters
The block schematic of ADC shown in Fig. provides the function just opposite to that of DAC. It
accepts an analog input voltage Va and produces an output binary word d1d2..dn of functional value
D, so that
D = d1 2-1 + d2 2-2 +…. + dn 2-n

where d1 is the most significant bit and d n is the least significant bit. An ADC usually has two
additional control lines: the START input to tell the ADC when to start the conversion and the EOC
(end of conversion) output to announce when the conversion is complete. Depending upon the type
of application, ADCs are designed for microprocessor interfacing or to directly drive LCD or LED
displays.
Types of ADC
Parallel Comparator (Flash) A/D converter
Counter type A/D converter
Servo Tracking A/D converter
Successive approximation type converter

The Parallel Comparator (Flash) A/D converter

This is the simplest, fastest, and most expensive technique. Figure (a) shows a 3-bit AID converter.
The circuit consists of a resistive divider network, 8 op-amp comparators and a 8-line to 3-line
encoder.
At each node of the resistive divider, a comparison voltage is available. Since all the resistors are of
equal value, the voltage levels available at the nodes are equally divided between the reference
voltage VR and the ground. The purpose of the circuit is to compare the analog input voltage V a
with each of the node voltages.
. The truth table for the flash type AD converter is shown in Fig. (c).
The circuit has the advantage of high speed as the conversion take place simultaneously rather than
sequentially. Typical conversion time is 100 ns or less. Conversion time is limited only by the
speed of the comparator and of the priority encoder.
This type of ADC has the disadvantage that the number of comparators required almost doubles for
each added bit. A 2-bit ADC requires 3 comparators, 3-bit ADC needs 7, whereas 4- bit requires 15
comparators. In general, the number of comparators required are 2 n - 1 where n is the desired
number of bits. Also, the larger the value of n, the more complex is the priority encoder.
The Counter type A/D converter
A 3-bit counting ADC based upon the above principle is shown in Fig. (a). The counter is reset to
zero count by the reset pulse.
Upon the release of RESET, the clock pulses are counted by the binary counter. These pulses go
through the AND gate which is enabled by the voltage comparator high output. The number of
pulses counted increase with time. The binary word representing this count is used as the input of a
D/A converter whose output is a staircase of the type shown in Fig. (b).

The analog output Vd of DAC is compared to the analog input Va by the comparator. If Va> Vd, the
output of the comparator becomes high and the AND gate is enabled to allow the transmission of
the clock pulses to the counter.
When Va< Vd, the output of the comparator becomes low and the AND gate is disabled. This stops
the counting at the time V a ≤ Vd and the digital output of the counter represents the analog input
voltage Va.
For a new value of analog input V a, a second reset pulse is applied to clear the counter. Upon the
end of the reset, the counting begins again as shown in Fig. (b).
The counter frequency must be low enough to give sufficient time for the DAC to settle and for the
comparator to respond. Low speed is the most serious drawback his method. The conversion time
can be as long as (2n- 1) clock periods depending upon the magnitude of input voltage Va.
For instance, a 12-bit system with 1 MHz clock frequency, the counter will take (2 12 - 1) µs = 4.095
ms to convert a full scale input.

Servo Tracking A/D Converter

An improved version of counting ADC is the tracking or a servo converter shown in fig. The circuit
consists of an up/down counter with the comparator controlling the action of the count.

A tracking A/D converter

The analog output of the DAC is Vd and is compared with the analog input V a. If the input Va, is
greater than the DAC output signal, the output of the comparator goes high and the counter is
caused to count up.
The DAC output increases with each incoming clock pulse and when it becomes more than V a, the
counter reverses the direction and counts down (but only by one count, LSB). This causes the
control to count up and the count increases by 1 LSB.
The process goes on being repeated and the digital output changes back and forth by ±1 LSB
around the correct value. As long as the analog input changes slowly, the tracking A/D will be
within one LSB of the correct value.
The tracking ADC has the advantage of being simple. The disadvantage, however, is the time
needed to stabilize as a new conversion value is directly proportional to the rate at which the analog
signal changes.
Successive Approximation Converter
The successive approximation technique uses a very efficient code search strategy to complete n-bit
conversion in just n-clock periods. An eight-bit converter would r e quire eight clock pulses to
obtain a digital output. The circuit uses a successive approximation register (SAR) to find the
required value of each bit by trial and error. The circuit operates as follows:
With the arrival of the START command, the SAR sets the MSB d 1 = 1 with all other bits to zero so
that the trial code is 10000000.
The output Vd of the DAC is now compared with analog input V a. If Va is greater than the DAC
output Vd then 10000000 is less than the correct digital representation. The MSB is left at ' 1' and
the next lower significant bit is made '1' and further tested.

However, if Va is less than the DAC output, then 10000000 is greater than the correct digital
representation. So reset MSB to '0' and go on to the next lower significant bit. This procedure is
repeated for all subsequent bits. one at a time , until all bit positions have been tested.
Whenever the DAC output crosses Va, the comparator changes state and this can be taken as the
end of conversion (EOC) command. Figure (a) shows a typical conversion sequence.
Problems
1.

2.