Lecture 17:

Introduction to Design For Testability (DFT) &

Manufacturing Test

Mark McDermott
Electrical and Computer Engineering
The University of Texas at Austin

10/22/18 VLSI-1 Class Notes

 Agenda

§ Introduction to testing
§ Logical faults corresponding to defects
§ DFT

10/22/18 VLSI-1 Class Notes 2

 Outline

§ Testing
– Logic Verification
– Silicon Debug
– Manufacturing Test
§ Fault Models
§ Observability and Controllability
§ Design for Test
– Scan
– BIST
§ Boundary Scan

10/22/18 VLSI-1 Class Notes 3

 Testing

§ Testing is everything when it comes to making $$$$$.

– Selling bad silicon can bankrupt a company.

§ Three main categories

– Functionality test or logic verification (before tapeout)
• Make sure functionality is correct
– Silicon debug (on first batch of chips from fab)
•
detective work
• You don’t want to mass-produce
bad chips
– Manufacturing test (on each mfg’d chip before shipping)
• You don’t want to ship
bad chips

10/22/18 VLSI-1 Class Notes 4

The Manufacturing Process is Imperfect

10/22/18 VLSI-1 Class Notes Page•5

5
 The Manufacturing Process is Imperfect

10/22/18 VLSI-1 Class Notes Page 6

 The Manufacturing Process is Imperfect

10/22/18 VLSI-1 Class Notes Page 7

 Testing

§ Testing and/or debugging a chip costs at various levels

Wafer level $0.01-$0.10
Packaged chip level $0.10-$1
Board level $1-$10
System level $10-$100
Field level $100-$1000

§ Cost goes up exponentially if fault detected at later stages

10/22/18 VLSI-1 Class Notes 8

 Testing

§ Testing is one of the most expensive parts of chips

– Logic verification accounts for > 60% of design effort for many chips
– Debug time after fabrication has enormous opportunity cost
– Shipping defective parts can sink a company
§ Example: Intel FDIV bug
– Logic error not caught until > 1M units shipped
– Recall cost >> $450M
– Was this a verification problem or a testing problem?

10/22/18 VLSI-1 Class Notes 9

 Logic Verification

§ Does the chip simulate correctly?

– Usually done at HDL level
– Verification engineers write test bench for HDL
• Can
t test all cases
• Look for corner cases
• Try to break logic design

§ Ex: 32-bit adder

– Test all combinations of corner cases as inputs:
• 0, 1, 2, 231-1, -1, -231, a few random numbers

§ Good tests require ingenuity

10/22/18 VLSI-1 Class Notes 10

 Silicon Debug

§ Test the first chips back from fabrication

– If you are lucky, they work the first time
– If not…
§ Logic bugs vs. electrical failures
– Most chip failures are logic bugs from inadequate simulation
– But some are electrical failures
• Crosstalk
• Dynamic nodes: leakage, charge sharing
• Ratio failures
– A few are tool or methodology failures (e.g. DRC)
§ Fix the bugs and fabricate a corrected chip

10/22/18 VLSI-1 Class Notes 11

 Shmoo Plots

§ How to diagnose failures?

– Hard to access chips
• Picoprobes
• Electron beam
• Laser voltage probing
• Built-in self-test
§ Shmoo plots
– Vary voltage, frequency, temperature
– Look for cause of
electrical failures

10/22/18 VLSI-1 Class Notes 12

 Manufacturing Test

§ A speck of dust on a wafer is sufficient to kill chip

§ Yield of any chip is < 100%
– Must test chips after manufacturing before delivery to customers to only
ship good parts
§ Manufacturing testers are
very expensive
– Minimize time on tester
– Careful selection of
test vectors

10/22/18 VLSI-1 Class Notes 13

 Cheap Testers

§ Tester and test fixtures

– Can be very expensive (e.g., $1-2M)
§ If you don
t have a multimillion dollar tester:
– Build a breadboard with LED
s and switches
– Hook up a logic analyzer and pattern generator
– Or use a low-cost functional chip tester

10/22/18 VLSI-1 Class Notes 14

 TestosterICs

§ Ex: TestosterICs functional chip tester

– Reads test vectors, applies them to your chip, and reports assertion failures
– A low cost ditigal VLSI tester

10/22/18 VLSI-1 Class Notes 15

 Stuck-At Faults

§ How does a chip fail?

– Need
fault model
– Usually failures are shorts between two conductors or opens in a conductor
– This can cause very complicated behavior

§ A simpler model: Stuck-At

– Assume all failures cause nodes to be
stuck-at 0 or 1, i.e. shorted to GND
or VDD
– Not quite true, but works well in practice

10/22/18 VLSI-1 Class Notes 16

Examples

10/22/18 VLSI-1 Class Notes •17

17
 Observability & Controllability
§ Observability: ease of observing a node by watching external
output pins of the chip

§ Controllability: ease of forcing a node to 0 or 1 by driving input

pins of the chip

§ Combinational logic is usually easy to observe and control

§ Finite state machines can be very difficult, requiring many cycles

to enter desired state
– Especially if state transition diagram is not known to the test engineer

10/22/18 VLSI-1 Class Notes 18

 Test Pattern Generation

§ Manufacturing test ideally would check every node in the circuit

to prove it is not stuck.

§ Apply the smallest sequence of test vectors necessary to prove

each node is not stuck.

§ Good observability and controllability reduces number of test

vectors required for manufacturing test.
– Reduces the cost of testing
– Motivates design-for-test

10/22/18 VLSI-1 Class Notes 19

 Test Example
SA1 SA0
§ A3
§ A2 A3
A2
n1

Y
§ A1 A1
n2 n3

§ A0 A0

§ n1
§ n2
§ n3
§Y

§ Minimum set:

10/22/18 VLSI-1 Class Notes 20

 Test Example
SA1 SA0
§ A3 {0110} {1110}
§ A2
A3 n1
A2
Y

§ A1 A1
n2 n3

§ A0 A0

§ n1
§ n2
§ n3
§Y

§ Minimum set:

10/22/18 VLSI-1 Class Notes 21

 Test Example
SA1 SA0
§ A3 {0110} {1110}
§ A2 {1010} {1110} A3
A2
n1

Y
§ A1 A1
n2 n3

§ A0 A0

§ n1
§ n2
§ n3
§Y

§ Minimum set:

10/22/18 VLSI-1 Class Notes 22

 Test Example
SA1 SA0
§ A3 {0110} {1110}
§ A2 {1010} {1110} A3
A2
n1

Y
§ A1 {0100} {0110} A1
n2 n3

§ A0 A0

§ n1
§ n2
§ n3
§Y

§ Minimum set:

10/22/18 VLSI-1 Class Notes 23

 Test Example
SA1 SA0
§ A3 {0110} {1110}
§ A2 {1010} {1110} A3
A2
n1

Y
§ A1 {0100} {0110} A1
n2 n3

§ A0 {0110} {0111} A0

§ n1
§ n2
§ n3
§Y

§ Minimum set:

10/22/18 VLSI-1 Class Notes 24

 Test Example
SA1 SA0
§ A3 {0110} {1110}
§ A2 {1010} {1110} A3
A2
n1

Y
§ A1 {0100} {0110} A1
n2 n3

§ A0 {0110} {0111} A0

§ n1 {1110} {0110}
§ n2
§ n3
§Y

§ Minimum set:

10/22/18 VLSI-1 Class Notes 25

 Test Example
SA1 SA0
§ A3 {0110} {1110}
§ A2 {1010} {1110} A3
A2
n1

Y
§ A1 {0100} {0110} A1
n2 n3

§ A0 {0110} {0111} A0

§ n1 {1110} {0110}
§ n2 {0110} {0100}
§ n3
§Y

§ Minimum set:

10/22/18 VLSI-1 Class Notes 26

 Test Example
SA1 SA0
§ A3 {0110} {1110}
§ A2 {1010} {1110} A3
A2
n1

Y
§ A1 {0100} {0110} A1
n2 n3

§ A0 {0110} {0111} A0

§ n1 {1110} {0110}
§ n2 {0110} {0100}
§ n3 {0101} {0110}
§Y

§ Minimum set:

10/22/18 VLSI-1 Class Notes 27

 Test Example
SA1 SA0
§ A3 {0110} {1110}
§ A2 {1010} {1110} A3
A2
n1

Y
§ A1 {0100} {0110} A1
n2 n3

§ A0 {0110} {0111} A0

§ n1 {1110} {0110}
§ n2 {0110} {0100}
§ n3 {0101} {0110}
§Y {0110} {1110}

§ Minimum set: {0100, 0101, 0110, 0111, 1010, 1110}

10/22/18 VLSI-1 Class Notes 28

 Design for Test

§ Design the chip to increase observability and controllability

§ If each register could be observed and controlled, test problem

reduces to testing combinational logic between registers.

§ Better yet, logic blocks could enter test mode where they
generate test patterns and report the results automatically.

10/22/18 VLSI-1 Class Notes 29

 Scan

§ Convert each flip-flop to a scan register CLK

SCAN
– Only costs one extra multiplexer

Flop
SI Q
§ Normal mode: flip-flops behave as usual D

§ Scan mode: flip-flops behave as shift register

§ Contents of flops
scan-in

Flop

Flop

Flop
can be scanned
Flop

Flop

Flop
out and new inputs
Logic
Cloud
Logic
Cloud outputs
Flop

Flop

Flop
values scanned in
Flop

Flop

Flop
scanout

10/22/18 VLSI-1 Class Notes 30

 Basics of Scan

F7 S F1
R
A
M
A C F
E H
F8 F2 F5
B D G

F9 F3 F6

F0 F4

10/22/18 VLSI-1 Class Notes Page 31

 Basics of Scan
SCAN IN

F7 S F1
R
A
M
A C F
E H
F8 F2 F5
B D G

F9 F3 F6

F0 F4

SCAN OUT

10/22/18 VLSI-1 Class Notes Page 32

 Scannable Flip-flops
SCAN
SCAN CLK Q
f f
D
D 0 X
Q
Flop
Q
SI 1 SI f f
(a) f f

(b)
f f

fd

f D
f Q
fd
SCAN
fd X
Q
fs f f
fs f
SI
(c)
fs
f f

10/22/18 VLSI-1 Class Notes 33

 Why Scan design?

• Makes internal circuit access much more direct to

allow for controllability and observability

• Converts a sequential test generation problem into a

combinational test generation problem

• Enables automatic test pattern generation (ATPG)

• Enables use of low-pincount, low cost testers (ATE)

10/22/18 VLSI-1 Class Notes 34

 Stuck-At Testing
SCAN IN

Test for C stuck-at 1

F7 S F1
R
A
M
A C F
E H
F8 F2 F5
B D G

F9 F3 F6

F0 F4

SCAN OUT

10/22/18 VLSI-1 Class Notes Page 35

 Stuck-At Testing
SCAN IN Load Scan Chain
Test for C stuck-at 1

S 0
R
A
M
A C F
E H
1
B D G

SCAN OUT

10/22/18 VLSI-1 Class Notes Page 36

 Stuck-At Testing
SCAN IN Pulse Clock
Test for C stuck-at 1

Test Result
S ?
R
A
M
A C F
E H
? 1
B D G

SCAN OUT

10/22/18 VLSI-1 Class Notes Page 37

 Stuck-At Testing
SCAN IN Unload Scan Chain
Test for C stuck-at 1

S 0
R
A
M
A C F
E H
1 1
B D G

SCAN OUT

10/22/18 VLSI-1 Class Notes Page 38

 Built-in Self-test

§ Built-in self-test lets blocks test themselves

– Generate pseudo-random inputs to combinational logic
– Combine outputs into a syndrome
– With high probability, block is fault-free if it produces the expected
syndrome

10/22/18 VLSI-1 Class Notes 39

 PRSG

§ Linear Feedback Shift Register

– Shift register with input taken from XOR of state
– Pseudo-Random Sequence Generator

Step Q
CLK
Q[0] Q[1] Q[2] 0 111
Flop

Flop

Flop
D D D
1
2
3
4
5
6
7
10/22/18 VLSI-1 Class Notes 40
 PRSG

§ Linear Feedback Shift Register

– Shift register with input taken from XOR of state
– Pseudo-Random Sequence Generator

Step Q
CLK
Q[0] Q[1] Q[2] 0 111
Flop

Flop

Flop
D D D
1 110
2
3
4
5
6
7
10/22/18 VLSI-1 Class Notes 41
 PRSG

§ Linear Feedback Shift Register

– Shift register with input taken from XOR of state
– Pseudo-Random Sequence Generator

Step Q
CLK
Q[0] Q[1] Q[2] 0 111
Flop

Flop

Flop
D D D
1 110
2 101
3
4
5
6
7
10/22/18 VLSI-1 Class Notes 42
 PRSG

§ Linear Feedback Shift Register

– Shift register with input taken from XOR of state
– Pseudo-Random Sequence Generator

Step Q
CLK
Q[0] Q[1] Q[2] 0 111
Flop

Flop

Flop
D D D
1 110
2 101
3 010
4
5
6
7
10/22/18 VLSI-1 Class Notes 43
 PRSG

§ Linear Feedback Shift Register

– Shift register with input taken from XOR of state
– Pseudo-Random Sequence Generator

Step Q
CLK
Q[0] Q[1] Q[2] 0 111
Flop

Flop

Flop
D D D
1 110
2 101
3 010
4 100
5
6
7
10/22/18 VLSI-1 Class Notes 44
 PRSG

§ Linear Feedback Shift Register

– Shift register with input taken from XOR of state
– Pseudo-Random Sequence Generator

Step Q
CLK
Q[0] Q[1] Q[2] 0 111
Flop

Flop

Flop
D D D
1 110
2 101
3 010
4 100
5 001
6
7
10/22/18 VLSI-1 Class Notes 45
 PRSG

§ Linear Feedback Shift Register

– Shift register with input taken from XOR of state
– Pseudo-Random Sequence Generator

Step Q
CLK
Q[0] Q[1] Q[2] 0 111
Flop

Flop

Flop
D D D
1 110
2 101
3 010
4 100
5 001
6 011
7
10/22/18 VLSI-1 Class Notes 46
 PRSG

§ Linear Feedback Shift Register

– Shift register with input taken from XOR of state
– Pseudo-Random Sequence Generator

Step Q
0 111
CLK
Q[0] Q[1] Q[2] 1 110
Flop

Flop

Flop
D D D
2 101
3 010
4 100
5 001
6 011
7 111
(repeats)
10/22/18 VLSI-1 Class Notes 47
 BILBO

§ Built-in Logic Block Observer

– Combine scan with PRSG & signature analysis
D[0] D[1] D[2]

C[0]
C[1]

Q[2] / SO
SI
Flop

Flop

Flop
1
0 Q[0]
Q[1]

MODE C[1] C[0]

Scan 0 0
Logic Signature
PRSG Test 0 1
Cloud Analyzer
Reset 1 0
Normal 1 1

10/22/18 VLSI-1 Class Notes 48

 Boundary Scan

§ Testing boards is also difficult

– Need to verify solder joints are good
• Drive a pin to 0, then to 1
• Check that all connected pins get the values
§ Through-hold boards used
bed of nails
§ SMT and BGA boards cannot easily contact pins
§ Build capability of observing and controlling pins into each chip to
make board test easier

10/22/18 VLSI-1 Class Notes 49

 Boundary Scan Example

PackageInterconnect

CHIP B CHIP C

Serial Data Out

CHIP A CHIP D

IO pad and Boundary Scan

Cell

Serial Data In

10/22/18 VLSI-1 Class Notes 50

 Boundary Scan Interface

§ Boundary scan is accessed through five pins

– TCK: test clock
– TMS: test mode select
– TDI: test data in
– TDO: test data out
– TRST*: test reset (optional)

§ Chips with internal scan chains can access the chains

through boundary scan for unified test strategy.

10/22/18 VLSI-1 Class Notes 51

 Summary

§ Think about testing from the beginning

– Simulate as you go
– Plan for test after fabrication

§
If you don’t test it, it won’t work! (Guaranteed)

10/22/18 VLSI-1 Class Notes 52