Lecture4 Cda3101
Lecture4 Cda3101
LOGIC DESIGN
The language of the machine is binary – that is, sequences of 1’s and 0’s. But why?
• At the hardware level, computers are streams of signals. These signals only have two
states of interest, high voltage and low voltage.
• Binary is merely a natural abstraction for the underlying signals.
• Rather than talking about voltage levels, we talk about logically true signals (having a value 1) and
logically false signals (having a value 0).
• We might also say that logically true signals are asserted, while logically false signals are de-asserted.
LOGIC BLOCKS
Logic Blocks are programmable logic components which take some input and produce
some output according to a set of logical rules.
• Combinational Logic Blocks – depend only on a set of inputs. Any given input will
always result in the same output.
• Sequential Logic Blocks – maintain an internal state, which may affect the output
obtained for a given set of input values.
TRUTH TABLES
Defining a combinational logic block is as simple as defining the output values for all
of the possible sets of input values.
Because our input takes only one of two values – 0 or 1 – for 𝑛 inputs, there are 2#
possible input combinations.
As long as we can define the output for each of these combinations, our
combinational logic block is fully defined.
TRUTH TABLES
• Consider a logic function with three inputs, A, B, and C, and three outputs, D, E, and F.
• D is true if at least one input is true,
• E is true if exactly two inputs are true, and
• F is true only if all three inputs are true.
• 𝐴 * 𝐵 ↔ 𝐴̅ + 𝐵
5
• 𝐴 + 𝐵 ↔ 𝐴̅ * 𝐵5
LOGIC EQUATIONS
Consider a logic function with three inputs, A, B, and C, and three outputs, D, E, and F.
• D is true if at least one input is true,
• E is true if exactly two inputs are true, and
• F is true only if all three inputs are true.
A
AND B
C 𝐶 = 𝐴*𝐵
A
OR B
C 𝐶 = 𝐴+𝐵
Here our AND and OR gates
accept two input values, but since
AND and OR are both
commutative and associative, they
NOT A C 𝐶 = 𝐴̅ can have any number of input
values.
LOGIC GATES
Note that it is common to avoid explicit NOT gates in favor of bubbles around the
input output lines. For example,
A
C
B
A
C
B
The multiplexor on the left has two input values, A and B. There is
an additional input value S, the selector (or control) value. The
selector value determines which of the input values, A or B, will be
used as the output value.
MULTIPLEXORS
As stated before, all logic functions can be implemented using only AND, OR, and
NOT. Below is the gate implementation of our example multiplexor.
S 𝐶 = (𝐴 * 𝑆̅) + (𝐵 * 𝑆)
MULTIPLEXORS
Clearly, with only two data inputs, our selector can uniquely identify the selected
input value using only a single selector input. We can select A if S is false (0) and B if
S is true (1). But what if we want more than two data inputs?
To uniquely identify each of 𝑛 data input values, we’ll need log = 𝑛 selector input
values.
It’s easy to convince ourselves of this. Using 𝑛 bits, we can represent the decimal
range 0 through (2# −1). Therefore, log = 𝑛 bits can be used to represent the range
0 through (2?@AB # −1), or 0 through (𝑛 − 1).
MULTIPLEXORS
So, to implement a multiplexor with 𝑛 data inputs and log = 𝑛 selector inputs, we can
implement the following.
• A decoder that generates 𝑛 signals, each indicating a different input value.
• An array of 𝑛 AND gates, each combining one of the inputs with a signal from the
decoder.
• A large OR gate that takes an input all of the outputs of the AND gates.
A 1-bit decoder
MULTIPLEXORS
As an example, let’s say we want to implement a multiplexor which accepts 4 input
bits. We will need 2 selector bits. The selector bits can take on the values 00, 01, 10,
11. Let’s say our selector-bits decoder uses the following truth table.
• Product of Sums
• A logical product (AND) is taken over a collection of logical sums (OR).
• Example: 𝐴̅ + 𝐵5 + 𝐶 * 𝐴̅ + 𝐶̅ + 𝐵 * (𝐵5 + 𝐶̅ + 𝐴)
TWO-LEVEL LOGIC
What is the advantage of using this canonical form of two-level representation?
Take for example the logic equation of E.
𝐸 = (𝐴 * 𝐵 + 𝐵 * 𝐶 + (𝐶 * 𝐴)) * (𝐴 * 𝐵 * 𝐶)
This equation has three levels of logic, resulting in three steps.
We must first perform 𝐴 * 𝐵 , 𝐵 * 𝐶 , and (𝐶 * 𝐴).
The results of these are logically summed,
After which the result is logically multiplied with another Boolean expression.
The canonical form below has only two steps, but performs the same logical function:
𝐸 = 𝐴 * 𝐵 * 𝐶̅ + 𝐴 * 𝐶 * 𝐵5 + (𝐵 * 𝐶 * 𝐴̅)
TWO-LEVEL LOGIC
It’s a bit harder to see why every logical function can be represented in the canonical
forms so let’s look at an example.
A B C D
0 0 0 0 Here, we have three input values A, B, and C and
output value D. Let’s try to construct the sum-of-products
0 0 1 1
representation of D.
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
TWO-LEVEL LOGIC
Sum-of-products representation of D:
First, we note that there are only four input combinations which
A B C D
result in a value of true for D. These combinations are 001, 010,
0 0 0 0 100, and 111. We will just refer to them as T1, T2, T4, and T7.
0 0 1 1 T1 So, we can at least say the following:
0 1 0 1 T2
0 1 1 0 𝐷 = 𝑇1 + 𝑇2 + 𝑇4 + 𝑇7
1 0 0 1 T4
In other words, if have any of those sequences as input, then D
1 0 1 0 must be true.
1 1 0 0
1 1 1 1 T7
TWO-LEVEL LOGIC
Sum-of-products representation of D:
Note that the contents of a PLA are fixed when the PLA is constructed but an
equivalent structure called a PAL can be programmed electronically.
PROGRAMMABLE LOGIC ARRAYS
A PLA can directly implement the truth table A B C D E F
of a set of logic functions with multiple inputs
0 0 0 0 0 0
and outputs. Let’s look at an example using
the truth table from earlier. 1 0 0 1 0 0
0 1 0 1 0 0
0 0 1 1 0 0
1 1 0 1 1 0
1 0 1 1 1 0
0 1 1 1 1 0
1 1 1 1 0 1
A B C D E F
To construct the PLA, we can perform a
process similar to constructing the sum-of-
0 0 0 0 0 0 products representation of a logical
1 0 0 1 0 0 T1 equation.
0 1 0 1 0 0 T2
First we note that there are only seven
0 0 1 1 0 0 T3 sequences which result in a truth value for
1 1 0 1 1 0 T4 any of the output values D, E, or F.
1 0 1 1 1 0 T5
0 1 1 1 1 0 T6
1 1 1 1 0 1 T7
PROGRAMMABLE LOGIC ARRAYS
The logic functions for D, E, and F can be
A B C D E F
expressed in terms of these sequences.
0 0 0 0 0 0
1 0 0 1 0 0 T1
𝐷 = 𝑇1 + 𝑇2 + 𝑇3 + 𝑇4 + 𝑇5 + 𝑇6 + 𝑇7
0 1 0 1 0 0 T2 𝐸 = 𝑇4 + 𝑇5 + 𝑇6
0 0 1 1 0 0 T3 𝐹 = 𝑇7
1 1 0 1 1 0 T4
1 0 1 1 1 0 T5
0 1 1 1 1 0 T6
1 1 1 1 0 1 T7
PROGRAMMABLE LOGIC ARRAYS
The logic functions for D, E, and F can be
A B C D E F
expressed in terms of these sequences.
0 0 0 0 0 0
1 0 0 1 0 0 T1
𝐷 = 𝑇1 + 𝑇2 + 𝑇3 + 𝑇4 + 𝑇5 + 𝑇6 + 𝑇7
0 1 0 1 0 0 T2 𝐸 = 𝑇4 + 𝑇5 + 𝑇6
0 0 1 1 0 0 T3 𝐹 = 𝑇7
1 1 0 1 1 0 T4 And each sequence can be expressed in terms of
1 0 1 1 1 0 T5 A, B, and C. For example,
0 1 1 1 1 0 T6 𝑇1 = 𝐴 * 𝐵5 * 𝐶̅
1 1 1 1 0 1 T7
PROGRAMMABLE LOGIC ARRAYS
So, our products (or minterms) are:
A B C D E F
𝑇1 = 𝐴 * 𝐵5 * 𝐶̅
0 0 0 0 0 0
𝑇2 = 𝐴̅ * 𝐵 * 𝐶̅
1 0 0 1 0 0 T1 𝑇3 = 𝐴̅ * 𝐵5 * 𝐶
0 1 0 1 0 0 T2 𝑇4 = 𝐴 * 𝐵 * 𝐶̅
𝑇5 = 𝐴 * 𝐵5 * 𝐶
0 0 1 1 0 0 T3 𝑇6 = 𝐴̅ * 𝐵 * 𝐶
1 1 0 1 1 0 T4 𝑇7 = 𝐴 * 𝐵 * 𝐶
1 0 1 1 1 0 T5 And our sums of products are:
0 1 1 1 1 0 T6 𝐷 = 𝑇1 + 𝑇2 + 𝑇3 + 𝑇4 + 𝑇5 + 𝑇6 + 𝑇7
1 1 1 1 0 1 T7 𝐸 = 𝑇4 + 𝑇5 + 𝑇6
𝐹 = 𝑇7
PROGRAMMABLE LOGIC ARRAYS
So, our products (or minterms) are:
𝑇1 = 𝐴 * 𝐵5 * 𝐶̅
𝑇2 = 𝐴̅ * 𝐵 * 𝐶̅
𝑇3 = 𝐴̅ * 𝐵5 * 𝐶
𝑇4 = 𝐴 * 𝐵 * 𝐶̅
𝑇5 = 𝐴 * 𝐵5 * 𝐶
𝑇6 = 𝐴̅ * 𝐵 * 𝐶
𝑇7 = 𝐴 * 𝐵 * 𝐶
And our sums of products are:
𝐷 = 𝑇1 + 𝑇2 + 𝑇3 + 𝑇4 + 𝑇5 + 𝑇6 + 𝑇7
𝐸 = 𝑇4 + 𝑇5 + 𝑇6
𝐹 = 𝑇7
ARITHMETIC LOGIC UNIT
The Arithmetic Logic Unit (ALU) is the central component of the computing process – it
performs all of the arithmetic and logical operations.
We can construct an ALU using only the AND, OR, NOT, and multiplexor logic blocks.
Since the MIPS word is 32 bits, our ALU needs to handle 32 bit inputs but we can
start by creating a 1 bit ALU and then extend our ALU for 32 bits.
ARITHMETIC LOGIC UNIT
We start with implementing an ALU that performs AND and OR operations. Our input
values are a and b. Our circuit performs 𝑎 * 𝑏 and 𝑎 + 𝑏. The actual result is selected
using a multiplexor where the selector value 0 indicates an AND operation and the
selector value 1 indicates an OR operation.
1 0 1 0
+ 1 1
ARITHMETIC LOGIC UNIT
Now we need to add addition to our ALU. We will represent the adder as a black
box which hides the implementation details of addition except to say that our adder
must accept two inputs for the operands and have one output for the result.
1 0 1 0
+ 1 1
1
ARITHMETIC LOGIC UNIT
Now we need to add addition to our ALU. We will represent the adder as a black
box which hides the implementation details of addition except to say that our adder
must accept two inputs for the operands and have one output for the result.