894 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 69, NO.

3, MARCH 2022

Performance, Power, and Area of Standard Cells

in Sub 3 nm Node Using Buried Power Rail
Jun-Sik Yoon , Member, IEEE, Jinsu Jeong , Seunghwan Lee ,
Junjong Lee , Graduate Student Member, IEEE, Sanguk Lee , Graduate Student Member, IEEE,
Rock-Hyun Baek , Member, IEEE, and Sung Kyu Lim, Senior Member, IEEE

Abstract — We analyzed the performance, power, area (Fig. 1) [1]–[5]. Fin shape has changed from tapered to rec-
of 3 nm node fin and nanosheet (NS) field-effect tran- tangular fin through full-fledged extreme ultraviolet (EUV) and
sistors (FETs) implementing buried power rail (BPR) SiGe channel [6]. Self-aligned contact and contact-over-active-
after full calibration to 5 nm node hardware. Fin-shaped
FETs (FinFETs) have smaller RC delay than do NS FETs gate (COAG) reduce the number of metal tracks [1], [2]. Single
(NSFETs) under the same footprint and two-fin configura- diffusion break (SDB) reduces the number of dummy gates to
tion. Larger number of NS channels boost drive currents increase the standard cell density [1], [2], [7]. If CPP and cell
but also increase gate capacitances as a tradeoff. Compared height are scaled down at constant rate from 10 nm node,
with 7 and 3 nm standard cells achieve 75% cell area scaling it is expected that 3 nm node has the CPP of 42 nm and the
in average. Cells using BPR decrease delay, transition time,
internal power, and pin capacitances under the same area. cell height of 120 nm. Gate-all-around (GAA) nanosheet field-
Larger cells such as D-flip flop (DFF) and XOR decrease effect transistors (NSFETs) reduce the short channel effects
those further because the parasitic capacitances of metal and have larger current drivability compared with FinFETs [8].
layers between signal and power/ground decrease much. Also nanosheet (NS) width (WNS ) is easily tuned at a certain
NS-based cells using BPR can improve delay and transition value, which enables performance and power optimization
time by increasing the number of NS channels, but increase
internal power and pin capacitance. Overall, fin-based cells for different applications. However, we should also consider
using BPR have smaller energy delay product by 12% com- the middle-of-line (MOL) layers because the parasitic RCs at
pared with those without BPR and by 10% compared with MOL level increase greatly as technology node advances [9].
NS-based cells using BPR. Buried power rail (BPR) has been proposed to place the
Index Terms — 3 nm, buried power rail (BPR), power (V DD) and ground (V SS) metal lines below the
fin, nanosheet (NS), performance-power-area (PPA), devices [10]. Especially, back-side BPR decreases the IR
standard cell. drop and the back-end-of-line (BEOL) routing congestion by
placing the power delivery network below the substrate [11].
I. I NTRODUCTION
Static random access memory (SRAM) implementing BPR

S ILICON fin-shaped field-effect transistors (FinFETs) have

been scaled down from 10 to 5 nm node with contin-
uous scaling of contacted poly pitch (CPP) and cell height
as bitline for signal routing decreases both access time and
dynamic power over conventional SRAM [12]. But to the
best of our knowledge, there are no quantitative analyses of
Manuscript received November 25, 2021; revised December 22, 2021; BPR-implemented standard cells in state-of-the-art technology
accepted December 23, 2021. Date of publication January 17, 2022; date nodes.
of current version February 24, 2022. This work was supported in part
by the Ministry of Trade, Industry and Energy under Grant 10080617,
This study is based on full calibration to 5 nm hardware,
in part by the Korea Semiconductor Research Consortium Support thus estimating the performances of device and cell in 3 nm
Program for the Development of the Future Semiconductor Device, node accurately. In addition, we designed 24 standard cells
in part by the Pohang University of Science and Technology (POSTECH)- in 3 nm implementing fin or NS structure or/and BPR,
Samsung Electronics Industry-Academic Cooperative Research Center,
in part by the National Research Foundation of Korea grant funded by and investigated those in terms of performance, power, and
the Ministry of Science, ICT under Grant 2020R1A4A4079777 and Grant area (PPA) using commercial electronic design automation
2020M3F3A2A02082436, and in part by BK21 FOUR and IC Design (EDA) tools. Therefore, this work provides the device design
Education Center. The review of this article was arranged by Editor R.
Wang. (Corresponding author: Rock-Hyun Baek.) guideline in the cell layout perspective.
Jun-Sik Yoon is with the Department of Electrical Engineering, Pohang
University of Science and Technology (POSTECH), Pohang 37673, II. S IMULATION M ETHOD
South Korea, and also with the School of Electrical and Computer Both FinFETs and NSFETs were simulated using Sentaurus
Engineering, Georgia Institute of Technology, Atlanta, GA 30332 USA
(e-mail: [email protected]). TCAD [13]. All the equations used in this work were same
Jinsu Jeong, Seunghwan Lee, Junjong Lee, Sanguk Lee, and as in [14] and [15]. Doping profile, mobility, and carrier
Rock-Hyun Baek are with the Department of Electrical Engineering, velocity were calibrated to 5-nm node FinFETs [6] as shown in
Pohang University of Science and Technology (POSTECH), Pohang
37673, South Korea (e-mail: [email protected]). Fig. 2(a). Geometry parameters of 5-nm node FinFETs were
Sung Kyu Lim is with the School of Electrical and Computer Engineer- also included in the inset. First, subthreshold swing (SS) and
ing, Georgia Institute of Technology, Atlanta, GA 30332 USA. drain-induced barrier lowering (DIBL) were fitted by changing
Color versions of one or more figures in this article are available at
https://doi.org/10.1109/TED.2021.3138865. source–drain (S–D) doping concentration and annealing time.
Digital Object Identifier 10.1109/TED.2021.3138865 Then, low-field mobility and its related parameters at high gate

0018-9383 © 2022 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.

Authorized licensed use limited to: National Taiwan University. Downloaded on December 12,2023 at 15:10:35 UTC from IEEE Xplore. Restrictions apply.
YOON et al.: PPA OF STANDARD CELLS IN SUB 3 nm NODE USING BPR 895

TABLE I
G EOMETRICAL PARAMETERS OF FinFET S AND NSFET S
IN 7 AND 3 nm N ODES

Fig. 1. Standard cell area (CPP × cell height) of three major industries
as technology node is scaled down from 10 to 7 nm nodes [1]–[5]. Based TABLE II
on the scaling trend, this work estimates the possible cell area in 3 nm G EOMETRY PARAMETERS AND R ESISTANCES OF
node and addresses the implementation of BPR or/and GAA. M ETAL L AYERS AND V IAS

node, but not 4 nm due to the loss of carrier mobility [19].

NS widths (WNS ) are 25 nm (W25) and 10 nm (W10) to match
the footprint of two- and one-fin FinFETs. It was announced
that NSFETs having larger WNS improve RC delay [17], but
Fig. 2. (a) Calibration results to 5 nm node FinFETs [6] and (b) ION –IOFF
here we designed the devices under the same active area with
plot for 7 nm [18], 5, and 3 nm of NFETs (filled) and PFETs (empty). FinFETs for fair comparison. NS thickness (TNS ) and spacing
(Tsp ) are 5 and 10 nm, respectively [8]. Table II indicates
electric field were calibrated by fitting the drain currents (Ids ) geometry parameters and resistances of metal layers and vias.
in the linear region. Finally, saturation velocity was modified to Resistance of metal layers (M1, M2) is 347 /μm [20], and
fit the Ids in the saturation region. Compared with the previous that of via (V0, V1) is 63.5  [21]. Resistance of MOL metals
calibrations done in 10 nm node [14]–[17], this work calibrates is 523 /μm from ASAP7 [18]. Metal BPR (MBPR) and
to state-of-the-art 5-nm node FinFETs. So, it would give much via BPR (VBPR) have the resistance of 65 /μm and 56 ,
reliable results to predict 3 nm and beyond nodes. respectively [10]. MBPR has the width of 25 nm and the aspect
In this work, it was assumed that 3 nm FinFETs follow the ratio of 2. VBPR has the width × length of 20 × 12 nm2 and
same performance gain as from 7 to 5 nm by improving the connects between MBPR and source-side MOL metals (M0).
ON -currents (ION ) by 15% with respect to 5 nm FinFETs [6]. Operation voltage (Vdd ) is fixed at 0.70 V.
The ION was improved through proper process advancements Fig. 3 shows the geometry of FinFETs and NSFETs. All
including Wfin scaling, much abrupt S/D doping profile for the process steps for FinFETs and NSFETs are equivalent as
similar DIBL and SS at the scaled gate length (L g ), and contact in [14]–[17]. Several geometrical parameters of the devices are
resistivity reduction. Fig. 2(b) shows the ION –OFF-currents specified. S/D doping concentration, annealing temperature,
(IOFF ) plot for 7 nm [18], 5, and 3 nm for three different and time are 4·1020 cm−3 , 1050 ◦ C, and 0.5 s, respec-
applications. From 7 to 5 nm, the ION was improved greatly tively. Doping concentration for punchthrough-stopper (PTS)
by 33% and 40% for N-type Field Effect Transistors (NFETs) region is 5·1018 cm−3 to prevent subfin leakage. Both the
and P-type Field Effect Transistors (PFETs), respectively, devices have the rectangular S/D epi, to be explained in
by taller and rectangular fin, SiGe high mobility channel, and Section III. For NSFETs, bottom oxide was used to completely
other process advancements. In this work, we chose standard remove the bottom transistor for dc/ac performance advance-
performance application (0.25 nA per fin) only for device and ments [22], [23]. We also considered SiGe intermixing to Si
cell-level analyses. NS channels causing threshold voltage changes [24].
Table I presents the geometry parameters of FinFETs and Electrical characteristics of the standard cells were pre-
NSFETs in 7 and 3 nm nodes. Geometrical parameters of 7 nm pared (Fig. 4). We used Synopsys EDA tools, except Cadence
node are from ASAP7 [18]. The 3 nm node has the cell height Liberate for library (LIB) file generation for fair comparison
of 120 nm, equal to total six fins or five metal tracks. Fin height with ASAP7. HSPICE fits the transfer, output, and capaci-
(Hfin ) is fixed to 55 nm, same as in 5 nm node. Fin width tance characteristics of the calibrated TCAD devices by using
(Wfin ) is chosen to 5 nm for better controllability than 5 nm Berkeley Short channel IGFET model (BSIM) common metal

Authorized licensed use limited to: National Taiwan University. Downloaded on December 12,2023 at 15:10:35 UTC from IEEE Xplore. Restrictions apply.
896 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 69, NO. 3, MARCH 2022

Fig. 3. Half schematic diagrams of FinFETs and NSFETs in 3 nm node.

Materials and three terminals [source (S), gate (G), and drain (D)] are
specified.

Fig. 5. (a) Schematic showing the concerns of S/D epi isolation in the
standard cell and (b) dc characteristics of the FinFETs having different
S/D epi schemes.
Fig. 4. Schematic flow to generate LIB file including the electrical
characteristics of the standard cells. around contact (WAC) are used due to S/D epi merging
[Fig. 5(b)]. Diamond epi without WAC can avoid this, but
gate (CMG). StarRC generates the nxtgrd file, containing the its dc performance is degraded by increasing the contact
parasitic RC of metal interconnects, from the interconnect resistance. So, we used S/D patterning (SDP) scheme forming
technology format (ITF). After drawing the standard cell rectangular S/D epi [15]. This scheme can maintain the dc
layouts using Custom Compiler, IC validator performs layout performance and isolate the S/D epi concurrently.
versus schematic (LVS) check. Then, StarRC does layout
parasitic extraction (LPE) using the LVS output and nxtgrd.
III. R ESULTS AND D ISCUSSION
Finally, Cadence Liberate uses SPICE parameters and parasitic
RC of the standard cells to generate LIB file containing all the A. Device-Level Characterization
electric characteristics of standard cells such as delay, transi- Fig. 6 summarizes the ION , gate capacitances (Cgg ), and RC
tion time (ttran ), internal power (Pint ), input pin capacitance delay (Cgg Vdd /ION ) of FinFETs and NSFETs in 3 nm node. IOFF
(Cpin ), and leakage power (Pleak ). To utilize BPR, we first are fixed to 0.5 nA for two-fin FinFETs and W25 NSFETs,
defined the resistances of MBPR and VBPR in ITF. After whereas the IOFF are 0.25 nA for one-fin FinFETs and W10
MBPR and VBPR are drawn in the cell layout, RC components NSFETs. ASAP7 also has the same IOFF of 0.25 nA/fin [18].
of MBPR and VBPR are extracted in the LPE step. Effective widths (Weff ) of FinFETs and NSFETs are calculated
To reside two-fin NFET/PFETs within the cell height of as Nfin · (Wfin + 2Hfin ) and NNS · (2WNS + 2TNS ), respectively.
120 nm, all the standard cells need one dummy fin between While the Cgg increases at constant rate as a function of
the devices to isolate S/D epi [Fig. 5(a)]. The diamond S/D NNS , the increasing rate of ION per NNS decreases. This effect
epi should not grow laterally over the length of fin pitch is explained by the ION normalized by Weff (ION /Weff ) in
(FP)-Wfin /2, which is 17.5 nm in 3 nm node, for the epi Table III. NSFETs have smaller ION /Weff as the NNS increases
isolation. But it is challenging when diamond epi and wrap- because the longer carrier path for bottom-most NS channel

Authorized licensed use limited to: National Taiwan University. Downloaded on December 12,2023 at 15:10:35 UTC from IEEE Xplore. Restrictions apply.
YOON et al.: PPA OF STANDARD CELLS IN SUB 3 nm NODE USING BPR 897

Fig. 7. INV×1 layouts of 3 nm node FinFETs without (left) and with (right)
BPR.

of BPR. All the layers except MBPR and VBPR are obtained
from ASAP7 [18]. Both COAG and SDB are adopted for
the standard cell design. NSFETs use the same metal layers
Fig. 6. ON-currents (ION ), gate capacitances (Cgg ), and RC delay of
FinFETs (dotted lines) and NSFETs (symbols) having different WNS and
as FinFETs, thus are not shown here. INV×1 without BPR
NNS . Effective widths (Weff ) of FinFETs and NSFETs are also specified has 12-nm-wide M1 layers for power/ground (V DD/V SS),
in the bracket. whereas that with BPR has 25-nm-wide MBPR layers enabling
TABLE III longer input ( A) and output (Y ) M1 lengths for better routabil-
ION N ORMALIZED BY Weff FOR FinFET S AND NSFET S ity in circuit design. The cells without BPR have 11.5 nm
proximity of fins to V DD/V SS lines, whereas the cells with
BPR have 5 nm proximity. V DD/V SS line resistances without
and with BPR are the same as those of M1 and MBPR,
respectively.
Table IV summarizes the electrical characteristics of two
standard cells (INV×1 and DFFH×1) of FinFETs and
NSFETs at different input slews and load capacitances (Cload ).
induces the larger parasitic resistance [17]. FinFETs and
The 7 nm standard cells are also included for comparison.
NSFETs have similar ION /Weff at the NNS of 3, but the NSFETs
Energy delay product (EDP) is calculated as the multiplication
have smaller ION under the same active area due to smaller
of power and delay squared.
Weff than FinFETs. The NSFETs with the NNS of 4 and
First, comparing 7 and 3 nm nodes, the cell area is scaled
5 have larger ION than the FinFETs due to their larger Weff ,
down significantly for both INV×1 (−77%) and DFFH×1
but degrade the Cgg arising from more channels, overlap, and
(−68%). As the 3-nm node uses two fins instead of three fins
outer-fringing capacitances [14]. Therefore, all the NSFETs
for 7 nm node, both Cpin and Pleak decrease. Taller fin for 3 nm
have larger RC delay than the FinFETs. Previous work [14]
node increases the ION per fin greatly. Overall, all the electrical
showed that NSFETs have smaller RC delay than FinFETs.
characteristics (delay, ttran , Pint ) are improved for 3 nm node.
But the FP in this work is 20 nm, shorter than 28 nm in [14],
Second, comparing fin-based cells, BPR decreases the Cpin
thus increasing the Weff per footprint for FinFETs compared
by 1% for INV×1 and 2% for DFFH×1 due to the reduced
with NSFETs in the two-fin configuration. Comparing one-fin
parasitic capacitance (Cpara ) between V DD/V SS and signal.
FinFETs and W10 NSFETs, FinFETs certainly outperform
Especially, BPR improves the delay, ttran , and Pint of DFFH×1
NSFETs in the one-fin configuration as the FinFETs have
greatly than INV×1 because the Cpara decreases much for
smaller Cgg at the same ION .
larger cells. Smaller resistance for MBPR compared with M1
reduces those metrics further as given in Table II.
B. Cell-Level Analysis Third, fin-based cells have smaller Cpin by 4% and 19%
Fig. 7 shows the INV×1 layouts of 3 nm node FinFETs than NS-based cells with the NNS of 4 and 5, respectively,
without (w/o) and with (w/) BPR. All the standard cells in arising from smaller Cgg (in Fig. 6). Different from RC delay
3 nm node have the same cell height of 120 nm irrespective results in Fig. 6, NS-based cells have shorter delay and ttran

Authorized licensed use limited to: National Taiwan University. Downloaded on December 12,2023 at 15:10:35 UTC from IEEE Xplore. Restrictions apply.
898 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 69, NO. 3, MARCH 2022

TABLE IV
E LECTRICAL C HARACTERISTICS OF INV×1 AND DFFH×1 IN 7 AND
3 nm N ODES AT D IFFERENT I NPUT S LEW AND L OAD C APACITANCES

Fig. 8. (a) Delay, (b) Pint , and area of the standard cells using FinFETs
without and with BPR.

between FinFETs and NSFETs as long as the PTS controls

the subfin leakage effectively [14]. So, the cell characteristics
are determined mostly by ION and Cgg as shown in Fig. 6.
Previous work for analog/RF application shows that NSFETs
have greater intrinsic gain (G m Ro ) than FinFETs due to
larger transconductance (G m ) by larger Weff and large output
resistance (Ro ) by better gate electrostatics [25]. But in terms
of the standard cells for digital application, fin-based cells
for more NNS . It is because the Cload is much greater than the show better results than NS-based ones.
Cgg and thus the ION dominantly affects the cell speed at the Third, this work only applies W10 and W25 NSFETs for
specific case. It is clear that more NNS decreases delay and one- and two-fin, respectively. WNS can be modulated at
ttran much by 6% and 11% for the slow case, respectively. But continuous level, whereas Nfin is discrete and Wfin and Hfin
the ION increase causes the Pint increase due to the increase are fixed. This design flexibility for NSFETs would give rise
of short-circuit currents in operation. to the improved cell performance, which is beyond the scope
Finally, fin- and NS-based INV×1 have similar EDPs, of the article.
whereas fin-based DFFH×1 have smaller EDP by 10% for the Fig. 8 summarizes delay, Pint , and area of all the standard
fast case and by 5% for the slow case than NS-based ones. cells using FinFETs without and with BPR for the medium
DFFH×1 use more number of field-effect transistors (FETs) speed case. All the standard cells except INV×1, NAND2 × 1,
than INV×1, so the Pint difference between FinFETs and and NOR2×1 improve the delay by BPR. Three standard cells
NSFETs increases. In addition, DFFH×1 has a one-fin con- with the greatest delay and Pint saving by BPR are DFFH×1,
figuration, and one-fin FinFETs outperform W10 NSFETs. XNOR3×1, and XOR3×1 because their cell areas are the largest.
Therefore, fin-based DFFH×1 w/ BPR have the smallest EDP As the cell is larger, Cpara between V DD/V SS and signal
in 3 nm node. decreases much for BPR. In addition, the smaller resistance
There are three possible reasons why NS-based cells have of MBPR over M1 further decreases the delay and Pint and
larger EDP than fin-based cells. benefits more as the cell is larger.
First, NSFETs lose the benefits of drive currents as the FP
is scaled down to 20 nm in 3 nm node. Under the same active
IV. C ONCLUSION
region for two-fin configuration, NSFETs need at least 4 of
NNS to meet similar ION as FinFETs, but more NNS increase the FinFETs and NSFETs implementing BPR are analyzed
Cgg as a tradeoff. For one-fin configuration, FinFETs are much thoroughly in terms of device and cell levels using full-
better than NSFETs because FinFETs have smaller facing area calibrated TCAD. SDP scheme is adopted for rectangular S/D
between S/D and gate and thus smaller Cgg . If three-fin or epi to prevent S/D epi merging. At the device level, NSFETs
beyond configuration is adopted, NSFETs would increase the have larger RC delay than FinFETs. Especially, the RC delay
drive currents over FinFETs. of W10 NSFETs is much larger than that of one-fin FinFETs
Second, there is minimal benefit of short channel control- due to large Cpara induced by large facing area between S/D
lability for GAA over fin channel. DIBL and SS are similar epi and gate. At the cell level, NS-based cells can decrease

Authorized licensed use limited to: National Taiwan University. Downloaded on December 12,2023 at 15:10:35 UTC from IEEE Xplore. Restrictions apply.
YOON et al.: PPA OF STANDARD CELLS IN SUB 3 nm NODE USING BPR 899

the delay and ttran by increasing the NNS , but increase the Pint [10] A. Gupta et al., “Buried power rail scaling and metal assessment for the
over fin-based cells as a tradeoff at the same input slew and 3 nm node and beyond,” in IEDM Tech. Dig., Dec. 2020, pp. 413–416.
[11] D. Prasad et al., “Buried power rails and back-side power grids: Arm
Cload . Overall, fin-based cells have smaller EDP than NS-based CPU power delivery network design beyond 5 nm,” in IEDM Tech. Dig.,
cells, especially for large cells where more number of FETs Dec. 2019, pp. 446–449.
are arranged. As the BPR is implemented, all the standard [12] R. Mathur et al., “Buried bitline for sub-5 nm SRAM design,” in IEDM
Tech. Dig., Dec. 2020, pp. 409–412.
cells improve Cpin , delay, ttran , and Pint , and more with larger [13] Version O-2018.06, Synopsys, Mountain View, CA, USA, 2018.
cells. Therefore, under two-fin configuration, FinFETs using [14] J.-S. Yoon, J. Jeong, S. Lee, and R.-H. Baek, “Systematic DC/AC
BPR scheme are promising for 3 nm node. performance benchmarking of sub-7-nm node FinFETs and nanosheet
FETs,” IEEE J. Electron Devices Soc., vol. 6, pp. 942–947, 2018.
[15] J.-S. Yoon et al., “Source/drain patterning FinFETs as solution for
R EFERENCES physical area scaling toward 5-nm node,” IEEE Access, vol. 7,
pp. 172290–172295, 2019.
[1] C. Auth et al., “A 10 nm high performance and low-power CMOS [16] J.-S. Yoon, J. Jeong, S. Lee, and R.-H. Baek, “Multi-V th strategies
technology featuring 3rd generation FinFET transistors, self-aligned of 7-nm node nanosheet FETs with limited nanosheet spacing,” IEEE
quad patterning, contact over active gate and cobalt local interconnects,” J. Electron Devices Soc., vol. 6, pp. 861–865, 2018.
in IEDM Tech. Dig., Dec. 2017, pp. 673–676. [17] J.-S. Yoon, J. Jeong, S. Lee, and R.-H. Baek, “Optimization of nanosheet
[2] X. Wang et al., “Design-technology co-optimization of standard cell number and width of multi-stacked nanosheet FETs for sub-7-nm node
libraries on Intel 10 nm process,” in IEDM Tech. Dig., Dec. 2018, system on chip applications,” Jpn. J. Appl. Phys., vol. 58, no. SB,
pp. 636–639. Mar. 2019, Art. no. SBBA12.
[3] J. Yuan et al., “High performance mobile SoC productization with [18] L. T. Clark et al., “ASAP7: A 7-nm FinFET predictive process design
second-generation 10-nm FinFET technology and extension to 8-nm kit,” Microelectron. J., vol. 53, pp. 105–115, Jul. 2016.
scaling,” in Proc. IEEE Symp. VLSI Technol., Jun. 2018, pp. 219–220. [19] X. He et al., “Impact of aggressive fin width scaling on FinFET device
[4] J. Deng et al., “5G and AI integrated high performance mobile SoC characteristics,” in IEDM Tech. Dig., Dec. 2017, pp. 493–496.
process-design co-development and production with 7 nm EUV FinFET [20] T. Nogami et al., “Comparison of key fine-line BEOL metallization
technology,” in Proc. IEEE Symp. VLSI Technol., Jun. 2020, pp. 1–2. schemes for beyond 7 nm node,” in Proc. Symp. VLSI Technol.,
[5] S. Narasimha et al., “A 7 nm CMOS Technology platform for mobile and Jun. 2017, pp. 148–149.
high performance compute application,” in IEDM Tech. Dig., Dec. 2017, [21] V. Moroz et al., “Can we ever get to a 100 nm tall library? Power
pp. 689–692. rail design for 1 nm technology node,” in Proc. Symp. VLSI Technol.,
[6] G. Yeap et al., “5 nm CMOS production technology platform featuring Jun. 2020, pp. 1–2.
full-fledged EUV, and high mobility channel FinFETs with densest [22] J. Zhang et al., “Full bottom dielectric isolation to enable stacked
0.021μm2 SRAM cells for mobile SoC and high performance computing nanosheet transistor for low power and high performance applications,”
applications,” in IEDM Tech. Dig., Dec. 2019, pp. 879–882. in IEDM Tech. Dig., Dec. 2019, pp. 250–253.
[7] W. C. Jeong et al., “True 7 nm platform technology featuring smallest [23] J.-S. Yoon, J. Jeong, S. Lee, and R.-H. Baek, “Punch-through-
FinFET and smallest SRAM cell by EUV, special constructs and 3rd stopper free nanosheet FETs with crescent inner-spacer and isolated
generation single diffusion break,” in Proc. IEEE Symp. VLSI Technol., source/drain,” IEEE Access, vol. 7, pp. 38593–38596, 2019.
Jun. 2018, pp. 59–60. [24] J. Jeong, J.-S. Yoon, S. Lee, and R.-H. Baek, “Threshold voltage
[8] N. Loubet et al., “Stacked nanosheet gate-all-around transistor to enable variations induced by Si1−x Gex and Si1−x Cx of sub 5-nm node silicon
scaling beyond FinFET,” in Proc. Symp. VLSI Technol., Jun. 2017, nanosheet field-effect transistors,” J. Nanosci. Nanotechnol., vol. 20,
pp. 230–231. no. 8, pp. 4684–4689, Aug. 2020.
[9] G. Bonilla, “The continuation of an interconnect-centric technology [25] J.-S. Yoon and R.-H. Baek, “Device design guideline of 5-nm-node
era—The MOL and BEOL challenge,” in Proc. VLSI Tech. Short Course, FinFETs and nanosheet FETs for analog/RF applications,” IEEE Access,
Jun. 2018, pp. 1–55. vol. 8, pp. 189395–189403, 2020.

Authorized licensed use limited to: National Taiwan University. Downloaded on December 12,2023 at 15:10:35 UTC from IEEE Xplore. Restrictions apply.