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Japanese Journal of Applied Physics 49 (2010) 100001 COMPREHENSIVE REVIEW

Current Status of Nonvolatile Semiconductor Memory Technology

Yoshihisa Fujisaki
Central Research Laboratory, Hitachi, Ltd., Kokubunji, Tokyo 185-8601, Japan
Received March 24, 2010; accepted May 1, 2010; published online October 20, 2010

In this report, an overview of the current status of nonvolatile semiconductor memory technology is presented. We are reaching the integration
limit of flash memories, and many new types of memories to replace conventional flash memories have been proposed. Unlike flash memories,
new nonvolatile memories do not require electric charge storing. The possibility of phase-change random access memory (PRAM) or resistive-
change RAM (ReRAM) replacing ultrahigh-density NAND flash memories has been discussed; however, there are many issues to overcome,
making the replacement difficult. Nonetheless, ferroelectric RAMs (FeRAMs) and MRAMs are gradually penetrating into fields where the
shortcomings of flash memories, such as high operating voltage, slow rewriting speed, and limited number of rewrites, make their use
inconvenient. For the successful application of new nonvolatile semiconductor memories, they must be practically utilized in new fields in which
flash memories are not applicable, and the technology for them must be developed. # 2010 The Japan Society of Applied Physics
DOI: 10.1143/JJAP.49.100001

miniaturization of flash memory is limited by the parasitic

1. Introduction effect,2) the phenomenon in which the storage of electric
Recently, nonvolatile semiconductor memories have become charges is affected by interference resulting from the
essential in our daily lives. For example, electrically erasable capacitive coupling with adjacent cells,3) which is the main
and programmable read-only memories (EEPROMs) and problem associated with increasing memory capacity. How-
ferroelectric random access memories (FeRAMs) are used ever, some solutions to this issue using highly advanced
in wireless railway passes and IC cards, which are used multilayered4) or multilevel5) structures have been proposed;
by millions of commuters every day. Large-capacity flash therefore, the memories based on other technologies cannot
memories are used in cellular phones, digital cameras, easily approach flash memory in terms of bit cost.
moving picture experts group (MPEG) audio players, However, the shortcomings of flash memories become
universal serial bus (USB) memories, and other devices. apparent in the fields of system memories with embedded
Moreover, nonvolatile semiconductor memories are used in logic and universal memories, which can replace all the
most domestic electronic appliances and in automobiles. memories in a system, such as static RAM (SRAM),
Thus far, metal–oxide–semiconductor (MOS)-type nonvola- dynamic RAM (DRAM), EEPROM, and flash memories,
tile memories, such as flash memories, have satisfied most with a single chip. The first practical applications of FeRAM
device requirements. and MRAM have overcome the drawbacks of flash memory.
Meanwhile, many new types of memory with operating In the future, when the use of electronics is expected to be
principles completely different from that of flash memories widespread in various fields, the requirements of memory
have been proposed. Typical new memories include the will become more diverse in order to accommodate the
above-mentioned FeRAM and magnetoresistive RAM purpose of each application, e.g., low power consumption
(MRAM), which are already being used in various applica- and cost, high speed, or long lifetime. This is the background
tions. As next-generation memories, research on phase- behind the currently ongoing development of various
change RAM (PRAM), resistive-change RAM (ReRAM), nonvolatile semiconductor memories. In this article, we
spin-transfer torque MRAM, and organic memories is provide an overview of future technological trends by
ongoing. considering the application fields of memories currently
Why is the development of these technologies required being proposed.
now? It is because, despite their apparently unlimited Note that Si–oxide–nitride–oxide–Si (SONOS)6) flash
versatility, even flash memories have some shortcomings, memories as well as memories using nanoparticle tunnel
as summarized in Table I. The operating voltages and speeds gates7) have been developed as advanced flash memories;
shown in the table are rough values because they depend on however, these memories are not discussed in this report.
the structures of the systems and circuits.1) FeRAM and MRAM are only briefly explained in §2 and
When flash memories are used as large-capacity recording §3 owing to the lack of space, because their practical
media, the drawbacks listed in Table I are expected to application is already underway and because their operating
remain negligible for the time being. This is because flash principles are almost completely understood.
memories have long been used as a product, and their
manufacturing cost per bit (bit cost) is substantially lower 2. FeRAM
than that of other memories. Among the drawbacks of flash FeRAM was the first memory to be put into full-scale
memories, the structure with embedded logic is disadvanta- practical use among the possible replacements for flash
geous because a booster circuit is required for the writing memories, and has now been established as a memory with
voltage. This will become a problem when the minimum embedded logic that can be used in wireless IC cards,
feature size F is reduced to less than 32 nm. In addition, the automobile equipment including event data recorders
(EDRs),8) and domestic electronic appliances. The greatest

This is a translated version of the original paper which appeared in Oyo advantage of FeRAM is its low power consumption, which
Buturi 77 (2008) 1060 [in Japanese]. is overwhelmingly superior to that of other memories.
100001-1 # 2010 The Japan Society of Applied Physics
Jpn. J. Appl. Phys. 49 (2010) 100001 Comprehensive Review

Table I. Problems with flash memory.

Problem Details Limitations in application

NOR: 7 – 9 V Disadvantageous for
High writing voltage
NAND: 17 –19 V memories with embedded logic
NOR: 1 ms/bit
Low writing speed Cannot be used as RAM
NAND: 1 ms/page
Limited number of rewrites 105 times Limited types of possible application
Difficult to achieve F < 30 nm because of electric Solved by using multilayered and vertical
Limited miniaturization level
charge interference between adjacent cells MOS structure
Complicated and high-cost Complicated fabrication of Disadvantageous for
manufacturing process floating gates memories with embedded logic

Page: Minimum unit of data writing. This is usually carried out in a block of approximately 512 bits–8 kbits.

oxides, which cause negligible oxygen loss.10,11) If an

industrial-level infinite rewrite endurance is achieved in
the future, FeRAM will become the memory most closely
approaching universal memory.
The main materials used in FeRAM are Pb(Zr,Ti)O3
(PZT) and SrBi2 Ta2 O9 (SBT);12) the former is suitable
for high-density integration because of the large remnant
polarization Pr , and the latter is suitable for low-voltage
operation because of the small coercive field Ec . However,
the ferroelectric properties should be further improved for
ultrahigh-density integration, and research on new types of
materials, such as (Bi,La)4 Ti3 O12 (BLT)13,14) and BiFeO3
(BFO),15,16) is being carried out.
Fig. 1. (Color online) Readout method of FeRAM. For bit ‘‘1’’ (the In addition to capacitor-type FeRAMs, which are already
ferroelectric capacitor is located at A on the hysteresis curve), the in practical use, research is ongoing on FeRAMs with a
capacitor moves from A to C then back to A on the hysteresis curve when
chain cell structure,17) which makes them suitable for
a readout pulse of VR is applied, and a current of Q1 =t flows on the bit
line. On the other hand, for bit ‘‘0’’ (the capacitor is at B), the capacitor high-density integration, and one transistor-type FeRAMs,
moves from B to C to A when the readout pulse is applied, and a larger in which the gate insulating film of a MOS transistor is
current of ðQ1 þ Q2 Þ=t flows on the bit line. The bit information ‘‘1’’ or replaced with a ferroelectric thin film. The structure of
‘‘0’’ is judged from the difference in the magnitudes of the currents. transistor-type FeRAMs is suitable for high-density integra-
However, the capacitor never fails to return to position A on the hysteresis
tion and is thus considered to be the ultimate structure for
curve (bit state of ‘‘1’’) once readout operation starts, regardless of the
initial conditions; therefore, it is necessary to rewrite the data after FeRAMs. Moreover, transistor-type FeRAMs do not require
readout. destructive readout, which is the greatest weakness of
capacitor-type FeRAMs, and have thus been targeted in
many research studies since the 1960s.18) However, because
Moreover, the writing speed and the maximum number of of the poor data retention characteristics,19) it is thought to be
rewrites of FeRAMs are at least one and six orders greater difficult to realize nonvolatile retention of data for 10 years.
than those of flash memories, respectively. Also, FeRAMs For FeRAMs, almost all the physics underlying their
can be operated at 2 V or lower and are thus advantageous practical application, such as the operating principles and
from many viewpoints. deterioration mechanisms, is already understood, and their
However, the maximum number of readouts is limited to performance can be easily improved by applying new
approximately 1012 because FeRAMs adopt a destructive materials and processes. In the future, highly integrated and
readout method (Fig. 1), by which bit information is low-cost (reduced bit cost) FeRAMs will be increasingly
destroyed at the time of readout (flash memories can realize developed along with pioneering applications. For further
infinite readouts). This is the main weakness of FeRAMs, information on FeRAMs, please refer to review articles
and does not apply to other types of memory. Also, FeRAMs reported elsewhere.19,20)
are slightly less suitable for high-density integration than
other memories because of their capacitor-type memory cell 3. MRAM
structure. The highest degree of integration ever reported The substantial mass production of MRAMs, although still
is 64 Mbits;9) however, only approximately 4-Mbit FeRAMs on a relatively small scale, started in 2006, and MRAMs are
are currently commercially available. now in practical use. The operating principle of MRAMs is
The limited rewrite endurance is due to the phenomenon based on tunnel magnetoresistance (TMR), through which
of oxygen being released from a ferroelectric oxide to the resistance is changed, and the physical mechanism of
electrodes and fixed charges being generated on the TMR is well understood.21) Figure 2 shows the MRAM cell
electrode surface. Sufficient robustness for infinite rewriting structure. The heart of this structure is a magnetic tunnel
has been achieved using oxide electrodes or Bi-layered junction (MTJ), which is a stack structure consisting of a
100001-2 # 2010 The Japan Society of Applied Physics
Jpn. J. Appl. Phys. 49 (2010) 100001 Comprehensive Review

Amorphizing
RESET Pulse
t1
Ta

Temperature
Crystallizing
(SET) Pulse

Tx
t2

Time

Fig. 3. Set and reset current pulses.31)

free layer with variable spin directions. This has numerous

advantages, such as a significant reduction in operating
Fig. 2. Cell structure of current–magnetic field conversion MRAM now current, suppression of the increase in the current density
starting to be practically applied.21) The current Isense is introduced via the with miniaturization, and the reduction in cell area owing to
bit line of a selection transistor connected to the MTJ, and the resistance the simplified structure. However, the current density at the
is measured. Writing is performed by changing the magnetization MTJ is expected to be as large as 107 A/cm2 ; thus, reliability
direction of the MTJ free layer using the magnetic field generated by
becomes a concern. Moreover, the small magnetoresistance
the current introduced to bit line and digit line. Toggling magnetic field
control is generally used to realize a cross-point cell. ratio of the conventional MTJ still remains an unsolved
problem for spin-transfer torque MRAMs. Although exten-
sive research on spin-transfer torque MRAMs is being
tunnel insulating film such as MgO sandwiched between two carried out, it is still in the exploratory stage.26)
magnetic films deposited as a magnetization fixed layer
(magnetization pinned layer) and a free layer. The magnetic 4. PRAM Technology
moments of the two films are controlled to be parallel (low PRAMs have a simple structure that can be easily mini-
resistance) or antiparallel (high resistance) to each other, so aturized, in which a chalcogenide semiconductor material
that they can be used for information storage. Writing is composed of group VI elements is sandwiched between
performed by introducing current to two adjacent lines for electrodes. Typical chalcogenide materials used for PRAMs
writing (bit line and digit line) and rotating the magnet- include Ge2 Sb2 Te5 and Sb2 Te3 , and systems with improved
ization direction of the free layer using the magnetic field operating speed and thermal stability obtained by doping
produced by the current. impurities into the above materials are also being exten-
The operating principles of MRAMs are clear; they have sively explored.27–29) The operating principle is based on the
been successfully used in practical applications; and the rapid transfer of a chalcogenide semiconductor between
various failure modes are being increasingly understood.22) crystalline and amorphous phases at a relatively low
The high operating speed of MRAMs is their most out- temperature (usually approximately 600  C).30) The energy
standing feature and can be equivalent to that of SRAMs. source used to trigger the phase change is Joule heat
Moreover, unlike FeRAMs, MRAMs have no degradation generated from the current. The electric resistance of the
mode and thus are capable of infinite rewrites. Accordingly, crystalline phase is low, whereas that of the amorphous
MRAMs are expected to be used as universal memories that phase is high. Data are stored in terms of resistance values
combine the functions of both DRAM and SRAM. Current- associated with this nonvolatile change in resistance.
ly, however, they are only used in limited applications, e.g., In PRAMs, the transfer from a high-resistance amor-
in drive recorders as advanced EDRs, as mentioned above.23) phous phase to a low-resistance crystalline phase is called
However, MRAMs currently in practical use require a ‘‘setting’’, and the reverse operation is called ‘‘resetting’’.
large writing current and are not suitable for high-density Figure 3 shows the typical set and reset current pulses
integration because of their complicated device structure. applied to a phase-change device.31) Setting and resetting in
Furthermore, reverse scaling holds, i.e., the current density PRAMs are controlled by current pulses instead of voltage
required to control the magnetic field increases with because the phase state is controlled by Joule heat. Usually,
miniaturization. Therefore, it is difficult to increase the the current saturation characteristics of transistors are used
integration density of MRAMs. In addition, the magneto- to produce current pulses. Therefore, MOS transistors are
resistance ratio of ‘‘1’’ to ‘‘0’’ is 100% or less,24) which is generally used as the selection device in the structure of
another barrier preventing the increase in the integration memory cells.
density of MRAMs. As shown in Fig. 3, a short pulse of approximately 10 ns is
Spin-transfer torque MRAMs have been proposed as a applied to a low-resistance cell to increase the temperature
solution to these problems.25) Unlike the conventional MTJ, of the phase-change material to the melting point or higher
the spin-transfer torque MRAM controls the magnetization in a short time during resetting, and then the material
direction of the free layer by inducing a current between is rapidly cooled to become amorphous. During setting, a
the magnetization pinned layer with aligned spin and the relatively long current pulse (approximately 1 ms) is applied
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Jpn. J. Appl. Phys. 49 (2010) 100001 Comprehensive Review

Fig. 4. (Color online) Set and reset characteristics.32)

Fig. 5. (Color online) Cross-sectional structure of bottom-contact

phase-change device.32)
to the cell to increase the temperature of the phase-change
material above the crystallization temperature but below the
melting point, and then the material is slowly cooled to
promote crystal growth and decrease the resistance of the
device.
When a threshold or higher voltage is applied to a high-
resistance cell during setting, avalanche breakdown occurs,
which is assumed to induce a large current. The band gap
energy of chalcogenide semiconductors is approximately
1 eV, and many chalcogenide materials exhibit a thermo-
electric conversion effect. The occurrence of avalanche
breakdown at a low voltage of approximately 1 V owing to
the relatively narrow band gap characterizes the low-voltage Fig. 6. Edge-contact phase-change device.34)
operation of PRAMs.
Figure 4 plots the typical set and reset characteristics of
PRAMs.32) In the figure, the set and reset currents are current of 100 mA by inserting an insulating film between the
approximately 40 and 100 mA, respectively, and the current plug and the phase-change film to prevent heat dissipa-
required for resetting determines the maximum operating tion.32,33)
current of the PRAMs. The reset current depends on the Figure 6 shows an edge-contact phase-change device.34)
volume of the section that undergoes phase change due to In the device shown in Fig. 5, the device size is determined
Joule heat, and thereby depends on the size of the phase- from the size of the lower electrode plug, and it is impossible
change device. That is, the maximum operating current Jmax to miniaturize the device beyond the limit of lithography
decreases as the size of the device decreases with miniatur- technology. This is unsatisfactory for reducing the current,
ization. Jmax / F 2 (F ¼ minimum feature size) holds as F and therefore, the edge-contact phase-change device in
approaches zero, and therefore, PRAMs are considered to be Fig. 6 was proposed as a solution. The contact area between
suitable for high-density integration. the phase-change film and the electrode is determined from
However, in reality, a large current is required to operate the film thickness of the thin-film electrode, enabling a
the PRAMs. Moreover, the miniaturization of transistors is reduction in the size of the phase-change device beyond the
difficult because of the insufficiency of current drivability limit of lithography. A reset current of 200 mA was achieved
of the cell-selection transistor, thus limiting the extent using this structure.
of miniaturization. To overcome these problems, various Figure 7 shows the structure of a wire phase-change
types of device structure have been proposed with the aim device.35) The cross-sectional area of the phase-change
of reducing the reset current. Some examples are shown section, fabricated in the shape of a wire, determines the
below. phase-change region. The reset current has been decreased to
Figure 5 shows a bottom-contact phase-change device.32) 140 mA (Note that the minimum current of the device, whose
This is the simplest structure, in which a plug is in contact reset characteristics are given in ref. 35, is 140 mA, although
with the bottom of a phase-change film; the extent of the a current of less than 100 mA is stated in the abstract). This
phase-change region is determined from the contact area of structure, however, has a drawback; that is, the fabrication
the plug and the phase-change film. Therefore, the minimum accuracy of the thin wire directly affects the amount of
feature size becomes the limit of device miniaturization, and variation in the reset current. In addition, there is another
it is difficult to reduce the operating current using this problem that applies to lateral devices in general, that is, the
structure. Nevertheless, our group has achieved a reset increase in cell area. Innovative solutions to these problems
100001-4 # 2010 The Japan Society of Applied Physics
Jpn. J. Appl. Phys. 49 (2010) 100001 Comprehensive Review

Table II. Reported values of reset current for various types of phase-
change device.

Device Reset current Reset area Reference Research

structure (mA) (nm2 ) number organization
Bottom-contact
phase-change Hitachi, Ltd.,
100 25434 32, 33
interface layer etc.
structure
Edge-contact
200 4000 34 Samsung
structure
Wire structure 140 90 35 IBM, etc.
Microtrench ST
600 1500 36
structure Microelectronics
Microtrench ST
400 400 37
structure Microelectronics
Bottleneck Aachen
280 3000 38
structure University
Pillar structure 900 197 39 IBM, etc.
Cross-spacer
240 1000 40 ITRI, etc.
structure
Pore structure 450 1451 41 IBM, etc.

Fig. 7. Wire phase-change device (film thicknesses of 3 and 10 nm).35)

Fig. 8. Cross-sectional structure of microtrench phase-change memory.36)

are still necessary to increase the integration density for wire the device is miniaturized by making use of fine pores on
phase-change devices. part of an insulating film during the semiconductor fabrica-
A microtrench structure has been proposed to reduce the tion process. However, few structures have achieved a reset
reset current to realize ultrahigh-density integration.36) current of less than 100 mA with high reproducibility.
Figure 8 shows its cross-sectional structure. The character- Table II shows the reset currents for the structures intro-
istic feature is the small lower electrode achieved using duced above.
a plug-side wall. This vertical structure has high process The 100-Mbit-level sample PRAM devices were being
reproducibility and requires only a small area for installa- shipped from multiple vendors as this article was written,
tion, thus making it suitable for high-density integration. A and PRAMs are in the final stages of practical application.
reset current of 400 mA was achieved for F ¼ 90 nm,37) and PRAMs can be miniaturized more easily than flash mem-
it was observed that this structure had the beneficial effect of ories and are currently considered as their most likely
reducing the operating current; however, the performance is successor; however, their operating current is too large to
still insufficient for practical use. The rewrite endurance of realize ultrahigh-density PRAMs.
the microtrench structure is as good as that of the bottom- If we attempt to fabricate PRAMs with density as high
contact structure, enabling 1011 rewrites, which is greater as that of first-generation 64-Gbit NAND flash memories
than the number of rewrites possible for flash memories. (F ¼ 28 nm), it will be necessary to decrease the reset
Various other structures with high potential have been current to 62 mA or less. The PRAMs must perform better
proposed, such as the bottleneck structure,38) in which a than NAND flash memories to replace them, and a reset
chalcogenide film is constricted, the pillar structure,39) the current of half this value, namely 30 mA or less, should be
cross-spacer structure,40) and the pore structure,41) by which realized by PRAMs (from the ITRS discussed in §7). Thus,
100001-5 # 2010 The Japan Society of Applied Physics
Jpn. J. Appl. Phys. 49 (2010) 100001 Comprehensive Review

significant progress is required before PRAMs can replace

NAND flash memories.
NOR flash memories have a slightly lower integration
density than NAND flash memories, and are mainly used for
storing system programs and user information on a small
scale. The greatest advantages of PRAMs over NOR flash
memories are the low operating voltage and high rewrite
durability. Flash memories require at least 10 V for writing,
whereas PRAMs can be operated at less than 2 V. For system
memories with embedded logic, eliminating the area of
a booster circuit is feasible and beneficial. The rewrite
durability of PRAMs is approximately 105 times higher than
that of NOR Flash memories; thus, the realization of PRAMs
is expected to open new application fields.
In PRAMs, however, it takes 200 – 300 ms for writing, and
the number of rewrites is limited, which makes their practical
use difficult. That is, we cannot use PRAMs as universal
memory that integrates NOR and DRAM in systems. The
current goals in the development of PRAM technology are to
explore the application fields to which the low-voltage
operation and high rewrite durability can contribute and to
continue to develop devices for use in such fields.

5. ReRAM
Fig. 9. One example of I–V characteristics of ReRAM using perovskite
Recently, research on memories using the resistive switching oxide.49)
phenomenon of devices, in which an oxide thin film or a
solid electrolyte film is sandwiched between electrodes, has 5.1.1 ReRAM using perovskite oxide
been actively carried out. Strictly speaking, MRAM and Most of the reported perovskite-oxide systems exhibit
PRAM are also resistive-change memories; in this section, bipolar operation. Figure 9 shows the typical current–
however, memories that operate with a mechanism different voltage (I–V) characteristics49) of a Ti/PCMO/SrRuO3
from those of MRAM and PRAM are collectively regarded (SRO) device structure. The dotted lines represent the first
as ReRAM. ReRAMs are roughly classified into two types: voltage scan, corresponding to the initialization process
one is based on the switching phenomenon of oxides, and the referred to as forming, by which I–V hysteresis occurs. In the
other is based on a chemical reaction in solid electrolytes. second and subsequent scans, the I–V characteristics drawn
We first introduce the memories based on the switching by solid lines are obtained. As clearly shown in the figure,
phenomenon of oxides. the device in a high-resistance state is switched to a low-
resistance state when a positive voltage is applied to its Ti
5.1 ReRAM using metal oxide electrode, and the device in a low-resistance state is switched
It has long been known that metal oxides exhibit switching to a high-resistance state when a negative voltage is applied.
behavior; the switching of some oxides, such as Al2 O3 and In the above example, the resistive change is caused by
NiO, was reported in the 1960s.42,43) Around the same time, the change in the Schottky barrier at the interface between
the concept of PRAM was also proposed by Ovshinsky,44) Ti and PCMO owing to the electric charges trapped at the
increasing expectations for the application of resistive- energy level of the interface. Although it is clear that the
change devices to memories. However, nonvolatile semi- fundamental feature of I–V characteristics comes from
conductor memories soon faded because many of their the Schottky barrier, the thermal stability of the device is
operating mechanisms were unclear, and magnetic recording questionable when assuming that the switching phenomenon
media were introduced. In the situation wherein flash is caused by the trapping of electric charges at the energy
memories have recently become common and their technol- level of the interface. There is another similar model in
ogy is reaching its limits, a research group at the University which the space-charge-limited current (SCLC) is assumed
of Houston introduced an integrated memory, ReRAM using to be the cause of the resistive change.50) In this model, it
Pr0:7 Ca0:3 MnO3 (PCMO).45,46) This triggered widespread is also assumed that the defect level near the electrode
research on ReRAMs. interface is related to the switching; however, problems still
ReRAMs using a metal oxide are further classified into remain in terms of the stability of nonvolatile operation.
two types: those using perovskite oxides such as PCMO and In a similar analysis focusing on the electrode interface, a
SrTiO3 (STO), and those using binary oxides such as NiO model in which the switching is assumed to originate from
and HfO2 . The former type mostly exhibits bipolar oper- the movement of oxygen holes in and out of the electrode
ation, whereas the latter can mostly realize unipolar (non- interface in an SRO/Nb:STO system has been proposed.51)
polar) operation. Moreover, their switching mechanism has In this mechanism, oxygen vacancies move following the
not necessarily been clarified, and we only briefly outline application of an electric field and the Schottky barrier
this classification here. For details, please refer to the review between SRO and STO changes, causing resistive switching.
articles.47,48) The relationship between the compliance current during
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Jpn. J. Appl. Phys. 49 (2010) 100001 Comprehensive Review

Fig. 10. (Color online) Switching model based on oxygen ion diffusion along crystal defects.52)

ON operation and the ON resistance can be well explained when the vacancies are aligned and connected to the upper
in this model. and lower electrodes in the form of a filament.
Figure 10 shows an example of the resistive switching Regarding the PCMO ReRAM, which sparked the boom
of bulk STO observed by analyzing single-crystal STO at of ReRAMs, a model for which a Mott transition of the
a very small current by mapping using a scanning probe PCMO bulk from a metal to an insulator is assumed has been
microscope (SPM).52) Oxygen ions diffuse through the proposed; however, there are objections to the theory that a
numerous crystal defect networks existing in STO when phenomenon associated with strongly correlated electrons
the SPM probe comes into contact with an exposed occurs in a polycrystalline thin film at room temperature.
section on the surface of the crystal. For example, when a Complementary models in which the occurrence of a Mott
negative voltage is applied to the probe, oxygen ions diffuse transition of a filament53) and an interface54) is considered
along the crystal defect networks, forming an oxygen- are being developed.
vacancy filament, which is highly conductive. In contrast, As discussed above, there are many theories on the
when a positive voltage is applied, oxygen ions flow switching mechanism, but no definitive theory has yet been
into the oxygen-vacancy filament, and the conduction established. We must continuously strive to clarify the
path is ruptured. Thus, it can be assumed that the STO mechanism with the aim of developing practical devices.
bulk has its own mechanism that causes the change in The issues regarding the application of perovskite ReRAM
resistance. are summarized below.
A number of oxygen vacancies are present in perovskite Most ReRAMs using a perovskite oxide exhibit bipolar
oxides and act as donors. These oxygen vacancies may serve switching and require the application of a positive or
as a conduction path that can allow a current to easily flow negative voltage for their operation. To be used in ultrahigh-
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Jpn. J. Appl. Phys. 49 (2010) 100001 Comprehensive Review

Fig. 11. Nonpolar operating ReRAM of Nb:STO system.55)

density integration, a cross-point cell structure using a diode As introduced above, ReRAMs using a perovskite oxide
for the cell selection device is advantageous; however, a are still in the switching mechanism analysis stage, and
diode cannot be used for the cell selection device in bipolar- sufficient information to judge their suitability for future flash
operating memories. Therefore, vertical-structure MOS memories has not yet been obtained. Moreover, ReRAMs
transistors or bipolar transistors must be used to apply the using a perovskite oxide, which is a multi-component oxide,
ReRAMs with a perovskite oxide to ultrahigh-density are not particularly suitable for ultrahigh-density integration
integration. because of their bipolar operation and inconsistent character-
Next, the operating speeds of ReRAMs using a perovskite istics depending on the composition. However, ReRAMs
oxide are generally high for both writing and readout; many using a perovskite oxide have high potential as a convenient
of them have achieved an operating time on the order of RAM owing to their switching speed, which is generally
100 ns. However, it has been frequently reported that the higher than that of other types of ReRAM and PRAMs.
resistance ratio is small and insufficiently reliable unless Therefore, replacing NOR+DRAM in small systems is
readout is performed at an extremely low voltage (in general, thought to be the most effective way of utilizing the
the lower the voltage, the higher the resistance ratio). The advantages of ReRAMs using a perovskite oxide.
lower limit of the readout voltage is approximately 0.3 V
from the viewpoint of practical use, and we must develop 5.1.2 ReRAM using binary transition-metal oxide
a method of ensuring a resistance ratio of at least 10 times Many types of nonvolatile memory in which a binary
at this voltage. The number of rewrites, which has been transition-metal oxide is sandwiched between oxide elec-
reported in only a few papers, is generally approximately trodes made of a precious-metal oxide or IrO2 have been
1000 except for certain experimental cases. Moreover, the proposed since 2005, when the fabrication of a prototype
durability of data retention has seldom been discussed. cross-point memory using a device in which NiO was
Figure 11 shows an exceptional ReRAM in which almost sandwiched between two Pt electrodes was reported.56) The
all the above issues were resolved.55) This ReRAM has a oxides used for such devices include NiO, TiO2 , and HfO2 ,
structure of Pt/Nb:STO/Si/Pt with nonpolar operation. all of which have an oxygen-deficient composition. For
Although the writing speed is slightly low, i.e., 300 ms is electrodes, Pt is most frequently used, and IrO2 has also been
required at 3.6-V operation, high durability of 106 rewrites used in a few cases.
with data retention for up to 106 s at 125  C has been All devices using a binary transition-metal oxide exhibit
reported. Because this ReRAM requires a relatively long nonpolar operation and are capable of forming a simple
time to switch to a high-resistance state and exhibits cross-point cell structure combined with a diode, thus
nonpolar operation unlike other types of ReRAM using a making them suitable for ultrahigh-density integration.
perovskite oxide, its operating principle is considered to be However, the switching mechanism of such devices has
similar to that of the ReRAM using Pt/TiO2 introduced in not been fully clarified yet. Currently, the following theory
the following section. For ReRAMs using a TiO2 system, the based on the analysis of impedance data is considered most
switching phenomenon may be caused by a filamentary likely: switching is caused by the formation and rupture of a
conduction path that is formed and ruptured during a redox filamentary conduction path as a result of a redox reaction
reaction on the electrode interface. of the oxides on the electrode interface.57)
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Fig. 12. Nonpolar ReRAM with Pt/NiO/Pt and Pt/IrO2 /NiO/IrO2 /Pt structures.58) Rewriting becomes more stable when IrO2 is used for the NiO
interface.

Fig. 13. Pulse operation of ReRAM with Pt/TiON/TiN structure.66)

Figure 12 shows the switching characteristics of ReRAMs electrode materials64) have been investigated in an attempt
with Pt/IrO2 /NiO/IrO2 /Pt and Pt/NiO/Pt structures.58) to determine the operating principles. The switching phe-
When an increasing DC voltage is applied to the devices, nomenon has also been confirmed for various types of
which are initially in the low-resistance state, switching from material, including WOx 65) and SiO2 .
a low-resistance state to a high-resistance state occurs (the As is clear from the above example, nonpolar switching
current sharply decreases) at a certain voltage (approxi- devices mostly require a long time for writing even for a
mately 0.8 V in the figure). When the voltage applied to the pulse operation. To solve this problem, a ReRAM using
high-resistance device is increased further, the high-resist- TiONx was proposed.66) The characteristics of its pulse
ance state is, in turn, switched to a low-resistance state. This operation are shown in Fig. 13.
switching phenomenon becomes stable when Pt/IrO2 is used In this ReRAM report, during the ON operation, a load
for the electrodes. The resistive change shown in Fig. 12 resistance of 22 k is inserted in series into the circuit, and a
involves no polarity, and will similarly occur when a pulsed voltage of 4.5 V/50 ns is applied. During the OFF
negative voltage is applied. However, the switching speed is operation, a pulsed voltage of 2.5 V/50 ns is applied without
low, and only DC characteristics are presented in most of the a load resistance. Inserting load resistance during the ON
reports. Similar phenomena were confirmed for HfO2 ,59,60) operation prevents excess current from flowing when the
TiO2 ,61,62) and other oxides. In the case of TiO2 , pulse device switches to a low-resistance state, and prevents the
operation was also reported.63) device from returning to the high-resistance state. Although
The pulse-based device has a Pt/TiO/TiN/W structure, high-speed writing was achieved in their study, the number
and the author considers its switching to be caused by the of rewrites was limited to only about 12 –13, as shown
conduction path that is formed and ruptured by the move- in Fig. 13, and many technological issues still remain.
ment of oxygen ions at the electrode interface, similar to the Recently, a paper on resolving these issues using Ti-doped
model proposed for perovskite STO. In the switching from a NiO has been published,67) and the number of rewrites has
high-resistance state to a low-resistance state (ON opera- been markedly increased to 100; however, it will still take a
tion), a pulsed voltage of 2 V/20 ns is applied, whereas in the long time to practically realize this device.
switching from a low-resistance state to a high-resistance The characteristic feature of ReRAMs using a binary
state (OFF operation), a pulsed voltage of 2.5 V/5 ms is transition-metal oxide is nonpolar operation, which makes
applied. In the case of NiO, the effect of amorphous NiO and them more suitable for ultrahigh-density integration than
the extent to which the performance depends on the bipolar-operating ReRAMs using a perovskite oxide. How-
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Jpn. J. Appl. Phys. 49 (2010) 100001 Comprehensive Review

Fig. 14. (Color online) Model using filamentary path formed by Cu ions
in solid electrolyte.69)
Fig. 15. (Color online) Switching characteristics of ReRAM with Ag/
Ag2 Se+GeSe/W structure.69)
ever, the instability in nonpolar-operating devices caused by
switching of the resistance state remains a problem. More-
over, other issues to be considered for high-density inte-
gration, such as the parasitic capacitance of wires and
interference between bits, have been pointed out because the
current induced during ON operation affects the resistance of
a device in the low-resistance state, RLOW .68) The switching
mechanism should also be analyzed to clarify the actual
status of the filament path. The reason why the number of
rewrites was as small as approximately 100 is probably
because the distribution of the materials forming a filamen-
tary conduction path becomes uneven when a unidirectional
voltage is applied. The first priority for this type of ReRAM
is a detailed analysis of the switching mechanism.

5.2 ReRAM using solid electrolyte

A solid electrolyte is a material that allows ions, whether
organic or inorganic, to freely move inside it. Solid
electrolytes are used for batteries, gas sensors, and other
applications. When metals with high diffusion speed, such as Fig. 16. Cross-sectional structure of ReRAM that supplies Cu ions to
Ag and Cu, are doped into a solid electrolyte, it becomes Ta2 O5 solid electrolyte and schematic of its operation.72)
possible to control the movement of these metallic ions
using the electric field generated from electrodes. Various
types of ReRAM that can achieve a switching operation by low voltage, has led to the development of solid electrolyte
applying an appropriate voltage and controlling the forma- memories. Figure 15 shows the switching characteristics
tion and rupture of a filamentary conduction path in the solid of the Ag/Ag2 Se+GeSe/W memory. Moreover, a memory
electrolyte have been proposed. Figure 14 shows a sche- using GeS, which has high thermal stability at 100  C or
matic of resistive switching due to the formation of a Ag higher,70) instead of GeSe, is also being examined.
bridge in a solid electrolyte.69) In this study, Ag ions were Large-scale integration is also being increasingly dis-
supplied from a Ag electrode that was placed on one side of cussed, and a prototype with a memory on the order of
the solid electrolyte film. 2 Mbits fabricated by integrating the device shown in Fig. 15
As solid electrolytes, Ag halides and chalcogenide has been reported.71) Using this device, a writing time as
crystals, such as AgI, Ag2 S, Ag2 Se, and Ag2 Te, have been short as 50 ns and 106 rewrites were achieved. However,
widely investigated; however, no significant progress has Fig. 15 shows that switching occurs at an extremely low
been achieved when the switching devices using these voltage of less than 0.1 V. It is therefore difficult to apply the
binary materials have been examined because their ion prototype device to practical highly integrated memories
conductivity is low at room temperature and is easily unless its characteristics are improved.
changed by even a slight change in composition. A ReRAM that switches in accordance with the formation
In contrast, the systems in which Ag or Cu is doped into and rupture of a filament path of Cu ions has also been
a glass compound (chalcogenide compound) containing a proposed in addition to a ReRAM that switches upon the
group VI element, namely, O, S, Se, or Te, or into a stable formation and rupture of a filament path of Ag ions.72) Ta2 O5
binary amorphous film comprising Si, Ge, As, and other is used for the solid electrolyte, and Cu ions are supplied
elements have high ionic conductivity, and the fabrication of from a Cu electrode. Figure 16 shows the cross-sectional
numerous prototype memories based on these systems has device structure and a schematic of its operation. The Cu
been reported. In particular, the Ag/Ag2 Se+GeSe/W electrode, which supplies Cu ions, is placed next to a solid
system, which exhibits stable switching characteristics at a Ta2 O5 electrolyte. In ref. 72, Cu2 S is also used for the solid
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Jpn. J. Appl. Phys. 49 (2010) 100001 Comprehensive Review

electrolyte, and the characteristics were compared between appears when a film of P(VDF–TrFE) is formed under
Cu2 S and Ta2 O5 . The switching voltage, which is approx- appropriate conditions. The ferroelectricity of P(VDF–TrFE)
imately 0.2 V for Cu2 S, increases to 0.6 V or higher when was discovered in the 1960s76) and has been practically used
Ta2 O5 , a high-resistance solid electrolyte, is used, which is a in piezoelectric devices and sensors; however, owing to the
practical operating voltage. This result indicates the direc- difficulty in reducing the film thickness, it has not been
tion the development of a method to control the switching investigated for use in memory devices.
voltage will take. Our group succeeded in reducing the film thickness to less
Fundamentally, memories based on solid electrolytes than 60 nm and achieved a remnant polarization of greater
exhibit bipolar operation and are not suitable for ultrahigh- than 10 mC/cm2 despite the small thickness.77) This would
density integration. However, solid electrolyte memories can enable a memory to operate at 2 V or lower.78) Recently, a
relatively easily realize a fast writing time of approximately prototype nonvolatile memory transistor fabricated on a
50 ns and as many as 104 –106 rewrites and, in this regard, flexible substance has been reported,79) and thus, research
are superior to oxide-based ReRAMs. Conversely, because with the aim of realizing applications different from those
Cu and Ag, both with an extremely high thermal diffusion based on conventional nonvolatile memories is being
coefficient, are used in these devices, there are temperature intensively carried out.80)
restrictions during the fabrication of these devices, thus The marked advantage of organic memories over those
limiting the flexibility of fabrication. However, there are based on conventional inorganic materials is the capability
various types of solid electrolytes, and therefore high of expressing their functions using a single constituent
expectations, for the discovery of new materials that can molecule. Therefore, downscaling to the subnanometer scale
solve the current problems such as insufficient retention time or smaller may become possible. However, many organic
due to the extremely low operating voltage and the low substances are vulnerable to heat and ultraviolet light, and
number of rewrites at only 106 . There is much hope for only a few can endure the fabrication process of Si LSI.
future research on, for example, the exploration of new Organic memories are expected to be most applicable
materials that can overcome the shortcomings of current in application fields where low-temperature processes
solid electrolyte memories and the establishment of fabri- are possible, such as in thin-film transistors and organic
cation processes. transistors, rather than in combination with Si MOS.
6. Organic Memory 7. Conclusions
Research on memories that combine a silicon semiconductor The current status of nonvolatile semiconductor memory
and an organic thin film is also being carried out intensively. technology was overviewed. The author introduced only
A molecule of an organic substance is of subnanometer to a small portion of the various memories being proposed,
nanometer size, and the marked downscaling of memory and many other innovative ideas are being proposed and
cells will be realized if molecular-level reactions can be reported. The International Technology Roadmap for Semi-
utilized for storing information. Organic memories are conductors (ITRS)81) publishes an annual report focusing on
classified into several categories, including those using redox various technologies, such as semiconductor technology and
reactions of molecules, those with a filamentary conduction fabrication technology. In the report, the nonvolatile semi-
path formed at the electrode interface similarly to oxide- conductor memories introduced in this article are classified
based ReRAMs, and those using organic ferroelectrics. using three tables. One is the main table summarizing the
For capacitor-type devices in which an organic molecular memories that have already been used in practice, such as
thin film made of Cu-tetracyanoquinodimethane (CuTCNQ) flash memories, FeRAM, and MRAM,82) and PRAM has
is sandwiched between Cu and Al electrodes, the precip- recently been added to this table. This may be an appropriate
itation of Cu can be controlled using a redox reaction of decision considering the fact that the shipping of sample
CuTCNQ, and a switching phenomenon thus occurs.73) The PRAMs has started.
characteristics of its operation are similar to those of the The second table is a detailed classification of emerging
operation of inorganic bipolar ReRAMs; namely, switching research on resistance-based memory devices currently
occurs at approximately 3 V. It has also been reported that being studied, which particularly emphasizes their catego-
the model based on a filament formed by Cu precipitation rization.83) Most types of ReRAM and organic memories are
cannot explain the switching to a low-resistance state included in this table. However, this table suffers from a lack
because the conduction characteristics of the device in the of space, and it is difficult to compare the given performance
low-resistance state are similar to those of semiconduc- indices. This is because ReRAMs and organic memories
tors.74) In addition, similar phenomena have been confirmed operate on the basis of various types of mechanisms, and this
for various other materials, including 2-amino-4,5-imida- difficulty of comparison is expected to continue for the time
zoledicarbonitrile (AIDCN).75) However, the mechanism being. The memories whose operating principles have been
underlying the resistive changes of most memories using clarified, such as ferroelectric gate transistors, are summa-
organic molecules still remains unclear, and we await the rized in the third table,84) from which the issues yet to be
results of future research. resolved can be clearly understood.
A random copolymer of vinylidene fluoride (VDF) and In addition, there is the Transition Table,85) which
trifluoroethylene (TrFE), namely, P(VDF–TrFE), is an illustrates the technologies that are expected to be included
organic material that exhibits ferroelectricity similarly to or excluded from the above three tables in the future; i.e.,
ferroelectric oxides. P(VDF–TrFE) is a crystalline organic memories that may be added to the main table if their
material, and the -phase, which exhibits ferroelectricity, research and development progresses, and those that may be
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Jpn. J. Appl. Phys. 49 (2010) 100001 Comprehensive Review

excluded from the table because of the lack of progress in sional miniaturization of NAND flash memories. Currently
research are listed in the Transition Table. In 2007, single the most advanced NAND flash memory uses technology
electron memory was excluded from the main table and with a scale of less than 30 nm, and this value is expected to
removed from the evaluation targets. reach 20 nm in the next few years. This trend has stimulated
The future of new types of nonvolatile memory can be research on new types of nonvolatile memories. The second
understood by following the discussion on the ITRS website, most significant development between 2008 and 2010 is that
which is available to everyone, and we recommend that PRAM has become commercially available. Although its
readers study the Roadmap thoroughly. To replace the density is much lower than that of NAND flash, this epoch-
practically used types of memory listed in the main table, making step opens the door to a new application field of
new memories are required to have significant advantages. nonvolatile memories. The understanding of the physics
In the future, various applications of electronic equipment underlying ReRAM has also increased together with the
will be continuously developed, and various types of improvement of performance90,91). Most of the above mem-
memory are thereby required for a ubiquitous-computing ories have a number of rewrites exceeding 105 cycles.
society. Flash memories are highly advantageous in specific The author is now confident that the semiconductor
fields but have some weaknesses. There is still room for the nonvolatile memory industry will grow much more rapidly
development of new types of nonvolatile memory, including than in the past decade if the currently emerging new mem-
ReRAM, that can compensate for the weaknesses of flash ories capture a small share of the market and are fabricated
memories. by mass production.
For their practical application, nonvolatile memories must
demonstrate a reliable nonvolatile performance. Perform-
ance reliability must be ensured for ten years in general; 1) International Technology Roadmap for Semiconductors, 2007 Edition,
however, nonvolatile memories will not be commercially Emerging Research Devices, p. 7 [Table ERD3].
2) K. Kim, J. H. Choi, J. Choi, and H.-S. Jeong: Proc. Int. Symp. VLSI
successful if it takes ten years to confirm the performance
Technology, 2005, p. 88.
reliability. Thus, accelerated aging tests are needed. This is 3) A. Fazio: MRS Bull. 29 (2004) 814.
an inherent problem of nonvolatile memories. 4) H. Tanaka, M. Kido, K. Yahashi, M. Oomura, R. Katsumata, M. Kito, Y.
For an accurate estimation of memory performance in an Fukuzumi, M. Sato, Y. Nagata, Y. Matsuoka, Y. Iwata, H. Aochi, and A.
accelerated aging test, we must precisely understand the Nitayama: Proc. Int. Symp. VLSI Technology, 2007, p. 14.
5) N. Shibata, H. Maejima, K. Isobe, K. Iwasa, M. Nakagawa, M. Fujiu, T.
physics underlying the deterioration due to accelerated
Shimizu, M. Honma, S. Hoshi, T. Kawaai, K. Kanebako, S. Yoshikawa,
aging. To this end, the operating principles of a device and H. Tabata, A. Inoue, T. Takahashi, T. Shano, Y. Komatsu, K. Nagaba, M.
its underlying physics must be understood. These require- Kosakai, N. Motohashi, K. Kanazawa, K. Imamiya, and H. Nakai: Proc.
ments raise the hurdle for nonvolatile memories in terms of Int. Symp. VLSI Circuits, 2007, p. 190.
reliability much more than for other electronic devices. The 6) H. M. White, D. A. Adams, and J. Bu: IEEE Circuits Devices Mag. 16
(2000) 22.
operation of many of the nonvolatile memories currently
7) B. Eitan, P. Pavan, I. Bloom, E. Aloni, A. Frommer, and D. Finzi: IEEE
being proposed is based on new principles, and therefore, Electron Device Lett. 21 (2000) 543.
they must overcome this high hurdle before practical 8) T. M. Kowalick: Vehicular Technology Conf., 2001, Vol. 4, p. 3037.
application. This is why it has taken a long time to com- 9) Y. M. Kang, H. J. Joo, J. H. Park, S. K. Kang, J.-H. Kim, S. G. Oh, H. S.
mercialize FeRAMs and MRAMs for practical use and Kim, Y. J. Kang, J. Y. Jung, D. Y. Choi, E. S. Lee, S. Y. Lee, H. S. Jeong,
and K. Kim: Proc. Int. Symp. VLSI Technology, 2006, p. 124.
why these memories are still struggling in the market. To
10) T. Nakamura, Y. Nakao, A. Kamisawa, and H. Takasu: Appl. Phys. Lett.
practically apply new types of nonvolatile semiconductor 65 (1994) 1522.
memory, we need a different way of thinking; that is, we 11) M. Tajiri and H. Nozawa: Jpn. J. Appl. Phys. 40 (2001) 5590.
must foster their technology by exploring new application 12) C. A. Araujo, J. D. Cuchiaro, L. D. McMillan, M. C. Scott, and J. F. Scott:
fields with fewer difficulties to achieve the mass production Nature 374 (1995) 627.
13) B. H. Park, B. S. Kang, S. D. Bu, T. W. Noh, J. Lee, and W. Jo: Nature
of such memories for use in these fields.
401 (1999) 63.
14) Y. Fujisaki, K. Iseki, and H. Ishiwara: Jpn. J. Appl. Phys. 42 (2003) L267.
Acknowledgement
15) J. Wang, J. B. Neaton, H. Zheng, V. Nagarajan, S. B. Ogale, B. Liu, D.
The author expresses his sincere thanks to the staff of the Viehland, V. Vaithyanathan, D. G. Schlom, U. V. Waghmare, N. A.
Solution LSI Center, Central Research Laboratory, Hitachi, Spaldin, K. M. Rabe, M. Wuttig, and R. Ramesh: Science 299 (2003)
1719.
Ltd., for their cooperation.
16) S. K. Shin, H. Ishiwara, K. Sato, and K. Maruyama: J. Appl. Phys. 102
(2007) 094109.
Appendix
17) N. Nagel, R. Bruchhaus, K. Hornik, U. Egger, H. Zhuang, H.-O. Joachim,
This paper was originally published in Oyo Buturi in 2008 T. Röhr, G. Beitel, T. Ozaki, and I. Kunishima: Proc. Int. Symp. VLSI
and translated from Japanese to English in 2010. Since its Technology, 2004, p. 146.
18) J. L. Moll and Y. Tarui: IEEE Trans. Electron Devices 10 (1963) 338.
publication in Oyo Buturi, great progress has been made
19) Y. Arimoto and H. Ishiwara: MRS Bull. 29 (2004) No. 11, 823.
in memory technology as a result of intensive research. This 20) Y. Fujisaki and H. Ishiwara: Mater. Res. Soc. Symp. Proc. 830 (2005) 64.
means that some of the main text should be modified. The 21) G. Grynkewich, J. Akerman, P. Brown, B. Butcher, R. W. Dave, M.
greatest achievement during the last two years has been DeHerrera, M. Durlam, B. N. Engel, J. Janesky, S. Pietambaram, N. D.
the accelerated miniaturization of NAND flash memories. Rizzo, J. M. Slaughter, K. Smith, J. J. Sun, and S. Tehrani: MRS Bull. 29
(2004) No. 11, 818.
A symbolic trend could be observed at the 2009 VLSI
22) J. Åkerman, P. Brown, B. Butcher, R. Dave, M. DeHerrera, M. Durlam,
Technological Symposium in Kyoto, where several pa- B. Engel, E. Fuchs, M. Griswold, G. Grynkewich, J. Janesky, J. Martin,
pers86–89) on three-dimensional NAND flash memories were J. Nahas, S. Pietambaram, N. Rizzo, J. Slaughter, K. Smith, J.-J. Sun, and
presented. This trend reflects the limitation of two-dimen- S. Tehrani: Mater. Res. Soc. Symp. Proc. 830 (2005) 191.

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Jpn. J. Appl. Phys. 49 (2010) 100001 Comprehensive Review

23) T. Sugibayashi, T. Honda, N. Sakimura, K. Nagahara, S. Miura, K. 51) S. H. Jeon, B. H. Park, J. Lee, B. Lee, and S. Han: Appl. Phys. Lett. 89
Shimura, K. Tsuji, Y. Fukumoto, H. Honjo, T. Suzuki, Y. Kato, S. Saito, (2006) 042904.
N. Kasai, H. Numata, N. Oshima, R. Nebashi, K. Suemitsu, T. Mukai, K. 52) K. Szot, W. Speier, G. Bihlmayer, and R. Waser: Nat. Mater. 5 (2006)
Mori, S. Fukami, N. Ishiwata, H. Hada, and S. Tahara: IEICE Tech. Rep. 312.
ICD 106 (2006) No. 2, p. 61 [in Japanese]. 53) R. Fors, S. I. Khartsev, and A. M. Grishin: Phys. Rev. B 71 (2005)
24) S. Tehrani: IEDM Tech. Dig., 2006, p. 585. 045305.
25) K. Miura, T. Kawahara, R. Takemura, J. Hayakawa, S. Ikeda, R. Sasaki, 54) M. J. Rozenberg, I. H. Inoue, and M. J. Sánchez: Appl. Phys. Lett. 88
H. Takahashi, H. Matsuoka, and H. Ohno: Proc. Int. Symp. VLSI (2006) 033510.
Technology, 2007, p. 234. 55) D. Choi, D. Lee, H. Sim, M. Chang, and H. Hwang: Appl. Phys. Lett. 88
26) Y. Huai: AAPPS Bull. 18 (2008) No. 6, 33. (2006) 082904.
27) H. Horii, J. H. Yi, J. H. Park, Y. H. Ha, I. G. Beak, S. O. Park, Y. N. 56) I. G. Baek, D. C. Kim, M. J. Lee, H.-J. Kim, E. K. Yim, M. S. Lee, J. E.
Hwang, S. H. Lee, Y. T. Kim, K. H. Lee, U. I. Chung, and J. T. Moon: Lee, S. E. Ahn, S. Seo, J. H. Lee, J. C. Park, Y. K. Cha, S. O. Park, H. S.
Proc. Int. Symp. VLSI Technology, 2003, p. 177. Kim, I. K. Yoo, U.-I. Chung, J. T. Moon, and B. I. Ryu: IEDM Tech. Dig.,
28) N. Matsuzaki, K. Kurotsuchi, Y. Matsui, O. Tonomura, N. Yamamoto, Y. 2005, p. 750.
Fujisaki, N. Kitai, R. Takemura, K. Osada, S. Hanzawa, H. Moriya, T. 57) Y. You, B. So, J. Hwang, W. Cho, S. Lee, T. Chung, C. Kim, and K. An:
Iwasaki, T. Kawahara, N. Takaura, M. Terao, M. Matsuoka, and M. Appl. Phys. Lett. 89 (2006) 222105.
Moniwa: IEDM Tech. Dig., 2005, p. 738. 58) D. C. Kim, M. J. Lee, S. E. Ahn, S. Seo, J. C. Park, I. K. Yoo, I. G. Baek,
29) T. Morikawa, K. Kurotsuchi, M. Kinoshita, N. Matsuzaki, Y. Matsui, Y. H. J. Kim, E. K. Yim, J. E. Lee, S. O. Park, H. S. Kim, U.-I. Chung, J. T.
Fujisaki, S. Hanzawa, A. Kotabe, M. Terao, H. Moriya, T. Iwasaki, M. Moon, and B. I. Ryu: Appl. Phys. Lett. 88 (2006) 232106.
Matsuoka, F. Nitta, M. Moniwa, T. Koga, and N. Takaura: IEDM Tech. 59) I. Park, K. Kim, S. Lee, and J. Ahn: Jpn. J. Appl. Phys. 46 (2007) 2172.
Dig., 2007, p. 307. 60) K. Kinoshita, C. Yoshida, H. Aso, M. Aoki, and Y. Sugiyama: Ext. Abstr.
30) M. Wuttig and N. Yamada: Nat. Mater. 6 (2007) 824. Int. Conf. Solid State Devices and Materials, 2006, p. 570.
31) S. Hudgens and B. Johnson: MRS Bull. 29 (2004) No. 11, 829. 61) M. Fujimoto, H. Koyama, M. Konagai, Y. Hosoi, K. Ishihara, S. Ohnishi,
32) Y. Fujisaki, N. Matsuzaki, K. Kurotsuchi, T. Morikawa, M. Kinoshita, N. and N. Awaya: Appl. Phys. Lett. 89 (2006) 223509.
Kitai, S. Hanzawa, H. Moriya, N. Takaura, M. Terao, M. Matsuoka, T. 62) D. S. Jeong, H. Schroeder, and R. Waser: Appl. Phys. Lett. 89 (2006)
Koga, and M. Moniwa: Mater. Res. Soc. Symp. Proc. 997 (2007) 293. 082909.
33) Y. Matsui, K. Kurotsuchi, O. Tonomura, T. Morikawa, M. Kinoshita, Y. 63) B. Choi, S. Choi, K. Kim, Y. Shin, C. Hwang, S. Hwang, S. Cho, S. Park,
Fujisaki, N. Matsuzaki, S. Hanzawa, M. Terao, N. Takaura, H. Moriya, T. and S. Hong: Appl. Phys. Lett. 89 (2006) 012906.
Iwasaki, M. Moniwa, and T. Koga: IEDM Tech. Dig., 2006, p. 769. 64) C. B. Lee, B. S. Kang, M. J. Lee, S. E. Ahn, G. Stefanovich, W. X.
34) Y. H. Ha, J. H. Yi, H. Horii, J. H. Park, S. H. Joo, S. O. Park, U.-I. Chung, Xianyu, J. B. Park, and B. H. Park: Appl. Phys. Lett. 91 (2007) 082104.
and J. T. Moon: Proc. Int. Symp. VLSI Technology, 2003, p. 175. 65) C. Ho, E. K. Lai, M. D. Lee, C. L. Pan, Y. D. Yao, K. Y. Hsieh, R. Liu,
35) Y. C. Chen, C. T. Rettner, S. Raoux, G. W. Burr, S. H. Chen, R. M. and C. Y. Lu: Proc. Int. Symp. VLSI Technology, 2007, p. 228.
Shelby, M. Salinga, W. P. Risk, T. D. Happ, G. M. McClelland, M. 66) Y. Hosoi, Y. Tamai, T. Ohnishi, K. Ishihara, T. Shibuya, Y. Inoue, S.
Breitwisch, A. Schrott, J. B. Philipp, M. H. Lee, R. Cheek, T. Nirschl, M. Yamazaki, T. Nakano, S. Ohnishi, N. Awaya, H. Inoue, H. Shima, H.
Lamorey, C. F. Chen, E. Joseph, S. Zaidi, B. Yee, H. L. Lung, R. Akinaga, H. Takagi, H. Akoh, and Y. Tokura: IEDM Tech. Dig., 2006,
Bergmann, and C. Lam: IEDM Tech. Dig., 2006, p. 777. p. 793.
36) F. Pellizzer, A. Pirovano, F. Ottogalli, M. Magistretti, M. Scaravaggi, P. 67) K. Tsunoda, K. Kinoshita, H. Noshiro, Y. Yamazaki, T. Iizuka, Y. Ito, A.
Zuliani, M. Tosi, A. Benvenuti, P. Besana, S. Cadeo, T. Marangon, R. Takahashi, A. Okano, Y. Sato, T. Fukano, M. Aoki, and Y. Sugiyama:
Morandi, R. Piva, A. Spandre, R. Zonca, A. Modelli, E. Varesi, T. IEDM Tech. Dig., 2007, p. 767.
Lowrey, A. Lacaita, G. Casagrande, P. Cappelletti, and R. Bez: Proc. Int. 68) K. Kinoshita, K. Tsunoda, Y. Sato, H. Noshiro, Y. Yamazaki, T. Fukano,
Symp. VLSI Technology, 2004, p. 18. S. Yagaki, M. Aoki, and Y. Sugiyama: Proc. Non-Volatile Semiconductor
37) F. Pellizzer, A. Benvenuti, B. Gleixner, Y. Kim, B. Johnson, M. Memory Workshop, 2007, p. 66.
Magistretti, T. Marangon, A. Pirovano, R. Bez, and G. Atwood: Proc. Int. 69) M. Kund, G. Beitel, C.-U. Pinnow, T. Röhr, J. Schumann, R. Symanczyk,
Symp. VLSI Technology, 2006, p. 122. K.-D. Ufert, and G. Mueller: IEDM Tech. Dig., 2005, p. 754.
38) F. Merget, D. H. Kim, P. H. Bolivar, and H. Kurz: Microsyst. Technol. 13 70) X. Feng, W. J. Bresser, and P. Boolchand: Phys. Rev. Lett. 78 (1997)
(2007) 169. 4422.
39) T. D. Happ, M. Breitwisch, A. Schrott, J. B. Philipp, M. H. Lee, R. Cheek, 71) H. Hönigschmid, M. Angerbauer, S. Dietrich, M. Dimitrova, D. Gogl, C.
T. Nirschl, M. Lamorey, C. H. Ho, S. H. Chen, C. F. Chen, E. Joseph, S. Liaw, M. Markert, R. Symanczyk, L. Altimime, S. Bournat, and G.
Zaidi, G. W. Burr, B. Yee, Y. C. Chen, S. Raoux, H. L. Lung, R. Müller: Proc. Int. Symp. VLSI Circuits, 2006, p. 110.
Bergmann, and C. Lam: Proc. Int. Symp. VLSI Technology, 2006, p. 120. 72) T. Sakamoto, N. Banno, N. Iguchi, H. Kawaura, H. Sunamura, S. Fujieda,
40) W. S. Chen, C. Lee, D. S. Chao, Y. C. Chen, F. Chen, C. W. Chen, R. K. Terabe, T. Hasegawa, and M. Aono: Proc. Int. Symp. VLSI
Yen, M. J. Chen, W. H. Wang, T. C. Hsiao, J. T. Yeh, S. H. Chiou, M. Y. Technology, 2007, p. 38.
Liu, T. C. Wang, L. L. Chein, C. Huang, N. T. Shih, L. S. Tu, D. Huang, 73) R. Müller, J. Genoe, and P. Heremans: Appl. Phys. Lett. 88 (2006)
T. H. Yu, M. J. Kao, and M.-J. Tsai: IEDM Tech. Dig., 2007, p. 319. 242105.
41) M. Breitwisch, T. Nirschl, C. F. Chen, Y. Zhu, M. H. Lee, M. Lamorey, 74) R. Müller, R. Naulaerts, J. Billen, J. Genoe, and P. Heremans: Appl. Phys.
G. W. Burr, E. Joseph, A. Schrott, J. B. Philipp, R. Cheek, T. D. Happ, Lett. 90 (2007) 063503.
S. H. Chen, S. Zaidr, P. Flaitz, J. Bruley, R. Dasaka, B. Rajendran, S. 75) Y. Yang, L. Ma, and J. Wu: MRS Bull. 29 (2004) 833.
Rossnage, M. Yang, Y. C. Chen, R. Bergmann, H. L. Lung, and C. Lam: 76) H. Kawai: Jpn. J. Appl. Phys. 8 (1969) 975.
Proc. Int. Symp. VLSI Technology, 2007, p. 100. 77) S. Fujisaki, H. Ishiwara, and Y. Fujisaki: Appl. Phys. Lett. 90 (2007)
42) T. W. Hickmott: J. Appl. Phys. 33 (1962) 2669. 162902.
43) J. Gibbsons and W. E. Beadle: Solid-State Electron. 7 (1964) 785. 78) S. Fujisaki, Y. Fujisaki, and H. Ishiwara: IEEE Trans. Ultrason.
44) S. R. Ovshinsky: Phys. Rev. Lett. 21 (1968) 1450. Ferroelectr. Freq. Control 54 (2007) 2592.
45) S. Q. Liu, N. J. Wu, and A. Ignatiev: Appl. Phys. Lett. 76 (2000) 2749. 79) J. Karasawa, T. Yasuda, T. Saeki, T. Aoki, S. Moriya, E. Hirai, T.
46) W. W. Zhuang, W. Pan, B. D. Ulrich, J. J. Lee, L. Stecker, A. Burmaster, Masuda, T. Kawase, T. Shimoda, D. P. Chu, C. J. Newsome, S. W. Tam,
D. R. Evans, S. T. Hsu, M. Tajiri, A. Shimaoka, K. Inoue, T. Naka, N. and M. Ishida: Proc. Int. Symp. Application of Ferroelectrics, 2007,
Awaya, K. Sakiyama, Y. Wang, S. Q. Liu, N. J. Wu, and A. Ignatiev: 30B-FR5-I1.
IEDM Tech. Dig., 2002, p. 193. 80) T. Sekitani, Y. Noguchi, S. Nakano, K. Zaitsu, Y. Kato, M. Takamiya, T.
47) R. Waser and M. Aono: Nat. Mater. 6 (2007) 833. Sakurai, and T. Someya: IEDM Tech. Dig., 2007, p. 221.
48) A. Sawa: Mater. Today 11 (2008) No. 6, 28. 81) Roadmap of 2007 edition can be downloaded from the following URL;
49) A. Sawa, R. Fujii, M. Kawasaki, and Y. Tokura: Appl. Phys. Lett. 85 http://www.itrs.net/Links/2007ITRS/Home2007.htm.
(2004) 4073. 82) International Technology Roadmap for Semiconductors, 2007 Edition,
50) Y. Xia, W. He, L. Chen, X. Meng, and Z. Liu: Appl. Phys. Lett. 90 (2007) Process Integration, Devices and Structures, p. 35 [Tables PIDS5a and
022907. PIDS5b].

100001-13 # 2010 The Japan Society of Applied Physics

Jpn. J. Appl. Phys. 49 (2010) 100001 Comprehensive Review

83) International Technology Roadmap for Semiconductors, 2007 Edition, 2009, p. 192.
Emerging Research Devices, p. 11 [Table ERD5b]. 90) R. Waser, R. Dittmann, G. Staikov, and K. Szot: Adv. Mater. 21 (2009)
84) International Technology Roadmap for Semiconductors, 2007 Edition, 2632.
Emerging Research Devices, p. 9 [Table ERD5a]. 91) D.-H. Kwon, K. M. Kim, J. H. Jang, J. M. Jeon, M. H. Lee, G. H. Kim,
85) International Technology Roadmap for Semiconductors, 2007 Edition, X.-S. Li, G.-S. Park, B. Lee, S. Han, M. Kim, and C. S. Hwang: Nat.
Emerging Research Devices, p. 8 [Table ERD4]. Nanotechnol. 5 (2010) 148.
86) R. Katsumata, M. Kito, Y. Fukuzumi, M. Kido, H. Tanaka, Y. Komori, M.
Ishiduki, J. Matsunami, T. Fujiwara, Y. Nagata, L. Zhang, Y. Iwata, R.
Kirisawa, H. Aochi, and A. Nitayama: Proc. Int. Symp. VLSI Technology,
2009, p. 136. Yoshihisa Fujisaki received his M.E. degree in
87) J. Kim, A. J. Hong, S. M. Kim, E. B. Song, J. H. Park, J. Han, S. Choi, D. physics and applied physics in 1981 from the
Jang, J.-T. Moon, and K. L. Wang: Proc. Int. Symp. VLSI Technology, Faculty of Science and Engineering, Waseda Uni-
2009, p. 186. versity. He joined Hitachi, Ltd., in 1981. He has
88) W. Kim, S. Choi, J. Sung, T. Lee, C. Park, H. Ko, J. Jung, I. Yoo, and Y. been involved in the development of lasers used for
Park: Proc. Int. Symp. VLSI Technology, 2009, p. 188. optical fiber communication, semi-insulating GaAs
89) J. Jang, H.-S. Kim, W. Cho, H. Cho, J. Kim, S. I. Shim, Y. Jang, J.-H. substrate crystals, ferroelectric nonvolatile memo-
Jeong, B.-K. Son, D. W. Kim, K. Kim, J.-J. Shim, J. S. Lim, K.-H. Kim, ries, and new types of nonvolatile memory in the
S. Y. Yi, J.-Y. Lim, D. Chung, H.-C. Moon, S. Hwang, J.-W. Lee, Y.-H. Central Research Laboratory, Hitachi, Ltd. He also
Son, U.-I. Chung, and W.-S. Lee: Proc. Int. Symp. VLSI Technology, has a doctorate in engineering.

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