International Journal of Advances in Applied Sciences (IJAAS)

Vol. 13, No. 1, March 2024, pp. 33~45

ISSN: 2252-8814, DOI: 10.11591/ijaas.v13.i1.pp33-45  33

A novel fuzzy-logic controller-MDsUPQC topology for power

quality improvement in multi-feeder distribution system

Sriramulu Naik Mudhavath, Lingineni Shanmukha Rao, Pidatala Prabhakara Sharma,

Sangu Bala Pushpa Latha
Department of Electrical and Electronics Engineering, Faculty of Electrical and Electronics Engineering,
Kallam Haranadhareddy Institute of Technology, Guntur, India

Article Info ABSTRACT

Article history: In the current situation, the significant usage of massive non-linear
functioned power electronic loads has been increased in domestic and
Received May 11, 2023 industrial applications. The main problem of power-quality (PQ)
Revised Aug 21, 2023 deterioration in both voltage quality and current quality from nominal values
Accepted Nov 9, 2023 and also damaging the single/multi feeder distribution systems. The major
contribution is to alleviate the PQ issues by employing novel multi-devices
unified power-quality conditioner (MDsUPQC) topology in a multi-feeder
Keywords: distribution system. This MDsUPQC comprises multiple voltage source
inverter (VSI) devices connected with a common direct current-link (DC-
Fuzzy-logic controller link) capacitor which is controlled by a proportional-integral (PI) controller.
MDsUPQC topology However, this controller has some technical issues that are not suited for the
Multi-feeder distribution regulation of common DC voltage at the desired level because of improper
system selection of gain values. The contribution of this work is proposing an
Power-quality improvement intelligent fuzzy-logic (FL) DC-link controller-driven MDsUPQC device
Total-harmonic distortion which evidences the intelligent knowledge base for better regulation of PQ
issues. The technique and performance of the suggested strategy for PQ
improvement, load sharing between feeders, and simulation results are
presented with comparative analysis utilizing the MATLAB/Simulink
software tool.
This is an open access article under the CC BY-SA license.

Corresponding Author:
Sriramulu Naik Mudhavath
Department of Electrical and Electronics Engineering, Faculty of Electrical and Electronics Engineering
Kallam Haranadhareddy Institute of Technology
Near Kallam Spinning Mills Limited, Guntur-Chennai Hwy, Dasaripalem, Andhra Pradesh 522019, India
Email: [email protected]

1. INTRODUCTION
Power-quality (PQ) issues in the power distribution network are identified based on multiple
circumstances that occur in sensitive load equipment and cause loss of capacity and production [1], [2]. PQ
identification approaches that are viable must be used to recognize the type of PQ issue impacting the
distribution network and monitoring system requirements with sophisticated monitoring techniques [3]. The
problem statement of this work is to mitigate multiple PQ issues encountered in distribution systems such as
harmonic current distortions, voltage harmonics, voltage sag-swells, unbalanced voltage, voltage flicker,
voltage interruptions, and frequency deviations.
In this view, various electrical engineers and researchers are compelled to create sophisticated PQ
improvement techniques known as customized power compensation (CPC) technology [4]. Hossain et al. [5]
showed a few feasible scenarios on series/shunt-connected compensation devices for enhanced PQ features
are presented. This CPC equipment uses custom-power devices (CPDs) to compensate for both current

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34  ISSN: 2252-8814

and/or voltage-allied PQ issues, resulting in a multi-feeder system that is sinusoidal, linear, fundamental, and
balanced [6]. The multi-feeder CPDs are classified based on specific issues such as interline-dynamic voltage
restorer (IDVR) [7], and interline power-flow controller (IPFC) [8]–[10]. These compensation tools
functioned independently to mitigate either voltage or current-allied PQ issues [11], [12]. The main
contribution of this work is, developing the novel multi-devices unified power-quality conditioner
(MDsUPQC) for mitigation of both voltage and current-related PQ issues in a multi-feeder distribution
system. Furthermore, it may transfer real-time reactive energy between feeders and ensure continuous power
supply to loads throughout power outages.
The proposed MDsUPQC device is made up of numerous voltage source inverters (VSIs) coupled in
a shunt-series fashion and driven by a typical direct current (DC) capacitor with the appropriate voltage level.
By utilizing viable reference signal extracting approaches, the proposed MDsUPQC minimizes both load and
source-side PQ concerns in a three-phase multi-feeder distribution system. The suggested MDsUPQC device
approach necessitates well-functioning control systems to extract reference voltage and current signals by
detecting supply voltage and non-linear load currents. In general, such as the synchronous reference frame
(SRF) control theory [13] was used to extract reference voltage from the series VSI-1,3 of the MDsUPQC.
Also, the instantaneous real-power (IRP) control theory [14] collects the reference current from the shunt-
VSI-2 of the MDsUPQC device. The direct current-link (DC-link) control of shunt-connected VSI-2 utilizes
the proportional-integral (PI) controller is considered as the second problem, which is not suited for
regulation of DC-link voltage at the desired level because of improper selection of gain values. The
contribution of this work is proposing an intelligent fuzzy-logic (FL) DC-link controller driven MDsUPQC
device which evidences the intelligent knowledge base for better regulation of PQ issues. The technique and
performance of the suggested strategy for PQ improvement, load sharing between feeders, and simulation
results are presented with comparative analysis utilising the MATLAB/Simulink software tool.

2. PROPOSED CONCEPT
The proposed MDsUPQC is made up of three VSI elements: one shunt-linked VSI-2 architecture to
alleviate all current issues in feeder-2 and two series-VSI 1,3 elements to alleviate all voltage difficulties on
the two feeders 1,2. One DC-link capacitor (CDC) powers these three VSI structures, which are coupled to a
multi-feeder distribution system via 1:1 transformers. The suggested MDsUPQC topology may improve PQ
and the sharing of load between neighboring feeders in a multi-feeder system. Without a requirement for
extra power, the MDsUPQC minimizes all types of interruptions in feeder-1. The second side of the line
transformers (LT-1 and LT-3) is linked in series to the main feeder-1 and neighboring feeder-2.
In this configuration, the MDsUPQC shunt VSI-2 in feeder-2 minimizes all current-related problems
including current harmonic imperfections, load balancing, reactive power management, and power-factor
adjustment caused by power-electronic non-linear load and maintains the voltage at the DC link as constant.
The series VSIs-1,3 of MDsUPQC in both feeder-1 and feeder-2 alleviate all voltage-related concerns such as
harmonics that are voltage distractions, imbalance voltage, sag in voltage, and voltage swelling, and 38% of
the power available from a feeder-2 has been injected. In this configuration, feeder-2 is connected to a very
sensitive non-linear (NL-2) load composed of three-phase uncontrolled-rectifier (UBR) loads that supply
converting energy to a resistive-inductive RL-load together. The suggested MDsUPQC topology is shown
schematically in Figure 1.

Figure 1. Schematic diagram of MDsUPQC topology for PQ enhancement

Int J Adv Appl Sci, Vol. 13, No. 1, March 2024: 33-45
Int J Adv Appl Sci ISSN: 2252-8814  35

3. CONTROL STRATEGIES
3.1. Proposed fuzzy-logic controlled synchronous reference frame control scheme for series VSIs-1,3
of MDsUPQC topology
In general, the MDsUPQC series VSI-1,3 functions as voltage-controlled devices of a multi-feeder
distribution network to regulate the common-coupling voltage with regard to the basic value of the load
voltage. Using Park's transformation technique, the measured actual supply voltages (V sabc1 and Vsabc2) in a
standard ABC-frame are transferred into direct (d-axis) and quadrature (q-axis) axes (Vsdq0.12) in a rotating
reference frame. The measured dq supply terminal voltage (V sdq0.12) is approximated with the dq reference
voltage (Vrabc12) after the dq transformation process to obtain the perfect compensated reference voltage with
error sequences. These error sequences are minimized using the trail-error approach and a PI controller with
proper proportional gain (Kp.r) and integral gain (Ki.r) choices. The transfer function of the voltage
controller is as (1).

𝑘𝑖.𝑠
𝑉𝑒𝑟𝑟 (𝑠) = (𝑘𝑝.𝑠 + ) × 𝐸𝑒𝑟𝑟 (𝑠) (1)
𝑠

The performance of a PI controller is always dependent on the selection of feasible gains with
necessary steps using the Ziegler-Nichols method. Because of this method, the traditional PI controller does
not auto-tune the gain values during parametric variations, sudden variations, and affecting the overall system
stability. It is realized the importance of an intelligent FL controller in the symbolic characterization of an
inference system with considerable expert knowledge. This FL controller exemplifies the intelligent
knowledge-based process, which includes FL-membership functions and an FL-rule base [11], [15]–[19].
The FL-rule base is the heart of FL control and the gathering of necessary information for depicting data
manipulation values, linguistic models, and FL-rule characterization, among other things.
∗
𝑉𝑒𝑟𝑟 (𝑠) = 𝑉𝑟𝑑𝑞0.12 − 𝑉𝑠𝑑𝑞0.12 (2)

∆𝑉𝑒𝑟𝑟 (𝑠) = 𝑉𝑒𝑟𝑟 (𝑠)- 𝑉𝑒𝑟𝑟 (𝑠 − 1) (3)

Where, 𝑉𝑒𝑟𝑟 (𝑠) and ∆𝑉𝑒𝑟𝑟 (𝑠) are the error and change in error. The related FL-membership functions and FL-
rule base are shown in Figure 2 and Table 1.

e( s), e( s) NB NM NS ZE PS PM PB
1

0.8

0.6

0.4

0.2

0
-1 - - -0.4 -0.2 0 0.2 0.4 0.6 0.8 1
0.8 0.6 e( s), e( s)

Figure 2. FL membership functions

Table 1. FL-rule-base
𝑒 (𝑠), ∆𝑒 (𝑠) NB NM NS ZE PS PM PB
NB NB NB NB NB NM NS ZE
NM NB NB NB NM NS ZE PS
NS NB NB NM NS ZE PS PM
ZE NB NM NS ZE PS PM PB
PS NM NS ZE PS PM PB PB
PM NS ZE PS PM PB PB PB
PB ZE NM NS ZE PS PM PB

Therefore, error sequences are reduced in the FL-SRF controller, which generates the appropriate
∗
reference voltage signals in the dq-frame (𝑉𝑟𝑒𝑓𝑑𝑞.12 ) as in (4). Then, using the inverse-Park's transformation
the procedure stated in (5), these voltages are retransformed into the ABC standard frame.

A novel fuzzy-logic controller-MDsUPQC topology for power quality …(Sriramulu Naik Mudhavath)
36  ISSN: 2252-8814
∗
𝑉𝑟𝑒𝑓𝑑𝑞.12 = (𝑉𝑟𝑑𝑞0.12 − 𝑉𝑠𝑑𝑞0.12 ) (4)

∗
𝑉𝑟𝑒𝑓𝑎.12 𝑐𝑜𝑠𝜃 𝑠𝑖𝑛𝜃 1
2𝜋 2𝜋 ∗
∗ 2 𝑐𝑜𝑠 [𝜃 −
[𝑉𝑟𝑒𝑓𝑏.12 ] = [ ] 𝑠𝑖𝑛 [𝜃 − ] 1] [𝑉𝑟𝑒𝑓𝑑.12 ] (5)
3 3 ∗
∗
3
2𝜋 2𝜋 𝑉𝑟𝑒𝑓𝑞.12
𝑉𝑟𝑒𝑓𝑐.12 𝑐𝑜𝑠 [𝜃 + ] 𝑠𝑖𝑛 [𝜃 + ] 1
3 3

∗
The generated reference voltage signals (𝑉𝑟𝑒𝑓𝑎𝑏𝑐.12 ) are transferred to the sinusoidal pulse width
modulation (PWM) approach for the production of possible switching pulses to the series connected VSI-1,3
of the MDsUPQC topology, which eliminates all voltage-related PQ problems. The schematic diagram of the
proposed FL-controlled FL-SRF control scheme for series VSI-1,3 of MDsUPQC topology is shown in
Figure 3.

Figure 3. Schematic diagram of proposed FL controlled FL-SRF control scheme for series VSI-1,3 of
MDsUPQC topology

3.2. Proposed fuzzy-logic controlled IRP controller for shunt VSI-2 of MDsUPQC topology
In general, the MDsUPQC shunt VSI-2 functions as a current-controlled apparatus at a multi-feeder
distribution system's point of common coupling (PCC) to handle current-related PQ concerns [20]–[22]. The
suggested FL-IRP control approach typically uses Clarke's conversion technique to convert conventional
ABC into αβ symmetric coordinates in a fixed reference frame. The instantaneous real and reactive power in
a symmetrical coordinate frame is calculated using (10) and (11) as shown in (6) and (7).

𝑝 = 𝑣𝑠𝛼2 𝑖𝑁𝐿𝛼2 + 𝑣𝑠𝛽2 𝑖𝑁𝐿𝛽2 (6)

𝑞 = −𝑣𝑠𝛽2 𝑖𝑁𝐿𝛼2 + 𝑣𝑠𝛼2 𝑖𝑁𝐿𝛽2 (7)

The non-linear distorted load currents in symmetrical αβ-frame are stated as (8).

𝑖𝑁𝐿𝛼2 1 𝑣𝑠𝛼2 𝑣𝑠𝛽2 𝑝

[𝑖 ]= [−𝑣 𝑣𝑠𝛼 2] [𝑞 ] (8)
𝑁𝐿𝛽2 ∆𝑘 𝑠𝛽2

Where,
2 2
∆𝑘 = 𝑣𝑠𝛼2 + 𝑣𝑠𝛽2 (9)

The resulting actual currents are then routed via a second-order high-pass filter, allowing more
advanced elements to get particular signals that act as references. The high-frequency sections are treated,
resulting in a component loss denoted as (P.Loss). In addition, the suggested FL control in the DC control
section, which is coupled to the primary controller, keeps the DC voltage of the shunt-connected VSI-2
stable. This FL controller exemplifies the intelligent knowledge-based process, which includes FL
membership functions and an FL-rule base. These FL-membership functions and FL-rules are key
components in FL controllers by incorporating significant human knowledge into an artificial knowledge
base. The DC control section corrects errors induced by the variation of the real DC voltage (𝑉𝑑𝑐.𝑐 ) and the

Int J Adv Appl Sci, Vol. 13, No. 1, March 2024: 33-45
Int J Adv Appl Sci ISSN: 2252-8814  37
∗
corresponding reference DC voltage (𝑉𝑑𝑐.𝑟 ). The (10) and (11) show the outcome of the controlling
component at the nth point.
∗
𝑉𝑑𝑐.𝑐𝑒𝑟 = 𝑉𝑑𝑐.𝑟 − 𝑉𝑑𝑐.𝑐 (10)

∆𝑖𝑎.𝑑𝑐 = 𝐾𝑝.𝑑 ∗ (𝑉𝑑𝑐.𝑐𝑒𝑟(𝑛) − 𝑉𝑑𝑐.𝑐𝑒𝑟(𝑛−1) ) + 𝐾𝑖.𝑑 ∗ (𝑉𝑑𝑐.𝑐𝑒𝑟(𝑛) ) (11)

The FL controller has a highly robust performance, is model-free, has a high strength index, and is
operated as a subjective decision based on a universe-approximation technique with an FL rule-based
algorithm. The related FL-membership functions and FL-rule base are depicted in Figure 2 and Table 1.
These immediate elements can be expressed as DC oscillating and AC averaging values, respectively.

𝑝 = 𝑝̅ + 𝑝̃
𝑞 = 𝑞̅ + 𝑞̃ (12)

Where, 𝑝̃𝑞̃ denotes oscillated AC values, 𝑝̅ 𝑞̅ denotes the averaged DC values. In addition, the extracted
∗
reference current signal (𝑖𝑐𝑟.𝛼𝛽 ) in αβ symmetrical frame is described as (13).

∗
𝑖𝑐𝑟.𝛼2 1 𝑣𝑠𝑡.𝛼2 −𝑣𝑠𝑡.𝛽 2 𝑝
[ ∗ ] = [𝑣 𝑣𝑠𝑡.𝛼2 ] [𝑞 ] (13)
𝑖𝑐𝑟.𝛽2 ∆𝑘 𝑠𝑡.𝛽2

Figure 4 depicts a schematic representation of the planned FL-IRP control method for MDsUPQC's
∗
shunt VSI-2. As a consequence, the acquired currents of reference (𝑖𝑐𝑟.𝛼𝛽2 ) in the αβ-frame are reverted into
the basic ABC frame using the inverse Clarke's translation process, yielding the ultimate reference current
∗
(𝑖𝑐𝑟.𝑎𝑏𝑐2 ) as given in (14):

1⁄ 1 0
∗ √2 ∗
𝑖𝑐𝑟.𝑎2 𝑖𝑐.02
√3⁄
= √ 1⁄ −1⁄
∗ 2 ∗
[𝑖𝑐𝑟.𝑏2 ]
3 √2 2 2 [𝑖𝑐.𝛼2
∗
] (14)
∗ 𝑖𝑐.𝛽2
𝑖𝑐𝑟.𝑐2
1 −1⁄ − √3⁄2
[ ⁄√2 2 ]

Finally, the reference currents extracted from the proposed FL-IRP control scheme are contrasted
with the actual supply currents for the production of switching pulses to the VSI-2 of the MDsUPQC device
via hysteresis current-control (HCC) as gate-pulse generation unit. The HCC is utilized for the production of
possible switching states to VSI-2 of the MDsUPQC through HCC band limits, which are regarded as limit
values of compensation currents that are rotated across the upper/lower limits of HCC bands. The schematic
diagram of the proposed FL-IRP control scheme for shunt VSI-2 of MDsUPQC topology is shown in
Figure 4.

Figure 4. Schematic diagram of proposed FL-IRP control scheme for shunt VSI-2 of MDsUPQC topology

A novel fuzzy-logic controller-MDsUPQC topology for power quality …(Sriramulu Naik Mudhavath)
38  ISSN: 2252-8814

4. RESULTS AND DISCUSSION

The performance of the suggested FL-controlled MDsUPQC device for PQ improvement, load
sharing across feeders, and simulation results are shown with an appealing comparison analysis. Table 2
shows the operational parameters and values of the proposed MDsUPQC topology as generalized estimated
values from many literature researches.

Table 2. Operating parameters and values of proposed MDsUPQC topology

Values
S. No Parameters
Feeder-1 Feeder-2
1 Three-phase source voltage (Vrms) Vsabc12-415 V, 50 Hz
2 Line impedance Rs12=0.15 Ω, Ls12-0.9 mH
3 Critical and sensitive load impedances RL=30 Ω, LL-20 mH VL=415 V, 50 Hz, PL=10 KW, QL=5 KVar
(NL-load) (critical load)
4 Linear (1:1) transformer 415 V, 50 Hz, linear model-5 KVA, 10% leakage reactance
5 Series-connected VSIs-1,3 filters Lse-3 mH, Cse-100 µF
6 Shunt-connected VSI-2 filters -- Rsh= 0.001 Ω, Lsh-10 mH
7 Common DC-link capacitor Vdc.c= 880 V, Cdc.c =1500 µF

4.1. Performance evaluation of series-connected VSI-1 of MDsUPQC in feeder-1 using proposed

fuzzy-logic controlled SRF control scheme
Simulation outcomes of series VSI-1 of FL-SRF-driven MDsUPQC in feeder-1 under voltage
harmonics are displayed in Figure 5. This feeder-1 is supplied with a voltage of 415 Vrms, 50 Hz supply
system to accomplish the critical load system. Regarding voltage harmonics, during 0.85 sec and 0.95 sec,
the main voltage is impacted by 5th and 7th-order harmonics, which present a major issue in feed-1. At this
period, the FL-SRF-driven MDsUPQC's series VSI-1 injects the necessary voltage using the in-phase
opposing concept to minimize voltage harmonics in the load voltage while offering a harmonic-free response.
Figure 6 depicts harmonic analysis. Total harmonic distortion (THD) analysis of the source voltage reaches
20.62% while harmonic presence is shown in Figure 6(a) and 0.43% while harmonic removal as shown in
Figure 6(b), which is substantially within IEEE-519/2014 requirements adjusted by series VSI-1 of FL-SRF
controlled MDsUPQC.
The effectiveness of the FL-SRF controlled MDsUPQC series VSI-1 in feeder-1 is validated under
voltage-sag, as illustrated in Figure 7. Because voltage sag does not exist in feeder-1, the source voltage
remains constant at 340 V while in the pre-sag state. When voltage sag is introduced in feeder-1 within 0.1
and 0.2 sec, the source voltage decreases slightly to 170 V because of sag in the source. The load voltage
remains constant at 340 V, however, since the series VSI-1 of feeder-1 introduces the needed voltage of
170 V to maintain the load voltage as stable. As shown in Figure 8, the functioning of the series VSI-1 of the
FL-SRF-driven MDsUPQC in feeder-1 is validated under voltage swell.

Figure 5. Simulated results of series-connected VSI-1 of FL-SRF controlled MDsUPQC in feeder-1 under
voltage harmonics

Int J Adv Appl Sci, Vol. 13, No. 1, March 2024: 33-45
Int J Adv Appl Sci ISSN: 2252-8814  39

(a) (b)

Figure 6. THD spectrum in feeder-1 during voltage harmonics of (a) source and (b) load voltage values

Figure 7. Voltage sag condition

Figure 8. Voltage swell condition

Because voltage swelling does not occur in feeder-1, the source's voltage remains stable at 340 V
while in the pre-swell state. Voltage swelling happens during 0.65 sec and 0.75 sec in feeder-1 due to swell in
the source voltage rising to 510 V. The load voltage remains stable at 340 V since the series VSI-1 of feeder-
1 injects/absorbs the extra voltage of 170 V to maintain the voltage of the load as constant. Under voltage
interruptions, the capability of the series-linked VSI-1 of the FL-SRF-driven MDsUPQC in Feeder-1 is
validated, as illustrated in Figure 9. Because these don't exist voltage disruptions in feeder-1, the source's
voltage is maintained stable at 340 V until 0.35 sec. While voltage disruptions occur in feeder-1 within 0.35
and 0.55 sec, the source voltage decreases to 0 V, affecting the load voltage while the compensator is not
enabled. The load voltage, however, remains stable at 340 V since the series VSI-1 of feeder-1 injects the
needed voltage of 430 V to maintain the voltage of the load as stable.

A novel fuzzy-logic controller-MDsUPQC topology for power quality …(Sriramulu Naik Mudhavath)
40  ISSN: 2252-8814

Figure 10 shows the active reactive power of the source, load, and series connected VSI-1 of
MDsUPQC topology in Feeder-1. The active power of the primary source remains consistent at 10 KW while
in the pre-sag state prior to 0.1 sec; while the voltage sag is given during 0.1 sec and 0.2 sec in feeder-1, the
source's active power is somewhat lowered to 5 KW owing to the rapid voltage-sag situation. In such an
instance, the series VSI-1 of the MDsUPQC introduces the required active power to the load, which is kept
steady at 5 KW in order to maintain the load's active power as constant at 10 KW, as shown in Figure 10(a).
In addition, while in the pre-sag state, the reactive power of the source remains consistent at 5 KVar.
The reactive power of the source is lowered to 2.5 KVar under the sagging state; the series linked VSI-1 of
the MDsUPQC introduces the required reactive power of 2.5 KVar to the load, which keeps the load's
reactive power as stable at 5 KVar, as illustrated in Figure 10(b). In a similar way for each of the prior
situations, the active and reactive powers are maintained as constant by employing the series VSI-1 of
MDsUPQC to improve the PQ characteristics in the feeder-1 of the multi-feeder distribution network.

Figure 9. Simulated results of series-connected VSI-1 of FL-SRF controlled MDsUPQC in feeder-1 under
voltage interruptions condition

(a)

(b)

Figure 10. Series connected source, load, VSI-1 of MDsUPQC topology in feeder-1
of (a) active power and (b) reactive power

Int J Adv Appl Sci, Vol. 13, No. 1, March 2024: 33-45
Int J Adv Appl Sci ISSN: 2252-8814  41

4.2. Performance evaluation of series-connected VSI-3 and shunt VSI-2 of MDsUPQC in feeder-2
using proposed fuzzy-logic controlled SRF/IRP control scheme
Figure 11 depicts the simulated results of the shunt VSI-2 of the MDsUPQC in feeder-2 under
current harmonic distortions. With a 415 V, 50 Hz supply system, feeder-2 has been energizing the three-
phase non-linear UBR load. The source current is distorted and harmonized as a result of these non-linear
power loads, producing serious issues in feeder-2 and increasing heat loss; the flow of extremely high rates
destroys the whole load system. To eliminate harmonics from the NL-UBR load, a shunt-connected VSI-2 of
MDsUPQC has been employed in the FL-IRP control scheme. As an in-phase opposition principle, the
proposed MDsUPQC of shunt-connected VSI mitigates all harmonic distortions and furnishes the pure-
sinusoidal voltage, and current with balanced nature.
The THD spectrum of source and load current values in feeder-2 in the presence of harmonic current
distortions is depicted in Figure 12. THD of non-linear power load current due to non-linear load switching is
nearly 30.05% (Figure 12(a)), and harmonic distortions in the supply current have been eliminated with an
average of 2.71% (Figure 12(b)), both of which falls well in IEEE-519/2014 standards provided by FL-IRP
controlled by shunt VSI-2 of MDsUPQC architecture. The DC-link capacitor voltage remains constant at 880
V with the help of the recommended FL controller, which maintains the PCC voltage stable as depicted in
Figure 13. As shown in Figure 14, the supply current is in phase with the voltage of the supply and defines
the identical power factor at the point of connection of feeder-2 in a multi-feeder distribution network.

Figure 11. Simulated results of shunt-connected VSI-2 of FL-IRP controlled MDsUPQC in feeder-2 under
non-linear load

(a)

(b)

Figure 12. THD spectrum of feeder-2 during the presence of harmonic current
distortions on (a) non-linear load current and (b) supply current
A novel fuzzy-logic controller-MDsUPQC topology for power quality …(Sriramulu Naik Mudhavath)
42  ISSN: 2252-8814

Figure 13. DC-link voltage

Figure 14. Supply voltage and supply current

Figure 15 depicts the simulated results of a series VSI-3 of FL-SRF-operated MDsUPQC in feeder-2
during voltage sag conditions. While voltage sag does not exist in feeder-2, the source voltage is held stable
at 340 V throughout the pre-sag condition. Due to the existence of voltage sag in the main input supply, the
voltage of the supply is lowered to 50% of the base value in feeder-2 during 0.25 sec and 0.35 sec. The load
voltage, even so, remains stable at 340 V due to the series VSI-3 of feeder-2 introducing the required voltage
of 170 V to maintain the essential load voltage as constant. The operation of the series VSI-3 of the
MDsUPQC in feeder-2 is demonstrated in Figure 16 under voltage-swell circumstances. Because voltage
swell does not occur in feeder-2, the source voltage remains constant at 340 V throughout the pre-swell
condition. Table 3 and Figure 17 depict the time instant between 0.55 sec supply voltage and critical load
voltage in feeder-2 of a multi-feeder distribution system. Table 4 and Figure 18 show the distribution system
at the time instant between 0.55 sec. Because voltage swell does not occur in feeder-2, the source voltage
remains constant at 340 V throughout the pre-swell condition. Table 4 and Figure 18 provide THD
comparisons and a graphical view of non-linear load current and supply current in feeder-1 of a multi-feeder
distribution system.

Figure 15. Voltage sag condition

Int J Adv Appl Sci, Vol. 13, No. 1, March 2024: 33-45
Int J Adv Appl Sci ISSN: 2252-8814  43

Figure 16. Voltage swell condition

Table 3. THD comparisons of supply voltage and critical load voltage in feeder-2 of multi-feeder distribution
system
THD Supply voltage (%) Critical load voltage (%)
Without MDsUPQC topology 20.68 20.68
With PI-SRF-controlled MDsUPQC topology [13] 20.62 0.52
With the proposed FL-SRF controlled MDsUPQC topology 20.62 0.43

Figure 17. Graphical view of THD comparisons in feeder-2 of the multi-feeder distribution system

Table 4. THD comparisons of non-linear load current, supply current in feeder-1 of multi-feeder distribution
system
THD Non-linear load current (%) Supply current (%)
Without MDsUPQC topology 30.07 30.07
With PI-IRP controlled MDsUPQC topology [14] 30.05 5.20
With the proposed FL-IRP controlled MDsUPQC topology 30.05 2.71

Figure 18. Graphical view of THD comparisons in feeder-1 of the multi-feeder distribution system

A novel fuzzy-logic controller-MDsUPQC topology for power quality …(Sriramulu Naik Mudhavath)
44  ISSN: 2252-8814

5. CONCLUSION
The suggested FL-controlled MDsUPQC topology for PQ improvement in a multi-feeder
distribution system was critically evaluated. By combining considerable human knowledge into an artificial
knowledge base, this FL controller exhibits an intelligent knowledge-based process. Over traditional control
systems, the suggested FL controller SRF/IRP-driven MDsUPQC architecture mitigates all voltage-current
allied PQ concerns. The performance of the suggested FL-controlled MDsUPQC device for PQ
improvement, load sharing across feeders, and simulation results are shown with an appealing comparison
analysis. THD analysis of source voltage reaches 20.62% during harmonic presence and 0.43% during
harmonic removal, which is well within IEEE-519/2014 requirements adjusted by series connected VSI-1 of
FL-SRF controlledMDsUPQC. THD spectrum of source and load current values in feeder-2 in the presence
of harmonic current distortions. The THD of non-linear current at the load is almost 30.05%, and harmonic
distortions in supply current are eliminated with a value of 2.71%, both of which are well within IEEE-
519/2014 norms compensated by FL-IRP controlled by shunt-connected VSI-2 of MDsUPQC topology.

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BIOGRAPHIES OF AUTHORS

Sriramulu Naik Mudhavath received a Ph.D. from Acharya Nagarjuna

University, Guntur, Andhra Pradesh, India in 2022 and an M.Tech. in Power Electronics and
Electric Drives from Jawaharlal Nehru Technological University Kakinada, Kakinada, A.P,
India in 2011. At present, he is working as an associate professor at Kallam Haranadhareddy
Institute of Engineering and Technology, Guntur, A.P., India. His research area of interest
includes power electronics, drives, FACTS devices, multi-level inverters, and renewable
energy sources. He published more than 10 papers in international journals and conferences.
He can be contacted at email: [email protected].

Lingineni Shanmukha Rao received a Ph.D. from Jawaharlal Nehru

Technological University Hyderabad (JNTUH), Hyderabad, India in 2016 and an M.Tech. in
Electrical Power Engineering from Jawaharlal Nehru Technological University (J.N.T.U),
Hyderabad, A.P, India in 2006. At present, he is working as a professor and head of the
Department of Electrical and Electronics Engineering at Kallam Haranadhareddy Institute of
Engineering and Technology, Guntur, A.P., India. He authored four books and published more
than 25 research papers in international journals and conferences. His research interests
include power system modeling and control, renewable energy sources, and soft computing
Techniques. He can be contacted at email: [email protected].

Pidatala Prabhakara Sharma received obtained his B.Tech. in EEE from

KLCE, AP, India. He completed his master of technology in High Voltage Engineering from
University College of Engineering, JNTUK- Kakinada. AP, India, and pursuing a Ph.D. at
Andhra University. He is currently working as an associate professor in the Department of
Electrical and Electronics Engineering at Kallam Haranadhareddy Institute of Technology,
Guntur, AP, India, since 2013. He published more than 20 papers in international journals and
conferences. He filed three patents. His area of interest includes electrical machines, HVDC,
AC-DC power flows, and soft computing techniques. He can be contacted at email:
[email protected].

Sangu Bala Pushpa Latha is an Undergraduate student studying IV B.Tech.

Electrical and Electronics Engineering from Kallam Haranadhareddy Institute of Engineering
and Technology, Guntur, A.P., India. She is one of the toppers at the colleges who got
meritorious scholarships and won many prizes in the technical events held at intra and inter-
college levels. Her research interests include power quality. She can be contacted at email:
[email protected].

A novel fuzzy-logic controller-MDsUPQC topology for power quality …(Sriramulu Naik Mudhavath)