07 Efr32mg21-Datasheet

EFR32MG21 Multiprotocol Wireless SoC
Family Data Sheet
The EFR32MG21 SoC is part of the Wireless Gecko portfolio.

KEY FEATURES
EFR32MG21 SoCs are ideal for enabling energy-friendly multipro-
tocol, multiband networking for IoT devices. • 32-bit ARM® Cortex®-M33 core with 80
MHz maximum operating frequency
The single-die solution combines an 80 MHz ARM Cortex-M33, a high performance 2.4 • Up to 1024 kB of flash and 96 kB of RAM
GHz radio, and an integrated Hardware Secure Engine to provide a highly secure, ener-
• 12-channel Peripheral Reflex System
gy efficient wireless SoC for IoT connected applications.
enabling autonomous interaction of MCU
peripherals
EFR32MG21 applications include:
• Integrated PA with up to 20 dBm (2.4
• IoT Multi-Protocol Devices GHz) TX power
• Lighting • Robust peripheral set and up to 20 GPIO
in a 4x4 QFN package
• Connected Home
• Gateways and Digital Assistants
• Building Automation and Security
Core / Memory Clock Management Energy Security

Management Crypto Acceleration
Secure Boot with
HF Crystal HF Fast Startup
Root of Trust and True Random
ARM CortexTM M33 processor Secure Loader Oscillator RC Oscillator RC Oscillator Voltage
Flash Program Regulator Number Generator
with DSP extensions,
Memory DPA
FPU and TrustZone EM23 HF RC
EUI Countermeasures
Oscillator Brown-Out
Detector Secure Debug
Authentication
LDMA LF Crystal Ultra LF RC LF
ETM Secure Debug RAM Memory Oscillator RC Oscillator Power-On Reset
Controller Oscillator Secure Engine
32-bit bus
Peripheral Reflex System
Radio Transceiver Serial I/O Ports Timers and Triggers Analog I/F
Interfaces
RF Frontend
DEMOD USART
External
Timer/Counter Protocol Timer IADC
Interrupts
BUFC
FRC
I
LNA
Q PGA IFADC General Analog
I2C Low Energy Timer Watchdog Timer
Purpose I/O Comparator
PA
AGC Pin Reset
Real Time
Capture Counter
CRC
RAC
PA Frequency
Synth
MOD Pin Wakeup
Back-Up Real
Time Counter
Lowest power mode with peripheral operational:
EM0—Active EM1—Sleep EM2—Deep Sleep EM3—Stop EM4—Shutoff
silabs.com | Building a more connected world. Copyright © 2024 by Silicon Laboratories Rev. 1.2
EFR32MG21 Multiprotocol Wireless SoC Family Data Sheet
Feature List
1. Feature List
The EFR32MG21 highlighted features are listed below.

• Low Power Wireless System-on-Chip • Wide selection of MCU peripherals
• High Performance 32-bit 80 MHz ARM Cortex®-M33 with • 12-bit 1 Msps SAR Analog to Digital Converter (ADC)
DSP instruction and floating-point unit for efficient signal • 2 × Analog Comparator (ACMP)
processing • Up to 20 General Purpose I/O pins with output state reten-
• Up to 1024 kB flash program memory tion and asynchronous interrupts
• Up to 96 kB RAM data memory • 8 Channel DMA Controller
• 2.4 GHz radio operation • 12 Channel Peripheral Reflex System (PRS)
• TX power up to 20 dBm • 3 × 16-bit Timer/Counter
• Low Energy Consumption • 3 Compare/Capture/PWM channels
• 8.8 mA RX current at 2.4 GHz (1 Mbps GFSK) • 1 × 32-bit Timer/Counter
• 9.4 mA RX current at 2.4 GHz (250 kbps O-QPSK DSSS) • 3 Compare/Capture/PWM channels
• 9.9 mA TX current @ 0 dBm output power at 2.4 GHz • 32-bit Real Time Counter
• 34.9 mA TX current @ 10 dBm output power at 2.4 GHz • 24-bit Low Energy Timer for waveform generation
• 50.9 μA/MHz in Active Mode (EM0) • 2 × Watchdog Timer
• 5.0 μA EM2 DeepSleep current • 3 × Universal Synchronous/Asynchronous Receiver/Trans-
mitter (UART/SPI/SmartCard(ISO 7816)/IrDA/I2S)
(96 kB RAM retention and RTC running from LFXO)
• 2 × I2C interface with SMBus support
• 4.5 μA EM2 DeepSleep current
• Wide Operating Range
(16 kB RAM retention and RTC running from LFRCO) • 1.71 V to 3.8 V single power supply
• High Receiver Performance • -40°C to 125°C ambient
• -104.3 dBm sensitivity @ 250 kbps O-QPSK DSSS • Secure Vault
• -97.1 dBm sensitivity @ 1 Mbit/s GFSK • Hardware Cryptographic Acceleration for AES128/192/256,
• -94 dBm sensitivity @ 2 Mbit/s GFSK ChaCha20-Poly1305, SHA-1, SHA-2/256/384/512, ECDSA
• -105 dBm sensitivity @ 125 kbps GFSK +ECDH(P-192, P-256, P-384, P-521), Ed25519 and
• Supported Modulation Formats Curve25519, J-PAKE, PBKDF2
• GFSK • True Random Number Generator (TRNG)
• OQPSK • ARM® TrustZone®
• Protocol Support • Secure Boot (Root of Trust Secure Loader)
• Bluetooth Low Energy (Bluetooth 5) • Secure Debug Unlock
• Zigbee • DPA Countermeasures
• Thread • Secure Key Management with PUF
• Anti-Tamper
• Secure Attestation
• QFN32 4x4 mm Package
• 0.4 mm pitch
silabs.com | Building a more connected world. Rev. 1.2 | 2

Ordering Information
2. Ordering Information
Table 2.1. Ordering Information
Max TX Secure
Ordering Code Flash (kB) RAM (kB) GPIO Package
Power Vault
EFR32MG21B020F768IM32-B 20 dBm 768 64 High 20 QFN32
EFR32MG21A020F768IM32-B 20 dBm 768 64 Mid 20 QFN32
EFR32MG21B020F768IM32-D 20 dBm 768 64 High 20 QFN32
EFR32MG21A020F768IM32-D 20 dBm 768 64 Mid 20 QFN32
Bluetooth 5.x: As the Bluetooth standard evolves, Silicon Labs is regularly adding new features. For more information on supported
Bluetooth capabilities, visit https://www.silabs.com/bluetooth-hardware.

Ordering Information
EFR32MG21B 020 F 1024 I M 32 - D R

Product Family
Security
Features
Memory
Size
Temperature Grade
Package
Pins
Revision
Tape & Reel
Field Options
Product Family • EFR32MG21: Wireless Gecko MG21 Family
Security • A: Secure Vault Mid

• B: Secure Vault High
Features [f1][f2][f3] • f1
• 0: Unused
• f2
• 1: 10 dBm PA Transmit Power
• 2: 20 dBm PA Transmit Power
• f3
• 0: Unused
Memory • F: Flash
Size • Memory Size in kBytes
Temperature Grade • I: -40 to +125 °C
Package • M: QFN
Pins • Number of Package Pins
Revision • B: Revision B
• D: Revision D
Tape & Reel • R: Tape & Reel (optional)
Figure 2.1. Ordering Code Key

Table of Contents
1. Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2 Radio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2.1 Antenna Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2.2 Fractional-N Frequency Synthesizer . . . . . . . . . . . . . . . . . . . . . 9
3.2.3 Receiver Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2.4 Transmitter Architecture . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2.5 Packet and State Trace . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2.6 Data Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2.7 Radio Controller (RAC). . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3 General Purpose Input/Output (GPIO) . . . . . . . . . . . . . . . . . . . . . .10
3.4 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.4.1 Clock Management Unit (CMU) . . . . . . . . . . . . . . . . . . . . . . .10
3.4.2 Internal and External Oscillators. . . . . . . . . . . . . . . . . . . . . . .10
3.5 Counters/Timers and PWM . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.5.1 Timer/Counter (TIMER) . . . . . . . . . . . . . . . . . . . . . . . . .10
3.5.2 Low Energy Timer (LETIMER) . . . . . . . . . . . . . . . . . . . . . . .10
3.5.3 Real Time Clock with Capture (RTCC) . . . . . . . . . . . . . . . . . . . .11
3.5.4 Back-Up Real Time Counter (BURTC) . . . . . . . . . . . . . . . . . . . .11
3.5.5 Watchdog Timer (WDOG) . . . . . . . . . . . . . . . . . . . . . . . . .11
3.6 Communications and Other Digital Peripherals . . . . . . . . . . . . . . . . . . .11
3.6.1 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) . . . . . . . . . .11
3.6.2 Inter-Integrated Circuit Interface (I2C) . . . . . . . . . . . . . . . . . . . . .11
3.6.3 Peripheral Reflex System (PRS) . . . . . . . . . . . . . . . . . . . . . .11
3.7 Secure Vault Features . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.7.1 Secure Boot with Root of Trust and Secure Loader (RTSL) . . . . . . . . . . . . .12
3.7.2 Cryptographic Accelerator. . . . . . . . . . . . . . . . . . . . . . . . .13
3.7.3 True Random Number Generator . . . . . . . . . . . . . . . . . . . . . .13
3.7.4 Secure Debug with Lock/Unlock. . . . . . . . . . . . . . . . . . . . . . .13
3.7.5 DPA Countermeasures. . . . . . . . . . . . . . . . . . . . . . . . . .13
3.7.6 Secure Key Management with PUF . . . . . . . . . . . . . . . . . . . . .13
3.7.7 Anti-Tamper . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.7.8 Secure Attestation . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.8 Analog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.8.1 Analog Comparator (ACMP) . . . . . . . . . . . . . . . . . . . . . . . .14
3.8.2 Analog to Digital Converter (IADC) . . . . . . . . . . . . . . . . . . . . . .14
3.9 Reset Management Unit (RMU) . . . . . . . . . . . . . . . . . . . . . . . .14
3.10 Core and Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.10.1 Processor Core . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.10.2 Memory System Controller (MSC) . . . . . . . . . . . . . . . . . . . . .15

3.10.3 Linked Direct Memory Access Controller (LDMA) . . . . . . . . . . . . . . . .15
3.11 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3.12 Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . .16
4. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1 Electrical Characteristics for Revision B . . . . . . . . . . . . . . . . . . . . .17
4.1.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . .18
4.1.2 General Operating Conditions . . . . . . . . . . . . . . . . . . . . . . .19
4.1.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .20
4.1.4 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.1.5 2.4 GHz RF Transceiver Characteristics . . . . . . . . . . . . . . . . . . . .26
4.1.6 Flash Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .41
4.1.7 Energy Mode Wake-up and Entry Times . . . . . . . . . . . . . . . . . . . .42
4.1.8 Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
4.1.9 GPIO Pins (3V GPIO pins) . . . . . . . . . . . . . . . . . . . . . . . .48
4.1.10 Analog to Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . .50
4.1.11 Analog Comparator (ACMP) . . . . . . . . . . . . . . . . . . . . . . .52
4.1.12 Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . .53
4.1.13 Brown Out Detectors . . . . . . . . . . . . . . . . . . . . . . . . . .54
4.1.14 USART SPI Main Timing. . . . . . . . . . . . . . . . . . . . . . . . .56
4.1.15 USART SPI Secondary Timing. . . . . . . . . . . . . . . . . . . . . . .58
4.1.16 I2C Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . .59
4.1.17 Boot Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
4.1.18 Crypto Operation Timing for SE Manager API. . . . . . . . . . . . . . . . . .62
4.1.19 Crypto Operation Average Current for SE Manager API . . . . . . . . . . . . . .64
4.2 Typical Performance Curves for Revision B . . . . . . . . . . . . . . . . . . . .66
4.2.1 Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
4.2.2 2.4 GHz Radio . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
4.3 Electrical Characteristics for Revision D . . . . . . . . . . . . . . . . . . . . .71
4.3.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . .72
4.3.2 General Operating Conditions . . . . . . . . . . . . . . . . . . . . . . .73
4.3.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .74
4.3.4 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . .75
4.3.5 2.4 GHz RF Transceiver Characteristics . . . . . . . . . . . . . . . . . . . .80
4.3.6 Flash Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .95
4.3.7 Energy Mode Wake-up and Entry Times . . . . . . . . . . . . . . . . . . . .96
4.3.8 Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
4.3.9 GPIO Pins (3V GPIO pins) . . . . . . . . . . . . . . . . . . . . . . 102
.
4.3.10 Analog to Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . 104
.
4.3.11 Analog Comparator (ACMP) . . . . . . . . . . . . . . . . . . . . . 106
.
4.3.12 Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . 107
4.3.13 Brown Out Detectors . . . . . . . . . . . . . . . . . . . . . . . . . 108
4.3.14 USART SPI Main Timing . . . . . . . . . . . . . . . . . . . . . . . . 110
4.3.15 USART SPI Secondary Timing . . . . . . . . . . . . . . . . . . . . . . 112
4.3.16 I2C Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . 113
4.3.17 Boot Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
4.3.18 Crypto Operation Timing for SE Manager API . . . . . . . . . . . . . . . . . 116

4.3.19 Crypto Operation Average Current for SE Manager API . . . . . . . . . . . . .118
4.4 Typical Performance Curves for Revision D . . . . . . . . . . . . . . . . . . .120
4.4.1 Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . 1. 21
4.4.2 2.4 GHz Radio . . . . . . . . . . . . . . . . . . . . . . . . . . 123 .
5. Typical Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . .126

5.1 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
5.2 RF Matching Networks . . . . . . . . . . . . . . . . . . . . . . . . . .126
5.2.1 2.4 GHz 0 dBm Matching Network . . . . . . . . . . . . . . . . . . . . . 127
5.2.2 2.4 GHz 10 dBm Matching Network . . . . . . . . . . . . . . . . . . . 1. 28
5.2.3 2.4 GHz 20 dBm Matching Network . . . . . . . . . . . . . . . . . . . 1. 28
5.3 Other Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
6. Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

6.1 QFN32 Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . 130
.
6.2 Alternate Function Table. . . . . . . . . . . . . . . . . . . . . . . . . . 131
6.3 Analog Peripheral Connectivity . . . . . . . . . . . . . . . . . . . . . . 1. 32
6.4 Digital Peripheral Connectivity . . . . . . . . . . . . . . . . . . . . . . . . 133
7. QFN32 Package Specifications. . . . . . . . . . . . . . . . . . . . . . . . 136

7.1 QFN32 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 136
7.2 QFN32 PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . .138
7.3 QFN32 Package Marking . . . . . . . . . . . . . . . . . . . . . . . . .140
8. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141

System Overview
3. System Overview
3.1 Introduction
The EFR32 product family combines an energy-friendly MCU with a high performance radio transceiver. The devices are well suited for
secure connected IoT multiprotocol devices requiring high performance and low energy consumption. This section gives a short intro-
duction to the full radio and MCU system. The detailed functional description can be found in the EFR32xG21 Reference Manual.
A block diagram of the EFR32MG21 family is shown in the figure below. The diagram shows a superset of features available on the
family, which vary by OPN. For more information about specific device features, consult the Ordering Information table.
Radio Transciever Port I/O Configuration IOVDD

RF Frontend DEMOD
BUFC
I
FRC
LNA
Digital Peripherals
Q
PGA IFADC
RF2G4_IO1 PA LETIMER
Port A
RF2G4_IO2 PAn
Frequency AGC Drivers
TIMER
CRC
RAC
PA
Synthesizer
MOD RTC Port B
PBn
Drivers
USART
Reset Port
RESETn ARM Cortex-M33 Core I2C Mapper Port C
Management PCn
Drivers
Unit
Serial Wire Up to 1024 kB Flash
Debug Signals and ETM Brown Out / Program Memory Crypto
(shared w/GPIO) Debug / Power-On Accelerator Port D
PDn
Programming Reset Up to 96 KB RAM Drivers
A A TRNG
TrustZone H P
B B
Energy Management Floating Point Unit CRC
PAVDD
RFVDD DMA Controller
IOVDD Analog Peripherals

AVDD Watchdog
DVDD Timer Internal
Reference
Clock Management
Voltage
Port Mapper
Input Mux
Regulator ULFRCO VDD

12-bit ADC
FSRCO
DECOUPLE HFRCOEM2
LFRCO
LFXTAL_I
LFXO +
LFXTAL_O -
HFRCO
HFXTAL_I Analog Comparator
HFXO
HFXTAL_O
Figure 3.1. Detailed EFR32MG21 Block Diagram
3.2 Radio
The EFR32MG21 features a highly configurable radio transceiver supporting Zigbee, Thread, and Bluetooth Low Energy wireless proto-
cols.
3.2.1 Antenna Interface
The 2.4 GHz antenna interface consists of two single-ended pins (RF2G4_IO1 and RF2G4_IO2) that interface directly to two LNAs and
two 10 dBm PAs. For devices that support 20 dBm, these pins also interface to the 20 dBm on-chip balun. Integrated switches select
either RF2G4_IO1 or RF2G4_IO2 to be the active path.
The external components and power supply connections for the antenna interface typical applications are shown in the RF Matching
Networks section.

System Overview
3.2.2 Fractional-N Frequency Synthesizer
The EFR32MG21 contains a high performance, low phase noise, fully integrated fractional-N frequency synthesizer. The synthesizer is
used in receive mode to generate the LO frequency for the down-conversion mixer. It is also used in transmit mode to directly generate
the modulated RF carrier.
The fractional-N architecture provides excellent phase noise performance, frequency resolution better than 100 Hz, and low energy
consumption. The synthesizer’s fast frequency settling allows for very short receiver and transmitter wake up times to reduce system
energy consumption.
3.2.3 Receiver Architecture
The EFR32MG21 uses a low-IF receiver architecture, consisting of a Low-Noise Amplifier (LNA) followed by an I/Q down-conversion
mixer. The I/Q signals are further filtered and amplified before being sampled by the IF analog-to-digital converter (IFADC).
The IF frequency is configurable from 150 kHz to 1371 kHz. The IF can further be configured for high-side or low-side injection, provid-
ing flexibility with respect to known interferers at the image frequency.
The Automatic Gain Control (AGC) module adjusts the receiver gain to optimize performance and avoid saturation for excellent selec-
tivity and blocking performance. The 2.4 GHz radio is calibrated at production to improve image rejection performance.
Demodulation is performed in the digital domain. The demodulator performs configurable decimation and channel filtering to allow re-
ceive bandwidths ranging from 0.1 to 2530 kHz. High carrier frequency and baud rate offsets are tolerated by active estimation and
compensation. Advanced features supporting high quality communication under adverse conditions include forward error correction by
block and convolutional coding as well as Direct Sequence Spread Spectrum (DSSS).
A Received Signal Strength Indicator (RSSI) is available for signal quality metrics, for level-based proximity detection, and for RF chan-
nel access by Collision Avoidance (CA) or Listen Before Talk (LBT) algorithms. An RSSI capture value is associated with each received
frame and the dynamic RSSI measurement can be monitored throughout reception.
3.2.4 Transmitter Architecture
The EFR32MG21 uses a direct-conversion transmitter architecture. For constant envelope modulation formats, the modulator controls
phase and frequency modulation in the frequency synthesizer. Transmit symbols or chips are optionally shaped by a digital shaping
filter. The shaping filter is fully configurable, including the BT product, and can be used to implement Gaussian or Raised Cosine shap-
ing.
Carrier Sense Multiple Access - Collision Avoidance (CSMA-CA) or Listen Before Talk (LBT) algorithms can be automatically timed by
the EFR32MG21. These algorithms are typically defined by regulatory standards to improve inter-operability in a given bandwidth be-
tween devices that otherwise lack synchronized RF channel access.
3.2.5 Packet and State Trace
The EFR32MG21 Frame Controller has a packet and state trace unit that provides valuable information during the development phase.
It features:
• Non-intrusive trace of transmit data, receive data and state information
• Data observability on a single-pin UART data output, or on a two-pin SPI data output
• Configurable data output bitrate / baudrate
• Multiplexed transmitted data, received data and state / meta information in a single serial data stream
3.2.6 Data Buffering
The EFR32MG21 features an advanced Radio Buffer Controller (BUFC) capable of handling up to 4 buffers of adjustable size from 64
bytes to 4096 bytes. Each buffer can be used for RX, TX or both. The buffer data is located in RAM, enabling zero-copy operations.
3.2.7 Radio Controller (RAC)
The Radio Controller controls the top level state of the radio subsystem in the EFR32MG21. It performs the following tasks:
• Precisely-timed control of enabling and disabling of the receiver and transmitter circuitry
• Run-time calibration of receiver, transmitter and frequency synthesizer
• Detailed frame transmission timing, including optional LBT or CSMA-CA

System Overview
3.3 General Purpose Input/Output (GPIO)
EFR32MG21 has up to 20 General Purpose Input/Output pins. Each GPIO pin can be individually configured as either an output or
input. More advanced configurations including open-drain, open-source, and glitch-filtering can be configured for each individual GPIO
pin. The GPIO pins can be overridden by peripheral connections, like SPI communication. Each peripheral connection can be routed to
several GPIO pins on the device. The input value of a GPIO pin can be routed through the Peripheral Reflex System to other peripher-
als. The GPIO subsystem supports asynchronous external pin interrupts.
All of the pins on ports A and port B are EM2 capable. These pins may be used by Low-Energy peripherals in EM2/3 and may also be
used as EM2/3 pin wake-ups. Pins on ports C and D are latched/retained in their current state when entering EM2 until EM2 exit upon
which internal peripherals could once again drive those pads.
A few GPIOs also have EM4 wake functionality. These pins are listed in the Alternate Function Table.
3.4 Clocking
3.4.1 Clock Management Unit (CMU)
The Clock Management Unit controls oscillators and clocks in the EFR32MG21. Individual enabling and disabling of clocks to all periph-
eral modules is performed by the CMU. The CMU also controls enabling and configuration of the oscillators. A high degree of flexibility
allows software to optimize energy consumption in any specific application by minimizing power dissipation in unused peripherals and
oscillators.
3.4.2 Internal and External Oscillators
The EFR32MG21 supports two crystal oscillators and fully integrates five RC oscillators, listed below.
• A high frequency crystal oscillator (HFXO) with integrated load capacitors, tunable in small steps, provides a precise timing refer-
ence for the MCU and RF synthesizer. The HFXO provides excellent RF clocking performance using a 38.4 MHz crystal. The HFXO
can also support an external clock source such as a TCXO for applications that require an extremely accurate clock frequency over
temperature.
• A 32.768 kHz crystal oscillator (LFXO) provides an accurate timing reference for low energy modes.
• An integrated high frequency RC oscillator (HFRCO) is available for the MCU system, when crystal accuracy is not required. The
HFRCO employs fast start-up at minimal energy consumption combined with a wide frequency range, from 1 MHz to 80 MHz.
• An integrated high frequency RC oscillator (HFRCOEM2) runs down to EM2 and is available for timing the general-purpose ADC
and the Serial Wire Viewer port with a wide frequency range.
• An integrated fast start-up RC oscillator (FSRCO) that runs at a fixed 20 MHz
• An integrated low frequency 32.768 kHz RC oscillator (LFRCO) for low power operation where high accuracy is not required.
• An integrated ultra-low frequency 1 kHz RC oscillator (ULFRCO) is available to provide a timing reference at the lowest energy con-
sumption in low energy modes.
3.5 Counters/Timers and PWM
3.5.1 Timer/Counter (TIMER)
TIMER peripherals keep track of timing, count events, generate PWM outputs and trigger timed actions in other peripherals through the
Peripheral Reflex System (PRS). The core of each TIMER is a 16-bit or 32-bit counter with up to 3 compare/capture channels. Each
channel is configurable in one of three modes. In capture mode, the counter state is stored in a buffer at a selected input event. In
compare mode, the channel output reflects the comparison of the counter to a programmed threshold value. In PWM mode, the TIMER
supports generation of pulse-width modulation (PWM) outputs of arbitrary waveforms defined by the sequence of values written to the
compare registers. In addition some timers offer dead-time insertion.
See 3.12 Configuration Summary for information on the feature set of each timer.
3.5.2 Low Energy Timer (LETIMER)
The unique LETIMER is a 24-bit timer that is available in energy mode EM0 Active, EM1 Sleep, EM2 Deep Sleep, and EM3 Stop. This
allows it to be used for timing and output generation when most of the device is powered down, allowing simple tasks to be performed
while the power consumption of the system is kept at an absolute minimum. The LETIMER can be used to output a variety of wave-
forms with minimal software intervention. The LETIMER is connected to the Peripheral Reflex System (PRS), and can be configured to
start counting on compare matches from other peripherals such as the Real Time Clock.

System Overview
3.5.3 Real Time Clock with Capture (RTCC)
The Real Time Clock with Capture (RTCC) is a 32-bit counter providing timekeeping down to EM3. The RTCC can be clocked by any of
the on-board low-frequency oscillators, and it is capable of providing system wake-up at user defined intervals.
A secondary RTC is used by the RF protocol stack for event scheduling, leaving the primary RTCC block available exclusively for appli-
cation software.
3.5.4 Back-Up Real Time Counter (BURTC)
The Back-Up Real Time Counter (BURTC) is a 32-bit counter providing timekeeping in all energy modes, including EM4. The BURTC
can be clocked by any of the on-board low-frequency oscillators, and it is capable of providing system wake-up at user-defined inter-
vals.
3.5.5 Watchdog Timer (WDOG)
The watchdog timer can act both as an independent watchdog or as a watchdog synchronous with the CPU clock. It has windowed
monitoring capabilities, and can generate a reset or different interrupts depending on the failure mode of the system. The watchdog can
also monitor autonomous systems driven by the Peripheral Reflex System (PRS).
3.6 Communications and Other Digital Peripherals
3.6.1 Universal Synchronous/Asynchronous Receiver/Transmitter (USART)
The Universal Synchronous/Asynchronous Receiver/Transmitter is a flexible serial I/O module. It supports full duplex asynchronous
UART communication with hardware flow control as well as RS-485, SPI, MicroWire and 3-wire. It can also interface with devices sup-
porting:
• ISO7816 SmartCards
• IrDA
• I2S
3.6.2 Inter-Integrated Circuit Interface (I2C)
The I2C module provides an interface between the MCU and a serial I2C bus. It is capable of acting as a main or secondary interface
and supports multi-drop buses. Standard-mode, fast-mode and fast-mode plus speeds are supported, allowing transmission rates from
10 kbit/s up to 1 Mbit/s. Bus arbitration and timeouts are also available, allowing implementation of an SMBus-compliant system. The
interface provided to software by the I2C module allows precise timing control of the transmission process and highly automated trans-
fers. Automatic recognition of addresses is provided in active and low energy modes. Note that not all instances of I2C are available in
all energy modes.
3.6.3 Peripheral Reflex System (PRS)
The Peripheral Reflex System provides a communication network between different peripheral modules without software involvement.
Peripheral modules producing Reflex signals are called producers. The PRS routes Reflex signals from producers to consumer periph-
erals which in turn perform actions in response. Edge triggers and other functionality such as simple logic operations (AND, OR, NOT)
can be applied by the PRS to the signals. The PRS allows peripherals to act autonomously without waking the MCU core, saving pow-
er.

System Overview
3.7 Secure Vault Features
A dedicated hardware secure engine containing its own CPU enables the Secure Vault functions. It isolates cryptographic functions and
data from the host Cortex-M33 core, and provides several additional security features. The EFR32MG21 family includes devices with
Secure Vault High and Secure Vault Mid capabilities, which are summarized in the table below.
Table 3.1. Secure Vault Features
Feature Secure Vault Mid Secure Vault High
True Random Number Generator (TRNG) Yes Yes
Secure Boot with Root of Trust and Secure Yes Yes

Loader (RTSL)
Secure Debug with Lock/Unlock Yes Yes
DPA Countermeasures Yes Yes
Anti-Tamper Yes
Secure Attestation Yes
Secure Key Management Yes
Symmetric Encryption • AES 128 / 192 / 256 bit • AES 128 / 192 / 256 bit
• ECB, CTR, CBC, CFB, CCM, GCM, • ECB, CTR, CBC, CFB, CCM, GCM,
CBC-MAC, and GMAC CBC-MAC, and GMAC
• ChaCha20
Public Key Encryption - ECDSA / ECDH / • p192 and p256 • p192, p256, p384 and p521
EdDSA • Curve25519 (ECDH)1 • Curve25519 (ECDH)
• Ed25519 (EdDSA)1 • Ed25519 (EdDSA)
Key Derivation • ECJ-PAKE p192 and p256 • ECJ-PAKE p192, p256, p384, and p521
• PBKDF2
• HKDF
Hashes • SHA-1 • SHA-1

• SHA-2/256 • SHA-2 256, 384, and 512
• Poly1305
Note:
1. These curves are supported in devices running SE v1.2.11 and higher
3.7.1 Secure Boot with Root of Trust and Secure Loader (RTSL)
The Secure Boot with RTSL authenticates a chain of trusted firmware that begins from an immutable memory (ROM).
It prevents malware injection, prevents rollback, ensures that only authentic firmware is executed, and protects Over The Air updates.
For more information about this feature, see AN1218: Series 2 Secure Boot with RTSL.

System Overview
3.7.2 Cryptographic Accelerator
The Cryptographic Accelerator is an autonomous hardware accelerator with Differential Power Analysis (DPA) countermeasures to pro-
tect keys.
It supports AES encryption and decryption with 128/192/256-bit keys, ChaCha20 encryption, and Elliptic Curve Cryptography (ECC) to
support public key operations, and hashes.
Supported block cipher modes of operation for AES include:

• ECB (Electronic Code Book)
• CTR (Counter Mode)
• CBC (Cipher Block Chaining)
• CFB (Cipher Feedback)
• GCM (Galois Counter Mode)
• CCM (Counter with CBC-MAC)
• CBC-MAC (Cipher Block Chaining Message Authentication Code)
• GMAC (Galois Message Authentication Code)
The Cryptographic Accelerator accelerates Elliptical Curve Cryptography and supports the NIST (National Institute of Standards and
Technology) recommended curves including P-192, P-256, P-384, and P-521 for ECDH (Elliptic Curve Diffie-Hellman) key derivation,
and ECDSA (Elliptic Curve Digital Signature Algorithm) sign and verify operations. Also supported is the non-NIST Curve25519 for
ECDH and Ed25519 for EdDSA (Edwards-curve Digital Signature Algorithm) sign and verify operations.
Secure Vault also supports ECJ-PAKE (Elliptic Curve variant of Password Authenticated Key Exchange by Juggling) and PBKDF2
(Password-Based Key Derivation Function 2).
Supported hashes include SHA-1, SHA-2/256/384/512 and Poly1305.
This implementation provides a fast and energy efficient solution to state of the art cryptographic needs.
3.7.3 True Random Number Generator
The True Random Number Generator module is a non-deterministic random number generator that harvests entropy from a thermal
energy source. It includes start-up health tests for the entropy source as required by NIST SP800-90B and AIS-31 as well as online
health tests required for NIST SP800-90C.
The TRNG is suitable for periodically generating entropy to seed an approved pseudo random number generator.
3.7.4 Secure Debug with Lock/Unlock
For obvious security reasons, it is critical for a product to have its debug interface locked before being released in the field.
Secure Vault also provides a secure debug unlock function that allows authenticated access based on public key cryptography. This
functionality is particularly useful for supporting failure analysis while maintaining confidentiality of IP and sensitive end-user data.
For more information about this feature, see AN1190: Series 2 Secure Debug.
3.7.5 DPA Countermeasures
The AES and ECC accelerators have Differential Power Analysis (DPA) countermeasures support. This makes it very expensive from a
time and effort standpoint to use DPA to recover secret keys.
3.7.6 Secure Key Management with PUF
Key material in Secure Vault High products is protected by "key wrapping" with a standardized symmetric encryption mechanism. This
method has the advantage of protecting a virtually unlimited number of keys, limited only by the storage that is accessible by the Cor-
tex-M33, which includes off-chip storage as well. The symmetric key used for this wrapping and unwrapping must be highly secure be-
cause it can expose all other key materials in the system. The Secure Vault Key Management system uses a Physically Unclonable
Function (PUF) to generate a persistent device-unique seed key on power up to dynamically generate this critical wrapping/unwrapping
key which is only visible to the AES encryption engine and is not retained when the device loses power.

System Overview
3.7.7 Anti-Tamper
Secure Vault High devices provide internal tamper protection which monitors parameters such as voltage, temperature, and electro-
magnetic pulses as well as detecting tamper of the security sub-system itself. Additionally, 8 external configurable tamper pins support
external tamper sources, such as enclosure tamper switches.
For each tamper event, the user is able to select the severity of the tamper response ranging from an interrupt, to a reset, to destroying
the PUF reconstruction data which will make all protected key materials un-recoverable and effectively render the device inoperable.
The tamper system also has an internal resettable event counter with programmable trigger threshold and refresh periods to mitigate
false positive tamper events.
For more information about this feature, see AN1247: Anti-Tamper Protection Configuration and Use.
3.7.8 Secure Attestation
Secure Vault High products support Secure Attestation, which begins with a secure identity that is created during the Silicon Labs man-
ufacturing process. During device production, each device generates its own public/private keypair and securely stores the wrapped
private key into immutable OTP memory and this key never leaves the device. The corresponding public key is extracted from the de-
vice and inserted into a binary DER-encoded X.509 device certificate, which is signed into a Silicon Labs CA chain and then program-
med back into the chip into an immutable OTP memory.
The secure identity can be used to authenticate the chip at any time in the life of the product. The production certification chain can be
requested remotely from the product. This certification chain can be used to verify that the device was authentically produced by Silicon
Labs. The device unique public key is also bound to the device certificate in the certification chain. A challenge can be sent to the chip
at any point in time to be signed by the device private key. The public key in the device certificate can then be used to verify the chal-
lenge response, proving that the device has access to the securely-stored private key, which prevents counterfeit products or imperso-
nation attacks.
For more information about this feature, see AN1268: Authenticating Silicon Labs Devices Using Device Certificates.
3.8 Analog
3.8.1 Analog Comparator (ACMP)
The Analog Comparator is used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is high-
er. Inputs are selected from among internal references and external pins. The tradeoff between response time and current consumption
is configurable by software. Two 6-bit reference dividers allow for a wide range of internally-programmable reference sources. The
ACMP can also be used to monitor the supply voltage. An interrupt can be generated when the supply falls below or rises above the
programmable threshold.
3.8.2 Analog to Digital Converter (IADC)
The IADC is a hybrid architecture combining techniques from both SAR and Delta-Sigma style converters. It has a resolution of up to 12
bits at up to 1 Msps. Hardware oversampling reduces system-level noise over multiple front-end samples. The IADC includes integrated
voltage references. Inputs are selectable from a wide range of sources, including pins configurable as either single-ended or differential.
3.9 Reset Management Unit (RMU)
The RMU is responsible for handling reset of the EFR32MG21. A wide range of reset sources are available, including several power
supply monitors, pin reset, software controlled reset, core lockup reset, and watchdog reset.

System Overview
3.10 Core and Memory
3.10.1 Processor Core
The ARM Cortex-M processor includes a 32-bit RISC processor integrating the following features and tasks in the system:
• ARM Cortex-M33 RISC processor achieving 1.50 Dhrystone MIPS/MHz
• ARM TrustZone security technology
• Embedded Trace Macrocell (ETM) for real-time trace and debug
• Up to 1024 kB flash program memory
• Up to 96 kB RAM data memory
• Configuration and event handling of all modules
• 2-pin Serial-Wire debug interface
3.10.2 Memory System Controller (MSC)
The Memory System Controller (MSC) is the program memory unit of the microcontroller. The flash memory is readable and writable
from both the Cortex-M33 and LDMA. In addition to the main flash array where Program code is normally written the MSC also provides
an Information block where additional information such as special user information or flash-lock bits are stored. There is also a read-
only page in the information block containing system and device calibration data. Read and write operations are supported in energy
modes EM0 Active and EM1 Sleep.
3.10.3 Linked Direct Memory Access Controller (LDMA)
The Linked Direct Memory Access (LDMA) controller allows the system to perform memory operations independently of software. This
reduces both energy consumption and software workload. The LDMA allows operations to be linked together and staged, enabling so-
phisticated operations to be implemented.

System Overview
3.11 Memory Map
The EFR32MG21 memory map is shown in the figures below. RAM and flash sizes are for the largest memory configuration.
0xfffffffe
0xe0100000
0xe00fffff
M33 Peripherals
0xe0000000
0xe0100000
0xdfffffff M33 ROM Table
0xe00ff000
0xb0003000
0xe0042000
0xb0002fff Embedded Trace Macrocell (ETM)
FRCRAM (non-secure) 0xe0041000
0xb0002000 Trace Port Interface Unit (TPIU)
0xe0040000
0xb0001fff
SEQRAM (non-secure) 0xe000f000
0xb0000000 System Control Space
0xe000e000
0xafffffff
0xe0003000
0xa0003000 Flash Patch and Breakpoint (FPB)
0xe0002000
0xa0002fff Data Watchpoint and Trace (DWT)
FRCRAM (secure) 0xe0001000
0xa0002000 Instrumentation Trace Macrocell (ITM)
0xe0000000
0xa0001fff
SEQRAM (secure)
0xa0000000
0x9fffffff
0x60000000
0x5fffffff
Peripherals (non-secure)
0x50000000
0x4fffffff
Peripherals (secure)
0x40000000
0x3fffffff 0x0fe0e400
FLASH_CHIPCONFIG
0x20018000 0x0fe0e000
0x20017fff
RAM (DMEM)
0x20000000 0x0fe08400
0x1fffffff FLASH_DEVINFO
0x0fe08000
0x0fe00400
Flash FLASH_USERDATA
0x0fe00000
0x00100000
0x00000000 FLASH
0x00000000
Figure 3.2. EFR32MG21 Memory Map — Core Peripherals and Code Space
3.12 Configuration Summary
The features of the EFR32MG21 are a subset of the feature set described in the device reference manual. The table below describes
device specific implementation of the features. Remaining modules support full configuration.
Table 3.2. Configuration Summary
Module Lowest Energy Mode Configuration
TIMER0 EM1 32-bit, 3-channels, +DTI
USART0 EM1 +IrDA, +I2S, +SmartCard
I2C0 EM2 / EM3
I2C1 EM1

Electrical Specifications
4. Electrical Specifications
4.1 Electrical Characteristics for Revision B
All electrical parameters in all tables are specified under the following conditions, unless stated otherwise:
• Typical values are based on TA = 25 °C and all supplies at 3.0 V, by production test and/or technology characterization.
• Radio performance numbers are measured in conducted mode, based on Silicon Laboratories reference designs using output pow-
er-specific external RF impedance-matching networks for interfacing to a 50 Ω antenna.
• Minimum and maximum values represent the worst conditions across supply voltage, process variation, and operating temperature,
unless stated otherwise.
Power Supply Pin Dependencies
Due to on-chip circuitry (e.g., diodes), some EFR32 power supply pins have a dependent relationship with one or more other power
supply pins. These internal relationships between the external voltages applied to the various EFR32 supply pins are defined below.
Exceeding the below constraints can result in damage to the device and/or increased current draw.
• DVDD ≥ DECOUPLE
• PAVDD ≥ RFVDD
• AVDD, IOVDD: No dependency with each other or any other supply pin. Additional leakage may occur if DVDD remains unpowered
with power applied to these supplies.

4.1.1 Absolute Maximum Ratings
Stresses above those listed below may cause permanent damage to the device. This is a stress rating only and functional operation of
the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure
to maximum rating conditions for extended periods may affect device reliability.
Table 4.1. Absolute Maximum Ratings
Parameter Symbol Test Condition Min Typ Max Unit
Storage temperature range TSTG -50 — +150 °C
Junction temperature TJMAX -I grade — — +135 °C
Voltage on any supply pin VDDMAX -0.3 — 3.8 V
Voltage ramp rate on any VDDRAMPMAX — — 1.0 V / µs

supply pin
Voltage on HFXO pins VHFXOPIN -0.3 — 1.2 V
DC voltage on any GPIO pin VDIGPIN -0.3 — VIOVDD + V

0.3
DC voltage on RESETn pin1 VRESETn -0.3 — 3.8 V
Input RF level on pins PRFMAX2G4 — — +10 dBm

RF2G4_IO1 and
RF2G4_IO2
Absolute voltage on RF pins VMAX2G4 -0.3 — VPAVDD V

RF2G4_IOx
Total current into VDD power IVDDMAX Source — — 200 mA

lines
Total current into VSS IVSSMAX Sink — — 200 mA

ground lines
Current per I/O pin IIOMAX Sink — — 50 mA
Source — — 50 mA
Current for all I/O pins IIOALLMAX Sink — — 200 mA
Note:
1. The RESETn pin has a pull-up device to the DVDD supply. For minimum leakage, RESETn should not exceed the voltage at
DVDD.

4.1.2 General Operating Conditions
This table specifies the general operating temperature range and supply voltage range for all supplies. The minimum and maximum
values of all other tables are specifed over this operating range, unless otherwise noted.
Table 4.2. General Operating Conditions
Operating ambient tempera- TA -I temperature grade 1 -40 — +125 °C

ture range
DVDD supply voltage VDVDD EM0/1 1.71 3.0 3.8 V
EM2/3/42 1.71 3.0 3.8 V
AVDD supply voltage VAVDD 1.71 3.0 3.8 V
IOVDDx operating supply VIOVDDx 1.71 3.0 3.8 V

voltage (All IOVDD pins)
PAVDD operating supply VPAVDD 1.71 3.0 3.8 V

voltage
RFVDD operating supply VRFVDD 1.71 3.0 VPAVDD V

voltage
DECOUPLE output capaci- CDECOUPLE 0.75 1.0 2.75 µF

tor3
HCLK and Core frequency fHCLK MODE = WS1, RAMWSEN = 14 — — 80 MHz
MODE = WS1, RAMWSEN = 04 — — 50 MHz
PCLK frequency fPCLK — — 50 MHz
EM01 Group A clock fre- fEM01GRPACLK — — 80 MHz

quency
HCLK Radio frequency5 fHCLKRADIO 38 38.4 40 MHz
External Clock Input fCLKIN VSCALE2 or VSCALE1, IOVDD ≥ — — 40 MHz

2.7 V
DPLL Reference Clock fDPLLREFCLK VSCALE2 or VSCALE1 — — 40 MHz
Note:
1. The device may operate continuously at the maximum allowable ambient TA rating as long as the absolute maximum TJMAX is not
exceeded. For an application with significant power dissipation, the allowable TA may be lower than the maximum TA rating. TA =
TJMAX - (THETAJA x PowerDissipation). Refer to the Absolute Maximum Ratings table and the Thermal Characteristics table for
TJMAX and THETAJA.
2. The DVDD supply is monitored by the DVDD BOD in EM0/1 and the LE DVDD BOD in EM2/3/4.
3. The system designer should consult the characteristic specs of the capacitor used on DECOUPLE to ensure its capacitance val-
ue stays within the specified bounds across temperature and DC bias.
4. Flash wait states are set by the MODE field in the MSC_READCTRL register. RAM wait states are enabled by setting the RAMW-
SEN bit in the SYSYCFG_DMEM0RAMCTRL register.
5. The recommended radio crystal frequency is 38.4 MHz. Any crystal frequency other than 38.4 MHz is expressly not supported.
The minimum and maximum HCLKRADIO frequency in this table represent the design limits, which are much wider than the typi-
cal crystal tolerance.

4.1.3 Thermal Characteristics
Table 4.3. Thermal Characteristics
Thermal Resistance Junction THE- 2-Layer PCB, Natural Convection1 — 94.3 — °C/W
to Ambient QFN32 (4x4mm) TAJA_QFN32_4X4
Package 4-Layer PCB, Natural Convection1 — 35.4 — °C/W
to Case QFN32 (4x4mm) TAJC_QFN32_4X4
Note:
1. Measured according to JEDEC standard JESD51-2A. Integrated Circuit Thermal Test Method Environmental Conditions - Natural
Convection (Still Air).

4.1.4 Current Consumption
4.1.4.1 MCU Current Consumption at 1.8 V
Unless otherwise indicated, typical conditions are: AVDD = DVDD = RFVDD = PAVDD = 1.8V. TA = 25 °C. Minimum and maximum
values in this table represent the worst conditions across process variation at TA = 25 °C.
Table 4.4. MCU Current Consumption at 1.8 V
Current consumption in EM0 IACTIVE 80 MHz HFRCO, CPU running — 50.9 — µA/MHz
mode with all peripherals dis- Prime from flash
abled1
80 MHz HFRCO, CPU running — 45.5 — µA/MHz
while loop from flash

CoreMark loop from flash
38.4 MHz crystal, CPU running — 63.6 — µA/MHz




1 MHz HFRCO, CPU running — 360 — µA/MHz

Current consumption in EM1 IEM1 80 MHz HFRCO — 28.7 — µA/MHz

mode with all peripherals dis-
abled1 38.4 MHz crystal — 46.7 — µA/MHz
38 MHz HFRCO — 38.7 — µA/MHz
1 MHz HFRCO — 343 — µA/MHz
Current consumption in EM2 IEM2 Full RAM retention and RTC run- — 5.0 — µA
mode ning from LFXO
Full RAM retention and RTC run- — 5.0 — µA

ning from LFRCO
1 bank (16kB) RAM retention and — 4.5 — µA

RTC running from LFRCO
mode ning from ULFRCO

RTC running from ULFRCO
Current consumption in EM4 IEM4 No BURTC, no LF oscillator — 0.14 — µA

mode
BURTC with LFXO — 0.51 — µA
Current consumption during IRST Hard pin reset held — 107 — µA

reset

Current Consumption per re- IRAM — 0.10 — µA

tained 16kB RAM bank in
EM2
Note:
1. The typical EM0/EM1 current measurement includes some current consumed by the security core for periodical housekeeping
purposes. This does not include current consumed by user-triggered security operations, such as cryptographic calculations.

Unless otherwise indicated, typical conditions are: AVDD = DVDD = RFVDD = PAVDD = 3.0 V. TA = 25 °C. Minimum and maximum
abled1
80 MHz HFRCO, CPU running — 45.6 55.5 µA/MHz





1 MHz HFRCO, CPU running — 362 1018 µA/MHz

Current consumption in EM1 IEM1 80 MHz HFRCO — 28.7 37.6 µA/MHz

38 MHz HFRCO — 38.7 57.5 µA/MHz
1 MHz HFRCO — 345 994 µA/MHz
mode ning from LFXO

ning from LFRCO
1 bank (16 kB) RAM retention and — 4.5 10.5 µA

Current consumption in EM3 IEM3 Full RAM retention and RTC run- — 4.8 11.4 µA
1 bank (16 kB) RAM retention and — 4.3 — µA

Current consumption in EM4 IEM4 No BURTC, no LF oscillator — 0.21 0.5 µA

mode

reset
Current consumption per re- IRAM — 0.10 — µA

EM2

Note:
4.1.4.3 Radio Current Consumption at 1.8 V
RF current consumption measured with MCU in EM1, HCLK = 38.4 MHz, and all MCU peripherals disabled. Unless otherwise indica-
ted, typical conditions are: AVDD = DVDD = IOVDD = RFVDD = PAVDD = 1.8V. Minimum and maximum values in this table represent
the worst conditions across process variation at TA = 25 °C.
Table 4.6. Radio Current Consumption at 1.8 V
Current consumption in re- IRX_ACTIVE 125 kbit/s, 2GFSK, f = 2.4 GHz — 9.0 — mA
ceive mode, active packet
reception 500 kbit/s, 2GFSK, f = 2.4 GHz — 9.1 — mA
1 Mbit/s, 2GFSK, f = 2.4 GHz — 8.8 — mA
802.15.4 receiving frame, f = 2.4 — 9.4 — mA

GHz
Current consumption in re- IRX_LISTEN 125 kbit/s, 2GFSK, f = 2.4 GHz — 9.0 — mA
ceive mode, listening for
packet 500 kbit/s, 2GFSK, f = 2.4 GHz — 9.0 — mA
802.15.4, f = 2.4 GHz — 9.2 — mA
Current consumption in ITX f = 2.4 GHz, CW, 0 dBm PA, 0 — 9.3 — mA

transmit mode dBm output power
f = 2.4 GHz, CW, 10 dBm PA, 0 — 16.6 — mA

dBm output power
f = 2.4 GHz, CW, 10 dBm PA, 10 — 33.8 — mA

dBm output power


GHz
802.15.4, f = 2.4 GHz — 9.2 — mA

f = 2.4 GHz, CW, 10 dBm PA, 0 — 16.7 — mA

dBm output power
f = 2.4 GHz, CW, 10 dBm PA, 10 — 34.0 — mA

dBm output power
f = 2.4 GHz, CW, 20 dBm PA, 10 — 60.8 — mA

dBm output power, PAVDD = 3.0
V
f = 2.4 GHz, CW, 20 dBm PA, 20 — 185 — mA

V

4.1.5 2.4 GHz RF Transceiver Characteristics
4.1.5.1 RF Transmitter Characteristics
4.1.5.1.1 RF Transmitter General Characteristics for the 2.4 GHz Band
Unless otherwise indicated, typical conditions are: TA = 25 °C, PAVDD = 3.0V, AVDD = DVDD = IOVDD = RFVDD = PAVDD. Crystal
frequency=38.4 MHz. RF center frequency 2.45 GHz. Antenna port 2.
Table 4.8. RF Transmitter General Characteristics for the 2.4 GHz Band
RF test frequency range FRANGE 2400 — 2483.5 MHz
Maximum TX power 1 POUTMAX 20 dBm PA, PAVDD = 3.3 V — +20.2 — dBm
Maximum TX power POUTMAX10 10 dBm PA — +10.5 — dBm
Maximum TX power POUTMAX0 0 dBm PA — +0.4 — dBm
Minimum active TX power POUTMIN 20 dBm PA, PAVDD = 3.3 V — -20.5 — dBm
10 dBm PA — -19.3 — dBm
0 dBm PA — -23.5 — dBm
Output power step size POUTSTEP 0 dBm PA,-15 dBm < Output — 1.5 — dB
Power < -5 dBm
0 dBm PA,-5 dBm < Output Pow- — 0.3 — dB

er < 0 dBm
10 dBm PA, -5 dBm < Output — 1.5 — dB

power < 0 dBm
10 dBm PA, 0 dBm < Output pow- — 1.0 — dB

er < 10 dBm
20 dBm PA, 0 dBm < Output Pow- — 0.7 — dB

er < 5 dBm
20 dBm PA, 5 dBm < output pow- — 0.5 — dB

er < POUTMAX
Output power variation vs POUTVAR_V 20 dBm PA Pout = POUTMAX out- — 0.8 — dB

PAVDD supply voltage varia- put power with PAVDD voltage
tion, frequency = 2450 MHz swept from 3.0V to 3.8V.
10 dbm PA output power with — 0.1 — dB

PAVDD voltage swept from 1.8 V
to 3.0 V
0 dBm PA output power with — 0.1 — dB

to 3.0 V
Output power variation vs POUTVAR_T AVDD = 3.3V supply, 20 dBm PA — 1.5 — dB

temperature, Frequency = at Pout = POUTMAX, (-40 to +125
2450 MHz °C)
10 dBm PA at 10 dBm, (-40 to — 0.3 — dB

+125 °C)
0 dBm PA at 0 dBm, (-40 to +125 — 2.1 — dB

°C)

Output power variation vs RF POUTVAR_F 20 dBm PA, POUTMAX, PAVDD = — 0.2 — dB

frequency 3.3 V.
10 dBm PA, 10 dBm — 0.2 — dB
0 dBm PA, 0 dBm — 0.1 — dB
Spurious emissions of har- SPURHRM_FCC_ Continuous transmission of CW — -47 — dBm

monics in restricted bands R carrier. Pout = POUTMAX. PAVDD
per FCC Part 15.205/15.209 = 3.3V. Test Frequency = 2450
MHz.
Continuous transmission of CW — -47 — dBm

carrier, Pout = 10 dBm, Test Fre-
quency = 2450 MHz.
Spurious emissions of har- SPURHRM_FCC_ Continuous transmission of CW — -26 — dBc

monics in non-restricted NRR carrier, Pout = POUTMAX, PAVDD
bands per FCC Part = 3.3V, Test Frequency = 2450
15.247/15.35 MHz.
Continuous transmission of CW — -26 — dBc

carrier. Pout = 10 dBm. Test Fre-
quency = 2450 MHz.

Spurious emissions out-of- SPUROOB_FCC_ Restricted bands 30-88 MHz, — -47 — dBm
band (above 2.483 GHz or R Continuous transmission of CW
below 2.4 GHz) in restricted carrier, 20 dBm PA, Pout =
bands, per FCC part POUTMAX, PAVDD = 3.3V. Test
15.205/15.209 Frequency = 2450 MHz.
Restricted bands 88 - 216 MHz, — -47 — dBm

Continuous transmission of CW
carrier, 20 dBm PA, Pout =
POUTMAX, PAVDD = 3.3V. Test
Frequency = 2450 MHz.

carrier, 20 dBm PA Pout =
Restricted bands >960 MHz, Con- — -47 — dBm

tinuous transmission of CW carri-
er, 20 dBm PA, Pout = POUTMAX,
PAVDD = 3.3V, Test Frequency =
2450 MHz.
Restricted bands 30-88 MHz, — -47 — dBm

quency = 2450 MHz

quency = 2450 MHz

quency = 2450 MHz
Restricted bands > 960 MHz, — -47 — dBm

quency = 2450 MHz
Spurious emissions per ETSI SPURETSI440 1G-14G, Pout = 10 dBm, Test Fre- — -36 — dBm
EN300.440 quency = 2450 MHz
47-74 MHz,87.5-108 MHz, — -56 — dBm

174-230 MHz, 470-862 MHz, Pout
= 10 dBm, Test Frequency = 2450
MHz
25-1000 MHz, excluding above — -42 — dBm

frequencies. Pout = 10 dBm, Test
Frequency = 2450 MHz
1G-12.75 GHz, excluding bands — -50 — dBm

listed above, Pout = 10 dBm, Test

Spurious emissions out-of- SPUROOB_FCC_ Frequencies above 2.483 GHz or — -26 — dBc
band in non-restricted bands NR below 2.4 GHz, continuous trans-
per FCC Part 15.247 mission CW carrier, 20 dBm PA,
Pout = POUTMAX, PAVDD = 3.3
V,Test Frequency = 2450 MHz
Frequencies above 2.483 GHz or — -26 — dBc

below 2.4 GHz, continuous trans-
mission CW carrier, Pout = 10
dBm, Test Frequency = 2450
MHz
Spurious emissions out-of- SPURETSI328 [2400-2BW to 2400-BW], — -26 — dBm

band, per ETSI 300.328 [2483.5+BW to 2483.5+2BW],
Pout = 10 dBm, Test Frequency =
2450 MHz
[2400-BW to 2400], [2483.5 to — -16 — dB

2483.5+BW] Pout = 10 dBm, Test
Note:
1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices cov-
ered in this data sheet can be found in the Max TX Power column of the Ordering Information Table.

4.1.5.1.2 RF Transmitter Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band
Table 4.9. RF Transmitter Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band
Error vector magnitude per EVM Average across frequency, signal — 2.7 — % rms
802.15.4-2011 is DSSS-OQPSK reference pack-
et, PAVDD = 3.3 V, Pout =
POUTMAX
Average across frequency, signal — 2.7 — % rms

is DSSS-OQPSK reference pack-
et, Pout = 10 dBm

et, Pout = 0 dBm
Power spectral density limit PSDLIMIT Relative, at carrier ± 3.5 MHz, — -50.3 — dBc/
PAVDD = 3.3 V, Pout = POUTMAX 100kHz
Relative, at carrier ± 3.5 MHz, — -50.7 — dBc/

Pout = 10 dBm 100kHz

Pout = 0 dBm 100kHz
Absolute, at carrier ± 3.5 MHz, — -38.8 — dBm/

Absolute, at carrier ± 3.5 MHz, — -49 — dBm/


Pout = 0 dBm 100kHz
Per FCC part 15.247, PAVDD = — +5.6 — dBm/

3.3 V, Pout = POUTMAX 3kHz
Per FCC part 15.247, Pout = 10 — -4.4 — dBm/

dBm 3kHz

dBm 3kHz
ETSI 300.328 Pout = 10 dBm — +8.1 — dBm
ETSI 300.328 Pout = 0 dbm — -1.9 — dBm
Occupied channel bandwidth OCPETSI328 99% BW at highest and lowest — 2.3 — MHz
per ETSI EN300.328 channels in band, Pout = 10 dBm
99% BW at highest and lowest — 2.2 — MHz

channels in band, Pout = 0 dBm

4.1.5.1.3 RF Transmitter Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 1 Mbps Data Rate
Table 4.10. RF Transmitter Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 1 Mbps Data Rate
Transmit 6 dB bandwidth TXBW PAVDD = 3.3 V, Pout = POUTMAX — 635.1 — kHz
Pout = 10 dBm — 672.9 — kHz
Pout = 0 dBm — 646.5 — kHz
Power spectral density limit PSDLIMIT PAVDD = 3.3 V, Pout = POUTMAX, — +6.4 — dBm/
Per FCC part 15.247 3kHz
Pout = 10 dBm, Per FCC part — -3.7 — dBm/

15.247 at 10 dBm 3kHz

15.247 at 0 dBm 3kHz
Per ETSI 300.328 at 10 dBm/1 — +10.2 — dBm

MHz
Occupied channel bandwidth OCPETSI328 Pout = 10 dBm 99% BW at highest — 1.1 — MHz
per ETSI EN300.328 and lowest channels in band
Pout = 0 dBm 99% BW at highest — 1.1 — MHz

and lowest channels in band
In-band spurious emissions, SPURINB PAVDD = 3.3 V, Pout = POUTMAX, — -26.3 — dBm
with allowed exceptions1 Inband spurs at ± 2 MHz
Pout = 10 dBm, Inband spurs at ± — -36.4 — dBm

2 MHz
Pout = 0 dBm, Inband spurs at ± 2 — -46.3 — dBm

MHz
PAVDD = 3.3 V, Pout = POUTMAX — -20 — dBm

Inband spurs at ± 3 MHz
Pout = 10 dBm Inband spurs at ± 3 — -41.9 — dBm

MHz

MHz
Note:
1. Per Bluetooth Core_5.1, Vol.6 Part A, Section 3.2.2, exceptions are allowed in up to three bands of 1 MHz width, centered on a
frequency which is an integer multiple of 1 MHz. These exceptions shall have an absolute value of -20 dBm or less.

Pout = 10 dBm — 1182.5 — kHz
Pout = 0 dBm — 1249.7 — kHz

15.247 at 10 dBm 3kHz


MHz


4 MHz

MHz
PAVDD = 3.3 V, Pout = POUTMAX — -35.7 — dBm


MHz

MHz
Note:

4.1.5.1.5 RF Transmitter Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 500 kbps Data Rate
Table 4.12. RF Transmitter Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 500 kbps Data Rate
Pout = 10 dBm — 760.1 — kHz
Pout = 0 dBm — 775.1 — kHz

15.247 at 10 dBm 3kHz


MHz

In-band spurious emissions, SPURINB Pout = 10 dBm, Inband spurs at ± — -38.3 — dBm
with allowed exceptions1 2 MHz

MHz


MHz

MHz
Note:

Pout = 10 dBm — 619.3 — kHz
Pout = 0 dBm — 617.4 — kHz
Pout = 10 dBm, Per FCC part — +4.5 — dBm/

15.247 at 10 dBm 3kHz


MHz


2 MHz

MHz


MHz

MHz
Note:

4.1.5.2 RF Receiver Characteristics
4.1.5.2.1 RF Receiver General Characteristics for the 2.4 GHz Band
Table 4.14. RF Receiver General Characteristics for the 2.4 GHz Band
RF tuning frequency range FRANGE 2400 — 2483.5 MHz
Receive mode maximum SPURRX 30 MHz to 1 GHz — -54.8 — dBm

spurious emission
1 GHz to 12 GHz — -57.1 — dBm
Max spurious emissions dur- SPURRX_FCC 216 MHz to 960 MHz, conducted — -54.8 — dBm
ing active receive mode, per measurement
FCC Part 15.109(a)
Above 960 MHz, conducted — -77.3 — dBm
measurement.

4.1.5.2.2 RF Receiver Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band
Table 4.15. RF Receiver Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band
Rx Max Strong Signal Input RXSAT Signal is reference signal1, packet — 10 — dBm
Level for 1% PER length is 20 octets
Sensitivity, 1% PER SENS Signal is reference signal, packet — -104.5 — dBm

length is 20 octets
Co-channel interferer rejec- CCR Desired signal 3 dB above sensi- — -0.2 — dB

tion, 1% PER tivity limit
Adjacent channel rejection, ACRREF1 Interferer is reference signal at +1 — 39.9 — dB

Interferer is reference signal, channel spacing
1% PER, desired is refer-
ence signal at 3 dB above Interferer is reference signal at -1 — 39.2 — dB
reference sensitivity level2 channel spacing
Alternate channel rejection, ACRREF2 Interferer is reference signal at +2 — 51.1 — dB

interferer is reference signal, channel spacing
Image rejection, 1% PER, IR Interferer is CW in image band3 — 43.5 — dB

desired is reference signal at
3 dB above reference sensi-
tivity level2
Blocking rejection of all other BLOCK Interferer frequency < desired fre- — 57.6 — dB
channels, 1% PER, desired quency -3 channel spacing
is reference signal at 3 dB
above reference sensitivity Interferer frequency > desired fre- — 57.5 — dB
level2, interferer is reference quency +3 channel spacing
signal
RSSI resolution RSSIRES -100 dBm to +5 dBm — 0.25 — dB
RSSI accuracy in the linear RSSILIN — +/-6 — dB

region as defined by
802.15.4-2020
Note:
1. Reference signal is defined as O-QPSK DSSS per 802.15.4, Frequency range = 2400-2483.5 MHz, Symbol rate = 62.5 ksym-
bols/s.
2. Reference sensitivity level is -85 dBm.
3. Due to low-IF frequency, there is some overlap of adjacent channel and image channel bands. Adjacent channel CW blocker
tests place the Interferer center frequency at the Desired frequency ± 5 MHz on the channel raster, whereas the image rejection
test places the CW interferer near the image frequency of the Desired signal carrier, regardless of the channel raster.

4.1.5.2.3 RF Receiver Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 1 Mbps Data Rate
Table 4.16. RF Receiver Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 1 Mbps Data Rate
Rx Max Strong Signal Input RXSAT Signal is reference signal, packet — 10 — dBm
Level for 0.1% BER length is 37 bytes1
Sensitivity SENS Signal is reference signal, 37 byte — -97.5 — dBm

payload1
With non-ideal signals2 1 — -97.1 — dBm
Signal to co-channel interfer- C/ICC (see notes)1 3 — +6.6 — dB

er
N ± 1 Adjacent channel se- C/I1 Interferer is reference signal at +1 — -8.3 — dB

lectivity MHz offset1 4 3 5
Interferer is reference signal at -1 — -8.7 — dB

MHz offset1 4 3 5
N ± 2 Alternate channel se- C/I2 Interferer is reference signal at +2 — -42.1 — dB


MHz offset1 4 3 5


MHz offset1 4 3 5
Selectivity to image frequen- C/IIM Interferer is reference signal at im- — -42.1 — dB

cy age frequency with 1 MHz preci-
sion1 5
Selectivity to image frequen- C/IIM_1 Interferer is reference signal at im- — -42.4 — dB

cy ± 1 MHz age frequency +1 MHz with 1
MHz precision1 5
Interferer is reference signal at im- — -8.3 — dB

age frequency -1 MHz with 1 MHz
precision1 5
Intermodulation performance IM n=36 — -23 — dBm
Note:
1. 0.1% Bit Error Rate.
2. With non-ideal signals as specified in Bluetooth Test Specification RF-PHY.TS.5.0.1 section 4.7.1
3. Desired signal -67 dBm.
4. Desired frequency 2402 MHz ≤ Fc ≤ 2480 MHz.
5. With allowed exceptions.
6. As specified in Bluetooth Core specification version 5.1, Vol 6, Part A, Section 4.4

Max usable receiver input SAT Signal is reference signal, packet — 10 — dBm
level length is 37 bytes1

payload1

er


MHz offset1 4 3 5


MHz offset1 4 3 5


MHz offset1 4 3 5

sion1 5

MHz precision1 5
Interferer is reference signal at im- — +6.0 — dB

precision1 5
Intermodulation performance IM n = 36 — -22.3 — dBm
Note:

4.1.5.2.5 RF Receiver Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 500 kbps Data Rate
Table 4.18. RF Receiver Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 500 kbps Data Rate
Sensitivity SENS Signal is reference signal1 — -100.6 — dBm

er


MHz offset1 4 3 5


MHz offset1 4 3 5


MHz offset1 4 3 5

sion1 5

MHz precision1 5

precision1 5
Note:


er


MHz offset1 4 3 5


MHz offset1 4 3 5


MHz offset1 4 3 5

sion1 5

MHz precision1 5

precision1 5
Note:

4.1.6 Flash Characteristics
Table 4.20. Flash Characteristics
Flash erase cycles before ECFLASH TA ≤ 125 °C 10,000 — — cycles

failure1
Flash data retention1 RETFLASH TA ≤ 125 °C 10 — — years
Program Time tPROG one word (32-bits) 40.2 44.0 47.9 µs
average per word over 128 words 9.97 10.9 11.9 µs
Page Erase Time2 tPERASE 11.6 12.7 13.9 ms
Mass Erase Time3 4 tMERASE 11.7 12.8 14.1 ms
Page Erase Current IERASE TA = 25 °C — — 2.13 mA
Program Current IWRITE TA = 25 °C — — 2.73 mA
Mass Erase Current IMERASE TA = 25 °C — — 2.30 mA
Flash Supply voltage during VFLASH 1.71 — 3.8 V

write or erase
Note:
1. Flash data retention information is published in the Quarterly Quality and Reliability Report.
2. Page Erase time is measured from setting the ERASEPAGE bit in the MSC_WRITECMD register until the BUSY bit in the MSC-
STATUS register is cleared to 0. Internal set-up and hold times are included.
3. Mass Erase is issued by the CPU and erases all of User space.
4. Mass Erase time is measured from setting the ERASEMAIN0 bit in the MSC_WRITECMD register until the BUSY bit in the MSC-

4.1.7 Energy Mode Wake-up and Entry Times
Unless otherwise specified, these times are measured using the HFRCO at 19 MHz.
Table 4.21. Energy Mode Wake-up and Entry Times
Wake-up Time from EM1 tEM1_WU Code execution from flash — 3 — HCLKs
Code execution from RAM — 1.43 — µs
Wake-up Time from EM2 tEM2_WU Code execution from flash — 12.2 — µs
Code execution from flash @ 80 — 9.00 — µs

MHz
Code execution from RAM @ 80 — 2.87 — µs

MHz

MHz

MHz
Wake-up Time from EM4 tEM4_WU Code execution from Flash — 17.8 — ms
Entry time to EM1 tEM1_ENT Code execution from flash — 1.52 — µs

4.1.8 Oscillators
4.1.8.1 High Frequency Crystal Oscillator
Unless otherwise indicated, typical conditions are: AVDD = DVDD = RFVDD = 3.0 V. TA = 25 °C. Minimum and maximum values in this
table represent the worst conditions across process variation, operating supply voltage range, and operating temperature range.
Table 4.22. High Frequency Crystal Oscillator
Crystal Frequency FHFXO see note1 2 — 38.4 — MHz
Supported crystal equivalent ESRHFXO_38M4 38.4 MHz, CL = 10 pF3 — — 40 Ω

series resistance (ESR)
Supported range of crystal CHFXO_LC 38.4 MHz, ESR = 404 — 10 — pF

load capacitance
Supply Current IHFXO — 500 — µA
Startup Time5 TSTARTUP 38.4 MHz, ESR = 40 Ω, CL = 10 — 160 — µs

pF
On-chip tuning cap step SSHFXO — 0.04 — pF

size6
Note:
1. The BLE radio requires a 38.4 MHz crystal with a tolerance of ± 50 ppm over temperature and aging. Please use a crystal with
the recommended frequency and tolerance.
2. The ZigBee radio requires a 38.4 MHz crystal with a tolerance of ± 40 ppm over temperature and aging. Please use a crystal with
3. The crystal should have a maximum ESR less than or equal to this maximum rating.
4. It is recommended to use a crystal with a 10 pF load capacitance rating. Only crystals with a 10 pF load cap rating have been
characterized for RF use.
5. Startup time does not include time implemented by programmable TIMEOUTSTEADY delay.
6. The tuning step size is the effective step size when incrementing both of the tuning capacitors by one count. The step size for the
each of the individual tuning capacitors is twice this value.

4.1.8.2 Low Frequency Crystal Oscillator
Table 4.23. Low Frequency Crystal Oscillator
Crystal Frequency FLFXO — 32.768 — kHz
Supported Crystal equivalent ESRLFXO GAIN = 0 — — 80 kΩ

GAIN = 1 to 3 — — 100 kΩ
Supported range of crystal CL_LFXO GAIN = 0 4 — 6 pF

load capacitance 1
GAIN = 1 6 — 10 pF
GAIN = 2 (see note2) 10 — 12.5 pF
GAIN = 3 (see note2) 12.5 — 18 pF
Current consumption ICL12p5 ESR = 70 kΩ, CL = 12.5 pF, — 357 — nA

GAIN3 = 2, AGC4 = 1
Startup Time TSTARTUP ESR = 70 kΩ, CL = 7 pF, GAIN3 = — 63 — ms

1, AGC4 = 1
On-chip tuning cap step size SSLFXO — 0.26 — pF
On-chip tuning capacitor val- CLFXO_MIN CAPTUNE = 0 — 4 — pF

ue at minimum setting5
On-chip tuning capacitor val- CLFXO_MAX CAPTUNE = 0x4F — 24.5 — pF

ue at maximum setting5
Note:
1. Total load capacitance seen by the crystal
2. Crystals with a load capacitance of greater than 12 pF require external load capacitors.
3. In LFXO_CAL Register
4. In LFXO_CFG Register
5. The effective load capacitance seen by the crystal will be CLFXO/2. This is because each XTAL pin has a tuning cap and the two
caps will be seen in series by the crystal

4.1.8.3 High Frequency RC Oscillator (HFRCO)
Unless otherwise indicated, typical conditions are: AVDD = DVDD = 3.0 V. TA = 25 °C. Minimum and maximum values in this table
represent the worst conditions across process variation, operating supply voltage range, and operating temperature range.
Table 4.24. High Frequency RC Oscillator (HFRCO)
Frequency Accuracy FHFRCO_ACC For all production calibrated fre- -3 — +3 %

quencies
Current consumption on all IHFRCO FHFRCO = 1 MHz — 27 — µA

supplies1
FHFRCO = 2 MHz — 27 — µA
FHFRCO = 38 MHz2 — 170 — µA
Clock Out current for ICLKOUT_HFRCOD FORCEEN bit of HFRCO0_CTRL — 3.0 — µA/MHz
HFRCODPLL4 PLL =1
Clock Out current for ICLKOUT_HFRCOE FORCEEN bit of — 1.6 — µA/MHz

HFRCOEM234 M23 HFRCOEM23_CTRL = 1
Coarse trim step Size (% of SSHFRCO_COARS Step size measured at coarse trim — 0.64 — %
period) E mid-scale. (Fine trim also set to
mid scale.)
Fine trim step Size (% of pe- SSHFRCO_FINE Step size measured at fine trim — 0.1 — %
riod) mid-scale. (Coarse trim also set to
mid scale.)
Period jitter PJHFRCO 19 MHz — 0.04 — % RMS
Startup Time5 TSTARTUP FREQRANGE = 0 to 7 — 3.2 — µs
FREQRANGE = 8 to 15 — 1.2 — µs

Band Frequency Limits6 fHFRCO_BAND FREQRANGE = 0 3.71 — 5.24 MHz
FREQRANGE = 1 4.39 — 6.26 MHz
Note:
1. Does not include additional clock tree current. See specifications for additional current when selected as a clock source for a par-
ticular clock multiplexer.
2. This frequency is calibrated for the HFRCODPLL (HFRCO0) only.
3. This frequency is calibrated for the HFRCOEM23 only.
4. When the HFRCO is enabled for characterization using the FORCEEN bit, the total current will be the HFRCO core current plus
the specified CLKOUT current. When the HFRCO is enabled on demand, the clock current may be different.
5. Hardware delay ensures settling to within ± 0.5%. Hardware also enforces this delay on a band change.
6. The frequency band limits represent the lowest and highest frequency which each band can achieve over the operating range.
4.1.8.4 Fast Start_Up RC Oscillator (FSRCO)
Table 4.25. Fast Start_Up RC Oscillator (FSRCO)
FSRCO frequency FFSRCO 17.2 20 21.2 MHz

4.1.8.5 Low Frequency RC Oscillator
Table 4.26. Low Frequency RC Oscillator
Nominal oscillation frequen- FLFRCO 31.785 32.768 33.751 kHz

cy
Frequency calibration step FTRIM_STEP Typical trim step at mid-scale — 0.33 — %
Startup time TSTARTUP — 220 — µs
Current consumption ILFRCO — 186 — nA
4.1.8.6 Ultra Low Frequency RC Oscillator
Table 4.27. Ultra Low Frequency RC Oscillator
Oscillation Frequency FULFRCO 0.944 1.0 1.095 kHz

4.1.9 GPIO Pins (3V GPIO pins)
Unless otherwise indicated, typical conditions are: AVDD = DVDD = IOVDD = 3.0 V.
Table 4.28. GPIO Pins (3V GPIO pins)
Leakage current ILEAK_IO MODEx = DISABLED, IOVDD = — 1.9 — nA

1.71V
MODEx = DISABLED, IOVDD = — 2.5 — nA

3.0 V
MODEx = DISABLED, IOVDD = — — 200 nA

3.8 V TA = 125 °C
Input low voltage1 VIL Any GPIO pin — — 0.3 * V

IOVDD
RESETn — — 0.3 * DVDD V
Input high voltage1 VIH Any GPIO pin 0.7 * — — V

IOVDD
RESETn 0.7 * DVDD — — V
Hysteresis of input voltage VHYS Any GPIO pin 0.05 * — — V

IOVDD
RESETn 0.05 * — — V
DVDD
Output low voltage VOL Sinking 20mA, IOVDD = 3.0 V — — 0.2 * V

IOVDD
Sinking 8mA, IOVDD = 1.71 V — — 0.4 * V

IOVDD
Output high voltage VOH Sourcing 20mA, IOVDD = 3.0 V 0.8 * — — V

IOVDD
Sourcing 8mA, IOVDD = 1.71 V 0.6 * — — V

IOVDD
GPIO rise time TGPIO_RISE IOVDD = 3.0V, Cload = 50pF, — 8.4 — ns

SLEWRATE = 4, 10% to 90%
IOVDD = 1.7V, Cload = 50pF, — 13 — ns

GPIO fall time TGPIO_FALL IOVDD = 3.0V, Cload = 50pF, — 7.1 — ns

IOVDD = 1.7V, Cload = 50pF, — 11.9 — ns

Pull up/down resistance2 RPULL Any GPIO pin. Pull-up to IOVDD: 35 44 55 kΩ

MODEn = DISABLE DOUT=1.
Pull-down to VSS: MODEn =
WIREDORPULLDOWN DOUT =
0.
RESETn pin. Pull-up to DVDD 35 44 55 kΩ
Maximum filtered glitch width TGF MODE = INPUT, DOUT = 1 — 26 — ns
RESETn low time to ensure TRESET 100 — — ns

pin reset

Note:
1. GPIO input thresholds are proportional to the IOVDD pin. RESETn input thresholds are proportional to DVDD.
2. GPIO pull-ups connect to IOVDD supply, pull-downs connect to VSS. RESETn pull-up connects to DVDD.

4.1.10 Analog to Digital Converter (ADC)
Unless otherwise indicated, typical conditions are: ADCCLK=10 MHz, OSR=2
Table 4.29. Analog to Digital Converter (ADC)
Main analog supply VAVDD Normal mode 1.71 — 3.8 V
Maximum Input Range1 VIN_MAX Maximum allowable input voltage 0 — AVDD V
Full-Scale Voltage VFS Voltage required for Full-Scale — VREF / Gain — V

measurement
Input Measurement Range VIN Differential Mode - Plus and Mi- -VFS — +VFS V
nus inputs
Single Ended Mode - One input 0 — VFS V

tied to ground
Input Sampling Capacitance Cs Analog Gain = 1x — 1.8 — pF
Analog Gain = 2x — 3.6 — pF
Analog Gain = 0.5x — 0.9 — pF
ADC clock frequency fADC_CLK Normal mode, Gain = 1x or 0.5x — — 10 MHz
Normal mode, Gain = 2x — — 5 MHz
Normal mode, Gain = 3x or 4x — — 2.5 MHz
Throughput rate fSAMPLE fADC_CLK = 10 MHz — — 1 Msps
Current from all supplies, IADC_CONTINU- 1 Msps, OSR=2, fADC_CLK = 10 — 290 385 µA
Continuous operation OUS MHz
Current in Standby mode. ISTBY Normal Mode — 16.3 — µA

ADC is not functional but can
wake up in 1us.
ADC Startup Time tstartup From power down state — 5 — µs
From standby state — 1 — µs
ADC Resolution Resolution — 12 — bits
Differential Nonlinearity DNL Differential Input. (No missing co- -1 +/- 0.25 +1.5 LSB12
des)
Integral Nonlinearity INL Differential Input. -2.5 +/- 0.65 -+2.5 LSB12
Effective number of bits ENOB Differential Input. Gain=1x, fIN = 10.5 11.18 — bits
10 kHz, Internal VREF=1.21V.
Signal to Noise + Distortion SNDR Differential Input. Gain=1x,fIN = 10 65 69.1 — dB

Ratio Normal Mode kHz, Internal VREF=1.21V
Differential Input. Gain=2x, fIN = — 68.8 — dB

10 kHz, Internal VREF=1.21V

Differential Input. Gain=0.5x, fIN = — 69.2 — dB


Total Harmonic Distortion THD Differential Input. Gain=1x, fIN =10 — -80.3 -70 dB
kHz, Internal VREF=1.21V
Spurious-Free Dynamic SFDR Differential Input. Gain=1x, fIN = 72 86.5 — dB

Range 10 kHz, Internal VREF=1.21V
Common Mode Rejection CMRR Normal mode. DC to 100 Hz — 87.0 — dB

Ratio
Normal mode. AC (measured at — 68.6 — dB
500 kHz)
Power Supply Rejection Ra- PSRR DC to 100 Hz — 80.4 — dB

tio
AC high frequency, using — 33.4 — dB
VREF_pad (measured at 500
kHz)
AC high frequency, using internal — 65.2 — dB

VBGR (measured at 500 kHz)
Gain Error, Normal mode GE GAIN = 1 and 0.5, using external -0.3 0.069 0.3 %
VREF, direct mode, fADC_CLK = 10
MHz
GAIN = 2, using external VREF, -0.4 0.151 0.4 %

direct mode, fADC_CLK = 5 MHz

direct mode, fADC_CLK = 2.5 MHz

Internal VREF, Gain=1 — 0.023 — %
Offset Error, Normal mode OFFSET GAIN = 1 and 0.5, Differential In- -3 0.27 3 LSB12
put
GAIN = 2, Differential Input -4 0.27 4 LSB12
External reference voltage VEVREF 1.0 — AVDD V

range1
Internal Reference voltage VIVREF — 1.21 — V
Note:
1. When inputs are routed to external GPIO pins, the maximum pin voltage is limited to the lower of the IOVDD and AVDD supplies.

Table 4.30. Analog Comparator (ACMP)
ACMP Supply current from IACMP BIAS = 4, HYST = DISABLED — 4.17 — µA

AVDD pin
BIAS = 5, HYST = DISABLED — 8.96 — µA
BIAS = 6, HYST = DISABLED — 23.1 — µA
BIAS = 7, HYST = DISABLED — 43.9 70 µA
ACMP Supply current from IACMP_WHYS BIAS = 4, HYST = SYM30MV — 5.98 — µA

AVDD pin with Hysteresis
BIAS = 5, HYST = SYM30MV — 13.0 — µA
Comparator delay with 100 TDELAY BIAS = 4 — 155 — ns

mV overdrive
BIAS = 5 — 86.6 — ns
BIAS = 6 — 50.6 — ns
BIAS = 7 — 39.9 — ns
Input offset voltage VOFFSET BIAS = 4, VCM = 0.15 to AVDD - -25 — +25 mV
0.15 V
BIAS = 7, VCM = 0.15 to AVDD - -30 — +30 mV

0.15 V
Input Range VIN Input Voltage Range 0 — AVDD V
Hysteresis (BIAS = 4) VHYST_4 HYST = SYM10MV1 — 21.2 — mV
HYST = SYM20MV1 — 39.9 — mV
Reference Voltage VACMPREF Internal 1.25 V Reference 1.19 1.25 1.31 V
Internal 2.5 V Reference 2.34 2.5 2.75 V
Capacitive Sense Oscillator RCSRESSEL CSRESSEL = 0 — 14 — kΩ

Resistance2
CSRESSEL = 1 — 24 — kΩ
Note:
1. VCM = 1.25 V
2. Capacitive Sense has been deprecated and is not recommended for use

4.1.12 Temperature Sensor
Table 4.31. Temperature Sensor
Temperature sensor range Tsense_range -40 — 125 °C
Temperature sensor resolu- TsenseRes — 0.25 — °C

tion

4.1.13 Brown Out Detectors
4.1.13.1 DVDD BOD
BOD thresholds on DVDD in EM0 and EM1 only, unless otherwise noted. Typical conditions are at TA = 25 °C. Minimum and maximum
values in this table represent the worst conditions across process variation, operating supply voltage range, and operating temperature
range.
Table 4.32. DVDD BOD
BOD threshold VDVDD_BOD Supply Rising — 1.67 1.71 V
Supply Falling 1.62 1.65 — V
BOD response time tDVDD_BOD_DE- Supply dropping at 100 mV/µs — 0.95 — µs

LAY slew rate1
BOD hysteresis VDVDD_BOD_HYS — 20 — mV

T
Note:
1. If the supply slew rate exceeds the specified slew rate, the BOD may trip later than expected (at a threshold below the minimum
specified threshold), or the BOD may not trip at all (e.g., if the supply ramps down and then back up at a very fast rate)
4.1.13.2 LE DVDD BOD
BOD thresholds on DVDD pin for low energy modes EM2 to EM4, unless otherwise noted.
Table 4.33. LE DVDD BOD
BOD threshold VDVDD_LE_BOD Supply Falling 1.5 — 1.71 V
BOD response time tDVDD_LE_BOD_D Supply dropping at 2 mV/µs slew — 50 — µs

ELAY rate1
BOD hysteresis VDVDD_LE_BOD_ — 20 — mV

HYST
Note:

4.1.13.3 AVDD and VIO BODs
BOD thresholds for AVDD BOD and BOD for VIO supply or supplies. All energy modes.
Table 4.34. AVDD and VIO BODs
BOD threshold VBOD Supply falling 1.45 — 1.71 V
BOD response time tBOD_DELAY Supply dropping at 2 mV/µs slew — 50 — µs

rate1
BOD hysteresis VBOD_HYST — 20 — mV
Note:

4.1.14 USART SPI Main Timing
CS tCS_MO
tSCLK_MO
SCLK
CLKPOL = 0
tSCLK
SCLK
CLKPOL = 1
MOSI
tSU_MI tH_MI
MISO
Figure 4.1. SPI Main Timing (SMSDELAY = 0)
CS tCS_MO
tSCLK_MO
SCLK
CLKPOL = 0
tSCLK
SCLK
CLKPOL = 1
MOSI
tSU_MI tH_MI
MISO

4.1.14.1 USART SPI Main Timing
Timing specifications are for all SPI signals routed to the same DBUS (DBUSAB or DBUSCD). All GPIO set to slew rate = 6.
Table 4.35. USART SPI Main Timing
SCLK period1 2 3 tSCLK 2*tPCLK — — ns
CS to MOSI1 2 tCS_MO -18.5 — 22.5 ns
SCLK to MOSI1 2 tSCLK_MO -13 — 11 ns
MISO setup time1 2 tSU_MI IOVDD = 1.62 V 44 — — ns
IOVDD = 3.0 V 34 — — ns
MISO hold time1 2 tH_MI -8.5 — — ns
Note:
1. Applies for both CLKPHA = 0 and CLKPHA = 1.
2. Measurement done with 8 pF output loading at 10% and 90% of the I/O supply.
3. tPCLK is one period of the selected PCLK.

4.1.15 USART SPI Secondary Timing
CS tCS_ACT_MI
tCS_DIS_MI
SCLK
CLKPOL = 0
tSCLK_HI tSCLK_LO
SCLK
CLKPOL = 1 tSU_MO
tSCLK
tH_MO
MOSI
tSCLK_MI
MISO
Figure 4.3. SPI Secondary Timing
4.1.15.1 USART SPI Secondary Timing
Table 4.36. USART SPI Secondary Timing
SCLK high time1 2 3 tSCLK_HI 2.5*tPCLK — — ns
SCLK low time1 2 3 tSCLK_LO 2.5*tPCLK — — ns
CS active to MISO1 2 tCS_ACT_MI 16 — 52.5 ns
CS disable to MISO1 2 tCS_DIS_MI 15 — 46 ns
MOSI setup time1 2 tSU_MO 3.5 — — ns
MOSI hold time1 2 3 tH_MO 4.5 — — ns
SCLK to MISO1 2 3 tSCLK_MI 13.5 + — 31 + ns

1.5*tPCLK 2.5*tPCLK
Note:
1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0).
2. Measurement done with 8 pF output loading at 10% and 90% of the I/O supply (figure shows 50%).

4.1.16 I2C Electrical Specifications
4.1.16.1 I2C Standard-mode (Sm)
CLHR set to 0 in the I2Cn_CTRL register.
Table 4.37. I2C Standard-mode (Sm)
SCL clock frequency1 fSCL 0 — 100 kHz
SCL clock low time tLOW 4.7 — — µs
SCL clock high time tHIGH 4 — — µs
SDA set-up time tSU_DAT 250 — — ns
SDA hold time tHD_DAT 0 — — ns
Repeated START condition tSU_STA 4.7 — — µs

set-up time
Repeated START condition tHD_STA 4.0 — — µs

hold time
STOP condition set-up time tSU_STO 4.0 — — µs
Bus free time between a tBUF 4.7 — — µs

STOP and START condition
Note:
1. The maximum SCL clock frequency listed is assuming that an arbitrary clock frequency is available. The maximum attainable
SCL clock frequency may be slightly less using the HFXO or HFRCO due to the limited frequencies available. The CLKDIV
should be set to a value that keeps the SCL clock frequency below the max value listed.

4.1.16.2 I2C Fast-mode (Fm)
Table 4.38. I2C Fast-mode (Fm)
SCL clock high time tHIGH 0.6 — — µs

set-up time

hold time

Note:

4.1.16.3 I2C Fast-mode Plus (Fm+)
Table 4.39. I2C Fast-mode Plus (Fm+)

set-up time

hold time

Note:
4.1.17 Boot Timing
Secure boot impacts the recovery time from all sources of device reset. In addition to the root code authentication process, which can-
not be disabled or bypassed, the root code can authenticate a bootloader, and the bootloader can authenticate the application. In
projects that include only an application and no bootloader, the root code can authenticate the application directly. The duration of each
authentication operation depends on two factors: the computation of the associated image hash, which is proportional to the size of the
image, and the verification of the image signature, which is independent of image size.
The duration for the root code to authenticate the bootloader will depend on the SE firmware version as well as on the size of the boot-
loader.
The duration for the bootloader to authenticate the application can depend on the size of the application.
The configurations below assume that the associated bootloader and application code images do not contain a bootloader certificate or
an application certificate. Authenticating a bootloader certificate or an application certificate will extend the boot time by an additional 6
to 7 ms.
The table below provides the durations from the termination of reset until the completion of the secure boot process (start of main()
function in the application image) under various conditions.
Conditions:
• SE firmware version 1.2.13
• Gecko Bootloader size 9.9 KB
Timing is expected to be similar for subsequent SE firmware versions. Refer to SE firmware release notes for any significant changes.

Table 4.40. Boot Timing
Boot time tBOOT Secure boot application check dis- — 29.2 — ms

abled, second stage bootloader
check enabled1, 50 kB application
size
Secure boot application check en- — 38.6 — ms

size

check enabled1, 150 kB applica-
tion size

tion size
Note:
1. Timing is measured with the specified bootloader size. Actual bootloader size will impact the boot timing slightly, with a similar
µs / kB ratio as application size.
4.1.18 Crypto Operation Timing for SE Manager API
Values in this table represent timing from SE Manager API call to return. The Cortex-M33 HCLK frequency is 38.4 MHz. The timing
specifications below are measured at the SE Manager function call API. Each duration in the table contains some portion that is influ-
enced by SE Manager build compilation and Cortex-M33 operating frequency and some portion that is influenced by the Hardware Se-
cure Engine's firmware version and its operating speed (typically 80 MHz). The contributions of the Cortex-M33 properties to the overall
specification timing are most pronounced for the shorter operations such as AES and hash when operating on small payloads. The
overhead of command processing at the mailbox interface can also dominate the timing for shorter operations.
Conditions:
• GSDK version 4.1.0

Table 4.41. Crypto Operation Timing for SE Manager API
AES-128 timing tAES128 AES-128 CCM encryption, PT 1 — 265 — µs

kB
AES-128 CCM encryption, PT 32 — 1450 — µs

kB
AES-128 CTR encryption, PT 1 — 231 — µs

kB

kB
AES-128 GCM encryption, PT 1 — 246 — µs

kB

kB

kB

kB

kB

kB

kB

kB
ECC P-256 timing tECC_P256 ECC key generation, P-256 — 5.5 — ms
ECC signing, P-256 — 5.7 — ms
ECC verification, P-256 — 6.1 — ms
ECC P-521 timing1 tECC_P521 ECC key generation, P-521 — 29.7 — ms
ECDH compute secret timing tECDH ECDH compute secret, P-5211 — 29.5 — ms
ECDH compute secret, P-255192 — 4.2 — ms

ECJPAKE client timing tECJPAKE_C ECJPAKE client write round one — 21.4 — ms
ECJPAKE client read round one — 14.3 — ms
ECJPAKE client write round two — 16.2 — ms
ECJPAKE client read round two — 7.6 — ms
ECJPAKE client derive secret — 10.5 — ms
ECJPAKE server timing tECJPAKE_S ECJPAKE server write round one — 21.4 — ms
ECJPAKE server read round one — 14.3 — ms
ECJPAKE server write round two — 16.3 — ms
ECJPAKE server read round two — 7.6 — ms
ECJPAKE server derive secret — 10.5 — ms
POLY-1305 timing1 tPOLY1305 POLY-1305, PT 1 kB — 212 — µs
POLY-1305, PT 32 kB — 1070 — µs
SHA-256 timing tSHA256 SHA-256, PT 1 kB — 251 — µs
SHA-256, PT 32 kB — 677 — µs
SHA-512 timing1 tSHA512 SHA-512, PT 1 kB — 251 — µs
SHA-512, PT 32 kB — 566 — µs
Note:
1. Option is only available on OPNs with Secure Vault High feature set.
2. Option is not available on Secure Vault Mid devices with SE firmware earlier than v1.2.10.
4.1.19 Crypto Operation Average Current for SE Manager API
Values in this table represent current consumed by security core during the operation, and represent additions to the current consumed
by the Cortex-M33 application CPU due to the Hardware Secure Engine CPU and its associated crypto accelerators. The current meas-
urements below represent the average value of the current for the duration of the crypto operation. Instantaneous peak currents may be
higher.
Conditions:
Current consumption is expected to be similar for subsequent SE firmware versions. Refer to SE firmware release notes for any signifi-
cant changes.

Table 4.42. Crypto Operation Average Current for SE Manager API
AES-128 current IAES128 AES-128 CCM encryption, PT 1 — 5.0 — mA

kB
AES-128 CCM encryption, PT 32 — 8.8 — mA

kB
AES-128 CTR encryption, PT 1 — 4.5 — mA

kB

kB
AES-128 GCM encryption, PT 1 — 4.7 — mA

kB

kB

kB

kB

kB

kB

kB

kB
ECC P-256 current IECCP256 ECC key generation, P-256 — 6.6 — mA
ECC signing, P-256 — 6.6 — mA
ECC verification, P-256 — 6.5 — mA
ECC P-521 current1 IECCP521 ECC key generation, P-521 — 6.7 — mA
ECDH compute secret cur- IECDH ECDH compute secret, P-5211 — 6.7 — mA
rent
ECDH compute secret, P-255192 — 6.4 — mA

ECJPAKE client current IECJPAKE_C ECJPAKE client write round one — 6.7 — mA
ECJPAKE client read round one — 6.6 — mA
ECJPAKE client write round two — 6.6 — mA
ECJPAKE client read round two — 6.5 — mA
ECJPAKE client derive secret — 6.6 — mA
ECJPAKE server current IECJPAKE_S ECJPAKE server write round one — 6.6 — mA
ECJPAKE server read round one — 6.6 — mA
ECJPAKE server write round two — 6.6 — mA
ECJPAKE server read round two — 6.5 — mA
ECJPAKE server derive secret — 6.5 — mA
POLY-1305 current1 IPOLY1305 POLY-1305, PT 1 kB — 4.4 — mA
POLY-1305, PT 32 kB — 6.4 — mA
SHA-256 current ISHA256 SHA-256, PT 1 kB — 3.4 — mA
SHA-256, PT 32 kB — 6.6 — mA
SHA-512 current1 ISHA512 SHA-512, PT 1 kB — 3.4 — mA
SHA-512, PT 32 kB — 6.1 — mA
Note:
4.2 Typical Performance Curves for Revision B
Typical performance curves indicate typical characterized performance under the stated conditions.

4.2.1 Supply Current
Figure 4.4. EM0 Active Mode Typical Supply Current vs. Temperature

Figure 4.5. EM2, EM3, and EM4 Sleep Mode Typical Supply Current vs. Temperature

4.2.2 2.4 GHz Radio
Figure 4.6. 2.4 GHz 20 dBm PA RF Transmitter Output Power

Figure 4.9. 2.4 GHz 802.15.4 RF Receiver Sensitivity

Figure 4.10. 2.4 GHz BLE RF Receiver Sensitivity
4.3 Electrical Characteristics for Revision D
All electrical parameters in all tables are specified under the following conditions, unless stated otherwise:
• Typical values are based on TA = 25 °C and all supplies at 3.0 V, by production test and/or technology characterization.
• Radio performance numbers are measured in conducted mode, based on Silicon Laboratories reference designs using output pow-
er-specific external RF impedance-matching networks for interfacing to a 50 Ω antenna.
• Minimum and maximum values represent the worst conditions across supply voltage, process variation, and operating temperature,
unless stated otherwise.
Power Supply Pin Dependencies
Due to on-chip circuitry (e.g., diodes), some EFR32 power supply pins have a dependent relationship with one or more other power
supply pins. These internal relationships between the external voltages applied to the various EFR32 supply pins are defined below.
Exceeding the below constraints can result in damage to the device and/or increased current draw.
• DVDD ≥ DECOUPLE
• PAVDD ≥ RFVDD
• AVDD, IOVDD: No dependency with each other or any other supply pin. Additional leakage may occur if DVDD remains unpowered
with power applied to these supplies.

4.3.1 Absolute Maximum Ratings
Stresses above those listed below may cause permanent damage to the device. This is a stress rating only and functional operation of
the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure
to maximum rating conditions for extended periods may affect device reliability.
Table 4.43. Absolute Maximum Ratings
Storage temperature range TSTG -50 — +150 °C
Junction temperature TJMAX -I grade — — +135 °C
Voltage on any supply pin VDDMAX -0.3 — 3.8 V
Voltage ramp rate on any VDDRAMPMAX — — 1.0 V / µs

supply pin
Voltage on HFXO pins VHFXOPIN -0.3 — 1.2 V
DC voltage on any GPIO pin VDIGPIN -0.3 — VIOVDD + V

0.3
DC voltage on RESETn pin1 VRESETn -0.3 — 3.8 V
Input RF level on pins PRFMAX2G4 — — +10 dBm

RF2G4_IO1 and
RF2G4_IO2
Absolute voltage on RF pins VMAX2G4 -0.3 — VPAVDD V

RF2G4_IOx
Total current into VDD power IVDDMAX Source — — 200 mA

lines
Total current into VSS IVSSMAX Sink — — 200 mA

ground lines
Current per I/O pin IIOMAX Sink — — 50 mA
Current for all I/O pins IIOALLMAX Sink — — 200 mA
Note:
1. The RESETn pin has a pull-up device to the DVDD supply. For minimum leakage, RESETn should not exceed the voltage at
DVDD.

4.3.2 General Operating Conditions
This table specifies the general operating temperature range and supply voltage range for all supplies. The minimum and maximum
values of all other tables are specifed over this operating range, unless otherwise noted.
Table 4.44. General Operating Conditions
Operating ambient tempera- TA -I temperature grade 1 -40 — +125 °C

ture range
DVDD supply voltage VDVDD EM0/1 1.71 3.0 3.8 V
EM2/3/42 1.71 3.0 3.8 V
AVDD supply voltage VAVDD 1.71 3.0 3.8 V
IOVDDx operating supply VIOVDDx 1.71 3.0 3.8 V

voltage (All IOVDD pins)
PAVDD operating supply VPAVDD 1.71 3.0 3.8 V

voltage
RFVDD operating supply VRFVDD 1.71 3.0 VPAVDD V

voltage
DECOUPLE output capaci- CDECOUPLE 0.75 1.0 2.75 µF

tor3
HCLK and Core frequency fHCLK MODE = WS1, RAMWSEN = 14 — — 80 MHz
PCLK frequency fPCLK — — 50 MHz
EM01 Group A clock fre- fEM01GRPACLK — — 80 MHz

quency
HCLK Radio frequency5 fHCLKRADIO 38 38.4 40 MHz
External Clock Input fCLKIN VSCALE2 or VSCALE1, IOVDD ≥ — — 40 MHz

2.7 V
DPLL Reference Clock fDPLLREFCLK VSCALE2 or VSCALE1 — — 40 MHz
Note:
1. The device may operate continuously at the maximum allowable ambient TA rating as long as the absolute maximum TJMAX is not
exceeded. For an application with significant power dissipation, the allowable TA may be lower than the maximum TA rating. TA =
TJMAX - (THETAJA x PowerDissipation). Refer to the Absolute Maximum Ratings table and the Thermal Characteristics table for
TJMAX and THETAJA.
2. The DVDD supply is monitored by the DVDD BOD in EM0/1 and the LE DVDD BOD in EM2/3/4.
3. The system designer should consult the characteristic specs of the capacitor used on DECOUPLE to ensure its capacitance val-
ue stays within the specified bounds across temperature and DC bias.
4. Flash wait states are set by the MODE field in the MSC_READCTRL register. RAM wait states are enabled by setting the RAMW-
SEN bit in the SYSYCFG_DMEM0RAMCTRL register.
5. The recommended radio crystal frequency is 38.4 MHz. Any crystal frequency other than 38.4 MHz is expressly not supported.
The minimum and maximum HCLKRADIO frequency in this table represent the design limits, which are much wider than the typi-
cal crystal tolerance.

4.3.3 Thermal Characteristics
Table 4.45. Thermal Characteristics
to Ambient QFN32 (4x4mm) TAJA_QFN32_4X4
to Case QFN32 (4x4mm) TAJC_QFN32_4X4
Note:
1. Measured according to JEDEC standard JESD51-2A. Integrated Circuit Thermal Test Method Environmental Conditions - Natural
Convection (Still Air).

4.3.4 Current Consumption
Unless otherwise indicated, typical conditions are: AVDD = DVDD = RFVDD = PAVDD = 1.8V. TA = 25 °C. Minimum and maximum
abled1





1 MHz HFRCO, CPU running — 360 — µA/MHz

Current consumption in EM1 IEM1 80 MHz HFRCO — 28.7 — µA/MHz

1 MHz HFRCO — 343 — µA/MHz
mode ning from LFXO

ning from LFRCO



mode

reset

Current Consumption per re- IRAM — 0.10 — µA

EM2
Note:

Unless otherwise indicated, typical conditions are: AVDD = DVDD = RFVDD = PAVDD = 3.0 V. TA = 25 °C. Minimum and maximum
abled1





1 MHz HFRCO, CPU running — 362 1018 µA/MHz

Current consumption in EM1 IEM1 80 MHz HFRCO — 28.7 37.6 µA/MHz

38 MHz HFRCO — 38.7 57.5 µA/MHz
1 MHz HFRCO — 345 994 µA/MHz
mode ning from LFXO

ning from LFRCO
1 bank (16 kB) RAM retention and — 4.5 10.5 µA

Current consumption in EM3 IEM3 Full RAM retention and RTC run- — 4.8 11.4 µA
1 bank (16 kB) RAM retention and — 4.3 — µA


mode

reset
Current consumption per re- IRAM — 0.10 — µA

EM2

Note:

GHz
802.15.4, f = 2.4 GHz — 9.2 — mA

f = 2.4 GHz, CW, 10 dBm PA, 0 — 16.6 — mA

dBm output power
f = 2.4 GHz, CW, 10 dBm PA, 10 — 34.9 — mA

dBm output power


GHz
802.15.4, f = 2.4 GHz — 9.2 — mA

f = 2.4 GHz, CW, 10 dBm PA, 0 — 16.7 — mA

dBm output power
f = 2.4 GHz, CW, 10 dBm PA, 10 — 35.4 — mA

dBm output power
f = 2.4 GHz, CW, 20 dBm PA, 10 — 60.8 — mA

V
f = 2.4 GHz, CW, 20 dBm PA, 20 — 186.5 — mA

V

4.3.5 2.4 GHz RF Transceiver Characteristics
4.3.5.1 RF Transmitter Characteristics
4.3.5.1.1 RF Transmitter General Characteristics for the 2.4 GHz Band
Table 4.50. RF Transmitter General Characteristics for the 2.4 GHz Band
RF test frequency range FRANGE 2400 — 2483.5 MHz
Maximum TX power 1 POUTMAX 20 dBm PA, PAVDD = 3.3 V — +20 — dBm
Maximum TX power POUTMAX10 10 dBm PA — +10 — dBm
Maximum TX power POUTMAX0 0 dBm PA — +0 — dBm
Minimum active TX power POUTMIN 20 dBm PA, PAVDD = 3.3 V — -14.1 — dBm
10 dBm PA — -13.3 — dBm
0 dBm PA — -24.9 — dBm
Output power step size POUTSTEP 0 dBm PA,-15 dBm < Output — 1.5 — dB
Power < -5 dBm
0 dBm PA,-5 dBm < Output Pow- — 0.3 — dB

er < 0 dBm
10 dBm PA, -5 dBm < Output — 1.5 — dB

power < 0 dBm
10 dBm PA, 0 dBm < Output pow- — 0.3 — dB

er < 10 dBm
20 dBm PA, 0 dBm < Output Pow- — 0.7 — dB

er < 5 dBm
20 dBm PA, 5 dBm < output pow- — 0.5 — dB

er < POUTMAX
Output power variation vs POUTVAR_V 20 dBm PA Pout = POUTMAX out- — 0.9 — dB

PAVDD supply voltage varia- put power with PAVDD voltage
tion, frequency = 2450 MHz swept from 3.0V to 3.8V.
10 dbm PA output power with — 0.1 — dB

to 3.0 V
0 dBm PA output power with — 0.1 — dB

to 3.0 V
Output power variation vs POUTVAR_T PAVDD = 3.3V supply, 20 dBm — 2.1 — dB

temperature, Frequency = PA at Pout = POUTMAX, (-40 to
2450 MHz +125 °C)
10 dBm PA at 10 dBm, (-40 to — 1.2 — dB

+125 °C)
0 dBm PA at 0 dBm, (-40 to +125 — 3 — dB

°C)

Output power variation vs RF POUTVAR_F 20 dBm PA, POUTMAX, PAVDD = — 0.2 — dB

frequency 3.3 V.
10 dBm PA, 10 dBm — 0.1 — dB
0 dBm PA, 0 dBm — 0.2 — dB
Spurious emissions of har- SPURHRM_FCC_ Continuous transmission of CW — -47 — dBm

monics in restricted bands R carrier. Pout = POUTMAX. PAVDD
per FCC Part 15.205/15.209 = 3.3V. Test Frequency = 2450
MHz.
Continuous transmission of CW — -47 — dBm

quency = 2450 MHz.
Spurious emissions of har- SPURHRM_FCC_ Continuous transmission of CW — -26 — dBc

monics in non-restricted NRR carrier, Pout = POUTMAX, PAVDD
bands per FCC Part = 3.3V, Test Frequency = 2450
15.247/15.35 MHz.
Continuous transmission of CW — -26 — dBc

carrier. Pout = 10 dBm. Test Fre-
quency = 2450 MHz.

Spurious emissions out-of- SPUROOB_FCC_ Restricted bands 30-88 MHz, — -47 — dBm
band (above 2.483 GHz or R Continuous transmission of CW
below 2.4 GHz) in restricted carrier, 20 dBm PA, Pout =
bands, per FCC part POUTMAX, PAVDD = 3.3V. Test
15.205/15.209 Frequency = 2450 MHz.

carrier, 20 dBm PA, Pout =

carrier, 20 dBm PA Pout =
Restricted bands >960 MHz, Con- — -47 — dBm

tinuous transmission of CW carri-
er, 20 dBm PA, Pout = POUTMAX,
PAVDD = 3.3V, Test Frequency =
2450 MHz.
Restricted bands 30-88 MHz, — -47 — dBm

quency = 2450 MHz

quency = 2450 MHz

quency = 2450 MHz
Restricted bands > 960 MHz, — -47 — dBm

quency = 2450 MHz
Spurious emissions per ETSI SPURETSI440 1G-14G, Pout = 10 dBm, Test Fre- — -36 — dBm
EN300.440 quency = 2450 MHz
47-74 MHz,87.5-108 MHz, — -56 — dBm

174-230 MHz, 470-862 MHz, Pout
= 10 dBm, Test Frequency = 2450
MHz
25-1000 MHz, excluding above — -42 — dBm

frequencies. Pout = 10 dBm, Test
Frequency = 2450 MHz
1G-12.75 GHz, excluding bands — -50 — dBm

listed above, Pout = 10 dBm, Test

Spurious emissions out-of- SPUROOB_FCC_ Frequencies above 2.483 GHz or — -26 — dBc
band in non-restricted bands NR below 2.4 GHz, continuous trans-
per FCC Part 15.247 mission CW carrier, 20 dBm PA,
Pout = POUTMAX, PAVDD = 3.3
V,Test Frequency = 2450 MHz
Frequencies above 2.483 GHz or — -26 — dBc

below 2.4 GHz, continuous trans-
mission CW carrier, Pout = 10
dBm, Test Frequency = 2450
MHz
Spurious emissions out-of- SPURETSI328 [2400-2BW to 2400-BW], — -26 — dBm

band, per ETSI 300.328 [2483.5+BW to 2483.5+2BW],
Pout = 10 dBm, Test Frequency =
2450 MHz
[2400-BW to 2400], [2483.5 to — -16 — dB

2483.5+BW] Pout = 10 dBm, Test
Note:
1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices cov-
ered in this data sheet can be found in the Max TX Power column of the Ordering Information Table.

4.3.5.1.2 RF Transmitter Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band
Table 4.51. RF Transmitter Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band
Error vector magnitude per EVM Average across frequency, signal — 3.1 — % rms
802.15.4-2011 is DSSS-OQPSK reference pack-
et, PAVDD = 3.3 V, Pout =
POUTMAX
Average across frequency, signal — 3 — % rms

et, Pout = 10 dBm

et, Pout = 0 dBm
Power spectral density limit PSDLIMIT Relative, at carrier ± 3.5 MHz, — -52.9 — dBc/
Relative, at carrier ± 3.5 MHz, — -53 — dBc/


Pout = 0 dBm 100kHz



Pout = 0 dBm 100kHz
Per FCC part 15.247, PAVDD = — -3.9 — dBm/

3.3 V, Pout = POUTMAX 3kHz

dBm 3kHz

dBm 3kHz
ETSI 300.328 Pout = 10 dBm — 8.2 — dBm
ETSI 300.328 Pout = 0 dbm — -1.7 — dBm
Occupied channel bandwidth OCPETSI328 99% BW at highest and lowest — 2.2 — MHz
per ETSI EN300.328 channels in band, Pout = 10 dBm
99% BW at highest and lowest — 2.2 — MHz

channels in band, Pout = 0 dBm

Pout = 10 dBm — 783.6 — kHz
Pout = 0 dBm — 785.3 — kHz
Power spectral density limit PSDLIMIT PAVDD = 3.3 V, Pout = POUTMAX, — -2.5 — dBm/

15.247 at 10 dBm 3kHz

Per ETSI 300.328 at 10 dBm/1 — 10 — dBm

MHz


2 MHz

MHz


MHz
Pout = 0 dBm Inband spurs at ± 3 — -53 — dBm

MHz
Note:

Pout = 10 dBm — 1414.6 — kHz
Pout = 0 dBm — 1415.4 — kHz
Power spectral density limit PSDLIMIT PAVDD = 3.3 V, Pout = POUTMAX, — -1.1 — dBm/

15.247 at 10 dBm 3kHz


MHz


4 MHz

MHz


MHz

MHz
Note:

Pout = 10 dBm — 721.7 — kHz
Pout = 0 dBm — 723.2 — kHz

15.247 at 10 dBm 3kHz

Per ETSI 300.328 at 10 dBm/1 — +10 — dBm

MHz

In-band spurious emissions, SPURINB Pout = 10 dBm, Inband spurs at ± — -38.2 — dBm
with allowed exceptions1 2 MHz

MHz


MHz

MHz
Note:

Pout = 10 dBm — 648.1 — kHz
Pout = 0 dBm — 648.3 — kHz
Pout = 10 dBm, Per FCC part — +3.6 — dBm/

15.247 at 10 dBm 3kHz

Per ETSI 300.328 at 10 dBm/1 — 9.9 — dBm

MHz


2 MHz

MHz


MHz

MHz
Note:

4.3.5.2 RF Receiver Characteristics
4.3.5.2.1 RF Receiver General Characteristics for the 2.4 GHz Band
Table 4.56. RF Receiver General Characteristics for the 2.4 GHz Band
RF tuning frequency range FRANGE 2400 — 2483.5 MHz
Receive mode maximum SPURRX 30 MHz to 1 GHz — -54.8 — dBm

spurious emission
1 GHz to 12 GHz — -57.1 — dBm
Max spurious emissions dur- SPURRX_FCC 216 MHz to 960 MHz, conducted — -54.8 — dBm
ing active receive mode, per measurement
FCC Part 15.109(a)
Above 960 MHz, conducted — -77.3 — dBm
measurement.

4.3.5.2.2 RF Receiver Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band
Table 4.57. RF Receiver Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band
Rx Max Strong Signal Input RXSAT Signal is reference signal1, packet — 10 — dBm
Level for 1% PER length is 20 octets
Sensitivity, 1% PER SENS Signal is reference signal, packet — -104.3 — dBm

length is 20 octets
Co-channel interferer rejec- CCR Desired signal 3 dB above sensi- — -0.5 — dB

tion, 1% PER tivity limit
Adjacent channel rejection, ACRREF1 Interferer is reference signal at +1 — 39.7 — dB

Interferer is reference signal, channel spacing
Alternate channel rejection, ACRREF2 Interferer is reference signal at +2 — 51 — dB

interferer is reference signal, channel spacing
Image rejection, 1% PER, IR Interferer is CW in image band3 — 47.8 — dB

desired is reference signal at
3 dB above reference sensi-
tivity level2
Blocking rejection of all other BLOCK Interferer frequency < desired fre- — 57.3 — dB
channels, 1% PER, desired quency -3 channel spacing
is reference signal at 3 dB
above reference sensitivity Interferer frequency > desired fre- — 57.2 — dB
level2, interferer is reference quency +3 channel spacing
signal
RSSI resolution RSSIRES -100 dBm to +5 dBm — 0.25 — dB
RSSI accuracy in the linear RSSILIN — +/-6 — dB

region as defined by
802.15.4-2020
Note:
1. Reference signal is defined as O-QPSK DSSS per 802.15.4, Frequency range = 2400-2483.5 MHz, Symbol rate = 62.5 ksym-
bols/s.
2. Reference sensitivity level is -85 dBm.
3. Due to low-IF frequency, there is some overlap of adjacent channel and image channel bands. Adjacent channel CW blocker
tests place the Interferer center frequency at the Desired frequency ± 5 MHz on the channel raster, whereas the image rejection
test places the CW interferer near the image frequency of the Desired signal carrier, regardless of the channel raster.

Rx Max Strong Signal Input RXSAT Signal is reference signal, packet — 10 — dBm
Level for 0.1% BER length is 37 bytes1

payload1
Signal to co-channel interfer- C/ICC (see notes)1 3 — +7 — dB

er


MHz offset1 4 3 5


MHz offset1 4 3 5


MHz offset1 4 3 5

sion1 5

MHz precision1 5

precision1 5
Intermodulation performance IM n=36 — -24.6 — dBm
Note:

Sensitivity SENS Signal is reference signal, 37 byte — -94 — dBm

payload1

er


MHz offset1 4 3 5

Interferer is reference signal at -4 — -49 — dB

MHz offset1 4 3 5


MHz offset1 4 3 5

sion1 5

MHz precision1 5
Interferer is reference signal at im- — +6.6 — dB

precision1 5
Intermodulation performance IM n = 36 — -17.1 — dBm
Note:

With non-ideal signals2 1 — -100 — dBm

er


MHz offset1 4 3 5


MHz offset1 4 3 5


MHz offset1 4 3 5

sion1 5

MHz precision1 5

precision1 5
Note:

Sensitivity SENS Signal is reference signal1 — -105 — dBm

er
N ± 1 Adjacent channel se- C/I1 Interferer is reference signal at +1 — -13 — dB


MHz offset1 4 3 5


MHz offset1 4 3 5


MHz offset1 4 3 5

sion1 5

MHz precision1 5
Interferer is reference signal at im- — -13 — dB

precision1 5
Note:

4.3.6 Flash Characteristics
Table 4.62. Flash Characteristics
Flash erase cycles before ECFLASH TA ≤ 125 °C 10,000 — — cycles

failure1
Flash data retention1 RETFLASH TA ≤ 125 °C 10 — — years
Program Time tPROG one word (32-bits) 25 31 35 µs
average per word over 128 words 8 9.5 11 µs
Page Erase Time2 tPERASE 16 17.5 20 ms
Mass Erase Time3 4 tMERASE 8 9 10.2 ms
Page Erase Current IERASE TA = 25 °C — — 2.13 mA
Program Current IWRITE TA = 25 °C — — 2.73 mA
Mass Erase Current IMERASE TA = 25 °C — — 2.30 mA
Flash Supply voltage during VFLASH 1.71 — 3.8 V

write or erase
Note:
1. Flash data retention information is published in the Quarterly Quality and Reliability Report.
2. Page Erase time is measured from setting the ERASEPAGE bit in the MSC_WRITECMD register until the BUSY bit in the MSC-
3. Mass Erase is issued by the CPU and erases all of User space.
4. Mass Erase time is measured from setting the ERASEMAIN0 bit in the MSC_WRITECMD register until the BUSY bit in the MSC-

4.3.7 Energy Mode Wake-up and Entry Times
Unless otherwise specified, these times are measured using the HFRCO at 19 MHz.
Table 4.63. Energy Mode Wake-up and Entry Times
Wake-up Time from EM1 tEM1_WU Code execution from flash — 3 — HCLKs

MHz

MHz

MHz

MHz
Wake-up Time from EM4 tEM4_WU Code execution from Flash — 15.1 — ms

4.3.8 Oscillators
4.3.8.1 High Frequency Crystal Oscillator
Unless otherwise indicated, typical conditions are: AVDD = DVDD = RFVDD = 3.0 V. TA = 25 °C. Minimum and maximum values in this
table represent the worst conditions across process variation, operating supply voltage range, and operating temperature range.
Table 4.64. High Frequency Crystal Oscillator
Crystal Frequency FHFXO see note1 2 — 38.4 — MHz
Supported crystal equivalent ESRHFXO_38M4 38.4 MHz, CL = 10 pF3 — — 40 Ω

Supported range of crystal CHFXO_LC 38.4 MHz, ESR = 404 — 10 — pF

load capacitance
Supply Current IHFXO — 500 — µA
Startup Time5 TSTARTUP 38.4 MHz, ESR = 40 Ω, CL = 10 — 160 — µs

pF
On-chip tuning cap step SSHFXO — 0.04 — pF

size6
Note:
1. The BLE radio requires a 38.4 MHz crystal with a tolerance of ± 50 ppm over temperature and aging. Please use a crystal with
2. The ZigBee radio requires a 38.4 MHz crystal with a tolerance of ± 40 ppm over temperature and aging. Please use a crystal with
3. The crystal should have a maximum ESR less than or equal to this maximum rating.
4. It is recommended to use a crystal with a 10 pF load capacitance rating. Only crystals with a 10 pF load cap rating have been
characterized for RF use.
5. Startup time does not include time implemented by programmable TIMEOUTSTEADY delay.
6. The tuning step size is the effective step size when incrementing both of the tuning capacitors by one count. The step size for the
each of the individual tuning capacitors is twice this value.

4.3.8.2 Low Frequency Crystal Oscillator
Table 4.65. Low Frequency Crystal Oscillator
Crystal Frequency FLFXO — 32.768 — kHz
Supported Crystal equivalent ESRLFXO GAIN = 0 — — 80 kΩ

GAIN = 1 to 3 — — 100 kΩ
Supported range of crystal CL_LFXO GAIN = 0 4 — 6 pF

load capacitance 1
GAIN = 1 6 — 10 pF
GAIN = 2 (see note2) 10 — 12.5 pF
GAIN = 3 (see note2) 12.5 — 18 pF
Current consumption ICL12p5 ESR = 70 kΩ, CL = 12.5 pF, — 220 — nA

GAIN3 = 2, AGC4 = 1
Startup Time TSTARTUP ESR = 70 kΩ, CL = 7 pF, GAIN3 = — 259 — ms

1, AGC4 = 1
On-chip tuning cap step size SSLFXO — 0.26 — pF
On-chip tuning capacitor val- CLFXO_MIN CAPTUNE = 0 — 4 — pF

ue at minimum setting5
On-chip tuning capacitor val- CLFXO_MAX CAPTUNE = 0x4F — 24.5 — pF

ue at maximum setting5
Note:
1. Total load capacitance seen by the crystal
2. Crystals with a load capacitance of greater than 12 pF require external load capacitors.
3. In LFXO_CAL Register
4. In LFXO_CFG Register
5. The effective load capacitance seen by the crystal will be CLFXO/2. This is because each XTAL pin has a tuning cap and the two
caps will be seen in series by the crystal

4.3.8.3 High Frequency RC Oscillator (HFRCO)
Unless otherwise indicated, typical conditions are: AVDD = DVDD = 3.0 V. TA = 25 °C. Minimum and maximum values in this table
represent the worst conditions across process variation, operating supply voltage range, and operating temperature range.
Table 4.66. High Frequency RC Oscillator (HFRCO)
Frequency Accuracy FHFRCO_ACC For all production calibrated fre- -3 — 3 %

quencies
Current consumption on all IHFRCO FHFRCO = 1 MHz — 27 — µA

supplies1
Clock Out current for ICLKOUT_HFRCOD FORCEEN bit of HFRCO0_CTRL — 5.0 — µA/MHz
HFRCODPLL4 PLL =1
Clock Out current for ICLKOUT_HFRCOE FORCEEN bit of — 1.25 — µA/MHz

HFRCOEM234 M23 HFRCOEM23_CTRL = 1
Coarse trim step Size (% of SSHFRCO_COARS Step size measured at coarse trim — 0.64 — %
period) E mid-scale. (Fine trim also set to
mid scale.)
Fine trim step Size (% of pe- SSHFRCO_FINE Step size measured at fine trim — 0.1 — %
riod) mid-scale. (Coarse trim also set to
mid scale.)
Period jitter PJHFRCO 19 MHz — 0.04 — % RMS
Startup Time5 TSTARTUP FREQRANGE = 0 to 7 — 3.2 — µs
FREQRANGE = 8 to 15 — 1.2 — µs

Band Frequency Limits6 fHFRCO_BAND FREQRANGE = 0 3.71 — 5.24 MHz
FREQRANGE = 6 11.5 — 17 MHz
FREQRANGE = 12 33 — 51 MHz
Note:
1. Does not include additional clock tree current. See specifications for additional current when selected as a clock source for a par-
ticular clock multiplexer.
2. This frequency is calibrated for the HFRCODPLL (HFRCO0) only.
3. This frequency is calibrated for the HFRCOEM23 only.
4. When the HFRCO is enabled for characterization using the FORCEEN bit, the total current will be the HFRCO core current plus
the specified CLKOUT current. When the HFRCO is enabled on demand, the clock current may be different.
5. Hardware delay ensures settling to within ± 0.5%. Hardware also enforces this delay on a band change.
6. The frequency band limits represent the lowest and highest frequency which each band can achieve over the operating range.
4.3.8.4 Fast Start_Up RC Oscillator (FSRCO)
Table 4.67. Fast Start_Up RC Oscillator (FSRCO)
FSRCO frequency FFSRCO 17.2 20 21.2 MHz

4.3.8.5 Low Frequency RC Oscillator
Table 4.68. Low Frequency RC Oscillator
Nominal oscillation frequen- FLFRCO 31.785 32.768 33.751 kHz

cy
Startup time TSTARTUP — 128 — µs
Current consumption ILFRCO — 177 — nA
4.3.8.6 Ultra Low Frequency RC Oscillator
Table 4.69. Ultra Low Frequency RC Oscillator
Oscillation Frequency FULFRCO 0.944 1.0 1.095 kHz

4.3.9 GPIO Pins (3V GPIO pins)
Unless otherwise indicated, typical conditions are: AVDD = DVDD = IOVDD = 3.0 V.
Table 4.70. GPIO Pins (3V GPIO pins)
Leakage current ILEAK_IO MODEx = DISABLED, IOVDD = — 1.9 — nA

1.71V
MODEx = DISABLED, IOVDD = — 2.5 — nA

3.0 V
PC03, PC04 and PD00 pins. — — 340 nA

MODEx = DISABLED, IOVDD =
3.8 V TA = 125 °C
All other GPIO pins. MODEx = — — 250 nA

DISABLED, IOVDD = 3.8 V TA =
125 °C
Input low voltage1 VIL Any GPIO pin — — 0.3 * V

IOVDD
RESETn — — 0.3 * DVDD V
Input high voltage1 VIH Any GPIO pin 0.7 * — — V

IOVDD
RESETn 0.7 * DVDD — — V
Hysteresis of input voltage VHYS Any GPIO pin 0.05 * — — V

IOVDD
RESETn 0.05 * — — V
DVDD
Output low voltage VOL Sinking 20mA, IOVDD = 3.0 V — — 0.2 * V

IOVDD
Sinking 8mA, IOVDD = 1.71 V — — 0.4 * V

IOVDD
Output high voltage VOH Sourcing 20mA, IOVDD = 3.0 V 0.8 * — — V

IOVDD
Sourcing 8mA, IOVDD = 1.71 V 0.6 * — — V

IOVDD
GPIO rise time TGPIO_RISE IOVDD = 3.0V, Cload = 50 pF, — 6.5 — ns

IOVDD = 1.7V, Cload = 50 pF, — 9.4 — ns

GPIO fall time TGPIO_FALL IOVDD = 3.0V, Cload = 50 pF, — 5.7 — ns

IOVDD = 1.7V, Cload = 50 pF, — 9.2 — ns

Pull up/down resistance2 RPULL Any GPIO pin. Pull-up to IOVDD: 33 44 55 kΩ

MODEn = DISABLE DOUT=1.
Pull-down to VSS: MODEn =
WIREDORPULLDOWN DOUT =
0.
RESETn pin. Pull-up to DVDD 33 44 55 kΩ

Maximum filtered glitch width TGF MODE = INPUT, DOUT = 1 — 26 — ns
RESETn low time to ensure TRESET 100 — — ns

pin reset
Note:
1. GPIO input thresholds are proportional to the IOVDD pin. RESETn input thresholds are proportional to DVDD.
2. GPIO pull-ups connect to IOVDD supply, pull-downs connect to VSS. RESETn pull-up connects to DVDD.

4.3.10 Analog to Digital Converter (ADC)
Unless otherwise indicated, typical conditions are: ADCCLK=10 MHz, OSR=2
Table 4.71. Analog to Digital Converter (ADC)
Main analog supply VAVDD Normal mode 1.71 — 3.8 V
Maximum Input Range1 VIN_MAX Maximum allowable input voltage 0 — AVDD V
Full-Scale Voltage VFS Voltage required for Full-Scale — VREF / Gain — V

measurement
Input Measurement Range VIN Differential Mode - Plus and Mi- -VFS — +VFS V
nus inputs
Single Ended Mode - One input 0 — VFS V

tied to ground
Input Sampling Capacitance Cs Analog Gain = 1x — 1.8 — pF
Analog Gain = 0.5x — 0.9 — pF
ADC clock frequency fADC_CLK Gain = 1x or 0.5x — — 10 MHz
Gain = 2x — — 5 MHz
Gain = 3x or 4x — — 2.5 MHz
Input sampling frequency fS — fADC_CLK/4 — MHz
Throughput rate fSAMPLE fADC_CLK = 10 MHz — — 1 Msps
Current from all supplies, IADC_CONTINU- 1 Msps, OSR=2, fADC_CLK = 10 — 310 400 µA
Continuous operation OUS MHz
Current in Standby mode. ISTBY — 16 — µA

ADC is not functional but can
wake up in 1us.
ADC Startup Time tstartup From power down state — 5 — µs
From standby state — 1 — µs
ADC Resolution Resolution — 12 — bits
Differential Nonlinearity DNL Differential Input. (No missing co- -1 +/- 0.25 1.5 LSB12
des)
Integral Nonlinearity INL Differential Input. -2.5 +/- 0.65 2.5 LSB12
Effective number of bits ENOB Differential Input. Gain=1x, fIN = 10.5 11.18 — bits
10 kHz, Internal VREF=1.21V.

Signal to Noise + Distortion SNDR Differential Input. Gain=1x,fIN = 10 65 69.1 — dB

Ratio Normal Mode kHz, Internal VREF=1.21V


Differential Input. Gain=0.5x, fIN = — 69.2 — dB

Total Harmonic Distortion THD Differential Input. Gain=1x, fIN =10 — -80.3 --70 dB
kHz, Internal VREF=1.21V
Spurious-Free Dynamic SFDR Differential Input. Gain=1x, fIN = 72 86.5 — dB

Range 10 kHz, Internal VREF=1.21V
Common Mode Rejection CMRR DC to 100 Hz — 87.0 — dB

Ratio
AC (measured at 500 kHz) — 68.6 — dB
Power Supply Rejection Ra- PSRR DC to 100 Hz — 80.4 — dB

tio
AC high frequency, using — 33.4 — dB
VREF_pad (measured at 500
kHz)
AC high frequency, using internal — 65.2 — dB

VBGR (measured at 500 kHz)
Gain Error, Normal mode GE GAIN = 1 and 0.5, using external -0.3 0.069 0.3 %
VREF, direct mode, fADC_CLK = 10
MHz

direct mode, fADC_CLK = 5 MHz


Internal VREF, Gain=1 — 0.023 — %
Offset Error, Normal mode OFFSET GAIN = 1 and 0.5, Differential In- -3 0.27 3 LSB12
put
External reference voltage VEVREF 1.0 — AVDD V

range1
Internal Reference voltage VIVREF — 1.18 — V
Note:
1. When inputs are routed to external GPIO pins, the maximum pin voltage is limited to the lower of the IOVDD and AVDD supplies.

Table 4.72. Analog Comparator (ACMP)
ACMP Supply current IACMP BIAS = 4, HYST = DISABLED — 5.5 — µA
BIAS = 5, HYST = DISABLED — 11 — µA
BIAS = 6, HYST = DISABLED — 27 — µA
BIAS = 7, HYST = DISABLED — 51 77 µA
ACMP Supply current with IACMP_WHYS BIAS = 4, HYST = SYM30MV — 7.5 — µA

Hysteresis
BIAS = 5, HYST = SYM30MV — 16 — µA
Comparator delay with 100 TDELAY BIAS = 4 — 222 — ns

mV overdrive
BIAS = 5 — 123 — ns
BIAS = 6 — 71 — ns
BIAS = 7 — 55 — ns
Input offset voltage VOFFSET BIAS = 4, VCM = 0.15 to AVDD - -25 — 25 mV

0.15 V
BIAS = 7, VCM = 0.15 to AVDD - -30 — 30 mV

0.15 V
Input Range VIN Input Voltage Range 0 — AVDD V
Hysteresis (BIAS = 4) VHYST_4 HYST = SYM10MV1 — 16.8 — mV
Reference Voltage VACMPREF Internal 1.25 V Reference 1.19 1.25 1.31 V
Internal 2.5 V Reference 2.34 2.5 2.75 V
Capacitive Sense Oscillator RCSRESSEL CSRESSEL = 0 — 15 — kΩ

Resistance2
Note:
1. VCM = 1.25 V
2. Capacitive Sense has been deprecated and is not recommended for use

4.3.12 Temperature Sensor
Table 4.73. Temperature Sensor
Temperature sensor range Tsense_range -40 — 125 °C
Temperature sensor resolu- TsenseRes — 0.25 — °C

tion

4.3.13 Brown Out Detectors
4.3.13.1 DVDD BOD
BOD thresholds on DVDD in EM0 and EM1 only, unless otherwise noted. Typical conditions are at TA = 25 °C. Minimum and maximum
values in this table represent the worst conditions across process variation, operating supply voltage range, and operating temperature
range.
Table 4.74. DVDD BOD
BOD threshold VDVDD_BOD Supply Rising — 1.67 1.71 V
Supply Falling 1.62 1.65 — V
BOD response time tDVDD_BOD_DE- Supply dropping at 100 mV/µs — 0.95 — µs

LAY slew rate1
BOD hysteresis VDVDD_BOD_HYS — 20 — mV

T
Note:
4.3.13.2 LE DVDD BOD
BOD thresholds on DVDD pin for low energy modes EM2 to EM4, unless otherwise noted.
Table 4.75. LE DVDD BOD
BOD threshold VDVDD_LE_BOD Supply Falling 1.5 — 1.71 V
BOD response time tDVDD_LE_BOD_D Supply dropping at 2 mV/µs slew — 50 — µs

ELAY rate1
BOD hysteresis VDVDD_LE_BOD_ — 20 — mV

HYST
Note:

4.3.13.3 AVDD and VIO BODs
BOD thresholds for AVDD BOD and BOD for VIO supply or supplies. All energy modes.
Table 4.76. AVDD and VIO BODs
BOD threshold VBOD Supply falling 1.45 — 1.71 V
BOD response time tBOD_DELAY Supply dropping at 2 mV/µs slew — 50 — µs

rate1
BOD hysteresis VBOD_HYST — 20 — mV
Note:

4.3.14 USART SPI Main Timing
CS tCS_MO
tSCLK_MO
SCLK
CLKPOL = 0
tSCLK
SCLK
CLKPOL = 1
MOSI
tSU_MI tH_MI
MISO
CS tCS_MO
tSCLK_MO
SCLK
CLKPOL = 0
tSCLK
SCLK
CLKPOL = 1
MOSI
tSU_MI tH_MI
MISO

4.3.14.1 USART SPI Main Timing
Table 4.77. USART SPI Main Timing
CS to MOSI1 2 tCS_MO -24 — 24.5 ns
SCLK to MOSI1 2 tSCLK_MO -17.5 — 16 ns
MISO setup time1 2 tSU_MI IOVDD = 1.62 V 50 — — ns
IOVDD = 3.0 V 35 — — ns
MISO hold time1 2 tH_MI -9 — — ns
Note:
1. Applies for both CLKPHA = 0 and CLKPHA = 1.
2. Measurement done with 8 pF output loading at 10% and 90% of the I/O supply.

4.3.15 USART SPI Secondary Timing
CS tCS_ACT_MI
tCS_DIS_MI
SCLK
CLKPOL = 0
tSCLK_HI tSCLK_LO
SCLK
CLKPOL = 1 tSU_MO
tSCLK
tH_MO
MOSI
tSCLK_MI
MISO
Figure 4.13. SPI Secondary Timing
4.3.15.1 USART SPI Secondary Timing
Table 4.78. USART SPI Secondary Timing
SCLK high time1 2 3 tSCLK_HI 2.5*tPCLK — — ns
SCLK low time1 2 3 tSCLK_LO 2.5*tPCLK — — ns
CS active to MISO1 2 tCS_ACT_MI 20 — 65 ns
CS disable to MISO1 2 tCS_DIS_MI 19.5 — 57 ns
MOSI setup time1 2 tSU_MO 3 — — ns
MOSI hold time1 2 3 tH_MO 2 — — ns
SCLK to MISO1 2 3 tSCLK_MI 16.5 + — 38 + ns

1.5*tPCLK 2.5*tPCLK
Note:
1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0).
2. Measurement done with 8 pF output loading at 10% and 90% of the I/O supply (figure shows 50%).

4.3.16 I2C Electrical Specifications
4.3.16.1 I2C Standard-mode (Sm)
Table 4.79. I2C Standard-mode (Sm)
SCL clock high time tHIGH 4 — — µs

set-up time

hold time

Note:

4.3.16.2 I2C Fast-mode (Fm)
Table 4.80. I2C Fast-mode (Fm)

set-up time

hold time

Note:

4.3.16.3 I2C Fast-mode Plus (Fm+)
Table 4.81. I2C Fast-mode Plus (Fm+)

set-up time

hold time

Note:
4.3.17 Boot Timing
Secure boot impacts the recovery time from all sources of device reset. In addition to the root code authentication process, which can-
not be disabled or bypassed, the root code can authenticate a bootloader, and the bootloader can authenticate the application. In
projects that include only an application and no bootloader, the root code can authenticate the application directly. The duration of each
authentication operation depends on two factors: the computation of the associated image hash, which is proportional to the size of the
image, and the verification of the image signature, which is independent of image size.
The duration for the root code to authenticate the bootloader will depend on the SE firmware version as well as on the size of the boot-
loader.
The duration for the bootloader to authenticate the application can depend on the size of the application.
The configurations below assume that the associated bootloader and application code images do not contain a bootloader certificate or
an application certificate. Authenticating a bootloader certificate or an application certificate will extend the boot time by an additional 6
to 7 ms.
The table below provides the durations from the termination of reset until the completion of the secure boot process (start of main()
function in the application image) under various conditions.
Conditions:
• Gecko Bootloader size 9.9 KB

Table 4.82. Boot Timing
Boot time tBOOT Secure boot application check dis- — 29.7 — ms

size

size

tion size

tion size
Note:
1. Timing is measured with the specified bootloader size. Actual bootloader size will impact the boot timing slightly, with a similar
µs / kB ratio as application size.
4.3.18 Crypto Operation Timing for SE Manager API
Values in this table represent timing from SE Manager API call to return. The Cortex-M33 HCLK frequency is 38.4 MHz. The timing
specifications below are measured at the SE Manager function call API. Each duration in the table contains some portion that is influ-
enced by SE Manager build compilation and Cortex-M33 operating frequency and some portion that is influenced by the Hardware Se-
cure Engine's firmware version and its operating speed (typically 80 MHz). The contributions of the Cortex-M33 properties to the overall
specification timing are most pronounced for the shorter operations such as AES and hash when operating on small payloads. The
overhead of command processing at the mailbox interface can also dominate the timing for shorter operations.
Conditions:

Table 4.83. Crypto Operation Timing for SE Manager API

kB

kB

kB

kB

kB

kB

kB

kB

kB

kB

kB

kB
ECC P-256 timing tECC_P256 ECC key generation, P-256 — 5.5 — ms
ECDH compute secret timing tECDH ECDH compute secret, P-5211 — 29.6 — ms

ECJPAKE client timing tECJPAKE_C ECJPAKE client write round one — 21.5 — ms
ECJPAKE client read round one — 14.3 — ms
ECJPAKE client write round two — 16.2 — ms
ECJPAKE client read round two — 7.6 — ms
ECJPAKE client derive secret — 10.5 — ms
ECJPAKE server timing tECJPAKE_S ECJPAKE server write round one — 21.4 — ms
ECJPAKE server read round one — 14.3 — ms
ECJPAKE server write round two — 16.2 — ms
ECJPAKE server read round two — 7.6 — ms
ECJPAKE server derive secret — 10.6 — ms
POLY-1305 timing1 tPOLY1305 POLY-1305, PT 1 kB — 214 — µs
POLY-1305, PT 32 kB — 1071 — µs
SHA-256 timing tSHA256 SHA-256, PT 1 kB — 109 — µs
SHA-256, PT 32 kB — 533 — µs
SHA-512 timing1 tSHA512 SHA-512, PT 1 kB — 107 — µs
SHA-512, PT 32 kB — 424 — µs
Note:
4.3.19 Crypto Operation Average Current for SE Manager API
Values in this table represent current consumed by security core during the operation, and represent additions to the current consumed
by the Cortex-M33 application CPU due to the Hardware Secure Engine CPU and its associated crypto accelerators. The current meas-
urements below represent the average value of the current for the duration of the crypto operation. Instantaneous peak currents may be
higher.
Conditions:
Current consumption is expected to be similar for subsequent SE firmware versions. Refer to SE firmware release notes for any signifi-
cant changes.

Table 4.84. Crypto Operation Average Current for SE Manager API

kB

kB

kB

kB

kB

kB

kB

kB

kB

kB

kB

kB
ECC P-256 current IECCP256 ECC key generation, P-256 — 5.8 — mA
ECDH compute secret cur- IECDH ECDH compute secret, P-5211 — 5.9 — mA
rent

ECJPAKE client current IECJPAKE_C ECJPAKE client write round one — 5.8 — mA
ECJPAKE client read round one — 5.8 — mA
ECJPAKE client write round two — 5.8 — mA
ECJPAKE client read round two — 5.7 — mA
ECJPAKE client derive secret — 5.8 — mA
ECJPAKE server current IECJPAKE_S ECJPAKE server write round one — 5.8 — mA
ECJPAKE server read round one — 5.8 — mA
ECJPAKE server write round two — 5.8 — mA
ECJPAKE server read round two — 5.7 — mA
ECJPAKE server derive secret — 5.8 — mA
POLY-1305 current1 IPOLY1305 POLY-1305, PT 1 kB — 4.1 — mA
POLY-1305, PT 32 kB — 5.5 — mA
SHA-256 current ISHA256 SHA-256, PT 1 kB — 3.4 — mA
SHA-256, PT 32 kB — 6.5 — mA
SHA-512 current1 ISHA512 SHA-512, PT 1 kB — 3.3 — mA
SHA-512, PT 32 kB — 6.2 — mA
Note:
4.4 Typical Performance Curves for Revision D
Typical performance curves indicate typical characterized performance under the stated conditions.

4.4.1 Supply Current
Figure 4.14. EM0 Active Mode Typical Supply Current vs. Temperature

Figure 4.15. EM2, EM3, and EM4 Sleep Mode Typical Supply Current vs. Temperature

4.4.2 2.4 GHz Radio

Figure 4.19. 2.4 GHz 802.15.4 RF Receiver Sensitivity

Figure 4.20. 2.4 GHz BLE RF Receiver Sensitivity

Typical Connection Diagrams
5. Typical Connection Diagrams
5.1 Power
Typical power supply connections are shown in the following figure.
VDD
Main +
Supply –
AVDD IOVDD
HFXTAL_I
HFXTAL_O
DVDD LFXTAL_I
LFXTAL_O
DECOUPLE
RFVDD PAVDD
Figure 5.1. EFR32MG21 Typical Application Circuit: Direct Supply Configuration
5.2 RF Matching Networks
RF Matching Network connections are described in the following sub-sections. For more information on matching networks and recom-
mendations, see AN930.2: EFR32 Series 2 2.4 GHz Matching Guide and AN928.2: EFR32 Series 2 Layout Design Guide.

5.2.1 2.4 GHz 0 dBm Matching Network
The recommended RF matching network circuit diagram for 2.4GHz applications with a transmit power of 0 dBm or less is shown in
Figure 5.2 Typical 0 dBm 2.4 GHz RF impedance-matching network circuit on page 127. Typical component values are shown in Table
5.1 2.4GHz 0 dBm Component Values on page 127. Please refer to the development board Bill of Materials for specific part recom-
mendation including tolerance, component size, recommended manufacturer, and recommended part number.
L1 C3
RF2G4_IO2 50Ω
C1 C2
RF2G4_IO1
C4
Figure 5.2. Typical 0 dBm 2.4 GHz RF impedance-matching network circuit
Table 5.1. 2.4GHz 0 dBm Component Values
Designator Value
C1 1.7 pF
C2 0.9 pF
L1 2.0 nH
C3 2.7 pF
C4 0.5 pF

The recommended RF matching network circuit diagram for 2.4GHz applications with a transmit power of greater than 0 dBm and up to
10 dBm is shown in Figure 5.3 Typical 10 dBm 2.4 GHz RF impedance-matching network circuit on page 128. Typical component val-
ues are shown in Table 5.2 2.4GHz 10 dBm Component Values on page 128. Please refer to the development board Bill of Materials
for specific part recommendation including tolerance, component size, recommended manufacturer, and recommended part number.
L1
RF2G4_IO2 50Ω
C1 C2
RF2G4_IO1
Table 5.2. 2.4GHz 10 dBm Component Values
Designator Value
C1 1.9 pF
L1 2.1 nH
C2 0.9 pF
The recommended RF matching network circuit diagram for 2.4 GHz applications is shown in Figure 5.4 Typical 20 dBm 2.4 GHz RF
impedance-matching network circuit on page 128. Typical component values are shown in Table 5.3 2.4 GHz 20 dBm Component Val-
ues on page 128. Please refer to the development board Bill of Materials for specific part recommendation including tolerance, compo-
nent size, recommended manufacturer, and recommended part number.
L1 L2
RF2G4_IO2 50Ω
C1 C2 C3
RF2G4_IO1
Table 5.3. 2.4 GHz 20 dBm Component Values
Designator Value
C1 2.3 pF
L1 2.3 nH
C2 0.8 pF
L2 1.1 nH
C3 0.3 pF

5.3 Other Connections
Other components or connections may be required to meet the system-level requirements. Application note, AN0002.2: EFM32 and
EFR32 Wireless Gecko Series 2 Hardware Design Considerations, contains detailed information on these connections. Application
notes can be accessed on the Silicon Labs website (www.silabs.com/32bit-appnotes).

Pin Definitions
6. Pin Definitions
6.1 QFN32 Device Pinout
Figure 6.1. QFN32 Device Pinout
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the sup-
ported features for each GPIO pin, see 6.2 Alternate Function Table, 6.3 Analog Peripheral Connectivity, and 6.4 Digital Peripheral
Connectivity.
Table 6.1. QFN32 Device Pinout
Pin Name Pin(s) Description Pin Name Pin(s) Description
PC00 1 GPIO PC01 2 GPIO
HFXTAL_I 7 High Frequency Crystal Input HFXTAL_O 8 High Frequency Crystal Output
RESETn 9 Reset Pin RFVDD 10 Radio power supply

Pin Definitions
Pin Name Pin(s) Description Pin Name Pin(s) Description
RFVSS 11 Radio Ground RF2G4_IO2 12 2.4 GHz RF input/output
RF2G4_IO1 13 2.4 GHz RF input/output PAVDD 14 Power Amplifier (PA) power supply
PB01 15 GPIO PB00 16 GPIO
PA00 17 GPIO PA01 18 GPIO
Decouple output for on-chip voltage

PA06 23 GPIO DECOUPLE 24 regulator. An external decoupling ca-
pacitor is required at this pin.
DVDD 25 Digital power supply AVDD 26 Analog power supply
IOVDD 27 Digital IO power supply. PD04 28 GPIO
PD03 29 GPIO PD02 30 GPIO
PD01 31 GPIO PD00 32 GPIO
6.2 Alternate Function Table
A wide selection of alternate functionality is available for multiplexing to various pins. The following table shows GPIO pins with support
for dedicated functions.
Table 6.2. GPIO Alternate Function Table
GPIO Alternate Functions
PA00 IADC0.VREFP
PA01 GPIO.SWCLK
PA02 GPIO.SWDIO
GPIO.SWV
PA03 GPIO.TDO
GPIO.TRACEDATA0
GPIO.TDI
PA04
GPIO.TRACECLK
PA05 GPIO.EM4WU0
PB01 GPIO.EM4WU3
PC00 GPIO.EM4WU6
PC05 GPIO.EM4WU7
PD00 LFXO.LFXTAL_O
LFXO.LFXTAL_I
PD01
LFXO.LF_EXTCLK
PD02 GPIO.EM4WU9

Pin Definitions
6.3 Analog Peripheral Connectivity
Many analog resources are routable and can be connected to numerous GPIO's. The table below indicates which peripherals are avail-
able on each GPIO port. When a differential connection is being used Positive inputs are restricted to the EVEN pins and Negative
inputs are restricted to the ODD pins. When a single ended connection is being used positive input is available on all pins. See the
device Reference Manual for more details on the ABUS and analog peripherals. Note that some functions may not be available on all
device variants.
Table 6.3. ABUS Routing Table
Peripheral Signal PA PB PC PD
EVEN ODD EVEN ODD EVEN ODD EVEN ODD
ACMP0 ANA_NEG Yes Yes Yes Yes Yes Yes Yes Yes
ANA_POS Yes Yes Yes Yes Yes Yes Yes Yes
ACMP1 ANA_NEG Yes Yes Yes Yes Yes Yes Yes Yes
IADC0 ANA_NEG Yes Yes Yes Yes Yes Yes Yes Yes

Pin Definitions
6.4 Digital Peripheral Connectivity
Many digital resources are routable and can be connected to numerous GPIO's. The table below indicates which peripherals are availa-
ble on each GPIO port. Note that some functions may not be available on all device variants.
Table 6.4. DBUS Routing Table
Peripheral.Resource PORT
PA PB PC PD
ACMP0.DIGOUT Available Available Available Available
ACMP1.DIGOUT Available Available Available Available
CMU.CLKIN0 Available Available
CMU.CLKOUT0 Available Available
FRC.DCLK Available Available
FRC.DFRAME Available Available
FRC.DOUT Available Available
I2C0.SCL Available Available Available Available
I2C0.SDA Available Available Available Available
I2C1.SCL Available Available
I2C1.SDA Available Available
LETIMER0.OUT0 Available Available
LETIMER0.OUT1 Available Available
MODEM.ANT0 Available Available Available Available
MODEM.ANT1 Available Available Available Available
MODEM.DCLK Available Available
MODEM.DIN Available Available
MODEM.DOUT Available Available
PRS.ASYNCH0 Available Available

Pin Definitions
PA PB PC PD
PRS.SYNCH0 Available Available Available Available
TIMER0.CC0 Available Available Available Available
TIMER0.CDTI0 Available Available Available Available
TIMER2.CC0 Available Available
TIMER2.CDTI0 Available Available
USART0.CLK Available Available Available Available
USART0.CS Available Available Available Available
USART0.CTS Available Available Available Available
USART0.RTS Available Available Available Available
USART0.RX Available Available Available Available
USART0.TX Available Available Available Available
USART1.CLK Available Available

Pin Definitions
PA PB PC PD
USART1.CS Available Available
USART1.CTS Available Available
USART1.RTS Available Available
USART1.RX Available Available
USART1.TX Available Available
USART2.CLK Available Available
USART2.CS Available Available
USART2.CTS Available Available
USART2.RTS Available Available
USART2.RX Available Available
USART2.TX Available Available

QFN32 Package Specifications
7. QFN32 Package Specifications
7.1 QFN32 Package Dimensions
Figure 7.1. QFN32 Package Drawing

Table 7.1. QFN32 Package Dimensions
Dimension Min Typ Max
A 0.80 0.85 0.90
A1 0.00 0.02 0.05
A3 0.20 REF
b 0.15 0.20 0.25
D 3.90 4.00 4.10
E 3.90 4.00 4.10
D2 2.60 2.70 2.80
E2 2.60 2.70 2.80
e 0.40 BSC
L 0.20 0.30 0.40
K 0.20 — —
R 0.075 — 0.125
aaa 0.10
bbb 0.07
ccc 0.10
ddd 0.05
eee 0.08
fff 0.10
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220, Variation VKKD-4.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

7.2 QFN32 PCB Land Pattern
Figure 7.2. QFN32 PCB Land Pattern Drawing

Table 7.2. QFN32 PCB Land Pattern Dimensions
Dimension Typ
L 0.76
W 0.22
e 0.40
S 3.21
S1 3.21
L1 2.80
W1 2.80
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
5. The stencil thickness should be 0.101 mm (4 mils).
6. The ratio of stencil aperture to land pad size can be 1:1 for all perimeter pads.
7. A 2x2 array of 1.10 mm x 1.10 mm openings on a 1.30 mm pitch can be used for the center ground pad.
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
10. Above notes and stencil design are shared as recommendations only. A customer or user may find it necessary to use
different parameters and fine tune their SMT process as required for their application and tooling.

7.3 QFN32 Package Marking
FFFF
PPPPPP
TTTTTT
YYWW
Figure 7.3. QFN32 Package Marking
The package marking consists of:

• FFFF – The product family codes.
1. Family Code ( B | M | F )
2. G (Gecko)
3. Series (2)
4. Device Configuration (1, 2, 3, ...)
• PPPPPP – The product option codes.
• 1-2. MCU Feature Codes
• 3-4. Radio Feature Codes
• 5. Flash (J = 1024k | I = 768k | H = 512k | W= 352k | G = 256k | F = 128k)
• 6. Temperature grade (G = -40 to 85 °C | I = -40 to 125 °C )
• TTTTTT – A trace or manufacturing code. The first letter is the device revision.
• YY – The last 2 digits of the assembly year.
• WW – The 2-digit workweek when the device was assembled.

Revision History
8. Revision History
Revision 1.2
May, 2024
• Merged document with EFR32MG21 Revision D datasheet.
• Corrected the lowest energy mode for LETIMER to EM3 in front page block diagram.
• 1. Feature List: Changed number of 16-bit Timer/Counter modules to 3 and added Secure Vault High features.
• 2. Ordering Information:
• Added Revision B Secure Vault High OPNs.
• Added all Revision D OPNs.
• Added note regarding Bluetooth 5.x support.
• Added Ordering Code Key.
• Removed Protocol Stack Column.
• 3.5.2 Low Energy Timer (LETIMER): Corrected lowest energy mode to EM3.
• Updated terminology to use inclusive lexicon.
• 3.7 Secure Vault Features: Added Secure Vault Features table and added Secure Vault High features.
• Table 3.2 Configuration Summary on page 16: Added TIMER3 and updated lowest energy mode for I2C0 to EM3.
• 4.1 Electrical Characteristics for Revision B: Added Power Supply Pin Dependencies section.
• Added section 4.3 Electrical Characteristics for Revision D with all Revision D specifications.
• 4.1.1 Absolute Maximum Ratings: Added "DC voltage on RESETn pin" specification and added note regarding RESETn pin's pullup
to DVDD.
• 4.1.2 General Operating Conditions: Added External Clock Input and DPLL Reference Clock maximum specifications.
• 4.1.5.1.4 RF Transmitter Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 2 Mbps Data Rate: Corrected condition for
In-band spurious emissions specification for PoutMAX from "+/- 2 MHz" to " +/- 4 MHz".
• 4.1.7 Energy Mode Wake-up and Entry Times: Changed units for "Wake-up time from EM1" specification from "AHB Clocks" to
"HCLKs".
• 4.1.8.1 High Frequency Crystal Oscillator: Added note to clarify "Startup Time" specification.
• 4.1.9 GPIO Pins (3V GPIO pins):
• Added "RESETn" test condition for VIL, VIH, and RPULL specifications.
• Updated test condition for VOL and VOH from "IOVDD = 1.62 V" to "IOVDD = 1.71 V".
• Added "RESETn low time to ensure pin reset" specification.
• 4.1.10 Analog to Digital Converter (ADC):
• Added 0.5x, 1x, 2x, 3x, and 4x gain test conditions for maximum "ADC clock frequency" specification.
• Added fADC_CLK to test conditions for "Gain Error, Normal mode" specification.
• Added note regarding pin voltage limitations.
• Removed the condition for IADC resolution.
• 4.1.11 Analog Comparator (ACMP): Added note regarding deprecated Capacitive Sensing feature.
• 4.1.14.1 USART SPI Main Timing and 4.1.15.1 USART SPI Secondary Timing:
• Added timing diagrams.
• Corrected references of "HPERCLK" to "PCLK".
• Corrected references of "VDD" to "I/O supply".
• Added 4.1.17 Boot Timing, 4.1.19 Crypto Operation Average Current for SE Manager API, and 4.1.18 Crypto Operation Timing for
SE Manager API.
• 5.2 RF Matching Networks:
• Added references to matching guide and layout design guide appnotes.
• Corrected 2G4RF1 and 2G4RF2 to RF2G4_IO1 and RF2G4_IO2.
• Table 6.2 GPIO Alternate Function Table on page 131: Added VREFP pin.
• Fixed minor typos throughout the document.

Revision History
Revision 1.1
September, 2019
• Updated the block diagram in the front page with new security features.
• Updated 1. Feature List with new security features.
• Replaced 'Standard' with 'Secure Element' under the Security column in 2. Ordering Information.
• Replaced Security Accelerator with Crypto Accelerator in Figure 3.1 Detailed EFR32MG21 Block Diagram on page 8.
• Updated 3.7 Secure Vault Features with more detailed information.
• Replaced 'ADC' with 'IADC' in 3.8.2 Analog to Digital Converter (IADC).
• Added the payload size under the Test Conditions of the parameter Sensitivity in Table 4.16 RF Receiver Characteristics for Blue-
tooth Low Energy in the 2.4 GHz Band 1 Mbps Data Rate on page 37 and Table 4.17 RF Receiver Characteristics for Bluetooth Low
Energy in the 2.4 GHz Band 2 Mbps Data Rate on page 38
• Corrected the units in Table 5.3 2.4 GHz 20 dBm Component Values on page 128.
• Added PC00 to Table 6.2 GPIO Alternate Function Table on page 131.
• Fixed minor typos throughout the document.
Revision 1.0
March, 2019
• Added Minimum and Maximum values to electrical specification tables.
• Updated BLE 125k and 500 kbps RF specifications to reflect latest silicon.
• Updated 20 dBm Tx RF specifications to reflect latest silicon.
• Added typical Curves.
• Added RF Matching networks.
• Updated RF specifications to reflect latest silicon.
• Updated typical specification values to reflect latest silicon.
• Wording, spelling, and grammar fixes.
Revision 0.5
February, 2019
• Added Flash electrical specification table.
• Added typical specification values for 20 dBm and 0 dBm PAs.
• Updated typical specification values for RF current consumption to reflect latest silicon.
Revision 0.42
January, 2019
• Updated typical values for all parameters, including RF parameters.
• Updated specification tables to reflect updated specification list.
• Synchronized revisions for all datasheets in device family.
Revision 0.4
July, 2018
• Updated specification tables to reflect updated specification list and inserted new specification tables.
• Updated typical values for key parameters.
Revision 0.1
May, 2018
Initial Release

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Disclaimer
Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software imple-
menters using or intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each
specific device, and “Typical” parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon
Labs reserves the right to make changes without further notice to the product information, specifications, and descriptions herein, and does not give warranties as to the
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EFR32MG21 Multiprotocol Wireless SoC

Family Data Sheet

The EFR32MG21 SoC is part of the Wireless Gecko portfolio.

Core / Memory Clock Management Energy Security

Peripheral Reflex System

Lowest power mode with peripheral operational:

EM0—Active EM1—Sleep EM2—Deep Sleep EM3—Stop EM4—Shutoff

The EFR32MG21 highlighted features are listed below.

silabs.com | Building a more connected world. Rev. 1.2 | 2

Table 2.1. Ordering Information

EFR32MG21B020F768IM32-B 20 dBm 768 64 High 20 QFN32

EFR32MG21B020F512IM32-B 20 dBm 512 64 High 20 QFN32

EFR32MG21B020F1024IM32-B 20 dBm 1024 96 High 20 QFN32

EFR32MG21B010F768IM32-B 10 dBm 768 64 High 20 QFN32

EFR32MG21B010F512IM32-B 10 dBm 512 64 High 20 QFN32

EFR32MG21B010F1024IM32-B 10 dBm 1024 96 High 20 QFN32

EFR32MG21A020F768IM32-B 20 dBm 768 64 Mid 20 QFN32

EFR32MG21A020F512IM32-B 20 dBm 512 64 Mid 20 QFN32

EFR32MG21A020F1024IM32-B 20 dBm 1024 96 Mid 20 QFN32

EFR32MG21A010F768IM32-B 10 dBm 768 64 Mid 20 QFN32

EFR32MG21A010F512IM32-B 10 dBm 512 64 Mid 20 QFN32

EFR32MG21A010F1024IM32-B 10 dBm 1024 96 Mid 20 QFN32

EFR32MG21B020F768IM32-D 20 dBm 768 64 High 20 QFN32

EFR32MG21B020F512IM32-D 20 dBm 512 64 High 20 QFN32

EFR32MG21B020F1024IM32-D 20 dBm 1024 96 High 20 QFN32

EFR32MG21B010F768IM32-D 10 dBm 768 64 High 20 QFN32

EFR32MG21B010F512IM32-D 10 dBm 512 64 High 20 QFN32

EFR32MG21B010F1024IM32-D 10 dBm 1024 96 High 20 QFN32

EFR32MG21A020F768IM32-D 20 dBm 768 64 Mid 20 QFN32

EFR32MG21A020F512IM32-D 20 dBm 512 64 Mid 20 QFN32

EFR32MG21A020F1024IM32-D 20 dBm 1024 96 Mid 20 QFN32

EFR32MG21A010F768IM32-D 10 dBm 768 64 Mid 20 QFN32

EFR32MG21A010F512IM32-D 10 dBm 512 64 Mid 20 QFN32

EFR32MG21A010F1024IM32-D 10 dBm 1024 96 Mid 20 QFN32

silabs.com | Building a more connected world. Rev. 1.2 | 3

EFR32MG21B 020 F 1024 I M 32 - D R

Product Family • EFR32MG21: Wireless Gecko MG21 Family

Security • A: Secure Vault Mid

Size • Memory Size in kBytes

Temperature Grade • I: -40 to +125 °C

Pins • Number of Package Pins

Tape & Reel • R: Tape & Reel (optional)

Figure 2.1. Ordering Code Key

silabs.com | Building a more connected world. Rev. 1.2 | 4

silabs.com | Building a more connected world. Rev. 1.2 | 5

silabs.com | Building a more connected world. Rev. 1.2 | 6

5. Typical Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . .126

6. Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

7. QFN32 Package Specifications. . . . . . . . . . . . . . . . . . . . . . . . 136

8. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141

silabs.com | Building a more connected world. Rev. 1.2 | 7

Radio Transciever Port I/O Configuration IOVDD

IOVDD Analog Peripherals

Regulator ULFRCO VDD

Figure 3.1. Detailed EFR32MG21 Block Diagram

3.2.1 Antenna Interface

silabs.com | Building a more connected world. Rev. 1.2 | 8

3.2.2 Fractional-N Frequency Synthesizer

3.2.3 Receiver Architecture