Scribd
Upload
11 views2 pages

Eee3131 Assignment 7

The document provides details about an assignment on computer memory topics. It includes questions about the differences between SRAM and DRAM, bus contention, memory chip specifications, memory capacities, ROM timing parameters, computer memory buses, RAM chip requirements, memory capacity calculations, memory addressing in hex, and specifications of different DDR memory types.

Uploaded by

Luyando Mfwankila
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
11 views2 pages

Eee3131 Assignment 7

The document provides details about an assignment on computer memory topics. It includes questions about the differences between SRAM and DRAM, bus contention, memory chip specifications, memory capacities, ROM timing parameters, computer memory buses, RAM chip requirements, memory capacity calculations, memory addressing in hex, and specifications of different DDR memory types.

Uploaded by

Luyando Mfwankila
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 2

EEE3131 ASSIGNMENT 7

DUE DATE: 07/06/2023


SUBMIT QUESTIONS: 3, 6, 11 and 12

1. Briefly describe the difference between SRAMs and DRAMs. What are the advantages
and disadvantages of each?
2. What do you understand by the term ‘bus contention’?
3. A certain semiconductor memory chip is specified as 2K X 8. How many words can be
stored on this chip? What is the word size? How many total bits can this chip store?
4. Which memory stores the most bits: a 5M X 8 memory or a memory that stores 1M
words at a word size of 16 bits?
5. Define the following terms.
(a) Memory cell
(b) Memory word
(c) Address
(d) Byte
(e) Access time
6. Figure 6.1 shows how data from a ROM can be transferred to an external register. The
ROM has the following timing parameters: tACC = 250 ns and tOE =120 ns. Assume that
the new address inputs have been applied to the ROM 500 ns before the occurrence of the
TRANSFER pulse. Determine the minimum duration of the TRANSFER pulse for
reliable transfer of data.
7. Repeat Problem 6 if the address inputs are changed 70 ns prior to the TRANSFER pulse.

Fig 6.1
8. (a)What are the three buses in a computer memory system?
(b) Which bus is used by the CPU to select the memory location?
(c) Which bus is used to carry data from memory to the CPU during a read operation?
(d) What is the source of data on the data bus during a write operation?

9. A microprocessor uses RAM chips of 1024 × 1 capacity.


(a) How many chips are required to yield the capacity of 1 Kbytes?
(b) How many chips will be required to provide the capacity of 16 Kbytes?

10. What is the capacity of a RAM which has 16 address inputs, 4 data inputs and 4 data
outputs?
11. In a microcomputer, the addresses of memory locations are binary numbers that identify
each memory circuit where a byte is stored. The number of bits that make up an address
depends on how many memory locations there are. Since the number of bits can be very
large, the addresses are often specified in hex instead of binary.
a. If a microcomputer uses a 20-bit address, how many different memory locations
are there?
b. How many hex digits are needed to represent the address of a memory location?
c. What is the hex address of the 256th memory location? (Note: The first address is
always 0.)
12. Complete the following Table:
Memory Type Max Speed Supply Voltage No. Of Pins On Connectors
DDR1 400 MHz 2.5 V 184
DDR2
DDR3
DDR4
DDR5

You might also like