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Application Report
Zero-Voltage-Switching Flyback Using UCC28780
Controller and UCC5304 Isolated Synchronous-
Rectifier Driver

ABSTRACT
This application report describes how the UCC28780 Active-Clamp Flyback controller can be paired with the
isolated driver UCC5304 to implement a Zero-Voltage-Switching Flyback (ZVSF) power supply, delivering high
efficiency and high power-density at a competitive cost compared to the conventional Quasi-Resonant (QR)
flyback topology.

Table of Contents
1 Introduction.............................................................................................................................................................................2
2 Topology Overview................................................................................................................................................................. 3
3 Topology Differences vs. ACF and QR................................................................................................................................. 4
4 Simplified Application Diagram.............................................................................................................................................5
5 ZVSF Advantages and Benefits.............................................................................................................................................6
6 Use of UCC28780 + UCC5304 to Implement ZVSF...............................................................................................................7
6.1 UCC28780 Key Features .................................................................................................................................................7
6.2 UCC5304 Key Features ...................................................................................................................................................7
6.3 Key Specifications .......................................................................................................................................................... 8
6.4 Power Stage Parameters ................................................................................................................................................ 8
6.5 Schematic Detailed Description .................................................................................................................................... 8
7 PMP21552 EVM......................................................................................................................................................................11
8 PMP21552 Performance Results......................................................................................................................................... 12
8.1 Efficiency ....................................................................................................................................................................... 12
8.2 Stand-by Power ............................................................................................................................................................. 13
8.3 “Tiny-Load” (0.25 W) Efficiency ...................................................................................................................................13
8.4 Conducted EMI .............................................................................................................................................................. 14
8.5 Radiated EMI ..................................................................................................................................................................15
8.6 Switching Waveforms ................................................................................................................................................... 17
9 Summary............................................................................................................................................................................... 18
10 References.......................................................................................................................................................................... 18

Trademarks
USB Type-C™ are trademarks of USB Implementers Forum.
All other trademarks are the property of their respective owners.

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Introduction www.ti.com

1 Introduction
Conventional fixed-frequency and quasi-resonant (QR) flybacks are limited in their power density and upper
switching frequency capability due to the switching loss and the dissipation of the transformer leakage
inductance energy. The active-clamp-flyback (ACF) overcomes these limitations by achieving zero-voltage-
switching (ZVS) and recycling of the leakage energy to the output. However, these benefits do not come for free,
the ACF requires some extra components to achieve the benefits – a second primary high-side switch, high-side
driver/level-shifter, bigger clamp capacitors, and so forth.
An alternative ZVS flyback (ZVSF) topology is introduced in this application note. This ZVSF topology achieves
ZVS only – that is, the leakage energy is not recovered. The power-loss saving realized by ZVS allows for
increased switching frequency and therefore smaller transformer size and higher power-density compared to QR
and fixed-frequency designs. This offers a simpler, lower component-count, moderate-performance alternative to
the ACF, that sits somewhere in between QR and ACF in terms of both performance and component-count
complexity.
The ZVSF topology is a good alternative to consider for medium-density high-volume applications, and this
application note shows how the ACF controller UCC28780 can be combined with an isolated driver UCC5304 to
implement ZVSF using secondary-side synchronous rectification (SR).

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www.ti.com Topology Overview

2 Topology Overview
Figure 2-1 shows the overall topology architecture along with some typical waveforms.
(ZVSF) Passive-clamp + ZVS

Vbulk
Lk N:1
isec

im

SR
iclamp VSW
PWML
driver QL
driver

PWMH
Isolator

VSW

iclamp

im

isec

PWMH

Figure 2-1. ZVSF Topology Block Diagram and Waveforms

In the same way as conventional QR or fixed-frequency flyback, the primary side uses a clamp snubber to limit
the Vds stress on the primary FET due to the leakage inductance, and much of the leakage inductance energy is
dissipated in the clamp. The clamp can be a TVS type, as Figure 2-1 shows, or an RCD snubber.
The ZVSF controller operates in transition-mode (TM) at heavy load, where the primary FET and secondary
synchronous rectifier (SR) are driven in complement to each other, with adaptive dead-time in between. The
primary on-time is adjusted by the control loop to adjust the peak primary magnetizing current, in order to
regulate the output voltage. The secondary SR on-time is extended beyond the normal zero-current point to
allow some negative magnetizing current to build up in the transformer. The energy associated with the negative
current discharges the total drain-node capacitance when the SR is turned off, and the next turn-on point for the
primary FET occurs when the drain voltage has dropped close to zero, for ZVS turn-on.

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3 Topology Differences vs. ACF and QR

(QR) Passive-clamp + QR (ZVSF) Passive-clamp + ZVS (ACF) Active-clamp + ZVS

Vbulk Vbulk Vbulk

Lk N:1 Lk N:1 Lk N:1
isec isec iclamp isec

im im im

SR SR SR
iclamp VSW iclamp VSW
VSW
GND PWML
QR PWML
driver QL driver QL HB driver QL
Controller
controller driver controller

PWMH
PWMH PWML
Isolator

UCC28780

VSW VSW VSW

Vbulk
EMI
iclamp iclamp iclamp

im im im

isec isec isec

PWMH PWMH

Figure 3-1. ZVSF Topology Block Diagram and Waveforms vs QR and ACF

Figure 3-1 shows that the ZVSF power circuit and waveforms are more similar to QR than to ACF. For both QR
and ZVSF, the leakage inductance energy is not recycled, but is instead mostly dissipated in the primary clamp.
At minimum input voltage and maximum rated-output voltage, a QR design would usually already operate close
to ZVS due to the natural resonant ringing between the magnetizing inductance and the equivalent switch node
capacitance – assuming that the transformer turns ratio is designed for a reflected voltage approximately equal
to the minimum input voltage (typical QR design target).
However, at high-line input voltages, even when switching on the first valley of the resonant ring, the
instantaneous voltage is non-zero and actually quite significant. As a result, QR design can only achieve ZVS at
minimum input voltage (VIN). For wide output-voltage range applications, such as USB-C PD and PPS chargers,
ZVS can only be achieved at minimum VIN and maximum VOUT – at lower VOUT levels, the reflected voltage is
also lower – so valley-switching will occur at a finite non-zero voltage level, with no ZVS.
An existing QR design can be converted to ZVSF by transitioning from the QR controller to UCC28780, and by
changing the local secondary-side SR controller to the isolated SR driver UCC5304. The PWMH output of the
UCC28780 takes the place of the SR controller through the isolated driver. By building up just enough negative
current, depending on VIN and VOUT levels, the ZVSF topology can achieve ZVS across the full range of VIN and
VOUT, enhancing any QR stage into a ZVSF stage over the full operating range.

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www.ti.com Simplified Application Diagram

4 Simplified Application Diagram

Figure 4-1 shows a simplified application diagram using the UCC28780 primary-side controller and UCC5304
isolated SR driver.

DBD NP NS
VAC ~
VO
± +

Gate
Driver RUN

UCC27517
PWMH
NA Iso Driver

UCC5304
VDD PWML RUN CS PWMH
VS
HV startup &
NTC SWS ZVS Sense

GND UCC28780
HVG

RDM FB

RTZ SET BUR REF

Figure 4-1. ZVSF Simplified Application Diagram

The UCC28780 SWS pin indirectly senses the primary FET drain voltage, and the SR on-time extension is auto-
adjusted with changes in load current and bulk-capacitor voltage to achieve ZVS with minimal excess negative
magnetizing current, to maximize efficiency. A primary-side RCD snubber is used to clamp the primary FET VDS.
An external low-side driver is used to interface the logic-level PWML drive signal to the primary FET gate.
The UCC5304 isolated driver is used to drive the SR across the reinforced isolation barrier between primary and
secondary. The short propagation delay (28 ns typical) ensures short SR FET body-diode conduction time, to
help improve efficiency.

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5 ZVSF Advantages and Benefits

Table 5-1 summarizes the ZVSF benefits and advantages over QR in key applications.
Table 5-1. Summary of ZVSF Benefits and Advantages Over QR in Certain Key Applications
End Equipment/Application Value of ZVSF over QR Demonstrated Benefit/Result

Wide-input-range adaptor Better high-line efficiency with high- QR @ 230 Vac 91.5~92%
frequency, small-size transformer due to ZVS
ZVSF @ 230 Vac ~93%
benefit

High-line-only or PFC front-end Better efficiency from ZVS vs. QR 1st-valley QR @ 230 Vac ~93%
switching
ZVSF @ 230 Vac ~94%
ACF-GaN @ 230 Vac ~95%+

Wide-VOUT PD or PPS Achieve ZVS across full VOUT range Commercial QR @ 230 Vac, 5 Vdc@15 W
~88%
Commercial ZVS-Aux IPD2105 @ 230 Vac, 5
Vdc@10W ~82%
ZVSF @ 230 Vac, 5 Vdc@15 W ~90%

Moderate-to-high-frequency designs for High-frequency QR designs → efficiency/ Low-frequency 65-W QR ~60 kHz needs
moderate density thermal limit at high-line RM10-size (or similar) transformer
ZVSF higher frequency and smaller ZVSF 65 W @ 180–200 kHz can use RM8-
transformer → same 90-V efficiency as QR, size transformer
but better high-line efficiency
Enables high frequency and medium power
density WITHOUT need for GaN

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6 Use of UCC28780 + UCC5304 to Implement ZVSF

As Figure 6-1 shows, the combination of UCC28780 controller and UCC5304 driver allows a ZVSF to be readily
implemented using available ICs. As already noted, an existing QR design can readily be converted to ZVSF,
using the schematic example.

Figure 6-1. PMP21552 65-W ZVSF Schematic (Partial) Using UCC28780 + UCC5304

6.1 UCC28780 Key Features

• Adaptive ZVS control
• Adjustable timing via RDM and RTZ for different size power FETs
• Programmable burst-mode threshold via BUR pin
• Input Brownout detection and protection
• Extensive protections – overpower, overtemperature, output overvoltage, overcurrent, short-circuit and pin-
faults
• RUN pin to allow the external iso-driver to be power-managed in stand-by and light load

6.2 UCC5304 Key Features

• Reinforced isolation to 7 kVpeak, 5 kVRMS
• Single-channel SOIC-8 wide-body package for > 8.5 mm creepage distance
• Fast propagation delay 28 ns typical, 40 ns maximum
• Common-Mode-Transient-Immunity (CMTI) > 100 V/ns
• 4-A/6-A peak source/sink for fast SR turn on and turn off
• Wide operating range on secondary-side VDD, 5-18 V

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6.3 Key Specifications

Table 6-1 lists the PMP21552 key specification parameters.
Table 6-1. PMP21552 Key Specification Parameters
PARAMETER SYMBOL VALUE UNIT

Minimum input voltage (on bulk VDCinmin 75 V

capacitor)

Maximum input voltage (on bulk VDCinmax 375 V

capacitor)

Output Voltage (maximum of PD VOUT 20 V

range)

Output load current (maximum) IOUT 3.25 A

Efficiency (target) η 93 %

Secondary rectifier forward Vd 0.1 V

voltage drop

Maximum allowed primary FET VDS_max_pri 540 V

VDS stress (90% of 600-V rating)

Maximum allowed SR FET VDS VDS_max_pri 135 V

stress (90% of 150-V rating)

Target minimum switching fsw_min 110 kHz

frequency (at full load, VDCinmin)

Duty-cycle loss for resonant KRES 8 %

voltage transitions

6.4 Power Stage Parameters

Choose Nps = 5 — this gives approximately 100-V reflected voltage, and achieves a good compromise for the
maximum VDS stress targets for both primary FET and secondary SR.

N ps : 5
N ps u V OUT Vd
DMAX : 0.573
VDCin min N ps u V OUT Vd
DMAX 2 u VDCin min2 u 1
LM : u u 1 K RES 110.366 +
2 u VOUT u I OUT f sw _ min (1)

6.5 Schematic Detailed Description

6.5.1 EMI Filter

Differential-mode (DM) filtering is provided by C3 and the PI-filter formed by C1 + L1 + C2, C4, C5.
Common-mode (CM) filtering is provided by CM-choke L2 and Y-cap C15.
A shield/CM-balance layer inside transformer T1 also helps reduce the CM noise.
A grounded transformer flux-band (to PGND) and a Copper shield around the EMI filter and over the primary
switch-node also help to reduce the EMI.

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6.5.2 Power Stage

Transformer T1 uses an interleaved structure with secondary winding sandwiched between two half-primary
windings; magnetizing inductance approximately 110 µH, Nps = 5, leakage inductance approximately 1.8 µH
(approximately 1.65%).
Primary MOSFET Q2 = IPD60R280P7S is chosen for a reasonable trade-off between RDS(on) and gate charge/
capacitance. The reflected voltage is set to 100 V (at 20-V output) and the RCD snubber is damped to allow use
of a 600-V FET and still achieve 90% derating margin.
Secondary-side SR Q5 = BSC093N15 150-V FET, again to give more than 90% derating margin.
6.5.3 RCD Snubber
R2, C6, and D10 are the main RCD-clamp snubber components. D10 is chosen to be a slow-recovery type to
help reduce the leakage energy consumed by the snubber. Damping resistors R5 and R7 are added to damp out
the leakage ring (see VDS waveforms in Section 8.6), to improve EMI and reduce the maximum VDS spike
slightly. TVS D11 is added to help clamp transient VDS spikes under short-duration transient events.
6.5.4 Low-Side Driver
A low-side driver U3 is used to level shift the TTL-level PWML signal from the controller to the higher level
required to drive FET Q2. LDO U1 provides a regulated rail at ~10 V to U3 to clamp the gate drive level when
Vdd_pri is too high.
6.5.5 HV Start-up and SWS Sensing
High-voltage depletion-mode FET Q4 (BSS126) is used to charge Vdd_pri at start-up; this eliminates the typical
start-up bleed-resistor chain, saving stand-by power and allowing much faster start-up time. Associated
components D6, D7, C23, C24, R18 and R24 provide various protections for Q4 under the various possible
operating modes (start-up, pin/component faults, and so forth.)
After start-up is complete, Q4 performs an additional function of sensing the switched-node voltage to detect
ZVS for the SWS input of the UCC28780, while blocking the high voltage.
6.5.6 I pk Adjust Circuit
As shown in the schematic diagram, the peak of the magnetizing current iM is adjusted in order to regulate the
output voltage as load power and input voltage vary.
At lighter loads, there is an efficiency benefit if the peak of the magnetizing current (Ipk) is increased somewhat,
because higher Ipk at light load increases the per-cycle efficiency, reduces the number of cycles required
(average switching frequency), and so increases overall efficiency in light load and reduces stand-by power.
U9 and associated components C30, C31, R22, R34, R36, and R51 provide an Ipk increase function in light-load
and stand-by modes by forming a switched divider on the CS pin.

6.5.7 Burst-Mode Hysteresis Circuit

Optional U10 and associated components D12, R45, R46, R47, R48, R49, R50, and C28 add additional
hysteresis to the BUR pin thresholds to help reduce possible audible noise at the burst-mode transitions.
6.5.8 Switched Supply Rail to UCC5304
Q1B, R12, R4, and C34 implement a switched supply rail for the isolated SR driver U4 – when the ENSR/RUN
signal goes low for longer intervals in SBP/LPM mode, the VCCI rail to U4 is effectively disconnected to save
bias and standby power.
6.5.9 Dual-Winding Aux Bias
Two primary-side auxiliary windings are used on the transformer to cope with the wide VOUT range more
efficiently. The tap at pin 6 connects directly to Vdd_pri through D3, R56, and provides Vdd_pri power when
VOUT is set to 12–20 V (lower auxiliary ratio to main secondary is 1:1). The upper tap at pin 5 (approx. 3:1 net

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ratio to main secondary) provides power to Vdd_pri when VOUT is < 12 V, with the higher ratio chosen to boost
the auxiliary rail to ~12 V when VOUT is as low as 4 V.
The LDO Q3, R17, D5, C44, C16, and C22 is needed to limit the aux rail generated by the upper rail when VOUT
is > 12 V. D5 is chosen to set the LDO regulated voltage low enough to be back-biased by the direct feed from
the lower aux when VOUT is high enough, to increase overall efficiency.
6.5.10 Active-Ripple-Cancellation Circuit
Q9, R37, and R39 are used to add hysteresis to the FB pin in burst-mode, to help stabilize the burst-mode
operation and deliver consistent burst lengths.

6.5.11 Secondary-Side Aux Bias for UCC5304

A secondary-referenced aux winding C-D connects to D21, C11 and to LDO Q6, R55, D2 and C29 to generate a
secondary bias rail VDD for the isolated driver's output. The turns ratio of 2:1 with respect to the main secondary
ensures adequate gate-drive level for the SR FET when VOUT is at the 5-V level. LDO Q6/D2 limit the VDD rail at
higher VOUT levels. To improve efficiency at high VOUT levels 15-20 V, a second LDO U7 is used to power VDD
directly from VOUT.

6.5.12 ATL431 Feedback Regulation and USB Type-C™ PD Interface

The feedback regulation circuit U5, C27, R32, R26, R25, and R31 is used to closed-loop control the current
pulled from the FB pin in order to regulate VOUT at the desired level. R27 and C25 are added to provide phase-
boost for control-loop stability. R28 connects to the USB-C PD controller, which controls how much current is
pulled through R28 in order to set the required PD voltage that is commanded by the USB Type-C load device.

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www.ti.com PMP21552 EVM

7 PMP21552 EVM

Figure 7-1. PMP21552 65-W ZVSF Reference Design PCB Assembly Using UCC28780 + UCC5304

PMP21552 is a released reference design for a 65-W USB-C PD adapter, using the UCC28780 and UCC5304
chipset in a ZVSF topology. The design supports 5 V/3 A, 9 V/3 A, 15 V/ 3A and 20 V/3.25 A in a compact 62-cc
size (open-frame dimensions 45 × 55 × 25 mm). Full-load efficiency is over 92.5% across the full universal
90-265 V AC range. The primary-side switch uses a Si super-junction FET, the transformer size is RM8, and the
design passes EN55022 level-B conducted and radiated emissions with margin.

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8 PMP21552 Performance Results

Full details of the PMP21552 design and performance are available online in the 65-W USB Type-C ZVS-
Flyback Reference Design . Selected performance highlights are shown here. Efficiency data does not include
the USB Type-C cable loss.
8.1 Efficiency
94%

92%

90%
Efficiency (%)

88%

86%

84%
90 V
115 V
82% 230 V
264 V
80%
5 15 25 35 45 55 65
20-V Output Power (W) D001

Figure 8-1. PMP21552 65-W ZVSF Efficiency vs Load/Line at 20-V Output

94%

92%

90%
Efficiency (%)

88%

86%

84%
115 V Avg Eff
230 V Avg Eff
82% DoE Level VI
CoC Tier 2
80%
5 10 15 20
Output Voltage (V) D002

Figure 8-2. PMP21552 65-W ZVSF Average Efficiency vs VOUT and Line

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8.2 Stand-by Power

Table 8-1 lists the stand-by power measurement results.
Table 8-1. Stand-by Power Measurement Results
Stand-by Power (5 V, no Load)

115 Vac 230 Vac

26 mW 30 mW

8.3 “Tiny-Load” (0.25 W) Efficiency

Table 8-2 lists the "tiny-load' measurement results.
Table 8-2. “Tiny-Load” Measurement Results
“Tiny Load” 250-mW Output Power at 20 V

115 Vac 230 Vac

Input power 370 mW 394 mW

Efficiency 68% 63%

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8.4 Conducted EMI

8.4.1 Passes EN55032 Level-B QP and AVG With Margin

Figure 8-3. PMP21552 65-W ZVSF QP and AVG Conducted Emissions at 115 V, 20-V, 65-W, Earthed Load;
L1 (L) and L2 (N)

Figure 8-4. PMP21552 65-W ZVSF QP and AVG Conducted Emissions at 230 V, 20-V, 65-W, Earthed Load;
L1 (L) and L2 (N)

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8.5 Radiated EMI

8.5.1 Passes EN55032 Level-B Vertical and Horizontal Polarization With Margin

Figure 8-5. PMP21552 65-W ZVSF Radiated Emissions at 115 V, 20-V, 65-W, Earthed Load, Horizontal
Polarization

Figure 8-6. PMP21552 65-W ZVSF Radiated Emissions at 115 V, 20-V, 65-W, Earthed Load, Vertical
Polarization

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Figure 8-7. PMP21552 65-W ZVSF Radiated Emissions at 230 V, 20-V, 65-W, Earthed Load, Horizontal
Polarization

Figure 8-8. PMP21552 65-W ZVSF Radiated Emissions at 230 V, 20-V, 65-W, Earthed Load, Vertical
Polarization

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8.6 Switching Waveforms

Figure 8-9. PMP21552 65-W ZVSF Waveforms at 264-V Input, 20-V, 65-W Output; Ch1: Pri Vgs; Ch2: Pri
Vrcs; Ch3: Pri Vds; Ch4: sec SR Vds

Figure 8-10. PMP21552 65-W ZVSF Waveforms at 264-V Input, 5-V, 15-W Output; Ch Pri Vgs; Ch2: Pri
Vrcs; Ch3: Pri Vds; Ch4: sec SR Vds

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Summary www.ti.com

9 Summary
For high-volume applications where higher efficiency and power-density are required, or higher switching
frequency and smaller size are required, the ZVSF topology is worth considering. It offers performance
advantages over QR and fixed-frequency single-switch flyback topologies. While it cannot deliver the same
efficiency and power-density performance as ACF, it does offer a simpler, lower component-count alternative.
The chipset of UCC28780 and UCC5304 are available from TI to implement the topology, along with a reference
design PMP21552 to help users get started.

10 References
• UCC28780 product folder: http://www.ti.com/product/UCC28780
• UCC5304 product folder: http://www.ti.com/product/UCC5304
• ZVSF reference design PMP21552 folder: http://www.ti.com/tool/PMP21552
• ACF-Si reference design PMP21479 folder: http://www.ti.com/tool/PMP21479

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