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Lecture 4-5 - ARM - Assembly - 3 (New)

The document discusses ARM assembly language instructions including barrel shifter operations, branch instructions, pre-indexed versus post-indexed addressing, load/store multiple instructions, and examples of using the stack pointer with different instructions.

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43 views33 pages

Lecture 4-5 - ARM - Assembly - 3 (New)

The document discusses ARM assembly language instructions including barrel shifter operations, branch instructions, pre-indexed versus post-indexed addressing, load/store multiple instructions, and examples of using the stack pointer with different instructions.

Uploaded by

abdelkarim.haider.7
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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ARM Assembly 3

Dr. Omar Fahmy


Associate Professor, P. Eng.
The Barrel Shifter
LSL : Logical Left Shift ASR: Arithmetic Right Shift

CF Destination 0 Destination CF

Multiplication by a power of 2 Division by a power of 2,


preserving the sign bit

LSR : Logical Shift Right ROR: Rotate Right

...0 Destination CF Destination CF

Division by a power of 2 Bit rotate with wrap around


from LSB to MSB

RRX: Rotate Right Extended

Destination CF

Single bit rotate with wrap around


from CF to MSB
Using the Barrel Shifter: The Second Operand

Operand Operand Register, optionally with shift


operation
1 2  Shift value can be either be:
 5 bit unsigned integer
 Specified in bottom byte of
another register.
Barrel
Shifter  Used for multiplication by a
power of 2
Example: ADD R1, R2, R3, LSL #2
(R2 + R3*4) -> R1

Immediate value
 8 bit number, with a range of 0-
ALU 255.
 Rotated right through even
number of positions
 Allows increased range of 32-bit
Result constants to be loaded directly
into registers
Branch Instructions

 Branch : B{<cond>} label


 Branch with Link :BL{<cond>} subroutine_label

31 28 27 25 24 23 0

Cond 1 0 1 L Offset

Link bit 0 = Branch


1 = Branch with link
Condition field

 The processor core shifts the offset field left by 2 positions,


sign-extends it and adds it to the PC
 ± 32 Mbyte range
 How to perform longer branches or absolute address branches?
solution: LDR PC,…
ARM Branches and Subroutines

 BL <subroutine>
 Stores return address in LR
 Returning implemented by restoring the PC from LR
 For non-leaf subroutines, LR will have to be stacked

func1 func2
STMFD :
: sp!,{regs,lr}
:
: :
:
BL func1 BL func2
:
: :
:
: LDMFD
sp!,{regs,pc} MOV pc, lr

main program subroutine leaf subroutine


(no calls)
Pre or Post Indexed Addressing?
 Pre-indexed: STR r0,[r1,#12]
Offset r0
Source
12 0x20c 0x5 0x5 Register
for STR
r1
Base
Register 0x200 0x200

Base-update form (‘!’): STR r0,[r1,#12]!

 Post-indexed: STR r0,[r1],#12


Updated r1 Offset
Base 0x20c 12 0x20c
Register r0
Source
Original r1 0x5 Register
Base 0x5 for STR
0x200
Register 0x200

Base register always updated


LDM / STM operation
 Load/Store Multiple Syntax:
<LDM|STM>{<cond>}<addressing_mode> Rb{!}, <register list>
 4 addressing modes:
LDMIA / STMIA increment after
LDMIB / STMIB increment before
LDMDA / STMDA decrement after
LDMDB / STMDB decrement before
IA IB DA DB
LDMxx r10, {r0,r1,r4} r4
STMxx r10, {r0,r1,r4}
r4 r1
r1 r0 Increasing
Base Register (Rb) r10 r0 r4 Address
r1 r4

Base-update possible: r0 r1
LDM r10!,{r0-r6} r0
LDM/STM for Stack Operations
Traditionally, a stack grows down in memory, with the last
“pushed” value at the lowest address. The ARM also supports
ascending stacks, where the stack structure grows up through
memory.
The value of the stack pointer can either:
• Point to the last occupied address (Full stack)
– and so needs pre-decrementing/incrementing (ie before the push)
• Point to an unoccupied address (Empty stack)
– and so needs post-decrementing/incrementing (ie after the push)
The stack type to be used is given by the postfix to the
instruction:
• STMFD / LDMFD : Full Descending stack
• STMFA / LDMFA : Full Ascending stack.
• STMED / LDMED : Empty Descending stack
• STMEA / LDMEA : Empty Ascending stack
Note: ARM Compilers will always use a Full descending stack.
Stack Examples
STMFD sp!, STMED sp!, STMFA sp!, STMEA sp!,
{r0,r1,r3-r5} {r0,r1,r3-r5} {r0,r1,r3-r5} {r0,r1,r3-r5}

0x418
SP r5 SP
r4 r5
r3 r4
r1 r3
r0 r1
Old SP Old SP r5 Old SP Old SP r0 0x400
r5 r4
r4 r3
r3 r1
r1 r0
SP r0 SP
0x3e8

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