Paper -1

Unit 1:

Introduction of Microcomputer System

Microcomputer systems are small and inexpensive computers that are widely used in various
applications. The 8085 microprocessor is an example of a Microcomputer System. A
microprocessor system contains two types of memory that are EPROM and R/WM, Input and
Output devices, and the buses that are used to link all the peripherals (memory and I/Os) to the
MPU.

The Microprocessor Unit (MPU)

The MPU is the brain of the microcomputer system. It contains the arithmetic and logic unit
(ALU) and the control unit (CU) that work together to execute instructions. The 8085
microcomputer system has 16 address lines ranging from A0 to A15 that are used to address
memory. The lower-order address bus A0-A7 is used to identify the input and output devices.

Memory

There are two types of memory in the microcomputer system: Erasable Programmable Read-
Only Memory (EPROM) and Random-Access Read-Write Memory (R/WM). EPROM is a type of
memory that can be programmed once and can be erased by exposing it to ultraviolet light.
R/WM is a type of memory that can be both read and written to. The MPU communicates with
memory through memory read and memory write control signals.

Input and Output (I/O) Devices

The microcomputer system contains input and output (I/O) devices that allow the system to
interact with the external environment. The microcomputer system has 8 data lines, D0-D7,
which are bidirectional and common to all devices. The microcomputer system generates four
control signals: memory read, memory write, I/O read, and I/O write. These signals are
connected to different peripheral devices.
Interfacing Devices

The MPU communicates with only one peripheral device at a time by enabling that peripheral
through its control signal. For example, to send data to the output device, the MPU places the
device address (or output port number) on the address bus, data on the data bus, and enables
the output device by using its control signal I/O Write. After that, the output device displays the
result.

The other peripheral devices that are not enabled remain in a high impedance state called Tri-
state. The bus drivers increase the current driving capacity of the buses, the decoder decodes
the address to identify the output port, and the latch holds data output for display. These
devices are called Interfacing devices. Interfacing devices are semiconductor chips that are
necessary to connect peripherals to the bus system.

In summary, the microcomputer system is a small and inexpensive computer that contains an
MPU, memory, input and output devices, and buses that connect all the peripherals. The
microcomputer system communicates with peripherals through control signals, which are
connected to different peripheral devices. Interfacing devices are necessary to connect
peripherals to the bus system.

The block diagram of a microcomputer system is shown below:

Advantages:
Flexibility: A microcomputer system can be customized to meet the needs of a wide range of
applications. It can be programmed to handle a variety of tasks, and its components can be
easily upgraded or replaced as needed.

Cost-effective: Microcomputer systems are generally less expensive than larger computer
systems, which makes them a cost-effective solution for many applications.

Compact size: Microcomputer systems are typically small and compact, which makes them
ideal for applications where space is limited.

Ease of use: Microcomputer systems are generally easy to use, particularly for individuals with
basic computer skills. They typically come with user-friendly interfaces and software that make
them easy to operate.

Disadvantages:

Limited processing power: Microcomputer systems typically have limited processing power
compared to larger computer systems. This can limit their ability to handle complex tasks or run
resource-intensive software.

Limited memory capacity: Microcomputer systems typically have limited memory capacity
compared to larger computer systems. This can limit their ability to handle large amounts of
data or run complex software.

Limited I/O options: Microcomputer systems typically have limited I/O options compared to
larger computer systems. This can limit their ability to interface with other devices or handle
complex I/O operations.

Limited expansion options: While microcomputer systems can be upgraded or replaced, they
typically have limited expansion options compared to larger computer systems. This can limit
their ability to grow or adapt to changing needs over time.
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General architecture of computer: -

A computer is a multipurpose programmable machine that reads binary instructions

from its memory, accepts binary data as input and processes data according to those

instructions, and provides result as output.

1)The physical components of the computer are called hardware

2)set of instructions written from the computer to perform a task is called a program

and a group of programs is called software

the computer includes CPU , memory, input and output as shown:

Fig –a- block diagram of computer

General architecture of A microcomputer:

The microcomputer is a complete computer similar to any other computer, except that the

CPU functions of the microcomputer are performed by the microprocessor.

It includes four components: microprocessor, input, output and memory (read/write memory

(RAM) and read only memory (ROM)). These components are organized around a common

communication path called a bus.

Fig –b- shows a simplified but formal structure of a microcomputer.

A microprocessor is a general purpose processing unit built into one chip ( a single

integrated circuit (IC)). is the heart of a microcomputer that perform:-

o executes instructions of the program and processes data.

o It is responsible for performing all arithmetic and logic operations

o controls overall system operation.

The mp can be divided into three segments:

1- Arithmetic / logic unit (ALU).

2- Register unit.

3- Control unit.

1- Arithmetic / logic unit (ALU): -

The ALU performs arithmetic operation such as addition and subtraction, and logic
operations such as AND, OR and exclusive OR, the results are stored either in registers

or in memory or set to output devices.

2- Register unit: -

The registers are used primarily to store data temporarily during the execution of

program.

3- Control unit: -

This unit provides the necessary control signal to all the operations in the

microcomputer.

Input device : -

Use to transfer data binary from the outside world to the mp. It includes devices such as

keyboards, analog-to-digital converters.

Output device : -

Use to transfers data from the mp to output devices such as light emitting diodes (LEDs),

printers.

Memory: -

Use to stores binary information such as instructions and data, and provides information to

the mp whenever necessary.

The memory has two types :

1- Read Only Memory (ROM)

2- Read /Write Memory (R/W M) or known as Random Access Memory (RAM)

MP 3

1- ROM: - this type can store program single time and read it many times.

Programs stored in the ROM can only be read they cannot be altered.

Note: - data stored in ROM will not be lost when the power-off.

2- R/W M or RAM: - it is used to store user programs and data. The information stored in

this memory can be read and altered easily.

Note: All data stored in RAM will be lost when power-off.

System bus: -

The system bus is a communication path between the mp and peripherals.

It is a group of wire that carries bits.

Types of Microprocessors:-

Microprocessors generally is categorized in terms of the maximum number of binary bits in

the data they process “ their word length”. Over time, five standard data widths have evolved

for microprocessors: 4-bit, 8-bit, 16-bit, 32-bit, 64-bit. There are so many manufacturers of

Microprocessors, but only two companies have been produces popular microprocessors: Intel

and Motorola.

How does the microcomputer work?

Assume that a program and data are already entered in the R/WM. the instruction are

stored sequentially in the memory. The mp fetches the first instruction from its memory,

decodes it, and executes that instruction. The sequence of fetch, decode and execute is

continued until the mp comes the instruction stop.

During the entire process, the mp uses the system bus to fetch the binary instruction and data

from the memory. It uses registers from the register section to store data temporarily and it

performs the computing function in the ALU section. Finally, it sends out the result in binary

using the same bus lines, to output device.

MP 4

Data types: -

Any data in computer system can be represented in many kinds depending on its size.

These kinds are:-

1- Bit (binary digit) and this can take only two state either zero (0) or one (1)

2- Nibble: this type consists of four bits and can take 16 state (24

).
3- Byte: this consists of 8-bits and can taken 256 state (28

).

4- Word: consists of 16-bits the computer recognizes and processes at a time.

5- Double word: consists of 32-bit .

Number Systems

For Microprocessors, information such as instruction, data and addresses are described with

numbers. The types of numbers are not normally the decimal numbers we are familiar with;

instead, binary and hexadecimal numbers are used. Table below shows Binary and

Hexadecimal representations for some decimal numbers.

Example: Evaluate the 16-bit binary representation of decimal number10710

, then evaluate its

hexadecimal representation

Solution:

10710

= 011010112

= 6B H

MP 5

Computer languages: -

low- level language:-

Machine language: -

Is the set of instructions designed into the machine makes up its machine language, a binary

language, composed of 0’s and 1’s, that is specific to each computer.

EX:-

0011 1100 :-

is an instruction that increments the number in the register called

the accumulator by one.

1000 0000 :-

is an instruction that adds the number in the register called B to the

number in the accumulator and keeps the sum in the accumulator.

Since it is difficult and tedious for people to recognize and write instruction in binary language,

for convenience, these instructions are written in hexadecimal (or octal) code and entered in a

single-board microcomputer by using Hex keys.

EX:-

The instruction hexadecimal equivalent

0011 1100 3C

1000 0000 80

Assembly language: -

Even though the instructions can be written in hexadecimal codes, it is still difficult to

understand a program written in hexadecimal numbers. Therefore, each manufacture of mp

has devised a symbolic code for each instruction, called a mnemonic, which consists of letters

to suggest the operation to be performed by that instruction.

EX: -

0011 1100 (3C H) is represented by the

mnemonic INR A

1000 0000 (80 H) is represented as ADD B

MP 6

-The machine language and assembly language are specific to each mp, and both are

considered Low-level language.

- The machine language is in binary and the assembly language is English-like words, the

mp understands only the binary. Then, how do the assembly language mnemonics get

translated into binary code?

The translation is performed either manually called hand assembly, or by a program called an

assembler.

Assembler: - A computer program that translates an assembly language program from

mnemonics to the binary machine code of a computer.

-high- level language:-

Programming languages that are machine independent. Like Fortran, Basic and Pascal.

Instructions written in this language are known as statements rather than mnemonics.

The Compiler and interpreter accept the English-like statements as their input called the

(source code), they translate the source code into the machine language compatible with the

mp being used in the system. This translation is called the (object code)

Fig-a- translation of high-level language program into machine code.

The difference between the compiler and the interpreter lies in the process of generating the

object code.

a- The compiler reads the entire program and then generates the object code

The compilers are generally used in languages such as Fortran, Pascal.

b- The interpreter reads one instruction at a time, produce its object code, and

executes the instruction before reading the next instruction

An interpreter used for the Basic language.

MP 7

Microprocessor architecture and its operation: -

The mp is a programmable logic device, designed with registers, flip-flops, and timing

elements. The mp has a set of instructions designed internally.

The mp performs primarily four operations: -

1- Memory read: read data from memory

2- Memory write: write data into memory

3- I/O read: accepts data from input device

4- I/O write: sends data to output device

All these operation are part of the communication process between the mp and peripheral

devices (including memory).

To communicate with a peripheral or memory location the mp needs to perform the following

steps: -

1- Identify the peripheral or the memory location (with it address)

2- Transfer data

3- Provide timing signals

The mp performs these function using three sets of comm. line called buses: -

The address bus, the data bus and control bus.

Address bus: - a group of lines that are used to send a memory address or device

address from the mp to the memory location or the peripheral.

Data bus: - a group of bi-directional lines which are used to transfer data between the

mp and peripherals or memory

The data bus determines the word length and the register size of the mp.

control bus: - single lines that are generated by the mp to provide controlling of various

operations.
To read an instruction from a memory location. The mp places the address on the address bus.

The address on the bus is decoded and the memory is identified. The mp sends a pulse called

memory read as the control signal. The pulse activates the memory chip and the contents of

the memory location are placed on the data bus and brought inside the mp.

Software Model of 8088/8086 microprocessor

Intel 8086 microprocessor is the enhanced version of Intel 8085 microprocessor. It was
designed by Intel in 1976.

The 8086 microprocessor is a16-bit, N-channel, HMOS microprocessor. Where the HMOS is
used for "High-speed Metal Oxide Semiconductor".

Intel 8086 is built on a single semiconductor chip and packaged in a 40-pin IC package. The type
of package is DIP (Dual Inline Package).

Intel 8086 uses 20 address lines and 16 data- lines. It can directly address up to 220 = 1 Mbyte
of memory.

It consists of a powerful instruction set, which provides operation like division and
multiplication very quickly.

8086 is designed to operate in two modes, i.e., Minimum and Maximum mode.

Difference between 8085 and 8086 Microprocessor

8085 Microprocessor 8086 Microprocessor

It is an 8-bit microprocessor. It is a 16-bit microprocessor.

It has a 16-bit address line. It has a 20-bit address line.

It has a 8-bit data bus. It has a 16-bit data bus.

The memory capacity is 64 KB. The memory capacity is 1 MB.

The Clock speed of this microprocessor is 3 MHz. The Clock speed of this microprocessor
varies between 5, 8 and 10 MHz for different versions.

It has five flags. It has nine flags.

8085 microprocessor does not support memory segmentation. 8086 microprocessor

supports memory segmentation.

It does not support pipelining. It supports pipelining.

It is accumulator based processor. It is general purpose register based

processor.

It has no minimum or maximum mode. It has minimum and maximum modes.

In 8085, only one processor is used. In 8086, more than one processor is used. An
additional external processor can also be employed.

It contains less number of transistors compare to 8086 microprocessor. It contains about 6500
transistor. It contains more number of transistors compare to 8085 microprocessor. It
contains about 29000 in size.

The cost of 8085 is low. The cost of 8086 is high.

8086 pins configuration

8086 Microprocessor

The description of the pins of 8086 is as follows:

AD0-AD15 (Address Data Bus): Bidirectional address/data lines. These are low order address
bus. They are multiplexed with data.

When these lines are used to transmit memory address, the symbol A is used instead of AD, for
example, A0- A15.

A16 - A19 (Output): High order address lines. These are multiplexed with status signals.

A16/S3, A17/S4: A16 and A17 are multiplexed with segment identifier signals S3 and S4.

A18/S5: A18 is multiplexed with interrupt status S5.

A19/S6: A19 is multiplexed with status signal S6.

BHE/S7 (Output): Bus High Enable/Status. During T1, it is low. It enables the data onto the most
significant half of data bus, D8-D15. 8-bit device connected to upper half of the data bus use
BHE signal. It is multiplexed with status signal S7. S7 signal is available during T3 and T4.

RD (Read): For read operation. It is an output signal. It is active when LOW.

Ready (Input): The addressed memory or I/O sends acknowledgment through this pin. When
HIGH, it denotes that the peripheral is ready to transfer data.

RESET (Input): System reset. The signal is active HIGH.

CLK (input): Clock 5, 8 or 10 MHz.

INTR: Interrupt Request.

NMI (Input): Non-maskable interrupt request.

TEST (Input): Wait for test control. When LOW the microprocessor continues execution
otherwise waits.

VCC: Power supply +5V dc.

GND: Ground.

Operating Modes of 8086

There are two operating modes of operation for Intel 8086, namely the minimum mode and the
maximum mode.

When only one 8086 CPU is to be used in a microprocessor system, the 8086 is used in the
Minimum mode of operation.
In a multiprocessor system 8086 operates in the Maximum mode.

Pin Description for Minimum Mode

In this minimum mode of operation, the pin MN/MX is connected to 5V D.C. supply i.e. MN/MX
= VCC.

The description about the pins from 24 to 31 for the minimum mode is as follows:

INTA (Output): Pin number 24 interrupts acknowledgement. On receiving interrupt signal, the
processor issues an interrupt acknowledgment signal. It is active LOW.

ALE (Output): Pin no. 25. Address latch enable. It goes HIGH during T1. The microprocessor
8086 sends this signal to latch the address into the Intel 8282/8283 latch.

DEN (Output): Pin no. 26. Data Enable. When Intel 8287/8286 octal bus transceiver is used this
signal. It is active LOW.

DT/R (output): Pin No. 27 data Transmit/Receives. When Intel 8287/8286 octal bus transceiver
is used this signal controls the direction of data flow through the transceiver. When it is HIGH,
data is sent out. When it is LOW, data is received.

M/IO (Output): Pin no. 28, Memory or I/O access. When this signal is HIGH, the CPU wants to
access memory. When this signal is LOW, the CPU wants to access I/O device.

WR (Output): Pin no. 29, Write. When this signal is LOW, the CPU performs memory or I/O
write operation.
HLDA (Output): Pin no. 30, Hold Acknowledgment. It is sent by the processor when it receives
HOLD signal. It is active HIGH signal. When HOLD is removed HLDA goes LOW.

HOLD (Input): Pin no. 31, Hold. When another device in microcomputer system wants to use
the address and data bus, it sends HOLD request to CPU through this pin. It is an active HIGH
signal.

Pin Description for Maximum Mode

In the maximum mode of operation, the pin MN/¯MX is made LOW. It is grounded. The
description about the pins from 24 to 31 is as follows:

QS1, QS0 (Output): Pin numbers 24, 25, Instruction Queue Status. Logics are given below:

QS1 QS0 Operation

0 0 No operation

0 1 1st byte of opcode from queue.

1 0 Empty the queue

1 1 Subsequent byte from queue

S0, S1, S2 (Output): Pin numbers 26, 27, 28 Status Signals. These signals are connected to the
bus controller of Intel 8288. This bus controller generates memory and I/O access control
signals. Logics for status signal are given below:

S2 S1 S0 Operation

0 0 0 Interrupt acknowledgement

0 0 1 Read data from I/O port

0 1 0 Write data from I/O port

0 1 1 Halt

1 0 0 Opcode fetch

1 0 1 Memory read

1 1 0 Memory write

1 1 1 Passive state

LOCK (Output): Pin no. 29. It is an active LOW signal. When this signal is LOW, all interrupts are
masked and no HOLD request is granted. In a multiprocessor system all other processors are
informed through this signal that they should not ask the CPU for relinquishing the bus control.

RG/GT1, RQ/GT0 (Bidirectional): Pin numbers 30, 31, Local Bus Priority Control. Other
processors ask the CPU by these lines to release the local bus.

In the maximum mode of operation signals WR, ALE, DEN, DT/R etc. are not available directly
from the processor. These signals are available from the controller 8288.

Functional units of 8086

8086 contains two independent functional units: a Bus Interface Unit (BIU) and an Execution
Unit (EU).

8086 Microprocessor

Fig: Block Diagram of Intel 8086 Microprocessor (8086 Architecture)

Bus Interface Unit (BIU)

The segment registers, instruction pointer and 6-byte instruction queue are associated with the
bus interface unit (BIU).

The BIU:
Handles transfer of data and addresses,

Fetches instruction codes, stores fetched instruction codes in first-in-first-out register set called
a queue,

Reads data from memory and I/O devices,

Writes data to memory and I/O devices,

It relocates addresses of operands since it gets un-relocated operand addresses from EU. The
EU tells the BIU from where to fetch instructions or where to read data.

It has the following functional parts:

Instruction Queue: When EU executes instructions, the BIU gets 6-bytes of the next instruction
and stores them in the instruction queue and this process is known as instruction pre fetch. This
process increases the speed of the processor.

Segment Registers: A segment register contains the addresses of instructions and data in
memory which are used by the processor to access memory locations. It points to the starting
address of a memory segment currently being used.

There are 4 segment registers in 8086 as given below:

Code Segment Register (CS): Code segment of the memory holds instruction codes of a
program.

Data Segment Register (DS): The data, variables and constants given in the program are held in
the data segment of the memory.

Stack Segment Register (SS): Stack segment holds addresses and data of subroutines. It also
holds the contents of registers and memory locations given in PUSH instruction.

Extra Segment Register (ES): Extra segment holds the destination addresses of some data of
certain string instructions.

Instruction Pointer (IP): The instruction pointer in the 8086 microprocessor acts as a program
counter. It indicates to the address of the next instruction to be executed.

Execution Unit (EU)

The EU receives opcode of an instruction from the queue, decodes it and then executes it.
While Execution, unit decodes or executes an instruction, then the BIU fetches instruction
codes from the memory and stores them in the queue.

The BIU and EU operate in parallel independently. This makes processing faster.

General purpose registers, stack pointer, base pointer and index registers, ALU, flag registers
(FLAGS), instruction decoder and timing and control unit constitute execution unit (EU). Let's
discuss them:

General Purpose Registers: There are four 16-bit general purpose registers: AX (Accumulator
Register), BX (Base Register), CX (Counter) and DX. Each of these 16-bit registers are further
subdivided into 8-bit registers as shown below:

16-bit registers 8-bit high-order registers 8-bit low-order registers

AX AH AL

BX BH BL

CX CH CL

DX DH DL

Index Register: The following four registers are in the group of pointer and index registers:

Stack Pointer (SP)

Base Pointer (BP)

Source Index (SI)

Destination Index (DI)

ALU: It handles all arithmetic and logical operations. Such as addition, subtraction,
multiplication, division, AND, OR, NOT operations.

Flag Register: It is a 16?bit register which exactly behaves like a flip-flop, means it changes
states according to the result stored in the accumulator. It has 9 flags and they are divided into
2 groups i.e. conditional and control flags.

Conditional Flags: This flag represents the result of the last arithmetic or logical instruction
executed. Conditional flags are:

Carry Flag

Auxiliary Flag
Parity Flag

Zero Flag

Sign Flag

Overflow Flag

Control Flags: It controls the operations of the execution unit. Control flags are:

Trap Flag

Interrupt Flag

Direction Flag

Interrupts

Interrupt is a process of creating a temporary halt during program execution and allows
peripheral devices to access the microprocessor.

Microprocessor responds to these interrupts with an interrupt service routine (ISR), which is a
short program or subroutine to instruct the microprocessor on how to handle the interrupt.

There are different types of interrupt in 8086:

8086 Microprocessor

Hardware Interrupts

Hardware interrupts are that type of interrupt which are caused by any peripheral device by
sending a signal through a specified pin to the microprocessor.

The Intel 8086 has two hardware interrupt pins:

NMI :(Non-Maskbale Interrupt)

INTR :(Interrupt Request) Maskable Interrupt.

NMI: NMI is a single Non-Maskable Interrupt having higher priority than the maskable
interrupt.

It cannot be disabled (masked) by user using software.

It is used by the processor to handle emergency conditions.

For example: It can be used to save program and data in case of power failure. An external
electronic circuitry is used to detect power failure, and to send an interrupt signal to 8086
through NMI line.

INTR: The INTR is a maskable interrupt. It can be enabled/disabled using interrupt flag (IF). After
receiving INTR from external device, the 8086 acknowledges through INTA signal.

It executes two consecutive interrupt acknowledge bus cycles.

Software Interrupt

A microprocessor can also be interrupted by internal abnormal conditions such as overflow;

division by zero; etc. A programmer can also interrupt microprocessor by inserting INT
instruction at the desired point in the program while debugging a program. Such an interrupt is
called a software interrupt.

The interrupt caused by an internal abnormal conditions also came under the heading of
software interrupt.

Example of software interrupts are:

TYPE 0 (division by zero)

TYPE 1 (single step execution for debugging a program)

TYPE 2 represents NMI (power failure condition)

TYPE 3 (break point interrupt)

TYPE 4 (overflow interrupt)

Interrupt pointer table for 8086

8086 Microprocessor

Fig: Interrupt pointer table for 8086

The 8086 can handle up to 256, hardware and software interrupts.

1KB memory acts as a table to contain interrupt vectors (or interrupt pointers), and it is called
interrupt vector table or interrupt pointer table. The 256 interrupt pointers have been
numbered from 0 to 255 (FF hex). The number assigned to an interrupt pointer is known as
type of that interrupt. For example, Type 0, Type 1, Type 2,...........Type 255 interrupt.

Addressing modes of 8086

The way for which an operand is specified for an instruction in the accumulator, in a general
purpose register or in memory location, is called addressing mode.

The 8086 microprocessors have 8 addressing modes. Two addressing modes have been
provided for instructions which operate on register or immediate data.

These two addressing modes are:

Register Addressing: In register addressing, the operand is placed in one of the 16-bit or 8-bit
general purpose registers.

Example
MOV AX, CX

ADD AL, BL

ADD CX, DX

Immediate Addressing: In immediate addressing, the operand is specified in the instruction

itself.

Example

MOV AL, 35H

MOV BX, 0301H

MOV [0401], 3598H

ADD AX, 4836H

The remaining 6 addressing modes specify the location of an operand which is placed in a
memory.

These 6 addressing modes are:

Direct Addressing: In direct addressing mode, the operand?s offset is given in the instruction as
an 8-bit or 16-bit displacement element.

Example

ADD AL, [0301]

The instruction adds the content of the offset address 0301 to AL. the operand is placed at the
given offset (0301) within the data segment DS.
Register Indirect Addressing: The operand's offset is placed in any one of the registers BX, BP, SI
or DI as specified in the instruction.

Example

MOV AX, [BX]

It moves the contents of memory locations addressed by the register BX to the register AX.

Based Addressing: The operand's offset is the sum of an 8-bit or 16-bit displacement and the
contents of the base register BX or BP. BX is used as base register for data segment, and the BP
is used as a base register for stack segment.

Effective address (Offset) = [BX + 8-bit or 16-bit displacement].

Example

MOV AL, [BX+05]; an example of 8-bit displacement.

MOV AL, [BX + 1346H]; example of 16-bit displacement.

Indexed Addressing: The offset of an operand is the sum of the content of an index register SI
or DI and an 8-bit or 16-bit displacement.

Offset (Effective Address) = [SI or DI + 8-bit or 16-bit displacement]

Example

MOV AX, [SI + 05]; 8-bit displacement.

MOV AX, [SI + 1528H]; 16-bit displacement.

Based Indexed Addressing: The offset of operand is the sum of the content of a base register BX
or BP and an index register SI or DI.

Effective Address (Offset) = [BX or BP] + [SI or DI]

Here, BX is used for a base register for data segment, and BP is used as a base register for stack
segment.

Example

ADD AX, [BX + SI]

MOV CX, [BX + SI]

Based Indexed with Displacement: In this mode of addressing, the operand's offset is given by:

Effective Address (Offset) = [BX or BP] + [SI or DI] + 8-bit or 16-bit displacement

Example

MOV AX, [BX + SI + 05]; 8-bit displacement

MOV AX, [BX + SI + 1235H]; 16-bit displacement

Instruction Set of 8086

Instructions are classified on the basis of functions they perform. They are categorized into the
following main types:

Data Transfer instruction

All the instructions which perform data movement come under this category. The source data
may be a register, memory location, port etc. the destination may be a register, memory
location or port. The following instructions come under this category:

Instruction Description

MOV: Moves data from register to register, register to memory, memory to register, memory to
accumulator, accumulator to memory, etc.

LDS: Loads a word from the specified memory locations into specified register. It also loads a
word from the next two memory locations into DS register.

LES: Loads a word from the specified memory locations into the specified register. It also
loads a word from next two memory locations into ES register.

LEA: Loads offset address into the specified register.

LAHF: Loads low order 8-bits of the flag register into AH register.

SAHF: Stores the content of AH register into low order bits of the flags register.

XLAT/XLATB: Reads a byte from the lookup table.

XCHG: Exchanges the contents of the 16-bit or 8-bit specified register with the contents of AX
register, specified register or memory locations.

PUSH :Pushes (sends, writes or moves) the content of a specified register or memory
location(s) onto the top of the stack.

POP Pops: (reads) two bytes from the top of the stack and keeps them in a specified register,
or memory location(s).

POPF: Pops (reads) two bytes from the top of the stack and keeps them in the flag register.

IN: Transfers data from a port to the accumulator or AX, DX or AL register.

OUT: Transfers data from accumulator or AL or AX register to an I/O port identified by the
second byte of the instruction.

Arithmetic Instructions

Instructions of this group perform addition, subtraction, multiplication, division, increment,

decrement, comparison, ASCII and decimal adjustment etc.
The following instructions come under this category:

Instruction Description

ADD: Adds data to the accumulator i.e. AL or AX register or memory locations.

ADC: Adds specified operands and the carry status (i.e. carry of the previous stage).

SUB : Subtract immediate data from accumulator, memory or register.

SBB : Subtract immediate data with borrow from accumulator, memory or register.

MUL: Unsigned 8-bit or 16-bit multiplication.

IMUL: Signed 8-bit or 16-bit multiplication.

DIV : Unsigned 8-bit or 16-bit division.

IDIV : Signed 8-bit or 16-bit division.

INC : Increment Register or memory by 1.

DEC : Decrement register or memory by 1.

DAA :Decimal Adjust after BCD Addition: When two BCD numbers are added, the DAA is used
after ADD or ADC instruction to get correct answer in BCD.

DAS : Decimal Adjust after BCD Subtraction: When two BCD numbers are added, the DAS is
used after SUB or SBB instruction to get correct answer in BCD.

AAA: ASCII Adjust for Addition: When ASCII codes of two decimal digits are added, the AAA is
used after addition to get correct answer in unpacked BCD.

AAD: Adjust AX Register for Division: It converts two unpacked BCD digits in AX to the
equivalent binary number. This adjustment is done before dividing two unpacked BCD digits in
AX by an unpacked BCD byte.

AAM: Adjust result of BCD Multiplication: This instruction is used after the multiplication of
two unpacked BCD.

AAS ASCII Adjust for Subtraction: This instruction is used to get the correct result in
unpacked BCD after the subtraction of the ASCII code of a number from ASCII code another
number.
CBW :Convert signed Byte to signed Word.

CWD :Convert signed Word to signed Doubleword.

NEG :Obtains 2's complement (i.e. negative) of the content of an 8-bit or 16-bit specified
register or memory location(s).

CMP :Compare Immediate data, register or memory with accumulator, register or memory
location(s).

Logical Instructions

Instruction of this group perform logical AND, OR, XOR, NOT and TEST operations. The following
instructions come under this category:

Instruction Description

AND: Performs bit by bit logical AND operation of two operands and places the result in the
specified destination.

OR :Performs bit by bit logical OR operation of two operands and places the result in the
specified destination.

XOR :Performs bit by bit logical XOR operation of two operands and places the result in the
specified destination.

NOT :Takes one's complement of the content of a specified register or memory location(s).

TEST :Perform logical AND operation of a specified operand with another specified operand.

Rotate Instructions

The following instructions come under this category:

Instruction Description

RCL: Rotate all bits of the operand left by specified number of bits through carry flag.

RCR: Rotate all bits of the operand right by specified number of bits through carry flag.

ROL : Rotate all bits of the operand left by specified number of bits.

ROR: Rotate all bits of the operand right by specified number of bits.

Shift Instructions
The following instructions come under this category:

Instruction Description

SAL or SHL: Shifts each bit of operand left by specified number of bits and put zero in LSB
position.

SAR: Shift each bit of any operand right by specified number of bits. Copy old MSB into new
MSB.

SHR :Shift each bit of operand right by specified number of bits and put zero in MSB position.

Branch Instructions

It is also called program execution transfer instruction. Instructions of this group transfer
program execution from the normal sequence of instructions to the specified destination or
target. The following instructions come under this category:

Instruction Description

JA or JNBE: Jump if above, not below, or equal i.e. when CF and ZF = 0

JAE/JNB/JNC: Jump if above, not below, equal or no carry i.e. when CF = 0

JB/JNAE/JC : Jump if below, not above, equal or carry i.e. when CF = 0

JBE/JNA : Jump if below, not above, or equal i.e. when CF and ZF = 1

JCXZ: Jump if CX register = 0

JE/JZ: Jump if zero or equal i.e. when ZF = 1

JG/JNLE : Jump if greater, not less or equal i.e. when ZF = 0 and CF = OF

JGE/JNL : Jump if greater, not less or equal i.e. when SF = OF

JL/JNGE : Jump if less, not greater than or equal i.e. when SF ≠ OF

JLE/JNG : Jump if less, equal or not greater i.e. when ZF = 1 and SF ≠ OF

JMP : Causes the program execution to jump unconditionally to the memory address or label
given in the instruction.

CALL: Calls a procedure whose address is given in the instruction and saves their return address
to the stack.
RET : Returns program execution from a procedure (subroutine) to the next instruction or
main program.

IRET: Returns program execution from an interrupt service procedure (subroutine) to the main
program.

INT : Used to generate software interrupt at the desired point in a program.

INTO: Software interrupts to indicate overflow after arithmetic operation.

LOOP: Jump to defined label until CX = 0.

LOOPZ/LOOPE: Decrement CX register and jump if CX ≠ 0 and ZF = 1.

LOOPNZ/LOOPNE: Decrement CX register and jump if CX ≠ 0 and ZF = 0.

Here, CF = Carry Flag

ZF = Zero Flag

OF = Overflow Flag

SF = Sign Flag

CX = Register

Flag Manipulation and Processor Control Instructions

Instructions of this instruction set are related to flag manipulation and machine control. The
following instructions come under this category:

Instruction Description

CLC Clear Carry Flag: This instruction resets the carry flag CF to 0.

CLD Clear Direction Flag: This instruction resets the direction flag DF to 0.

CLI Clear Interrupt Flag: This instruction resets the interrupt flag IF to 0.

CMC This instruction take complement of carry flag CF.

STC Set carry flag CF to 1.

STD Set direction flag to 1.

STI Set interrupt flag IF to 1.

HLT Halt processing. It stops program execution.

NOP Performs no operation.

ESC Escape: makes bus free for external master like a coprocessor or peripheral device.

WAIT When WAIT instruction is executed, the processor enters an idle state in which the
processor does no processing.

LOCK It is a prefix instruction. It makes the LOCK pin low till the execution of the next
instruction.

String Instructions

String is series of bytes or series of words stored in sequential memory locations. The 8086
provides some instructions which handle string operations such as string movement,
comparison, scan, load and store.

The following instructions come under this category:

Instruction Description

MOVS/MOVSB/MOVSW: Moves 8-bit or 16-bit data from the memory location(s) addressed by
SI register to the memory location addressed by DI register.

CMPS/CMPSB/CMPSW: Compares the content of memory location addressed by DI register

with the content of memory location addressed by SI register.

SCAS/SCASB/SCASW : Compares the content of accumulator with the content of memory

location addressed by DI register in the extra segment ES.

LODS/LODSB/LODSW: Loads 8-bit or 16-bit data from memory location addressed by SI register
into AL or AX register.

STOS/STOSB/STOSW : Stores 8-bit or 16-bit data from AL or AX register in the memory location
addressed by DI register.

REP Repeats the given instruction until CX ≠ 0

REPE/ REPZ : Repeats the given instruction till CX ≠ 0 and ZF = 1

REPNE/REPNZ: Repeats the given instruction till CX ≠ 0 and ZF = 0

Memory and I/O Interfacing

Several memory chips and I/O devices are connected to a microprocessor.

The following figure shows a schematic diagram to interface memory chips and I/O devices to a
microprocessor.

Memory and I/O Interfacing

Memory Interfacing

When we are executing any instruction, the address of memory location or an I/O device is sent
out by the microprocessor. The corresponding memory chip or I/O device is selected by a
decoding circuit.

Memory requires some signals to read from and write to registers and microprocessor
transmits some signals for reading or writing data.

The interfacing process includes matching the memory requirements with the microprocessor
signals. Therefore, the interfacing circuit should be designed in such a way that it matches the
memory signal requirements with the microprocessor's signals.

I/O interfacing

As we know, keyboard and displays are used as communication channel with outside world.
Therefore, it is necessary that we interface keyboard and displays with the microprocessor. This
is called I/O interfacing. For this type of interfacing, we use latches and buffers for interfacing
the keyboards and displays with the microprocessor.

But the main drawback of this interfacing is that the microprocessor can perform only one
function.
8279 Programmable Keyboard

The Intel 8279 is a programmable keyboard interfacing device. Data input and display are the
integral part of microprocessor kits and microprocessor-based systems.

8279 has been designed for the purpose of 8-bit Intel microprocessors.

8279 has two sections namely keyboard section and display section.

The function of the keyboard section is to interface the keyboard which is used as input device
for the microprocessor. It can also interface toggle or thumb switches.

The purpose of the display section is to drive alphanumeric displays or indicator lights. It is
directly connected to the microprocessor bus.

The microprocessor is relieved from the burden of scanning the keyboard or refreshing the
display.

Some important Features are:

Simultaneous keyboard display operations

Scanned sensor mode

Scanned keyboard mode

8-character keyboard FIFO

Strobed input entry mode

2-key lock out or N-key roll over with contact debounce

Single 16-charcter display

Dual 8 or 16 numerical display

Interrupt output on key entry

Programmable scan timing and mode programmable from CPU

8257 DMA Controller

The data transfer from fast I/O devices to the memory or from the memory to I/O devices
through the accumulator is a time consuming process. For this situation, the Direct Memory
Access (DMA) technique is preferred. In DMA data transfer scheme, data is directly transferred
from an I/O device to RAM or from RAM to an I/O device.

Using a DMA controller, the device requests the CPU to hold its address, data and control bus,
so the device is free to transfer data directly to/from the memory. The DMA data transfer is
initiated only after receiving HLDA signal from the CPU.

How DMA operations are performed?

Following are the operations performed by a DMA:

Initially, the device has to send DMA request (DRQ) to DMA controller for sending the data
between the device and the memory.

The DMA controller sends Hold request (HRQ) to the CPU and waits for the CPU for the HLDA.

When CPU gets the HLDA signal then, it leaves the control over the bus and acknowledges the
HOLD request through HLDA signal.

Now the CPU is in the HOLD state and the DMA controller has to manage the operations over
the buses between the CPU, memory and I/O devices.

Intel 8257

The Intel 8257 is a programmable DMA controller.

It is a 4-channel programmable Direct Memory Access (DMA) controller.

It is a 40 pin I.C. package and requires +5V supply for its operation.
It can perform three operations, namely read, write, and verify.

Each channel incorporates two 16-bit registers, namely DMA address register and byte count
register.

Each channel can transfer data up to 64kb and can be programmed independently.

It operates in 2 -modes: Master mode and Slave mode.

8257 Architecture

The following diagram is the architecture of Intel 8257:

Memory and I/O Interfacing

8257 Pin Description

Memory and I/O Interfacing

DRQ0 - DRQ3: These are DMA request lines. An I/O device sends the DMA request on one of
these lines. On the line, a HIGH status generates a DMA request.

DACK0 - DACK3: These are DMA acknowledge lines. The Intel 8257 sends an acknowledge signal
through one of these lines informing an I/O device that it has been selected for DMA data
transfer. On the line, a LOW acknowledges the I/O device.

A0 - A7: These are address lines. A0 - A3 are bidirectional lines. These lines carry 4 LSBs of 16-bit
memory address generated by the 8257 in the master mode. In the slave mode, these lines are
all the input lines. The inputs select one from the registers to be read or programmed. A4 - A7
lines gives tristated outputs in the master mode which carry 4 through 7 of the 16-bit memory
address generated by the Intel 8257.

D0 - D7: These are data lines. These are bidirectional three state lines. While programming the
controller the CPU sends data for the DMA address register, the byte count register and the
mode set register through these data lines.
AEN: Address latch enable.

ADSTB: A HIGH on this line latches the 8MSBs of the address, which are sent on D-bus, into Intel
8212 connected for this purpose.

CS: It is chip select.

(I/OR): I/O read. It is a bidirectional line. In output mode it is used to access data from the I/O
device during the DMA write cycle.

(I/OW): I/O write. It is a bidirectional line. In output mode it allows the transfer of data to the
I/O device during the DMA read cycle. Data is transferred from the memory.

MEMR: Memory read

MEMW: Memory write

TC: Byte count (Terminal count).

MARK: Modulo 128 Mark.

CLK: Clock

HRQ: Hold request

HLDA: Hold acknowledge

Memory Organization in the 8086 Microprocessor

In this tutorial, we will learn about how the memory is organized inside the 8086
Microprocessor? We will also learn that how the 8086 microprocessor is capable of handling up
to 16 bits of data at a time even though each memory location in it is byte-addressable.

By Monika Sharma Last updated : May 15, 2023

There are 20 address lines in the 8086 microprocessor. This gives us 220 different memory
locations. Hence the total size is 220 Bytes (as each memory location is Byte Addressable, i.e.
one byte of data can be stored at every single location), which is equal to 1MB.

Even the memory is byte-addressable, yet the 8086 microprocessor an easily handle up to 16
bits of data at a time through its 16 data lines. So, to organize the memory efficiently, the entire
memory in 8086 is divided into two memory banks: odd bank and the even bank.

memory organization 8086

The way in which data is read or written is decided by the value of BHE, and the last address bit,
that is the A0 line. It is done in the following way:

BHE' A0 Operation performed on memory

0 0 16 bits of data will be read or written into the memory

0 1 8 bits of data will be read/written into the odd memory bank

1 0 8 bits of data will be read/written into the even memory bank

1 1 No operation is performed

To read or write 8 bits of data, it would require only 1 CPU cycle, no matter the data is stored in
any of the memory banks, but to read or write 16 bits of data, the BIU of the 8086 may require
either 1 or 2 memory cycles depending upon whether the lower byte of word is located at even
or odd memory address.

If the lower byte of the word is stored at even memory bank and the upper byte is stored at
odd memory bank then the CPU will require only 1 memory cycle. So, it is better to store data
in this way.

If the lower byte of the word is located at an odd memory address, then the CPU will require 2
memory cycles. The first memory cycle is required for accessing the lower byte of the word
through the higher data bus, i.e. D15 to D8, and the second memory cycle is required for
accessing the upper byte of the word through the lower data bus, i.e. D7 to D0.

Memory Segmentation in 8086 Microprocessor

Last Updated : 18 Oct, 2019

Prerequisite – Segmentation

Segmentation is the process in which the main memory of the computer is logically divided into
different segments and each segment has its own base address. It is basically used to enhance
the speed of execution of the computer system, so that the processor is able to fetch and
execute the data from the memory easily and fast.

Need for Segmentation –

The Bus Interface Unit (BIU) contains four 16 bit special purpose registers (mentioned below)
called as Segment Registers.

Code segment register (CS): is used for addressing memory location in the code segment of the
memory, where the executable program is stored.

Data segment register (DS): points to the data segment of the memory where the data is
stored.

Extra Segment Register (ES): also refers to a segment in the memory which is another data
segment in the memory.
Stack Segment Register (SS): is used for addressing stack segment of the memory. The stack
segment is that segment of memory which is used to store stack data.

The number of address lines in 8086 is 20, 8086 BIU will send 20bit address, so as to access one
of the 1MB memory locations. The four segment registers actually contain the upper 16 bits of
the starting addresses of the four memory segments of 64 KB each with which the 8086 is
working at that instant of time. A segment is a logical unit of memory that may be up to 64
kilobytes long. Each segment is made up of contiguous memory locations. It is an independent,
separately addressable unit. Starting address will always be changing. It will not be fixed.

Note that the 8086 does not work the whole 1MB memory at any given time. However, it works
only with four 64KB segments within the whole 1MB memory.

Below is the one way of positioning four 64 kilobyte segments within the 1M byte memory
space of an 8086.

Types Of Segmentation –
Overlapping Segment – A segment starts at a particular address and its maximum size can go up
to 64kilobytes. But if another segment starts along with this 64kilobytes location of the first
segment, then the two are said to be Overlapping Segment.

Non-Overlapped Segment – A segment starts at a particular address and its maximum size can
go up to 64kilobytes. But if another segment starts before this 64kilobytes location of the first
segment, then the two segments are said to be Non-Overlapped Segment.

Rules of Segmentation Segmentation process follows some rules as follows:

The starting address of a segment should be such that it can be evenly divided by 16.

Minimum size of a segment can be 16 bytes and the maximum can be 64 kB.

Advantages of the Segmentation The main advantages of segmentation are as follows:

It provides a powerful memory management mechanism.

Data related or stack related operations can be performed in different segments.

Code related operation can be done in separate code segments.

It allows to processes to easily share data.

It allows to extend the address ability of the processor, i.e. segmentation allows the use of 16
bit registers to give an addressing capability of 1 Megabytes. Without segmentation, it would
require 20 bit registers.

It is possible to enhance the memory size of code data or stack segments beyond 64 KB by
allotting more than one segment for each area.

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Faculty of Engineering and Technology

University of Lucknow

Er. Priyanka Singh

B.Tech –IV Sem

Fundamentals of Microprocessor (EC-403)

8086(Machine Language Instruction Formats)

•A machine language instruction format has one or more number of fields associated

with it.

•The first field is called as operation code field or op-code field, which indicates the

type of operation to be performed by the CPU

•The instruction format also contains other fields known as operand fields

•The CPU executes the instruction using the information which reside in these fields

•There are six general formats of instructions in 8086 instruction set.

•The length of an instruction may vary from 1 byte to 6 bytes. The instruction formats

are described as follows

1 One Byte Instruction:

•This format is only one byte long and may have the implied data or register operands.

•The least significant 3-bits of the opcode are used for specifying the register operand, if

any.

•Otherwise, all the 8 bits form an opcode and the operands are implied

2 Register to Register:

•This format is 2 bytes long

•The first byte of the code specifies the operation code and width of the operand

specified by ‘w’ bit.

•The second byte of the code shows the register operands and R/M field, as shown

below.

•The register represented by the REG field is one of the operands.

•The R/M field specifies another register or memory location i.e. the other operand.

3 Register to/from memory with no displacement:

•This format is also 2 bytes long and similar to the Register to Register format except

for the MOD field as shown.

•The MOD field shows the mode of addressing. The MOD, R/M, REG and the ‘W’

fields are decided in Table 2.2.

4 Register to/from Memory with Displacement:

•This type of instruction format contains 1 or 2 additional bytes for displacement along

with 2 byte format of the register to/from memory without displacement. The format is

as shown below.

5 Immediate Operand to Register:

•In this format, the first byte as well as the 3-bits from the second byte which are used

for REG field in case of register to register format are used for opcode.

•It also contains one or two bytes of immediate data. The complete instruction format is

as shown below.

6 Immediate Operand to Memory with 16-bit displacement:

•This type of instruction format requires 5 or 6 bytes for coding.

•The first 2 bytes contain the information regarding OPCODE, MOD and R/M fields.

The remaining 4 bytes contain 2 bytes of displacement and 2 bytes of data as shown.