PIC16(L)F1704/8

14/20-Pin 8-Bit Advanced Analog Flash Microcontrollers

High-Performance RISC CPU Special Microcontroller Features

• C Compiler Optimized Architecture • Operating Voltage Range:
• Only 49 Instructions - 1.8V-3.6V (PIC16LF1704/8)
• Up to 14 Kbytes Linear Program Memory - 2.3V-5.5V (PIC16F1704/8)
Addressing • Temperature Range:
• Operating Speed: - Industrial: -40°C to 85°C
- DC – 32 MHz - Extended: -40°C to 125°C
- DC – 125 ns instruction cycle • Power-on Reset (POR)
• Interrupt Capability with Automatic Context • Low Power Brown-Out Reset (LPBOR)
Saving • Extended Watch-Dog Timer (WDT):
• 16-Level Deep Hardware Stack with Optional - Programmable period from 1 ms to 256s
Overflow/Underflow Reset • Programmable Code Protection
• Direct, Indirect and Relative Addressing modes: • In-Circuit Serial Programming™ (ICSP™) via
- Two full 16-bit File Select Registers (FSRs) Two Pins
- FSRs can read program and data memory • In-Circuit Debug (ICD) via Two Pins
• High-Endurance Flash Data Memory (HEF) • Enhanced Low-Voltage Programming (LVP)
- 128 bytes of nonvolatile data storage • Power-Saving Sleep mode
- 100k erase/write cycles
Digital Peripheral Features
Flexible Oscillator Structure • Up to 17 I/O Pins and one Input-only Pin:
• 16 MHz Internal Oscillator Block: - High current sink/source for LED drivers
- Accurate to ±1%, typical - Individually programmable weak pull-ups
- Software selectable frequency range from - Interrupt-on-change pin option with edge
16 MHz to 250 kHz selectable option
- PLL multiplier to 32 MHz • Timer0: 8-Bit Timer/Counter with 8-Bit
• 31 kHz Low-Power Internal Oscillator Programmable Prescaler
• External Oscillator Block with: • Enhanced Timer1:
- Three crystal/resonator modes up to 20 MHz - 16-bit timer/counter with prescaler
- Three external clock modes up to 20 MHz - External Gate Input mode
• Fail-Safe Clock Monitor: - Dedicated low-power 32 kHz oscillator driver
- Allows for safe shutdown if peripheral clock • Timer2:
stops - Up to three (TMR2/4/6)
• Two-Speed Oscillator Start-up - 8-Bit Timer/Counter
• Oscillator Start-up Timer (OST) - 8-Bit Period Register
- Prescaler and Postscaler
eXtreme Low-Power (XLP) Features • Capture, Compare, PWM (CCP) Module
• Master Synchronous Serial Port (SSP) with SPI
• Sleep mode: 50 nA @ 1.8V, typical and I2C with:
• Watchdog Timer: 500 nA @ 1.8V, typical - 7-bit address masking
• Secondary Oscillator: 500 nA @ 32 kHz - SMBus/PMBusTM compatibility
• Operating Current: • Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART):
- 8 µA @ 32 kHz, 1.8V, typical
- RS-232, RS-485 and LIN compatible
- 32 µA/MHz @ 1.8V, typical - Auto-Baud Detect
- Auto-wake-up on Start

 2013-2015 Microchip Technology Inc. DS40001715D-page 1

PIC16(L)F1704/8
Digital Peripheral Features (Continued) Analog Peripheral Features
• Complementary Output Generator (COG): • Operational Amplifiers:
- Push-Pull, Full Bridge, and Steering modes - Up to two configurable op amps
- Dedicated Rise/Fall Input Triggers - Selectable internal and external channels
- Dedicated Deadtime Delay Counters - High/Low selectable Gain Bandwidth Product
- Dedicated Phase Delay Counters • Two High-Speed Comparators:
- Dedicated Blanking Delay Counters - 60 ns response time
- Concurrent Auto-Shutdown Selection - Low-power/High-power mode
• Two Pulse Width Modulation (PWM) modules: - Comparator outputs externally accessible
- 10-bit Duty-Cycle Control - Software hysteresis enable
• Three Configurable Logic Cell (CLC) modules: • Analog-to-Digital Converter (ADC) module
- Generate a selected function of up to four - 10-bit resolution, 12 channels
inputs - Auto conversion start capability
- Combinational and State Logic - Conversion available during Sleep
- External or Internal input/output pins • 8-Bit Digital-to-Analog Converter (DAC):
- Operation in Sleep - Output available externally
• Peripheral Pin Select (PPS): - Positive and negative reference selection
- Digital outputs mapped to any GPIO pin - Internal connections to comparators,
- Digital inputs from any GPIO pin op amps, Fixed Voltage Reference (FVR)
- CLC input multiplexing and ADC
• Zero-Cross Detection Circuit:
- Constant Voltage Output
- Current Source/Sink
- Interrupt on Edge Detect
• Voltage Reference module:
- Fixed Voltage Reference (FVR) with 1.024V,
2.048V and 4.096V output levels

PIC16(L)F170x Family Types

Program Memory
Data Sheet Index

High-Endurance

10-bit ADC (ch)

MSSP (I2C/SPI)
Flash (words)

Comparators
Flash (bytes)

High-Speed/
Data SRAM

Zero Cross
8-bit DAC

Debug(1)
EUSART
(8/16-bit)
Op Amp
(bytes)

Timers
I/O’s(2)

PWM

COG
CCP

CLC

PPS

XLP
Device

PIC16(L)F1703 (3) 2048 256 128 12 8 0 0 2 1 2/1 2 0 0 0 1 0 Y I/E Y

PIC16(L)F1704 (1) 4096 512 128 12 8 1 2 2 1 4/1 2 2 1 1 1 3 Y I/E Y
PIC16(L)F1705 (2) 8192 1024 128 12 8 1 2 2 1 4/1 2 2 1 1 1 3 Y I/E Y
PIC16(L)F1707 (3) 2048 256 128 18 12 0 0 2 1 2/1 2 0 0 0 1 0 Y I/E Y
PIC16(L)F1708 (1) 4096 512 128 18 12 1 2 2 1 4/1 2 2 1 1 1 3 Y I/E Y
PIC16(L)F1709 (2) 8192 1024 128 18 12 1 2 2 1 4/1 2 2 1 1 1 3 Y I/E Y
Note 1: Debugging Methods: (I) – Integrated on Chip; (H) – using Debug Header; E – using Emulation Header.
2: One pin is input-only.
Data Sheet Index: (Unshaded devices are described in this document.)
1: DS40001715 PIC16(L)F1704/8 Data Sheet, 14/20-Pin Flash, 8-bit Microcontrollers.
2: DS40001729 PIC16(L)F1705/9 Data Sheet, 14/20-Pin Flash, 8-bit Microcontrollers.
3: DS40001722 PIC16(L)F1703/7 Data Sheet, 14/20-Pin Flash, 8-bit Microcontrollers

Note: For other small form-factor package availability and marking information, please visit
http://www.microchip.com/packaging or contact your local sales office.

DS40001715D-page 2  2013-2015 Microchip Technology Inc.

 PIC16(L)F1704/8
PIN DIAGRAMS

FIGURE 1: 14-PIN PDIP, SOIC, TSSOP DIAGRAM FOR PIC16(L)F1704

VDD 1 14 VSS
RA5 2 13 RA0/ICSPDAT

PIC16(L)F1704
RA4 3 12 RA1/ICSPCLK
VPP/MCLR/RA3 4 11 RA2
RC5 5 10 RC0
RC4 6 9 RC1
RC3 7 8 RC2

Note: See Table 1 for the pin allocation table.

FIGURE 2: 16-PIN QFN VDD

VSS
NC
NC

13
16
15
14

RA5 1 12 RA0/ICSPDAT
RA4 2 11 RA1/ICSPCLK
RA3/MCLR/VPP 3 PIC16(L)F1704 10 RA2
RC5 4 9 RC0
5
6
7
8
RC3
RC2
RC1
RC4

Note: See Table 1 for the pin allocation table.

 2013-2015 Microchip Technology Inc. DS40001715D-page 3

PIC16(L)F1704/8
FIGURE 3: 20-PIN PDIP, SOIC,SSOP

VDD 1 20 VSS
RA5 2 19 ICSPDAT/RA0
RA4 3 18 ICSPCLK/RA1

PIC16(L)F1708
VPP/MCLR/RA3 4 17 RA2
RC5 5 16 RC0
RC4 6 15 RC1
RC3 7 14 RC2
RC6 8 13 RB4
RC7 9 12 RB5
RB7 10 11 RB6

Note: See Table 2 for the pin allocation table.

FIGURE 4: 20-PIN QFN

RA0/ICSPDAT
RA4
RA5
VDD
VSS
19

17
20

16
18

VPP/MCLR/RA3 1 15 RA1/ICSPCLK
RC5 2 14 RA2
RC4 3 PIC16(L)F1708 13 RC0
RC3 4 12 RC1
RC6 5 11 RC2
10
6
7
8
9
RC7
RB7
RB6
RB5
RB4

Note: See Table 2 for the pin allocation table.

DS40001715D-page 4  2013-2015 Microchip Technology Inc.

 Pin Allocation Tables
 2013-2015 Microchip Technology Inc.

TABLE 1: PDIP/SOIC/SSOP 14/16-PIN ALLOCATION TABLE (PIC16(L)F1704)

Comparator

Zero Cross
Reference

EUSART

Interrupt
Op Amp

Pull-up
Timers

MSSP

Basic
PWM
I/O(2)

COG
ADC

DAC
QFN

CCP

CLC
RA0 13 12 AN0 VREF- C1IN+ — DAC1OUT1 — — — — — — — — IOC Y ICSPDAT
RA1 12 11 AN1 VREF+ C1IN0- — — — — — — — — — — IOC Y ICSPCLK
C2IN0-
RA2 11 10 AN2 — — — DAC1OUT2 ZCD T0CKI(1) — — COGIN(1) — — — INT(1) Y —
IOC
RA3 4 3 — — — — — — — — — — — — — IOC Y MCLR
VPP
RA4 3 2 AN3 — — — — — T1G(1) — — — — — — IOC Y CLKOUT
SOSCO OSC2
RA5 2 1 — — — — — — T1CKI(1) — — — — — CLCIN3(1) IOC Y CLKIN
SOSCI OSC1
RC0 10 9 AN4 — C2IN+ OPA1IN+ — — — — — — SCK(1) — — IOC Y —
SCL(3)
RC1 9 8 AN5 — C1IN1- OPA1IN- — — — — — — SDI(1) — CLCIN2(1) IOC Y —
C2IN1- SDA(3)
RC2 8 7 AN6 — C1IN2- OPA1OUT — — — — — — — — — IOC Y —
C2IN2-
RC3 7 6 AN7 — C1IN3- OPA2OUT — — — CCP2(1) — — SS(1) — CLCIN0(1) IOC Y —
C2IN3-
RC4 6 5 — — — OPA2IN- — — — — — — — CK(1) CLCIN1(1) IOC Y —

PIC16(L)F1704/8
RC5 5 4 — — — OPA2IN+ — — — CCP1(1) — — — RX(1,3) — IOC Y —
VDD 1 16 — — — — — — — — — — — — — — — VDD
VSS 14 13 — — — — — — — — — — — — — — — VSS
— — — — C1OUT — — — — CPP1 PWM3OUT COGA SDA(3) CK CLC1OUT — — —
— — — — C2OUT — — — — CPP2 PWM4OUT COGB SCL(3) DT(3) CLC2OUT — — —
OUT(2)
— — — — — — — — — — — COGC SDO TX CLC3OUT — — —
— — — — — — — — — — — COGD SCK — — — — —
DS40001715D-page 5

Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 12-1.
2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. See Register 12-3.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
 TABLE 2: 20-PIN ALLOCATION TABLE (PIC16(L)F1708)
DS40001715D-page 6

PIC16(L)F1704/8
Comparator
PDIP/SOIC/

Zero Cross
Reference

EUSART

Interrupt
Op Amp

Pull-up
Timers

MSSP
SSOP

Basic
PWM
I/O(2)

COG
ADC

DAC
QFN

CCP

CLC
RA0 19 16 AN0 VREF- C1IN+ — DAC1OUT1 — — — — — — — — IOC Y ICSPDAT
RA1 18 15 AN1 VREF+ C1IN0- — — — — — — — — — — IOC Y ICSPCLK
C2IN0-
RA2 17 14 AN2 — — — DAC1OUT2 ZCD T0CKI(1) — — COGIN(1) — — — INT(1) Y —
IOC
RA3 4 1 — — — — — — — — — — — — — IOC Y MCLR
VPP
RA4 3 20 AN3 — — — — — T1G(1) — — — — — — IOC Y CLKOUT
SOSCO OSC2
RA5 2 19 — — — — — — T1CKI — — — — — CLCIN3(1) IOC Y CLKIN
SOSCI OSC1
RB4 13 10 AN10 — — OPA1IN- — — — — — — SDI(1) — — IOC Y —
SDA(3)
RB5 12 9 AN11 — — OPA1IN+ — — — — — — — RX(1,3) IOC Y —
RB6 11 8 — — — — — — — — — — SCK(1) — — IOC Y —
SCL(3)
RB7 10 7 — — — — — — — — — — — CK(1) — IOC Y —
RC0 16 13 AN4 — C2IN+ — — — — — — — — — — IOC Y —
RC1 15 12 AN5 — C1IN1- — — — — — — — — — CLCIN2(1) IOC Y —
C2IN1-
RC2 14 11 AN6 — C1IN2- OPA1OUT — — — — — — — — — IOC Y —
C2IN2-
RC3 7 4 AN7 — C1IN3- OPA2OUT — — — CCP2(1) — — — — CLCIN0(1) IOC Y —
C2IN3-
RC4 6 3 — — — — — — — — — — — — CLCIN1(1) IOC Y —
RC5 5 2 — — — — — — — CCP1(1) — — — — — IOC Y —
 2013-2015 Microchip Technology Inc.

RC6 8 5 AN8 — — OPA2IN- — — — — — — SS(1) — — IOC Y —

RC7 9 6 AN9 — — OPA2IN+ — — — — — — — — — IOC Y —
VDD 1 18 — — — — — — — — — — — — — — — VDD
VSS 20 17 — — — — — — — — — — — — — — — VSS
— — — — C1OUT — — — — CPP1 PWM3OUT COGA SDA(3) CK CLC1OUT — — —
— — — — C2OUT — — — — CPP2 PWM4OUT COGB SCL(3) DT(3) CLC2OUT — — —
OUT(2)
— — — — — — — — — — — COGC SDO TX CLC3OUT — — —
— — — — — — — — — — — COGD SCK — — — — —
Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 12-2.
2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. See Register 12-3.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
 PIC16(L)F1704/8
Table of Contents
Device Overview ................................................................................................................................................................................... 9
Enhanced Mid-Range CPU ................................................................................................................................................................. 17
Memory Organization.......................................................................................................................................................................... 19
Device Configuration ........................................................................................................................................................................... 48
Resets ................................................................................................................................................................................................. 54
Oscillator Module (with Fail-Safe Clock Monitor) ................................................................................................................................ 62
Interrupts ............................................................................................................................................................................................. 80
Power-Down Mode (Sleep) ................................................................................................................................................................. 93
Watchdog Timer (WDT) ...................................................................................................................................................................... 97
Flash Program Memory Control ........................................................................................................................................................ 102
I/O Ports ............................................................................................................................................................................................ 118
Peripheral Pin Select (PPS) Module ................................................................................................................................................. 136
Interrupt-On-Change ......................................................................................................................................................................... 143
Fixed Voltage Reference (FVR) ....................................................................................................................................................... 149
Temperature Indicator Module .......................................................................................................................................................... 152
Comparator Module .......................................................................................................................................................................... 154
Pulse Width Modulation (PWM) ........................................................................................................................................................ 163
Complementary Output Generator (COG) Module ........................................................................................................................... 169
Configurable Logic Cell (CLC) .......................................................................................................................................................... 201
Analog-to-Digital Converter (ADC) Module ....................................................................................................................................... 217
Operational Amplifier (OPA) Modules ............................................................................................................................................... 231
8-Bit Digital-to-Analog Converter (DAC1) Module ............................................................................................................................. 234
Zero-Cross Detection (ZCD) Module ................................................................................................................................................ 238
Timer0 Module .................................................................................................................................................................................. 242
Timer1 Module with Gate Control ..................................................................................................................................................... 245
Timer2/4/6 Module ............................................................................................................................................................................ 256
Capture/Compare/PWM Modules ..................................................................................................................................................... 261
Master Synchronous Serial Port (MSSP) Module .............................................................................................................................. 268
Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ........................................................................ 324
In-Circuit Serial Programming™ (ICSP™) ........................................................................................................................................ 355
Instruction Set Summary ................................................................................................................................................................... 357
Electrical Specifications .................................................................................................................................................................... 371
DC and AC Characteristics Graphs and Charts ................................................................................................................................ 403
Development Support ....................................................................................................................................................................... 425
Packaging Information ...................................................................................................................................................................... 429
Appendix A: Data Sheet Revision History......................................................................................................................................... 448
The Microchip Web Site .................................................................................................................................................................... 449
Customer Change Notification Service ............................................................................................................................................. 449
Customer Support ............................................................................................................................................................................. 449
Product Identification System ........................................................................................................................................................... 450

 2013-2015 Microchip Technology Inc. DS40001715D-page 7

PIC16(L)F1704/8

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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).

Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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DS40001715D-page 8  2013-2015 Microchip Technology Inc.

 PIC16(L)F1704/8
1.0 DEVICE OVERVIEW
The PIC16(L)F1704/8 are described within this data
sheet. They are available in 14-pin and 20-pin DIP
packages and 16-pin and 20-pin QFN packages.
Figure 1-1 shows a block diagram of the
PIC16(L)F1704/8 devices. Table 1-2 shows the pinout
descriptions.
Reference Table 1-1 for peripherals available per device.

TABLE 1-1: DEVICE PERIPHERAL

SUMMARY

PIC16(L)F1704

PIC16(L)F1708
Peripheral

Analog-to-Digital Converter (ADC) ● ●

Digital-to-Analog Converter (DAC) ● ●
Complementary Output Generator (COG) ● ●
Fixed Voltage Reference (FVR) ● ●
Zero Cross Detection (ZCD) ● ●
Temperature Indicator ● ●
Capture/Compare/PWM (CCP/ECCP) Modules
CCP1 ● ●
CCP2 ● ●
Comparators
C1 ● ●
C2 ● ●
Configurable Logic Cell (CLC)
CLC1 ● ●
CLC2 ● ●
CLC3 ● ●
Enhanced Universal Synchronous/Asynchronous
Receiver/Transmitter (EUSART)
EUSART ● ●
Master Synchronous Serial Ports
MSSP ● ●
Op Amp
Op Amp 1 ● ●
Op Amp 2 ● ●
Pulse Width Modulator (PWM)
PWM3 ● ●
PWM4 ● ●
Timers
Timer0 ● ●
Timer1 ● ●
Timer2 ● ●

 2013-2015 Microchip Technology Inc. DS40001715D-page 9

PIC16(L)F1704/8
FIGURE 1-1: PIC16(L)F1704/8 BLOCK DIAGRAM

Program
Flash Memory
RAM PORTA

PORTB(1)
CLKOUT Timing
Generation

HFINTOSC/
CLKIN CPU PORTC
LFINTOSC
Oscillator

Figure 1-1

MCLR

ZCD

Op Amps PWM Timer0 Timer1 Timer2 MSSP Comparators

COG

Temp. ADC
FVR DAC CCPs EUSART CLCs
Indicator 10-Bit

Note 1: PIC16(L)F1708 only.

2: See applicable chapters for more information on peripherals.

DS40001715D-page 10  2013-2015 Microchip Technology Inc.

 PIC16(L)F1704/8

TABLE 1-2: PIC16(L)F1704 PINOUT DESCRIPTION

Input Output
Name Function Description
Type Type

RA0/AN0/VREF-/C1IN+/ RA0 TTL/ST CMOS General purpose I/O.

DAC1OUT/ICSPDAT
AN0 AN — ADC Channel 0 input.
VREF- AN — ADC Negative Voltage Reference input.
C1IN+ AN — Comparator C1 positive input.
DAC1OUT — AN Digital-to-Analog Converter output.
ICSPDAT ST CMOS ICSP™ Data I/O.
RA1/AN1/VREF+/C1IN0-/C2IN0-/ RA1 TTL/ST CMOS General purpose I/O.
ICSPCLK AN1 AN — ADC Channel 1 input.
VREF+ AN — ADC Voltage Reference input.
C1IN0- AN — Comparator C2 negative input.
C2IN0- AN — Comparator C3 negative input.
ICSPCLK ST — Serial Programming Clock.
RA2/AN2/DAC1OUT2/ZCD/ RA2 TTL/ST CMOS General purpose I/O.
T0CKI(1)/COGIN(1)/INT(1) AN2 AN — ADC Channel 2 input.
DAC1OUT2 — AN Digital-to-Analog Converter output.
ZCD — AN Zero Cross Detection Current Source/Sink.
T0CKI TTL/ST — Timer0 clock input.
COGIN TTL/ST — Complementary Output Generator input.
INT TTL/ST — External interrupt.
RA3/MCLR/VPP RA3 TTL/ST CMOS General purpose input.
MCLR ST — Master Clear with internal pull-up.
VPP HV — Programming voltage.
RA4/AN3/T1G(1)/SOSCO/ RA4 TTL/ST CMOS General purpose I/O.
OSC2/CLKOUT AN3 AN — ADC Channel 3 input.
T1G TTL/ST — Timer1 gate input.
SOSCO XTAL XTAL Secondary Oscillator Connection.
OSC2 — XTAL Crystal/Resonator (LP, XT, HS modes).
CLKOUT — CMOS FOSC/4 output.
RA5/T1CKI(1)/SOSCI/ RA5 TTL/ST CMOS General purpose I/O.
CLCIN3(1)/OSC1/CLKIN T1CKI TTL/ST — Timer1 clock input.
SOSCI XTAL XTAL Secondary Oscillator Connection.
CLCIN3 TTL/ST — Configurable Logic Cell source input.
OSC1 — XTAL Crystal/Resonator (LP, XT, HS modes).
CLKIN TTL/ST — External clock input (EC mode).
RC0/AN4/C2IN+/OPA1IN+/ RC0 TTL/ST — General purpose I/O.
SCK(1)/SCL(3) AN4 AN — ADC Channel 4 input.
C2IN+ AN — Comparator positive input.
OPA1IN+ AN — Operational Amplifier 1 non-inverting input.
SCK TTL/ST — SPI clock.
SCL I2C — I2C clock.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HV = High Voltage XTAL = Crystal levels
Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 12-1.
2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output
selection registers. See Register 12-3.
3: These I2C functions are bidirectional. The output pin selections must be the same as the input pin selections.

 2013-2015 Microchip Technology Inc. DS40001715D-page 11

PIC16(L)F1704/8
TABLE 1-2: PIC16(L)F1704 PINOUT DESCRIPTION (CONTINUED)
Input Output
Name Function Description
Type Type
RC1/AN5/C1IN1-/C2IN1-/ RC1 TTL/ST CMOS General purpose I/O.
OPA1IN-/SDI(1)/SDA(3)/ AN5 AN — ADC Channel 5 input.
CLCIN2(1)
C1IN1- AN — Comparator C1 negative input.
C2IN1- AN — Comparator C2 negative input.
OPA1IN- AN — Operational Amplifier 1 inverting input.
SDI CMOS — SPI data input.
SDA I2C — I2C data input.
CLCIN2 TTL/ST — Configurable Logic Cell source input.
RC2/AN6/C1IN2-/C2IN2-/ RC2 TTL/ST CMOS General purpose I/O.
OPA1OUT AN6 AN — ADC Channel 6 input.
C1IN2- AN — Comparator C1 negative input.
C2IN2- AN — Comparator C2 negative input.
OPA1OUT — AN Operational Amplifier 1 output.
RC3/AN7/C1IN3-/C2IN3-/ RC3 TTL/ST CMOS General purpose I/O.
OPA2OUT/CCP2(1)/SS(1)/ AN7 AN — ADC Channel 7 input.
CLCIN0(1)
C1IN3- AN — Comparator C1 negative input.
C2IN3- AN — Comparator C2 negative input.
OPA2OUT — AN Operational Amplifier 2 output.
CCP2 TTL/ST CMOS Capture/Compare/PWM2.
SS TTL/ST — Slave Select input.
CLCIN0 TTLST — Configurable Logic Cell source input.
RC4/OPA2IN-/CK(1)/CLCIN1(1) RC4 TTL/ST CMOS General purpose I/O.
OPA2IN- AN — Operational Amplifier 2 inverting input.
CK TTL/ST CMOS USART synchronous clock.
CLCIN1 TTL/ST — Configurable Logic Cell source input.
(1) (1)
RC5/OPA2IN+/CCP1 /RX RC5 TTL/ST CMOS General purpose I/O.
OPA2IN+ AN — Operational Amplifier 2 non-inverting input.
CCP1 TTL/ST CMOS Capture/Compare/PWM1.
RX TTL/ST — USART asynchronous input.
VDD VDD Power — Positive supply.
VSS VSS Power — Ground reference.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HV = High Voltage XTAL = Crystal levels
Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 12-1.
2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output
selection registers. See Register 12-3.
3: These I2C functions are bidirectional. The output pin selections must be the same as the input pin selections.

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 PIC16(L)F1704/8
TABLE 1-2: PIC16(L)F1704 PINOUT DESCRIPTION (CONTINUED)
Input Output
Name Function Description
Type Type
OUT(2) C1OUT — CMOS Comparator output.
C2OUT — CMOS Comparator output.
CCP1 — CMOS Capture/Compare/PWM1 output.
CCP2 — CMOS Capture/Compare/PWM2 output.
PWM3OUT — CMOS PWM3 output.
PWM4OUT — CMOS PWM4 output.
COGA — CMOS Complementary Output Generator Output A.
COGB — CMOS Complementary Output Generator Output B.
COGC — CMOS Complementary Output Generator Output C.
COGD — CMOS Complementary Output Generator Output D.
SDA(3) — OD I2C data input/output.
SDO — CMOS SPI data output.
SCK — CMOS SPI clock output.
SCL(3) — OD I2C clock output.
TX/CK — CMOS USART asynchronous TX data/synchronous clock output.
DT — CMOS USART synchronous data output.
CLC1OUT — CMOS Configurable Logic Cell 1 source output.
CLC2OUT — CMOS Configurable Logic Cell 2 source output.
CLC3OUT — CMOS Configurable Logic Cell 3 source output.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HV = High Voltage XTAL = Crystal levels
Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 12-1.
2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output
selection registers. See Register 12-3.
3: These I2C functions are bidirectional. The output pin selections must be the same as the input pin selections.

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PIC16(L)F1704/8

TABLE 1-3: PIC16(L)F1708 PIN OUT DESCRIPTION

Input Output
Name Function Description
Type Type

RA0/AN0/VREF-/C1IN+/ RA0 TTL/ST CMOS General purpose I/O.

DAC1OUT/ICSPDAT
AN0 AN — ADC Channel 0 input.
VREF- AN — ADC Negative Voltage Reference input.
C1IN+ AN — Comparator C1 positive input.
DAC1OUT — AN Digital-to-Analog Converter output.
ICSPDAT ST CMOS ICSP™ Data I/O.
RA1/AN1/VREF+/C1IN0-/C2IN0-/ RA1 TTL/ST CMOS General purpose I/O.
ICSPCLK AN1 AN — ADC Channel 1 input.
VREF+ AN — ADC Voltage Reference input.
C1IN0- AN — Comparator C2 negative input.
C2IN0- AN — Comparator C3 negative input.
ICSPCLK ST — Serial Programming Clock.
RA2/AN2/DAC1OUT2/ZCD/ RA2 TTL/ST CMOS General purpose I/O.
T0CKI(1)/COGIN(1)/INT(1) AN2 AN — ADC Channel 2 input.
DAC1OUT2 — AN Digital-to-Analog Converter output.
ZCD — AN Zero-Cross Detection Current Source/Sink.
T0CKI ST — Timer0 clock input.
COGIN ST CMOS Complementary Output Generator input.
INT ST — External interrupt.
RA3/MCLR/VPP RA3 TTL/ST CMOS General purpose I/O.
MCLR ST — Master Clear with internal pull-up.
VPP HV — Programming voltage.
RA4/AN3/T1G(1)/SOSCO/ RA4 TTL/ST CMOS General purpose I/O.
OSC2/CLKOUT AN3 AN — ADC Channel 3 input.
T1G ST — Timer1 gate input.
SOSCO XTAL XTAL Secondary Oscillator Connection.
OSC2 — XTAL Crystal/Resonator (LP, XT, HS modes).
CLKOUT — CMOS FOSC/4 output.
RA5/T1CKI/SOSCI/ RA5 TTL/ST CMOS General purpose I/O.
CLCIN3(1)/OSC1/CLKIN T1CKI ST — Timer1 clock input.
SOSCI XTAL XTAL Secondary Oscillator Connection.
CLCIN3 ST — Configurable Logic Cell source input.
OSC1 — XTAL Crystal/Resonator (LP, XT, HS modes).
CLKIN ST — External clock input (EC mode).
RB4/AN10/OPA1IN-/SCK(1)/ RB4 TTL/ST CMOS General purpose I/O.
SDA(3) AN10 AN — ADC Channel 10 input.
OPA1IN- AN — Operational Amplifier 1 inverting input.
SCK ST CMOS SPI clock.
2
SDA I C OD I2C data input/output.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HV = High Voltage XTAL = Crystal levels
Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 12-2.
2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output
selection registers. See Register 12-3.
3: These I2C functions are bidirectional. The output pin selections must be the same as the input pin selections.

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 PIC16(L)F1704/8
TABLE 1-3: PIC16(L)F1708 PIN OUT DESCRIPTION (CONTINUED)
Input Output
Name Function Description
Type Type
RB5/AN11/OPA1IN+/RX(1) RB5 TTL/ST CMOS General purpose I/O.
AN11 AN — ADC Channel 11 input.
OPA1IN+ AN — Operational Amplifier 1 non-inverting input.
RX ST — USART asynchronous input.
RB6/SDI(1)/SCL(3) RB6 TTL/ST CMOS General purpose I/O.
SDI CMOS — SPI data input.
SCL I2C OD I2C clock.
RB7/CK(1) RB7 TTL/ST CMOS General purpose I/O.
CK ST CMOS USART synchronous clock.
RC0/AN4/C2IN+ RC0 TTL/ST CMOS General purpose I/O.
AN4 AN — ADC Channel 4 input.
C2IN+ AN — Comparator positive input.
RC1/AN5/C1IN1-/C2IN1-/ RC1 TTL/ST CMOS General purpose I/O.
CLCIN2(1) AN5 AN — ADC Channel 5 input.
C1IN1- AN — Comparator C1 negative input.
C2IN1- AN — Comparator C2 negative input.
CLCIN2 ST — Configurable Logic Cell source input.
RC2/AN6/C1IN2-/C2IN2-/ RC2 TTL/ST CMOS General purpose I/O.
OPA1OUT AN6 AN — ADC Channel 6 input.
C1IN2- AN — Comparator C1 negative input.
C2IN2- AN — Comparator C2 negative input.
OPA1OUT — AN Operational Amplifier 1 output.
RC3/AN7/C1IN3-/C2IN3-/ RC3 TTL/ST CMOS General purpose I/O.
OPA2OUT/CCP2(1)/CLCIN0(1) AN7 AN — ADC Channel 7 input.
C1IN3- AN — Comparator C1 negative input.
C2IN3- AN — Comparator C2 negative input.
OPA2OUT — AN Operational Amplifier 2 output.
CCP2 ST CMOS Capture/Compare/PWM2.
CLCIN0 ST — Configurable Logic Cell source input.
(1)
RC4/CLCIN1 RC4 TTL/ST CMOS General purpose I/O.
CLCIN1 ST — Configurable Logic Cell source input.
RC5/CCP1(1) RC5 TTL/ST CMOS General purpose I/O.
CCP1 ST CMOS Capture/Compare/PWM1.
RC6/AN8/OPA2IN-/SS(1) RC6 TTL/ST CMOS General purpose I/O.
AN8 AN — ADC Channel 8 input.
OPA2IN- AN — Operational Amplifier 2 inverting input.
SS ST — Slave Select input.
RC7/AN9/OPA2IN+ RC7 TTL/ST CMOS General purpose I/O.
AN9 AN — ADC Channel 9 input.
OPA2IN+ AN — Operational Amplifier 2 non-inverting input.
VDD VDD Power — Positive supply.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HV = High Voltage XTAL = Crystal levels
Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 12-2.
2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output
selection registers. See Register 12-3.
3: These I2C functions are bidirectional. The output pin selections must be the same as the input pin selections.

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PIC16(L)F1704/8
TABLE 1-3: PIC16(L)F1708 PIN OUT DESCRIPTION (CONTINUED)
Input Output
Name Function Description
Type Type
VSS VSS Power — Ground reference.
(2)
OUT C1OUT — CMOS Comparator output.
C2OUT — CMOS Comparator output.
CCP1 — CMOS Capture/Compare/PWM1 output.
CCP2 — CMOS Capture/Compare/PWM2 output.
PWM3OUT — CMOS PWM3 output.
PWM4OUT — CMOS PWM4 output.
COGA — CMOS Complementary Output Generator Output A.
COGB — CMOS Complementary Output Generator Output B.
COGC — CMOS Complementary Output Generator Output C.
COGD — CMOS Complementary Output Generator Output D.
SDA(3) — OD I2C data input/output.
SDO — CMOS SPI data output.
SCK — CMOS SPI clock output.
SCL(3) I2C OD I2C clock output.
TX/CK — CMOS USART asynchronous TX data/synchronous clock output.
DT — CMOS USART synchronous data output.
CLC1OUT — CMOS Configurable Logic Cell 1 source output.
CLC2OUT — CMOS Configurable Logic Cell 2 source output.
CLC3OUT — CMOS Configurable Logic Cell 3 source output.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HV = High Voltage XTAL = Crystal levels
Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 12-2.
2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output
selection registers. See Register 12-3.
3: These I2C functions are bidirectional. The output pin selections must be the same as the input pin selections.

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 PIC16(L)F1704/8
2.0 ENHANCED MID-RANGE CPU Relative addressing modes are available. Two File
Select Registers (FSRs) provide the ability to read
This family of devices contain an enhanced mid-range program and data memory.
8-bit CPU core. The CPU has 49 instructions. Interrupt
• Automatic Interrupt Context Saving
capability includes automatic context saving. The
hardware stack is 16 levels deep and has Overflow and • 16-level Stack with Overflow and Underflow
Underflow Reset capability. Direct, Indirect, and • File Select Registers
• Instruction Set

FIGURE 2-1: CORE BLOCK DIAGRAM

15
Configuration 15 8
Data Bus
Program Counter
Flash
MUX

Program
Memory 16-Level
8 Level Stack
Stack
RAM
(13-bit)
(15-bit)

Program
14 Program Memory 12 RAM Addr
Bus
Read (PMR)
Addr MUX
Instruction
Instruction Reg
reg
Indirect
Direct Addr 7 Addr
5 12 12

15 BSR
FSR Reg
reg
FSR0reg
FSR Reg
FSR1 Reg
FSR reg
15 STATUS Reg
STATUS reg
8

3 MUX
Power-up
Timer
Instruction Oscillator
Decodeand
Decode & Start-up Timer
ALU
Control
OSC1/CLKIN Power-on
Reset 8
Timing Watchdog
OSC2/CLKOUT Generation Timer W reg
Brown-out
Reset

Internal
Oscillator
Block
VDD VSS

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PIC16(L)F1704/8
2.1 Automatic Interrupt Context
Saving
During interrupts, certain registers are automatically
saved in shadow registers and restored when returning
from the interrupt. This saves stack space and user
code. See Section 7.5 “Automatic Context Saving”
for more information.

2.2 16-Level Stack with Overflow and

Underflow
These devices have a hardware stack memory 15 bits
wide and 16 words deep. A Stack Overflow or
Underflow will set the appropriate bit (STKOVF or
STKUNF) in the PCON register, and if enabled, will
cause a software Reset. See Section 3.6 “Stack” for
more details.

2.3 File Select Registers

There are two 16-bit File Select Registers (FSR). FSRs
can access all file registers and program memory,
which allows one Data Pointer for all memory. When an
FSR points to program memory, there is one additional
instruction cycle in instructions using INDF to allow the
data to be fetched. General purpose memory can now
also be addressed linearly, providing the ability to
access contiguous data larger than 80 bytes. There are
also new instructions to support the FSRs. See
Section 3.7 “Indirect Addressing” for more details.

2.4 Instruction Set

There are 49 instructions for the enhanced mid-range
CPU to support the features of the CPU. See
Section 31.0 “Instruction Set Summary” for more
details.

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 PIC16(L)F1704/8
3.0 MEMORY ORGANIZATION 3.1 Program Memory Organization
These devices contain the following types of memory: The enhanced mid-range core has a 15-bit program
counter capable of addressing a 32K x 14 program
• Program Memory
memory space. Table 3-1 shows the memory sizes
- Configuration Words implemented for the PIC16(L)F1704/8 family. Accessing
- Device ID a location above these boundaries will cause a
- User ID wrap-around within the implemented memory space.
- Flash Program Memory The Reset vector is at 0000h and the interrupt vector is
• Data Memory at 0004h (see Figure 3-1).
- Core Registers
- Special Function Registers
- General Purpose RAM
- Common RAM

Note 1: The method to access Flash memory

through the PMCON registers is described
in Section 10.0 “Flash Program Memory
Control”.
The following features are associated with access and
control of program memory and data memory:
• PCL and PCLATH
• Stack
• Indirect Addressing

TABLE 3-1: DEVICE SIZES AND ADDRESSES

Program Memory Space Last Program Memory High-Endurance Flash
Device
(Words) Address Memory Address Range(1)
PIC16(L)F1704/8 4,096 0FFFh 0F80h - 0FFFh
Note 1: High-endurance Flash applies to the low byte of each address in the range.

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PIC16(L)F1704/8
FIGURE 3-1: PROGRAM MEMORY MAP 3.1.1 READING PROGRAM MEMORY AS
AND STACK FOR DATA
PIC16(L)F1704/8 There are two methods of accessing constants in
program memory. The first method is to use tables of
RETLW instructions. The second method is to set an
PC<14:0>
FSR to point to the program memory.
CALL, CALLW 15
RETURN, RETLW 3.1.1.1 RETLW Instruction
Interrupt, RETFIE
The RETLW instruction can be used to provide access
Stack Level 0
to tables of constants. The recommended way to create
Stack Level 1
such a table is shown in Example 3-1.

Stack Level 15 EXAMPLE 3-1: RETLW INSTRUCTION

constants
Reset Vector 0000h BRW ;Add Index in W to
;program counter to
;select data
Interrupt Vector 0004h RETLW DATA0 ;Index0 data
RETLW DATA1 ;Index1 data
0005h
RETLW DATA2
Page 0
On-chip 07FFh
RETLW DATA3
Program
Memory 0800h
Page 1 my_function
;… LOTS OF CODE…
0FFFh
MOVLW DATA_INDEX
1000h
Rollover to Page 0 call constants
;… THE CONSTANT IS IN W

The BRW instruction makes this type of table very

simple to implement. If your code must remain portable
with previous generations of microcontrollers, then the
BRW instruction is not available so the older table read
method must be used.

3.1.1.2 Indirect Read with FSR

The program memory can be accessed as data by
setting bit 7 of the FSRxH register and reading the
matching INDFx register. The MOVIW instruction will
place the lower eight bits of the addressed word in the
W register. Writes to the program memory cannot be
performed via the INDF registers. Instructions that
Rollover to Page 1 access the program memory via the FSR require one
7FFFh
extra instruction cycle to complete. Example 3-2
demonstrates accessing the program memory via an
FSR.
The high directive will set bit<7> if a label points to a
location in program memory.

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 PIC16(L)F1704/8
EXAMPLE 3-2: ACCESSING PROGRAM
MEMORY VIA FSR
constants
DW DATA0 ;First constant
DW DATA1 ;Second constant
DW DATA2
DW DATA3
my_function
;… LOTS OF CODE…
MOVLW DATA_INDEX
ADDLW LOW constants
MOVWF FSR1L
MOVLW HIGH constants;MSb sets
automatically
MOVWF FSR1H
BTFSC STATUS, C ;carry from ADDLW?
INCF FSR1H, f ;yes
MOVIW 0[FSR1]
;THE PROGRAM MEMORY IS IN W

3.2 High-Endurance Flash

This device has a 128-byte section of high-endurance
Program Flash Memory (PFM) in lieu of data
EEPROM. This area is especially well suited for non-
volatile data storage that is expected to be updated fre-
quently over the life of the end product. See
Section 10.2 “Flash Program Memory Overview”
for more information on writing data to PFM. See
Section 3.1.1.2 “Indirect Read with FSR” for more
information about using the FSR registers to read byte
data stored in PFM.

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PIC16(L)F1704/8
3.3 Data Memory Organization 3.3.1.1 STATUS Register
The data memory is partitioned in 32 memory banks The STATUS register, shown in Register 3-1, contains:
with 128 bytes in a bank. Each bank consists of • the arithmetic status of the ALU
(Figure 3-2): • the Reset status
• 12 core registers The STATUS register can be the destination for any
• 20 Special Function Registers (SFR) instruction, like any other register. If the STATUS
• Up to 80 bytes of General Purpose RAM (GPR) register is the destination for an instruction that affects
• 16 bytes of common RAM the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
The active bank is selected by writing the bank number device logic. Furthermore, the TO and PD bits are not
into the Bank Select Register (BSR). Unimplemented writable. Therefore, the result of an instruction with the
memory will read as ‘0’. All data memory can be STATUS register as destination may be different than
accessed either directly (via instructions that use the intended.
file registers) or indirectly via the two File Select
Registers (FSR). See Section 3.7 “Indirect For example, CLRF STATUS will clear the upper three
Addressing” for more information. bits and set the Z bit. This leaves the STATUS register
as ‘000u u1uu’ (where u = unchanged).
Data memory uses a 12-bit address. The upper five bits
of the address define the Bank address and the lower It is recommended, therefore, that only BCF, BSF,
seven bits select the registers/RAM in that bank. SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
3.3.1 CORE REGISTERS affect any Status bits. For other instructions not
affecting any Status bits (Refer to Section 31.0
The core registers contain the registers that directly
“Instruction Set Summary”).
affect the basic operation. The core registers occupy
the first 12 addresses of every data memory bank Note: The C and DC bits operate as Borrow and
(addresses x00h/x08h through x0Bh/x8Bh). These Digit Borrow out bits, respectively, in
registers are listed below in Table 3-2. For detailed subtraction.
information, see Table 3-9.

TABLE 3-2: CORE REGISTERS

Addresses BANKx
x00h or x80h INDF0
x01h or x81h INDF1
x02h or x82h PCL
x03h or x83h STATUS
x04h or x84h FSR0L
x05h or x85h FSR0H
x06h or x86h FSR1L
x07h or x87h FSR1H
x08h or x88h BSR
x09h or x89h WREG
x0Ah or x8Ah PCLATH
x0Bh or x8Bh INTCON

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 PIC16(L)F1704/8
3.4 Register Definitions: Status
REGISTER 3-1: STATUS: STATUS REGISTER
U-0 U-0 U-0 R-1/q R-1/q R/W-0/u R/W-0/u R/W-0/u
(1)
— — — TO PD Z DC C(1)
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7-5 Unimplemented: Read as ‘0’

bit 4 TO: Time-Out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT Time-out occurred
bit 3 PD: Power-Down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
bit 0 C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred

Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand.

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PIC16(L)F1704/8
3.4.1 SPECIAL FUNCTION REGISTER FIGURE 3-2: BANKED MEMORY
The Special Function Registers are registers used by PARTITIONING
the application to control the desired operation of
peripheral functions in the device. The Special Function Memory Region
7-bit Bank Offset
Registers occupy the 20 bytes after the core registers of
every data memory bank (addresses x0Ch/x8Ch
through x1Fh/x9Fh). The registers associated with the 00h
operation of the peripherals are described in the Core Registers
appropriate peripheral chapter of this data sheet. (12 bytes)
0Bh
3.4.2 GENERAL PURPOSE RAM 0Ch
There are up to 80 bytes of GPR in each data memory Special Function Registers
bank. The General Purpose RAM occupies the 80 (20 bytes maximum)
bytes after the SFR registers of selected data memory 1Fh
banks.
20h
3.4.2.1 Linear Access to GPR
The general purpose RAM can be accessed in a
non-banked method via the FSRs. This can simplify
access to large memory structures. See Section 3.7.2
“Linear Data Memory” for more information. General Purpose RAM
(80 bytes maximum)
3.4.3 COMMON RAM
There are 16 bytes of common RAM accessible from all
banks.

6Fh
70h
Common RAM
(16 bytes)
7Fh

3.4.4 DEVICE MEMORY MAPS

The memory maps for the device family are as shown
in Tables 3-3 through 3-8.

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 TABLE 3-3: PIC16(L)F1704 MEMORY MAP (BANKS 0-7)
 2013-2015 Microchip Technology Inc.

BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7

000h 080h 100h 180h 200h 280h 300h 380h
Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers
(Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2)
00Bh 08Bh 10Bh 18Bh 20Bh 28Bh 30Bh 38Bh
00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch WPUA 28Ch ODCONA 30Ch SLRCONA 38Ch INLVLA
00Dh — 08Dh — 10Dh — 18Dh — 20Dh — 28Dh — 30Dh — 38Dh —
00Eh PORTC 08Eh TRISC 10Eh LATC 18Eh ANSELC 20Eh WPUC 28Eh ODCONC 30Eh SLRCONC 38Eh INLVLC
00Fh — 08Fh — 10Fh — 18Fh — 20Fh — 28Fh — 30Fh — 38Fh —
010h — 090h — 110h — 190h — 210h — 290h — 310h — 390h —
011h PIR1 091h PIE1 111h CM1CON0 191h PMADRL 211h SSP1BUF 291h CCPR1L 311h — 391h IOCAP
012h PIR2 092h PIE2 112h CM1CON1 192h PMADRH 212h SSP1ADD 292h CCPR1H 312h — 392h IOCAN
013h PIR3 093h PIE3 113h CM2CON0 193h PMDATL 213h SSP1MSK 293h CCP1CON 313h — 393h IOCAF
014h — 094h — 114h CM2CON1 194h PMDATH 214h SSP1STAT 294h — 314h — 394h —
015h TMR0 095h OPTION_REG 115h CMOUT 195h PMCON1 215h SSP1CON 295h — 315h — 395h —
016h TMR1L 096h PCON 116h BORCON 196h PMCON2 216h SSP1CON2 296h — 316h — 396h —
017h TMR1H 097h WDTCON 117h FVRCON 197h VREGCON(1) 217h SSP1CON3 297h — 317h — 397h IOCCP
018h T1CON 098h OSCTUNE 118h DAC1CON0 198h — 218h — 298h CCPR2L 318h — 398h IOCCN
019h T1GCON 099h OSCCON 119h DAC1CON1 199h RC1REG 219h — 299h CCPR2H 319h — 399h IOCCF
01Ah TMR2 09Ah OSCSTAT 11Ah — 19Ah TX1REG 21Ah — 29Ah CCP2CON 31Ah — 39Ah —
01Bh PR2 09Bh ADRESL 11Bh — 19Bh SP1BRGL 21Bh — 29Bh — 31Bh — 39Bh —
01Ch T2CON 09Ch ADRESH 11Ch ZCD1CON 19Ch SP1BRGH 21Ch — 29Ch — 31Ch — 39Ch —
01Dh — 09Dh ADCON0 11Dh — 19Dh RC1STA 21Dh — 29Dh — 31Dh — 39Dh —
01Eh — 09Eh ADCON1 11Eh — 19Eh TX1STA 21Eh — 29Eh CCPTMRS 31Eh — 39Eh —
01Fh — 09Fh ADCON2 11Fh — 19Fh BAUD1CON 21Fh — 29Fh — 31Fh — 39Fh —
020h 0A0h 120h 1A0h 220h 2A0h 320h General Purpose 3A0h
Register
General General General General General General 32Fh 16 Bytes
Purpose Purpose Purpose Purpose Purpose Purpose 330h Unimplemented
Register Register Register Register Register Register Read as ‘0’

PIC16(L)F1704/8
80 Bytes 80 Bytes 80 Bytes 80 Bytes 80 Bytes 80 Bytes Unimplemented
Read as ‘0’
06Fh 0EFh 16Fh 1EFh 26Fh 2EFh 36Fh 3EFh
070h 0F0h 170h 1F0h 270h 2F0h 370h 3F0h
Common RAM Accesses Accesses Accesses Accesses Accesses Accesses Accesses
70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh
07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh

Legend: = Unimplemented data memory locations, read as ‘0’.

DS40001715D-page 25

Note 1: Unimplemented on PIC16LF1704.

 TABLE 3-4: PIC16(L)1708 MEMORY MAP (BANKS 0-7)
DS40001715D-page 26

PIC16(L)F1704/8
BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7
000h 080h 100h 180h 200h 280h 300h 380h
Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers
(Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2)
00Bh 08Bh 10Bh 18Bh 20Bh 28Bh 30Bh 38Bh
00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch WPUA 28Ch ODCONA 30Ch SLRCONA 38Ch INLVLA
00Dh PORTB 08Dh TRISB 10Dh LATB 18Dh ANSELB 20Dh WPUB 28Dh ODCONB 30Dh SLRCONB 38Dh INLVLB
00Eh PORTC 08Eh TRISC 10Eh LATC 18Eh ANSELC 20Eh WPUC 28Eh ODCONC 30Eh SLRCONC 38Eh INLVLC
00Fh — 08Fh — 10Fh — 18Fh — 20Fh — 28Fh — 30Fh — 38Fh —
010h — 090h — 110h — 190h — 210h — 290h — 310h — 390h —
011h PIR1 091h PIE1 111h CM1CON0 191h PMADRL 211h SSP1BUF 291h CCPR1L 311h — 391h IOCAP
012h PIR2 092h PIE2 112h CM1CON1 192h PMADRH 212h SSP1ADD 292h CCPR1H 312h — 392h IOCAN
013h PIR3 093h PIE3 113h CM2CON0 193h PMDATL 213h SSP1MSK 293h CCP1CON 313h — 393h IOCAF
014h — 094h — 114h CM2CON1 194h PMDATH 214h SSP1STAT 294h — 314h — 394h IOCBP
015h TMR0 095h OPTION_REG 115h CMOUT 195h PMCON1 215h SSP1CON 295h — 315h — 395h IOCBN
016h TMR1L 096h PCON 116h BORCON 196h PMCON2 216h SSP1CON2 296h — 316h — 396h IOCBF
017h TMR1H 097h WDTCON 117h FVRCON 197h VREGCON(1) 217h SSP1CON3 297h — 317h — 397h IOCCP
018h T1CON 098h OSCTUNE 118h DAC1CON0 198h — 218h — 298h CCPR2L 318h — 398h IOCCN
019h T1GCON 099h OSCCON 119h DAC1CON1 199h RC1REG 219h — 299h CCPR2H 319h — 399h IOCCF
01Ah TMR2 09Ah OSCSTAT 11Ah — 19Ah TX1REG 21Ah — 29Ah CCP2CON 31Ah — 39Ah —
01Bh PR2 09Bh ADRESL 11Bh — 19Bh SP1BRGL 21Bh — 29Bh — 31Bh — 39Bh —
01Ch T2CON 09Ch ADRESH 11Ch ZCD1CON 19Ch SP1BRGH 21Ch — 29Ch — 31Ch — 39Ch —
01Dh — 09Dh ADCON0 11Dh — 19Dh RC1STA 21Dh — 29Dh — 31Dh — 39Dh —
01Eh — 09Eh ADCON1 11Eh — 19Eh TX1STA 21Eh — 29Eh CCPTMRS 31Eh — 39Eh —
01Fh — 09Fh ADCON2 11Fh — 19Fh BAUD1CON 21Fh — 29Fh — 31Fh — 39Fh —
020h 0A0h 120h 1A0h 220h 2A0h 320h General Purpose 3A0h
Register
General General General General General General 32Fh 16 Bytes
Purpose Purpose Purpose Purpose Purpose Purpose 330h Unimplemented
Register Register Register Register Register Register Read as ‘0’
80 Bytes 80 Bytes 80 Bytes 80 Bytes 80 Bytes 80 Bytes Unimplemented
Read as ‘0’
06Fh 0EFh 16Fh 1EFh 26Fh 2EFh 36Fh 3EFh
 2013-2015 Microchip Technology Inc.

070h 0F0h 170h 1F0h 270h 2F0h 370h 3F0h

Common RAM Accesses Accesses Accesses Accesses Accesses Accesses Accesses
70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh
07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh

Legend: = Unimplemented data memory locations, read as ‘0’.

Note 1: Unimplemented on PIC16LF1708.
 TABLE 3-5: PIC16(L)F1704/8 MEMORY MAP, BANK 8-23
 2013-2015 Microchip Technology Inc.

BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 13 BANK 14 BANK 15

400h 480h 500h 580h 600h 680h 700h 780h
Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers
(Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2)
40Bh 48Bh 50Bh 58Bh 60Bh 68Bh 70Bh 78Bh
40Ch — 48Ch — 50Ch — 58Ch — 60Ch — 68Ch — 70Ch — 78Ch —
40Dh — 48Dh — 50Dh — 58Dh — 60Dh — 68Dh — 70Dh — 78Dh —
40Eh — 48Eh — 50Eh — 58Eh — 60Eh — 68Eh — 70Eh — 78Eh —
40Fh — 48Fh — 50Fh — 58Fh — 60Fh — 68Fh — 70Fh — 78Fh —
410h — 490h — 510h — 590h — 610h — 690h — 710h — 790h —
411h — 491h — 511h OPA1CON 591h — 611h — 691h COG1PHR 711h — 791h —
412h — 492h — 512h — 592h — 612h — 692h COG1PHF 712h — 792h —
413h — 493h — 513h — 593h — 613h — 693h COG1BLKR 713h — 793h —
414h — 494h — 514h — 594h — 614h — 694h COG1BLKF 714h — 794h —
415h TMR4 495h — 515h OPA2CON 595h — 615h — 695h COG1DBR 715h — 795h —
416h PR4 496h — 516h — 596h — 616h — 696h COG1DBF 716h — 796h —
417h T4CON 497h — 517h — 597h — 617h PWM3DCL 697h COG1CON0 717h — 797h —
418h — 498h — 518h — 598h — 618h PWM3DCH 698h COG1CON1 718h — 798h —
419h — 499h — 519h — 599h — 619h PWM3CON 699h COG1RIS 719h — 799h —
41Ah — 49Ah — 51Ah — 59Ah — 61Ah PWM4DCL 69Ah COG1RSIM 71Ah — 79Ah —
41Bh — 49Bh — 51Bh — 59Bh — 61Bh PWM4DCH 69Bh COG1FIS 71Bh — 79Bh —
41Ch TMR6 49Ch — 51Ch — 59Ch — 61Ch PWM4CON 69Ch COG1FSIM 71Ch — 79Ch —
41Dh PR6 49Dh — 51Dh — 59Dh — 61Dh — 69Dh COG1ASD0 71Dh — 79Dh —
41Eh T6CON 49Eh — 51Eh — 59Eh — 61Eh — 69Eh COG1ASD1 71Eh — 79Eh —
41Fh — 49Fh — 51Fh — 59Fh — 61Fh — 69Fh COG1STR 71Fh — 79Fh —
420h 4A0h 520h 5A0h 620h 6A0h 720h 7A0h

Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented

Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’

46Fh 4EFh 56Fh 5EFh 66Fh 6EFh 76Fh 7EFh

470h 4F0h 570h 5F0h 670h 6F0h 770h 7F0h
Accesses Accesses Accesses Accesses Accesses Accesses Accesses Accesses

PIC16(L)F1704/8
70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh
47Fh 4FFh 57Fh 5FFh 67Fh 6FFh 77Fh 7FFh

BANK 16 BANK 17 BANK 18 BANK 19 BANK 20 BANK 21 BANK 22 BANK 23

800h 880h 900h 980h A00h A80h B00h B80h
Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers
(Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2)
80Bh 88Bh 90Bh 98Bh A0Bh A8Bh B0Bh B8Bh
80Ch 88Ch 90Ch 98Ch A0Ch A8Ch B0Ch B8Ch
DS40001715D-page 27

Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented

Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’
86Fh 8EFh 96Fh 9EFh A6Fh AEFh B6Fh BEFh
870h 8F0h 970h 9F0h A70h AF0h B70h BF0h
Accesses Accesses Accesses Accesses Accesses Accesses Accesses Accesses
70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh
87Fh 8FFh 97Fh 9FFh A7Fh AFFh B7Fh BFFh
Legend: = Unimplemented data memory locations, read as ‘0’.
 TABLE 3-6: PIC16(L)F1704/8 MEMORY MAP, BANK 24-31
DS40001715D-page 28

PIC16(L)F1704/8
BANK 24 BANK 25 BANK 26 BANK 27 BANK 28 BANK 29 BANK 30 BANK 31
C00h C80h D00h D80h E00h E80h F00h F80h
Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers
(Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2)
C0Bh C8Bh D0Bh D8Bh E0Bh E8Bh F0Bh F8Bh
C0Ch — C8Ch — D0Ch — D8Ch — E0Ch E8Ch F0Ch F8Ch
C0Dh — C8Dh — D0Dh — D8Dh — E0Dh E8Dh F0Dh F8Dh
C0Eh — C8Eh — D0Eh — D8Eh — E0Eh E8Eh F0Eh F8Eh
C0Fh — C8Fh — D0Fh — D8Fh — E0Fh E8Fh F0Fh F8Fh
C10h — C90h — D10h — D90h — E10h E90h F10h F90h
C11h — C91h — D11h — D91h — E11h E91h F11h F91h
C12h — C92h — D12h — D92h — E12h E92h F12h F92h
C13h — C93h — D13h — D93h — E13h E93h F13h F93h
C14h — C94h — D14h — D94h — E14h E94h F14h F94h
C15h — C95h — D15h — D95h — E15h E95h F15h F95h
C16h — C96h — D16h — D96h — E16h E96h F16h F96h
C17h — C97h — D17h — D97h — E17h E97h F17h F97h
See Table 3-7 for See Table 3-7 for See Table 3-7 for See Table 3-8 for
C18h — C98h — D18h — D98h — E18h register mapping E98h register mapping F18h register mapping F98h register mapping
C19h — C99h — D19h — D99h — E19h details E99h details F19h details F99h details
C1Ah — C9Ah — D1Ah — D9Ah — E1Ah E9Ah F1Ah F9Ah
C1Bh — C9Bh — D1Bh — D9Bh — E1Bh E9Bh F1Bh F9Bh
C1Ch — C9Ch — D1Ch — D9Ch — E1Ch E9Ch F1Ch F9Ch
C1Dh — C9Dh — D1Dh — D9Dh — E1Dh E9Dh F1Dh F9Dh
C1Eh — C9Eh — D1Eh — D9Eh — E1Eh E9Eh F1Eh F9Eh
C1Fh — C9Fh — D1Fh — D9Fh — E1Fh E9Fh F1Fh F9Fh
C20h CA0h D20h DA0h E20h EA0h F20h FA0h

Unimplemented Unimplemented Unimplemented Unimplemented

Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’

C6Fh CEFh D6Fh DEFh E6Fh EEFh F6Fh FEFh

C70h CF0h D70h DF0h E70h EF0h F70h FF0h
 2013-2015 Microchip Technology Inc.

Accesses Accesses Accesses Accesses Accesses Accesses Accesses Accesses

70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh
CFFh CFFh D7Fh DFFh E7Fh EFFh F7Fh FFFh

Legend: = Unimplemented data memory locations, read as ‘0’.

 PIC16(L)F1704/8
TABLE 3-7: PIC16(L)F1704/8 MEMORY MAP, BANK 28-30

Bank 28 Bank 29 Bank 30

E0Ch — E8Ch — F0Ch —
E0Dh — E8Dh — F0Dh —
E0Eh — E8Eh — F0Eh —
E0Fh PPSLOCK E8Fh — F0Fh CLCDATA
E10h INTPPS E90h RA0PPS F10h CLC1CON
E11h T0CKIPPS E91h RA1PPS F11h CLC1POL
E12h T1CKIPPS E92h RA2PPS F12h CLC1SEL0
E13h T1GPPS E93h — F13h CLC1SEL1
E14h CCP1PPS E94h RA4PPS F14h CLC1SEL2
E15h CCP2PPS E95h RA5PPS F15h CLC1SEL3
E16h — E96h — F16h CLC1GLS0
E17h COGINPPS E97h — F17h CLC1GLS1
E18h — E98h — F18h CLC1GLS2
E19h — E99h — F19h CLC1GLS3
E1Ah — E9Ah — F1Ah CLC2CON
E1Bh — E9Bh — F1Bh CLC2POL
E1Ch — E9Ch RB4PPS(1) F1Ch CLC2SEL0
E1Dh — E9Dh RB5PPS(1) F1Dh CLC2SEL1
E1Eh — E9Eh RB6PPS(1) F1Eh CLC2SEL2
E1Fh — E9Fh RB7PPS(1) F1Fh CLC2SEL3
E20h SSPCLKPPS EA0h RC0PPS F20h CLC2GLS0
E21h SSPDATPPS EA1h RC1PPS F21h CLC2GLS1
E22h SSPSSPPS EA2h RC2PPS F22h CLC2GLS2
E23h — EA3h RC3PPS F23h CLC2GLS3
E24h RXPPS EA4h RC4PPS F24h CLC3CON
E25h CKPPS EA5h RC5PPS F25h CLC3POL
E26h — EA6h RC6PPS(1) F26h CLC3SEL0
E27h — EA7h RC7PPS(1) F27h CLC3SEL1
E28h CLCIN0PPS EA8h — F28h CLC3SEL2
E29h CLCIN1PPS EA9h — F29h CLC3SEL3
E2Ah CLCIN2PPS EAAh — F2Ah CLC3GLS0
E2Bh CLCIN3PPS EABh — F2Bh CLC3GLS1
E2Ch — EACh — F2Ch CLC3GLS2
E2Dh — EADh — F2Dh CLC3GLS3
E2Eh — EAEh — F2Eh —
E2Fh — EAFh — F2Fh —
E30h — EB0h — F30h —
E31h — EB1h — F31h —
E32h — EB2h — F32h —
E33h — EB3h — F33h —
E34h — EB4h — F34h —
E35h — EB5h — F35h —
E36h — EB6h — F36h —
E37h — EB7h — F37h —
E38h — EB8h — F38h —
E39h — EB9h — F39h —
E3Ah — EBAh — F3Ah —
E3Bh — EBBh — F3Bh —
E3Ch — EBCh — F3Ch —
E3Dh — EBDh — F3Dh —
E3Eh — EBEh — F3Eh —
E3Fh — EBFh — F3Fh —
E40h EC0h F40h
—
— —
E6Fh EEFh F6Fh
Legend: = Unimplemented data memory locations, read as ‘0’,
Note 1: Only available on PIC16(L)F1708 devices

 2013-2015 Microchip Technology Inc. DS40001715D-page 29

PIC16(L)F1704/8
TABLE 3-8: PIC16(L)F1704/8 MEMORY
MAP, BANK 31
Bank 31
F8Ch
Unimplemented
Read as ‘0’
FE3h
FE4h STATUS_SHAD
FE5h WREG_SHAD
FE6h BSR_SHAD
FE7h PCLATH_SHAD
FE8h FSR0L_SHAD
FE9h FSR0H_SHAD
FEAh FSR1L_SHAD
FEBh FSR1H_SHAD
FECh —
FEDh STKPTR
FEEh TOSL
FEFh TOSH
Legend: = Unimplemented data memory locations,
read as ‘0’,

DS40001715D-page 30  2013-2015 Microchip Technology Inc.

 PIC16(L)F1704/8
3.4.5 CORE FUNCTION REGISTERS
SUMMARY
The Core Function registers listed in Table 3-9 can be
addressed from any Bank.

TABLE 3-9: CORE FUNCTION REGISTERS SUMMARY

Value on Value on all
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR other Resets

Bank 0-31
x00h or Addressing this location uses contents of FSR0H/FSR0L to address data memory
INDF0 xxxx xxxx uuuu uuuu
x80h (not a physical register)
x01h or Addressing this location uses contents of FSR1H/FSR1L to address data memory
INDF1 xxxx xxxx uuuu uuuu
x81h (not a physical register)
x02h or
PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
x82h
x03h or
STATUS — — — TO PD Z DC C ---1 1000 ---q quuu
x83h
x04h or
FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu
x84h
x05h or
FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
x85h
x06h or
FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu
x86h
x07h or
FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000
x87h
x08h or
BSR — — — BSR4 BSR3 BSR2 BSR1 BSR0 ---0 0000 ---0 0000
x88h
x09h or
WREG Working Register 0000 0000 uuuu uuuu
x89h
x0Ah or
PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
x8Ah
x0Bh or
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000
x8Bh
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: These registers can be addressed from any bank.

 2013-2015 Microchip Technology Inc. DS40001715D-page 31

PIC16(L)F1704/8

TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY

Value on all
Value on
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other
POR, BOR
Resets
Bank 0
00Ch PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx --uu uuuu
00Dh PORTB(3) RB7 RB6 RB5 RB4 — — — — xxxx ---- uuuu ----
00Eh PORTC RC7(3) RC6(3) RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu
00Fh — Unimplemented — —
010h — Unimplemented — —
011h PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 0000 0-00 0000 0-00
012h PIR2 OSFIF C2IF C1IF — BCL1IF TMR6IF TMR4IF CCP2IF 000- 00-- 000- 00--
013h PIR3 — — COGIF ZCDIF — CLC3IF CLC2IF CLC1IF --00 -000 --00 -000
014h — Unimplemented — —
015h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu
016h TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
017h TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
018h T1CON TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC — TMR1ON 0000 00-0 uuuu uu-u
019h T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS<1:0> 0000 0x00 uuuu uxuu
DONE
01Ah TMR2 Holding Register for the 8-bit TMR2 Register xxxx xxxx uuuu uuuu
01Bh PR2 Timer2 Period Register xxxx xxxx uuuu uuuu
01Ch T2CON — T2OUTPS<3:0> TMR2ON T2CKPS<1:0> -000 0000 -000 0000
01Dh
to — Unimplemented — —
01Fh
Bank 1
08Ch TRISA — — TRISA5 TRISA4 —(1) TRISA2 TRISA1 TRISA0 --11 1111 --11 1111
(3)
08Dh TRISB TRISB7 TRISB6 TRISB5 TRISB4 — — — — 1111 ---- 1111 ----
08Eh TRISC TRISC7(3) TRISC6(3) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
08Fh — Unimplemented — —
090h — Unimplemented — —
091h PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
092h PIE2 OSFIE C2IE C1IE — BCL1IE TMR6IE TMR4IE CCP2IE 000- 0000 000- 0000
093h PIE3 — — COGIE ZCDIE — CLC3IE CLC2IE CLC1IE --00 -000 --00 -000
094h — Unimplemented — —
095h OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 1111 1111 1111 1111
096h PCON STKOVF STKUNF — RWDT RMCLR RI POR BOR 00-1 11qq qq-q qquu
097h WDTCON — — WDTPS<4:0> SWDTEN --01 0110 --01 0110
098h OSCTUNE — — TUN<5:0> --00 0000 --00 0000
099h OSCCON SPLLEN IRCF<3:0> — SCS<1:0> 0011 1-00 0011 1-00
09Ah OSCSTAT SOSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS 00q0 --00 qqqq --0q
09Bh ADRESL ADC Result Register Low xxxx xxxx uuuu uuuu
09Ch ADRESH ADC Result Register High xxxx xxxx uuuu uuuu
09Dh ADCON0 — CHS<4:0> GO/DONE ADON -000 0000 -000 0000
09Eh ADCON1 ADFM ADCS<2:0> — ADNREF ADPREF<1:0> 0000 -000 0000 -000
09Fh ADCON2 TRIGSEL<3:0> — — — — 0000 ---- 0000 ----
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: Unimplemented, read as ‘1’.
2: PIC16(L)F1704 only.
3: PIC16(L)F1708 only.
4: Unimplemented on PIC16LF1704/8.

DS40001715D-page 32  2013-2015 Microchip Technology Inc.

 PIC16(L)F1704/8
TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on all
Value on
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other
POR, BOR
Resets

Bank 2
10Ch LATA — — LATA5 LATA4 — LATA2 LATA1 LATA0 --xx -xxx --uu -uuu
10Dh LATB(3) LATB7 LATB6 LATB5 LATB4 — — — — xxxx ---- uuuu ----
10Eh LATC LATC7(3) LATC6(3) LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx xxxx uuuu uuuu
10Fh — Unimplemented — —
110h — Unimplemented — —
111h CM1CON0 C1ON C1OUT — C1POL C1ZLF C1SP C1HYS C1SYNC 00-0 0100 00-0 0100
112h CM1CON1 C1INTP C1INTN C1PCH<2:0> C1NCH<2:0> 0000 0000 0000 0000
113h CM2CON0 C2ON C2OUT — C2POL C2ZLF C2SP C2HYS C2SYNC 00-0 0100 00-0 0100
114h CM2CON1 C2INTP C2INTN C2PCH<2:0> C2NCH<2:0> 0000 0000 0000 0000
115h CMOUT — — — — — — MC2OUT MC1OUT ---- --00 ---- --00
116h BORCON SBOREN BORFS — — — — — BORRDY 1x-- ---q uu-- ---u
117h FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 0q00 0000 0q00 0000
118h DAC1CON0 DAC1EN --- DAC1OE1 DAC1OE2 DAC1PSS<1:0> --- DAC1NSS 0-00 00-0 0-00 00-0
119h DAC1CON1 DAC1R<7:0> 0000 0000 0000 0000
11Ah — Unimplemented — —
11Bh — Unimplemented — —
11Ch ZCD1CON ZCD1EN — ZCD1OUT ZCD1POL — — ZCD1INTP ZCD1INTN 0-00 --00 0-00 --00
11Dh — Unimplemented — —
11Eh — Unimplemented — —
11Fh — Unimplemented — —
Bank 3
18Ch ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 ---1 1111 ---1 1111
18Dh ANSELB(3) — — ANSB5 ANSB4 — — — — --11 ---- --11 ----
18Eh ANSELC ANSC7(3) ANSC6(3) ANSC5(2) ANSC4(2) ANSC3 ANSC2 ANSC1 ANSC0 1111 1111 1111 1111
18Fh — Unimplemented — —
190h — Unimplemented — —
191h PMADRL Program Memory Address Register Low Byte 0000 0000 0000 0000
192h PMADRH —(1) Program Memory Address Register High Byte 1000 0000 1000 0000
193h PMDATL Program Memory Read Data Register Low Byte xxxx xxxx uuuu uuuu
194h PMDATH — — Program Memory Read Data Register High Byte --xx xxxx --uu uuuu
195h PMCON1 — CFGS LWLO FREE WRERR WREN WR RD -000 x000 -000 q000
196h PMCON2 Program Memory Control Register 2 0000 0000 0000 0000
197h VREGCON(4) — — — — — — VREGPM Reserved ---- --01 ---- --01
198h — Unimplemented — —
199h RC1REG USART Receive Data Register 0000 0000 0000 0000
19Ah TX1REG USART Transmit Data Register 0000 0000 0000 0000
19Bh SP1BRGL BRG<7:0> 0000 0000 0000 0000
19Ch SP1BRGH BRG<15:8> 0000 0000 0000 0000
19Dh RC1STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 0000 0000 0000
19Eh TX1STA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010
19Fh BAUD1CON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: Unimplemented, read as ‘1’.
2: PIC16(L)F1704 only.
3: PIC16(L)F1708 only.
4: Unimplemented on PIC16LF1704/8.

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PIC16(L)F1704/8
TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on all
Value on
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other
POR, BOR
Resets

Bank 4
20Ch WPUA — — WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 --11 1111 --11 1111
20Dh WPUB(3) WPUB7 WPUB6 WPUB5 WPUB4 — — — — 1111 ---- 1111 ----
20Eh WPUC WPUC7(3) WPUC6(3) WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 1111 1111 1111 1111
20Fh — Unimplemented — —
210h — Unimplemented — —
211h SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
212h SSP1ADD ADD<7:0> 0000 0000 0000 0000
213h SSP1MSK MSK<7:0> 1111 1111 1111 1111
214h SSP1STAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
215h SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 0000 0000 0000 0000
216h SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000
217h SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000
218h
— — Unimplemented — —
21Fh
Bank 5
28Ch ODCONA — — ODA5 ODA4 — ODA2 ODA1 ODA0 --00 -000 --00 -000
28Dh ODCONB(3) ODB7 ODB6 ODB5 ODB4 — — — — 0000 ---- 0000 ----
28Eh ODCONC ODC7(3) ODC6(3) ODC5 ODC4 ODC3 ODC2 ODC1 ODC0 0000 0000 0000 0000
28Fh — Unimplemented — —
290h — Unimplemented — —
291h CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx uuuu uuuu
292h CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx uuuu uuuu
293h CCP1CON — — DC1B<1:0> CCP1M<3:0> --00 0000 --00 0000
294h
— — Unimplemented — —
297h
298h CCPR2L Capture/Compare/PWM Register 2 (LSB) xxxx xxxx uuuu uuuu
299h CCPR2H Capture/Compare/PWM Register 2 (MSB) xxxx xxxx uuuu uuuu
29Ah CCP2CON — — DC2B<1:0> CCP2M<3:0> --00 0000 --00 0000
29Bh
— — Unimplemented — —
29Dh
29Eh CCPTMRS P4TSEL<1:0> P3TSEL<1:0> C2TSEL<1:0> C1TSEL<1:0> 0000 0000 0000 0000
29Fh — Unimplemented — —
Bank 6
30Ch SLRCONA — — SLRA5 SLRA4 — SLRA2 SLRA1 SLRA0 --00 -000 --00 -000
30Dh SLRCONB(3) SLRB7 SLRB6 SLRB5 SLRB4 — — — — 0000 ---- 0000 ----
30Eh SLRCONC SLRC7(3) SLRC6(3) SLRC5 SLRC4 SLRC3 SLRC2 SLRC1 SLRC0 0000 0000 0000 0000
30Fh
— — Unimplemented — —
31Fh
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: Unimplemented, read as ‘1’.
2: PIC16(L)F1704 only.
3: PIC16(L)F1708 only.
4: Unimplemented on PIC16LF1704/8.

DS40001715D-page 34  2013-2015 Microchip Technology Inc.

 PIC16(L)F1704/8
TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on all
Value on
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other
POR, BOR
Resets

Bank 7
38Ch INLVLA — — INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 --11 1111 --11 1111
38Dh INLVLB(3) INLVLB7 INLVLB6 INLVLB5 INLVLB4 — — — — 1111 ---- 1111 ----
38Eh INLVLC INLVLC7(3) INLVLC6(3) INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 1111 1111 1111 1111
38Fh — Unimplemented — —
390h — Unimplemented — —
391h IOCAP — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 --00 0000 --00 0000
392h IOCAN — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 --00 0000 --00 0000
393h IOCAF — — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 --00 0000 --00 0000
394h IOCBP(3) IOCBP7 IOCBP6 IOCBP5 IOCBP4 — — — — 0000 ---- 0000 ----
395h IOCBN(3) IOCBN7 IOCBN6 IOCBN5 IOCBN4 — — — — 0000 ---- 0000 ----
396h IOCBF(3) IOCBF7 IOCBF6 IOCBF5 IOCBF4 — — — — 0000 ---- 0000 ----
397h IOCCP IOCCP7(3) IOCCP6(3) IOCCP5 IOCCP4 IOCCP3 IOCCP2 IIOCCP1 IOCCP0 0000 0000 0000 0000
398h IOCCN IOCCN7(3) IOCCN6(3) IOCCN5 IOCCN4 IOCCN3 IOCCN2 IIOCCN1 IOCCN0 0000 0000 0000 0000
399h IOCCF IOCCF7(3) IOCCF6(3) IOCCF5 IOCCF4 IOCCF3 IOCCF2 IIOCCF1 IOCCF0 0000 0000 0000 0000
39Ah
— — Unimplemented — —
39Fh
Bank 8
40Ch
— — Unimplemented — —
414h
415h TMR4 Holding Register for the Least Significant Byte of the 16-bit TMR4 Register xxxx xxxx uuuu uuuu
416h PR4 Holding Register for the Most Significant Byte of the 16-bit TMR4 Register xxxx xxxx uuuu uuuu
417h T4CON — T4OUTPS<3:0> TMR4ON T4CKPS<1:0> -000 0000 -000 0000
418h
— — Unimplemented — —
41Bh
41Ch TMR6 Holding Register for the Least Significant Byte of the 16-bit TMR6 Register xxxx xxxx uuuu uuuu
41Dh PR6 Holding Register for the Most Significant Byte of the 16-bit TMR6 Register xxxx xxxx uuuu uuuu
41Eh T6CON — T6OUTPS<3:0> TMR6ON T6CKPS<1:0> -000 0000 -000 0000
41Fh — Unimplemented — —
Bank 9
48Ch
to — Unimplemented — —
49Fh
Bank 10
50Ch
— — Unimplemented — —
510h
511h OPA1CON OPA1EN OPA1SP — OPA1UG — — OPA1PCH<1:0> 00-0 --00 00-0 --00
512h
— — Unimplemented — —
514h
515h OPA2CON OPA2EN OPA2SP — OPA2UG — — OPA2PCH<1:0> 00-0 --00 00-0 --00
516h
— — Unimplemented — —
51Fh
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: Unimplemented, read as ‘1’.
2: PIC16(L)F1704 only.
3: PIC16(L)F1708 only.
4: Unimplemented on PIC16LF1704/8.

 2013-2015 Microchip Technology Inc. DS40001715D-page 35

PIC16(L)F1704/8
TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on all
Value on
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other
POR, BOR
Resets

Bank 11
D8Ch
to — Unimplemented — —
DADh
Bank 12
60Ch
to — Unimplemented — —
616h
617h PWM3DCL PWM3DC<1:0> — — — — — — xx-- ---- uu-- ----
618h PWM3DCH PWM3DC<9:2> xxxx xxxx uuuu uuuu
619h PWM3CON PWM3EN — PWM3OUT PWM3POL — — — — 0-x0 ---- u-uu ----
61Ah PWM4DCL PWM4DC<1:0> — — — — — — 00-- ---- uu-- ----
61Bh PWM4DCH PWM4DC<9:2> 0000 0000 uuuu uuuu
61Ch PWM4CON PWM4EN — PWM4OUT PWM4POL — — — — 0-x0 ---- u-uu ----
61Dh
— — Unimplemented — —
61Fh
Bank 13
68Ch
to — Unimplemented — —
690h
691h COG1PHR — — COG Rising Edge Phase Counter Register --xx xxxx --uu uuuu
692h COG1PHF — — COG Falling Edge Phase Counter Register --xx xxxx --uu uuuu
693h COG1BLKR — — COG Rising Edge Blanking Counter Register --xx xxxx --uu uuuu
694h COG1BLKF — — COG Falling Edge Blanking Counter Register --xx xxxx --uu uuuu
695h COG1DBR — — COG Rising Edge Dead-band Counter Register --xx xxxx --uu uuuu
696h COG1DBF — — COG Falling Edge Dead-band Counter Register --xx xxxx --uu uuuu
697h COG1CON0 G1EN G1LD — G1CS<1:0> G1MD<2:0> 00-0 0000 00-0 0000
698h COG1CON1 G1RDBS G1FDBS — — G1POLD G1POLC G1POLB G1POLA 00-- 0000 00-- 0000
699h COG1RIS — G1RIS6 G1RIS5 G1RIS4 G1RIS3 G1RIS2 G1RIS1 G1RIS0 -000 0000 -000 0000

69Ah COG1RSIM — G1RSIM6 G1RSIM5 G1RSIM4 G1RSIM3 G1RSIM2 G1RSIM1 G1RSIM0 -000 0000 -000 0000

69Bh COG1FIS — G1FIS6 G1FIS5 G1FIS4 G1FIS3 G1FIS2 G1FIS1 G1FIS0 -000 0000 -000 0000

69Ch COG1FSIM — G1FSIM6 G1FSIM5 G1FSIM4 G1FSIM3 G1FSIM2 G1FSIM1 G1FSIM0 -000 0000 -000 0000

69Dh COG1ASD0 G1ASE G1ARSEN G1ASDBD<1:0> G1ASDAC<1:0> — — 0001 01-- 0001 01--
69Eh COG1ASD1 — — — — G1AS3E G1AS2E G1AS1E G1AS0E ---- 0000 ---- 0000
69Fh COG1STR G1SDATD G1SDATC G1SDATB G1SDATA G1STRD G1STRC G1STRB G1STRA 0000 0001 0000 0001

Bank 14-27
x0Ch/ — Unimplemented — —
x8Ch
—
x1Fh/
x9Fh
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: Unimplemented, read as ‘1’.
2: PIC16(L)F1704 only.
3: PIC16(L)F1708 only.
4: Unimplemented on PIC16LF1704/8.

DS40001715D-page 36  2013-2015 Microchip Technology Inc.

 PIC16(L)F1704/8
TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on all
Value on
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other
POR, BOR
Resets

Bank 28
E0Ch
— — Unimplemented — —
E0Eh
E0Fh PPSLOCK — — — — — — — PPSLOCKED ---- ---0 ---- ---0
E10h INTPPS — — — INTPPS<4:0> ---0 0010 ---u uuuu
E11h T0CKIPPS — — — T0CKIPPS<4:0> ---0 0010 ---u uuuu
E12h T1CKIPPS — — — T1CKIPPS<4:0> ---0 0101 ---u uuuu
E13h T1GPPS — — — T1GPPS<4:0> ---0 0100 ---u uuuu
E14h CCP1PPS — — — CCP1PPS<4:0> ---1 0101 ---u uuuu
E15h CCP2PPS — — — CCP2PPS<4:0> ---1 0011 ---u uuuu
E16h — Unimplemented — —
E17h COGINPPS — — — COGINPPS<4:0> ---0 0010 ---u uuuu
E18h
— — Unimplemented — —
E1Fh
— — — SSPCLKPPS<4:0> ---1 0000(3) ---u uuuu
E20h SSPCLKPPS
— — — SSPCLKPPS<4:0> ---0 1110(4) ---u uuuu
— — — SSPDATPPS<4:0> ---1 0001(3) ---u uuuu
E21h SSPDATPPS
— — — SSPDATPPS<4:0> ---0 1100(4) ---u uuuu
— — — SSPSSPPS<4:0> ---1 0011(3) ---u uuuu
E22h SSPSSPPS
— — — SSPSSPPS<4:0> ---1 0110(4) ---u uuuu
E23h — Unimplemented — —
— — — RXPPS<4:0> ---1 0101(3) ---u uuuu
E24h RXPPS
— — — RXPPS<4:0> ---0 1101(4) ---u uuuu
— — — CKPPS<4:0> ---1 0100(3) ---u uuuu
E25h CKPPS
— — — CKPPS<4:0> ---0 1111(4) ---u uuuu
E26h — Unimplemented — —
E27h — Unimplemented — —
E28h CLCIN0PPS — — — CLCIN0PPS<4:0> ---1 0011 ---u uuuu
E29h CLCIN1PPS — — — CLCIN1PPS<4:0> ---1 0100 ---u uuuu
E2Ah CLCIN2PPS — — — CLCIN2PPS<4:0> ---1 0001 ---u uuuu
E2Bh CLCIN3PPS — — — CLCIN3PPS<4:0> ---0 0101 ---u uuuu
E2Ch
to — Unimplemented — —
E7Fh
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: Unimplemented, read as ‘1’.
2: PIC16(L)F1704 only.
3: PIC16(L)F1708 only.
4: Unimplemented on PIC16LF1704/8.

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PIC16(L)F1704/8
TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on all
Value on
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other
POR, BOR
Resets

Bank 29
E8Ch
—
E8Fh — Unimplemented — —
E90h RA0PPS — — — RA0PPS<4:0> ---0 0000 ---u uuuu
E91h RA1PPS — — — RA1PPS<4:0> ---0 0000 ---u uuuu
E92h RA2PPS — — — RA2PPS<4:0> ---0 0000 ---u uuuu
E93h — Unimplemented — —
E94h RA4PPS — — — RA4PPS<4:0> ---0 0000 ---u uuuu
E95h RA5PPS — — — RA5PPS<4:0> ---0 0000 ---u uuuu
E96h — Unimplemented — —
E97h — Unimplemented — —
E98h — Unimplemented — —
E99h — Unimplemented — —
E9Ah — Unimplemented — —
E9Bh — Unimplemented — —

E9Ch RB4PPS (3) — — — RB4PPS<4:0> ---0 0000 ---u uuuu

E9Dh RB5PPS(3) — — — RB5PPS<4:0> ---0 0000 ---u uuuu

E9Eh RB6PPS (4) — — — RB6PPS<4:0> ---0 0000 ---u uuuu

E9Fh RB7PPS(3) — — — RB7PPS<4:0> ---0 0000 ---u uuuu

EA0h RC0PPS — — — RC0PPS<4:0> ---0 0000 ---u uuuu
EA1h RC1PPS — — — RC1PPS<4:0> ---0 0000 ---u uuuu
EA2h RC2PPS — — — RC2PPS<4:0> ---0 0000 ---u uuuu
EA3h RC3PPS — — — RC3PPS<4:0> ---0 0000 ---u uuuu
EA4h RC4PPS — — — RC4PPS<4:0> ---0 0000 ---u uuuu
EA5h RC5PPS — — — RC5PPS<4:0> ---0 0000 ---u uuuu

EA6h RC6PPS (4) — — — RC6PPS<4:0> ---0 0000 ---u uuuu

EA7h RC7PPS(4) — — — RC7PPS<4:0> ---0 0000 ---u uuuu

EA8h
—
EEFh — Unimplemented — —
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: Unimplemented, read as ‘1’.
2: PIC16(L)F1704 only.
3: PIC16(L)F1708 only.
4: Unimplemented on PIC16LF1704/8.

DS40001715D-page 38  2013-2015 Microchip Technology Inc.

 PIC16(L)F1704/8
TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on all
Value on
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other
POR, BOR
Resets

Bank 30
F0Ch
—
F0Eh — Unimplemented — —
F0Fh CLCDATA — — — — — MLC3OUT MLC2OUT MLC1OUT ---- -000 ---- -000
F10h CLC1CON LC1EN — LC1OUT LC1INTP LC1INTN LC1MODE<2:0> 0-x0 0000 0-00 0000
F11h CLC1POL LC1POL — — — LC1G4POL LC1G3POL LC1G2POL LC1G1POL x--- xxxx 0--- uuuu
F12h CLC1SEL0 — — — LC1D1S<4:0> ---x xxxx ---u uuuu
F13h CLC1SEL1 — — — LC1D2S<4:0> ---x xxxx ---u uuuu
F14h CLC1SEL2 — — — LC1D3S<4:0> ---x xxxx ---u uuuu
F15h CLC1SEL3 — — — LC1D4S<4:0> ---x xxxx ---u uuuu
F16h CLC1GLS0 LC1G1D4T LC1G1D4N LC1G1D3T LC1G1D3N LC1G1D2T LC1G1D2N LC1G1D1T LC1G1D1N xxxx xxxx uuuu uuuu
F17h CLC1GLS1 LC1G2D4T LC1G2D4N LC1G2D3T LC1G2D3N LC1G2D2T LC1G2D2N LC1G2D1T LC1G2D1N xxxx xxxx uuuu uuuu
F18h CLC1GLS2 LC1G3D4T LC1G3D4N LC1G3D3T LC1G3D3N LC1G3D2T LC1G3D2N LC1G3D1T LC1G3D1N xxxx xxxx uuuu uuuu
F19h CLC1GLS3 LC1G4D4T LC1G4D4N LC1G4D3T LC1G4D3N LC1G4D2T LC1G4D2N LC1G4D1T LC1G4D1N xxxx xxxx uuuu uuuu
F1Ah CLC2CON LC2EN — LC2OUT LC2INTP LC2INTN LC2MODE<2:0> 0-00 0000 0-00 0000
F1Bh CLC2POL LC2POL — — — LC2G4POL LC2G3POL LC2G2POL LC2G1POL 0--- xxxx 0--- uuuu
F1Ch CLC2SEL0 — — — LC2D1S<4:0> ---x xxxx ---u uuuu
F1Dh CLC2SEL1 — — — LC2D2S<4:0> ---x xxxx ---u uuuu
F1Eh CLC2SEL2 — — — LC2D3S<4:0> ---x xxxx ---u uuuu
F1Fh CLC2SEL3 — — — LC2D4S<4:0> ---x xxxx ---u uuuu
F20h CLC2GLS0 LC2G1D4T LC2G1D4N LC2G1D3T LC2G1D3N LC2G1D2T LC2G1D2N LC2G1D1T LC2G1D1N xxxx xxxx uuuu uuuu
F21h CLC2GLS1 LC2G2D4T LC2G2D4N LC2G2D3T LC2G2D3N LC2G2D2T LC2G2D2N LC2G2D1T LC2G2D1N xxxx xxxx uuuu uuuu
F22h CLC2GLS2 LC2G3D4T LC2G3D4N LC2G3D3T LC2G3D3N LC2G3D2T LC2G3D2N LC2G3D1T LC2G3D1N xxxx xxxx uuuu uuuu
F23h CLC2GLS3 LC2G4D4T LC2G4D4N LC2G4D3T LC2G4D3N LC2G4D2T LC2G4D2N LC2G4D1T LC2G4D1N xxxx xxxx uuuu uuuu
F24h CLC3CON LC3EN — LC3OUT LC3INTP LC3INTN LC3MODE<2:0> 0-00 0000 0-00 0000
F25h CLC3POL LC3POL — — — LC3G4POL LC3G3POL LC3G2POL LC3G1POL 0--- xxxx 0--- uuuu
F26h CLC3SEL0 — — — LC3D1S<4:0> ---x xxxx ---u uuuu
F27h CLC3SEL1 — — — LC3D2S<4:0> ---x xxxx ---u uuuu
F28h CLC3SEL2 — — — LC3D3S<4:0> ---x xxxx ---u uuuu
F29h CLC3SEL3 — — — LC3D4S<4:0> ---x xxxx ---u uuuu
F2Ah CLC3GLS0 LC3G1D4T LC3G1D4N LC3G1D3T LC3G1D3N LC3G1D2T LC3G1D2N LC3G1D1T LC3G1D1N xxxx xxxx uuuu uuuu
F2Bh CLC3GLS1 LC3G2D4T LC3G2D4N LC3G2D3T LC3G2D3N LC3G2D2T LC3G2D2N LC3G2D1T LC3G2D1N xxxx xxxx uuuu uuuu
F2Ch CLC3GLS2 LC3G3D4T LC3G3D4N LC3G3D3T LC3G3D3N LC3G3D2T LC3G3D2N LC3G3D1T LC3G3D1N xxxx xxxx uuuu uuuu
F2Dh CLC3GLS3 LC3G4D4T LC3G4D4N LC3G4D3T LC3G4D3N LC3G4D2T LC3G4D2N LC3G4D1T LC3G4D1N xxxx xxxx uuuu uuuu
F2Eh
— — Unimplemented — —
F6Fh
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: Unimplemented, read as ‘1’.
2: PIC16(L)F1704 only.
3: PIC16(L)F1708 only.
4: Unimplemented on PIC16LF1704/8.

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PIC16(L)F1704/8
TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on all
Value on
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other
POR, BOR
Resets

Bank 31
F8Ch
to — Unimplemented — —
FE3h
FE4h STATUS_ — — — — — Z DC C ---- -xxx ---- -uuu
SHAD
FE5h WREG_ Working Register Shadow xxxx xxxx uuuu uuuu
SHAD
FE6h BSR_SHAD — — — Bank Select Register Shadow ---x xxxx ---u uuuu
FE7h PCLATH_ — Program Counter Latch High Register Shadow -xxx xxxx uuuu uuuu
SHAD
FE8h FSR0L_ Indirect Data Memory Address 0 Low Pointer Shadow xxxx xxxx uuuu uuuu
SHAD
FE9h FSR0H_ Indirect Data Memory Address 0 High Pointer Shadow xxxx xxxx uuuu uuuu
SHAD
FEAh FSR1L_ Indirect Data Memory Address 1 Low Pointer Shadow xxxx xxxx uuuu uuuu
SHAD
FEBh FSR1H_ Indirect Data Memory Address 1 High Pointer Shadow xxxx xxxx uuuu uuuu
SHAD
FECh — Unimplemented — —
FEDh STKPTR — — — Current Stack Pointer ---1 1111 ---1 1111
FEEh TOSL Top of Stack Low byte xxxx xxxx uuuu uuuu
FEFh TOSH — Top of Stack High byte -xxx xxxx -uuu uuuu
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: Unimplemented, read as ‘1’.
2: PIC16(L)F1704 only.
3: PIC16(L)F1708 only.
4: Unimplemented on PIC16LF1704/8.

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3.5 PCL and PCLATH 3.5.3 COMPUTED FUNCTION CALLS
The Program Counter (PC) is 15 bits wide. The low byte A computed function CALL allows programs to maintain
comes from the PCL register, which is a readable and tables of functions and provide another way to execute
writable register. The high byte (PC<14:8>) is not directly state machines or look-up tables. When performing a
readable or writable and comes from PCLATH. On any table read using a computed function CALL, care
Reset, the PC is cleared. Figure 3-3 shows the five should be exercised if the table location crosses a PCL
situations for the loading of the PC. memory boundary (each 256-byte block).
If using the CALL instruction, the PCH<2:0> and PCL
FIGURE 3-3: LOADING OF PC IN registers are loaded with the operand of the CALL
DIFFERENT SITUATIONS instruction. PCH<6:3> is loaded with PCLATH<6:3>.
The CALLW instruction enables computed calls by
14 PCH PCL 0 Instruction with
combining PCLATH and W to form the destination
PC PCL as
Destination address. A computed CALLW is accomplished by
7 8 loading the W register with the desired address and
6 0
PCLATH ALU Result executing CALLW. The PCL register is loaded with the
value of W and PCH is loaded with PCLATH.
14 PCH PCL 0 3.5.4 BRANCHING
PC GOTO, CALL
The branching instructions add an offset to the PC.
6 4 0 11 This allows relocatable code and code that crosses
PCLATH OPCODE <10:0> page boundaries. There are two forms of branching,
BRW and BRA. The PC will have incremented to fetch
14 PCH PCL 0
PC CALLW the next instruction in both cases. When using either
branching instruction, a PCL memory boundary may be
6 7 0 8 crossed.
PCLATH W
If using BRW, load the W register with the desired
unsigned address and execute BRW. The entire PC will
14 PCH PCL 0
PC BRW be loaded with the address PC + 1 + W.
If using BRA, the entire PC will be loaded with PC + 1 +,
15 the signed value of the operand of the BRA instruction.
PC + W

14 PCH PCL 0
PC BRA

15
PC + OPCODE <8:0>

3.5.1 MODIFYING PCL

Executing any instruction with the PCL register as the
destination simultaneously causes the Program
Counter PC<14:8> bits (PCH) to be replaced by the
contents of the PCLATH register. This allows the entire
contents of the program counter to be changed by
writing the desired upper seven bits to the PCLATH
register. When the lower eight bits are written to the
PCL register, all 15 bits of the program counter will
change to the values contained in the PCLATH register
and those being written to the PCL register.

3.5.2 COMPUTED GOTO

A computed GOTO is accomplished by adding an offset to
the program counter (ADDWF PCL). When performing a
table read using a computed GOTO method, care should
be exercised if the table location crosses a PCL memory
boundary (each 256-byte block). Refer to Application
Note AN556, “Implementing a Table Read” (DS00556).

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3.6 Stack 3.6.1 ACCESSING THE STACK
All devices have a 16-level x 15-bit wide hardware The stack is available through the TOSH, TOSL and
stack (refer to Figure 3-1). The stack space is not part STKPTR registers. STKPTR is the current value of the
of either program or data space. The PC is PUSHed Stack Pointer. TOSH:TOSL register pair points to the
onto the stack when CALL or CALLW instructions are TOP of the stack. Both registers are read/writable. TOS
executed or an interrupt causes a branch. The stack is is split into TOSH and TOSL due to the 15-bit size of the
POPed in the event of a RETURN, RETLW or a RETFIE PC. To access the stack, adjust the value of STKPTR,
instruction execution. PCLATH is not affected by a which will position TOSH:TOSL, then read/write to
PUSH or POP operation. TOSH:TOSL. STKPTR is five bits to allow detection of
overflow and underflow.
The stack operates as a circular buffer if the STVREN
bit is programmed to ‘0‘ (Configuration Words). This Note: Care should be taken when modifying the
means that after the stack has been PUSHed sixteen STKPTR while interrupts are enabled.
times, the seventeenth PUSH overwrites the value that
During normal program operation, CALL, CALLW and
was stored from the first PUSH. The eighteenth PUSH
Interrupts will increment STKPTR while RETLW,
overwrites the second PUSH (and so on). The
RETURN, and RETFIE will decrement STKPTR. At any
STKOVF and STKUNF flag bits will be set on an Over-
time, STKPTR can be inspected to see how much
flow/Underflow, regardless of whether the Reset is
stack is left. The STKPTR always points at the currently
enabled.
used place on the stack. Therefore, a CALL or CALLW
Note: There are no instructions/mnemonics will increment the STKPTR and then write the PC, and
called PUSH or POP. These are actions a return will unload the PC and then decrement the
that occur from the execution of the CALL, STKPTR.
CALLW, RETURN, RETLW and RETFIE Reference Figure 3-4 through Figure 3-7 for examples
instructions or the vectoring to an interrupt of accessing the stack.
address.

FIGURE 3-4: ACCESSING THE STACK EXAMPLE 1

Stack Reset Disabled

TOSH:TOSL 0x0F STKPTR = 0x1F
(STVREN = 0)
0x0E
0x0D
0x0C
0x0B
0x0A
Initial Stack Configuration:
0x09
After Reset, the stack is empty. The
0x08 empty stack is initialized so the Stack
Pointer is pointing at 0x1F. If the Stack
0x07
Overflow/Underflow Reset is enabled, the
0x06 TOSH/TOSL registers will return ‘0’. If
the Stack Overflow/Underflow Reset is
0x05 disabled, the TOSH/TOSL registers will
return the contents of stack address 0x0F.
0x04
0x03
0x02
0x01
0x00
Stack Reset Enabled
TOSH:TOSL 0x1F 0x0000 STKPTR = 0x1F
(STVREN = 1)

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FIGURE 3-5: ACCESSING THE STACK EXAMPLE 2

0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09 This figure shows the stack configuration
after the first CALL or a single interrupt.
0x08 If a RETURN instruction is executed, the
0x07 return address will be placed in the
Program Counter and the Stack Pointer
0x06 decremented to the empty state (0x1F).

0x05
0x04
0x03
0x02
0x01
TOSH:TOSL 0x00 Return Address STKPTR = 0x00

FIGURE 3-6: ACCESSING THE STACK EXAMPLE 3

0x0F
0x0E
0x0D
0x0C
After seven CALLs or six CALLs and an
0x0B interrupt, the stack looks like the figure
on the left. A series of RETURN instructions
0x0A will repeatedly place the return addresses
into the Program Counter and pop the stack.
0x09
0x08

0x07
TOSH:TOSL 0x06 Return Address STKPTR = 0x06

0x05 Return Address

0x04 Return Address
0x03 Return Address
0x02 Return Address
0x01 Return Address
0x00 Return Address

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FIGURE 3-7: ACCESSING THE STACK EXAMPLE 4

0x0F Return Address

0x0E Return Address

0x0D Return Address

0x0C Return Address

0x0B Return Address

0x0A Return Address

When the stack is full, the next CALL or
0x09 Return Address an interrupt will set the Stack Pointer to
0x10. This is identical to address 0x00
0x08 Return Address so the stack will wrap and overwrite the
return address at 0x00. If the Stack
0x07 Return Address Overflow/Underflow Reset is enabled, a
Reset will occur and location 0x00 will
0x06 Return Address not be overwritten.
0x05 Return Address

0x04 Return Address

0x03 Return Address

0x02 Return Address

0x01 Return Address

TOSH:TOSL 0x00 Return Address STKPTR = 0x10

3.6.2 OVERFLOW/UNDERFLOW RESET

If the STVREN bit in Configuration Words is
programmed to ‘1’, the device will be reset if the stack
is PUSHed beyond the sixteenth level or POPed
beyond the first level, setting the appropriate bits
(STKOVF or STKUNF, respectively) in the PCON
register.

3.7 Indirect Addressing

The INDFn registers are not physical registers. Any
instruction that accesses an INDFn register actually
accesses the register at the address specified by the
File Select Registers (FSR). If the FSRn address
specifies one of the two INDFn registers, the read will
return ‘0’ and the write will not occur (though Status bits
may be affected). The FSRn register value is created
by the pair FSRnH and FSRnL.
The FSR registers form a 16-bit address that allows an
addressing space with 65536 locations. These locations
are divided into three memory regions:
• Traditional Data Memory
• Linear Data Memory
• Program Flash Memory

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FIGURE 3-8: INDIRECT ADDRESSING

0x0000 0x0000

Traditional
Data Memory

0x0FFF 0x0FFF
0x1000
Reserved
0x1FFF
0x2000

Linear
Data Memory

0x29AF
0x29B0
FSR Reserved
0x7FFF
Address
Range 0x8000 0x0000

Program
Flash Memory

0xFFFF 0x7FFF

Note: Not all memory regions are completely implemented. Consult device memory tables for memory limits.

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3.7.1 TRADITIONAL DATA MEMORY
The traditional data memory is a region from FSR
address 0x000 to FSR address 0xFFF. The addresses
correspond to the absolute addresses of all SFR, GPR
and common registers.

FIGURE 3-9: TRADITIONAL DATA MEMORY MAP

Direct Addressing Indirect Addressing

4 BSR 0 6 From Opcode 0 7 FSRxH 0 7 FSRxL 0

0 0 0 0

Bank Select Location Select Bank Select Location Select

00000 00001 00010 11111
0x00

0x7F
Bank 0 Bank 1 Bank 2 Bank 31

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3.7.2 LINEAR DATA MEMORY 3.7.3 PROGRAM FLASH MEMORY
The linear data memory is the region from FSR To make constant data access easier, the entire
address 0x2000 to FSR address 0x29AF. This region is Program Flash Memory is mapped to the upper half of
a virtual region that points back to the 80-byte blocks of the FSR address space. When the MSB of FSRnH is
GPR memory in all the banks. set, the lower 15 bits are the address in program
Unimplemented memory reads as 0x00. Use of the memory which will be accessed through INDF. Only the
linear data memory region allows buffers to be larger lower eight bits of each memory location is accessible
than 80 bytes because incrementing the FSR beyond via INDF. Writing to the Program Flash Memory cannot
one bank will go directly to the GPR memory of the next be accomplished via the FSR/INDF interface. All
bank. instructions that access Program Flash Memory via the
FSR/INDF interface will require one additional
The 16 bytes of common memory are not included in instruction cycle to complete.
the linear data memory region.
FIGURE 3-11: PROGRAM FLASH
FIGURE 3-10: LINEAR DATA MEMORY MEMORY MAP
MAP
7 FSRnH 0 7 FSRnL 0
7 FSRnH 0 7 FSRnL 0 1
0 0 1
Location Select 0x8000 0x0000
Location Select 0x2000 0x020
Bank 0
0x06F
0x0A0
Bank 1
Program
0x0EF Flash
0x120 Memory
Bank 2 (low 8
bits)
0x16F

0xF20
Bank 30 0x7FFF
0xFFFF
0x29AF 0xF6F

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4.0 DEVICE CONFIGURATION
Device configuration consists of Configuration Words,
Code Protection and Device ID.

4.1 Configuration Words

There are several Configuration Word bits that allow
different oscillator and memory protection options.
These are implemented as Configuration Word 1 at
8007h and Configuration Word 2 at 8008h.
Note: The DEBUG bit in Configuration Words is
managed automatically by device
development tools including debuggers
and programmers. For normal device
operation, this bit should be maintained as
a ‘1’.

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4.2 Register Definitions: Configuration Words

REGISTER 4-1: CONFIG1: CONFIGURATION WORD 1

R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 U-1
FCMEN IESO CLKOUTEN BOREN<1:0> —
bit 13 bit 8

R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1

(1)
CP MCLRE PWRTE WDTE<1:0> FOSC<2:0>
bit 7 bit 0

Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’
‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase

bit 13 FCMEN: Fail-Safe Clock Monitor Enable bit

1 = Fail-Safe Clock Monitor and internal/external switchover are both enabled.
0 = Fail-Safe Clock Monitor is disabled
bit 12 IESO: Internal External Switchover bit
1 = Internal/External Switchover mode is enabled
0 = Internal/External Switchover mode is disabled
bit 11 CLKOUTEN: Clock Out Enable bit
If FOSC configuration bits are set to LP, XT, HS modes:
This bit is ignored, CLKOUT function is disabled. Oscillator function on the CLKOUT pin.
All other FOSC modes:
1 = CLKOUT function is disabled. I/O function on the CLKOUT pin.
0 = CLKOUT function is enabled on the CLKOUT pin
bit 10-9 BOREN<1:0>: Brown-out Reset Enable bits
11 = BOR enabled
10 = BOR enabled during operation and disabled in Sleep
01 = BOR controlled by SBOREN bit of the BORCON register
00 = BOR disabled
bit 8 Unimplemented: Read as ‘1’
bit 7 CP: Code Protection bit(1)
1 = Program memory code protection is disabled
0 = Program memory code protection is enabled
bit 6 MCLRE: MCLR/VPP Pin Function Select bit
If LVP bit = 1:
This bit is ignored.
If LVP bit = 0:
1 = MCLR/VPP pin function is MCLR; Weak pull-up enabled.
0 = MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of
WPUE3 bit.
bit 5 PWRTE: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
bit 4-3 WDTE<1:0>: Watchdog Timer Enable bit
11 = WDT enabled
10 = WDT enabled while running and disabled in Sleep
01 = WDT controlled by the SWDTEN bit in the WDTCON register
00 = WDT disabled

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REGISTER 4-1: CONFIG1: CONFIGURATION WORD 1 (CONTINUED)
bit 2-0 FOSC<2:0>: Oscillator Selection bits
111 = ECH: External Clock, High-Power mode (4-20 MHz): device clock supplied to CLKIN pin
110 = ECM: External Clock, Medium-Power mode (0.5-4 MHz): device clock supplied to CLKIN pin
101 = ECL: External Clock, Low-Power mode (0-0.5 MHz): device clock supplied to CLKIN pin
100 = INTOSC oscillator: I/O function on CLKIN pin
011 = EXTRC oscillator: External RC circuit connected to CLKIN pin
010 = HS oscillator: High-speed crystal/resonator connected between OSC1 and OSC2 pins
001 = XT oscillator: Crystal/resonator connected between OSC1 and OSC2 pins
000 = LP oscillator: Low-power crystal connected between OSC1 and OSC2 pins

Note 1: The entire Flash program memory will be erased when the code protection is turned off during an erase.
When a Bulk Erase Program Memory Command is executed, the entire Program Flash Memory and
configuration memory will be erased.

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REGISTER 4-2: CONFIG2: CONFIGURATION WORD 2

R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
(1) (2) (3)
LVP DEBUG LPBOR BORV STVREN PLLEN
bit 13 bit 8

R/P-1 U-1 U-1 U-1 U-1 R/P-1 R/P-1 R/P-1

ZCDDIS — — — — PPS1WAY WRT<1:0>
bit 7 bit 0

Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’
‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase

bit 13 LVP: Low-Voltage Programming Enable bit(1)

1 = Low-voltage programming enabled
0 = High-voltage on MCLR must be used for programming
bit 12 DEBUG: In-Circuit Debugger Mode bit(2)
1 = In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins
0 = In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger
bit 11 LPBOR: Low-Power BOR Enable bit
1 = Low-Power Brown-out Reset is disabled
0 = Low-Power Brown-out Reset is enabled
bit 10 BORV: Brown-out Reset Voltage Selection bit(3)
1 = Brown-out Reset voltage (VBOR), low trip point selected.
0 = Brown-out Reset voltage (VBOR), high trip point selected.
bit 9 STVREN: Stack Overflow/Underflow Reset Enable bit
1 = Stack Overflow or Underflow will cause a Reset
0 = Stack Overflow or Underflow will not cause a Reset
bit 8 PLLEN: PLL Enable bit
1 = 4xPLL enabled
0 = 4xPLL disabled
bit 7 ZCDDIS: ZCD Disable bit
1 = ZCD disabled. ZCD can be enabled by setting the ZCDSEN bit of ZCDCON
0 = ZCD always enabled
bit 6-3 Unimplemented: Read as ‘1’
bit 2 PPS1WAY: PPSLOCK Bit One-Way Set Enable bit
1 = The PPSLOCK bit can only be set once after an unlocking sequence is executed; once PPSLOCK is set, all
future changes to PPS registers are prevented
0 = The PPSLOCK bit can be set and cleared as needed (provided an unlocking sequence is executed)
bit 1-0 WRT<1:0>: Flash Memory Self-Write Protection bits
4 kW Flash memory
11 = Write protection off
10 = 000h to 1FFh write protected, 200h to FFFh may be modified by PMCON control
01 = 000h to 7FFh write protected, 800h to FFFh may be modified by PMCON control
00 = 000h to FFFh write protected, no addresses may be modified by PMCON control

Note 1: The LVP bit cannot be programmed to ‘0’ when Programming mode is entered via LVP.
2: The DEBUG bit in Configuration Words is managed automatically by device development tools including debuggers
and programmers. For normal device operation, this bit should be maintained as a ‘1’.
3: See VBOR parameter for specific trip point voltages.

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4.3 Code Protection
Code protection allows the device to be protected from
unauthorized access. Program memory protection is
controlled independently. Internal access to the
program memory is unaffected by any code protection
setting.

4.3.1 PROGRAM MEMORY PROTECTION

The entire program memory space is protected from
external reads and writes by the CP bit in Configuration
Words. When CP = 0, external reads and writes of
program memory are inhibited and a read will return all
‘0’s. The CPU can continue to read program memory,
regardless of the protection bit settings. Writing the
program memory is dependent upon the write
protection setting. See Section 4.4 “Write
Protection” for more information.

4.4 Write Protection

Write protection allows the device to be protected from
unintended self-writes. Applications, such as boot
loader software, can be protected while allowing other
regions of the program memory to be modified.
The WRT<1:0> bits in Configuration Words define the
size of the program memory block that is protected.

4.5 User ID
Four memory locations (8000h-8003h) are designated
as ID locations where the user can store checksum or
other code identification numbers. These locations are
readable and writable during normal execution. See
Section 10.4 “User ID, Device ID and Configuration
Word Access” for more information on accessing
these memory locations. For more information on
checksum calculation, see the “PIC16(L)F170X
Memory Programming Specification” (DS41683).

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4.6 Device ID and Revision ID
The 14-bit device ID word is located at 8006h and the
14-bit revision ID is located at 8005h. These locations
are read-only and cannot be erased or modified. See
Section 10.4 “User ID, Device ID and Configuration
Word Access” for more information on accessing
these memory locations.
Development tools, such as device programmers and
debuggers, may be used to read the Device ID and
Revision ID.

4.7 Register Definitions: Device and Revision

REGISTER 4-3: DEVID: DEVICE ID REGISTER

R R R R R R
DEV<13:8>
bit 13 bit 8

R R R R R R R R
DEV<7:0>
bit 7 bit 0

Legend:
R = Readable bit
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 13-0 DEV<13:0>: Device ID bits

Device DEVID<13:0> Values

PIC16F1704 11 0000 0100 0011 (3043h)
PIC16LF1704 11 0000 0100 0101 (3045h)
PIC16F1708 11 0000 0100 0010 (3042h)
PIC16LF1708 11 0000 0100 0100 (3044h)

REGISTER 4-4: REVID: REVISION ID REGISTER

R R R R R R
REV<13:8>
bit 13 bit 8

R R R R R R R R
REV<7:0>
bit 7 bit 0

Legend:
R = Readable bit
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 13-0 REV<13:0>: Revision ID bits

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5.0 RESETS
There are multiple ways to reset this device:
• Power-On Reset (POR)
• Brown-Out Reset (BOR)
• Low-Power Brown-Out Reset (LPBOR)
• MCLR Reset
• WDT Reset
• RESET instruction
• Stack Overflow
• Stack Underflow
• Programming mode exit
To allow VDD to stabilize, an optional power-up timer
can be enabled to extend the Reset time after a BOR
or POR event.
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 5-1.

FIGURE 5-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

ICSP™ Programming Mode Exit

RESET Instruction

Stack Underflow
Stack Overlfow

MCLRE
VPP/MCLR
Sleep

WDT
Time-out Device
Reset

Power-on
Reset
VDD
BOR
Active(1)
Brown-out R
PWRT
Reset
Done

LFINTOSC
LPBOR PWRTE
Reset

Note 1: See Table 5-1 for BOR active conditions.

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5.1 Power-On Reset (POR) 5.2 Brown-Out Reset (BOR)
The POR circuit holds the device in Reset until VDD has The BOR circuit holds the device in Reset when VDD
reached an acceptable level for minimum operation. reaches a selectable minimum level. Between the
Slow rising VDD, fast operating speeds or analog POR and BOR, complete voltage range coverage for
performance may require greater than minimum VDD. execution protection can be implemented.
The PWRT, BOR or MCLR features can be used to The Brown-out Reset module has four operating
extend the start-up period until all device operation modes controlled by the BOREN<1:0> bits in
conditions have been met. Configuration Words. The four operating modes are:
5.1.1 POWER-UP TIMER (PWRT) • BOR is always on
The Power-up Timer provides a nominal 64 ms • BOR is off when in Sleep
time-out on POR or Brown-out Reset. • BOR is controlled by software
The device is held in Reset as long as PWRT is active. • BOR is always off
The PWRT delay allows additional time for the VDD to Refer to Table 5-1 for more information.
rise to an acceptable level. The Power-up Timer is The Brown-out Reset voltage level is selectable by
enabled by clearing the PWRTE bit in Configuration configuring the BORV bit in Configuration Words.
Words.
A VDD noise rejection filter prevents the BOR from
The Power-up Timer starts after the release of the POR triggering on small events. If VDD falls below VBOR for
and BOR. a duration greater than parameter TBORDC, the device
For additional information, refer to Application Note will reset. See Figure 5-2 for more information.
AN607, “Power-up Trouble Shooting” (DS00607).

TABLE 5-1: BOR OPERATING MODES

Instruction Execution upon:
BOREN<1:0> SBOREN Device Mode BOR Mode
Release of POR or Wake-up from Sleep

11 X X Active Waits for BOR ready(1) (BORRDY = 1)

Awake Active
10 X Waits for BOR ready (BORRDY = 1)
Sleep Disabled
1 X Active Waits for BOR ready(1) (BORRDY = 1)
01
0 X Disabled
Begins immediately (BORRDY = x)
00 X X Disabled
Note 1: In these specific cases, “Release of POR” and “Wake-up from Sleep”, there is no delay in start-up. The BOR
ready flag, (BORRDY = 1), will be set before the CPU is ready to execute instructions because the BOR
circuit is forced on by the BOREN<1:0> bits.

5.2.1 BOR IS ALWAYS ON 5.2.3 BOR CONTROLLED BY SOFTWARE

When the BOREN bits of Configuration Words are When the BOREN bits of Configuration Words are
programmed to ‘11’, the BOR is always on. The device programmed to ‘01’, the BOR is controlled by the
start-up will be delayed until the BOR is ready and VDD SBOREN bit of the BORCON register. The device
is higher than the BOR threshold. start-up is not delayed by the BOR ready condition or
BOR protection is active during Sleep. The BOR does the VDD level.
not delay wake-up from Sleep. BOR protection begins as soon as the BOR circuit is
ready. The status of the BOR circuit is reflected in the
5.2.2 BOR IS OFF IN SLEEP BORRDY bit of the BORCON register.
When the BOREN bits of Configuration Words are BOR protection is unchanged by Sleep.
programmed to ‘10’, the BOR is on, except in Sleep.
The device start-up will be delayed until the BOR is
ready and VDD is higher than the BOR threshold.
BOR protection is not active during Sleep. The device
wake-up will be delayed until the BOR is ready.

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FIGURE 5-2: BROWN-OUT SITUATIONS

VDD
VBOR

Internal
Reset TPWRT(1)

VDD
VBOR

Internal < TPWRT

Reset TPWRT(1)

VDD
VBOR

Internal
Reset TPWRT(1)

Note 1: TPWRT delay only if PWRTE bit is programmed to ‘0’.

5.3 Register Definitions: BOR Control

REGISTER 5-1: BORCON: BROWN-OUT RESET CONTROL REGISTER

R/W-1/u R/W-0/u U-0 U-0 U-0 U-0 U-0 R-q/u
SBOREN BORFS(1) — — — — — BORRDY
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7 SBOREN: Software Brown-out Reset Enable bit

If BOREN <1:0> in Configuration Words  01:
SBOREN is read/write, but has no effect on the BOR.
If BOREN <1:0> in Configuration Words = 01:
1 = BOR Enabled
0 = BOR Disabled
bit 6 BORFS: Brown-out Reset Fast Start bit(1)
If BOREN<1:0> = 11 (Always on) or BOREN<1:0> = 00 (Always off)
BORFS is Read/Write, but has no effect.
If BOREN <1:0> = 10 (Disabled in Sleep) or BOREN<1:0> = 01 (Under software control):
1 = Band gap is forced on always (covers sleep/wake-up/operating cases)
0 = Band gap operates normally, and may turn off
bit 5-1 Unimplemented: Read as ‘0’
bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit
1 = The Brown-out Reset circuit is active
0 = The Brown-out Reset circuit is inactive

Note 1: BOREN<1:0> bits are located in Configuration Words.

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5.4 Low-Power Brown-Out Reset 5.6 Watchdog Timer (WDT) Reset
(LPBOR) The Watchdog Timer generates a Reset if the firmware
The Low-Power Brown-Out Reset (LPBOR) is an does not issue a CLRWDT instruction within the time-out
essential part of the Reset subsystem. Refer to period. The TO and PD bits in the STATUS register are
Figure 5-1 to see how the BOR interacts with other changed to indicate the WDT Reset. See Section 9.0
modules. “Watchdog Timer (WDT)” for more information.
The LPBOR is used to monitor the external VDD pin.
When too low of a voltage is detected, the device is 5.7 RESET Instruction
held in Reset. When this occurs, a register bit (BOR) is A RESET instruction will cause a device Reset. The RI
changed to indicate that a BOR Reset has occurred. bit in the PCON register will be set to ‘0’. See Table 5-4
The same bit is set for both the BOR and the LPBOR. for default conditions after a RESET instruction has
Refer to Register 5-2. occurred.
5.4.1 ENABLING LPBOR
5.8 Stack Overflow/Underflow Reset
The LPBOR is controlled by the LPBOR bit of
Configuration Words. When the device is erased, the The device can reset when the Stack Overflows or
LPBOR module defaults to disabled. Underflows. The STKOVF or STKUNF bits of the PCON
register indicate the Reset condition. These Resets are
5.4.1.1 LPBOR Module Output enabled by setting the STVREN bit in Configuration
Words. See 3.6.2 “Overflow/Underflow Reset” for
The output of the LPBOR module is a signal indicating
more information.
whether or not a Reset is to be asserted. This signal is
OR’d together with the Reset signal of the BOR
module to provide the generic BOR signal, which goes 5.9 Programming Mode Exit
to the PCON register and to the power control block. Upon exit of Programming mode, the device will
behave as if a POR had just occurred.
5.5 MCLR
The MCLR is an optional external input that can reset 5.10 Power-Up Timer
the device. The MCLR function is controlled by the The Power-up Timer optionally delays device execution
MCLRE bit of Configuration Words and the LVP bit of after a BOR or POR event. This timer is typically used to
Configuration Words (Table 5-2). allow VDD to stabilize before allowing the device to start
running.
TABLE 5-2: MCLR CONFIGURATION The Power-up Timer is controlled by the PWRTE bit of
MCLRE LVP MCLR Configuration Words.

0 0 Disabled 5.11 Start-up Sequence

1 0 Enabled
Upon the release of a POR or BOR, the following must
x 1 Enabled
occur before the device will begin executing:
5.5.1 MCLR ENABLED 1. Power-up Timer runs to completion (if enabled).
When MCLR is enabled and the pin is held low, the 2. Oscillator start-up timer runs to completion (if
device is held in Reset. The MCLR pin is connected to required for oscillator source).
VDD through an internal weak pull-up. 3. MCLR must be released (if enabled).
The device has a noise filter in the MCLR Reset path. The total time-out will vary based on oscillator configu-
The filter will detect and ignore small pulses. ration and Power-up Timer configuration. See
Section 6.0 “Oscillator Module (with Fail-Safe
Note: A Reset does not drive the MCLR pin low. Clock Monitor)” for more information.
The Power-up Timer and oscillator start-up timer run
5.5.2 MCLR DISABLED
independently of MCLR Reset. If MCLR is kept low
When MCLR is disabled, the pin functions as a general long enough, the Power-up Timer and oscillator
purpose input and the internal weak pull-up is under start-up timer will expire. Upon bringing MCLR high, the
software control. See Section 11.1 “PORTA device will begin execution after 10 FOSC cycles (see
Registers” for more information. Figure 5-3). This is useful for testing purposes or to
synchronize more than one device operating in parallel.

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FIGURE 5-3: RESET START-UP SEQUENCE

VDD

Internal POR

TPWRT
Power-up Timer

MCLR

TMCLR
Internal RESET

Oscillator Modes
External Crystal
TOST
Oscillator Start-up Timer

Oscillator

FOSC

Internal Oscillator

Oscillator

FOSC

External Clock (EC)

CLKIN

FOSC

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5.12 Determining the Cause of a Reset
Upon any Reset, multiple bits in the STATUS and
PCON register are updated to indicate the cause of the
Reset. Table 5-3 and Table 5-4 show the Reset
conditions of these registers.

TABLE 5-3: RESET STATUS BITS AND THEIR SIGNIFICANCE

STKOVF STKUNF RWDT RMCLR RI POR BOR TO PD Condition
0 0 1 1 1 0 x 1 1 Power-on Reset
0 0 1 1 1 0 x 0 x Illegal, TO is set on POR
0 0 1 1 1 0 x x 0 Illegal, PD is set on POR
0 0 u 1 1 u 0 1 1 Brown-out Reset
u u 0 u u u u 0 u WDT Reset
u u u u u u u 0 0 WDT Wake-up from Sleep
u u u u u u u 1 0 Interrupt Wake-up from Sleep
u u u 0 u u u u u MCLR Reset during normal operation
u u u 0 u u u 1 0 MCLR Reset during Sleep
u u u u 0 u u u u RESET Instruction Executed
1 u u u u u u u u Stack Overflow Reset (STVREN = 1)
u 1 u u u u u u u Stack Underflow Reset (STVREN = 1)

TABLE 5-4: RESET CONDITION FOR SPECIAL REGISTERS

Program STATUS PCON
Condition
Counter Register Register
Power-on Reset 0000h ---1 1000 00-- 110x
MCLR Reset during normal operation 0000h ---u uuuu uu-- 0uuu
MCLR Reset during Sleep 0000h ---1 0uuu uu-- 0uuu
WDT Reset 0000h ---0 uuuu uu-- uuuu
WDT Wake-up from Sleep PC + 1 ---0 0uuu uu-- uuuu
Brown-out Reset 0000h ---1 1uuu 00-- 11u0
(1)
Interrupt Wake-up from Sleep PC + 1 ---1 0uuu uu-- uuuu
RESET Instruction Executed 0000h ---u uuuu uu-- u0uu
Stack Overflow Reset (STVREN = 1) 0000h ---u uuuu 1u-- uuuu
Stack Underflow Reset (STVREN = 1) 0000h ---u uuuu u1-- uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on
the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.

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5.13 Power Control (PCON) Register
The Power Control (PCON) register contains flag bits
to differentiate between a:
• Power-on Reset (POR)
• Brown-out Reset (BOR)
• Reset Instruction Reset (RI)
• MCLR Reset (RMCLR)
• Watchdog Timer Reset (RWDT)
• Stack Underflow Reset (STKUNF)
• Stack Overflow Reset (STKOVF)
The PCON register bits are shown in Register 5-2.

5.14 Register Definitions: Power Control

REGISTER 5-2: PCON: POWER CONTROL REGISTER

R/W/HS-0/q R/W/HS-0/q U-0 R/W/HC-1/q R/W/HC-1/q R/W/HC-1/q R/W/HC-q/u R/W/HC-q/u
STKOVF STKUNF — RWDT RMCLR RI POR BOR
bit 7 bit 0

Legend:
HC = Bit is cleared by hardware HS = Bit is set by hardware
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7 STKOVF: Stack Overflow Flag bit

1 = A Stack Overflow occurred
0 = A Stack Overflow has not occurred or cleared by firmware
bit 6 STKUNF: Stack Underflow Flag bit
1 = A Stack Underflow occurred
0 = A Stack Underflow has not occurred or cleared by firmware
bit 5 Unimplemented: Read as ‘0’
bit 4 RWDT: Watchdog Timer Reset Flag bit
1 = A Watchdog Timer Reset has not occurred or set to ‘1’ by firmware
0 = A Watchdog Timer Reset has occurred (cleared by hardware)
bit 3 RMCLR: MCLR Reset Flag bit
1 = A MCLR Reset has not occurred or set to ‘1’ by firmware
0 = A MCLR Reset has occurred (cleared by hardware)
bit 2 RI: RESET Instruction Flag bit
1 = A RESET instruction has not been executed or set to ‘1’ by firmware
0 = A RESET instruction has been executed (cleared by hardware)
bit 1 POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0 BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset
occurs)

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TABLE 5-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
BORCON SBOREN BORFS — — — — — BORRDY 56
PCON STKOVF STKUNF — RWDT RMCLR RI POR BOR 60
STATUS — — — TO PD Z DC C 23
WDTCON — — WDTPS<4:0> SWDTEN 100
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Resets.

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6.0 OSCILLATOR MODULE (WITH The oscillator module can be configured in one of the
following clock modes.
FAIL-SAFE CLOCK MONITOR)
1. ECL – External Clock Low-Power mode
6.1 Overview (0 MHz to 0.5 MHz)
2. ECM – External Clock Medium Power mode
The oscillator module has a wide variety of clock (0.5 MHz to 4 MHz)
sources and selection features that allow it to be used 3. ECH – External Clock High-Power mode
in a wide range of applications while maximizing (4 MHz to 32 MHz)
performance and minimizing power consumption.
4. LP – 32 kHz Low-Power Crystal mode.
Figure 6-1 illustrates a block diagram of the oscillator
module. 5. XT – Medium Gain Crystal or Ceramic Resonator
Oscillator mode (up to 4 MHz)
Clock sources can be supplied from external oscillators,
6. HS – High Gain Crystal or Ceramic Resonator
quartz crystal resonators, ceramic resonators and
mode (4 MHz to 20 MHz)
Resistor-Capacitor (RC) circuits. In addition, the system
clock source can be supplied from one of two internal 7. EXTRC – External Resistor-Capacitor
oscillators and PLL circuits, with a choice of speeds 8. INTOSC – Internal oscillator (31 kHz to 32 MHz)
selectable via software. Additional clock features Clock Source modes are selected by the FOSC<2:0>
include: bits in the Configuration Words. The FOSC bits
• Selectable system clock source between external determine the type of oscillator that will be used when
or internal sources via software. the device is first powered.
• Two-Speed Start-up mode, which minimizes The ECH, ECM, and ECL clock modes rely on an
latency between external oscillator start-up and external logic level signal as the device clock source.
code execution. The LP, XT, and HS clock modes require an external
• Fail-Safe Clock Monitor (FSCM) designed to crystal or resonator to be connected to the device.
detect a failure of the external clock source (LP, Each mode is optimized for a different frequency range.
XT, HS, ECH, ECM, ECL or EXTRC modes) and The EXTRC clock mode requires an external resistor
switch automatically to the internal oscillator. and capacitor to set the oscillator frequency.
• Oscillator Start-up Timer (OST) ensures stability The INTOSC internal oscillator block produces low,
of crystal oscillator sources. medium, and high-frequency clock sources,
designated LFINTOSC, MFINTOSC and HFINTOSC.
(see Internal Oscillator Block, Figure 6-1). A wide
selection of device clock frequencies may be derived
from these three clock sources.

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FIGURE 6-1: SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM
Secondary
Oscillator Timer1
Timer1 Clock Source Option
SOSCO for other modules
T1OSCEN
Enable
SOSCI Oscillator T1OSC
01
External
LP, XT, HS, RC, EC
Oscillator
OSC2 0
0 Sleep
1
Sleep
FOSC
OSC1 PRIMUX 00 To CPU and
Peripherals
4 x PLL 1

PLLMUX
IRCF<3:0>
INTOSC
16 MHz 1X
1111
8 MHz
Internal
Oscillator 4 MHz
Block 2 MHz SCS<1:0>
Postscaler

1 MHz
HFPLL
MUX
16 MHz 500 kHz
(HFINTOSC) 250 kHz
125 kHz
500 kHz
Source 500 kHz 62.5 kHz
(MFINTOSC) 31.25 kHz
31 kHz 31 kHz
Source 0000

31 kHz (LFINTOSC) WDT, PWRT, Fail-Safe Clock Monitor

Two-Speed Start-up and other modules

Inputs Outputs

PLLEN or
SCS FOSC<2:0> IRCF PRIMUX PLLMUX
SPLLEN

0 x 1 0
=100 =1110 1 1
1
=00 ≠1110 1 0
0 x 0 0
≠100
1 x 0 1
≠00 X X X X X

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6.2 Clock Source Types The Oscillator Start-up Timer (OST) is disabled when
EC mode is selected. Therefore, there is no delay in
Clock sources can be classified as external or internal. operation after a Power-on Reset (POR) or wake-up
External clock sources rely on external circuitry for the from Sleep. Because the PIC® MCU design is fully
clock source to function. Examples are: oscillator static, stopping the external clock input will have the
modules (ECH, ECM, ECL mode), quartz crystal effect of halting the device while leaving all data intact.
resonators or ceramic resonators (LP, XT and HS Upon restarting the external clock, the device will
modes) and Resistor-Capacitor (EXTRC) mode resume operation as if no time had elapsed.
circuits.
Internal clock sources are contained within the FIGURE 6-2: EXTERNAL CLOCK (EC)
oscillator module. The internal oscillator block has two MODE OPERATION
internal oscillators and a dedicated Phase-Lock Loop
(HFPLL) that are used to generate three internal OSC1/CLKIN
Clock from
system clock sources: the 16 MHz High-Frequency Ext. System
Internal Oscillator (HFINTOSC), 500 kHz (MFINTOSC) PIC® MCU
and the 31 kHz Low-Frequency Internal Oscillator
(LFINTOSC). OSC2/CLKOUT
FOSC/4 or I/O(1)
The system clock can be selected between external or
internal clock sources via the System Clock Select
Note 1: Output depends upon CLKOUTEN bit of the
(SCS) bits in the OSCCON register. See Section 6.3 Configuration Words.
“Clock Switching” for additional information.

6.2.1 EXTERNAL CLOCK SOURCES 6.2.1.2 LP, XT, HS Modes

An external clock source can be used as the device The LP, XT and HS modes support the use of quartz
system clock by performing one of the following crystal resonators or ceramic resonators connected to
actions: OSC1 and OSC2 (Figure 6-3). The three modes select
• Program the FOSC<2:0> bits in the Configuration a low, medium or high gain setting of the internal
Words to select an external clock source that will inverter-amplifier to support various resonator types
be used as the default system clock upon a and speed.
device Reset. LP Oscillator mode selects the lowest gain setting of the
• Write the SCS<1:0> bits in the OSCCON register internal inverter-amplifier. LP mode current consumption
to switch the system clock source to: is the least of the three modes. This mode is designed to
- Secondary oscillator during run-time, or drive only 32.768 kHz tuning-fork type crystals (watch
crystals).
- An external clock source determined by the
value of the FOSC bits. XT Oscillator mode selects the intermediate gain
setting of the internal inverter-amplifier. XT mode
See Section 6.3 “Clock Switching”for more informa-
current consumption is the medium of the three modes.
tion.
This mode is best suited to drive resonators with a
6.2.1.1 EC Mode medium drive level specification.

The External Clock (EC) mode allows an externally HS Oscillator mode selects the highest gain setting of the
generated logic level signal to be the system clock internal inverter-amplifier. HS mode current consumption
source. When operating in this mode, an external clock is the highest of the three modes. This mode is best
source is connected to the OSC1 input. suited for resonators that require a high drive setting.
OSC2/CLKOUT is available for general purpose I/O or Figure 6-3 and Figure 6-4 show typical circuits for
CLKOUT. Figure 6-2 shows the pin connections for EC quartz crystal and ceramic resonators, respectively.
mode.
EC mode has three power modes to select from through
Configuration Words:
• ECH – High power, 4-32 MHz
• ECM – Medium power, 0.5-4 MHz
• ECL – Low power, 0-0.5 MHz

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FIGURE 6-3: QUARTZ CRYSTAL FIGURE 6-4: CERAMIC RESONATOR
OPERATION (LP, XT OR OPERATION
HS MODE) (XT OR HS MODE)

PIC® MCU PIC® MCU

OSC1/CLKIN OSC1/CLKIN

C1 To Internal C1 To Internal
Logic Logic
Quartz
RF(2) Sleep RP(3)
Crystal RF(2) Sleep

C2 OSC2/CLKOUT
RS(1) OSC2/CLKOUT
C2 Ceramic RS(1)
Resonator
Note 1: A series resistor (RS) may be required for
quartz crystals with low drive level. Note 1: A series resistor (RS) may be required for
ceramic resonators with low drive level.
2: The value of RF varies with the Oscillator mode
selected (typically between 2 M to 10 M. 2: The value of RF varies with the Oscillator mode
selected (typically between 2 M to 10 M.
3: An additional parallel feedback resistor (RP)
Note 1: Quartz crystal characteristics vary may be required for proper ceramic resonator
according to type, package and operation.
manufacturer. The user should consult the
manufacturer data sheets for specifications
and recommended application. 6.2.1.3 Oscillator Start-up Timer (OST)
2: Always verify oscillator performance over If the oscillator module is configured for LP, XT or HS
the VDD and temperature range that is modes, the Oscillator Start-up Timer (OST) counts
expected for the application. 1024 oscillations from OSC1. This occurs following a
3: For oscillator design assistance, reference Power-on Reset (POR) and when the Power-up Timer
the following Microchip Application Notes: (PWRT) has expired (if configured), or a wake-up from
Sleep. During this time, the program counter does not
• AN826, “Crystal Oscillator Basics and increment and program execution is suspended,
Crystal Selection for rfPIC® and PIC® unless either FSCM or Two-Speed Start-Up are
Devices” (DS00826) enabled. In this case, code will continue to execute at
• AN849, “Basic PIC® Oscillator Design” the selected INTOSC frequency while the OST is
(DS00849) counting. The OST ensures that the oscillator circuit,
• AN943, “Practical PIC® Oscillator using a quartz crystal resonator or ceramic resonator,
Analysis and Design” (DS00943) has started and is providing a stable system clock to
• AN949, “Making Your Oscillator Work” the oscillator module.
(DS00949) In order to minimize latency between external oscillator
start-up and code execution, the Two-Speed Clock
Start-up mode can be selected (see Section 6.4
“Two-Speed Clock Start-up Mode”).

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PIC16(L)F1704/8
6.2.1.4 4x PLL
Note 1: Quartz crystal characteristics vary
The oscillator module contains a 4x PLL that can be according to type, package and
used with both external and internal clock sources to manufacturer. The user should consult the
provide a system clock source. The input frequency for manufacturer data sheets for specifications
the 4x PLL must fall within specifications. See the PLL and recommended application.
Clock Timing Specifications in Table 32-9.
2: Always verify oscillator performance over
The 4x PLL may be enabled for use by one of two the VDD and temperature range that is
methods: expected for the application.
1. Program the PLLEN bit in Configuration Words 3: For oscillator design assistance, reference
to a ‘1’. the following Microchip Application Notes:
2. Write the SPLLEN bit in the OSCCON register to • AN826, “Crystal Oscillator Basics and
a ‘1’. If the PLLEN bit in Configuration Words is Crystal Selection for rfPIC® and PIC®
programmed to a ‘1’, then the value of SPLLEN Devices” (DS00826)
is ignored.
• AN849, “Basic PIC® Oscillator Design”
(DS00849)
6.2.1.5 Secondary Oscillator
• AN943, “Practical PIC® Oscillator
The secondary oscillator is a separate crystal oscillator Analysis and Design” (DS00943)
that is associated with the Timer1 peripheral. It is
• AN949, “Making Your Oscillator Work”
optimized for timekeeping operations with a 32.768
(DS00949)
kHz crystal connected between the SOSCO and
SOSCI device pins. • TB097, “Interfacing a Micro Crystal
MS1V-T1K 32.768 kHz Tuning Fork
The secondary oscillator can be used as an alternate Crystal to a PIC16F690/SS” (DS91097)
system clock source and can be selected during
• AN1288, “Design Practices for
run-time using clock switching. Refer to Section 6.3
Low-Power External Oscillators”
“Clock Switching” for more information.
(DS01288)
FIGURE 6-5: QUARTZ CRYSTAL
OPERATION
(SECONDARY
OSCILLATOR)

PIC® MCU

SOSCI

C1 To Internal
Logic
32.768 kHz
Quartz
Crystal

C2 SOSCO

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 PIC16(L)F1704/8
6.2.1.6 External RC Mode 6.2.2 INTERNAL CLOCK SOURCES
The external Resistor-Capacitor (EXTRC) mode The device may be configured to use the internal
supports the use of an external RC circuit. This allows oscillator block as the system clock by performing one
the designer maximum flexibility in frequency choice of the following actions:
while keeping costs to a minimum when clock accuracy • Program the FOSC<2:0> bits in Configuration
is not required. Words to select the INTOSC clock source, which
The RC circuit connects to OSC1. OSC2/CLKOUT is will be used as the default system clock upon a
available for general purpose I/O or CLKOUT. The device Reset.
function of the OSC2/CLKOUT pin is determined by the • Write the SCS<1:0> bits in the OSCCON register
CLKOUTEN bit in Configuration Words. to switch the system clock source to the internal
Figure 6-6 shows the external RC mode connections. oscillator during run-time. See Section 6.3
“Clock Switching” for more information.
FIGURE 6-6: EXTERNAL RC MODES In INTOSC mode, OSC1/CLKIN is available for general
purpose I/O. OSC2/CLKOUT is available for general
purpose I/O or CLKOUT.
VDD
PIC® MCU
The function of the OSC2/CLKOUT pin is determined
REXT by the CLKOUTEN bit in Configuration Words.
OSC1/CLKIN Internal The internal oscillator block has two independent
Clock oscillators and a dedicated Phase-Lock Loop, HFPLL
CEXT that can produce one of three internal system clock
VSS sources.
1. The HFINTOSC (High-Frequency Internal
OSC2/CLKOUT Oscillator) is factory calibrated and operates at
FOSC/4 or I/O(1)
16 MHz. The HFINTOSC source is generated
from the 500 kHz MFINTOSC source and the
Recommended values: 10 k  REXT  100 k, <3V dedicated Phase-Lock Loop, HFPLL. The
3 k  REXT  100 k, 3-5V frequency of the HFINTOSC can be
CEXT > 20 pF, 2-5V
user-adjusted via software using the OSCTUNE
Note 1: Output depends upon CLKOUTEN bit of the register (Register 6-3).
Configuration Words. 2. The MFINTOSC (Medium-Frequency Internal
Oscillator) is factory calibrated and operates at
The RC oscillator frequency is a function of the supply 500 kHz. The frequency of the MFINTOSC can
voltage, the resistor (REXT) and capacitor (CEXT) values be user-adjusted via software using the
and the operating temperature. Other factors affecting OSCTUNE register (Register 6-3).
the oscillator frequency are: 3. The LFINTOSC (Low-Frequency Internal
• threshold voltage variation Oscillator) is uncalibrated and operates at
• component tolerances 31 kHz.
• packaging variations in capacitance
The user also needs to take into account variation due
to tolerance of external RC components used.

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6.2.2.1 HFINTOSC 6.2.2.3 Internal Oscillator Frequency
The High-Frequency Internal Oscillator (HFINTOSC) is Adjustment
a factory calibrated 16 MHz internal clock source. The The 500 kHz internal oscillator is factory calibrated.
frequency of the HFINTOSC can be altered via This internal oscillator can be adjusted in software by
software using the OSCTUNE register (Register 6-3). writing to the OSCTUNE register (Register 6-3). Since
The output of the HFINTOSC connects to a postscaler the HFINTOSC and MFINTOSC clock sources are
and multiplexer (see Figure 6-1). One of multiple derived from the 500 kHz internal oscillator a change in
frequencies derived from the HFINTOSC can be the OSCTUNE register value will apply to both.
selected via software using the IRCF<3:0> bits of the The default value of the OSCTUNE register is ‘0’. The
OSCCON register. See Section 6.2.2.7 “Internal value is a 6-bit two’s complement number. A value of
Oscillator Clock Switch Timing” for more information. 1Fh will provide an adjustment to the maximum
The HFINTOSC is enabled by: frequency. A value of 20h will provide an adjustment to
the minimum frequency.
• Configure the IRCF<3:0> bits of the OSCCON
register for the desired HF frequency, and When the OSCTUNE register is modified, the oscillator
frequency will begin shifting to the new frequency. Code
• FOSC<2:0> = 100, or
execution continues during this shift. There is no
• Set the System Clock Source (SCS) bits of the indication that the shift has occurred.
OSCCON register to ‘1x’
OSCTUNE does not affect the LFINTOSC frequency.
A fast start-up oscillator allows internal circuits to power Operation of features that depend on the LFINTOSC
up and stabilize before switching to HFINTOSC. clock source frequency, such as the Power-up Timer
The High-Frequency Internal Oscillator Ready bit (PWRT), Watchdog Timer (WDT), Fail-Safe Clock
(HFIOFR) of the OSCSTAT register indicates when the Monitor (FSCM) and peripherals, are not affected by the
HFINTOSC is running. change in frequency.
The High-Frequency Internal Oscillator Status Locked
6.2.2.4 LFINTOSC
bit (HFIOFL) of the OSCSTAT register indicates when
the HFINTOSC is running within 2% of its final value. The Low-Frequency Internal Oscillator (LFINTOSC) is
an uncalibrated 31 kHz internal clock source.
The High-Frequency Internal Oscillator Stable bit
(HFIOFS) of the OSCSTAT register indicates when the The output of the LFINTOSC connects to a multiplexer
HFINTOSC is running within 0.5% of its final value. (see Figure 6-1). Select 31 kHz, via software, using the
IRCF<3:0> bits of the OSCCON register. See
6.2.2.2 MFINTOSC Section 6.2.2.7 “Internal Oscillator Clock Switch
The Medium-Frequency Internal Oscillator Timing” for more information. The LFINTOSC is also
(MFINTOSC) is a factory calibrated 500 kHz internal the frequency for the Power-up Timer (PWRT),
clock source. The frequency of the MFINTOSC can be Watchdog Timer (WDT) and Fail-Safe Clock Monitor
altered via software using the OSCTUNE register (FSCM).
(Register 6-3). The LFINTOSC is enabled by selecting 31 kHz
The output of the MFINTOSC connects to a postscaler (IRCF<3:0> bits of the OSCCON register = 000) as the
and multiplexer (see Figure 6-1). One of nine system clock source (SCS bits of the OSCCON
frequencies derived from the MFINTOSC can be register = 1x), or when any of the following are
selected via software using the IRCF<3:0> bits of the enabled:
OSCCON register. See Section 6.2.2.7 “Internal • Configure the IRCF<3:0> bits of the OSCCON
Oscillator Clock Switch Timing” for more information. register for the desired LF frequency, and
The MFINTOSC is enabled by: • FOSC<2:0> = 100, or
• Configure the IRCF<3:0> bits of the OSCCON • Set the System Clock Source (SCS) bits of the
register for the desired HF frequency, and OSCCON register to ‘1x’
• FOSC<2:0> = 100, or Peripherals that use the LFINTOSC are:
• Set the System Clock Source (SCS) bits of the • Power-up Timer (PWRT)
OSCCON register to ‘1x’ • Watchdog Timer (WDT)
The Medium-Frequency Internal Oscillator Ready bit • Fail-Safe Clock Monitor (FSCM)
(MFIOFR) of the OSCSTAT register indicates when the The Low-Frequency Internal Oscillator Ready bit
MFINTOSC is running. (LFIOFR) of the OSCSTAT register indicates when the
LFINTOSC is running.

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6.2.2.5 Internal Oscillator Frequency 6.2.2.6 32 MHz Internal Oscillator
Selection Frequency Selection
The system clock speed can be selected via software The Internal Oscillator Block can be used with the
using the Internal Oscillator Frequency Select bits 4x PLL associated with the External Oscillator Block to
IRCF<3:0> of the OSCCON register. produce a 32 MHz internal system clock source. The
The postscaled output of the 16 MHz HFINTOSC, following settings are required to use the 32 MHz
500 kHz MFINTOSC, and 31 kHz LFINTOSC connect internal clock source:
to a multiplexer (see Figure 6-1). The Internal Oscillator • The FOSC bits in Configuration Words must be
Frequency Select bits IRCF<3:0> of the OSCCON set to use the INTOSC source as the device
register select the frequency output of the internal system clock (FOSC<2:0> = 100).
oscillators. One of the following frequencies can be • The SCS bits in the OSCCON register must be
selected via software: cleared to use the clock determined by
- 32 MHz (requires 4x PLL) FOSC<2:0> in Configuration Words
- 16 MHz (SCS<1:0> = 00).
- 8 MHz • The IRCF bits in the OSCCON register must be
set to the 8 MHz HFINTOSC set to use
- 4 MHz
(IRCF<3:0> = 1110).
- 2 MHz
• The SPLLEN bit in the OSCCON register must be
- 1 MHz set to enable the 4x PLL, or the PLLEN bit of the
- 500 kHz (default after Reset) Configuration Words must be programmed to a
- 250 kHz ‘1’.
- 125 kHz Note: When using the PLLEN bit of the
- 62.5 kHz Configuration Words, the 4x PLL cannot
- 31.25 kHz be disabled by software and the SPLLEN
option will not be available.
- 31 kHz (LFINTOSC)
Note: Following any Reset, the IRCF<3:0> bits The 4x PLL is not available for use with the internal
of the OSCCON register are set to ‘0111’ oscillator when the SCS bits of the OSCCON register
and the frequency selection is set to are set to ‘1x’. The SCS bits must be set to ‘00’ to use
500 kHz. The user can modify the IRCF the 4x PLL with the internal oscillator.
bits to select a different frequency.
The IRCF<3:0> bits of the OSCCON register allow
duplicate selections for some frequencies. These
duplicate choices can offer system design trade-offs.
Lower power consumption can be obtained when
changing oscillator sources for a given frequency.
Faster transition times can be obtained between
frequency changes that use the same oscillator source.

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6.2.2.7 Internal Oscillator Clock Switch
Timing
When switching between the HFINTOSC, MFINTOSC
and the LFINTOSC, the new oscillator may already be
shut down to save power (see Figure 6-7). If this is the
case, there is a delay after the IRCF<3:0> bits of the
OSCCON register are modified before the frequency
selection takes place. The OSCSTAT register will
reflect the current active status of the HFINTOSC,
MFINTOSC and LFINTOSC oscillators. The sequence
of a frequency selection is as follows:
1. IRCF<3:0> bits of the OSCCON register are
modified.
2. If the new clock is shut down, a clock start-up
delay is started.
3. Clock switch circuitry waits for a falling edge of
the current clock.
4. The current clock is held low and the clock
switch circuitry waits for a rising edge in the new
clock.
5. The new clock is now active.
6. The OSCSTAT register is updated as required.
7. Clock switch is complete.
See Figure 6-7 for more details.
If the internal oscillator speed is switched between two
clocks of the same source, there is no start-up delay
before the new frequency is selected. Clock switching
time delays are shown in Table 6-1.
Start-up delay specifications are located in the
oscillator tables of Section 32.0 “Electrical
Specifications”.

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FIGURE 6-7: INTERNAL OSCILLATOR SWITCH TIMING

HFINTOSC/ LFINTOSC (FSCM and WDT disabled)

MFINTOSC
HFINTOSC/
MFINTOSC
Oscillator Delay(1) 2-cycle Sync Running

LFINTOSC

IRCF <3:0> 0 0

System Clock

HFINTOSC/ LFINTOSC (Either FSCM or WDT enabled)

MFINTOSC
HFINTOSC/
MFINTOSC
2-cycle Sync Running

LFINTOSC

IRCF <3:0> 0 0

System Clock

LFINTOSC HFINTOSC/MFINTOSC
LFINTOSC turns off unless WDT or FSCM is enabled
LFINTOSC
Oscillator Delay(1) 2-cycle Sync Running

HFINTOSC/
MFINTOSC

IRCF <3:0> =0 0

System Clock

Note: See Table 6-1 for more information.

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6.3 Clock Switching 6.3.3 SECONDARY OSCILLATOR
The system clock source can be switched between The secondary oscillator is a separate crystal oscillator
external and internal clock sources via software using associated with the Timer1 peripheral. It is optimized
the System Clock Select (SCS) bits of the OSCCON for timekeeping operations with a 32.768 kHz crystal
register. The following clock sources can be selected connected between the SOSCO and SOSCI device
using the SCS bits: pins.

• Default system oscillator determined by FOSC The secondary oscillator is enabled using the
bits in Configuration Words T1OSCEN control bit in the T1CON register. See
Section 25.0 “Timer1 Module with Gate Control” for
• Timer1 32 kHz crystal oscillator
more information about the Timer1 peripheral.
• Internal Oscillator Block (INTOSC)
6.3.4 SECONDARY OSCILLATOR READY
6.3.1 SYSTEM CLOCK SELECT (SCS)
(SOSCR) BIT
BITS
The user must ensure that the secondary oscillator is
The System Clock Select (SCS) bits of the OSCCON
ready to be used before it is selected as a system clock
register select the system clock source that is used for
source. The Secondary Oscillator Ready (SOSCR) bit
the CPU and peripherals.
of the OSCSTAT register indicates whether the
• When the SCS bits of the OSCCON register = 00, secondary oscillator is ready to be used. After the
the system clock source is determined by the SOSCR bit is set, the SCS bits can be configured to
value of the FOSC<2:0> bits in the Configuration select the secondary oscillator.
Words.
• When the SCS bits of the OSCCON register = 01, 6.3.5 CLOCK SWITCHING BEFORE
the system clock source is the secondary oscillator. SLEEP
• When the SCS bits of the OSCCON register = 1x, When clock switching from an old clock to a new clock
the system clock source is chosen by the internal is requested just prior to entering Sleep mode, it is
oscillator frequency selected by the IRCF<3:0> necessary to confirm that the switch is complete before
bits of the OSCCON register. After a Reset, the the SLEEP instruction is executed. Failure to do so may
SCS bits of the OSCCON register are always result in an incomplete switch and consequential loss
cleared. of the system clock altogether. Clock switching is
Note: Any automatic clock switch, which may confirmed by monitoring the clock Status bits in the
occur from Two-Speed Start-up or OSCSTAT register. Switch confirmation can be
Fail-Safe Clock Monitor, does not update accomplished by sensing that the ready bit for the new
the SCS bits of the OSCCON register. The clock is set or the ready bit for the old clock is cleared.
user can monitor the OSTS bit of the For example, when switching between the internal
OSCSTAT register to determine the current oscillator with the PLL and the internal oscillator without
system clock source. the PLL, monitor the PLLR bit. When PLLR is set, the
switch to 32 MHz operation is complete. Conversely,
When switching between clock sources, a delay is when PLLR is cleared, the switch from 32 MHz
required to allow the new clock to stabilize. These operation to the selected internal clock is complete.
oscillator delays are shown in Table 6-1.

6.3.2 OSCILLATOR START-UP TIMER

STATUS (OSTS) BIT
The Oscillator Start-up Timer Status (OSTS) bit of the
OSCSTAT register indicates whether the system clock
is running from the external clock source, as defined by
the FOSC<2:0> bits in the Configuration Words, or
from the internal clock source. In particular, OSTS
indicates that the Oscillator Start-up Timer (OST) has
timed out for LP, XT or HS modes. The OST does not
reflect the status of the secondary oscillator.

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6.4 Two-Speed Clock Start-up Mode 6.4.1 TWO-SPEED START-UP MODE
CONFIGURATION
Two-Speed Start-up mode provides additional power
savings by minimizing the latency between external Two-Speed Start-up mode is configured by the
oscillator start-up and code execution. In applications following settings:
that make heavy use of the Sleep mode, Two-Speed • IESO (of the Configuration Words) = 1;
Start-up will remove the external oscillator start-up Internal/External Switchover bit (Two-Speed
time from the time spent awake and can reduce the Start-up mode enabled).
overall power consumption of the device. This mode • SCS (of the OSCCON register) = 00.
allows the application to wake-up from Sleep, perform
• FOSC<2:0> bits in the Configuration Words
a few instructions using the INTOSC internal oscillator
configured for LP, XT or HS mode.
block as the clock source and go back to Sleep without
waiting for the external oscillator to become stable. Two-Speed Start-up mode is entered after:
Two-Speed Start-up provides benefits when the • Power-on Reset (POR) and, if enabled, after
oscillator module is configured for LP, XT or HS Power-up Timer (PWRT) has expired, or
modes. The Oscillator Start-up Timer (OST) is enabled • Wake-up from Sleep.
for these modes and must count 1024 oscillations
before the oscillator can be used as the system clock
source.
If the oscillator module is configured for any mode
other than LP, XT or HS mode, then Two-Speed
Start-up is disabled. This is because the external clock
oscillator does not require any stabilization time after
POR or an exit from Sleep.
If the OST count reaches 1024 before the device
enters Sleep mode, the OSTS bit of the OSCSTAT
register is set and program execution switches to the
external oscillator. However, the system may never
operate from the external oscillator if the time spent
awake is very short.
Note: Executing a SLEEP instruction will abort
the oscillator start-up time and will cause
the OSTS bit of the OSCSTAT register to
remain clear.

TABLE 6-1: OSCILLATOR SWITCHING DELAYS

Switch From Switch To Frequency Oscillator Delay
LFINTOSC(1) 31 kHz
Sleep/POR MFINTOSC(1) 31.25 kHz-500 kHz 2 cycles
HFINTOSC(1) 31.25 kHz-16 MHz
Sleep/POR EC, RC(1) DC – 32 MHz 2 cycles
LFINTOSC EC, RC(1) DC – 32 MHz 1 cycle of each
Secondary Oscillator
Sleep/POR 32 kHz-20 MHz 1024 Clock Cycles (OST)
LP, XT, HS(1)
MFINTOSC(1) 31.25 kHz-500 kHz
Any clock source 2 s (approx.)
HFINTOSC(1) 31.25 kHz-16 MHz
Any clock source LFINTOSC(1) 31 kHz 1 cycle of each
Any clock source Secondary Oscillator 32 kHz 1024 Clock Cycles (OST)
PLL inactive PLL active 16-32 MHz 2 ms (approx.)
Note 1: PLL inactive.

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6.4.2 TWO-SPEED START-UP 6.4.3 CHECKING TWO-SPEED CLOCK
SEQUENCE STATUS
1. Wake-up from Power-on Reset or Sleep. Checking the state of the OSTS bit of the OSCSTAT
2. Instructions begin execution by the internal register will confirm if the microcontroller is running
oscillator at the frequency set in the IRCF<3:0> from the external clock source, as defined by the
bits of the OSCCON register. FOSC<2:0> bits in the Configuration Words, or the
3. OST enabled to count 1024 clock cycles. internal oscillator.
4. OST timed out, wait for falling edge of the
internal oscillator.
5. OSTS is set.
6. System clock held low until the next falling edge
of new clock (LP, XT or HS mode).
7. System clock is switched to external clock
source.

FIGURE 6-8: TWO-SPEED START-UP

INTOSC

TOST

OSC1 0 1 1022 1023

OSC2

Program Counter PC - N PC PC + 1

System Clock

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6.5 Fail-Safe Clock Monitor 6.5.3 FAIL-SAFE CONDITION CLEARING
The Fail-Safe Clock Monitor (FSCM) allows the device The Fail-Safe condition is cleared after a Reset,
to continue operating should the external oscillator fail. executing a SLEEP instruction or changing the SCS bits
The FSCM can detect oscillator failure any time after of the OSCCON register. When the SCS bits are
the Oscillator Start-up Timer (OST) has expired. The changed, the OST is restarted. While the OST is
FSCM is enabled by setting the FCMEN bit in the running, the device continues to operate from the
Configuration Words. The FSCM is applicable to all INTOSC selected in OSCCON. When the OST times
external Oscillator modes (LP, XT, HS, EC, Secondary out, the Fail-Safe condition is cleared after successfully
Oscillator and RC). switching to the external clock source. The OSFIF bit
should be cleared prior to switching to the external
clock source. If the Fail-Safe condition still exists, the
FIGURE 6-9: FSCM BLOCK DIAGRAM
OSFIF flag will again become set by hardware.
Clock Monitor
Latch 6.5.4 RESET OR WAKE-UP FROM SLEEP
External
S Q The FSCM is designed to detect an oscillator failure
Clock
after the Oscillator Start-up Timer (OST) has expired.
The OST is used after waking up from Sleep and after
LFINTOSC any type of Reset. The OST is not used with the EC or
÷ 64 R Q
Oscillator RC Clock modes so that the FSCM will be active as
soon as the Reset or wake-up has completed. When
31 kHz 488 Hz the FSCM is enabled, the Two-Speed Start-up is also
(~32 s) (~2 ms)
enabled. Therefore, the device will always be executing
Sample Clock code while the OST is operating.
Clock
Failure Note: Due to the wide range of oscillator start-up
Detected times, the Fail-Safe circuit is not active
during oscillator start-up (i.e., after exiting
Reset or Sleep). After an appropriate
6.5.1 FAIL-SAFE DETECTION amount of time, the user should check the
The FSCM module detects a failed oscillator by Status bits in the OSCSTAT register to
comparing the external oscillator to the FSCM sample verify the oscillator start-up and that the
clock. The sample clock is generated by dividing the system clock switchover has successfully
LFINTOSC by 64. See Figure 6-9. Inside the fail completed.
detector block is a latch. The external clock sets the
latch on each falling edge of the external clock. The
sample clock clears the latch on each rising edge of the
sample clock. A failure is detected when an entire
half-cycle of the sample clock elapses before the
external clock goes low.

6.5.2 FAIL-SAFE OPERATION

When the external clock fails, the FSCM switches the
device clock to an internal clock source and sets the bit
flag OSFIF of the PIR2 register. Setting this flag will
generate an interrupt if the OSFIE bit of the PIE2
register is also set. The device firmware can then take
steps to mitigate the problems that may arise from a
failed clock. The system clock will continue to be
sourced from the internal clock source until the device
firmware successfully restarts the external oscillator
and switches back to external operation.
The internal clock source chosen by the FSCM is
determined by the IRCF<3:0> bits of the OSCCON
register. This allows the internal oscillator to be
configured before a failure occurs.

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FIGURE 6-10: FSCM TIMING DIAGRAM

Sample Clock

System Oscillator
Clock Failure
Output

Clock Monitor Output

(Q)
Failure
Detected
OSCFIF

Test Test Test

Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.

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6.6 Register Definitions: Oscillator Control

REGISTER 6-1: OSCCON: OSCILLATOR CONTROL REGISTER

R/W-0/0 R/W-0/0 R/W-1/1 R/W-1/1 R/W-1/1 U-0 R/W-0/0 R/W-0/0
SPLLEN IRCF<3:0> — SCS<1:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 SPLLEN: Software PLL Enable bit

If PLLEN in Configuration Words = 1:
SPLLEN bit is ignored. 4x PLL is always enabled (subject to oscillator requirements)
If PLLEN in Configuration Words = 0:
1 = 4x PLL Is enabled
0 = 4x PLL is disabled
bit 6-3 IRCF<3:0>: Internal Oscillator Frequency Select bits
1111 = 16 MHz HF
1110 = 8 MHz or 32 MHz HF(2)
1101 = 4 MHz HF
1100 = 2 MHz HF
1011 = 1 MHz HF
1010 = 500 kHz HF(1)
1001 = 250 kHz HF(1)
1000 = 125 kHz HF(1)
0111 = 500 kHz MF (default upon Reset)
0110 = 250 kHz MF
0101 = 125 kHz MF
0100 = 62.5 kHz MF
0011 = 31.25 kHz HF(1)
0010 = 31.25 kHz MF
000x = 31 kHz LF
bit 2 Unimplemented: Read as ‘0’
bit 1-0 SCS<1:0>: System Clock Select bits
1x = Internal oscillator block
01 = Secondary oscillator
00 = Clock determined by FOSC<2:0> in Configuration Words

Note 1: Duplicate frequency derived from HFINTOSC.

2: 32 MHz when SPLLEN bit is set. Refer to Section 6.2.2.6 “32 MHz Internal Oscillator Frequency
Selection”.

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REGISTER 6-2: OSCSTAT: OSCILLATOR STATUS REGISTER

R-1/q R-0/q R-q/q R-0/q R-0/q R-q/q R-0/0 R-0/q
SOSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Conditional

bit 7 SOSCR: Secondary Oscillator Ready bit

If T1OSCEN = 1:
1 = Secondary oscillator is ready
0 = Secondary oscillator is not ready
If T1OSCEN = 0:
1 = Secondary clock source is always ready
bit 6 PLLR 4x PLL Ready bit
1 = 4x PLL is ready
0 = 4x PLL is not ready
bit 5 OSTS: Oscillator Start-up Timer Status bit
1 = Running from the clock defined by the FOSC<2:0> bits of the Configuration Words
0 = Running from an internal oscillator (FOSC<2:0> = 100)
bit 4 HFIOFR: High-Frequency Internal Oscillator Ready bit
1 = HFINTOSC is ready
0 = HFINTOSC is not ready
bit 3 HFIOFL: High-Frequency Internal Oscillator Locked bit
1 = HFINTOSC is at least 2% accurate
0 = HFINTOSC is not 2% accurate
bit 2 MFIOFR: Medium-Frequency Internal Oscillator Ready bit
1 = MFINTOSC is ready
0 = MFINTOSC is not ready
bit 1 LFIOFR: Low-Frequency Internal Oscillator Ready bit
1 = LFINTOSC is ready
0 = LFINTOSC is not ready
bit 0 HFIOFS: High-Frequency Internal Oscillator Stable bit
1 = HFINTOSC is at least 0.5% accurate
0 = HFINTOSC is not 0.5% accurate

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REGISTER 6-3: OSCTUNE: OSCILLATOR TUNING REGISTER

U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — TUN<5:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 TUN<5:0>: Frequency Tuning bits
100000 = Minimum frequency
•
•
•
111111 =
000000 = Oscillator module is running at the factory-calibrated frequency
000001 =
•
•
•
011110 =
011111 = Maximum frequency

TABLE 6-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES

Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page

OSCCON SPLLEN IRCF<3:0> — SCS<1:0> 77

OSCSTAT SOSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS 78
OSCTUNE — — TUN<5:0> 79
PIR2 OSFIF C2IF C1IF — BCL1IF TMR6IF TMR4IF CCP2IF 90
PIE2 OSFIE C2IE C1IE — BCL1IE TMR6IE TMR4IE CCP2IE 87
T1CON TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC — TMR1ON 253
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.

TABLE 6-3: SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES

Name Register
Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0
on Page

CONFIG1 13:8 — — FCMEN IESO CLKOUTEN BOREN<1:0> —

49
7:0 CP MCLRE PWRTE WDTE<1:0> FOSC<2:0>
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.

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7.0 INTERRUPTS
The interrupt feature allows certain events to preempt
normal program flow. Firmware is used to determine
the source of the interrupt and act accordingly. Some
interrupts can be configured to wake the MCU from
Sleep mode.
This chapter contains the following information for
Interrupts:
• Operation
• Interrupt Latency
• Interrupts During Sleep
• INT Pin
• Automatic Context Saving
Many peripherals produce interrupts. Refer to the
corresponding chapters for details.
A block diagram of the interrupt logic is shown in
Figure 7-1.

FIGURE 7-1: INTERRUPT LOGIC

TMR0IF Wake-up
TMR0IE (If in Sleep mode)

INTF
Peripheral Interrupts INTE
(TMR1IF) PIR1<0>
IOCIF
(TMR1IE) PIE1<0> Interrupt
IOCIE to CPU

PEIE

PIRn<7>
GIE
PIEn<7>

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7.1 Operation 7.2 Interrupt Latency
Interrupts are disabled upon any device Reset. They Interrupt latency is defined as the time from when the
are enabled by setting the following bits: interrupt event occurs to the time code execution at the
• GIE bit of the INTCON register interrupt vector begins. The latency for synchronous
interrupts is three or four instruction cycles. For
• Interrupt Enable bit(s) for the specific interrupt
asynchronous interrupts, the latency is three to five
event(s)
instruction cycles, depending on when the interrupt
• PEIE bit of the INTCON register (if the Interrupt occurs. See Figure 7-2 and Figure 7-3 for more details.
Enable bit of the interrupt event is contained in the
PIE1 or PIE2 registers)
The INTCON, PIR1 and PIR2 registers record
individual interrupts via interrupt flag bits. Interrupt flag
bits will be set, regardless of the status of the GIE, PEIE
and individual interrupt enable bits.
The following events happen when an interrupt event
occurs while the GIE bit is set:
• Current prefetched instruction is flushed
• GIE bit is cleared
• Current Program Counter (PC) is pushed onto the
stack
• Critical registers are automatically saved to the
shadow registers (See “Section 7.5 “Automatic
Context Saving”)
• PC is loaded with the interrupt vector 0004h
The firmware within the Interrupt Service Routine (ISR)
should determine the source of the interrupt by polling
the interrupt flag bits. The interrupt flag bits must be
cleared before exiting the ISR to avoid repeated
interrupts. Because the GIE bit is cleared, any interrupt
that occurs while executing the ISR will be recorded
through its interrupt flag, but will not cause the
processor to redirect to the interrupt vector.
The RETFIE instruction exits the ISR by popping the
previous address from the stack, restoring the saved
context from the shadow registers and setting the GIE
bit.
For additional information on a specific interrupt’s
operation, refer to its peripheral chapter.
Note 1: Individual interrupt flag bits are set,
regardless of the state of any other
enable bits.
2: All interrupts will be ignored while the GIE
bit is cleared. Any interrupt occurring
while the GIE bit is clear will be serviced
when the GIE bit is set again.

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FIGURE 7-2: INTERRUPT LATENCY

OSC1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

CLKR Interrupt Sampled

during Q1

Interrupt

GIE

PC PC-1 PC PC+1 0004h 0005h

Execute 1 Cycle Instruction at PC Inst(PC) NOP NOP Inst(0004h)

Interrupt

GIE

PC+1/FSR New PC/

PC PC-1 PC 0004h 0005h
ADDR PC+1

Execute 2 Cycle Instruction at PC Inst(PC) NOP NOP Inst(0004h)

Interrupt

GIE

PC PC-1 PC FSR ADDR PC+1 PC+2 0004h 0005h

Execute 3 Cycle Instruction at PC INST(PC) NOP NOP NOP Inst(0004h) Inst(0005h)

Interrupt

GIE

PC PC-1 PC FSR ADDR PC+1 PC+2 0004h 0005h

Execute 3 Cycle Instruction at PC INST(PC) NOP NOP NOP NOP Inst(0004h)

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 PIC16(L)F1704/8
FIGURE 7-3: INT PIN INTERRUPT TIMING

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

CLKOUT (3)
(4)

INT pin
(1)
(1)
INTF (5) Interrupt Latency (2)

GIE

INSTRUCTION FLOW
PC PC PC + 1 PC + 1 0004h 0005h
Instruction
Fetched Inst (PC) Inst (PC + 1) — Inst (0004h) Inst (0005h)

Instruction Forced NOP Forced NOP Inst (0004h)

Inst (PC – 1) Inst (PC)
Executed

Note 1: INTF flag is sampled here (every Q1).

2: Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKOUT not available in all oscillator modes.
4: For minimum width of INT pulse, refer to AC specifications in Section 32.0 “Electrical Specifications””.
5: INTF is enabled to be set any time during the Q4-Q1 cycles.

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PIC16(L)F1704/8
7.3 Interrupts During Sleep
Some interrupts can be used to wake from Sleep. To
wake from Sleep, the peripheral must be able to
operate without the system clock. The interrupt source
must have the appropriate Interrupt Enable bit(s) set
prior to entering Sleep.
On waking from Sleep, if the GIE bit is also set, the
processor will branch to the interrupt vector. Otherwise,
the processor will continue executing instructions after
the SLEEP instruction. The instruction directly after the
SLEEP instruction will always be executed before
branching to the ISR. Refer to Section 8.0
“Power-Down Mode (Sleep)” for more details.

7.4 INT Pin

The INT pin can be used to generate an asynchronous
edge-triggered interrupt. This interrupt is enabled by
setting the INTE bit of the INTCON register. The
INTEDG bit of the OPTION_REG register determines on
which edge the interrupt will occur. When the INTEDG
bit is set, the rising edge will cause the interrupt. When
the INTEDG bit is clear, the falling edge will cause the
interrupt. The INTF bit of the INTCON register will be set
when a valid edge appears on the INT pin. If the GIE and
INTE bits are also set, the processor will redirect
program execution to the interrupt vector.

7.5 Automatic Context Saving

Upon entering an interrupt, the return PC address is
saved on the stack. Additionally, the following registers
are automatically saved in the shadow registers:
• W register
• STATUS register (except for TO and PD)
• BSR register
• FSR registers
• PCLATH register
Upon exiting the Interrupt Service Routine, these
registers are automatically restored. Any modifications
to these registers during the ISR will be lost. If
modifications to any of these registers are desired, the
corresponding shadow register should be modified and
the value will be restored when exiting the ISR. The
shadow registers are available in Bank 31 and are
readable and writable. Depending on the user’s
application, other registers may also need to be saved.

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 PIC16(L)F1704/8
7.6 Register Definitions: Interrupt Control

REGISTER 7-1: INTCON: INTERRUPT CONTROL REGISTER

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0
GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF(1)
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 GIE: Global Interrupt Enable bit

1 = Enables all active interrupts
0 = Disables all interrupts
bit 6 PEIE: Peripheral Interrupt Enable bit
1 = Enables all active peripheral interrupts
0 = Disables all peripheral interrupts
bit 5 TMR0IE: Timer0 Overflow Interrupt Enable bit
1 = Enables the Timer0 interrupt
0 = Disables the Timer0 interrupt
bit 4 INTE: INT External Interrupt Enable bit
1 = Enables the INT external interrupt
0 = Disables the INT external interrupt
bit 3 IOCIE: Interrupt-on-Change Enable bit
1 = Enables the interrupt-on-change
0 = Disables the interrupt-on-change
bit 2 TMR0IF: Timer0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed
0 = TMR0 register did not overflow
bit 1 INTF: INT External Interrupt Flag bit
1 = The INT external interrupt occurred
0 = The INT external interrupt did not occur
bit 0 IOCIF: Interrupt-on-Change Interrupt Flag bit(1)
1 = When at least one of the interrupt-on-change pins changed state
0 = None of the interrupt-on-change pins have changed state

Note 1: The IOCIF Flag bit is read-only and cleared when all the interrupt-on-change flags in the IOCxF registers
have been cleared by software.

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.

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REGISTER 7-2: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 TMR1GIE: Timer1 Gate Interrupt Enable bit

1 = Enables the Timer1 gate acquisition interrupt
0 = Disables the Timer1 gate acquisition interrupt
bit 6 ADIE: Analog-to-Digital Converter (ADC) Interrupt Enable bit
1 = Enables the ADC interrupt
0 = Disables the ADC interrupt
bit 5 RCIE: USART Receive Interrupt Enable bit
1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt
bit 4 TXIE: USART Transmit Interrupt Enable bit
1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt
bit 3 SSP1IE: Synchronous Serial Port (MSSP) Interrupt Enable bit
1 = Enables the MSSP interrupt
0 = Disables the MSSP interrupt
bit 2 CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the Timer2 to PR2 match interrupt
0 = Disables the Timer2 to PR2 match interrupt
bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit
1 = Enables the Timer1 overflow interrupt
0 = Disables the Timer1 overflow interrupt

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

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 PIC16(L)F1704/8

REGISTER 7-3: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2

R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
OSFIE C2IE C1IE — BCL1IE TMR6IE TMR4IE CCP2IE
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 OSFIE: Oscillator Fail Interrupt Enable bit

1 = Enables the Oscillator Fail interrupt
0 = Disables the Oscillator Fail interrupt
bit 6 C2IE: Comparator C2 Interrupt Enable bit
1 = Enables the Comparator C2 interrupt
0 = Disables the Comparator C2 interrupt
bit 5 C1IE: Comparator C1 Interrupt Enable bit
1 = Enables the Comparator C1 interrupt
0 = Disables the Comparator C1 interrupt
bit 4 Unimplemented: Read as ‘0’
bit 3 BCL1IE: MSSP Bus Collision Interrupt Enable bit
1 = Enables the MSSP Bus Collision Interrupt
0 = Disables the MSSP Bus Collision Interrupt
bit 2 TMR6IE: TMR6 to PR6 Match Interrupt Enable bit
1 = Enables the Timer6 to PR6 match interrupt
0 = Disables the Timer6 to PR6 match interrupt
bit 1 TMR4IE: TMR4to PR4 Match Interrupt Enable bit
1 = Enables the Timer4 to PR4 match interrupt
0 = Disables the Timer4 to PR4 match interrupt
bit 0 CCP2IE: CCP2 Interrupt Enable bit
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

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PIC16(L)F1704/8

REGISTER 7-4: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3

U-0 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0
— — COGIE ZCDIE — CLC3IE CLC2IE CLC1IE
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5 COGIE: COG Auto-Shutdown Interrupt Enable bit
1 = COG interrupt enabled
0 = COG interrupt disabled
bit 4 ZCDIE: Zero-Cross Detection Interrupt Enable bit
1 = ZCD interrupt enabled
0 = ZCD interrupt disabled
bit 3 Unimplemented: Read as ‘0’
bit 2 CLC3IE: CLC3 Interrupt Enable bit
1 = CLC3 interrupt enabled
0 = CLC3 interrupt disabled
bit 1 CLC2IE: CLC2 Interrupt Enable bit
1 = CLC2 interrupt enabled
0 = CLC2 interrupt disabled
bit 0 CLC1IE: CLC1 Interrupt Enable bit
1 = CLC1 interrupt enabled
0 = CLC1 interrupt disabled

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

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 PIC16(L)F1704/8

REGISTER 7-5: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1

R/W-0/0 R/W-0/0 R-0/0 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 TMR1GIF: Timer1 Gate Interrupt Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending
bit 6 ADIF: Analog-to-Digital Converter (ADC) Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 5 RCIF: USART Receive Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 4 TXIF: USART Transmit Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 3 SSP1IF: Synchronous Serial Port (MSSP) Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 2 CCP1IF: CCP1 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 1 TMR2IF: Timer2 to PR2 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.

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PIC16(L)F1704/8

REGISTER 7-6: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2

R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
OSFIF C2IF C1IF — BCL1IF TMR6IF TMR4IF CCP2IF
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 OSFIF: Oscillator Fail Interrupt Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending
bit 6 C2IF: Comparator C2 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 5 C1IF: Comparator C1 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 4 Unimplemented: Read as ‘0’
bit 3 BCL1IF: MSSP Bus Collision Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 2 TMR6IF: Timer6 to PR6 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 1 TMR4IF: Timer4 to PR4 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 0 CCP2IF: CCP2 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.

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 PIC16(L)F1704/8

REGISTER 7-7: PIR3: PERIPHERAL INTERRUPT REQUEST REGISTER 3

U-0 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0
— — COGIF ZCDIF — CLC3IF CLC2IF CLC1IF
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5 COGIF: COG Auto-Shutdown Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 4 ZCDIF: Zero-Cross Detection Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 3 Unimplemented: Read as ‘0’
bit 2 CLC3IF: CLC3 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 1 CLC2IF: CLC2 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 0 CLC1IF: CLC1 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.

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PIC16(L)F1704/8
TABLE 7-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 85

OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 244
PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 86
PIE2 OSFIE C2IE C1IE — BCL1IE TMR6IE TMR4IE CCP2IE 87
PIE3 — — COGIE ZCDIE — CLC3IE CLC2IE CLC1IE 88
PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 89
PIR2 OSFIF C2IF C1IF — BCL1IF TMR6IF TMR4IF CCP2IF 90
PIR3 — — COGIF ZCDIF — CLC3IF CLC2IF CLC1IF 91
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by interrupts.

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 PIC16(L)F1704/8
8.0 POWER-DOWN MODE (SLEEP) 8.1 Wake-up from Sleep
The Power-down mode is entered by executing a The device can wake-up from Sleep through one of the
SLEEP instruction. following events:
Upon entering Sleep mode, the following conditions 1. External Reset input on MCLR pin, if enabled
exist: 2. BOR Reset, if enabled
1. WDT will be cleared but keeps running, if 3. POR Reset
enabled for operation during Sleep. 4. Watchdog Timer, if enabled
2. PD bit of the STATUS register is cleared. 5. Any external interrupt
3. TO bit of the STATUS register is set. 6. Interrupts by peripherals capable of running
4. CPU clock is disabled. during Sleep (see individual peripheral for more
5. 31 kHz LFINTOSC is unaffected and peripherals information)
that operate from it may continue operation in The first three events will cause a device Reset. The
Sleep. last three events are considered a continuation of
6. Timer1 and peripherals that operate from program execution. To determine whether a device
Timer1 continue operation in Sleep when the Reset or wake-up event occurred, refer to
Timer1 clock source selected is: Section 5.12 “Determining the Cause of a Reset”.
• LFINTOSC When the SLEEP instruction is being executed, the next
• T1CKI instruction (PC + 1) is prefetched. For the device to
• Secondary oscillator wake-up through an interrupt event, the corresponding
interrupt enable bit must be enabled. Wake-up will
7. ADC is unaffected, if the dedicated FRC
occur regardless of the state of the GIE bit. If the GIE
oscillator is selected.
bit is disabled, the device continues execution at the
8. I/O ports maintain the status they had before instruction after the SLEEP instruction. If the GIE bit is
SLEEP was executed (driving high, low or enabled, the device executes the instruction after the
high-impedance). SLEEP instruction, the device will then call the Interrupt
9. Resets other than WDT are not affected by Service Routine. In cases where the execution of the
Sleep mode. instruction following SLEEP is not desirable, the user
Refer to individual chapters for more details on should have a NOP after the SLEEP instruction.
peripheral operation during Sleep. The WDT is cleared when the device wakes up from
To minimize current consumption, the following Sleep, regardless of the source of wake-up.
conditions should be considered:
• I/O pins should not be floating
• External circuitry sinking current from I/O pins
• Internal circuitry sourcing current from I/O pins
• Current draw from pins with internal weak pull-ups
• Modules using 31 kHz LFINTOSC
• Modules using secondary oscillator
I/O pins that are high-impedance inputs should be
pulled to VDD or VSS externally to avoid switching
currents caused by floating inputs.
Examples of internal circuitry that might be sourcing
current include modules such as the DAC and FVR
modules. See Section 22.0 “8-Bit Digital-to-Analog
Converter (DAC1) Module” and Section 14.0 “Fixed
Voltage Reference (FVR)” for more information on
these modules.

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PIC16(L)F1704/8
8.1.1 WAKE-UP USING INTERRUPTS • If the interrupt occurs during or after the
execution of a SLEEP instruction
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit - SLEEP instruction will be completely
and interrupt flag bit set, one of the following will occur: executed
- Device will immediately wake-up from Sleep
• If the interrupt occurs before the execution of a
SLEEP instruction - WDT and WDT prescaler will be cleared
- SLEEP instruction will execute as a NOP - TO bit of the STATUS register will be set
- WDT and WDT prescaler will not be cleared - PD bit of the STATUS register will be cleared
- TO bit of the STATUS register will not be set Even if the flag bits were checked before executing a
- PD bit of the STATUS register will not be SLEEP instruction, it may be possible for flag bits to
cleared become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.

FIGURE 8-1: WAKE-UP FROM SLEEP THROUGH INTERRUPT

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLKIN(1)
CLKOUT(2) TOST(3)

Interrupt flag Interrupt Latency (4)

GIE bit
(INTCON reg.) Processor in
Sleep

Instruction Flow
PC PC PC + 1 PC + 2 PC + 2 PC + 2 0004h 0005h
Instruction Inst(PC + 1) Inst(PC + 2) Inst(0004h) Inst(0005h)
Fetched Inst(PC) = Sleep
Instruction Sleep Inst(PC + 1) Forced NOP Forced NOP
Executed Inst(PC - 1) Inst(0004h)

Note 1: External clock. High, Medium, Low mode assumed.

2: CLKOUT is shown here for timing reference.
3: TOST = 1024 TOSC. This delay does not apply to EC, RC and INTOSC Oscillator modes or Two-Speed Start-up (see Section 6.4
“Two-Speed Clock Start-up Mode”.
4: GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line.

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 PIC16(L)F1704/8
8.2 Low-Power Sleep Mode 8.2.2 PERIPHERAL USAGE IN SLEEP
The PIC16F1704/8 device contains an internal Low Some peripherals that can operate in Sleep mode will
Dropout (LDO) voltage regulator, which allows the not operate properly with the Low-Power Sleep mode
device I/O pins to operate at voltages up to 5.5V while selected. The Low-Power Sleep mode is intended for
the internal device logic operates at a lower voltage. use only with the following peripherals:
The LDO and its associated reference circuitry must • Brown-Out Reset (BOR)
remain active when the device is in Sleep mode. The • Watchdog Timer (WDT)
PIC16F1704/8 allows the user to optimize the
• External interrupt pin/Interrupt-on-change pins
operating current in Sleep, depending on the
application requirements. • Timer1 (with external clock source<100 kHz)

A Low-Power Sleep mode can be selected by setting

the VREGPM bit of the VREGCON register. With this Note: The PIC16LF1704/8 does not have a
bit set, the LDO and reference circuitry are placed in a configurable Low-Power Sleep mode.
low-power state when the device is in Sleep. PIC16LF1704/8 is an unregulated device
and is always in the lowest power state
8.2.1 SLEEP CURRENT VS. WAKE-UP when in Sleep, with no wake-up time
TIME penalty. This device has a lower maximum
In the default operating mode, the LDO and reference VDD and I/O voltage than the
circuitry remain in the normal configuration while in PIC16F1704/8. See Section 32.0
Sleep. The device is able to exit Sleep mode quickly “Electrical Specifications” for more
since all circuits remain active. In Low-Power Sleep information.
mode, when waking up from Sleep, an extra delay time
is required for these circuits to return to the normal
configuration and stabilize.
The Low-Power Sleep mode is beneficial for
applications that stay in Sleep mode for long periods of
time. The normal mode is beneficial for applications
that need to wake from Sleep quickly and frequently.

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PIC16(L)F1704/8
8.3 Register Definitions: Voltage Regulator Control

REGISTER 8-1: VREGCON: VOLTAGE REGULATOR CONTROL REGISTER(1)

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-1/1
— — — — — — VREGPM Reserved
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-2 Unimplemented: Read as ‘0’

bit 1 VREGPM: Voltage Regulator Power Mode Selection bit
1 = Low-Power Sleep mode enabled in Sleep(2)
Draws lowest current in Sleep, slower wake-up
0 = Normal-Power mode enabled in Sleep(2)
Draws higher current in Sleep, faster wake-up
bit 0 Reserved: Read as ‘1’. Maintain this bit set.

Note 1: PIC16F1704/8 only.

2: See Section 32.0 “Electrical Specifications”.

TABLE 8-1: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE

Register on
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Page

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 85

IOCAP — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 145
IOCAN — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 145
IOCAF — — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 145
IOCBP(1) IOCBP7 IOCBP6 IOCBP5 IOCBP4 — — — — 146
IOCBN(1) IOCBN7 IOCBN6 IOCBN5 IOCBN4 — — — — 146
(1)
IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 — — — — 146
IOCCP IOCCP7(1) IOCCP6(1) IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0 147
IOCCN IOCCN7(1) IOCCN6(1) IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0 147
IOCCF IOCCF7(1) IOCCF6(1) IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0 147
PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 86
PIE2 OSFIE C2IE C1IE — BCL1IE TMR6IE TMR4IE CCP2IE 87
PIE3 — — COGIE ZCDIE — CLC3IE CLC2IE CLC1IE 88
PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 89
PIR2 OSFIF C2IF C1IF — BCL1IF TMR6IF TMR4IF CCP2IF 90
PIR3 — — COGIF ZCDIF — CLC3IF CLC2IF CLC1IF 91
STATUS — — — TO PD Z DC C 23
VREGCON(2) — — — — — — VREGPM Reserved 96
WDTCON — — WDTPS<4:0> SWDTEN 100
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used in Power-Down mode.
Note 1: PIC16(L)F1708 only.
2: PIC16F1704/8 only.

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 PIC16(L)F1704/8
9.0 WATCHDOG TIMER (WDT)
The Watchdog Timer is a system timer that generates
a Reset if the firmware does not issue a CLRWDT
instruction within the time-out period. The Watchdog
Timer is typically used to recover the system from
unexpected events.
The WDT has the following features:
• Independent clock source
• Multiple operating modes
- WDT is always on
- WDT is off when in Sleep
- WDT is controlled by software
- WDT is always off
• Configurable time-out period is from 1 ms to 256
seconds (nominal)
• Multiple Reset conditions
• Operation during Sleep

FIGURE 9-1: WATCHDOG TIMER BLOCK DIAGRAM

WDTE<1:0> = 01
SWDTEN

WDTE<1:0> = 11 23-bit Programmable

LFINTOSC WDT Time-out
Prescaler WDT
WDTE<1:0> = 10
Sleep
WDTPS<4:0>

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PIC16(L)F1704/8
9.1 Independent Clock Source 9.4 Clearing the WDT
The WDT derives its time base from the 31 kHz The WDT is cleared when any of the following
LFINTOSC internal oscillator. Time intervals in this conditions occur:
chapter are based on a nominal interval of 1 ms. See • Any Reset
Table 32-8: Oscillator Parameters for the LFINTOSC
• CLRWDT instruction is executed
specification.
• Device enters Sleep
9.2 WDT Operating Modes • Device wakes up from Sleep
• Oscillator fail
The Watchdog Timer module has four operating modes
• WDT is disabled
controlled by the WDTE<1:0> bits in Configuration
Words. See Table 9-1. • Oscillator Start-up Timer (OST) is running
See Table 9-2 for more information.
9.2.1 WDT IS ALWAYS ON
When the WDTE bits of Configuration Words are set to 9.5 Operation During Sleep
‘11’, the WDT is always on.
When the device enters Sleep, the WDT is cleared. If
WDT protection is active during Sleep. the WDT is enabled during Sleep, the WDT resumes
counting.
9.2.2 WDT IS OFF IN SLEEP
When the device exits Sleep, the WDT is cleared
When the WDTE bits of Configuration Words are set to again. The WDT remains clear until the OST, if
‘10’, the WDT is on, except in Sleep. enabled, completes. See Section 6.0 “Oscillator
WDT protection is not active during Sleep. Module (with Fail-Safe Clock Monitor)” for more
information on the OST.
9.2.3 WDT CONTROLLED BY SOFTWARE When a WDT time-out occurs while the device is in
When the WDTE bits of Configuration Words are set to Sleep, no Reset is generated. Instead, the device
‘01’, the WDT is controlled by the SWDTEN bit of the wakes up and resumes operation. The TO and PD bits
WDTCON register. in the STATUS register are changed to indicate the
WDT protection is unchanged by Sleep. See Table 9-1 event. See STATUS Register (Register 3-1) for more
for more details. information.

TABLE 9-1: WDT OPERATING MODES

Device WDT
WDTE<1:0> SWDTEN
Mode Mode

11 X X Active
Awake Active
10 X
Sleep Disabled
1 Active
01 X
0 Disabled
00 X X Disabled

9.3 Time-Out Period

The WDTPS bits of the WDTCON register set the
time-out period from 1 ms to 256 seconds (nominal).
After a Reset, the default time-out period is two
seconds.

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 PIC16(L)F1704/8

TABLE 9-2: WDT CLEARING CONDITIONS

Conditions WDT
WDTE<1:0> = 00
WDTE<1:0> = 01 and SWDTEN = 0
WDTE<1:0> = 10 and enter Sleep
Cleared
CLRWDT Command
Oscillator Fail Detected
Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK
Exit Sleep + System Clock = XT, HS, LP Cleared until the end of OST
Change INTOSC divider (IRCF bits) Unaffected

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PIC16(L)F1704/8
9.6 Register Definitions: Watchdog Control

REGISTER 9-1: WDTCON: WATCHDOG TIMER CONTROL REGISTER

U-0 U-0 R/W-0/0 R/W-1/1 R/W-0/0 R/W-1/1 R/W-1/1 R/W-0/0
(1)
— — WDTPS<4:0> SWDTEN
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-1 WDTPS<4:0>: Watchdog Timer Period Select bits(1)
Bit Value = Prescale Rate
11111 = Reserved. Results in minimum interval (1:32)
•
•
•
10011 = Reserved. Results in minimum interval (1:32)

10010 = 1:8388608 (223) (Interval 256s nominal)

10001 = 1:4194304 (222) (Interval 128s nominal)
10000 = 1:2097152 (221) (Interval 64s nominal)
01111 = 1:1048576 (220) (Interval 32s nominal)
01110 = 1:524288 (219) (Interval 16s nominal)
01101 = 1:262144 (218) (Interval 8s nominal)
01100 = 1:131072 (217) (Interval 4s nominal)
01011 = 1:65536 (Interval 2s nominal) (Reset value)
01010 = 1:32768 (Interval 1s nominal)
01001 = 1:16384 (Interval 512 ms nominal)
01000 = 1:8192 (Interval 256 ms nominal)
00111 = 1:4096 (Interval 128 ms nominal)
00110 = 1:2048 (Interval 64 ms nominal)
00101 = 1:1024 (Interval 32 ms nominal)
00100 = 1:512 (Interval 16 ms nominal)
00011 = 1:256 (Interval 8 ms nominal)
00010 = 1:128 (Interval 4 ms nominal)
00001 = 1:64 (Interval 2 ms nominal)
00000 = 1:32 (Interval 1 ms nominal)
bit 0 SWDTEN: Software Enable/Disable for Watchdog Timer bit
If WDTE<1:0> = 1x:
This bit is ignored.
If WDTE<1:0> = 01:
1 = WDT is turned on
0 = WDT is turned off
If WDTE<1:0> = 00:
This bit is ignored.

Note 1: Times are approximate. WDT time is based on 31 kHz LFINTOSC.

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TABLE 9-3: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
OSCCON SPLLEN IRCF<3:0> — SCS<1:0> 77
STATUS — — — TO PD Z DC C 23
WDTCON — — WDTPS<4:0> SWDTEN 100
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by
Watchdog Timer.

TABLE 9-4: SUMMARY OF CONFIGURATION WORD WITH WATCHDOG TIMER

Register
Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0
on Page
13:8 — — FCMEN IESO CLKOUTEN BOREN<1:0> —
CONFIG1 49
7:0 CP MCLRE PWRTE WDTE<1:0> FOSC<2:0>
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Watchdog Timer.

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PIC16(L)F1704/8
10.0 FLASH PROGRAM MEMORY 10.1.1 PMCON1 AND PMCON2
CONTROL REGISTERS
PMCON1 is the control register for Flash program
The Flash program memory is readable and writable
memory accesses.
during normal operation over the full VDD range.
Program memory is indirectly addressed using Special Control bits RD and WR initiate read and write,
Function Registers (SFRs). The SFRs used to access respectively. These bits cannot be cleared, only set, in
program memory are: software. They are cleared by hardware at completion
of the read or write operation. The inability to clear the
• PMCON1
WR bit in software prevents the accidental, premature
• PMCON2 termination of a write operation.
• PMDATL
The WREN bit, when set, will allow a write operation to
• PMDATH occur. On power-up, the WREN bit is clear. The
• PMADRL WRERR bit is set when a write operation is interrupted
• PMADRH by a Reset during normal operation. In these situations,
following Reset, the user can check the WRERR bit
When accessing the program memory, the
and execute the appropriate error handling routine.
PMDATH:PMDATL register pair forms a 2-byte word
that holds the 14-bit data for read/write, and the The PMCON2 register is a write-only register. Attempting
PMADRH:PMADRL register pair forms a 2-byte word to read the PMCON2 register will return all ‘0’s.
that holds the 15-bit address of the program memory To enable writes to the program memory, a specific
location being read. pattern (the unlock sequence), must be written to the
The write time is controlled by an on-chip timer. The PMCON2 register. The required unlock sequence
write/erase voltages are generated by an on-chip charge prevents inadvertent writes to the program memory
pump rated to operate over the operating voltage range write latches and Flash program memory.
of the device.
The Flash program memory can be protected in two 10.2 Flash Program Memory Overview
ways; by code protection (CP bit in Configuration Words) It is important to understand the Flash program memory
and write protection (WRT<1:0> bits in Configuration structure for erase and programming operations. Flash
Words). program memory is arranged in rows. A row consists of
Code protection (CP = 0)(1), disables access, reading a fixed number of 14-bit program memory words. A row
and writing, to the Flash program memory via external is the minimum size that can be erased by user software.
device programmers. Code protection does not affect After a row has been erased, the user can reprogram
the self-write and erase functionality. Code protection all or a portion of this row. Data to be written into the
can only be reset by a device programmer performing program memory row is written to 14-bit wide data write
a Bulk Erase to the device, clearing all Flash program latches. These write latches are not directly accessible
memory, Configuration bits and User IDs. to the user, but may be loaded via sequential writes to
Write protection prohibits self-write and erase to a the PMDATH:PMDATL register pair.
portion or all of the Flash program memory as defined
Note: If the user wants to modify only a portion
by the bits WRT<1:0>. Write protection does not affect
of a previously programmed row, then the
a device programmers ability to read, write or erase the
contents of the entire row must be read
device.
and saved in RAM prior to the erase.
Note 1: Code protection of the entire Flash Then, new data and retained data can be
program memory array is enabled by written into the write latches to reprogram
clearing the CP bit of Configuration Words. the row of Flash program memory.
However, any unprogrammed locations
10.1 PMADRL and PMADRH Registers can be written without first erasing the row.
In this case, it is not necessary to save and
The PMADRH:PMADRL register pair can address up rewrite the other previously programmed
to a maximum of 32K words of program memory. When locations.
selecting a program address value, the MSB of the
See Table 10-1 for Erase Row size and the number of
address is written to the PMADRH register and the LSB
write latches for Flash program memory.
is written to the PMADRL register.

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 PIC16(L)F1704/8
FIGURE 10-1: FLASH PROGRAM
TABLE 10-1: FLASH MEMORY MEMORY READ
ORGANIZATION BY DEVICE FLOWCHART
Write
Row Erase
Device Latches
(words)
(words) Start
Read Operation
PIC16(L)F1704
32 32
PIC16(L)F1708
Select
10.2.1 READING THE FLASH PROGRAM Program or Configuration Memory
MEMORY (CFGS)
To read a program memory location, the user must:
1. Write the desired address to the
Select
PMADRH:PMADRL register pair. Word Address
2. Clear the CFGS bit of the PMCON1 register. (PMADRH:PMADRL)
3. Then, set control bit RD of the PMCON1 register.
Once the read control bit is set, the program memory
Flash controller will use the second instruction cycle to Initiate Read operation
(RD = 1)
read the data. This causes the second instruction
immediately following the “BSF PMCON1,RD” instruction
to be ignored. The data is available in the very next cycle,
in the PMDATH:PMDATL register pair; therefore, it can Instruction Fetched ignored
NOP execution forced
be read as two bytes in the following instructions.
PMDATH:PMDATL register pair will hold this value until
another read or until it is written to by the user.
Instruction Fetched ignored
Note: The two instructions following a program NOP execution forced
memory read are required to be NOPs.
This prevents the user from executing a
2-cycle instruction on the next instruction Data read now in
after the RD bit is set. PMDATH:PMDATL

End
Read Operation

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PIC16(L)F1704/8
FIGURE 10-2: FLASH PROGRAM MEMORY READ CYCLE EXECUTION

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Flash ADDR PC PC + 1 PMADRH,PMADRL PC +3

PC+3 PC + 4 PC + 5

Flash Data INSTR (PC) INSTR (PC + 1) PMDATH,PMDATL INSTR (PC + 3) INSTR (PC + 4)

INSTR(PC + 1) INSTR(PC + 2)
INSTR(PC - 1) BSF PMCON1,RD instruction ignored instruction ignored INSTR(PC + 3) INSTR(PC + 4)
executed here executed here Forced NOP Forced NOP executed here executed here
executed here executed here

RD bit

PMDATH
PMDATL
Register

EXAMPLE 10-1: FLASH PROGRAM MEMORY READ

* This code block will read 1 word of program

* memory at the memory address:
PROG_ADDR_HI : PROG_ADDR_LO
* data will be returned in the variables;
* PROG_DATA_HI, PROG_DATA_LO

BANKSEL PMADRL ; Select Bank for PMCON registers

MOVLW PROG_ADDR_LO ;
MOVWF PMADRL ; Store LSB of address
MOVLW PROG_ADDR_HI ;
MOVWF PMADRH ; Store MSB of address

BCF PMCON1,CFGS ; Do not select Configuration Space

BSF PMCON1,RD ; Initiate read
NOP ; Ignored (Figure 10-1)
NOP ; Ignored (Figure 10-1)

MOVF PMDATL,W ; Get LSB of word

MOVWF PROG_DATA_LO ; Store in user location
MOVF PMDATH,W ; Get MSB of word
MOVWF PROG_DATA_HI ; Store in user location

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10.2.2 FLASH MEMORY UNLOCK FIGURE 10-3: FLASH PROGRAM
SEQUENCE MEMORY UNLOCK
The unlock sequence is a mechanism that protects the SEQUENCE FLOWCHART
Flash program memory from unintended self-write
programming or erasing. The sequence must be
Start
executed and completed without interruption to
Unlock Sequence
successfully complete any of the following operations:
• Row Erase
• Load program memory write latches Write 055h to
• Write of program memory write latches to PMCON2
program memory
• Write of program memory write latches to User
IDs Write 0AAh to
PMCON2
The unlock sequence consists of the following steps:
1. Write 55h to PMCON2
Initiate
2. Write AAh to PMCON2
Write or Erase operation
3. Set the WR bit in PMCON1 (WR = 1)
4. NOP instruction
5. NOP instruction Instruction Fetched ignored
Once the WR bit is set, the processor will always force NOP execution forced
two NOP instructions. When an Erase Row or Program
Row operation is being performed, the processor will stall
internal operations (typical 2 ms), until the operation is Instruction Fetched ignored
complete and then resume with the next instruction. NOP execution forced
When the operation is loading the program memory write
latches, the processor will always force the two NOP
instructions and continue uninterrupted with the next End
instruction. Unlock Sequence
Since the unlock sequence must not be interrupted,
global interrupts should be disabled prior to the unlock
sequence and re-enabled after the unlock sequence is
completed.

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PIC16(L)F1704/8
10.2.3 ERASING FLASH PROGRAM FIGURE 10-4: FLASH PROGRAM
MEMORY MEMORY ERASE
While executing code, program memory can only be FLOWCHART
erased by rows. To erase a row:
1. Load the PMADRH:PMADRL register pair with Start
any address within the row to be erased. Erase Operation
2. Clear the CFGS bit of the PMCON1 register.
3. Set the FREE and WREN bits of the PMCON1
register. Disable Interrupts
4. Write 55h, then AAh, to PMCON2 (Flash (GIE = 0)
programming unlock sequence).
5. Set control bit WR of the PMCON1 register to Select
begin the erase operation. Program or Configuration Memory
See Example 10-2. (CFGS)

After the “BSF PMCON1,WR” instruction, the processor

requires two cycles to set up the erase operation. The Select Row Address
user must place two NOP instructions immediately (PMADRH:PMADRL)
following the WR bit set instruction. The processor will
halt internal operations for the typical 2 ms erase time.
This is not Sleep mode as the clocks and peripherals Select Erase Operation
will continue to run. After the erase cycle, the processor (FREE = 1)
will resume operation with the third instruction after the
PMCON1 write instruction.
Enable Write/Erase Operation
(WREN = 1)

Unlock Sequence
Figure 10-3
(FIGURE x-x)

CPU stalls while

Erase operation completes
(2ms typical)

Disable Write/Erase Operation

(WREN = 0)

Re-enable Interrupts
(GIE = 1)

End
Erase Operation

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 PIC16(L)F1704/8
EXAMPLE 10-2: ERASING ONE ROW OF PROGRAM MEMORY
; This row erase routine assumes the following:
; 1. A valid address within the erase row is loaded in ADDRH:ADDRL
; 2. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM)

BCF INTCON,GIE ; Disable ints so required sequences will execute properly

BANKSEL PMADRL
MOVF ADDRL,W ; Load lower 8 bits of erase address boundary
MOVWF PMADRL
MOVF ADDRH,W ; Load upper 6 bits of erase address boundary
MOVWF PMADRH
BCF PMCON1,CFGS ; Not configuration space
BSF PMCON1,FREE ; Specify an erase operation
BSF PMCON1,WREN ; Enable writes

MOVLW 55h ; Start of required sequence to initiate erase

MOVWF PMCON2 ; Write 55h
Sequence
Required

MOVLW 0AAh ;
MOVWF PMCON2 ; Write AAh
BSF PMCON1,WR ; Set WR bit to begin erase
NOP ; NOP instructions are forced as processor starts
NOP ; row erase of program memory.
;
; The processor stalls until the erase process is complete
; after erase processor continues with 3rd instruction

BCF PMCON1,WREN ; Disable writes

BSF INTCON,GIE ; Enable interrupts

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PIC16(L)F1704/8
10.2.4 WRITING TO FLASH PROGRAM The following steps should be completed to load the
MEMORY write latches and program a row of program memory.
These steps are divided into two parts. First, each write
Program memory is programmed using the following
latch is loaded with data from the PMDATH:PMDATL
steps:
using the unlock sequence with LWLO = 1. When the
1. Load the address in PMADRH:PMADRL of the last word to be loaded into the write latch is ready, the
row to be programmed. LWLO bit is cleared and the unlock sequence
2. Load each write latch with data. executed. This initiates the programming operation,
3. Initiate a programming operation. writing all the latches into Flash program memory.
4. Repeat steps 1 through 3 until all data is written. Note: The special unlock sequence is required
Before writing to program memory, the word(s) to be to load a write latch with data or initiate a
written must be erased or previously unwritten. Flash programming operation. If the
Program memory can only be erased one row at a time. unlock sequence is interrupted, writing to
No automatic erase occurs upon the initiation of the the latches or program memory will not be
write. initiated.
Program memory can be written one or more words at 1. Set the WREN bit of the PMCON1 register.
a time. The maximum number of words written at one 2. Clear the CFGS bit of the PMCON1 register.
time is equal to the number of write latches. See 3. Set the LWLO bit of the PMCON1 register.
Figure 10-5 (row writes to program memory with 32 When the LWLO bit of the PMCON1 register is
write latches) for more details. ‘1’, the write sequence will only load the write
The write latches are aligned to the Flash row address latches and will not initiate the write to Flash
boundary defined by the upper 10-bits of program memory.
PMADRH:PMADRL, (PMADRH<6:0>:PMADRL<7:5>) 4. Load the PMADRH:PMADRL register pair with
with the lower five bits of PMADRL, (PMADRL<4:0>) the address of the location to be written.
determining the write latch being loaded. Write 5. Load the PMDATH:PMDATL register pair with
operations do not cross these boundaries. At the the program memory data to be written.
completion of a program memory write operation, the
6. Execute the unlock sequence (Section 10.2.2
data in the write latches is reset to contain 0x3FFF.
“Flash Memory Unlock Sequence”). The write
latch is now loaded.
7. Increment the PMADRH:PMADRL register pair
to point to the next location.
8. Repeat steps 5 through 7 until all but the last
write latch has been loaded.
9. Clear the LWLO bit of the PMCON1 register.
When the LWLO bit of the PMCON1 register is
‘0’, the write sequence will initiate the write to
Flash program memory.
10. Load the PMDATH:PMDATL register pair with
the program memory data to be written.
11. Execute the unlock sequence (Section 10.2.2
“Flash Memory Unlock Sequence”). The
entire program memory latch content is now
written to Flash program memory.
Note: The program memory write latches are
reset to the blank state (0x3FFF) at the
completion of every write or erase
operation. As a result, it is not necessary
to load all the program memory write
latches. Unloaded latches will remain in
the blank state.
An example of the complete write sequence is shown in
Example 10-3. The initial address is loaded into the
PMADRH:PMADRL register pair; the data is loaded
using indirect addressing.

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 FIGURE 10-5: BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 32 WRITE LATCHES
DS40001715D-page 109

PIC16(L)F1704/8
7 6 0 7 5 4 0
Rev. 10-000004A_A0

7 5 0 7 0
PMADRH PMADRL - - PMDATH PMDATL
- r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 c4 c3 c2 c1 c0 6 8

14

Program Memory Write Latches

10 5
14 14 14 14

Write Latch #0 Write Latch #1 Write Latch #30 Write Latch #31
PMADRL<4:0> 00h 01h 1Eh 1Fh

14 14 14 14

Row Addr Addr Addr Addr

000h 0000h 0001h 001Eh 001Fh

001h 0020h 0021h 003Eh 003Fh
002h 0040h 0041h 005Eh 005Fh
CFGS = 0
 2013-2015 Microchip Technology Inc.

3FEh 7FC0h 7FC1h 7FDEh 7FDFh

Row 3FFh 7FE0h 7FE1h 7FFEh 7FFFh
Address
PMADRH<6:0>: Decode Flash Program Memory
PMADRL<7:5>

400h 8000h - 8003h 8004h – 8005h 8006h 8007h – 8008h 8009h - 801Fh
DEVICE ID Configuration
USER ID 0 - 3 reserved reserved
CFGS = 1 Dev / Rev Words

Configuration Memory
PIC16(L)F1704/8
FIGURE 10-6: FLASH PROGRAM MEMORY WRITE FLOWCHART

Start
Write Operation

Determine number of words Enable Write/Erase

to be written into Program or Operation (WREN = 1)
Configuration Memory.
The number of words cannot
exceed the number of words
per row.
(word_cnt) Load the value to write
(PMDATH:PMDATL)

Update the word counter Write Latches to Flash

Disable Interrupts
(word_cnt--) (LWLO = 0)
(GIE = 0)

Unlock Sequence
Select
Last word to Yes (Figure10-3
Figure x-x)
Program or Config. Memory
(CFGS) write ?

No CPU stalls while Write

Select Row Address operation completes
(PMADRH:PMADRL) (2ms typical)
Unlock Sequence
(Figure10-3
Figure x-x)

Select Write Operation

(FREE = 0)
Disable
No delay when writing to Write/Erase Operation
Program Memory Latches (WREN = 0)
Load Write Latches Only
(LWLO = 1)

Re-enable Interrupts
(GIE = 1)
Increment Address
(PMADRH:PMADRL++)

End
Write Operation

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 PIC16(L)F1704/8
EXAMPLE 10-3: WRITING TO FLASH PROGRAM MEMORY
; This write routine assumes the following:
; 1. 64 bytes of data are loaded, starting at the address in DATA_ADDR
; 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR,
; stored in little endian format
; 3. A valid starting address (the least significant bits = 00000) is loaded in ADDRH:ADDRL
; 4. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM)
;
BCF INTCON,GIE ; Disable ints so required sequences will execute properly
BANKSEL PMADRH ; Bank 3
MOVF ADDRH,W ; Load initial address
MOVWF PMADRH ;
MOVF ADDRL,W ;
MOVWF PMADRL ;
MOVLW LOW DATA_ADDR ; Load initial data address
MOVWF FSR0L ;
MOVLW HIGH DATA_ADDR ; Load initial data address
MOVWF FSR0H ;
BCF PMCON1,CFGS ; Not configuration space
BSF PMCON1,WREN ; Enable writes
BSF PMCON1,LWLO ; Only Load Write Latches
LOOP
MOVIW FSR0++ ; Load first data byte into lower
MOVWF PMDATL ;
MOVIW FSR0++ ; Load second data byte into upper
MOVWF PMDATH ;

MOVF PMADRL,W ; Check if lower bits of address are '00000'

XORLW 0x1F ; Check if we're on the last of 32 addresses
ANDLW 0x1F ;
BTFSC STATUS,Z ; Exit if last of 32 words,
GOTO START_WRITE ;

MOVLW 55h ; Start of required write sequence:

MOVWF PMCON2 ; Write 55h
MOVLW 0AAh ;
Sequence
Required

MOVWF PMCON2 ; Write AAh

BSF PMCON1,WR ; Set WR bit to begin write
NOP ; NOP instructions are forced as processor
; loads program memory write latches
NOP ;

INCF PMADRL,F ; Still loading latches Increment address

GOTO LOOP ; Write next latches

START_WRITE
BCF PMCON1,LWLO ; No more loading latches - Actually start Flash program
; memory write

MOVLW 55h ; Start of required write sequence:

MOVWF PMCON2 ; Write 55h
Sequence

MOVLW 0AAh ;
Required

MOVWF PMCON2 ; Write AAh

BSF PMCON1,WR ; Set WR bit to begin write
NOP ; NOP instructions are forced as processor writes
; all the program memory write latches simultaneously
NOP ; to program memory.
; After NOPs, the processor
; stalls until the self-write process in complete
; after write processor continues with 3rd instruction
BCF PMCON1,WREN ; Disable writes
BSF INTCON,GIE ; Enable interrupts

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PIC16(L)F1704/8
10.3 Modifying Flash Program Memory FIGURE 10-7: FLASH PROGRAM
MEMORY MODIFY
When modifying existing data in a program memory
FLOWCHART
row, and data within that row must be preserved, it must
first be read and saved in a RAM image. Program
memory is modified using the following steps:
Start
1. Load the starting address of the row to be Modify Operation
modified.
2. Read the existing data from the row into a RAM
image.
Read Operation
3. Modify the RAM image to contain the new data (Figure10-1
Figure x.x)
to be written into program memory.
4. Load the starting address of the row to be
rewritten. An image of the entire row read
5. Erase the program memory row. must be stored in RAM
6. Load the write latches with data from the RAM
image.
7. Initiate a programming operation.
Modify Image
The words to be modified are
changed in the RAM image

Erase Operation
(Figure10-4
Figure x.x)

Write Operation
use RAM image
(Figure10-6
Figure x.x)

End
Modify Operation

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10.4 User ID, Device ID and
Configuration Word Access
Instead of accessing program memory, the User ID’s,
Device ID/Revision ID and Configuration Words can be
accessed when CFGS = 1 in the PMCON1 register.
This is the region that would be pointed to by
PC<15> = 1, but not all addresses are accessible.
Different access may exist for reads and writes. Refer
to Table 10-2.
When read access is initiated on an address outside
the parameters listed in Table 10-2, the
PMDATH:PMDATL register pair is cleared, reading
back ‘0’s.

TABLE 10-2: USER ID, DEVICE ID AND CONFIGURATION WORD ACCESS (CFGS = 1)
Address Function Read Access Write Access
8000h-8003h User IDs Yes Yes
8005h-8006h Device ID/Revision ID Yes No
8007h-8008h Configuration Words 1 and 2 Yes No

EXAMPLE 10-4: CONFIGURATION WORD AND DEVICE ID ACCESS

* This code block will read 1 word of program memory at the memory address:
* PROG_ADDR_LO (must be 00h-08h) data will be returned in the variables;
* PROG_DATA_HI, PROG_DATA_LO

BANKSEL PMADRL ; Select correct Bank

MOVLW PROG_ADDR_LO ;
MOVWF PMADRL ; Store LSB of address
CLRF PMADRH ; Clear MSB of address

BSF PMCON1,CFGS ; Select Configuration Space

BCF INTCON,GIE ; Disable interrupts
BSF PMCON1,RD ; Initiate read
NOP ; Executed (See Figure 10-2)
NOP ; Ignored (See Figure 10-2)
BSF INTCON,GIE ; Restore interrupts

MOVF PMDATL,W ; Get LSB of word

MOVWF PROG_DATA_LO ; Store in user location
MOVF PMDATH,W ; Get MSB of word
MOVWF PROG_DATA_HI ; Store in user location

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10.5 Write Verify
It is considered good programming practice to verify that
program memory writes agree with the intended value.
Since program memory is stored as a full page then the
stored program memory contents are compared with the
intended data stored in RAM after the last write is
complete.

FIGURE 10-8: FLASH PROGRAM

MEMORY VERIFY
FLOWCHART

Start
Verify Operation

This routine assumes that the last row

of data written was from an image
saved in RAM. This image will be used
to verify the data currently stored in
Flash Program Memory.

Read Operation
(Figure
Figure x.x)
10-1

PMDAT = No
RAM image
?

Yes Fail
Verify Operation

No Last
Word ?

Yes

End
Verify Operation

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10.6 Register Definitions: Flash Program Memory Control

REGISTER 10-1: PMDATL: PROGRAM MEMORY DATA LOW BYTE REGISTER

R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
PMDAT<7:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 PMDAT<7:0>: Read/write value for Least Significant bits of program memory

REGISTER 10-2: PMDATH: PROGRAM MEMORY DATA HIGH BYTE REGISTER

U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
— — PMDAT<13:8>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 PMDAT<13:8>: Read/write value for Most Significant bits of program memory

REGISTER 10-3: PMADRL: PROGRAM MEMORY ADDRESS LOW BYTE REGISTER

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
PMADR<7:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 PMADR<7:0>: Specifies the Least Significant bits for program memory address

REGISTER 10-4: PMADRH: PROGRAM MEMORY ADDRESS HIGH BYTE REGISTER

U-1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
—(1) PMADR<14:8>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 Unimplemented: Read as ‘1’

bit 6-0 PMADR<14:8>: Specifies the Most Significant bits for program memory address

Note 1: Unimplemented, read as ‘1’.

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REGISTER 10-5: PMCON1: PROGRAM MEMORY CONTROL 1 REGISTER

U-1 R/W-0/0 R/W-0/0 R/W/HC-0/0 R/W/HC-x/q(2) R/W-0/0 R/S/HC-0/0 R/S/HC-0/0
—(1) CFGS LWLO(3) FREE WRERR WREN WR RD
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware

bit 7 Unimplemented: Read as ‘1’

bit 6 CFGS: Configuration Select bit
1 = Access Configuration, User ID and Device ID Registers
0 = Access Flash program memory
bit 5 LWLO: Load Write Latches Only bit(3)
1 = Only the addressed program memory write latch is loaded/updated on the next WR command
0 = The addressed program memory write latch is loaded/updated and a write of all program memory write latches
will be initiated on the next WR command
bit 4 FREE: Program Flash Erase Enable bit
1 = Performs an erase operation on the next WR command (hardware cleared upon completion)
0 = Performs a write operation on the next WR command
bit 3 WRERR: Program/Erase Error Flag bit
1 = Condition indicates an improper program or erase sequence attempt or termination (bit is set automatically
on any set attempt (write ‘1’) of the WR bit).
0 = The program or erase operation completed normally
bit 2 WREN: Program/Erase Enable bit
1 = Allows program/erase cycles
0 = Inhibits programming/erasing of program Flash
bit 1 WR: Write Control bit
1 = Initiates a program Flash program/erase operation.
The operation is self-timed and the bit is cleared by hardware once operation is complete.
The WR bit can only be set (not cleared) in software.
0 = Program/erase operation to the Flash is complete and inactive
bit 0 RD: Read Control bit
1 = Initiates a program Flash read. Read takes one cycle. RD is cleared in hardware. The RD bit can only be set
(not cleared) in software.
0 = Does not initiate a program Flash read
Note 1: Unimplemented bit, read as ‘1’.
2: The WRERR bit is automatically set by hardware when a program memory write or erase operation is started (WR = 1).
3: The LWLO bit is ignored during a program memory erase operation (FREE = 1).

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REGISTER 10-6: PMCON2: PROGRAM MEMORY CONTROL 2 REGISTER

W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0
Program Memory Control Register 2
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 Flash Memory Unlock Pattern bits

To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the
PMCON1 register. The value written to this register is used to unlock the writes. There are specific
timing requirements on these writes.

TABLE 10-3: SUMMARY OF REGISTERS ASSOCIATED WITH FLASH PROGRAM MEMORY

Register on
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Page
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 85
PMCON1 — (1) CFGS LWLO FREE WRERR WREN WR RD 116
PMCON2 Program Memory Control Register 2 117
PMADRL PMADRL<7:0> 115
(1)
PMADRH — PMADRH<6:0> 115
PMDATL PMDATL<7:0> 115
PMDATH — — PMDATH<5:0> 115
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Flash program memory.
Note 1: Unimplemented, read as ‘1’.

TABLE 10-4: SUMMARY OF CONFIGURATION WORD WITH FLASH PROGRAM MEMORY

Register
Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0
on Page

13:8 — — — — CLKOUTEN BOREN<1:0> —

CONFIG1 49
7:0 CP MCLRE PWRTE WDTE<1:0> — FOSC<1:0>
CONFIG2 13:8 — — LVP DEBUG LPBOR BORV STVREN PLLEN
51
7:0 ZCDDIS — — — — PPS1WAY WRT<1:0>
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Flash program memory.

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11.0 I/O PORTS FIGURE 11-1: GENERIC I/O PORT
OPERATION
Each port has six standard registers for its operation.
These registers are:
• TRISx registers (data direction)
• PORTx registers (reads the levels on the pins of Read LATx
TRISx
the device)
• LATx registers (output latch) D Q

• INLVLx (input level control) Write LATx

Write PORTx
• ODCONx registers (open-drain) CK VDD
• SLRCONx registers (slew rate Data Register
Some ports may have one or more of the following
additional registers. These registers are: Data Bus
I/O pin
• ANSELx (analog select) Read PORTx
• WPUx (weak pull-up)
To digital peripherals
In general, when a peripheral is enabled on a port pin, VSS
ANSELx
that pin cannot be used as a general purpose output. To analog peripherals
However, the pin can still be read.

TABLE 11-1: PORT AVAILABILITY PER

DEVICE
PORTB

PORTC
PORTA

Device

PIC16(L)F1704 ● ●
PIC16(L)F1708 ● ● ●
The Data Latch (LATx registers) is useful for
read-modify-write operations on the value that the I/O
pins are driving.
A write operation to the LATx register has the same
effect as a write to the corresponding PORTx register.
A read of the LATx register reads of the values held in
the I/O PORT latches, while a read of the PORTx
register reads the actual I/O pin value.
Ports that support analog inputs have an associated
ANSELx register. When an ANSEL bit is set, the digital
input buffer associated with that bit is disabled.
Disabling the input buffer prevents analog signal levels
on the pin between a logic high and low from causing
excessive current in the logic input circuitry. A
simplified model of a generic I/O port, without the
interfaces to other peripherals, is shown in Figure 11-1.

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11.1 PORTA Registers 11.1.5 INPUT THRESHOLD CONTROL
The INLVLA register (Register 11-8) controls the input
11.1.1 DATA REGISTER voltage threshold for each of the available PORTA input
PORTA is a 6-bit wide, bidirectional port. The pins. A selection between the Schmitt Trigger CMOS or
corresponding data direction register is TRISA the TTL Compatible thresholds is available. The input
(Register 11-2). Setting a TRISA bit (= 1) will make the threshold is important in determining the value of a read
corresponding PORTA pin an input (i.e., disable the of the PORTA register and also the level at which an
output driver). Clearing a TRISA bit (= 0) will make the interrupt-on-change occurs, if that feature is enabled.
corresponding PORTA pin an output (i.e., enables See Table 32-4: I/O Ports for more information on
output driver and puts the contents of the output latch threshold levels.
on the selected pin). The exception is RA3, which is
Note: Changing the input threshold selection
input-only and its TRIS bit will always read as ‘1’.
should be performed while all peripheral
Example 11-1 shows how to initialize PORTA.
modules are disabled. Changing the
Reading the PORTA register (Register 11-1) reads the threshold level during the time a module is
status of the pins, whereas writing to it will write to the active may inadvertently generate a
PORT latch. All write operations are read-modify-write transition associated with an input pin,
operations. Therefore, a write to a port implies that the regardless of the actual voltage level on
port pins are read, this value is modified and then that pin.
written to the PORT data latch (LATA).
11.1.6 ANALOG CONTROL
11.1.2 DIRECTION CONTROL
The ANSELA register (Register 11-4) is used to
The TRISA register (Register 11-2) controls the configure the Input mode of an I/O pin to analog.
PORTA pin output drivers, even when they are being Setting the appropriate ANSELA bit high will cause all
used as analog inputs. The user should ensure the bits digital reads on the pin to be read as ‘0’ and allow
in the TRISA register are maintained set when using analog functions on the pin to operate correctly.
them as analog inputs. I/O pins configured as analog
The state of the ANSELA bits has no effect on digital
inputs always read ‘0’.
output functions. A pin with TRIS clear and ANSEL set
11.1.3 OPEN-DRAIN CONTROL will still operate as a digital output, but the Input mode
will be analog. This can cause unexpected behavior
The ODCONA register (Register 11-6) controls the when executing read-modify-write instructions on the
open-drain feature of the port. Open-drain operation is affected port.
independently selected for each pin. When an
ODCONA bit is set, the corresponding port output Note: The ANSELA bits default to the Analog
becomes an open-drain driver capable of sinking mode after Reset. To use any pins as
current only. When an ODCONA bit is cleared, the digital general purpose or peripheral
corresponding port output pin is the standard push-pull inputs, the corresponding ANSEL bits
drive capable of sourcing and sinking current. must be initialized to ‘0’ by user software.

11.1.4 SLEW RATE CONTROL EXAMPLE 11-1: INITIALIZING PORTA

; This code example illustrates
The SLRCONA register (Register 11-7) controls the
; initializing the PORTA register. The
slew rate option for each port pin. Slew rate control is ; other ports are initialized in the same
independently selectable for each port pin. When an ; manner.
SLRCONA bit is set, the corresponding port pin drive is
slew rate limited. When an SLRCONA bit is cleared, BANKSEL PORTA ;
The corresponding port pin drive slews at the maximum CLRF PORTA ;Init PORTA
rate possible. BANKSEL LATA ;Data Latch
CLRF LATA ;
BANKSEL ANSELA ;
CLRF ANSELA ;digital I/O
BANKSEL TRISA ;
MOVLW B'00111000' ;Set RA<5:3> as inputs
MOVWF TRISA ;and set RA<2:0> as
;outputs

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11.1.7 PORTA FUNCTIONS AND OUTPUT
PRIORITIES
Each PORTA pin is multiplexed with other functions.
Each pin defaults to the PORT latch data after Reset.
Other functions are selected with the peripheral pin
select logic. See Section 12.0 “Peripheral Pin Select
(PPS) Module” for more information.
Analog input functions, such as ADC and comparator
inputs are not shown in the peripheral pin select lists.
These inputs are active when the I/O pin is set for
Analog mode using the ANSELA register. Digital output
functions may continue to control the pin when it is in
Analog mode.

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11.2 Register Definitions: PORTA

REGISTER 11-1: PORTA: PORTA REGISTER

U-0 U-0 R/W-x/x R/W-x/x R-x/x R/W-x/x R/W-x/x R/W-x/x
— — RA5 RA4 RA3 RA2 RA1 RA0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 RA<5:0>: PORTA I/O Value bits(1)
1 = Port pin is > VIH
0 = Port pin is < VIL

Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return
of actual I/O pin values.

REGISTER 11-2: TRISA: PORTA TRI-STATE REGISTER

U-0 U-0 R/W-1/1 R/W-1/1 U-1 R/W-1/1 R/W-1/1 R/W-1/1
— — TRISA5 TRISA4 —(1) TRISA2 TRISA1 TRISA0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4 TRISA<5:4>: PORTA Tri-State Control bit
1 = PORTA pin configured as an input (tri-stated)
0 = PORTA pin configured as an output
bit 3 Unimplemented: Read as ‘1’
bit 2-0 TRISA<2:0>: PORTA Tri-State Control bit
1 = PORTA pin configured as an input (tri-stated)
0 = PORTA pin configured as an output

Note 1: Unimplemented, read as ‘1’.

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REGISTER 11-3: LATA: PORTA DATA LATCH REGISTER

U-0 U-0 R/W-x/u R/W-x/u U-0 R/W-x/u R/W-x/u R/W-x/u
— — LATA5 LATA4 — LATA2 LATA1 LATA0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4 LATA<5:4>: RA<5:4> Output Latch Value bits(1)
bit 3 Unimplemented: Read as ‘0’
bit 2-0 LATA<2:0>: RA<2:0> Output Latch Value bits(1)

Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return
of actual I/O pin values.

REGISTER 11-4: ANSELA: PORTA ANALOG SELECT REGISTER

U-0 U-0 U-0 R/W-1/1 U-0 R/W-1/1 R/W-1/1 R/W-1/1
— — — ANSA4 — ANSA2 ANSA1 ANSA0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-5 Unimplemented: Read as ‘0’

bit 4 ANSA4: Analog Select between Analog or Digital Function on pin RA4
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
0 = Digital I/O. Pin is assigned to port or digital special function.
bit 3 Unimplemented: Read as ‘0’
bit 2-0 ANSA<2:0>: Analog Select between Analog or Digital Function on pins RA<2:0>, respectively
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
0 = Digital I/O. Pin is assigned to port or digital special function.

Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.

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REGISTER 11-5: WPUA: WEAK PULL-UP PORTA REGISTER

U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1
— — WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 WPUA<5:0>: Weak Pull-up Register bits
1 = Pull-up enabled
0 = Pull-up disabled
Note 1: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is configured as an output.

REGISTER 11-6: ODCONA: PORTA OPEN-DRAIN CONTROL REGISTER

U-0 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0
— — ODA5 ODA4 — ODA2 ODA1 ODA0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4 ODA<5:4>: PORTA Open-Drain Enable bits
For RA<5:4> pins, respectively
1 = Port pin operates as open-drain drive (sink current only)
0 = Port pin operates as standard push-pull drive (source and sink current)
bit 3 Unimplemented: Read as ‘0’
bit 2-0 ODA<2:0>: PORTA Open-Drain Enable bits
For RA<2:0> pins, respectively
1 = Port pin operates as open-drain drive (sink current only)
0 = Port pin operates as standard push-pull drive (source and sink current)

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REGISTER 11-7: SLRCONA: PORTA SLEW RATE CONTROL REGISTER

U-0 U-0 R/W-1/1 R/W-1/1 U-0 R/W-1/1 R/W-1/1 R/W-1/1
— — SLRA5 SLRA4 — SLRA2 SLRA1 SLRA0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4 SLRA<5:4>: PORTA Slew Rate Enable bits
For RA<5:4> pins, respectively
1 = Port pin slew rate is limited
0 = Port pin slews at maximum rate
bit 3 Unimplemented: Read as ‘0’
bit 2-0 SLRA<2:0>: PORTA Slew Rate Enable bits
For RA<2:0> pins, respectively
1 = Port pin slew rate is limited
0 = Port pin slews at maximum rate

REGISTER 11-8: INLVLA: PORTA INPUT LEVEL CONTROL REGISTER

U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 INLVLA<5:0>: PORTA Input Level Select bits
For RA<5:0> pins, respectively
1 = ST input used for PORT reads and interrupt-on-change
0 = TTL input used for PORT reads and interrupt-on-change

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TABLE 11-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page

ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 122

INLVLA — — INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 124
LATA — — LATA5 LATA4 — LATA2 LATA1 LATA0 122
ODCONA — — ODA5 ODA4 — ODA2 ODA1 ODA0 123
OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 244
PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 121
SLRCONA — — SLRA5 SLRA4 — SLRA2 SLRA1 SLRA0 124
(1)
TRISA — — TRISA5 TRISA4 — TRISA2 TRISA1 TRISA0 121
WPUA — — WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 123
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.
Note 1: Unimplemented, read as ‘1’.

TABLE 11-3: SUMMARY OF CONFIGURATION WORD WITH PORTA

Register
Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0
on Page

13:8 — — FCMEN IESO CLKOUTEN BOREN<1:0> —

CONFIG1 49
7:0 CP MCLRE PWRTE WDTE<1:0> FOSC<2:0>
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by PORTA.

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11.3 PORTB Registers 11.3.4 INPUT THRESHOLD CONTROL
(PIC16(L)F1708 only) The INLVLB register (Register 11-16) controls the input
voltage threshold for each of the available PORTB input
PORTB is a 4-bit wide, bidirectional port. The
pins. A selection between the Schmitt Trigger CMOS or
corresponding data direction register is TRISB
the TTL Compatible thresholds is available. The input
(Register 11-10). Setting a TRISB bit (= 1) will make the
threshold is important in determining the value of a read
corresponding PORTB pin an input (i.e., put the
of the PORTB register and also the level at which an
corresponding output driver in a High-Impedance mode).
interrupt-on-change occurs, if that feature is enabled.
Clearing a TRISB bit (= 0) will make the corresponding
See Table 32-4: I/O Ports for more information on
PORTB pin an output (i.e., enable the output driver and
threshold levels.
put the contents of the output latch on the selected pin).
Example 11-1 shows how to initialize an I/O port. Note: Changing the input threshold selection
Reading the PORTB register (Register 11-9) reads the should be performed while all peripheral
status of the pins, whereas writing to it will write to the modules are disabled. Changing the
PORT latch. All write operations are read-modify-write threshold level during the time a module is
operations. Therefore, a write to a port implies that the active may inadvertently generate a
port pins are read, this value is modified and then written transition associated with an input pin,
to the PORT data latch (LATB). regardless of the actual voltage level on
that pin.
11.3.1 DIRECTION CONTROL
11.3.5 ANALOG CONTROL
The TRISB register (Register 11-10) controls the
PORTB pin output drivers, even when they are being The ANSELB register (Register 11-12) is used to
used as analog inputs. The user should ensure the bits in configure the Input mode of an I/O pin to analog.
the TRISB register are maintained set when using them Setting the appropriate ANSELB bit high will cause all
as analog inputs. I/O pins configured as analog inputs digital reads on the pin to be read as ‘0’ and allow
always read ‘0’. analog functions on the pin to operate correctly.
The state of the ANSELB bits has no effect on digital
11.3.2 OPEN-DRAIN CONTROL output functions. A pin with TRIS clear and ANSELB set
The ODCONB register (Register 11-14) controls the will still operate as a digital output, but the Input mode
open-drain feature of the port. Open-drain operation is will be analog. This can cause unexpected behavior
independently selected for each pin. When an when executing read-modify-write instructions on the
ODCONB bit is set, the corresponding port output affected port.
becomes an open-drain driver capable of sinking Note: The ANSELB bits default to the Analog
current only. When an ODCONB bit is cleared, the mode after Reset. To use any pins as
corresponding port output pin is the standard push-pull digital general purpose or peripheral
drive capable of sourcing and sinking current. inputs, the corresponding ANSEL bits
must be initialized to ‘0’ by user software.
11.3.3 SLEW RATE CONTROL
The SLRCONB register (Register 11-15) controls the 11.3.6 PORTB FUNCTIONS AND OUTPUT
slew rate option for each port pin. Slew rate control is PRIORITIES
independently selectable for each port pin. When an
Each pin defaults to the PORT latch data after reset.
SLRCONB bit is set, the corresponding port pin drive is
Other functions are selected with the peripheral pin
slew rate limited. When an SLRCONB bit is cleared,
select logic. See Section 12.0 “Peripheral Pin Select
The corresponding port pin drive slews at the maximum
(PPS) Module” for more information. Analog input
rate possible.
functions, such as ADC and Op Amp inputs, are not
shown in the peripheral pin select lists. These inputs
are active when the I/O pin is set for Analog mode using
the ANSELB register. Digital output functions may
continue to control the pin when it is in Analog mode.

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11.4 Register Definitions: PORTB
REGISTER 11-9: PORTB: PORTB REGISTER
R/W-x/u R/W-x/u R/W-x/u R/W-x/u U-0 U-0 U-0 U-0
RB7 RB6 RB5 RB4 — — — —
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-4 RB<7:4>: PORTB General Purpose I/O Pin bits(1)

1 = Port pin is > VIH
0 = Port pin is < VIL
bit 3-0 Unimplemented: Read as ‘0’

Note 1: Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is return of
actual I/O pin values.

REGISTER 11-10: TRISB: PORTB TRI-STATE REGISTER

R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 U-0 U-0 U-0 U-0
TRISB7 TRISB6 TRISB5 TRISB4 — — — —
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-4 TRISB<7:4>: PORTB Tri-State Control bits

1 = PORTB pin configured as an input (tri-stated)
0 = PORTB pin configured as an output
bit 3-0 Unimplemented: Read as ‘0’

REGISTER 11-11: LATB: PORTB DATA LATCH REGISTER

R/W-x/u R/W-x/u R/W-x/u R/W-x/u U-0 U-0 U-0 U-0
LATB7 LATB6 LATB5 LATB4 — — — —
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-4 LATB<7:4>: PORTB Output Latch Value bits(1)

bit 3-0 Unimplemented: Read as ‘0’

Note 1: Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is return of
actual I/O pin values.

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REGISTER 11-12: ANSELB: PORTB ANALOG SELECT REGISTER

U-0 U-0 R/W-1/1 R/W-1/1 U-0 U-0 U-0 U-0
— — ANSB5 ANSB4 — — — —
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4 ANSB<5:4>: Analog Select between Analog or Digital Function on pins RB<5:4>, respectively
0 = Digital I/O. Pin is assigned to port or digital special function.
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
bit 3-0 Unimplemented: Read as ‘0’

Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.

REGISTER 11-13: WPUB: WEAK PULL-UP PORTB REGISTER

R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 U-0 U-0 U-0 U-0
WPUB7 WPUB6 WPUB5 WPUB4 — — — —
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-4 WPUB<7:4>: Weak Pull-up Register bits

1 = Pull-up enabled
0 = Pull-up disabled
bit 3-0 Unimplemented: Read as ‘0’

Note 1: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is configured as an output.

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REGISTER 11-14: ODCONB: PORTB OPEN-DRAIN CONTROL REGISTER

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0
ODB7 ODB6 ODB5 ODB4 — — — —
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-4 ODB<7:4>: PORTB Open-Drain Enable bits

For RB<7:4> pins, respectively
1 = Port pin operates as open-drain drive (sink current only)
0 = Port pin operates as standard push-pull drive (source and sink current)
bit 3-0 Unimplemented: Read as ‘0’

REGISTER 11-15: SLRCONB: PORTB SLEW RATE CONTROL REGISTER

R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 U-0 U-0 U-0 U-0
SLRB7 SLRB6 SLRB5 SLRB4 — — — —
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-4 SLRB<7:4>: PORTB Slew Rate Enable bits

For RB<7:4> pins, respectively
1 = Port pin slew rate is limited
0 = Port pin slews at maximum rate
bit 3-0 Unimplemented: Read as ‘0’

REGISTER 11-16: INLVLB: PORTB INPUT LEVEL CONTROL REGISTER

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0
INLVLB7 INLVLB6 INLVLB5 INLVLB4 — — — —
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-4 INLVLB<7:4>: PORTB Input Level Select bits

For RB<7:4> pins, respectively
1 = ST input used for PORT reads and interrupt-on-change
0 = TTL input used for PORT reads and interrupt-on-change
bit 3-0 Unimplemented: Read as ‘0’

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TABLE 11-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
ANSELB — — ANSB5 ANSB4 — — — — 128
INLVLB INLVLB7 INLVLB6 INLVLB5 INLVLB4 — — — — 129
LATB LATB7 LATB6 LATB5 LATB4 — — — — 127
ODCONB ODB7 ODB6 ODB5 ODB4 — — — — 129
PORTB RB7 RB6 RB5 RB4 — — — — 127
SLRCONB SLRB7 SLRB6 SLRB5 SLRB4 — — — — 129
TRISB TRISB7 TRISB6 TRISB5 TRISB4 — — — — 129
WPUB WPUB7 WPUB6 WPUB5 WPUB4 — — — — 128
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by
PORTB.

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11.5 PORTC Registers 11.5.4 OPEN-DRAIN CONTROL
The ODCONC register (Register 11-22) controls the
11.5.1 DATA REGISTER open-drain feature of the port. Open-drain operation is
PORTC is a 6-bit wide bidirectional port in the independently selected for each pin. When an
PIC16(L)F1704 device and 8-bit wide bidirectional port in ODCONC bit is set, the corresponding port output
the PIC16(L)F1708 device. The corresponding data becomes an open-drain driver capable of sinking
direction register is TRISC (Register 11-18). Setting a current only. When an ODCONC bit is cleared, the
TRISC bit (= 1) will make the corresponding PORTC pin corresponding port output pin is the standard push-pull
an input (i.e., put the corresponding output driver in a drive capable of sourcing and sinking current.
High-Impedance mode). Clearing a TRISC bit (= 0) will
make the corresponding PORTC pin an output (i.e., 11.5.5 SLEW RATE CONTROL
enable the output driver and put the contents of the The SLRCONC register (Register 11-23) controls the
output latch on the selected pin). Example 11-1 shows slew rate option for each port pin. Slew rate control is
how to initialize an I/O port. independently selectable for each port pin. When an
Reading the PORTC register (Register 11-17) reads the SLRCONC bit is set, the corresponding port pin drive is
status of the pins, whereas writing to it will write to the slew rate limited. When an SLRCONC bit is cleared,
PORT latch. All write operations are read-modify-write The corresponding port pin drive slews at the maximum
operations. Therefore, a write to a port implies that the rate possible.
port pins are read, this value is modified and then written
to the PORT data latch (LATC). 11.5.6 ANALOG CONTROL
The ANSELC register (Register 11-20) is used to
11.5.2 DIRECTION CONTROL configure the Input mode of an I/O pin to analog.
The TRISC register (Register 11-18) controls the Setting the appropriate ANSELC bit high will cause all
PORTC pin output drivers, even when they are being digital reads on the pin to be read as ‘0’ and allow
used as analog inputs. The user should ensure the bits in analog functions on the pin to operate correctly.
the TRISC register are maintained set when using them The state of the ANSELC bits has no effect on digital
as analog inputs. I/O pins configured as analog inputs output functions. A pin with TRIS clear and ANSELC set
always read ‘0’. will still operate as a digital output, but the Input mode
will be analog. This can cause unexpected behavior
11.5.3 INPUT THRESHOLD CONTROL when executing read-modify-write instructions on the
The INLVLC register (Register 11-24) controls the input affected port.
voltage threshold for each of the available PORTC
Note: The ANSELC bits default to the Analog
input pins. A selection between the Schmitt Trigger
mode after Reset. To use any pins as
CMOS or the TTL Compatible thresholds is available.
digital general purpose or peripheral
The input threshold is important in determining the
inputs, the corresponding ANSEL bits
value of a read of the PORTC register and also the
must be initialized to ‘0’ by user software.
level at which an interrupt-on-change occurs, if that
feature is enabled. See Table 32-4: I/O Ports for more 11.5.7 PORTC FUNCTIONS AND OUTPUT
information on threshold levels. PRIORITIES
Note: Changing the input threshold selection Each pin defaults to the PORT latch data after reset.
should be performed while all peripheral Other functions are selected with the peripheral pin
modules are disabled. Changing the select logic. See Section 12.0 “Peripheral Pin Select
threshold level during the time a module is (PPS) Module” for more information.
active may inadvertently generate a
Analog input functions, such as ADC and comparator
transition associated with an input pin,
inputs, are not shown in the peripheral pin select lists.
regardless of the actual voltage level on
These inputs are active when the I/O pin is set for
that pin.
Analog mode using the ANSELC register. Digital output
functions may continue to control the pin when it is in
Analog mode.

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11.6 Register Definitions: PORTC

REGISTER 11-17: PORTC: PORTC REGISTER

R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
(2) (2)
RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 RC<7:0>: PORTC General Purpose I/O Pin bits(1, 2)

1 = Port pin is > VIH
0 = Port pin is < VIL

Note 1: Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is return of actual
I/O pin values.
2: RC<7:6> are available on PIC16(L)F1708 only.

REGISTER 11-18: TRISC: PORTC TRI-STATE REGISTER

R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1
TRISC7(1) TRISC6(1) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 TRISC<7:0>: PORTC Tri-State Control bits(1)

1 = PORTC pin configured as an input (tri-stated)
0 = PORTC pin configured as an output

Note 1: TRISC<7:6> are available on PIC16(L)F1708 only.

REGISTER 11-19: LATC: PORTC DATA LATCH REGISTER

R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
LATC7(1) LATC6(1) LATC5 LATC4 LATC3 LATC2 LATC1 LATC0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 LATC<7:0>: PORTC Output Latch Value bits(1)

Note 1: LATC<7:6> are available on PIC16(L)F1708 only.

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REGISTER 11-20: ANSELC: PORTC ANALOG SELECT REGISTER

R/W-1/1 R/W-1/1 U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1
ANSC7(2) ANSC6(2) ANSC5(3) ANSC4(3) ANSC3 ANSC2 ANSC1 ANSC0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 ANSC<7:0>: Analog Select between Analog or Digital Function on pins RC<7:0>, respectively(1)
0 = Digital I/O. Pin is assigned to port or digital special function.
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.

Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
2: ANSC<7:6> are available on PIC16(L)F1708 only.
3: ANSC<5:4> are available on PIC16(L)F1704 only.

REGISTER 11-21: WPUC: WEAK PULL-UP PORTC REGISTER

R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1
(3) (3)
WPUC7 WPUC6 WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 WPUC<7:0>: Weak Pull-up Register bits(3)

1 = Pull-up enabled
0 = Pull-up disabled

Note 1: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is configured as an output.
3: WPUC<7:6> are available on PIC16(L)F1708 only.

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REGISTER 11-22: ODCONC: PORTC OPEN-DRAIN CONTROL REGISTER

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
ODC7(1) ODC6(1) ODC5 ODC4 ODC3 ODC2 ODC1 ODC0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 ODC<7:0>: PORTC Open-Drain Enable bits(1)

For RC<7:0> pins, respectively
1 = Port pin operates as open-drain drive (sink current only)
0 = Port pin operates as standard push-pull drive (source and sink current)

Note 1: ODC<7:6> are available on PIC16(L)F1708 only.

REGISTER 11-23: SLRCONC: PORTC SLEW RATE CONTROL REGISTER

R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1
SLRC7(1) SLRC6(1) SLRC5 SLRC4 SLRC3 SLRC2 SLRC1 SLRC0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 SLRC<7:0>: PORTC Slew Rate Enable bits(1)

For RC<7:0> pins, respectively
1 = Port pin slew rate is limited
0 = Port pin slews at maximum rate

Note 1: SLRC<7:6> are available on PIC16(L)F1708 only.

REGISTER 11-24: INLVLC: PORTC INPUT LEVEL CONTROL REGISTER

R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1
INLVLC7(1) INLVLC6(1) INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 INLVLC<7:0>: PORTC Input Level Select bits(1)

For RC<7:0> pins, respectively
1 = ST input used for PORT reads and interrupt-on-change
0 = TTL input used for PORT reads and interrupt-on-change

Note 1: INLVLC<7:6> are available on PIC16(L)F1708 only.

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TABLE 11-5: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page

ANSELC ANSC7(1) ANSC6(1) ANSC5(2) ANSC4(2) ANSC3 ANSC2 ANSC1 ANSC0 133
(1) (1)
INLVLC INLVLC7 INLVLC6 INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 134
(1) (1)
LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 132
(1) (1)
ODCONC ODC7 ODC6 ODC5 ODC4 ODC3 ODC2 ODC1 ODC0 134
PORTC RC7(1) RC6(1) RC5 RC4 RC3 RC2 RC1 RC0 132
SLRCONC SLRC7(1) SLRC6(1) SLRC5 SLRC4 SLRC3 SLRC2 SLRC1 SLRC0 134
(1) (1)
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 132
(1) (1)
WPUC WPUC7 WPUC6 WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 133
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by
PORTC.
Note 1: PIC16(L)F1708 only.
2: PIC16(L)F1704 only.

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12.0 PERIPHERAL PIN SELECT Although every peripheral has its own PPS input
selection register, the selections are identical for every
(PPS) MODULE
peripheral as shown in Register 12-1 for
The Peripheral Pin Select (PPS) module connects PIC16(L)F1704 devices and Register 12-2 for
peripheral inputs and outputs to the device I/O pins. PIC16(L)F1708 devices.
Only digital signals are included in the selections. All
Note: The notation “xxx” in the register name is
analog inputs and outputs remain fixed to their
a place holder for the peripheral identifier.
assigned pins. Input and output selections are
For example, CLC1PPS.
independent as shown in the simplified block diagram
Figure 12-1.
12.2 PPS Outputs
12.1 PPS Inputs Each I/O pin has a PPS register with which the pin
Each peripheral has a PPS register with which the output source is selected. With few exceptions, the port
inputs to the peripheral are selected. Inputs include the TRIS control associated with that pin retains control
device pins. over the pin output driver. Peripherals that control the
pin output driver as part of the peripheral operation will
Multiple peripherals can operate from the same source override the TRIS control as needed. These
simultaneously. Port reads always return the pin level peripherals include:
regardless of peripheral PPS selection. If a pin also has
associated analog functions, the ANSEL bit for that pin • EUSART (synchronous operation)
must be cleared to enable the digital input buffer. • MSSP (I2C)
• COG (auto-shutdown)
Although every pin has its own PPS peripheral
selection register, the selections are identical for every
pin as shown in Register 12-3.
Note: The notation “Rxy” is a place holder for the
pin identifier. For example, RA0PPS.

FIGURE 12-1: SIMPLIFIED PPS BLOCK DIAGRAM

PPS Outputs
RA0PPS
PPS Inputs

abcPPS RA0
RA0
Peripheral abc

RxyPPS

Rxy

Peripheral xyz
RC7 RC7PPS

xyzPPS RC7

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12.3 Bidirectional Pins 12.5 PPS Permanent Lock
PPS selections for peripherals with bidirectional The PPS can be permanently locked by setting the
signals on a single pin must be made so that the PPS PPS1WAY Configuration bit. When this bit is set, the
input and PPS output select the same pin. Peripherals PPSLOCKED bit can only be cleared and set one time
that have bidirectional signals include: after a device Reset. This allows for clearing the
• EUSART (synchronous operation) PPSLOCKED bit so that the input and output selections
can be made during initialization. When the
• MSSP (I2C)
PPSLOCKED bit is set after all selections have been
Note: The I2C default input pins are I2C and made, it will remain set and cannot be cleared until after
SMBus compatible and are the only pins the next device Reset event.
on the device with this compatibility.
12.6 Operation During Sleep
12.4 PPS Lock
PPS input and output selections are unaffected by
The PPS includes a mode in which all input and output Sleep.
selections can be locked to prevent inadvertent
changes. PPS selections are locked by setting the 12.7 Effects of a Reset
PPSLOCKED bit of the PPSLOCK register. Setting and
clearing this bit requires a special sequence as an extra A device Power-On-Reset (POR) clears all PPS input
precaution against inadvertent changes. Examples of and output selections to their default values. All other
setting and clearing the PPSLOCKED bit are shown in Resets leave the selections unchanged. Default input
Example 12-1. selections are shown in pin allocation Table 1 and
Table 2.
EXAMPLE 12-1: PPS LOCK/UNLOCK
SEQUENCE
; suspend interrupts
bcf INTCON,GIE
; BANKSEL PPSLOCK ; set bank
; required sequence, next 5 instructions
movlw 0x55
movwf PPSLOCK
movlw 0xAA
movwf PPSLOCK
; Set PPSLOCKED bit to disable writes or
; Clear PPSLOCKED bit to enable writes
bsf PPSLOCK,PPSLOCKED
; restore interrupts
bsf INTCON,GIE

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12.8 Register Definitions: PPS Input Selection
REGISTER 12-1: xxxPPS: PERIPHERAL xxx INPUT SELECTION (PIC16(L)F1704)
U-0 U-0 U-0 R/W-q/u R/W-q/u R/W-q/u R/W-q/u R/W-q/u
— — — xxxPPS<4:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = value depends on peripheral

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 xxxPPS<4:0>: Peripheral xxx Input Selection bits
11xxx = Reserved. Do not use.

1011x = Reserved. Do not use.

10101 = Peripheral input is RC5
10100 = Peripheral input is RC4
10011 = Peripheral input is RC3
10010 = Peripheral input is RC2
10001 = Peripheral input is RC1
10000 = Peripheral input is RC0

01xxx = Reserved. Do not use.

0011X = Reserved. Do not use.

00101 = Peripheral input is RA5
00100 = Peripheral input is RA4
00011 = Peripheral input is RA3
00010 = Peripheral input is RA2
00001 = Peripheral input is RA1
00000 = Peripheral input is RA0

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REGISTER 12-2: xxxPPS: PERIPHERAL xxx INPUT SELECTION (PIC16(L)F1708)

U-0 U-0 U-0 R/W-q/u R/W-q/u R/W-q/u R/W-q/u R/W-q/u
— — — xxxPPS<4:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = value depends on peripheral

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 xxxPPS<4:0>: Peripheral xxx Input Selection bits
11xxx = Reserved. Do not use.

10111 = Peripheral input is RC7

10110 = Peripheral input is RC6
10101 = Peripheral input is RC5
10100 = Peripheral input is RC4
10011 = Peripheral input is RC3
10010 = Peripheral input is RC2
10001 = Peripheral input is RC1
10000 = Peripheral input is RC0

01111 = Peripheral input is RB7

01110 = Peripheral input is RB6
01101 = Peripheral input is RB5
01100 = Peripheral input is RB4

010xx = Reserved. Do not use.

0011X = Reserved. Do not use.

00101 = Peripheral input is RA5
00100 = Peripheral input is RA4
00011 = Peripheral input is RA3
00010 = Peripheral input is RA2
00001 = Peripheral input is RA1
00000 = Peripheral input is RA0

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REGISTER 12-3: RxyPPS: PIN Rxy OUTPUT SOURCE SELECTION REGISTER

U-0 U-0 U-0 R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u
— — — RxyPPS<4:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 RxyPPS<4:0>: Pin Rxy Output Source Selection bits
11xxx = Reserved
10111 = Rxy source is C2OUT
10110 = Rxy source is C1OUT
10101 = Rxy source is DT(1)
10100 = Rxy source is TX/CK(1)
10011 = Reserved
10010 = Rxy source is SDO
10001 = Rxy source is SDA(1)
10000 = Rxy source is SCK/SCL(1)

01111 = Rxy source is PWM4OUT

01110 = Rxy source is PWM3OUT
01101 = Rxy source is CCP2
01100 = Rxy source is CCP1
01011 = Rxy source is COG1D(1)
01010 = Rxy source is COG1C(1)
01001 = Rxy source is COG1B(1)
01000 = Rxy source is COG1A(1)

00111 = Reserved
00110 = Rxy source is LC3OUT
00101 = Rxy source is LC2OUT
00100 = Rxy source is LC1OUT
00011 = Reserved
00010 = Reserved
00001 = Reserved
00000 = Rxy source is LATxy
Note 1: TRIS control is overridden by the peripheral as required.

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REGISTER 12-4: PPSLOCK: PPS LOCK REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0
— — — — — — — PPSLOCKED
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-1 Unimplemented: Read as ‘0’

bit 0 PPSLOCKED: PPS Locked bit
1= PPS is locked. PPS selections can not be changed.
0= PPS is not locked. PPS selections can be changed.

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TABLE 12-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE PPS MODULE

Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on page
PPSLOCK — — — — — — — PPSLOCKED 141
INTPPS — — — INTPPS<4:0> 139
T0CKIPPS — — — T0CKIPPS<4:0> 139
T1CKIPPS — — — T1CKIPPS<4:0> 139
T1GPPS — — — T1GPPS<4:0> 139
CCP1PPS — — — CCP1PPS<4:0> 139
CCP2PPS — — — CCP2PPS<4:0> 139
COGPPS — — — COGPPS<4:0> 139
SSPCLKPPS — — — SSPCLKPPS<4:0> 139
SSPDATPPS — — — SSPDATPPS<4:0> 139
SSPSSPPS — — — SSPSSPPS<4:0> 139
RXPPS — — — RXPPS<4:0> 139
CKPPS — — — CKPPS<4:0> 139
CLCIN0PPS — — — CLCIN0PPS<4:0> 139
CLCIN1PPS — — — CLCIN1PPS<4:0> 139
CLCIN2PPS — — — CLCIN2PPS<4:0> 139
CLCIN3PPS — — — CLCIN3PPS<4:0> 139
RA0PPS — — — RA0PPS<4:0> 140
RA1PPS — — — RA1PPS<4:0> 140
RA2PPS — — — RA2PPS<4:0> 140
RA4PPS — — — RA4PPS<4:0> 140
RA5PPS — — — RA5PPS<4:0> 140
RB4PPS(1) — — — RB4PPS<4:0> 140
RB5PPS(1) — — — RB5PPS<4:0> 140
(1)
RB6PPS — — — RB6PPS<4:0> 140
RB7PPS(1) — — — RB7PPS<4:0> 140
RC0PPS — — — RC0PPS<4:0> 140
RC1PPS — — — RC1PPS<4:0> 140
RC2PPS — — — RC2PPS<4:0> 140
RC3PPS — — — RC3PPS<4:0> 140
RC4PPS — — — RC4PPS<4:0> 140
RC5PPS — — — RC5PPS<4:0> 140
RC6PPS(1) — — — RC6PPS<4:0> 140
RC7PPS(1) — — — RC7PPS<4:0> 140
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the PPS module.
Note 1: PIC16(L)F1708 only.

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13.0 INTERRUPT-ON-CHANGE 13.3 Interrupt Flags
All pins on all ports can be configured to operate as The bits located in the IOCxF registers are status flags
Interrupt-On-Change (IOC) pins. An interrupt can be that correspond to the interrupt-on-change pins of each
generated by detecting a signal that has either a rising port. If an expected edge is detected on an appropriately
edge or a falling edge. Any individual pin, or combination enabled pin, then the status flag for that pin will be set,
of pins, can be configured to generate an interrupt. The and an interrupt will be generated if the IOCIE bit is set.
interrupt-on-change module has the following features: The IOCIF bit of the INTCON register reflects the status
of all IOCxF bits.
• Interrupt-on-Change enable (Master Switch)
• Individual pin configuration
13.4 Clearing Interrupt Flags
• Rising and falling edge detection
• Individual pin interrupt flags The individual status flags, (IOCxF register bits), can be
cleared by resetting them to zero. If another edge is
Figure 13-1 is a block diagram of the IOC module.
detected during this clearing operation, the associated
status flag will be set at the end of the sequence,
13.1 Enabling the Module regardless of the value actually being written.
To allow individual pins to generate an interrupt, the In order to ensure that no detected edge is lost while
IOCIE bit of the INTCON register must be set. If the clearing flags, only AND operations masking out known
IOCIE bit is disabled, the edge detection on the pin will changed bits should be performed. The following
still occur, but an interrupt will not be generated. sequence is an example of what should be performed.

13.2 Individual Pin Configuration EXAMPLE 13-1: CLEARING INTERRUPT

FLAGS
For each pin, a rising edge detector and a falling edge
(PORTA EXAMPLE)
detector are present. To enable a pin to detect a rising
edge, the associated bit of the IOCxP register is set. To MOVLW 0xff
enable a pin to detect a falling edge, the associated bit XORWF IOCAF, W
of the IOCxN register is set. ANDWF IOCAF, F

A pin can be configured to detect rising and falling

edges simultaneously by setting the associated bits in 13.5 Operation in Sleep
both of the IOCxP and IOCxN registers.
The interrupt-on-change interrupt sequence will wake
the device from Sleep mode, if the IOCIE bit is set.
If an edge is detected while in Sleep mode, the affected
IOCxF register will be updated prior to the first instruction
executed out of Sleep.

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FIGURE 13-1: INTERRUPT-ON-CHANGE BLOCK DIAGRAM (PORTA EXAMPLE)
Rev. 10-000 037A
6/2/201 4

IOCANx D Q

R Q4Q1
edge
detect

RAx

to data bus
data bus = S
IOCAFx
IOCAPx D Q
0 or 1
D Q

R
write IOCAFx
IOCIE
Q2
IOC interrupt
to CPU core
from all other
IOCnFx individual
pin detectors

FOSC

Q1 Q1 Q1

Q2 Q2 Q2

Q3 Q3 Q3

Q4 Q4 Q4

Q4Q1 Q4Q1 Q4Q1 Q4Q1

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 PIC16(L)F1704/8
13.6 Register Definitions: Interrupt-on-Change Control

REGISTER 13-1: IOCAP: INTERRUPT-ON-CHANGE PORTA POSITIVE EDGE REGISTER

U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 IOCAP<5:0>: Interrupt-on-Change PORTA Positive Edge Enable bits
1 = Interrupt-on-Change enabled on the pin for a positive going edge. IOCAFx bit and IOCIF flag will be set
upon detecting an edge.
0 = Interrupt-on-Change disabled for the associated pin.

REGISTER 13-2: IOCAN: INTERRUPT-ON-CHANGE PORTA NEGATIVE EDGE REGISTER

U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 IOCAN<5:0>: Interrupt-on-Change PORTA Negative Edge Enable bits
1 = Interrupt-on-Change enabled on the pin for a negative going edge. IOCAFx bit and IOCIF flag will be set
upon detecting an edge.
0 = Interrupt-on-Change disabled for the associated pin.

REGISTER 13-3: IOCAF: INTERRUPT-ON-CHANGE PORTA FLAG REGISTER

U-0 U-0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0
— — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardware

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 IOCAF<5:0>: Interrupt-on-Change PORTA Flag bits
1 = An enabled change was detected on the associated pin.
Set when IOCAPx = 1 and a rising edge was detected on RAx, or when IOCANx = 1 and a falling edge was
detected on RAx.
0 = No change was detected, or the user cleared the detected change.

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REGISTER 13-4: IOCBP: INTERRUPT-ON-CHANGE PORTB POSITIVE EDGE REGISTER(1)

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0
IOCBP7 IOCBP6 IOCBP5 IOCBP4 — — — —
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-4 IOCBP<7:4>: Interrupt-on-Change PORTB Positive Edge Enable bits

1 = Interrupt-on-Change enabled on the pin for a positive going edge. IOCBFx bit and IOCIF flag will be set upon
detecting an edge.
0 = Interrupt-on-Change disabled for the associated pin.
bit 3-0 Unimplemented: Read as ‘0’

Note 1: PIC16(L)F1708 only.

REGISTER 13-5: IOCBN: INTERRUPT-ON-CHANGE PORTB NEGATIVE EDGE REGISTER(1)

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0
IOCBN7 IOCBN6 IOCBN5 IOCBN4 — — — —
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-4 IOCBN<7:4>: Interrupt-on-Change PORTB Negative Edge Enable bits

1 = Interrupt-on-Change enabled on the pin for a negative going edge. IOCBFx bit and IOCIF flag will be set upon
detecting an edge.
0 = Interrupt-on-Change disabled for the associated pin.
bit 3-0 Unimplemented: Read as ‘0’

Note 1: PIC16(L)F1708 only.

REGISTER 13-6: IOCBF: INTERRUPT-ON-CHANGE PORTB FLAG REGISTER(1)

R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 U-0 U-0 U-0 U-0
IOCBF7 IOCBF6 IOCBF5 IOCBF4 — — — —
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardware

bit 7-4 IOCBF<7:4>: Interrupt-on-Change PORTB Flag bits

1 = An enabled change was detected on the associated pin.
Set when IOCBPx = 1 and a rising edge was detected on RBx, or when IOCBNx = 1 and a falling edge was
detected on RBx.
0 = No change was detected, or the user cleared the detected change.
bit 3-0 Unimplemented: Read as ‘0’

Note 1: PIC16(L)F1708 only.

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REGISTER 13-7: IOCCP: INTERRUPT-ON-CHANGE PORTC POSITIVE EDGE REGISTER

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
IOCCP7(1) IOCCP6(1) IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 IOCCP<7:0>: Interrupt-on-Change PORTC Positive Edge Enable bits

1 = Interrupt-on-Change enabled on the pin for a positive going edge. IOCCFx bit and IOCIF flag will be set
upon detecting an edge.
0 = Interrupt-on-Change disabled for the associated pin.
Note 1: PIC16(L)F1708 only.

REGISTER 13-8: IOCCN: INTERRUPT-ON-CHANGE PORTC NEGATIVE EDGE REGISTER

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
IOCCN7(1) IOCCN6(1) IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 IOCCN<7:0>: Interrupt-on-Change PORTC Negative Edge Enable bits

1 = Interrupt-on-Change enabled on the pin for a negative going edge. IOCCFx bit and IOCIF flag will be set upon
detecting an edge.
0 = Interrupt-on-Change disabled for the associated pin.

Note 1: PIC16(L)F1708 only.

REGISTER 13-9: IOCCF: INTERRUPT-ON-CHANGE PORTC FLAG REGISTER

R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0
(1) (1)
IOCCF7 IOCCF6 IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardware

bit 7-0 IOCCF<7:0>: Interrupt-on-Change PORTC Flag bits

1 = An enabled change was detected on the associated pin.
Set when IOCCPx = 1 and a rising edge was detected on RCx, or when IOCCNx = 1 and a falling edge was
detected on RCx.
0 = No change was detected, or the user cleared the detected change.

Note 1: PIC16(L)F1708 only.

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TABLE 13-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 122
ANSELB (1) — — ANSB5 ANSB4 — — — — 128
(1) (1) (2) (2)
ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 ANSC1 ANSC0 133
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 85
IOCAF — — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 145
IOCAN — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 145
IOCAP — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 145
IOCBF(1) IOCBF7 IOCBF6 IOCBF5 IOCBF4 — — — — 146
IOCBN(1) IOCBN7 IOCBN6 IOCBN5 IOCBN4 — — — — 146
(1)
IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 — — — — 146
(1)
IOCCF IOCCF7 IOCCF6(1) IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0 147
IOCCN IOCCN7(1) IOCCN6(1) IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0 147
IOCCP IOCCP7(1) IOCCP6(1) IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0 147
TRISA — — TRISA5 TRISA4 —(3) TRISA2 TRISA1 TRISA0 121
(1)
TRISB TRISB7 TRISB6 TRISB5 TRISB4 — — — — 127
(1)
TRISC TRISC7 TRISC6(1) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 132
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by interrupt-on-change.
Note 1: PIC16(L)F1708 only.
2: PIC16(L)F1704 only.
3: Unimplemented, read as ‘1’.

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14.0 FIXED VOLTAGE REFERENCE 14.1 Independent Gain Amplifiers
(FVR) The output of the FVR supplied to the ADC,
The Fixed Voltage Reference, or FVR, is a stable Comparators, and DAC is routed through two
voltage reference, independent of VDD, with 1.024V, independent programmable gain amplifiers. Each
2.048V or 4.096V selectable output levels. The output amplifier can be programmed for a gain of 1x, 2x or 4x,
of the FVR can be configured to supply a reference to produce the three possible voltage levels.
voltage to the following: The ADFVR<1:0> bits of the FVRCON register are
• ADC input channel used to enable and configure the gain amplifier settings
for the reference supplied to the ADC module.
• ADC positive reference
Reference Section 20.0 “Analog-to-Digital Converter
• Comparator positive input (ADC) Module” for additional information.
• Digital-to-Analog Converter (DAC)
The CDAFVR<1:0> bits of the FVRCON register are
The FVR can be enabled by setting the FVREN bit of used to enable and configure the gain amplifier settings
the FVRCON register. for the reference supplied to the DAC and comparator
module. Reference Section 22.0 “8-Bit Digital-to-Ana-
log Converter (DAC1) Module” and Section 16.0
“Comparator Module” for additional information.

14.2 FVR Stabilization Period

When the Fixed Voltage Reference module is enabled, it
requires time for the reference and amplifier circuits to
stabilize. Once the circuits stabilize and are ready for use,
the FVRRDY bit of the FVRCON register will be set. See
Figure 33-74: Wake from Sleep, VREGPM = 0.

FIGURE 14-1: VOLTAGE REFERENCE BLOCK DIAGRAM

ADFVR<1:0>
2
X1
X2 FVR BUFFER1
X4 (To ADC Module)

CDAFVR<1:0> 2
X1
X2 FVR BUFFER2
X4 (To Comparators, DAC, Op Amp)

HFINTOSC Enable

HFINTOSC

To BOR, LDO

+
FVREN
_ FVRRDY

Any peripheral requiring the

Fixed Reference
(See Table 14-1)

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TABLE 14-1: PERIPHERALS REQUIRING THE FIXED VOLTAGE REFERENCE (FVR)

Peripheral Conditions Description
HFINTOSC FOSC<2:0> = 100 and INTOSC is active and device is not in Sleep
IRCF<3:0>  000x
BOREN<1:0> = 11 BOR always enabled
BOR BOREN<1:0> = 10 and BORFS = 1 BOR disabled in Sleep mode, BOR Fast Start enabled
BOREN<1:0> = 01 and BORFS = 1 BOR under software control, BOR Fast Start enabled
LDO All PIC16F1704/8 devices, when The device runs off of the ULP regulator when in Sleep mode
VREGPM = 1 and not in Sleep

14.3 FVR Buffer Stabilization Period

When either FVR Buffer1 or FVR Buffer2 is enabled,
then the buffer amplifier circuits require 30 µs to
stabilize. This stabilization time is still required when
the FVR buffer is in operation.

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14.4 Register Definitions: FVR Control

REGISTER 14-1: FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER

R/W-0/0 R-q/q R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
FVREN FVRRDY(1) TSEN (3)
TSRNG (3)
CDAFVR<1:0> ADFVR<1:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7 FVREN: Fixed Voltage Reference Enable bit

1 = Fixed Voltage Reference is enabled
0 = Fixed Voltage Reference is disabled
bit 6 FVRRDY: Fixed Voltage Reference Ready Flag bit(1)
1 = Fixed Voltage Reference output is ready for use
0 = Fixed Voltage Reference output is not ready or not enabled
bit 5 TSEN: Temperature Indicator Enable bit(3)
1 = Temperature Indicator is enabled
0 = Temperature Indicator is disabled
bit 4 TSRNG: Temperature Indicator Range Selection bit(3)
1 = VOUT = VDD - 4VT (High Range)
0 = VOUT = VDD - 2VT (Low Range)
bit 3-2 CDAFVR<1:0>: Comparator FVR Buffer Gain Selection bits
11 = Comparator FVR Buffer Gain is 4x, with output VCDAFVR = 4x VFVR(2)
10 = Comparator FVR Buffer Gain is 2x, with output VCDAFVR = 2x VFVR(2)
01 = Comparator FVR Buffer Gain is 1x, with output VCDAFVR = 1x VFVR
00 = Comparator FVR Buffer is off
bit 1-0 ADFVR<1:0>: ADC FVR Buffer Gain Selection bit
11 = ADC FVR Buffer Gain is 4x, with output VADFVR = 4x VFVR(2)
10 = ADC FVR Buffer Gain is 2x, with output VADFVR = 2x VFVR(2)
01 = ADC FVR Buffer Gain is 1x, with output VADFVR = 1x VFVR
00 = ADC FVR Buffer is off

Note 1: FVRRDY is always ‘1’ on PIC16F1704/8 only.

2: Fixed Voltage Reference output cannot exceed VDD.
3: See Section 15.0 “Temperature Indicator Module” for additional information.

TABLE 14-2: SUMMARY OF REGISTERS ASSOCIATED WITH FIXED VOLTAGE REFERENCE

Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on page
FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 151
Legend: Shaded cells are not used with the Fixed Voltage Reference.

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15.0 TEMPERATURE INDICATOR FIGURE 15-1: TEMPERATURE CIRCUIT
MODULE DIAGRAM

This family of devices is equipped with a temperature

circuit designed to measure the operating temperature VDD
of the silicon die. The circuit’s range of operating
TSEN
temperature falls between -40°C and +85°C. The
output is a voltage that is proportional to the device
temperature. The output of the temperature indicator is
internally connected to the device ADC. TSRNG

The circuit may be used as a temperature threshold

detector or a more accurate temperature indicator,
depending on the level of calibration performed. A one-
point calibration allows the circuit to indicate a
VOUT
temperature closely surrounding that point. A two-point To ADC
Temp. Indicator
calibration allows the circuit to sense the entire range
of temperature more accurately. Reference Application
Note AN1333, “Use and Calibration of the Internal
Temperature Indicator” (DS01333) for more details
regarding the calibration process.

15.1 Circuit Operation 15.2 Minimum Operating VDD

Figure 15-1 shows a simplified block diagram of the When the temperature circuit is operated in low range,
temperature circuit. The proportional voltage output is the device may be operated at any operating voltage
achieved by measuring the forward voltage drop across that is within specifications.
multiple silicon junctions.
When the temperature circuit is operated in high range,
Equation 15-1 describes the output characteristics of the device operating voltage, VDD, must be high
the temperature indicator. enough to ensure that the temperature circuit is
correctly biased.
EQUATION 15-1: VOUT RANGES Table 15-1 shows the recommended minimum VDD vs.
range setting.
High Range: VOUT = VDD - 4VT
TABLE 15-1: RECOMMENDED VDD VS.
Low Range: VOUT = VDD - 2VT RANGE
Min. VDD, TSRNG = 1 Min. VDD, TSRNG = 0
The temperature sense circuit is integrated with the 3.6V 1.8V
Fixed Voltage Reference (FVR) module. See
Section 14.0 “Fixed Voltage Reference (FVR)” for 15.3 Temperature Output
more information.
The circuit is enabled by setting the TSEN bit of the The output of the circuit is measured using the internal
FVRCON register. When disabled, the circuit draws no Analog-to-Digital Converter. A channel is reserved for
current. the temperature circuit output. Refer to Section 20.0
“Analog-to-Digital Converter (ADC) Module” for
The circuit operates in either high or low range. The high detailed information.
range, selected by setting the TSRNG bit of the
FVRCON register, provides a wider output voltage. This
provides more resolution over the temperature range,
but may be less consistent from part to part. This range
requires a higher bias voltage to operate and thus, a
higher VDD is needed.
The low range is selected by clearing the TSRNG bit of
the FVRCON register. The low range generates a lower
voltage drop and thus, a lower bias voltage is needed to
operate the circuit. The low range is provided for low
voltage operation.

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15.4 ADC Acquisition Time
To ensure accurate temperature measurements, the
user must wait at least 200 s after the ADC input
multiplexer is connected to the temperature indicator
output before the conversion is performed. In addition,
the user must wait 200 s between sequential
conversions of the temperature indicator output.

TABLE 15-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE TEMPERATURE INDICATOR

Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on page
FVRCON FVREN FVRRDY TSEN TSRNG CDFVR<1:0> ADFVR<1:0> 151
Legend: Shaded cells are unused by the temperature indicator module.

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16.0 COMPARATOR MODULE FIGURE 16-1: SINGLE COMPARATOR
Comparators are used to interface analog circuits to a
digital circuit by comparing two analog voltages and VIN+ +
providing a digital indication of their relative magnitudes. Output
Comparators are very useful mixed signal building VIN- –
blocks because they provide analog functionality
independent of program execution. The analog
comparator module includes the following features:
• Independent comparator control VIN-
• Programmable input selection VIN+
• Comparator output is available internally/externally
• Programmable output polarity
• Interrupt-on-change
• Wake-up from Sleep Output
• Programmable Speed/Power optimization
• PWM shutdown
Note: The black areas of the output of the
• Programmable and Fixed Voltage Reference
comparator represents the uncertainty
16.1 Comparator Overview due to input offsets and response time.

A single comparator is shown in Figure 16-1 along with

the relationship between the analog input levels and
the digital output. When the analog voltage at VIN+ is
less than the analog voltage at VIN-, the output of the
comparator is a digital low level. When the analog
voltage at VIN+ is greater than the analog voltage at
VIN-, the output of the comparator is a digital high level.
The comparators available for this device are located in
Table 16-1.

TABLE 16-1: AVAILABLE COMPARATORS

Device C1 C2
PIC16(L)F1704/8 ● ●

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FIGURE 16-2: COMPARATOR MODULE SIMPLIFIED BLOCK DIAGRAM
CxNCH<2:0>
CxON(1)
3 Interrupt CxINTP

det
CXIN0- 0 Set CxIF
CXIN1- 1
2 MUX Interrupt CxINTN
CXIN2-
(2)
det
CXIN3- 3
CXPOL
Reserved 4 CxVN
-
0 to CMXCON0 (CXOUT)
Reserved 5 D Q
Cx and CM2CON1 (MCXOUT)
FVR Buffer2 + ZLF 1
6
CxVP
Q1 EN
7
CxHYS
AGND CxZLF
CxSP
async_CxOUT

CXSYNC
TRIS bit
CXOUT
0

D Q 1
CXIN+ 0 From Timer1
tmr1_clk sync_CxOUT
Reserved 1 To Timer1
MUX
(2)
Reserved 2

Reserved 3

Reserved 4

DAC_Output 5

FVR Buffer2 6

AGND CxON

CXPCH<2:0>
3

Note 1: When CxON = 0, the comparator will produce a ‘0’ at the output.
2: When CxON = 0, all multiplexer inputs are disconnected.

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16.2 Comparator Control 16.2.3 COMPARATOR OUTPUT POLARITY
Each comparator has two control registers: CMxCON0 Inverting the output of the comparator is functionally
and CMxCON1. equivalent to swapping the comparator inputs. The
polarity of the comparator output can be inverted by
The CMxCON0 register (see Register 16-1) contains setting the CxPOL bit of the CMxCON0 register.
Control and Status bits for the following: Clearing the CxPOL bit results in a non-inverted output.
• Enable Table 16-2 shows the output state versus input
• Output conditions, including polarity control.
• Output polarity TABLE 16-2: COMPARATOR OUTPUT
• Zero latency filter STATE VS. INPUT
• Speed/Power selection CONDITIONS
• Hysteresis enable Input Condition CxPOL CxOUT
• Output synchronization
CxVN > CxVP 0 0
The CMxCON1 register (see Register 16-2) contains
CxVN < CxVP 0 1
Control bits for the following:
CxVN > CxVP 1 1
• Interrupt enable
CxVN < CxVP 1 0
• Interrupt edge polarity
• Positive input channel selection 16.2.4 COMPARATOR SPEED/POWER
• Negative input channel selection SELECTION
16.2.1 COMPARATOR ENABLE The trade-off between speed or power can be
optimized during program execution with the CxSP
Setting the CxON bit of the CMxCON0 register enables control bit. The default state for this bit is ‘1’, which
the comparator for operation. Clearing the CxON bit selects the Normal-Speed mode. Device power
disables the comparator resulting in minimum current consumption can be optimized at the cost of slower
consumption. comparator propagation delay by clearing the CxSP bit
to ‘0’.
16.2.2 COMPARATOR OUTPUT
SELECTION
The output of the comparator can be monitored by
reading either the CxOUT bit of the CMxCON0 register
or the MCxOUT bit of the CMOUT register. In order to
make the output available for an external connection,
the following conditions must be true:
• Desired pin PPS control
• Corresponding TRIS bit must be cleared
• CxON bit of the CMxCON0 register must be set

Note 1: The internal output of the comparator is

latched with each instruction cycle.
Unless otherwise specified, external
outputs are not latched.

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16.3 Comparator Hysteresis The associated interrupt flag bit, CxIF bit of the PIR2
register, must be cleared in software. If another edge is
A selectable amount of separation voltage can be detected while this flag is being cleared, the flag will still
added to the input pins of each comparator to provide a be set at the end of the sequence.
hysteresis function to the overall operation. Hysteresis
is enabled by setting the CxHYS bit of the CMxCON0 Note: Although a comparator is disabled, an
register. interrupt can be generated by changing
the output polarity with the CxPOL bit of
See Comparator Specifications in Table 32-18:
the CMxCON0 register, or by switching
Comparator Specifications for more information.
the comparator on or off with the CxON bit
of the CMxCON0 register.
16.4 Timer1 Gate Operation
The output resulting from a comparator operation can 16.6 Comparator Positive Input
be used as a source for gate control of Timer1. See Selection
Section 25.6 “Timer1 Gate” for more information.
This feature is useful for timing the duration or interval Configuring the CxPCH<2:0> bits of the CMxCON1
of an analog event. register directs an internal voltage reference or an
analog pin to the non-inverting input of the comparator:
It is recommended that the comparator output be
synchronized to Timer1. This ensures that Timer1 does • CxIN+ analog pin
not increment while a change in the comparator is • DAC output
occurring. • FVR (Fixed Voltage Reference)
• VSS (Ground)
16.4.1 COMPARATOR OUTPUT
SYNCHRONIZATION See Section 14.0 “Fixed Voltage Reference (FVR)”
for more information on the Fixed Voltage Reference
The output from a comparator can be synchronized module.
with Timer1 by setting the CxSYNC bit of the
CMxCON0 register. See Section 22.0 “8-Bit Digital-to-Analog Converter
(DAC1) Module” for more information on the DAC
Once enabled, the comparator output is latched on the input signal.
falling edge of the Timer1 source clock. If a prescaler is
used with Timer1, the comparator output is latched after Any time the comparator is disabled (CxON = 0), all
the prescaling function. To prevent a race condition, the comparator inputs are disabled.
comparator output is latched on the falling edge of the
Timer1 clock source and Timer1 increments on the 16.7 Comparator Negative Input
rising edge of its clock source. See the Comparator Selection
Block Diagram (Figure 16-2) and the Timer1 Block
Diagram (Figure 25-1) for more information. The CxNCH<2:0> bits of the CMxCON0 register direct
an analog input pin and internal reference voltage or
analog ground to the inverting input of the comparator:
16.5 Comparator Interrupt
• CxIN- pin
An interrupt can be generated upon a change in the
• FVR (Fixed Voltage Reference)
output value of the comparator for each comparator, a
rising edge detector and a falling edge detector are • Analog Ground
present. Some inverting input selections share a pin with the
When either edge detector is triggered and its operational amplifier output function. Enabling both
associated enable bit is set (CxINTP and/or CxINTN functions at the same time will direct the operational
bits of the CMxCON1 register), the Corresponding amplifier output to the comparator inverting input.
Interrupt Flag bit (CxIF bit of the PIR2 register) will be
set.
To enable the interrupt, you must set the following bits: Note: To use CxINy+ and CxINy- pins as analog
input, the appropriate bits must be set in
• CxON, CxPOL and CxSP bits of the CMxCON0 the ANSEL register and the correspond-
register ing TRIS bits must also be set to disable
• CxIE bit of the PIE2 register the output drivers.
• CxINTP bit of the CMxCON1 register (for a rising
edge detection)
• CxINTN bit of the CMxCON1 register (for a falling
edge detection)
• PEIE and GIE bits of the INTCON register

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16.8 Comparator Response Time the hardware and software relying on this signal.
Therefore, a digital filter has been added to the
The comparator output is indeterminate for a period of comparator output to suppress the comparator output
time after the change of an input source or the selection oscillation. Once the comparator output changes, the
of a new reference voltage. This period is referred to as output is prevented from reversing the change for a
the response time. The response time of the comparator nominal time of 20 ns. This allows the comparator
differs from the settling time of the voltage reference. output to stabilize without affecting other dependent
Therefore, both of these times must be considered when devices. Refer to Figure 16-3.
determining the total response time to a comparator
input change. See the Comparator and Voltage
Reference Specifications in Table 32-18: Comparator
Specifications for more details.

16.9 Zero Latency Filter

In high-speed operation, and under proper circuit
conditions, it is possible for the comparator output to
oscillate. This oscillation can have adverse effects on

FIGURE 16-3: COMPARATOR ZERO LATENCY FILTER OPERATION

CxOUT From Comparator

CxOUT From ZLF

TZLF

Output waiting for TZLF to expire before an output change is allowed.

TZLF has expired so output change of ZLF is immediate based on

comparator output change.

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16.10 Analog Input Connection
Considerations
A simplified circuit for an analog input is shown in
Figure 16-4. Since the analog input pins share their
connection with a digital input, they have reverse
biased ESD protection diodes to VDD and VSS. The
analog input, therefore, must be between VSS and VDD.
If the input voltage deviates from this range by more
than 0.6V in either direction, one of the diodes is
forward biased and a latch-up may occur.
A maximum source impedance of 10 k is recommended
for the analog sources. Also, any external component
connected to an analog input pin, such as a capacitor or
a Zener diode, should have very little leakage current to
minimize inaccuracies introduced.
Note 1: When reading a PORT register, all pins
configured as analog inputs will read as a
‘0’. Pins configured as digital inputs will
convert as an analog input, according to
the input specification.
2: Analog levels on any pin defined as a
digital input, may cause the input buffer to
consume more current than is specified.

FIGURE 16-4: ANALOG INPUT MODEL

VDD
Analog
Input
pin VT  0.6V RIC
Rs < 10K
To Comparator

CPIN ILEAKAGE(1)
VA VT  0.6V
5 pF

Vss

Legend: CPIN = Input Capacitance

ILEAKAGE = Leakage Current at the pin due to various junctions
RIC = Interconnect Resistance
RS = Source Impedance
VA = Analog Voltage
VT = Threshold Voltage

Note 1: See I/O Ports in Table 32-4: I/O Ports.

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16.11 Register Definitions: Comparator Control

REGISTER 16-1: CMxCON0: COMPARATOR Cx CONTROL REGISTER 0

R/W-0/0 R-0/0 U-0 R/W-0/0 R/W-0/0 R/W-1/1 R/W-0/0 R/W-0/0
CxON CxOUT — CxPOL CxZLF CxSP CxHYS CxSYNC
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 CxON: Comparator Enable bit

1 = Comparator is enabled
0 = Comparator is disabled and consumes no active power
bit 6 CxOUT: Comparator Output bit
If CxPOL = 1 (inverted polarity):
1 = CxVP < CxVN
0 = CxVP > CxVN
If CxPOL = 0 (non-inverted polarity):
1 = CxVP > CxVN
0 = CxVP < CxVN
bit 5 Unimplemented: Read as ‘0’
bit 4 CxPOL: Comparator Output Polarity Select bit
1 = Comparator output is inverted
0 = Comparator output is not inverted
bit 3 CxZLF: Comparator Zero Latency Filter Enable bit
1 = Comparator output is filtered
0 = Comparator output is unfiltered
bit 2 CxSP: Comparator Speed/Power Select bit
1 = Comparator operates in normal power, higher speed mode
0 = Comparator operates in low-power, low-speed mode
bit 1 CxHYS: Comparator Hysteresis Enable bit
1 = Comparator hysteresis enabled
0 = Comparator hysteresis disabled
bit 0 CxSYNC: Comparator Output Synchronous Mode bit
1 = Comparator output to Timer1 and I/O pin is synchronous to changes on Timer1 clock source.
Output updated on the falling edge of Timer1 clock source.
0 = Comparator output to Timer1 and I/O pin is asynchronous.

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REGISTER 16-2: CMxCON1: COMPARATOR Cx CONTROL REGISTER 1

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
CxINTP CxINTN CxPCH<2:0> CxNCH<2:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 CxINTP: Comparator Interrupt on Positive Going Edge Enable bits

1 = The CxIF interrupt flag will be set upon a positive going edge of the CxOUT bit
0 = No interrupt flag will be set on a positive going edge of the CxOUT bit
bit 6 CxINTN: Comparator Interrupt on Negative Going Edge Enable bits
1 = The CxIF interrupt flag will be set upon a negative going edge of the CxOUT bit
0 = No interrupt flag will be set on a negative going edge of the CxOUT bit
bit 5-3 CxPCH<2:0>: Comparator Positive Input Channel Select bits
111 = CxVP connects to AGND
110 = CxVP connects to FVR Buffer 2
101 = CxVP connects to VDAC
100 = CxVP unconnected, input floating
011 = CxVP unconnected, input floating
010 = CxVP unconnected, input floating
001 = CxVN unconnected, input floating
000 = CxVP connects to CxIN+ pin
bit 2-0 CxNCH<2:0>: Comparator Negative Input Channel Select bits
111 = CxVN connects to AGND
110 = CxVN connects to FVR Buffer 2
101 = CxVN unconnected, input floating
100 = CxVN unconnected, input floating
011 = CxVN connects to CxIN3- pin
010 = CxVN connects to CxIN2- pin
001 = CxVN connects to CxIN1- pin
000 = CxVN connects to CxIN0- pin

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REGISTER 16-3: CMOUT: COMPARATOR OUTPUT REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 R-0/0 R-0/0
— — — — — — MC2OUT MC1OUT
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-2 Unimplemented: Read as ‘0’

bit 1 MC2OUT: Mirror Copy of C2OUT bit
bit 0 MC1OUT: Mirror Copy of C1OUT bit

TABLE 16-3: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARATOR MODULE

Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 122
ANSELB(1) — — ANSB5 ANSB4 — — — — 128
ANSELC ANSC7(1) ANSC6(1) ANSC5(2) ANSC4(2) ANSC3 ANSC2 ANSC1 ANSC0 133
CM1CON0 C1ON C1OUT — C1POL C1ZLF C1SP C1HYS C1SYNC 160
CM2CON0 C2ON C2OUT — C2POL C2ZLF C2SP C2HYS C2SYNC 160
CM1CON1 C1NTP C1INTN C1PCH<2:0> C1NCH<2:0> 161
CM2CON1 C2NTP C2INTN C2PCH<2:0> C2NCH<2:0> 161
CMOUT — — — — — — MC2OUT MC1OUT 162
FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 151
DAC1CON0 DAC1EN — DAC1OE1 DAC1OE2 DAC1PSS<1:0> — DAC1NSS 237
DAC1CON1 DAC1R<7:0> 237
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 85
PIE2 OSFIE C2IE C1IE — BCL1IE TMR6IE TMR4IE CCP2IE 87
PIR2 OSFIF C2IF C1IF — BCL1IF TMR6IF TMR4IF CCP2IF 90
TRISA — — TRISA5 TRISA4 —(3) TRISA2 TRISA1 TRISA0 121
TRISB(1) TRISB7 TRISB6 TRISB5 TRISB4 — — — — 127
TRISC TRISC7(1) TRISC6(1) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 132
Legend: — = unimplemented location, read as ‘0’. Shaded cells are unused by the comparator module.
Note 1: PIC16(L)F1708 only.
2: PIC16(L)F1704 only.
3: Unimplemented, read as ‘1’.

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17.0 PULSE WIDTH MODULATION Figure 17-1 shows a simplified block diagram of PWM
operation.
(PWM)
Figure 17-2 shows a typical waveform of the PWM
The PWM module generates a Pulse-Width Modulated signal.
signal determined by the duty cycle, period, and
resolution that are configured by the following registers:
• PR2
• T2CON
• PWMxDCH
• PWMxDCL
• PWMxCON

FIGURE 17-1: SIMPLIFIED PWM BLOCK DIAGRAM

Duty Cycle registers PWMxDCL<7:6>

PWMxDCH

Latched PWMxOUT
(Not visible to user)
to other peripherals: CLC and CWG

Comparator R Q 0 PWMx

S Q 1

TMR2 Module

TMR2 (1) Output Polarity (PWMxPOL)

Comparator

Clear Timer,
PR2 PWMx pin and
latch Duty Cycle

Note 1: 8-bit timer is concatenated with the two Least Significant bits of 1/FOSC adjusted by the Timer2 prescaler to
create a 10-bit time base.

For a step-by-step procedure on how to set up this

module for PWM operation, refer to Section 17.1.9
“Setup for PWM Operation using PWMx Pins”.

FIGURE 17-2: PWM OUTPUT

Period

Pulse Width
TMR2 = PR2

TMR2 =
PWMxDCH<7:0>:PWMxDCL<7:6>
TMR2 = 0

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17.1 PWMx Pin Configuration When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
All PWM outputs are multiplexed with the PORT data
latch. The user must configure the pins as outputs by • TMR2 is cleared
clearing the associated TRIS bits. • The PWM output is active. (Exception: When the
PWM duty cycle = 0%, the PWM output will
17.1.1 FUNDAMENTAL OPERATION remain inactive.)
The PWM module produces a 10-bit resolution output. • The PWMxDCH and PWMxDCL register values
Timer2 and PR2 set the period of the PWM. The are latched into the buffers.
PWMxDCL and PWMxDCH registers configure the
duty cycle. The period is common to all PWM modules, Note: The Timer2 postscaler has no effect on the
whereas the duty cycle is independently controlled. PWM operation.
Note: The Timer2 postscaler is not used in the
17.1.4 PWM DUTY CYCLE
determination of the PWM frequency. The
postscaler could be used to have a servo The PWM duty cycle is specified by writing a 10-bit value
update rate at a different frequency than the to the PWMxDCH and PWMxDCL register pair. The
PWM output. PWMxDCH register contains the eight MSbs and the
PWMxDCL<7:6>, the two LSbs. The PWMxDCH and
All PWM outputs associated with Timer2 are set when PWMxDCL registers can be written to at any time.
TMR2 is cleared. Each PWMx is cleared when TMR2
is equal to the value specified in the corresponding Equation 17-2 is used to calculate the PWM pulse
PWMxDCH (8 MSb) and PWMxDCL<7:6> (2 LSb) width.
registers. When the value is greater than or equal to Equation 17-3 is used to calculate the PWM duty cycle
PR2, the PWM output is never cleared (100% duty ratio.
cycle).
Note: The PWMxDCH and PWMxDCL registers EQUATION 17-2: PULSE WIDTH
are double buffered. The buffers are updated
when Timer2 matches PR2. Care should be Pulse Width =  PWMxDCH:PWMxDCL<7:6>  
taken to update both registers before the
T OS C  (TMR2 Prescale Value)
timer match occurs.

17.1.2 PWM OUTPUT POLARITY Note: TOSC = 1/FOSC

The output polarity is inverted by setting the PWMxPOL

bit of the PWMxCON register. EQUATION 17-3: DUTY CYCLE RATIO

17.1.3 PWM PERIOD  PWMxDCH:PWMxDCL<7:6> 

Duty Cycle Ratio = -----------------------------------------------------------------------------------
4  PR2 + 1 
The PWM period is specified by the PR2 register of
Timer2. The PWM period can be calculated using the
formula of Equation 17-1. The 8-bit timer TMR2 register is concatenated with the
two Least Significant bits of 1/FOSC, adjusted by the
EQUATION 17-1: PWM PERIOD Timer2 prescaler to create the 10-bit time base. The
system clock is used if the Timer2 prescaler is set to 1:1.
PWM Period =   PR2  + 1   4  T OSC 
(TMR2 Prescale Value)

Note: TOSC = 1/FOSC

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 PIC16(L)F1704/8
17.1.5 PWM RESOLUTION
The resolution determines the number of available duty
cycles for a given period. For example, a 10-bit resolution
will result in 1024 discrete duty cycles, whereas an 8-bit
resolution will result in 256 discrete duty cycles.
The maximum PWM resolution is ten bits when PR2 is
255. The resolution is a function of the PR2 register
value as shown by Equation 17-4.

EQUATION 17-4: PWM RESOLUTION

log  4  PR2 + 1  
Resolution = ------------------------------------------ bits
log  2 

Note: If the pulse width value is greater than the

period the assigned PWM pin(s) will
remain unchanged.

TABLE 17-1: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)

PWM Frequency 0.31 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz
Timer Prescale 64 4 1 1 1 1
PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17
Maximum Resolution (bits) 10 10 10 8 7 6.6

TABLE 17-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz)

PWM Frequency 0.31 kHz 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz
Timer Prescale 64 4 1 1 1 1
PR2 Value 0x65 0x65 0x65 0x19 0x0C 0x09
Maximum Resolution (bits) 8 8 8 6 5 5

17.1.6 OPERATION IN SLEEP MODE

In Sleep mode, the TMR2 register will not increment
and the state of the module will not change. If the
PWMx pin is driving a value, it will continue to drive that
value. When the device wakes up, TMR2 will continue
from its previous state.

17.1.7 CHANGES IN SYSTEM CLOCK

FREQUENCY
The PWM frequency is derived from the system clock
frequency (FOSC). Any changes in the system clock
frequency will result in changes to the PWM frequency.
Refer to Section 6.0 “Oscillator Module (with
Fail-Safe Clock Monitor)” for additional details.

17.1.8 EFFECTS OF RESET

Any Reset will force all ports to Input mode and the
PWM registers to their Reset states.

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PIC16(L)F1704/8
17.1.9 SETUP FOR PWM OPERATION 17.1.10 SETUP FOR PWM OPERATION TO
USING PWMx PINS OTHER DEVICE PERIPHERALS
The following steps should be taken when configuring The following steps should be taken when configuring
the module for PWM operation using the PWMx pins: the module for PWM operation to be used by other
1. Disable the PWMx pin output driver(s) by setting device peripherals:
the associated TRIS bit(s). 1. Disable the PWMx pin output driver(s) by setting
2. Clear the PWMxCON register. the associated TRIS bit(s).
3. Load the PR2 register with the PWM period value. 2. Clear the PWMxCON register.
4. Load the PWMxDCH register and bits <7:6> of 3. Load the PR2 register with the PWM period value.
the PWMxDCL register with the PWM duty cycle 4. Load the PWMxDCH register and bits <7:6> of
value. the PWMxDCL register with the PWM duty cycle
5. Configure and start Timer2: value.
• Clear the TMR2IF interrupt flag bit of the PIR1 5. Configure and start Timer2:
register. See Note below. • Clear the TMR2IF interrupt flag bit of the PIR1
• Configure the T2CKPS bits of the T2CON register. See Note below.
register with the Timer2 prescale value. • Configure the T2CKPS bits of the T2CON
• Enable Timer2 by setting the TMR2ON bit of register with the Timer2 prescale value.
the T2CON register. • Enable Timer2 by setting the TMR2ON bit of
6. Enable PWM output pin and wait until Timer2 the T2CON register.
overflows, TMR2IF bit of the PIR1 register is set. 6. Enable PWM output pin:
See Note below. • Wait until Timer2 overflows, TMR2IF bit of the
7. Enable the PWMx pin output driver(s) by clear- PIR1 register is set. See Note below.
ing the associated TRIS bit(s) and setting the 7. Configure the PWM module by loading the
desired pin PPS control bits. PWMxCON register with the appropriate values.
8. Configure the PWM module by loading the Note: In order to send a complete duty cycle and
PWMxCON register with the appropriate values. period on the first PWM output, the above
Note 1: In order to send a complete duty cycle steps must be included in the setup
and period on the first PWM output, the sequence. If it is not critical to start with a
above steps must be followed in the order complete PWM signal on the first output,
given. If it is not critical to start with a then step 6 may be ignored.
complete PWM signal, then move Step 8
to replace Step 4.
2: For operation with other peripherals only,
disable PWMx pin outputs.

DS40001715D-page 166  2013-2015 Microchip Technology Inc.

 PIC16(L)F1704/8
17.2 Register Definitions: PWM Control

REGISTER 17-1: PWMxCON: PWM CONTROL REGISTER

R/W-0/0 U-0 R-0/0 R/W-0/0 U-0 U-0 U-0 U-0
PWMxEN — PWMxOUT PWMxPOL — — — —
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 PWMxEN: PWM Module Enable bit

1 = PWM module is enabled
0 = PWM module is disabled
bit 6 Unimplemented: Read as ‘0’
bit 5 PWMxOUT: PWM module output level when bit is read.
bit 4 PWMxPOL: PWMx Output Polarity Select bit
1 = PWM output is active-low.
0 = PWM output is active-high.
bit 3-0 Unimplemented: Read as ‘0’

 2013-2015 Microchip Technology Inc. DS40001715D-page 167

PIC16(L)F1704/8

REGISTER 17-2: PWMxDCH: PWM DUTY CYCLE HIGH BITS

R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
PWMxDCH<7:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 PWMxDCH<7:0>: PWM Duty Cycle Most Significant bits

These bits are the MSbs of the PWM duty cycle. The two LSbs are found in PWMxDCL Register.

REGISTER 17-3: PWMxDCL: PWM DUTY CYCLE LOW BITS

R/W-x/u R/W-x/u U-0 U-0 U-0 U-0 U-0 U-0
PWMxDCL<7:6> — — — — — —
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 PWMxDCL<7:6>: PWM Duty Cycle Least Significant bits

These bits are the LSbs of the PWM duty cycle. The MSbs are found in PWMxDCH Register.
bit 5-0 Unimplemented: Read as ‘0’

TABLE 17-3: SUMMARY OF REGISTERS ASSOCIATED WITH PWM

Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page

CCPTMRS P4TSEL<1:0> P3TSEL<1:0> C2TSEL<1:0> C1TSEL<1:0> 260

PR2 Timer2 module Period Register 256
PWM3CON PWM3EN — PWM3OUT PWM3POL — — — — 167
PWM3DCH PWM3DCH<7:0> 168
PWM3DCL PWM3DCL<7:6> — — — — — — 168
PWM4CON PWM4EN — PWM4OUT PWM4POL — — — — 167
PWM4DCH PWM4DCH<7:0> 168
PWM4DCL PWM4DCL<7:6> — — — — — — 168
RxyPPS — — — RxyPPS<4:0> 140
T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 258
TMR2 Timer2 module Register 256
Legend: - = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the PWM.

DS40001715D-page 168  2013-2015 Microchip Technology Inc.

 PIC16(L)F1704/8
18.0 COMPLEMENTARY OUTPUT 18.1 Fundamental Operation
GENERATOR (COG) MODULE
18.1.1 STEERING (ALL MODES)
The primary purpose of the Complementary Output
Generator (COG) is to convert a single output PWM The active COG data can be independently steered to
signal into a two output complementary PWM signal. four outputs. Steering applies only to modes 000 and
The COG can also convert two separate input events 001. Outputs are selected by setting the GxSTRA
into a single or complementary PWM output. through GxSTRD bits of the GxSTR register
(Register 18-9). Depending on the mode, the signal on
The COG PWM frequency and duty cycle are the output will be the primary PWM signal, the
determined by a rising event input and a falling event complement of the primary signal, or a static level.
input. The rising event and falling event may be the When the steering bits are cleared then the output data
same source. Sources may be synchronous or is the static level determined by the GxSDATA through
asynchronous to the COG_clock. GxSDATD bits of the GxSTR register.
The rate at which the rising event occurs determines
the PWM frequency. The time from the rising event 18.1.2 STEERED PWM MODES
input to the falling event input determines the duty In steered PWM mode, the PWM signal derived from
cycle. the input event sources is output as a single phase
A selectable clock input is used to generate the phase PWM which can be steered to any combination of the
delay, blanking, and dead-band times. Dead-band time four COG outputs. Output steering takes effect on the
can also be generated with a programmable time delay, instruction cycle following the write to the GxSTR
which is independent from all clock sources. register.
Simplified block diagrams of the various COG modes Synchronous steered PWM mode is identical to the
are shown in Figure 18-2 through Figure 18-6. steered PWM mode except that changes to the output
steering take effect on the first rising event after the
The COG module has the following features:
GxSTR register write. Static output data is not
• Six modes of operation: synchronized.
- Steered PWM mode Steering mode configurations are shown in Figure 18-2
- Synchronous Steered PWM mode and Figure 18-3.
- Forward Full-Bridge mode Steered PWM and synchronous steered PWM modes
- Reverse Full-Bridge mode are selected by setting the GxMD bits of the
- Half-Bridge mode COGxCON0 register (Register 18-1) to ‘000’ and ‘001’
- Push-Pull mode respectively.
• Selectable COG_clock clock source
18.1.3 FULL-BRIDGE MODES
• Independently selectable rising event sources
In both Forward and Reverse Full-Bridge modes, two of
• Independently selectable falling event sources
the four COG outputs are active and the other two are
• Independently selectable edge or level event inactive. Of the two active outputs, one is modulated by
sensitivity the PWM input signal and the other is on at 100% duty
• Independent output polarity selection cycle. When the direction is changed, the dead-band
• Phase delay with independent rising and falling time is inserted to delay the modulated output. This
delay times gives the unmodulated driver time to shut down,
• Dead-band control with: thereby, preventing shoot-through current in the series
connected power devices.
- independent rising and falling event
dead-band times In Forward Full-Bridge mode, the PWM input
- Synchronous and asynchronous timing modulates the COGxD output and drives the COGA
output at 100%.
• Blanking control with independent rising and
falling event blanking times In Reverse Full-Bridge mode, the PWM input
• Auto-shutdown control with: modulates the COGxB output and drives the COGxC
output at 100%.
- Independently selectable shutdown sources
- Auto-restart enable The full-bridge configuration is shown in Figure 18-4.
Typical full-bridge waveforms are shown in
- Auto-shutdown pin override control
Figure 18-12 and Figure 18-13.
(high, low, off, and High-Z)
Full-Bridge Forward and Full-Bridge Reverse modes
are selected by setting the GxMD bits of the
COGxCON0 register to ‘010’ and ‘011’, respectively.

 2013-2015 Microchip Technology Inc. DS40001715D-page 169

 FIGURE 18-1: EXAMPLE OF FULL-BRIDGE APPLICATION
DS40001715D-page 170

PIC16(L)F1704/8
V+

FET QA QC FET
Driver Driver
COGxA

Load
COGxB
FET FET
Driver Driver

COGxC
QB QD

V-
COGxD
 2013-2015 Microchip Technology Inc.
 PIC16(L)F1704/8
18.1.4 HALF-BRIDGE MODE It may be necessary to guard against the possibility of
circuit faults. In this case, the active drive must be
In half-bridge mode, the COG generates a two output
terminated before the Fault condition causes damage.
complementary PWM waveform from rising and falling
This is referred to as auto-shutdown and is covered in
event sources. In the simplest configuration, the rising
Section 18.8 “Auto-shutdown Control”.
and falling event sources are the same signal, which is
a PWM signal with the desired period and duty cycle. The COG can be configured to operate in phase
The COG converts this single PWM input into a dual delayed conjunction with another PWM. The active
complementary PWM output. The frequency and duty drive cycle is delayed from the rising event by a phase
cycle of the dual PWM output match those of the single delay timer. Phase delay is covered in more detail in
input PWM signal. The off-to-on transition of each out- Section 18.7 “Phase Delay”.
put can be delayed from the on-to-off transition of the A typical operating waveform, with phase delay and
other output, thereby, creating a time immediately after dead-band, generated from a single CCP1 input is
the PWM transition where neither output is driven. This shown in Figure 18-10.
is referred to as dead time and is covered in
Section 18.5 “Dead-Band Control”.
A typical operating waveform, with dead-band, generated
from a single CCP1 input is shown in Figure 18-9.
The primary output can be steered to either or both
COGxA and COGxC. The complementary output can be
steered to either or both COGxB and COGxD.
Half-Bridge mode is selected by setting the GxMD bits
of the COGxCON0 register to ‘100’.

18.1.5 PUSH-PULL MODE

In Push-Pull mode, the COG generates a single PWM
output that alternates, every PWM period, between the
two pairs of the COG outputs. COGxA has the same
signal as COGxC. COGxB has the same signal as
COGxD. The output drive activates with the rising input
event and terminates with the falling event input. Each
rising event starts a new period and causes the output
to switch to the COG pair not used in the previous
period.
The push-pull configuration is shown in Figure 18-6. A
typical push-pull waveform generated from a single
CCP1 input is shown in Figure 18-11.
Push-Pull mode is selected by setting the GxMD bits of
the COGxCON0 register to ‘101’.

18.1.6 EVENT DRIVEN PWM (ALL MODES)

Besides generating PWM and complementary outputs
from a single PWM input, the COG can also generate
PWM waveforms from a periodic rising event and a
separate falling event. In this case, the falling event is
usually derived from analog feedback within the
external PWM driver circuit. In this configuration, high
power switching transients may trigger a false falling
event that needs to be blanked out. The COG can be
configured to blank falling (and rising) event inputs for
a period of time immediately following the rising (and
falling) event drive output. This is referred to as input
blanking and is covered in Section 18.6 “Blanking
Control”.

 2013-2015 Microchip Technology Inc. DS40001715D-page 171

 FIGURE 18-2: SIMPLIFIED COG BLOCK DIAGRAM (STEERED PWM MODE, GXMD = 0)
DS40001715D-page 172

PIC16(L)F1704/8
GxASDAC<1:0>

‘1’ 11
‘0’ 10
High-Z 01
reserved 11 00
HFINTOSC 10 COG_clock 1 COGxA
Fosc 01 1
Fosc/4 00 0
GxPOLA GxSDATA 0
GxCS<1:0> Rising Input Block GxSTRA GxASDBD<1:0>
unimplemented src7 clock
src6 ‘1’ 11
PWM3OUT
src5 Reset Dominates ‘0’ 10
CCP2
src4 High-Z 01
CCP1 rising_event S Q 00
CLC1OUT src3 1 COGxB
C2OUT src2 R Q 1
C1OUT src1 0
COGINPPS src0 count_en GxSDATB 0
GxPOLB
GxSTRB GxASDAC<1:0>
Falling Input Block
unimplemented src7 ‘1’ 11
src6 clock ‘0’ 10
PWM3OUT
CCP2 src5 High-Z 01
src4 00
CCP1
CLC1OUT src3 falling_event 1 COGxC
C2OUT src2 1
C1OUT src1 0
COGINPPS src0 GxSDATC 0
count_en GxPOLC
GxSTRC GxASDBD<1:0>

‘1’ 11
‘0’ 10
GxEN
High-Z 01
00
 2013-2015 Microchip Technology Inc.

1 COGxD
COGINPPS 1
GxAS0E 0
C1OUT GxSDATD 0
GxPOLD
GxAS1E Auto-shutdown source
GxSTRD
C2OUT
GxAS2E
CLC2OUT S Q GxASE
GxAS3E GxARSEN S
Write GxASE Low R D Q
Write GxASE High Set Dominates
 FIGURE 18-3: SIMPLIFIED COG BLOCK DIAGRAM (SYNCHRONOUS STEERED PWM MODE, GXMD = 1)
 2013-2015 Microchip Technology Inc.

GxASDAC<1:0>

‘1’ 11
‘0’ 10
High-Z 01
reserved 11 00
HFINTOSC 10 COG_clock 1 COGxA
Fosc 01 1
Fosc/4 00 0
GxPOLA GxSDATA 0
GxCS<1:0> Rising Input Block GxSTRA D Q GxASDBD<1:0>
unimplemented src7 clock
src6 ‘1’ 11
PWM3OUT
src5 Reset Dominates ‘0’ 10
CCP2
src4 High-Z 01
CCP1 rising_event S Q 00
CLC1OUT src3 1 COGxB
C2OUT src2 R Q 1
C1OUT src1 0
COGINPPS src0 count_en GxSDATB 0
GxPOLB
GxSTRB D Q GxASDAC<1:0>
Falling Input Block
unimplemented src7 ‘1’ 11
src6 clock ‘0’ 10
PWM3OUT
CCP2 src5 High-Z 01
src4 00
CCP1
CLC1OUT src3 falling_event 1 COGxC
C2OUT src2 1
C1OUT src1 0
COGINPPS src0 GxSDATC 0
count_en GxPOLC
GxSTRC D Q GxASDBD<1:0>

‘1’

PIC16(L)F1704/8
11
‘0’ 10
GxEN
High-Z 01
00
1 COGxD
COGINPPS 1
GxAS0E 0
C1OUT GxSDATD 0
GxPOLD
GxAS1E Auto-shutdown source
GxSTRD D Q
C2OUT
DS40001715D-page 173

GxAS2E
CLC2OUT S Q GxASE
GxAS3E GxARSEN S
Write GxASE Low R D Q
Write GxASE High Set Dominates
 FIGURE 18-4: SIMPLIFIED COG BLOCK DIAGRAM (FULL-BRIDGE MODES, FORWARD: GXMD = 2, REVERSE: GXMD = 3)
DS40001715D-page 174

PIC16(L)F1704/8
GxASDAC<1:0>

‘1’ 11
‘0’ 10
High-Z 01
reserved 11 00
HFINTOSC 10 COG_clock 1 COGxA
Fosc 01
Fosc/4 00 0
Rising Dead-Band Block
GxCS<1:0> GxPOLA
Rising Input Block GxASDBD<1:0>
clock
unimplemented src7 clock signal_out
src6 ‘1’ 11
PWM3OUT signal_in
src5 Reset Dominates ‘0’ 10
CCP2
src4 High-Z 01
CCP1 rising_event S Q 00
CLC1OUT src3 1 COGxB
C2OUT src2 R Q
C1OUT src1 0
COGINPPS src0 count_en
GxPOLB
GxASDAC<1:0>
Falling Input Block Falling Dead-Band Block
unimplemented src7 ‘1’ 11
clock clock ‘0’ 10
PWM3OUT src6
signal_out High-Z 01
CCP2 src5
src4 signal_in 00
CCP1
CLC1OUT src3 falling_event 1 COGxC
C2OUT src2
C1OUT src1 0
COGINPPS src0 count_en
GxPOLC
GxASDBD<1:0>
Forward/Reverse
GxMD0 D Q ‘1’ 11
‘0’ 10
GxEN
Q High-Z 01
00
 2013-2015 Microchip Technology Inc.

1
COGINPPS COGxD
GxAS0E 0
C1OUT
GxAS1E Auto-shutdown source GxPOLD
C2OUT
GxAS2E
CLC2OUT S Q GxASE
GxAS3E GxARSEN S
Write GxASE Low R D Q
Write GxASE High Set Dominates
 FIGURE 18-5: SIMPLIFIED COG BLOCK DIAGRAM (HALF-BRIDGE MODE, GXMD = 4)
 2013-2015 Microchip Technology Inc.

GxASDAC<1:0>

‘1’ 11
‘0’ 10
High-Z 01
reserved 11 00
HFINTOSC 10 COG_clock 1 COGxA
Fosc 01
Fosc/4 00 0

GxCS<1:0> GxPOLA
Rising Input Block GxASDBD<1:0>
Rising Dead-Band Block
unimplemented src7 clock
src6 clock ‘1’ 11
PWM3OUT
src5 Reset Dominates ‘0’ 10
CCP2 signal_out
src4 High-Z 01
CCP1 rising_event S Q signal_in 00
CLC1OUT src3 1 COGxB
C2OUT src2 R Q
C1OUT src1 0
COGINPPS src0 count_en
GxPOLB
GxASDAC<1:0>
Falling Input Block Falling Dead-Band Block
unimplemented src7 ‘1’ 11
clock clock ‘0’ 10
PWM3OUT src6
signal_out High-Z 01
CCP2 src5
src4 signal_in 00
CCP1
CLC1OUT src3 falling_event 1 COGxC
C2OUT src2
C1OUT src1 0
COGINPPS src0 count_en
GxPOLC
GxASDBD<1:0>

‘1’

PIC16(L)F1704/8
11
‘0’ 10
GxEN
High-Z 01
00
1
COGINPPS COGxD
GxAS0E 0
C1OUT
GxAS1E Auto-shutdown source GxPOLD
C2OUT
DS40001715D-page 175

GxAS2E
CLC2OUT S Q GxASE
GxAS3E GxARSEN S
Write GxASE Low R D Q
Write GxASE High Set Dominates
 FIGURE 18-6: SIMPLIFIED COG BLOCK DIAGRAM (PUSH-PULL MODE, GXMD = 5)
DS40001715D-page 176

PIC16(L)F1704/8
GxASDAC<1:0>

‘1’ 11
‘0’ 10
High-Z 01
reserved 11 00
HFINTOSC 10 COG_clock 1 COGxA
Fosc 01
Fosc/4 00 0

GxCS<1:0> GxPOLA
Rising Input Block GxASDBD<1:0>
unimplemented src7 clock Push-Pull
src6 ‘1’ 11
PWM3OUT D Q
src5 Reset Dominates ‘0’ 10
CCP2
src4 High-Z 01
CCP1 rising_event S Q Q
R 00
CLC1OUT src3 1 COGxB
C2OUT src2 R Q
C1OUT src1 0
COGINPPS src0 count_en
GxPOLB
GxASDAC<1:0>
Falling Input Block
unimplemented src7 ‘1’ 11
src6 clock ‘0’ 10
PWM3OUT
src5 High-Z 01
CCP2
src4 00
CCP1
CLC1OUT src3 falling_event 1 COGxC
C2OUT src2
C1OUT src1 0
COGINPPS src0 count_en
GxPOLC
GxASDBD<1:0>

‘1’ 11
‘0’ 10
GxEN
High-Z 01
00
 2013-2015 Microchip Technology Inc.

1
COGINPPS COGxD
GxAS0E 0
C1OUT
GxAS1E Auto-shutdown source GxPOLD
C2OUT
GxAS2E
CLC2OUT S Q GxASE
GxAS3E GxARSEN S
Write GxASE Low R D Q
Write GxASE High Set Dominates
 FIGURE 18-7: COG (RISING/FALLING) INPUT BLOCK
 2013-2015 Microchip Technology Inc.

clock
GxPH(R/F)<3:0>
Blanking
count_en =
Cnt/Clr Phase
Delay
GxBLK(F/R)<3:0>

src7
Gx(R/F)IS7 D Q 1
(rising/falling)_event
LE 0
Gx(R/F)SIM7
src6
Gx(R/F)IS6 D Q 1

LE 0
Gx(R/F)SIM6
src5
Gx(R/F)IS5 D Q 1

LE 0
Gx(R/F)SIM5
src4
Gx(R/F)IS4 D Q 1

LE 0
Gx(R/F)SIM4
src3
Gx(R/F)IS3 D Q 1

LE 0

PIC16(L)F1704/8
Gx(R/F)SIM3
src2
Gx(R/F)IS2 D Q 1

LE 0
Gx(R/F)SIM2
src1
Gx(R/F)IS1 D Q 1

LE 0
DS40001715D-page 177

Gx(R/F)SIM1
src0
Gx(R/F)IS0 D Q 1

LE 0
Gx(R/F)SIM0
PIC16(L)F1704/8
FIGURE 18-8: COG (RISING/FALLING) DEAD-BAND BLOCK

Gx(R/F)DBTS

clock Synchronous
Delay
=
Cnt/Clr
0 0
1 GxDBR<3:0> 1

Asynchronous
Delay Chain

signal_out
signal_in

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 PIC16(L)F1704/8
FIGURE 18-9: TYPICAL HALF-BRIDGE MODE COG OPERATION WITH CCP1

COG_clock
Source

CCP1

COGxA

Rising_event Dead-band
Falling_event Dead-band Falling_event Dead-band
COGxB

FIGURE 18-10: HALF-BRIDGE MODE COG OPERATION WITH CCP1 AND PHASE DELAY

COG_clock
Source

CCP1

COGxA

Rising_event
Dead-Band
Falling_event Dead-Band Phase Delay Falling_event
Dead-Band
COGxB

FIGURE 18-11: PUSH-PULL MODE COG OPERATION WITH CCP1

CCP1

COGxA

COGxB

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PIC16(L)F1704/8
FIGURE 18-12: FULL-BRIDGE FORWARD MODE COG OPERATION WITH CCP1

CCP1

COGxA

COGxB

COGxC

COGxD

FIGURE 18-13: FULL-BRIDGE MODE COG OPERATION WITH CCP1 AND DIRECTION CHANGE

CCP1

COGxA
Falling_event Dead-Band

COGxB

COGxC

COGxD

CxMD0

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 PIC16(L)F1704/8
18.2 Clock Sources precluding an output change. The comparator output
stays low and without a high-to-low transition to trigger
The COG_clock is used as the reference clock to the the edge sense, the drive of the COG output will be stuck
various timers in the peripheral. Timers that use the in a constant drive-on condition. See Figure 18-14.
COG_clock include:
• Rising and falling dead-band time FIGURE 18-14: EDGE VS LEVEL SENSE
• Rising and falling blanking time
• Rising and falling event phase delay Rising (CCP1)
Clock sources available for selection include:
Falling (C1OUT)
• 8 MHz HFINTOSC (active during Sleep)
• Instruction clock (FOSC/4) C1IN- hyst
• System clock (FOSC)
The clock source is selected with the GxCS<1:0> bits COGOUT
of the COGxCON0 register (Register 18-1).
Edge Sensitive
18.3 Selectable Event Sources
Rising (CCP1)
The COG uses any combination of independently
selectable event sources to generate the
Falling (C1OUT)
complementary waveform. Sources fall into two
categories: hyst
C1IN-
• Rising event sources
• Falling event sources COGOUT
The rising event sources are selected by setting bits in
the COGxRIS register (Register 18-3). The falling event Level Sensitive
sources are selected by setting bits in the COGxFIS
register (Register 18-5). All selected sources are ‘OR’d 18.3.2 RISING EVENT
together to generate the corresponding event signal.
Refer to Figure 18-7. The rising event starts the PWM output active duty
cycle period. The rising event is the low-to-high
18.3.1 EDGE VS. LEVEL SENSING transition of the rising_event output. When the rising
event phase delay and dead-band time values are zero,
Event input detection may be selected as level or edge the primary output starts immediately. Otherwise, the
sensitive. The detection mode is individually selectable primary output is delayed. The rising event source
for every source. Rising source detection modes are causes all the following actions:
selected with the COGxRSIM register (Register 18-4).
Falling source detection modes are selected with the • Start rising event phase delay counter (if enabled).
COGxFSIM register (Register 18-6). A set bit enables • Clear complementary output after phase delay.
edge detection for the corresponding event source. A • Start falling event input blanking (if enabled).
cleared bit enables level detection. • Start dead-band delay (if enabled).
In general, events that are driven from a periodic • Set primary output after dead-band delay expires.
source should be edge detected and events that are
derived from voltage thresholds at the target circuit 18.3.3 FALLING EVENT
should be level sensitive. Consider the following two The falling event terminates the PWM output active duty
examples: cycle period. The falling event is the high-to-low
1. The first example is an application in which the transition of the falling_event output. When the falling
period is determined by a 50% duty cycle clock and the event phase delay and dead-band time values are zero,
COG output duty cycle is determined by a voltage level the complementary output starts immediately. Otherwise,
fed back through a comparator. If the clock input is level the complementary output is delayed. The falling event
sensitive, duty cycles less than 50% will exhibit erratic source causes all the following actions:
operation. • Start falling event phase delay counter (if enabled).
2. The second example is similar to the first except that • Clear primary output.
the duty cycle is close to 100%. The feedback • Start rising event input blanking (if enabled).
comparator high-to-low transition trips the COG drive off,
• Start falling event dead-band delay (if enabled).
but almost immediately the period source turns the drive
back on. If the off cycle is short enough, the comparator • Set complementary output after dead-band delay
input may not reach the low side of the hysteresis band expires.

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18.4 Output Control In Half-Bridge mode, the rising_event dead-band time
delays all selected primary outputs from going active
Upon disabling, or immediately after enabling the COG for the selected dead time after the rising event.
module, the primary COG outputs are inactive and COGxA and COGxC are the primary outputs in
complementary COG outputs are active. Half-Bridge mode.
18.4.1 OUTPUT ENABLES In Half-Bridge mode, the falling_event dead-band time
delays all selected complementary outputs from going
There are no output enable controls in the COG active for the selected dead time after the falling event.
module. Instead, each device pin has an individual COGxB and COGxD are the complementary outputs in
output selection control called the PPS register. All Half-Bridge mode.
four COG outputs are available for selection in the
PPS register of every pin. In Full-Bridge mode, the dead-time delay occurs only
during direction changes. The modulated output is
When a COG output is enabled by PPS selection, the delayed for the falling_event dead time after a direction
output on the pin has several possibilities, which change from forward to reverse. The modulated output
depend on the steering control, GxEN bit, and is delayed for the rising_event dead time after a
shutdown state as shown in Table 18-1 direction change from reverse to forward.
.
TABLE 18-1: PIN OUTPUT STATES 18.5.1 ASYNCHRONOUS DELAY CHAIN
DEAD-BAND DELAY
GxSTR
GxEN
bit
Shutdown Output Asynchronous dead-band delay is determined by the
time it takes the input to propagate through a series of
x 0 Inactive Static steering data delay elements. Each delay element is a nominal five
x 1 Active Shutdown override nanoseconds.
0 1 Inactive Inactive state Set the COGxDBR register (Register 18-10) value to
1 1 Inactive Active PWM signal the desired number of delay elements in the
rising_event dead-band time. Set the COGxDBF
18.4.2 POLARITY CONTROL register (Register 18-11) value to the desired number
of delay elements in the falling_event dead-band time.
The polarity of each COG output can be selected When the value is zero, dead-band delay is disabled.
independently. When the output polarity bit is set, the
corresponding output is active-low. Clearing the output 18.5.2 SYNCHRONOUS COUNTER
polarity bit configures the corresponding output as DEAD-BAND DELAY
active-high. However, polarity affects the outputs in
only one of the four shutdown override modes. See Synchronous counter dead band is timed by counting
Section 18.8, Auto-shutdown Control for more details. COG_clock periods from zero up to the value in the
dead-band count register. Use Equation 18-1 to
Output polarity is selected with the GxPOLA through calculate dead-band times.
GxPOLD bits of the COGxCON1 register
(Register 18-2). Set the COGxDBR count register value to obtain the
desired rising_event dead-band time. Set the
COGxDBF count register value to obtain the desired
18.5 Dead-Band Control
falling_event dead-band time. When the value is zero,
The dead-band control provides for non-overlapping dead-band delay is disabled.
PWM output signals to prevent shoot-through current
in the external power switches. Dead time affects the 18.5.3 SYNCHRONOUS COUNTER
output only in the Half-Bridge mode and when DEAD-BAND TIME UNCERTAINTY
changing direction in the Full-Bridge mode. When the rising and falling events that trigger the
The COG contains two dead-band timers. One dead-band counters come from asynchronous inputs,
dead-band timer is used for rising event dead-band it creates uncertainty in the synchronous counter
control. The other is used for falling event dead-band dead-band time. The maximum uncertainty is equal to
control. Timer modes are selectable as either: one COG_clock period. Refer to Example 18-1 for
more detail.
• Asynchronous delay chain
• Synchronous counter When event input sources are asynchronous with no
phase delay, use the asynchronous delay chain
The dead-band timer mode is selected for the dead-band mode to avoid the dead-band time
rising_event and falling_event dead-band times with uncertainty.
the respective GxRDBS and GxFDBS bits of the
COGxCON1 register (Register 18-2).

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 PIC16(L)F1704/8
18.5.4 RISING EVENT DEAD-BAND falling input events. Once started, blanking extends for
the time specified by the corresponding blanking
Rising event dead band delays the turn-on of the
counter.
primary outputs from when complementary outputs are
turned off. The rising event dead-band time starts Blanking is timed by counting COG_clock periods from
when the rising_ event output goes true. zero up to the value in the blanking count register. Use
Equation 18-1 to calculate blanking times.
See Section 18.5.1, Asynchronous delay chain
dead-band delay and Section 18.5.2, Synchronous
18.6.1 FALLING EVENT BLANKING OF
counter dead-band delay for more information on
RISING EVENT INPUTS
setting the rising edge dead-band time.
The falling event blanking counter inhibits rising event
18.5.5 FALLING EVENT DEAD-BAND inputs from triggering a rising event. The falling event
Falling event dead band delays the turn-on of blanking time starts when the rising event output drive
complementary outputs from when the primary outputs goes false.
are turned off. The falling event dead-band time starts The falling event blanking time is set by the value
when the falling_ event output goes true. contained in the COGxBLKF register (Register 18-13).
See Section 18.5.1, Asynchronous delay chain Blanking times are calculated using the formula shown
dead-band delay and Section 18.5.2, Synchronous in Equation 18-1.
counter dead-band delay for more information on When the COGxBLKF value is zero, falling event
setting the rising edge dead-band time. blanking is disabled and the blanking counter output is
true, thereby, allowing the event signal to pass straight
18.5.6 DEAD-BAND OVERLAP through to the event trigger circuit.
There are two cases of dead-band overlap:
18.6.2 RISING EVENT BLANKING OF
• Rising-to-falling FALLING EVENT INPUTS
• Falling-to-rising
The rising event blanking counter inhibits falling event
18.5.6.1 Rising-to-Falling Overlap inputs from triggering a falling event. The rising event
blanking time starts when the falling event output drive
In this case, the falling event occurs while the rising goes false.
event dead-band counter is still counting. When this
happens, the primary drives are suppressed and the The rising event blanking time is set by the value
dead-band extends by the falling event dead-band contained in the COGxBLKR register (Register 18-12).
time. At the termination of the extended dead-band When the COGxBLKR value is zero, rising event
time, the complementary drive goes true. blanking is disabled and the blanking counter output is
true, thereby, allowing the event signal to pass straight
18.5.6.2 Falling-to-Rising Overlap through to the event trigger circuit.
In this case, the rising event occurs while the falling
event dead-band counter is still counting. When this 18.6.3 BLANKING TIME UNCERTAINTY
happens, the complementary drive is suppressed and When the rising and falling sources that trigger the
the dead-band extends by the rising event dead-band blanking counters are asynchronous to the
time. At the termination of the extended dead-band COG_clock, it creates uncertainty in the blanking time.
time, the primary drive goes true. The maximum uncertainty is equal to one COG_clock
period. Refer to Equation 18-1 and Example 18-1 for
18.6 Blanking Control more detail.

Input blanking is a function, whereby, the event inputs 18.7 Phase Delay
can be masked or blanked for a short period of time.
This is to prevent electrical transients caused by the It is possible to delay the assertion of either or both the
turn-on/off of power components from generating a rising event and falling events. This is accomplished
false input event. by placing a non-zero value in COGxPHR or
The COG contains two blanking counters: one COGxPHF phase-delay count register, respectively
triggered by the rising event and the other triggered by (Register 18-14 and Register 18-15). Refer to
the falling event. The counters are cross coupled with Figure 18-10 for COG operation with CCP1 and phase
the events they are blanking. The falling event delay. The delay from the input rising event signal
blanking counter is used to blank rising input events switching to the actual assertion of the events is
and the rising event blanking counter is used to blank calculated the same as the dead-band and blanking
delays. Refer to Equation 18-1.

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PIC16(L)F1704/8
When the phase-delay count value is zero, phase EXAMPLE 18-1: TIMER UNCERTAINTY
delay is disabled and the phase-delay counter output
Given:
is true, thereby, allowing the event signal to pass
straight through to the complementary output driver Count = Ah = 10d
flop. F COG_Clock = 8MHz
Therefore:
18.7.1 CUMULATIVE UNCERTAINTY 1
It is not possible to create more than one COG_clock of
T uncertainty = --------------------------
F COG_clock
uncertainty by successive stages. Consider that the
phase-delay stage comes after the blanking stage, the 1
= --------------- = 125ns
dead-band stage comes after either the blanking or 8MHz
phase-delay stages, and the blanking stage comes
after the dead-band stage. When the preceding stage
is enabled, the output of that stage is necessarily Proof:
synchronous with the COG_clock, which removes any Count
T min = --------------------------
possibility of uncertainty in the succeeding stage. F COG_clock
EQUATION 18-1: PHASE, DEAD-BAND, = 125ns  10d = 1.25s
AND BLANKING TIME
CALCULATION
Count + 1
T max = --------------------------
F COG_clock
T min = Count
F COG_clock = 125ns   10d + 1 
Count + 1 = 1.375s
T max = --------------------------
F COG_clock Therefore:
T uncertainty = T max – T min T uncertainty = T max – T min
Also: = 1.375s – 1.25s
1
T uncertainty = --------------------------
F COG_clock = 125ns
Where:

T Count
Rising Phase Delay COGxPHR
Falling Phase Delay COGxPHF
Rising Dead Band COGxDBR
Falling Dead Band COGxDBF
Rising Event Blanking COGxBLKR
Falling Event Blanking COGxBLKF

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 PIC16(L)F1704/8
18.8 Auto-shutdown Control 18.8.2 PIN OVERRIDE LEVELS
Auto-shutdown is a method to immediately override The levels driven to the output pins, while the
the COG output levels with specific overrides that shutdown is active, are controlled by the
allow for safe shutdown of the circuit. GxASDAC<1:0> and GxASDBC<1:0> bits of the
COGxASD0 register (Register 18-7). GxASDAC<1:0>
The shutdown state can be either cleared controls the COGxA and COGxC override levels and
automatically or held until cleared by software. In GxASDBC<1:0> controls the COGxB and COGxD
either case, the shutdown overrides remain in effect override levels. There are four override options for
until the first rising event after the shutdown is cleared. each output pair:
18.8.1 SHUTDOWN • Forced low
The shutdown state can be entered by either of the • Forced high
following two mechanisms: • Tri-state
• Software generated • PWM inactive state (same state as that caused by
a falling event)
• External Input
Note: The polarity control does not apply to the
18.8.1.1 Software Generated Shutdown forced low and high override levels but
Setting the GxASE bit of the COGxASD0 register does apply to the PWM inactive state.
(Register 18-7) will force the COG into the shutdown
state. 18.8.3 AUTO-SHUTDOWN RESTART
When auto-restart is disabled, the shutdown state will After an auto-shutdown event has occurred, there are
persist until the first rising event after the GxASE bit is two ways to resume operation:
cleared by software. • Software controlled
When auto-restart is enabled, the GxASE bit will clear • Auto-restart
automatically and resume operation on the first rising The restart method is selected with the GxARSEN bit
event after the shutdown input clears. See of the COGxASD0 register. Waveforms of a software
Figure 18-15 and Section 18.8.3.2 “Auto-Restart”. controlled automatic restart are shown in Figure 18-15.

18.8.1.2 External Shutdown Source 18.8.3.1 Software Controlled Restart

External shutdown inputs provide the fastest way to When the GxARSEN bit of the COGxASD0 register is
safely suspend COG operation in the event of a Fault cleared, software must clear the GxASE bit to restart
condition. When any of the selected shutdown inputs COG operation after an auto-shutdown event.
goes true, the output drive latches are reset and the
The COG will resume operation on the first rising
COG outputs immediately go to the selected override
event after the GxASE bit is cleared. Clearing the
levels without software delay.
shutdown state requires all selected shutdown inputs
Any combination of the input sources can be selected to be false, otherwise, the GxASE bit will remain set.
to cause a shutdown condition. Shutdown occurs
when the selected source is low. Shutdown input 18.8.3.2 Auto-Restart
sources include:
When the GxARSEN bit of the COGxASD0 register is
• Any input pin selected with the COGxPPS control set, the COG will restart from the auto-shutdown state
• C2OUT automatically.
• C1OUT The GxASE bit will clear automatically and the COG
• CLC2OUT will resume operation on the first rising event after all
selected shutdown inputs go false.
Shutdown inputs are selected independently with bits
of the COGxASD1 register (Register 18-8).

Note: Shutdown inputs are level sensitive, not

edge sensitive. The shutdown state cannot
be cleared as long as the shutdown input
level persists, except by disabling
auto-shutdown,

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 FIGURE 18-15: AUTO-SHUTDOWN WAVEFORM – CCP1 AS RISING AND FALLING EVENT INPUT SOURCE
DS40001715D-page 186

PIC16(L)F1704/8
1 2 3 4 5

CCP1

GxARSEN

Next rising event

Shutdown input

Next rising event Cleared in hardware

GxASE Cleared in software

GxASDAC 2b00

GxASDBD 2b00 2b00

COGxA

COGxB

Operating State
 2013-2015 Microchip Technology Inc.

NORMAL OUTPUT SHUTDOWN NORMAL OUTPUT SHUTDOWN NORMAL OUTPUT

SOFTWARE CONTROLLED RESTART AUTO-RESTART

 PIC16(L)F1704/8
18.9 Buffer Updates 18.12 Configuring the COG
Changes to the phase, dead band, and blanking count The following steps illustrate how to properly configure
registers need to occur simultaneously during COG the COG to ensure a synchronous start with the rising
operation to avoid unintended operation that may event input:
occur as a result of delays between each register 1. If a pin is to be used for the COG fault or event
write. This is accomplished with the GxLD bit of the input, use the COGxPPS register to configure
COGxCON0 register and double buffering of the the desired pin.
phase, blanking, and dead-band count registers.
2. Clear all ANSEL register bits associated with
Before the COG module is enabled, writing the count pins that are used for COG functions.
registers loads the count buffers without need of the 3. Ensure that the TRIS control bits corresponding
GxLD bit. However, when the COG is enabled, the to the COG outputs to be used are set so that all
count buffer updates are suspended after writing the are configured as inputs. The COG module will
count registers until after the GxLD bit is set. When the enable the output drivers as needed later.
GxLD bit is set, the phase, dead-band, and blanking
4. Clear the GxEN bit, if not already cleared.
register values are transferred to the corresponding
buffers synchronous with COG operation. The GxLD 5. Set desired dead-band times with the
bit is cleared by hardware when the transfer is COGxDBR and COGxDBF registers and select
complete. the source with the COGxRDBS and
COGxFDBS bits of the COGxCON1 register.
18.10 Input and Output Pin Selection 6. Set desired blanking times with the COGxBLKR
and COGxBLKF registers.
The COG has one selection for an input from a device 7. Set desired phase delay with the COGxPHR
pin. That one input can be used as rising and falling and COGxPHF registers.
event source or a fault source. The COG1PPS register
8. Select the desired shutdown sources with the
is used to select the pin. Refer to Register 12-1 and
COGxASD1 register.
Register 12-2.
9. Setup the following controls in COGxASD0
The pin PPS control registers are used to enable the auto-shutdown register:
COG outputs. Any combination of outputs to pins is
• Select both output override controls to the
possible including multiple pins for the same output.
desired levels (this is necessary, even if not
See the RxyPPS control register and Section 12.2
using auto-shutdown because start-up will be
“PPS Outputs” for more details.
from a shutdown state).
• Set the GxASE bit and clear the GxARSEN
18.11 Operation During Sleep bit.
The COG continues to operate in Sleep provided that 10. Select the desired rising and falling event sources
the COG_clock, rising event, and falling event sources with the COGxRIS and COGxFIS registers.
remain active. 11. Select the desired rising and falling event modes
The HFINTSOC remains active during Sleep when the with the COGxRSIM and COGxFSIM registers.
COG is enabled and the HFINTOSC is selected as the 12. Configure the following controls in the
COG_clock source. COGxCON1 register:
• Select the desired clock source
• Select the desired dead-band timing sources
13. Configure the following controls in the
COGxSTR register:
• Set the steering bits of the outputs to be
used.
• Set the static levels.
14. Set the polarity controls in the COGxCON1
register.
15. Set the GxEN bit.
16. Set the pin PPS controls to direct the COG
outputs to the desired pins.
17. If auto-restart is to be used, set the GxARSEN bit
and the GxASE will be cleared automatically.
Otherwise, clear the GxASE bit to start the COG.

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18.13 Register Definitions: COG Control

REGISTER 18-1: COGxCON0: COG CONTROL REGISTER 0

R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
GxEN GxLD — GxCS<1:0> GxMD<2:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7 GxEN: COGx Enable bit

1 = Module is enabled
0 = Module is disabled
bit 6 GxLD: COGx Load Buffers bit
1 = Phase, blanking, and dead-band buffers to be loaded with register values on next input events
0 = Register to buffer transfer is complete
bit 5 Unimplemented: Read as ‘0’
bit 4-3 GxCS<1:0>: COGx Clock Selection bits
11 = Reserved. Do not use.
10 = COG_clock is HFINTOSC (stays active during Sleep)
01 = COG_clock is FOSC
00 = COG_clock is FOSC/4
bit 2-0 GxMD<2:0>: COGx Mode Selection bits
11x = Reserved. Do not use.
101 = COG outputs operate in Push-Pull mode
100 = COG outputs operate in Half-Bridge mode
011 = COG outputs operate in Reverse Full-Bridge mode
010 = COG outputs operate in Forward Full-Bridge mode
001 = COG outputs operate in synchronous steered PWM mode
000 = COG outputs operate in steered PWM mode

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 PIC16(L)F1704/8

REGISTER 18-2: COGxCON1: COG CONTROL REGISTER 1

R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
GxRDBS GxFDBS — — GxPOLD GxPOLC GxPOLB GxPOLA
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7 GxRDBS: COGx Rising Event Dead-band Timing Source Select bit
1 = Delay chain and COGxDBR are used for dead-band timing generation
0 = COGx_clock and COGxDBR are used for dead-band timing generation
bit 6 GxFDBS: COGx Falling Event Dead-band Timing Source select bit
1 = Delay chain and COGxDF are used for dead-band timing generation
0 = COGx_clock and COGxDBF are used for dead-band timing generation
bit 5-4 Unimplemented: Read as ‘0’.
bit 3 GxPOLD: COGxD Output Polarity Control bit
1 = Active level of COGxD output is low
0 = Active level of COGxD output is high
bit 2 GxPOLC: COGxC Output Polarity Control bit
1 = Active level of COGxC output is low
0 = Active level of COGxC output is high
bit 1 GxPOLB: COGxB Output Polarity Control bit
1 = Active level of COGxB output is low
0 = Active level of COGxB output is high
bit 0 GxPOLA: COGxA Output Polarity Control bit
1 = Active level of COGxA output is low
0 = Active level of COGxA output is high

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PIC16(L)F1704/8

REGISTER 18-3: COGxRIS: COG RISING EVENT INPUT SELECTION REGISTER

U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— GxRIS6 GxRIS5 GxRIS4 GxRIS3 GxRIS2 GxRIS1 GxRIS0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7 Unimplemented: Read as ‘0’

bit 6 GxRIS6: COGx Rising Event Input Source 6 Enable bit
1 = PWM3 output is enabled as a rising event input
0 = PWM3 has no effect on the rising event
bit 5 GxRIS5: COGx Rising Event Input Source 5 Enable bit
1 = CCP2 output is enabled as a rising event input
0 = CCP2 output has no effect on the rising event
bit 4 GxRIS4: COGx Rising Event Input Source 4 Enable bit
1 = CCP1 is enabled as a rising event input
0 = CCP1 has no effect on the rising event
bit 3 GxRIS3: COGx Rising Event Input Source 3 Enable bit
1 = CLC1 output is enabled as a rising event input
0 = CLC1 output has no effect on the rising event
bit 2 GxRIS2: COGx Rising Event Input Source 2 Enable bit
1 = Comparator 2 output is enabled as a rising event input
0 = Comparator 2 output has no effect on the rising event
bit 1 GxRIS1: COGx Rising Event Input Source 1 Enable bit
1 = Comparator 1 output is enabled as a rising event input
0 = Comparator 1 output has no effect on the rising event
bit 0 GxRIS0: COGx Rising Event Input Source 0 Enable bit
1 = Pin selected with COGxPPS control register is enabled as rising event input
0 = Pin selected with COGxPPS control has no effect on the rising event

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REGISTER 18-4: COGxRSIM: COG RISING EVENT SOURCE INPUT MODE REGISTER
U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— GxRSIM6 GxRSIM5 GxRSIM4 GxRSIM3 GxRSIM2 GxRSIM1 GxRSIM0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7 Unimplemented: Read as ‘0’

bit 6 GxRSIM6: COGx Rising Event Input Source 6 Mode bit
GxRIS6 = 1:
1 = PWM3 output low-to-high transition will cause a rising event after rising event phase delay
0 = PWM3 output high level will cause an immediate rising event
GxRIS6 = 0:
PWM3 output has no effect on rising event
bit 5 GxRSIM5: COGx Rising Event Input Source 5 Mode bit
GxRIS5 = 1:
1 = CCP2 output low-to-high transition will cause a rising event after rising event phase delay
0 = CCP2 output high level will cause an immediate rising event
GxRIS5 = 0:
CCP2 output has no effect on rising event
bit 4 GxRSIM4: COGx Rising Event Input Source 4 Mode bit
GxRIS4 = 1:
1 = CCP1 low-to-high transition will cause a rising event after rising event phase delay
0 = CCP1 high level will cause an immediate rising event
GxRIS4 = 0:
CCP1 has no effect on rising event
bit 3 GxRSIM3: COGx Rising Event Input Source 3 Mode bit
GxRIS3 = 1:
1 = CLC1 output low-to-high transition will cause a rising event after rising event phase delay
0 = CLC1 output high level will cause an immediate rising event
GxRIS3 = 0:
CLC1 output has no effect on rising event
bit 2 GxRSIM2: COGx Rising Event Input Source 2 Mode bit
GxRIS2 = 1:
1 = Comparator 2 low-to-high transition will cause a rising event after rising event phase delay
0 = Comparator 2 high level will cause an immediate rising event
GxRIS2 = 0:
Comparator 2 has no effect on rising event
bit 1 GxRSIM1: COGx Rising Event Input Source 1 Mode bit
GxRIS1 = 1:
1 = Comparator 1 low-to-high transition will cause a rising event after rising event phase delay
0 = Comparator 1 high level will cause an immediate rising event
GxRIS1 = 0:
Comparator 1 has no effect on rising event
bit 0 GxRSIM0: COGx Rising Event Input Source 0 Mode bit
GxRIS0 = 1:
1 = Pin selected with COGxPPS control low-to-high transition will cause a rising event after rising event
phase delay
0 = Pin selected with COGxPPS control high level will cause an immediate rising event
GxRIS0 = 0:
Pin selected with COGxPPS control has no effect on rising event

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REGISTER 18-5: COGxFIS: COG FALLING EVENT INPUT SELECTION REGISTER

U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— GxFIS6 GxFIS5 GxFIS4 GxFIS3 GxFIS2 GxFIS1 GxFIS0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7 Unimplemented: Read as ‘0’

bit 6 GxFIS6: COGx Falling Event Input Source 6 Enable bit
1 = PWM3 output is enabled as a falling event input
0 = PWM3 has no effect on the falling event
bit 5 GxFIS5: COGx Falling Event Input Source 5 Enable bit
1 = CCP2 output is enabled as a falling event input
0 = CCP2 output has no effect on the falling event
bit 4 GxFIS4: COGx Falling Event Input Source 4 Enable bit
1 = CCP1 is enabled as a falling event input
0 = CCP1 has no effect on the falling event
bit 3 GxFIS3: COGx Falling Event Input Source 3 Enable bit
1 = CLC1 output is enabled as a falling event input
0 = CLC1 output has no effect on the falling event
bit 2 GxFIS2: COGx Falling Event Input Source 2 Enable bit
1 = Comparator 2 output is enabled as a falling event input
0 = Comparator 2 output has no effect on the falling event
bit 1 GxFIS1: COGx Falling Event Input Source 1 Enable bit
1 = Comparator 1 output is enabled as a falling event input
0 = Comparator 1 output has no effect on the falling event
bit 0 GxFIS0: COGx Falling Event Input Source 0 Enable bit
1 = Pin selected with COGxPPS control register is enabled as falling event input
0 = Pin selected with COGxPPS control has no effect on the falling event

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REGISTER 18-6: COGxFSIM: COG FALLING EVENT SOURCE INPUT MODE REGISTER
U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— GxFSIM6 GxFSIM5 GxFSIM4 GxFSIM3 GxFSIM2 GxFSIM1 GxFSIM0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7 Unimplemented: Read as ‘0’

bit 6 GxFSIM6: COGx Falling Event Input Source 6 Mode bit
GxFIS6 = 1:
1 = PWM3 output high-to-low transition will cause a falling event after falling event phase delay
0 = PWM3 output low level will cause an immediate falling event
GxFIS6 = 0:
PWM3 output has no effect on falling event
bit 5 GxFSIM5: COGx Falling Event Input Source 5 Mode bit
GxFIS5 = 1:
1 = CCP2 output high-to-low transition will cause a falling event after falling event phase delay
0 = CCP2 output low level will cause an immediate falling event
GxFIS5 = 0:
CCP2 output has no effect on falling event
bit 4 GxFSIM4: COGx Falling Event Input Source 4 Mode bit
GxFIS4 = 1:
1 = CCP1 high-to-low transition will cause a falling event after falling event phase delay
0 = CCP1 low level will cause an immediate falling event
GxFIS4 = 0:
CCP1 has no effect on falling event
bit 3 GxFSIM3: COGx Falling Event Input Source 3 Mode bit
GxFIS3 = 1:
1 = CLC1 output high-to-low transition will cause a falling event after falling event phase delay
0 = CLC1 output low level will cause an immediate falling event
GxFIS3 = 0:
CLC1 output has no effect on falling event
bit 2 GxFSIM2: COGx Falling Event Input Source 2 Mode bit
GxFIS2 = 1:
1 = Comparator 2 high-to-low transition will cause a falling event after falling event phase delay
0 = Comparator 2 low level will cause an immediate falling event
GxFIS2 = 0:
Comparator 2 has no effect on falling event
bit 1 GxFSIM1: COGx Falling Event Input Source 1 Mode bit
GxFIS1 = 1:
1 = Comparator 1 high-to-low transition will cause a falling event after falling event phase delay
0 = Comparator 1 low level will cause an immediate falling event
GxFIS1 = 0:
Comparator 1 has no effect on falling event
bit 0 GxFSIM0: COGx Falling Event Input Source 0 Mode bit
GxFIS0 = 1:
1 = Pin selected with COGxPPS control high-to-low transition will cause a falling event after falling event
phase delay
0 = Pin selected with COGxPPS control low level will cause an immediate falling event
GxFIS0 = 0:
Pin selected with COGxPPS control has no effect on falling event

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REGISTER 18-7: COGxASD0: COG AUTO-SHUTDOWN CONTROL REGISTER 0

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0
GxASE GxARSEN GxASDBD<1:0> GxASDAC<1:0> — —
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7 GxASE: Auto-Shutdown Event Status bit

1 = COG is in the shutdown state
0 = COG is either not in the shutdown state or will exit the shutdown state on the next rising event
bit 6 GxARSEN: Auto-Restart Enable bit
1 = Auto-restart is enabled
0 = Auto-restart is disabled
bit 5-4 GxASDBD<1:0>: COGxB and COGxD Auto-shutdown Override Level Select bits
11 = A logic ‘1’ is placed on COGxB and COGxD when shutdown is active
10 = A logic ‘0’ is placed on COGxB and COGxD when shutdown is active
01 = COGxB and COGxD are tri-stated when shutdown is active
00 = The inactive state of the pin, including polarity, is placed on COGxB and COGxD when shutdown
is active
bit 3-2 GxASDAC<1:0>: COGxA and COGxC Auto-shutdown Override Level Select bits
11 = A logic ‘1’ is placed on COGxA and COGxC when shutdown is active
10 = A logic ‘0’ is placed on COGxA and COGxC when shutdown is active
01 = COGxA and COGxC are tri-stated when shutdown is active
00 = The inactive state of the pin, including polarity, is placed on COGxA and COGxC when shutdown
is active
bit 1-0 Unimplemented: Read as ‘0’

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REGISTER 18-8: COGxASD1: COG AUTO-SHUTDOWN CONTROL REGISTER 1

U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — — — GxAS3E GxAS2E GxAS1E GxAS0E
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7-4 Unimplemented: Read as ‘0’

bit 3 GxAS3E: COGx Auto-shutdown Source Enable bit 3
1 = COGx is shutdown when CLC2 output is low
0 = CLC2 output has no effect on shutdown
bit 2 GxAS2E: COGx Auto-shutdown Source Enable bit 2
1 = COGx is shutdown when Comparator 2 output is low
0 = Comparator 2 output has no effect on shutdown
bit 1 GxAS1E: COGx Auto-shutdown Source Enable bit 1
1 = COGx is shutdown when Comparator 1 output is low
0 = Comparator 1 output has no effect on shutdown
bit 0 GxAS0E: COGx Auto-shutdown Source Enable bit 0
1 = COGx is shutdown when Pin selected with COGxPPS control is low
0 = Pin selected with COGxPPS control has no effect on shutdown

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REGISTER 18-9: COGxSTR: COG STEERING CONTROL REGISTER 1

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
GxSDATD GxSDATC GxSDATB GxSDATA GxSTRD GxSTRC GxSTRB GxSTRA
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7 GxSDATD: COGxD Static Output Data bit

1 = COGxD static data is high
0 = COGxD static data is low
bit 6 GxSDATC: COGxC Static Output Data bit
1 = COGxC static data is high
0 = COGxC static data is low
bit 5 GxSDATB: COGxB Static Output Data bit
1 = COGxB static data is high
0 = COGxB static data is low
bit 4 GxSDATA: COGxA Static Output Data bit
1 = COGxA static data is high
0 = COGxA static data is low
bit 3 GxSTRD: COGxD Steering Control bit
1 = COGxD output has the COGxD waveform with polarity control from GxPOLD bit
0 = COGxD output is the static data level determined by the GxSDATD bit
bit 2 GxSTRC: COGxC Steering Control bit
1 = COGxC output has the COGxC waveform with polarity control from GxPOLC bit
0 = COGxC output is the static data level determined by the GxSDATC bit
bit 1 GxSTRB: COGxB Steering Control bit
1 = COGxB output has the COGxB waveform with polarity control from GxPOLB bit
0 = COGxB output is the static data level determined by the GxSDATB bit
bit 0 GxSTRA: COGxA Steering Control bit
1 = COGxA output has the COGxA waveform with polarity control from GxPOLA bit
0 = COGxA output is the static data level determined by the GxSDATA bit

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REGISTER 18-10: COGxDBR: COG RISING EVENT DEAD-BAND COUNT REGISTER

U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
GxDBR<5:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 GxDBR<5:0>: Rising Event Dead-band Count Value bits
GxRDBS = 0:
= Number of COGx clock periods to delay primary output after rising event
GxRDBS = 1:
= Number of delay chain element periods to delay primary output after rising event

REGISTER 18-11: COGxDBF: COG FALLING EVENT DEAD-BAND COUNT REGISTER

U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
GxDBF<5:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 GxDBF<5:0>: Falling Event Dead-band Count Value bits
GxFDBS = 0:
= Number of COGx clock periods to delay complementary output after falling event input
GxFDBS = 1:
= Number of delay chain element periods to delay complementary output after falling event input

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REGISTER 18-12: COGxBLKR: COG RISING EVENT BLANKING COUNT REGISTER

U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
GxBLKR<5:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 GxBLKR<5:0>: Rising Event Blanking Count Value bits
= Number of COGx clock periods to inhibit falling event inputs

REGISTER 18-13: COGxBLKF: COG FALLING EVENT BLANKING COUNT REGISTER

U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
GxBLKF<5:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 GxBLKF<5:0>: Falling Event Blanking Count Value bits
= Number of COGx clock periods to inhibit rising event inputs

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REGISTER 18-14: COGxPHR: COG RISING EDGE PHASE DELAY COUNT REGISTER
U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
— — GxPHR<5:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 GxPHR<5:0>: Rising Edge Phase Delay Count Value bits
= Number of COGx clock periods to delay rising edge event

REGISTER 18-15: COGxPHF: COG FALLING EDGE PHASE DELAY COUNT REGISTER
U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
— — GxPHF<5:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 GxPHF<5:0>: Falling Edge Phase Delay Count Value bits
= Number of COGx clock periods to delay falling edge event

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TABLE 18-2: SUMMARY OF REGISTERS ASSOCIATED WITH COG
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page

ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 122

ANSELB(1) — — ANSB5 ANSB4 — — — — 128
ANSELC ANSC7(1) ANSC6(1) ANSC5(2) ANSC4(2) ANSC3 ANSC2 ANSC1 ANSC0 133
COG1PHR — — G1PHR<5:0> 199
COG1PHF — — G1PHF<5:0> 199
COG1BLKR — — G1BLKR<5:0> 198
COG1BLKF — — G1BLKF<5:0> 198
COG1DBR — — G1DBR<5:0> 197
COG1DBF — — G1DBF<5:0> 197
COG1RIS — G1RIS6 G1RIS5 G1RIS4 G1RIS3 G1RIS2 G1RIS1 G1RIS0 190
COG1RSIM — G1RSIM6 G1RSIM5 G1RSIM4 G1RSIM3 G1RSIM2 G1RSIM1 G1RSIM0 191
COG1FIS — G1FIS6 G1FIS5 G1FIS4 G1FIS3 G1FIS2 G1FIS1 G1FIS0 192
COG1FSIM — G1FSIM6 G1FSIM5 G1FSIM4 G1FSIM3 G1FSIM2 G1FSIM1 G1FSIM0 193
COG1CON0 G1EN G1LD — G1CS<1:0> G1MD<2:0> 188
COG1CON1 G1RDBS G1FDBS — — G1POLD G1POLC G1POLB G1POLA 189
COG1ASD0 G1ASE G1ARSEN G1ASDBD<1:0> G1ASDAC<1:0> — — 194
COG1ASD1 — — — — G1AS3E G1AS2E G1AS1E G1AS0E 195
COG1STR G1SDATD G1SDATC G1SDATB G1SDATA G1STRD G1STRC G1STRB G1STRA 196
INTCON GIE PEIE T0IE INTE IOCIE T0IF INTF IOCIF 85
COG1PPS — — — COG1PPS<4:0> 139
PIE2 OSFIE C2IE C1IE — BCL1IE TMR6IE TMR4IE CCP2IE 87
PIR2 OSFIF C2IF C1IF — BCL1IF TMR6IF TMR4IF CCP2IF 90
RxyPPS — — — RxyPPS<4:0> 140
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by COG.
Note 1: PIC16(L)F1708 only.
2: PIC16(L)F1704 only.

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19.0 CONFIGURABLE LOGIC CELL Refer to Figure 19-1 for a simplified diagram showing
signal flow through the CLCx.
(CLC)
Possible configurations include:
The Configurable Logic Cell (CLCx) provides
programmable logic that operates outside the speed • Combinatorial Logic
limitations of software execution. The logic cell takes up - AND
to 32 input signals and, through the use of configurable - NAND
gates, reduces the 32 inputs to four logic lines that drive - AND-OR
one of eight selectable single-output logic functions. - AND-OR-INVERT
Input sources are a combination of the following: - OR-XOR
• I/O pins - OR-XNOR
• Internal clocks • Latches
• Peripherals - S-R
• Register bits - Clocked D with Set and Reset
The output can be directed internally to peripherals and - Transparent D with Set and Reset
to an output pin. - Clocked J-K with Reset

FIGURE 19-1: CLCx SIMPLIFIED BLOCK DIAGRAM

LCxOUT
D Q
MLCxOUT

Q1
LCx_in[0]
LCx_in[1]
to Peripherals
LCx_in[2]
Input Data Selection Gates(1)

. lcxg1
LCxEN

. lcxg2

lcxg3
Logic
Function
(2)
lcxq LCx_out PPS
Module
CLCx

. lcxg4
LCxPOL

LCx_in[29] LCxMODE<2:0> Interrupt

LCx_in[30] det
LCx_in[31]
LCXINTP
set bit
LCXINTN CLCxIF
Interrupt
det

Note 1: See Figure 19-2: Input Data Selection and Gating.

2: See Figure 19-3: Programmable Logic Functions.

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19.1 CLCx Setup TABLE 19-1: CLCx DATA INPUT SELECTION
Programming the CLCx module is performed by lcxdy
Data Input CLCx
configuring the four stages in the logic signal flow. The DxS
four stages are: LCx_in[31] 11111 FOSC
• Data selection LCx_in[30] 11110 HFINTOSC
• Data gating LCx_in[29] 11101 LFINTOSC
• Logic function selection LCx_in[28] 11100 ADC FRC
• Output polarity
LCx_in[27] 11011 IOCIF set signal (bit?)
Each stage is setup at run time by writing to the LCx_in[26] 11010 T2_match
corresponding CLCx Special Function Registers. This
has the added advantage of permitting logic LCx_in[25] 11001 T1_overflow
reconfiguration on-the-fly during program execution. LCx_in[24] 11000 T0_overflow
LCx_in[23] 10111 T6_match
19.1.1 DATA SELECTION
LCx_in[22] 10110 T4_match
There are 32 signals available as inputs to the
LCx_in[21] 10101 DT from EUSART
configurable logic. Four 32-input multiplexers are used
to select the inputs to pass on to the next stage. LCx_in[20] 10100 TX/CK from EUSART
Data selection is through four multiplexers as indicated LCx_in[19] 10011 ZCDx_out from Zero-Cross Detect
on the left side of Figure 19-2. Data inputs in the figure LCx_in[18] 10010 SDO from MSSP
are identified by a generic numbered input name. LCx_in[17] 10001 Reserved
Table 19-1 correlates the generic input name to the LCx_in[16] 10000 SCK from MSSP
actual signal for each CLC module. The column labeled LCx_in[15] 01111 PWM4_out
lcxdy indicates the MUX selection code for the selected
data input. DxS is an abbreviation for the MUX select LCx_in[14] 01110 PWM3_out
input codes: LCxD1S<4:0> through LCxD4S<4:0>. LCx_in[13] 01101 CCP2 output
Data inputs are selected with CLCxSEL0 through LCx_in[12] 01100 CCP1 output
CLCxSEL3 registers (Register 19-3 through LCx_in[11] 01011 COG1B
Register 19-6). LCx_in[10] 01010 COG1A
Note: Data selections are undefined at power-up. LCx_in[9] 01001 C2OUT
LCx_in[8] 01000 C1OUT
LCx_in[7] 00111 Reserved
LCx_in[6] 00110 LC3_out from the CLC3
LCx_in[5] 00101 LC2_out from the CLC2
LCx_in[4] 00100 LC1_out from the CLC1
LCx_in[3] 00011 CLCIN3 pin input selected in
CLCIN3PPS register
LCx_in[2] 00010 CLCIN2 pin input selected in
CLCIN2PPS register
LCx_in[1] 00001 CLCIN1 pin input selected in
CLCIN1PPS register
LCx_in[0] 00000 CLCIN0 pin input selected in
CLCIN0PPS register

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19.1.2 DATA GATING Data gating is indicated in the right side of Figure 19-2.
Only one gate is shown in detail. The remaining three
Outputs from the input multiplexers are directed to the
gates are configured identically with the exception that
desired logic function input through the data gating
the data enables correspond to the enables for that
stage. Each data gate can direct any combination of the
gate.
four selected inputs.
Note: Data gating is undefined at power-up. 19.1.3 LOGIC FUNCTION
The gate stage is more than just signal direction. The There are eight available logic functions including:
gate can be configured to direct each input signal as • AND-OR
inverted or non-inverted data. Directed signals are • OR-XOR
ANDed together in each gate. The output of each gate
• AND
can be inverted before going on to the logic function
stage. • S-R Latch
• D Flip-Flop with Set and Reset
The gating is in essence a 1-to-4 input
AND/NAND/OR/NOR gate. When every input is • D Flip-Flop with Reset
inverted and the output is inverted, the gate is an OR of • J-K Flip-Flop with Reset
all enabled data inputs. When the inputs and output are • Transparent Latch with Set and Reset
not inverted, the gate is an AND or all enabled inputs. Logic functions are shown in Figure 19-3. Each logic
Table 19-2 summarizes the basic logic that can be function has four inputs and one output. The four inputs
obtained in gate 1 by using the gate logic select bits. are the four data gate outputs of the previous stage.
The table shows the logic of four input variables, but The output is fed to the inversion stage and from there
to other peripherals, an output pin, and back to the
each gate can be configured to use less than four. If
CLCx itself.
no inputs are selected, the output will be zero or one,
depending on the gate output polarity bit. 19.1.4 OUTPUT POLARITY
TABLE 19-2: DATA GATING LOGIC The last stage in the configurable logic cell is the output
polarity. Setting the LCxPOL bit of the CLCxCON
CLCxGLS0 LCxG1POL Gate Logic register inverts the output signal from the logic stage.
0x55 1 AND Changing the polarity while the interrupts are enabled
will cause an interrupt for the resulting output transition.
0x55 0 NAND
0xAA 1 NOR
0xAA 0 OR
0x00 0 Logic 0
0x00 1 Logic 1

It is possible (but not recommended) to select both the

true and negated values of an input. When this is done,
the gate output is zero, regardless of the other inputs,
but may emit logic glitches (transient-induced pulses).
If the output of the channel must be zero or one, the
recommended method is to set all gate bits to zero and
use the gate polarity bit to set the desired level.
Data gating is configured with the logic gate select
registers as follows:
• Gate 1: CLCxGLS0 (Register 19-7)
• Gate 2: CLCxGLS1 (Register 19-8)
• Gate 3: CLCxGLS2 (Register 19-9)
• Gate 4: CLCxGLS3 (Register 19-10)
Register number suffixes are different than the gate
numbers because other variations of this module have
multiple gate selections in the same register.

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19.1.5 CLCx SETUP STEPS 19.2 CLCx Interrupts
The following steps should be followed when setting up An interrupt will be generated upon a change in the
the CLCx: output value of the CLCx when the appropriate interrupt
• Disable CLCx by clearing the LCxEN bit. enables are set. A rising edge detector and a falling
• Select desired inputs using CLCxSEL0 through edge detector are present in each CLC for this purpose.
CLCxSEL3 registers (See Table 19-1). The CLCxIF bit of the associated PIR registers will be
• Clear any associated ANSEL bits. set when either edge detector is triggered and its
• Set all TRIS bits associated with inputs. associated enable bit is set. The LCxINTP enables
• Clear all TRIS bits associated with outputs. rising edge interrupts and the LCxINTN bit enables
falling edge interrupts. Both are located in the
• Enable the chosen inputs through the four gates
CLCxCON register.
using CLCxGLS0, CLCxGLS1, CLCxGLS2, and
CLCxGLS3 registers. To fully enable the interrupt, set the following bits:
• Select the gate output polarities with the • LCxON bit of the CLCxCON register
LCxPOLy bits of the CLCxPOL register. • CLCxIE bit of the associated PIE registers
• Select the desired logic function with the • LCxINTP bit of the CLCxCON register (for a rising
LCxMODE<2:0> bits of the CLCxCON register. edge detection)
• Select the desired polarity of the logic output with • LCxINTN bit of the CLCxCON register (for a
the LCxPOL bit of the CLCxPOL register. (This falling edge detection)
step may be combined with the previous gate out-
• PEIE and GIE bits of the INTCON register
put polarity step).
• If driving a device pin, set the desired pin PPS The CLCxIF bit of the associated PIR registers, must
control register and also clear the TRIS bit be cleared in software as part of the interrupt service. If
corresponding to that output. another edge is detected while this flag is being
cleared, the flag will still be set at the end of the
• If interrupts are desired, configure the following
sequence.
bits:
- Set the LCxINTP bit in the CLCxCON register
19.3 Output Mirror Copies
for rising event.
- Set the LCxINTN bit in the CLCxCON Mirror copies of all LCxCON output bits are contained
register for falling event. in the CLCxDATA register. Reading this register reads
- Set the CLCxIE bit of the associated PIE the outputs of all CLCs simultaneously. This prevents
registers. any reading skew introduced by testing or reading the
CLCxOUT bits in the individual CLCxCON registers.
- Set the GIE and PEIE bits of the INTCON
register.
• Enable the CLCx by setting the LCxEN bit of the
19.4 Effects of a Reset
CLCxCON register. The CLCxCON register is cleared to zero as the result
of a Reset. All other selection and gating values remain
unchanged.

19.5 Operation During Sleep

The CLC module operates independently from the
system clock and will continue to run during Sleep,
provided that the input sources selected remain active.
The HFINTOSC remains active during Sleep when the
CLC module is enabled and the HFINTOSC is
selected as an input source, regardless of the system
clock source selected.
In other words, if the HFINTOSC is simultaneously
selected as the system clock and as a CLC input
source, when the CLC is enabled, the CPU will go idle
during Sleep, but the CLC will continue to operate and
the HFINTOSC will remain active.
This will have a direct effect on the Sleep mode current.

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FIGURE 19-2: INPUT DATA SELECTION AND GATING

Data Selection
LCx_in[0] 00000

Data GATE 1

lcxd1T LCxD1G1T

lcxd1N LCxD1G1N
LCx_in[31] 11111
LCxD2G1T
LCxD1S<4:0>

LCxD2G1N lcxg1
LCx_in[0] 00000
LCxD3G1T
LCxG1POL
lcxd2T
LCxD3G1N
lcxd2N
LCxD4G1T
LCx_in[31] 11111

LCxD2S<4:0> LCxD4G1N

LCx_in[0] 00000
Data GATE 2
lcxg2
lcxd3T
(Same as Data GATE 1)
lcxd3N
Data GATE 3
LCx_in[31] 11111
lcxg3
LCxD3S<4:0>
(Same as Data GATE 1)

LCx_in[0] 00000 Data GATE 4

lcxg4

lcxd4T (Same as Data GATE 1)

lcxd4N

LCx_in[31] 11111

LCxD4S<4:0>

Note: All controls are undefined at power-up.

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FIGURE 19-3: PROGRAMMABLE LOGIC FUNCTIONS
AND - OR OR - XOR

lcxg1 lcxg1
lcxg2 lcxg2
lcxq lcxq
lcxg3 lcxg3
lcxg4 lcxg4

LCxMODE<2:0>= 000 LCxMODE<2:0>= 001

4-Input AND S-R Latch

lcxg1 lcxg1
S Q lcxq
lcxg2 lcxg2
lcxq
lcxg3 lcxg3
R
lcxg4 lcxg4

LCxMODE<2:0>= 010 LCxMODE<2:0>= 011

1-Input D Flip-Flop with S and R 2-Input D Flip-Flop with R

lcxg4
lcxg4
S D Q lcxq
lcxg2 D Q lcxq lcxg2

lcxg1
lcxg1 R
R
lcxg3
lcxg3

LCxMODE<2:0>= 100 LCxMODE<2:0>= 101

J-K Flip-Flop with R 1-Input Transparent Latch with S and R

lcxg4
lcxg2 J Q lcxq
S
lcxg1 lcxg2 D Q lcxq

lcxg4 K
R
lcxg1 LE
R
lcxg3
lcxg3
LCxMODE<2:0>= 110 LCxMODE<2:0>= 111

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19.6 Register Definitions: CLC Control

REGISTER 19-1: CLCxCON: CONFIGURABLE LOGIC CELL CONTROL REGISTER

R/W-0/0 U-0 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
LCxEN — LCxOUT LCxINTP LCxINTN LCxMODE<2:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 LCxEN: Configurable Logic Cell Enable bit

1 = Configurable logic cell is enabled and mixing input signals
0 = Configurable logic cell is disabled and has logic zero output
bit 6 Unimplemented: Read as ‘0’
bit 5 LCxOUT: Configurable Logic Cell Data Output bit
Read-only: logic cell output data, after LCxPOL; sampled from lcx_out wire.
bit 4 LCxINTP: Configurable Logic Cell Positive Edge Going Interrupt Enable bit
1 = CLCxIF will be set when a rising edge occurs on lcx_out
0 = CLCxIF will not be set
bit 3 LCxINTN: Configurable Logic Cell Negative Edge Going Interrupt Enable bit
1 = CLCxIF will be set when a falling edge occurs on lcx_out
0 = CLCxIF will not be set
bit 2-0 LCxMODE<2:0>: Configurable Logic Cell Functional Mode bits
111 = Cell is 1-input transparent latch with S and R
110 = Cell is J-K flip-flop with R
101 = Cell is 2-input D flip-flop with R
100 = Cell is 1-input D flip-flop with S and R
011 = Cell is S-R latch
010 = Cell is 4-input AND
001 = Cell is OR-XOR
000 = Cell is AND-OR

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REGISTER 19-2: CLCxPOL: SIGNAL POLARITY CONTROL REGISTER

R/W-0/0 U-0 U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u
LCxPOL — — — LCxG4POL LCxG3POL LCxG2POL LCxG1POL
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 LCxPOL: LCOUT Polarity Control bit

1 = The output of the logic cell is inverted
0 = The output of the logic cell is not inverted
bit 6-4 Unimplemented: Read as ‘0’
bit 3 LCxG4POL: Gate 4 Output Polarity Control bit
1 = The output of gate 4 is inverted when applied to the logic cell
0 = The output of gate 4 is not inverted
bit 2 LCxG3POL: Gate 3 Output Polarity Control bit
1 = The output of gate 3 is inverted when applied to the logic cell
0 = The output of gate 3 is not inverted
bit 1 LCxG2POL: Gate 2 Output Polarity Control bit
1 = The output of gate 2 is inverted when applied to the logic cell
0 = The output of gate 2 is not inverted
bit 0 LCxG1POL: Gate 1 Output Polarity Control bit
1 = The output of gate 1 is inverted when applied to the logic cell
0 = The output of gate 1 is not inverted

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REGISTER 19-3: CLCxSEL0: GENERIC CLCx DATA 1 SELECT REGISTER

U-0 U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
— — — LCxD1S<4:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 LCxD1S<4:0>: CLCx Data1 Input Selection bits
See Table 19-1.

REGISTER 19-4: CLCxSEL1: GENERIC CLCx DATA 2 SELECT REGISTER

U-0 U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
— — — LCxD2S<4:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 LCxD2S<4:0>: CLCx Data 2 Input Selection bits
See Table 19-1.

REGISTER 19-5: CLCxSEL2: GENERIC CLCx DATA 3 SELECT REGISTER

U-0 U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
— — — LCxD3S<4:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 LCxD3S<4:0>: CLCx Data 3 Input Selection bits
See Table 19-1.

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REGISTER 19-6: CLCxSEL3: GENERIC CLCx DATA 4 SELECT REGISTER

U-0 U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
— — — LCxD4S<4:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 LCxD4S<4:0>: CLCx Data 4 Input Selection bits
See Table 19-1.

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REGISTER 19-7: CLCxGLS0: GATE 1 LOGIC SELECT REGISTER

R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
LCxG1D4T LCxG1D4N LCxG1D3T LCxG1D3N LCxG1D2T LCxG1D2N LCxG1D1T LCxG1D1N
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 LCxG1D4T: Gate 1 Data 4 True (non-inverted) bit

1 = lcxd4T is gated into lcxg1
0 = lcxd4T is not gated into lcxg1
bit 6 LCxG1D4N: Gate 1 Data 4 Negated (inverted) bit
1 = lcxd4N is gated into lcxg1
0 = lcxd4N is not gated into lcxg1
bit 5 LCxG1D3T: Gate 1 Data 3 True (non-inverted) bit
1 = lcxd3T is gated into lcxg1
0 = lcxd3T is not gated into lcxg1
bit 4 LCxG1D3N: Gate 1 Data 3 Negated (inverted) bit
1 = lcxd3N is gated into lcxg1
0 = lcxd3N is not gated into lcxg1
bit 3 LCxG1D2T: Gate 1 Data 2 True (non-inverted) bit
1 = lcxd2T is gated into lcxg1
0 = lcxd2T is not gated into lcxg1
bit 2 LCxG1D2N: Gate 1 Data 2 Negated (inverted) bit
1 = lcxd2N is gated into lcxg1
0 = lcxd2N is not gated into lcxg1
bit 1 LCxG1D1T: Gate 1 Data 1 True (non-inverted) bit
1 = lcxd1T is gated into lcxg1
0 = lcxd1T is not gated into lcxg1
bit 0 LCxG1D1N: Gate 1 Data 1 Negated (inverted) bit
1 = lcxd1N is gated into lcxg1
0 = lcxd1N is not gated into lcxg1

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REGISTER 19-8: CLCxGLS1: GATE 2 LOGIC SELECT REGISTER

R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
LCxG2D4T LCxG2D4N LCxG2D3T LCxG2D3N LCxG2D2T LCxG2D2N LCxG2D1T LCxG2D1N
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 LCxG2D4T: Gate 2 Data 4 True (non-inverted) bit

1 = lcxd4T is gated into lcxg2
0 = lcxd4T is not gated into lcxg2
bit 6 LCxG2D4N: Gate 2 Data 4 Negated (inverted) bit
1 = lcxd4N is gated into lcxg2
0 = lcxd4N is not gated into lcxg2
bit 5 LCxG2D3T: Gate 2 Data 3 True (non-inverted) bit
1 = lcxd3T is gated into lcxg2
0 = lcxd3T is not gated into lcxg2
bit 4 LCxG2D3N: Gate 2 Data 3 Negated (inverted) bit
1 = lcxd3N is gated into lcxg2
0 = lcxd3N is not gated into lcxg2
bit 3 LCxG2D2T: Gate 2 Data 2 True (non-inverted) bit
1 = lcxd2T is gated into lcxg2
0 = lcxd2T is not gated into lcxg2
bit 2 LCxG2D2N: Gate 2 Data 2 Negated (inverted) bit
1 = lcxd2N is gated into lcxg2
0 = lcxd2N is not gated into lcxg2
bit 1 LCxG2D1T: Gate 2 Data 1 True (non-inverted) bit
1 = lcxd1T is gated into lcxg2
0 = lcxd1T is not gated into lcxg2
bit 0 LCxG2D1N: Gate 2 Data 1 Negated (inverted) bit
1 = lcxd1N is gated into lcxg2
0 = lcxd1N is not gated into lcxg2

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REGISTER 19-9: CLCxGLS2: GATE 3 LOGIC SELECT REGISTER

R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
LCxG3D4T LCxG3D4N LCxG3D3T LCxG3D3N LCxG3D2T LCxG3D2N LCxG3D1T LCxG3D1N
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 LCxG3D4T: Gate 3 Data 4 True (non-inverted) bit

1 = lcxd4T is gated into lcxg3
0 = lcxd4T is not gated into lcxg3
bit 6 LCxG3D4N: Gate 3 Data 4 Negated (inverted) bit
1 = lcxd4N is gated into lcxg3
0 = lcxd4N is not gated into lcxg3
bit 5 LCxG3D3T: Gate 3 Data 3 True (non-inverted) bit
1 = lcxd3T is gated into lcxg3
0 = lcxd3T is not gated into lcxg3
bit 4 LCxG3D3N: Gate 3 Data 3 Negated (inverted) bit
1 = lcxd3N is gated into lcxg3
0 = lcxd3N is not gated into lcxg3
bit 3 LCxG3D2T: Gate 3 Data 2 True (non-inverted) bit
1 = lcxd2T is gated into lcxg3
0 = lcxd2T is not gated into lcxg3
bit 2 LCxG3D2N: Gate 3 Data 2 Negated (inverted) bit
1 = lcxd2N is gated into lcxg3
0 = lcxd2N is not gated into lcxg3
bit 1 LCxG3D1T: Gate 3 Data 1 True (non-inverted) bit
1 = lcxd1T is gated into lcxg3
0 = lcxd1T is not gated into lcxg3
bit 0 LCxG3D1N: Gate 3 Data 1 Negated (inverted) bit
1 = lcxd1N is gated into lcxg3
0 = lcxd1N is not gated into lcxg3

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REGISTER 19-10: CLCxGLS3: GATE 4 LOGIC SELECT REGISTER

R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
LCxG4D4T LCxG4D4N LCxG4D3T LCxG4D3N LCxG4D2T LCxG4D2N LCxG4D1T LCxG4D1N
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 LCxG4D4T: Gate 4 Data 4 True (non-inverted) bit

1 = lcxd4T is gated into lcxg4
0 = lcxd4T is not gated into lcxg4
bit 6 LCxG4D4N: Gate 4 Data 4 Negated (inverted) bit
1 = lcxd4N is gated into lcxg4
0 = lcxd4N is not gated into lcxg4
bit 5 LCxG4D3T: Gate 4 Data 3 True (non-inverted) bit
1 = lcxd3T is gated into lcxg4
0 = lcxd3T is not gated into lcxg4
bit 4 LCxG4D3N: Gate 4 Data 3 Negated (inverted) bit
1 = lcxd3N is gated into lcxg4
0 = lcxd3N is not gated into lcxg4
bit 3 LCxG4D2T: Gate 4 Data 2 True (non-inverted) bit
1 = lcxd2T is gated into lcxg4
0 = lcxd2T is not gated into lcxg4
bit 2 LCxG4D2N: Gate 4 Data 2 Negated (inverted) bit
1 = lcxd2N is gated into lcxg4
0 = lcxd2N is not gated into lcxg4
bit 1 LCxG4D1T: Gate 4 Data 1 True (non-inverted) bit
1 = lcxd1T is gated into lcxg4
0 = lcxd1T is not gated into lcxg4
bit 0 LCxG4D1N: Gate 4 Data 1 Negated (inverted) bit
1 = lcxd1N is gated into lcxg4
0 = lcxd1N is not gated into lcxg4

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REGISTER 19-11: CLCDATA: CLC DATA OUTPUT

U-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0
— — — — — MLC3OUT MLC2OUT MLC1OUT
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-3 Unimplemented: Read as ‘0’

bit 2 MLC3OUT: Mirror copy of LC3OUT bit
bit 1 MLC2OUT: Mirror copy of LC2OUT bit
bit 0 MLC1OUT: Mirror copy of LC1OUT bit

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TABLE 19-3: SUMMARY OF REGISTERS ASSOCIATED WITH CLCx

Register
Name Bit7 Bit6 Bit5 Bit4 BIt3 Bit2 Bit1 Bit0
on Page

ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 122

ANSELB(1) — — ANSB5 ANSB4 — — — — 128
ANSELC ANSC7(1) ANSC6(1) ANSC5(2) ANSC4(2) ANSC3 ANSC2 ANSC1 ANSC0 133
CLC1CON LC1EN — LC1OUT LC1INTP LC1INTN LC1MODE<2:0> 207
CLC2CON LC2EN — LC2OUT LC2INTP LC2INTN LC2MODE<2:0> 207
CLC3CON LC3EN — LC3OUT LC3INTP LC3INTN LC3MODE<2:0> 207
CLCDATA — — — — — MLC3OUT MLC2OUT MLC1OUT 215
CLC1GLS0 LC1G1D4T LC1G1D4N LC1G1D3T LC1G1D3N LC1G1D2T LC1G1D2N LC1G1D1T LC1G1D1N 211
CLC1GLS1 LC1G2D4T LC1G2D4N LC1G2D3T LC1G2D3N LC1G2D2T LC1G2D2N LC1G2D1T LC1G2D1N 212
CLC1GLS2 LC1G3D4T LC1G3D4N LC1G3D3T LC1G3D3N LC1G3D2T LC1G3D2N LC1G3D1T LC1G3D1N 213
CLC1GLS3 LC1G4D4T LC1G4D4N LC1G4D3T LC1G4D3N LC1G4D2T LC1G4D2N LC1G4D1T LC1G4D1N 214
CLC1POL LC1POL — — — LC1G4POL LC1G3POL LC1G2POL LC1G1POL 208
CLC1SEL0 — — — LC1D1S<4:0> 209
CLC1SEL1 — — — LC1D2S<4:0> 209
CLC1SEL2 — — — LC1D3S<4:0> 209
CLC1SEL3 — — — LC1D4S<4:0> 210
CLC2GLS0 LC2G1D4T LC2G1D4N LC2G1D3T LC2G1D3N LC2G1D2T LC2G1D2N LC2G1D1T LC2G1D1N 211
CLC2GLS1 LC2G2D4T LC2G2D4N LC2G2D3T LC2G2D3N LC2G2D2T LC2G2D2N LC2G2D1T LC2G2D1N 212
CLC2GLS2 LC2G3D4T LC2G3D4N LC2G3D3T LC2G3D3N LC2G3D2T LC2G3D2N LC2G3D1T LC2G3D1N 213
CLC2GLS3 LC2G4D4T LC2G4D4N LC2G4D3T LC2G4D3N LC2G4D2T LC2G4D2N LC2G4D1T LC2G4D1N 214
CLC2POL LC2POL — — — LC2G4POL LC2G3POL LC2G2POL LC2G1POL 208
CLC2SEL0 — — — LC2D1S<4:0> 209
CLC2SEL1 — — — LC2D2S<4:0> 209
CLC2SEL2 — — — LC2D3S<4:0> 209
CLC2SEL3 — — — LC2D4S<4:0> 210
CLC3GLS0 LC3G1D4T LC3G1D4N LC3G1D3T LC3G1D3N LC3G1D2T LC3G1D2N LC3G1D1T LC3G1D1N 211
CLC3GLS1 LC3G2D4T LC3G2D4N LC3G2D3T LC3G2D3N LC3G2D2T LC3G2D2N LC3G2D1T LC3G2D1N 212
CLC3GLS2 LC3G3D4T LC3G3D4N LC3G3D3T LC3G3D3N LC3G3D2T LC3G3D2N LC3G3D1T LC3G3D1N 213
CLC3GLS3 LC3G4D4T LC3G4D4N LC3G4D3T LC3G4D3N LC3G4D2T LC3G4D2N LC3G4D1T LC3G4D1N 214
CLC3POL LC3POL — — — LC3G4POL LC3G3POL LC3G2POL LC3G1POL 208
CLC3SEL0 — — — LC3D1S<4:0> 209
CLC3SEL1 — — — LC3D2S<4:0> 209
CLC3SEL2 — — — LC3D3S<4:0> 209
CLC3SEL3 — — — LC3D4S<4:0> 210
CLCxPPS — — — CLCxPPS<4:0> 138, 139
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 85
PIE3 — — COGIE ZCDIE — CLC3IE CLC2IE CLC1IE 88
PIR3 — — COGIF ZCDIF — CLC3IF CLC2IF CLC1IF 91
RxyPPS — — — RxyPPS<4:0> 140
TRISA — — TRISA5 TRISA4 —(3) TRISA2 TRISA1 TRISA0 121
TRISB(4) TRISB7 TRISB6 TRISB5 TRISB4 — — — — 127
TRISC TRISC7(4) TRISC6(4) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 132
Legend: — = unimplemented read as ‘0’. Shaded cells are not used for CLC module.
Note 1: PIC16(L)F1708 only.
2: PIC16(L)F1704 only.
3: Unimplemented, read as ‘1’.

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20.0 ANALOG-TO-DIGITAL
CONVERTER (ADC) MODULE
The Analog-to-Digital Converter (ADC) allows
conversion of an analog input signal to a 10-bit binary
representation of that signal. This device uses analog
inputs, which are multiplexed into a single sample and
hold circuit. The output of the sample and hold is
connected to the input of the converter. The converter
generates a 10-bit binary result via successive
approximation and stores the conversion result into the
ADC result registers (ADRESH:ADRESL register pair).
Figure 20-1 shows the block diagram of the ADC.
The ADC voltage reference is software selectable to be
either internally generated or externally supplied.
The ADC can generate an interrupt upon completion of
a conversion. This interrupt can be used to wake-up the
device from Sleep.

FIGURE 20-1: ADC BLOCK DIAGRAM

VDD
ADPREF = 00 ADPREF = 11
FVR_Buffer1

VREF+ ADPREF = 10

AN0 00000 VREF- = VSS

VREF+/AN1 00001 ADNREF = 0
AN2 00010
AN3 00011
AN4 00100 ADNREF = 1
AN5 00101
AN6 00110
AN7 00111 ADCREF+ ADCREF-

AN8 01000 ADC

AN9 01001 10
GO/DONE
AN10 01010
AN11 01011 0 = Left Justify
ADFM
1 = Right Justify
ADON 16

Reserved 11100 VSS ADRESH ADRESL

Temp Indicator 11101
DAC_output 11110
FVR_Buffer1 11111

CHS<4:0>

Note 1: When ADON = 0, all multiplexer inputs are disconnected.

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20.1 ADC Configuration 20.1.4 CONVERSION CLOCK
When configuring and using the ADC the following The source of the conversion clock is software
functions must be considered: selectable via the ADCS bits of the ADCON1 register.
There are seven possible clock options:
• Port configuration
• FOSC/2
• Channel selection
• FOSC/4
• ADC voltage reference selection
• FOSC/8
• ADC conversion clock source
• FOSC/16
• Interrupt control
• FOSC/32
• Result formatting
• FOSC/64
20.1.1 PORT CONFIGURATION • FRC (internal RC oscillator)
The ADC can be used to convert both analog and The time to complete one bit conversion is defined as
digital signals. When converting analog signals, the I/O TAD. One full 10-bit conversion requires 11.5 TAD
pin should be configured for analog by setting the periods as shown in Figure 20-2.
associated TRIS and ANSEL bits. Refer to For correct conversion, the appropriate TAD specification
Section 11.0 “I/O Ports” for more information. must be met. Refer to Table 32-16: ADC Conversion
Note: Analog voltages on any pin that is defined Requirements for more information. Table 20-1 gives
as a digital input may cause the input buf- examples of appropriate ADC clock selections.
fer to conduct excess current. Note: Unless using the FRC, any changes in the
system clock frequency will change the
20.1.2 CHANNEL SELECTION ADC clock frequency, which may
There are up to 17 channel selections available: adversely affect the ADC result.
• AN<13:8, 4:0> pins (PIC16(L)F1704 only)
• AN<21,13:0> pins (PIC16(L)F1708 only)
• Temperature Indicator
• DAC_output
• FVR_buffer1
The CHS bits of the ADCON0 register (Register 20-1)
determine which channel is connected to the sample
and hold circuit.
When changing channels, a delay is required before
starting the next conversion. Refer to Section 20.2
“ADC Operation” for more information.

20.1.3 ADC VOLTAGE REFERENCE

The ADPREF bits of the ADCON1 register provides
control of the positive voltage reference. The positive
voltage reference can be:
• VREF+ pin
• VDD
• FVR 2.048V
• FVR 4.096V (Not available on LF devices)
The ADNREF bit of the ADCON1 register provides
control of the negative voltage reference. The negative
voltage reference can be:
• VREF- pin
• VSS
See Section 20.0 “Analog-to-Digital Converter
(ADC) Module” for more details on the Fixed Voltage
Reference.

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TABLE 20-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES
ADC Clock Period (TAD) Device Frequency (FOSC)

ADC
ADCS<2:0> 32 MHz 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz
Clock Source

FOSC/2 000 62.5ns(2) 100 ns(2) 125 ns(2) 250 ns(2) 500 ns(2) 2.0 s
FOSC/4 100 125 ns (2)
200 ns (2)
250 ns (2)
500 ns (2)
1.0 s 4.0 s
FOSC/8 001 0.5 s(2) 400 ns(2) 0.5 s(2) 1.0 s 2.0 s 8.0 s(3)
FOSC/16 101 800 ns 800 ns 1.0 s 2.0 s 4.0 s 16.0 s(3)
FOSC/32 010 1.0 s 1.6 s 2.0 s 4.0 s 8.0 s (3)
32.0 s(2)
FOSC/64 110 2.0 s 3.2 s 4.0 s 8.0 s (3)
16.0 s (2)
64.0 s(2)
FRC x11 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4)
Legend: Shaded cells are outside of recommended range.
Note 1: See TAD parameter for FRC source typical TAD value.
2: These values violate the required TAD time.
3: Outside the recommended TAD time.
4: The ADC clock period (TAD) and total ADC conversion time can be minimized when the ADC clock is derived from the
system clock FOSC. However, the FRC oscillator source must be used when conversions are to be performed with the
device in Sleep mode.

FIGURE 20-2: ANALOG-TO-DIGITAL CONVERSION TAD CYCLES

TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11

b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

THCD
Conversion Starts
TACQ On the following cycle:
Holding capacitor disconnected
from analog input (THCD).
ADRESH:ADRESL is loaded,
GO bit is cleared,
Set GO bit ADIF bit is set,
holding capacitor is reconnected to analog input.
Enable ADC (ADON bit)
and
Select channel (ACS bits)

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20.1.5 INTERRUPTS 20.1.6 RESULT FORMATTING
The ADC module allows for the ability to generate an The 10-bit ADC conversion result can be supplied in
interrupt upon completion of an Analog-to-Digital two formats, left justified or right justified. The ADFM bit
conversion. The ADC Interrupt Flag is the ADIF bit in of the ADCON1 register controls the output format.
the PIR1 register. The ADC Interrupt Enable is the Figure 20-3 shows the two output formats.
ADIE bit in the PIE1 register. The ADIF bit must be
cleared in software.
Note 1: The ADIF bit is set at the completion of
every conversion, regardless of whether
or not the ADC interrupt is enabled.
2: The ADC operates during Sleep only
when the FRC oscillator is selected.
This interrupt can be generated while the device is
operating or while in Sleep. If the device is in Sleep, the
interrupt will wake-up the device. Upon waking from
Sleep, the next instruction following the SLEEP
instruction is always executed. If the user is attempting
to wake-up from Sleep and resume in-line code
execution, the ADIE bit of the PIE1 register and the
PEIE bit of the INTCON register must both be set and
the GIE bit of the INTCON register must be cleared. If
all three of these bits are set, the execution will switch
to the Interrupt Service Routine.

FIGURE 20-3: 10-BIT ADC CONVERSION RESULT FORMAT

ADRESH ADRESL
(ADFM = 0) MSB LSB
bit 7 bit 0 bit 7 bit 0

10-bit ADC Result Unimplemented: Read as ‘0’

(ADFM = 1) MSB LSB

bit 7 bit 0 bit 7 bit 0

Unimplemented: Read as ‘0’ 10-bit ADC Result

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20.2 ADC Operation 20.2.4 ADC OPERATION DURING SLEEP
The ADC module can operate during Sleep. This
20.2.1 STARTING A CONVERSION requires the ADC clock source to be set to the FRC
To enable the ADC module, the ADON bit of the option. When the FRC oscillator source is selected, the
ADCON0 register must be set to a ‘1’. Setting the ADC waits one additional instruction before starting the
GO/DONE bit of the ADCON0 register to a ‘1’ will start conversion. This allows the SLEEP instruction to be
the Analog-to-Digital conversion. executed, which can reduce system noise during the
conversion. If the ADC interrupt is enabled, the device
Note: The GO/DONE bit should not be set in the
will wake-up from Sleep when the conversion
same instruction that turns on the ADC.
completes. If the ADC interrupt is disabled, the ADC
Refer to Section 20.2.6 “ADC Conver-
module is turned off after the conversion completes,
sion Procedure”.
although the ADON bit remains set.
20.2.2 COMPLETION OF A CONVERSION When the ADC clock source is something other than
FRC, a SLEEP instruction causes the present
When the conversion is complete, the ADC module will: conversion to be aborted and the ADC module is
• Clear the GO/DONE bit turned off, although the ADON bit remains set.
• Set the ADIF Interrupt Flag bit
20.2.5 AUTO-CONVERSION TRIGGER
• Update the ADRESH and ADRESL registers with
new conversion result The Auto-conversion Trigger allows periodic ADC
measurements without software intervention. When a
20.2.3 TERMINATING A CONVERSION rising edge of the selected source occurs, the
If a conversion must be terminated before completion, GO/DONE bit is set by hardware.
the GO/DONE bit can be cleared in software. The The Auto-conversion Trigger source is selected with
ADRESH and ADRESL registers will be updated with the TRIGSEL<3:0> bits of the ADCON2 register.
the partially complete Analog-to-Digital conversion Using the Auto-conversion Trigger does not assure
sample. Incomplete bits will match the last bit proper ADC timing. It is the user’s responsibility to
converted. ensure that the ADC timing requirements are met.
Note: A device Reset forces all registers to their See Table 20-2 for auto-conversion sources.
Reset state. Thus, the ADC module is
TABLE 20-2: AUTO-CONVERSION
turned off and any pending conversion is
SOURCES
terminated.
Source Peripheral Signal Name
CCP1
CCP2
Timer0 T0_overflow
Timer1 T1_overflow
Timer2 T2_match
Timer4 T4_match
Timer6 T6_match
Comparator C1 C1OUT_sync
Comparator C2 C2OUT_sync
CLC1 LC1_out
CLC2 LC2_out
CLC3 LC3_out

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20.2.6 ADC CONVERSION PROCEDURE EXAMPLE 20-1: ADC CONVERSION
This is an example procedure for using the ADC to ;This code block configures the ADC
perform an Analog-to-Digital conversion: ;for polling, Vdd and Vss references, FRC
;oscillator and AN0 input.
1. Configure Port:
;
• Disable pin output driver (Refer to the TRIS ;Conversion start & polling for completion
register) ; are included.
• Configure pin as analog (Refer to the ANSEL ;
register) BANKSEL ADCON1 ;
MOVLW B’11110000’ ;Right justify, FRC
• Disable weak pull-ups either globally (Refer ;oscillator
to the OPTION_REG register) or individually MOVWF ADCON1 ;Vdd and Vss Vref
(Refer to the appropriate WPUx register) BANKSEL TRISA ;
2. Configure the ADC module: BSF TRISA,0 ;Set RA0 to input
• Select ADC conversion clock BANKSEL ANSEL ;
BSF ANSEL,0 ;Set RA0 to analog
• Configure voltage reference BANKSEL WPUA
• Select ADC input channel BCF WPUA,0 ;Disable weak
• Turn on ADC module ;pull-up on RA0
BANKSEL ADCON0 ;
3. Configure ADC interrupt (optional): MOVLW B’00000001’ ;Select channel AN0
• Clear ADC interrupt flag MOVWF ADCON0 ;Turn ADC On
• Enable ADC interrupt CALL SampleTime ;Acquisiton delay
BSF ADCON0,ADGO ;Start conversion
• Enable peripheral interrupt
BTFSC ADCON0,ADGO ;Is conversion done?
• Enable global interrupt(1) GOTO $-1 ;No, test again
4. Wait the required acquisition time(2). BANKSEL ADRESH ;
5. Start conversion by setting the GO/DONE bit. MOVF ADRESH,W ;Read upper 2 bits
MOVWF RESULTHI ;store in GPR space
6. Wait for ADC conversion to complete by one of BANKSEL ADRESL ;
the following: MOVF ADRESL,W ;Read lower 8 bits
• Polling the GO/DONE bit MOVWF RESULTLO ;Store in GPR space
• Waiting for the ADC interrupt (interrupts
enabled)
7. Read ADC Result.
8. Clear the ADC interrupt flag (required if interrupt
is enabled).

Note 1: The global interrupt can be disabled if the

user is attempting to wake-up from Sleep
and resume in-line code execution.
2: Refer to Section 20.4 “ADC Acquisi-
tion Requirements”.

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20.3 Register Definitions: ADC Control

REGISTER 20-1: ADCON0: ADC CONTROL REGISTER 0

U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— CHS<4:0> GO/DONE ADON
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 Unimplemented: Read as ‘0’

bit 6-2 CHS<4:0>: Analog Channel Select bits
11111 = FVR_Buffer1 Output(2)
11110 = DAC_output(1)
11101 = Temperature Indicator(3)
11100 = Reserved. No channel connected
11011 = Reserved. No channel connected.
•
•
•
01100 = Reserved. No channel connected.
01011 = AN11
01010 = AN10
01001 = AN9
01000 = AN8
00111 = AN7
00110 = AN6
00101 = AN5
00100 = AN4
00011 = AN3
00010 = AN2
00001 = AN1
00000 = AN0
bit 1 GO/DONE: ADC Conversion Status bit
1 = ADC conversion cycle in progress. Setting this bit starts an ADC conversion cycle.
This bit is automatically cleared by hardware when the ADC conversion has completed.
0 = ADC conversion completed/not in progress
bit 0 ADON: ADC Enable bit
1 = ADC is enabled
0 = ADC is disabled and consumes no operating current

Note 1: See Section 22.0 “8-Bit Digital-to-Analog Converter (DAC1) Module” for more information.
2: See Section 14.0 “Fixed Voltage Reference (FVR)” for more information.
3: See Section 15.0 “Temperature Indicator Module” for more information.

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REGISTER 20-2: ADCON1: ADC CONTROL REGISTER 1
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0
ADFM ADCS<2:0> — ADNREF ADPREF<1:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 ADFM: ADC Result Format Select bit

1 = Right justified. Six Most Significant bits of ADRESH are set to ‘0’ when the conversion result is
loaded.
0 = Left justified. Six Least Significant bits of ADRESL are set to ‘0’ when the conversion result is
loaded.
bit 6-4 ADCS<2:0>: ADC Conversion Clock Select bits
111 = FRC (clock supplied from an internal RC oscillator)
110 = FOSC/64
101 = FOSC/16
100 = FOSC/4
011 = FRC (clock supplied from an internal RC oscillator)
010 = FOSC/32
001 = FOSC/8
000 = FOSC/2
bit 3 Unimplemented: Read as ‘0’
bit 2 ADNREF: A/D Negative Voltage Reference Configuration
0 = VREF- is connected to VSS
1 = VREF- is connected to external VREF
bit 1-0 ADPREF<1:0>: ADC Positive Voltage Reference Configuration bits
11 = VREF+ is connected to internal FVR_Buffer1(1)
10 = VREF+ is connected to external VREF+ pin(1)
01 = Reserved
00 = VREF+ is connected to VDD

Note 1: When selecting the VREF+ pin as the source of the positive reference, be aware that a minimum voltage
specification exists. See Table 32-16: ADC Conversion Requirements for details.

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REGISTER 20-3: ADCON2: ADC CONTROL REGISTER 2

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0
(1)
TRIGSEL<3:0> — — — —
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-4 TRIGSEL<3:0>: Auto-Conversion Trigger Selection bits(1)

0000 = No auto-conversion trigger selected
0001 = CCP1
0010 = CCP2
0011 = Timer0 – T0_overflow(2)
0100 = Timer1 – T1_overflow(2)
0101 = Timer2 – T2_match
0110 = Comparator C1 – C1OUT_sync
0111 = Comparator C2 – C2OUT_sync
1000 = CLC1 – LC1_out
1001 = CLC2 – LC2_out
1010 = CLC3 – LC3_out
1011 = Reserved
1100 = Timer4 – T4_match
1101 = Timer6 – T6_match
1110 = Reserved
1111 = Reserved
bit 3-0 Unimplemented: Read as ‘0’
Note 1: This is a rising edge sensitive input for all sources.
2: Signal also sets its corresponding interrupt flag.

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REGISTER 20-4: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0

R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
ADRES<9:2>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 ADRES<9:2>: ADC Result Register bits

Upper eight bits of 10-bit conversion result

REGISTER 20-5: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0

R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
ADRES<1:0> — — — — — —
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 ADRES<1:0>: ADC Result Register bits

Lower two bits of 10-bit conversion result
bit 5-0 Reserved: Do not use.

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REGISTER 20-6: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1

R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
— — — — — — ADRES<9:8>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-2 Reserved: Do not use.

bit 1-0 ADRES<9:8>: ADC Result Register bits
Upper two bits of 10-bit conversion result

REGISTER 20-7: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1

R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
ADRES<7:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 ADRES<7:0>: ADC Result Register bits

Lower eight bits of 10-bit conversion result

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20.4 ADC Acquisition Requirements source impedance is decreased, the acquisition time
may be decreased. After the analog input channel is
For the ADC to meet its specified accuracy, the charge selected (or changed), an ADC acquisition must be
holding capacitor (CHOLD) must be allowed to fully done before the conversion can be started. To calculate
charge to the input channel voltage level. The Analog the minimum acquisition time, Equation 20-1 may be
Input model is shown in Figure 20-4. The source used. This equation assumes that 1/2 LSb error is used
impedance (RS) and the internal sampling switch (RSS) (1,024 steps for the ADC). The 1/2 LSb error is the
impedance directly affect the time required to charge maximum error allowed for the ADC to meet its
the capacitor CHOLD. The sampling switch (RSS) specified resolution.
impedance varies over the device voltage (VDD), refer
to Figure 20-4. The maximum recommended
impedance for analog sources is 10 k. As the

EQUATION 20-1: ACQUISITION TIME EXAMPLE

Assumptions: Temperature = 50°C and external impedance of 10k  5.0V V DD

T ACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
= T AMP + T C + T COFF
= 2µs + T C +   Temperature - 25°C   0.05µs/°C  

The value for TC can be approximated with the following equations:

V AP P LI ED  1 – -------------------------- = V CHOLD
1
;[1] VCHOLD charged to within 1/2 lsb
 n+1 
2 –1
–TC
 ----------
RC
V AP P LI ED  1 – e  = V CHOLD ;[2] VCHOLD charge response to VAPPLIED
 
– Tc
 ---------
V AP P LI ED  1 – e  = V A PP LIE D  1 – -------------------------- ;combining [1] and [2]
RC 1
  n+1 
2 –1

Note: Where n = number of bits of the ADC.

Solving for TC:

T C = – C HOLD  R IC + R SS + R S  ln(1/2047)
= – 10pF  1k  + 7k  + 10k   ln(0.0004885)
= 1.37 µs
Therefore:
T A CQ = 2µs + 892ns +   50°C- 25°C   0.05 µs/°C  
= 4.62µs

Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.

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FIGURE 20-4: ANALOG INPUT MODEL

VDD
Analog Sampling
Input Switch
VT  0.6V
Rs pin RIC  1k SS Rss

VA CPIN I LEAKAGE(1)
VT  0.6V CHOLD = 10 pF
5 pF
Ref-

6V
5V RSS
Legend: CHOLD = Sample/Hold Capacitance VDD 4V
3V
CPIN = Input Capacitance 2V
I LEAKAGE = Leakage current at the pin due to
various junctions
5 6 7 8 9 10 11
RIC = Interconnect Resistance
Sampling Switch
RSS = Resistance of Sampling Switch (k)
SS = Sampling Switch
VT = Threshold Voltage

Note 1: Refer to Table 32-4: I/O Ports (parameter D060).

FIGURE 20-5: ADC TRANSFER FUNCTION

Full-Scale Range

3FFh
3FEh
3FDh
3FCh
ADC Output Code

3FBh

03h
02h
01h
00h
Analog Input Voltage
0.5 LSB 1.5 LSB

Ref- Zero-Scale
Transition Full-Scale
Transition Ref+

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TABLE 20-3: SUMMARY OF REGISTERS ASSOCIATED WITH ADC
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page

ADCON0 — CHS<4:0> GO/DONE ADON 223

ADCON1 ADFM ADCS<2:0> — ADNREF ADPREF<1:0> 224
ADCON2 TRIGSEL<3:0> — — — — 225
ADRESH ADC Result Register High 226, 227
ADRESL ADC Result Register Low 226, 227
ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 122
(1)
ANSELB — — ANSB5 ANSB4 — — — — 128
ANSELC ANSC7(1) ANSC6(1) ANSC5(2) ANSC4(2) ANSC3 ANSC2 ANSC1 ANSC0 133
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 85
PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 86
PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 89
TRISA — — TRISA5 TRISA4 —(3) TRISA2 TRISA1 TRISA0 121
TRISB(1) TRISB7 TRISB6 TRISB5 TRISB4 — — — — 127
TRISC TRISC7(1) TRISC6(1) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 132
FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 151
DAC1CON0 DAC1EN — DAC1OE1 DAC1OE2 DAC1PSS<1:0> — DAC1NSS 237
Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’, q = value depends on condition. Shaded cells are not
used for the ADC module.
Note 1: PIC16(L)F1708 only.
2: PIC16(L)F1704 only.
3: Unimplemented, read as ‘1’.

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21.0 OPERATIONAL AMPLIFIER
(OPA) MODULES
The Operational Amplifier (OPA) is a standard
three-terminal device requiring external feedback to
operate. The OPA module has the following features:
• External connections to I/O ports
• Low leakage inputs
• Factory Calibrated Input Offset Voltage

FIGURE 21-1: OPAx MODULE BLOCK DIAGRAM

OPAXEN
OPAxIN+ 0x
OPAXSP(1)
DAC_output 10
OPA OPAXOUT
FVR_Buffer 2 11 OPAxIN- 0

1
OPAxNCH<1:0>
OPAXUG

Note 1: The OPAxSP bit must be set. Low-Power mode is not supported.

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21.1 OPA Module Performance 21.1.1 OPA Module Control
Common AC and DC performance specifications for The OPA module is enabled by setting the OPAxEN bit
the OPA module: of the OPAxCON register. When enabled, the OPA
forces the output driver of OPAxOUT pin into tri-state to
• Common Mode Voltage Range
prevent contention between the driver and the OPA
• Leakage Current output.
• Input Offset Voltage
Note: When the OPA module is enabled, the
• Open Loop Gain
OPAxOUT pin is driven by the op amp
• Gain Bandwidth Product output, not by the PORT digital driver.
Common mode voltage range is the specified voltage Refer to Table 32-17: Operational Amplifier
range for the OPA+ and OPA- inputs, for which the OPA (OPA) for the op amp output drive
module will perform to within its specifications. The capability.
OPA module is designed to operate with input voltages
between VSS and VDD. Behavior for Common mode 21.1.2 UNITY GAIN MODE
voltages greater than VDD, or below VSS, are not The OPAxUG bit of the OPAxCON register selects the
guaranteed. Unity Gain mode. When unity gain is selected, the OPA
Leakage current is a measure of the small source or output is connected to the inverting input and the
sink currents on the OPA+ and OPA- inputs. To OPAxIN pin is relinquished, releasing the pin for
minimize the effect of leakage currents, the effective general purpose input and output.
impedances connected to the OPA+ and OPA- inputs
should be kept as small as possible and equal. 21.2 Effects of Reset
Input offset voltage is a measure of the voltage A device Reset forces all registers to their Reset state.
difference between the OPA+ and OPA- inputs in a This disables the OPA module.
closed loop circuit with the OPA in its linear region. The
offset voltage will appear as a DC offset in the output
equal to the input offset voltage, multiplied by the gain
of the circuit. The input offset voltage is also affected by
the Common mode voltage. The OPA is factory
calibrated to minimize the input offset voltage of the
module.
Open loop gain is the ratio of the output voltage to the
differential input voltage, (OPA+) - (OPA-). The gain is
greatest at DC and falls off with frequency.
Gain Bandwidth Product or GBWP is the frequency
at which the open loop gain falls off to 0 dB.

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21.3 Register Definitions: Op Amp Control

REGISTER 21-1: OPAxCON: OPERATIONAL AMPLIFIERS (OPAx) CONTROL REGISTERS

R/W-0/0 R/W-0/0 U-0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0
OPAxEN OPAxSP — OPAxUG — — OPAxCH<1:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7 OPAxEN: Op Amp Enable bit

1 = Op amp is enabled
0 = Op amp is disabled and consumes no active power
bit 6 OPAxSP: Op Amp Speed/Power Select bit
1 = Op amp operates in high GBWP mode
0 = Reserved. Do not use.
bit 5 Unimplemented: Read as ‘0’
bit 4 OPAxUG: Op Amp Unity Gain Select bit
1 = OPA output is connected to inverting input. OPAxIN- pin is available for general purpose I/O.
0 = Inverting input is connected to the OPAxIN- pin
bit 3-2 Unimplemented: Read as ‘0’
bit 1-0 OPAxCH<1:0>: Non-inverting Channel Selection bits
11 = Non-inverting input connects to FVR Buffer 2 output
10 = Non-inverting input connects to DAC_output
0x = Non-inverting input connects to OPAxIN+ pin

TABLE 21-1: SUMMARY OF REGISTERS ASSOCIATED WITH OP AMPS

Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
ANSELB(1) — — ANSB5 ANSB4 — — — — 128
ANSELC ANSC7(1) ANSC6(1) ANSC5(2) ANSC4(2) ANSC3 ANSC2 ANSC1 ANSC0 128
DAC1CON0 DAC1EN — DAC1OE1 DAC1OE2 DAC1PSS<1:0> — DAC1NSS 237
DAC1CON1 DAC1R<7:0> 237
FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 151
OPA1CON OPA1EN OPA1SP — OPA1UG — — OPA1PCH<1:0> 233
OPA2CON OPA2EN OPA2SP — OPA2UG — — OPA2PCH<1:0> 233
(1)
TRISB TRISB7 TRISB6 TRISB5 TRISB4 — — — — 127
TRISC TRISC7(1) TRISC6(1) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 132
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by op amps.
Note 1: PIC16(L)F1708 only.
2: PIC16(L)F1704 only.
3: Unimplemented, read as ‘1’.

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22.0 8-BIT DIGITAL-TO-ANALOG 22.1 Output Voltage Selection
CONVERTER (DAC1) MODULE The DAC has 256 voltage level ranges. The 256 levels
The Digital-to-Analog Converter supplies a variable are set with the DAC1R<7:0> bits of the DAC1CON1
voltage reference, ratiometric with the input source, register.
with 256 selectable output levels. The DAC output voltage is determined by Equation 22-1:
The input of the DAC can be connected to:
• External VREF pins
• VDD supply voltage
• FVR (Fixed Voltage Reference)
The output of the DAC can be configured to supply a
reference voltage to the following:
• Comparator positive input
• ADC input channel
• DAC1OUT1 pin
• DAC1OUT2 pin
The Digital-to-Analog Converter (DAC) is enabled by
setting the DAC1EN bit of the DAC1CON0 register.

EQUATION 22-1: DAC OUTPUT VOLTAGE

IF DAC1EN = 1
DAC1R  7:0 
VOUT =   VSOURCE+ – VSOURCE-   --------------------------------
- + VSOURCE-
 8 
2
VSOURCE+ = VDD, VREF, or FVR BUFFER 2

VSOURCE- = VSS

22.2 Ratiometric Output Level

The DAC output value is derived using a resistor ladder
with each end of the ladder tied to a positive and
negative voltage reference input source. If the voltage
of either input source fluctuates, a similar fluctuation will
result in the DAC output value.
The value of the individual resistors within the ladder
can be found in Table 32-19: Digital-to-Analog
Converter (DAC) Specifications.

22.3 DAC Voltage Reference Output

The DAC voltage can be output to the DAC1OUT1 and
DAC1OUT2 pins by setting the respective DAC1OE1
and DAC1OE2 bits of the DAC1CON0 register.
Selecting the DAC voltage for output on either
DAC1OUTX pin automatically overrides the digital
output buffer and digital input threshold detector
functions of that pin. Reading the DAC1OUTX pin when
it has been configured for DAC voltage output will
always return a ‘0’.
Due to the limited current drive capability, a buffer must
be used on the DAC voltage output for external
connections to either DAC1OUTx pin. Figure 22-2
shows an example buffering technique.

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FIGURE 22-1: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM

Digital-to-Analog Converter (DAC)

FVR Buffer2
VDD
VSOURCE+
DAC1R<7:0>
8
VREF+
R

R
DAC1PSS<1:0>
2
R
DAC1EN
R

256-to-1 MUX
256 DAC1_Output (To Comparator and
Steps ADC Modules)

R
R
DAC1OUT1
R
DAC1OE1
DAC1NSS
DAC1OUT2

VREF- VSOURCE- DAC1OE2

VSS

FIGURE 22-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE

PIC® MCU

DAC
R
Module
+
Voltage DAC1OUTX Buffered DAC Output
–
Reference
Output
Impedance

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22.4 Operation During Sleep
The DAC continues to function during Sleep. When the
device wakes up from Sleep through an interrupt or a
Watchdog Timer time-out, the contents of the
DAC1CON0 register are not affected. To minimize
current consumption in Sleep mode, the voltage
reference should be disabled.

22.5 Effects of a Reset

A device Reset affects the following:
• DAC is disabled.
• DAC output voltage is removed from the
DAC1OUT pin.
• The DAC1R<4:0> voltage reference control bits
are cleared.

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22.6 Register Definitions: DAC Control

REGISTER 22-1: DAC1CON0: VOLTAGE REFERENCE CONTROL REGISTER 0

R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0
DAC1EN — DAC1OE1 DAC1OE2 DAC1PSS<1:0> — DAC1NSS
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 DAC1EN: DAC1 Enable bit

1 = DAC is enabled
0 = DAC is disabled
bit 6 Unimplemented: Read as ‘0’
bit 5 DAC1OE1: DAC1 Voltage Output 1 Enable bit
1 = DAC voltage level is also an output on the DAC1OUT1 pin
0 = DAC voltage level is disconnected from the DAC1OUT1 pin
bit 4 DAC1OE2: DAC1 Voltage Output 2 Enable bit
1 = DAC voltage level is also an output on the DAC1OUT2 pin
0 = DAC voltage level is disconnected from the DAC1OUT2 pin
bit 3-2 DAC1PSS<1:0>: DAC1 Positive Source Select bits
11 = Reserved, do not use
10 = FVR Buffer2 output
01 = VREF+ pin
00 = VDD
bit 1 Unimplemented: Read as ‘0’
bit 0 DAC1NSS: DAC1 Negative Source Select bits
1 = VREF- pin
0 = VSS

REGISTER 22-2: DAC1CON1: VOLTAGE REFERENCE CONTROL REGISTER 1

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
DAC1R<7:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 DAC1R<7:0>: DAC1 Voltage Output Select bits

TABLE 22-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE DAC1 MODULE

Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on page
DAC1CON0 DAC1EN — DAC1OE1 DAC1OE2 DAC1PSS<1:0> — DAC1NSS 237
DAC1CON1 DAC1R<7:0> 237
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used with the DAC module.

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PIC16(L)F1704/8
23.0 ZERO-CROSS DETECTION 23.1 External Resistor Selection
(ZCD) MODULE The ZCD module requires a current limiting resistor in
The ZCD module detects when an A/C signal crosses series with the external voltage source. The impedance
through the ground potential. The actual zero-crossing and rating of this resistor depends on the external
threshold is the zero-crossing reference voltage, source peak voltage. Select a resistor value that will
ZCPINV, which is typically 0.75V above ground. drop all of the peak voltage when the current through
the resistor is nominally 300 µA (refer to Equation 23-1
The connection to the signal to be detected is through and Figure 23-1). Make sure that the ZCD I/O pin
a series current limiting resistor. The module applies a internal weak pull-up is disabled so it does not interfere
current source or sink to the ZCD pin to maintain a with the current source and sink.
constant voltage on the pin, thereby preventing the pin
voltage from forward biasing the ESD protection
EQUATION 23-1: EXTERNAL RESISTOR
diodes. When the applied voltage is greater than the
reference voltage, the module sinks current. When the
applied voltage is less than the reference voltage, the V PEAK
R SERIES = ----------------
–4
-
module sources current. The current source and sink 3 10
action keeps the pin voltage constant over the full
range of the applied voltage. The ZCD module is
shown in the simplified block diagram Figure 23-2. FIGURE 23-1: EXTERNAL VOLTAGE
The ZCD module is useful when monitoring an A/C
VMAXPEAK
waveform for, but not limited to, the following purposes:
VPEAK VMINPEAK
• A/C period measurement
• Accurate long term time measurement
• Dimmer phase delayed drive ZCPINV
• Low EMI cycle switching

FIGURE 23-2: SIMPLIFIED ZCD BLOCK DIAGRAM

VPULLUP
VDD optional

RPULLUP
External current
- limiting resistor

ZCPINV + ZCD pin RSERIES External

RPULLDOWN voltage
source
optional

ZCDx_output
D Q ZCDxOUT
ZCDxPOL
Q1 LE

Interrupt
det
Sets
ZCDxINTP ZCDIF flag

ZCDxINTN
Interrupt
det

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23.2 ZCD Logic Output 23.5 Correcting for ZCPINV offset
The ZCD module includes a Status bit, which can be The actual voltage at which the ZCD switches is the
read to determine whether the current source or sink is reference voltage at the non-inverting input of the ZCD
active. The ZCDxOUT bit of the ZCDxCON register is op amp. For external voltage source waveforms, other
set when the current sink is active, and cleared when than square waves, this voltage offset from zero
the current source is active. The ZCDxOUT bit is causes the zero-cross event to occur either too early or
affected by the polarity bit. too late. When the waveform is varying relative to VSS,
then the zero cross is detected too early as the
23.3 ZCD Logic Polarity waveform falls and too late as the waveform rises.
When the waveform is varying relative to VDD, then the
The ZCDxPOL bit of the ZCDxCON register inverts the zero cross is detected too late as the waveform rises
ZCDxOUT bit relative to the current source and sink and too early as the waveform falls. The actual offset
output. When the ZCDxPOL bit is set, a ZCDxOUT high time can be determined for sinusoidal waveforms with
indicates that the current source is active, and a low the corresponding equations shown in Equation 23-2.
output indicates that the current sink is active.
The ZCDxPOL bit affects the ZCD interrupts. See EQUATION 23-2: ZCD EVENT OFFSET
Section 23.4 “ZCD Interrupts”.
When External Voltage Source is relative to Vss:
23.4 ZCD Interrupts
asin  ------------------
Z CPINV
An interrupt will be generated upon a change in the V PEAK
ZCD logic output when the appropriate interrupt T OFFSET = -----------------------------------
enables are set. A rising edge detector and a falling 2  Freq
edge detector are present in the ZCD for this purpose.
The ZCDIF bit of the PIR3 register will be set when When External Voltage Source is relative to VDD:
either edge detector is triggered and its associated
enable bit is set. The ZCDxINTP enables rising edge
asin  ---------------------------------
V DD – Z CPINV
interrupts and the ZCDxINTN bit enables falling edge
interrupts. Both are located in the ZCDxCON register. V PEAK
T OFFSET = -------------------------------------------------
To fully enable the interrupt, the following bits must be set: 2  Freq
• ZCDIE bit of the PIE3 register
• ZCDxINTP bit of the ZCDxCON register This offset time can be compensated for by adding a
(for a rising edge detection) pull-up or pull-down biasing resistor to the ZCD pin. A
• ZCDxINTN bit of the ZCDxCON register pull-up resistor is used when the external voltage
(for a falling edge detection) source is varying relative to VSS. A pull-down resistor is
used when the voltage is varying relative to VDD. The
• PEIE and GIE bits of the INTCON register
resistor adds a bias to the ZCD pin so that the target
Changing the ZCDxPOL bit will cause an interrupt, external voltage source must go to zero to pull the pin
regardless of the level of the ZCDxEN bit. voltage to the ZCPINV switching voltage. The pull-up or
The ZCDIF bit of the PIR3 register must be cleared in pull-down value can be determined with the equations
software as part of the interrupt service. If another edge shown in Equation 23-3 or Equation 23-4.
is detected while this flag is being cleared, the flag will
still be set at the end of the sequence. EQUATION 23-3: ZCD PULL-UP/DOWN
When External Signal is relative to Vss:

R SERIE S  V PULLUP – Z CPINV 

R PULLUP = -------------------------------------------------------------------------
Z CPINV
When External Signal is relative to VDD:

R SERIES  Z CPINV 
R PULLDOWN = ---------------------------------------------
 V DD – Z CPINV 

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The pull-up and pull-down resistor values are 23.6 Handling VPEAK Variations
significantly affected by small variations of ZCPINV.
Measuring ZCPINV can be difficult, especially when the If the peak amplitude of the external voltage is
waveform is relative to VDD. However, by combining expected to vary, the series resistor must be selected
Equations 23-2 and 23-3, the resistor value can be to keep the ZCD current source and sink below the
determined from the time difference between the design maximum range of ± 600 A and above a
ZCDx_output high and low periods. Note that the time reasonable minimum range. A general rule of thumb is
difference, ∆T, is 4*TOFFSET. The equation for that the maximum peak voltage can be no more than
determining the pull-up and pull-down resistor values six times the minimum peak voltage. To ensure that the
from the high and low ZCDx_output periods is shown in maximum current does not exceed ± 600 A and the
Equation 23-4. The ZCDx_output signal can be directly minimum is at least ± 100 A, compute the series
observed on a pin by routing the ZCDx_output signal resistance as shown in Equation 23-5. The
through one of the CLCs. compensating pull-up for this series resistance can be
determined with Equation 23-3 because the pull-up
value is independent from the peak voltage.
EQUATION 23-4:
EQUATION 23-5: SERIES R FOR V RANGE
 
 V BI A S 
R = R SERIES  ---------------------------------------------------------------- – 1 V MAXPEAK + V MINPEAK
 V PE AK  sin  Freq ----------- T  
-  R SERIES = ---------------------------------------------------------
   2   –4
7 10

R is pull-up or pull-down resistor.

23.7 Operation During Sleep
VBIAS is VPULLUP when R is pull-up or VDD when R
is pull-down. The ZCD current sources and interrupts are unaffected
by Sleep.
∆T is the ZCDOUT high and low period difference.

23.8 Effects of a Reset

The ZCD circuit can be configured to default to the active
or inactive state on Power-On-Reset (POR). When the
ZCDDIS Configuration bit is cleared, the ZCD circuit will
be active at POR. When the ZCDDIS Configuration bit is
set, the ZCDxEN bit of the ZCDxCON register must be
set to enable the ZCD module.

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23.9 Register Definitions: ZCD Control

REGISTER 23-1: ZCDxCON: ZERO-CROSS DETECTION CONTROL REGISTER

R/W-0/0 U-0 R-x/x R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0
ZCDxEN — ZCDxOUT ZCDxPOL — — ZCDxINTP ZCDxINTN
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = value depends on configuration bits

bit 7 ZCDxEN: Zero-Cross Detection Enable bit(1)

1 = Zero-cross detect is enabled. ZCD pin is forced to output to source and sink current.
0 = Zero-cross detect is disabled. ZCD pin operates according to PPS and TRIS controls.
bit 6 Unimplemented: Read as ‘0’
bit 5 ZCDxOUT: Zero-Cross Detection Logic Level bit
ZCDxPOL bit = 0:
1 = ZCD pin is sinking current
0 = ZCD pin is sourcing current
ZCDxPOL bit = 1:
1 = ZCD pin is sourcing current
0 = ZCD pin is sinking current
bit 4 ZCDxPOL: Zero-Cross Detection Logic Output Polarity bit
1 = ZCD logic output is inverted
0 = ZCD logic output is not inverted
bit 3-2 Unimplemented: Read as ‘0’
bit 1 ZCDxINTP: Zero-Cross Positive Edge Interrupt Enable bit
1 = ZCDIF bit is set on low-to-high ZCDx_output transition
0 = ZCDIF bit is unaffected by low-to-high ZCDx_output transition
bit 0 ZCDxINTN: Zero-Cross Negative Edge Interrupt Enable bit
1 = ZCDIF bit is set on high-to-low ZCDx_output transition
0 = ZCDIF bit is unaffected by high-to-low ZCDx_output transition
Note 1: The ZCDxEN bit has no effect when the ZCDDIS Configuration bit is cleared.

TABLE 23-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE ZCD MODULE

Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on page
PIE3 — — COGIE ZCDIE — — — — 88
PIR3 — — CWGIF ZCDIF — — — — 91
ZCD1CON ZCD1EN — ZCD1OUT ZCD1POL — — ZCD1INTP ZCD1INTN 241
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the ZCD module.

TABLE 23-2: SUMMARY OF CONFIGURATION WORD WITH THE ZCD MODULE

Register
Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0
on Page

CONFIG2 13:8 — — LVP DEBUG LPBOR BORV STVREN PLLEN 51

7:0 ZCDDIS — — — — — WRT<1:0>
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the ZCD module.

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24.0 TIMER0 MODULE 24.1.2 8-BIT COUNTER MODE
The Timer0 module is an 8-bit timer/counter with the In 8-Bit Counter mode, the Timer0 module will increment
following features: on every rising or falling edge of the T0CKI pin.

• 8-bit timer/counter register (TMR0) 8-Bit Counter mode using the T0CKI pin is selected by
setting the TMR0CS bit in the OPTION_REG register to
• 8-bit prescaler (independent of Watchdog Timer)
‘1’.
• Programmable internal or external clock source
The rising or falling transition of the incrementing edge
• Programmable external clock edge selection
for either input source is determined by the TMR0SE bit
• Interrupt on overflow in the OPTION_REG register.
• TMR0 can be used to gate Timer1
Figure 24-1 is a block diagram of the Timer0 module.

24.1 Timer0 Operation

The Timer0 module can be used as either an 8-bit timer
or an 8-bit counter.

24.1.1 8-BIT TIMER MODE

The Timer0 module will increment every instruction
cycle, if used without a prescaler. 8-bit Timer mode is
selected by clearing the TMR0CS bit of the
OPTION_REG register.
When TMR0 is written, the increment is inhibited for
two instruction cycles immediately following the write.
Note: The value written to the TMR0 register
can be adjusted, in order to account for
the two instruction cycle delay when
TMR0 is written.

FIGURE 24-1: BLOCK DIAGRAM OF THE TIMER0

FOSC/4
Data Bus
0
8
T0CKI 1
Sync
1 2 TCY TMR0
0
TMR0SE TMR0CS Set Flag bit TMR0IF
8-bit on Overflow
Prescaler PSA
Overflow to Timer1

PS<2:0>

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24.1.3 SOFTWARE PROGRAMMABLE
PRESCALER
A software programmable prescaler is available for
exclusive use with Timer0. The prescaler is enabled by
clearing the PSA bit of the OPTION_REG register.
Note: The Watchdog Timer (WDT) uses its own
independent prescaler.
There are eight prescaler options for the Timer0
module ranging from 1:2 to 1:256. The prescale values
are selectable via the PS<2:0> bits of the
OPTION_REG register. In order to have a 1:1 prescaler
value for the Timer0 module, the prescaler must be
disabled by setting the PSA bit of the OPTION_REG
register.
The prescaler is not readable or writable. All instructions
writing to the TMR0 register will clear the prescaler.

24.1.4 TIMER0 INTERRUPT

Timer0 will generate an interrupt when the TMR0
register overflows from FFh to 00h. The TMR0IF
interrupt flag bit of the INTCON register is set every
time the TMR0 register overflows, regardless of
whether or not the Timer0 interrupt is enabled. The
TMR0IF bit can only be cleared in software. The Timer0
interrupt enable is the TMR0IE bit of the INTCON
register.
Note: The Timer0 interrupt cannot wake the
processor from Sleep since the timer is
frozen during Sleep.

24.1.5 8-BIT COUNTER MODE

SYNCHRONIZATION
When in 8-Bit Counter mode, the incrementing edge on
the T0CKI pin must be synchronized to the instruction
clock. Synchronization can be accomplished by
sampling the prescaler output on the Q2 and Q4 cycles
of the instruction clock. The high and low periods of the
external clocking source must meet the timing
requirements as shown in Table 32-12: Timer0 and
Timer1 External Clock Requirements.

24.1.6 OPERATION DURING SLEEP

Timer0 cannot operate while the processor is in Sleep
mode. The contents of the TMR0 register will remain
unchanged while the processor is in Sleep mode.

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24.2 Register Definitions: Option Register

REGISTER 24-1: OPTION_REG: OPTION REGISTER

R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1
WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 WPUEN: Weak Pull-Up Enable bit

1 = All weak pull-ups are disabled (except MCLR, if it is enabled)
0 = Weak pull-ups are enabled by individual WPUx latch values
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of INT pin
0 = Interrupt on falling edge of INT pin
bit 5 TMR0CS: Timer0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (FOSC/4)
bit 4 TMR0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is not assigned to the Timer0 module
0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS<2:0>: Prescaler Rate Select bits
Bit Value Timer0 Rate

000 1:2
001 1:4
010 1:8
011 1 : 16
100 1 : 32
101 1 : 64
110 1 : 128
111 1 : 256

TABLE 24-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0

Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 85
OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 244
TMR0 Timer0 Module Register 242*
TRISA — — TRISA5 TRISA4 —(1) TRISA2 TRISA1 TRISA0 121
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the Timer0 module.
* Page provides register information.
Note 1: Unimplemented, read as ‘1’.

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25.0 TIMER1 MODULE WITH GATE • Gate Toggle mode
CONTROL • Gate Single-pulse mode
• Gate Value Status
The Timer1 module is a 16-bit timer/counter with the
• Gate Event Interrupt
following features:
Figure 25-1 is a block diagram of the Timer1 module.
• 16-bit timer/counter register pair (TMR1H:TMR1L)
• Programmable internal or external clock source
• 2-bit prescaler
• Dedicated 32 kHz oscillator circuit
• Optionally synchronized comparator out
• Multiple Timer1 gate (count enable) sources
• Interrupt on overflow
• Wake-up on overflow (external clock,
Asynchronous mode only)
• Time base for the Capture/Compare function
• Auto-conversion Trigger (with CCP)
• Selectable Gate Source Polarity

FIGURE 25-1: TIMER1 BLOCK DIAGRAM

T1GSS<1:0>

T1G 00 T1GSPM

From Timer0 01 t1g_in 0

Overflow T1GVAL Data Bus
0 D Q
sync_C1OUT 10 Single-Pulse RD
1 T1GCON
Acq. Control Q1 EN
D Q 1
sync_C2OUT 11 Interrupt
Q T1GGO/DONE Set
TMR1ON CK
det TMR1GIF
R
T1GPOL T1GTM
TMR1GE
Set flag bit TMR1ON
TMR1IF on To Comparator Module
Overflow TMR1(2)
EN Synchronized
To ADC Auto-Conversion 0 clock input
TMR1H TMR1L T1CLK
Q D
1
TMR1CS<1:0>
T1SYNC
SOSCO OUT
LFINTOSC 11
SOSC Prescaler Synchronize(3)
1 1, 2, 4, 8 det
SOSCI 10
EN
2
0
FOSC T1CKPS<1:0>
Internal 01
Clock FOSC/2
T1OSCEN Sleep input
Internal
FOSC/4 Clock
Internal 00
(1) Clock
T1CKI
To Clock Switching Modules

Note 1: ST Buffer is high speed type when using T1CKI.

2: Timer1 register increments on rising edge.
3: Synchronize does not operate while in Sleep.

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25.1 Timer1 Operation 25.2 Clock Source Selection
The Timer1 module is a 16-bit incrementing counter The TMR1CS<1:0> and T1OSCEN bits of the T1CON
which is accessed through the TMR1H:TMR1L register register are used to select the clock source for Timer1.
pair. Writes to TMR1H or TMR1L directly update the Table 25-2 displays the clock source selections.
counter.
25.2.1 INTERNAL CLOCK SOURCE
When used with an internal clock source, the module is
a timer and increments on every instruction cycle. When the internal clock source is selected, the
When used with an external clock source, the module TMR1H:TMR1L register pair will increment on multiples
can be used as either a timer or counter and of FOSC as determined by the Timer1 prescaler.
increments on every selected edge of the external When the FOSC internal clock source is selected, the
source. Timer1 register value will increment by four counts every
Timer1 is enabled by configuring the TMR1ON and instruction clock cycle. Due to this condition, a 2 LSB
TMR1GE bits in the T1CON and T1GCON registers, error in resolution will occur when reading the Timer1
respectively. Table 25-1 displays the Timer1 enable value. To utilize the full resolution of Timer1, an
selections. asynchronous input signal must be used to gate the
Timer1 clock input.

TABLE 25-1: TIMER1 ENABLE The following asynchronous sources may be used:
SELECTIONS • Asynchronous event on the T1G pin to Timer1
gate
Timer1
TMR1ON TMR1GE
Operation • C1 or C2 comparator input to Timer1 gate

0 0 Off 25.2.2 EXTERNAL CLOCK SOURCE

0 1 Off When the external clock source is selected, the Timer1
1 0 Always On module may work as a timer or a counter.
1 1 Count Enabled When enabled to count, Timer1 is incremented on the
rising edge of the external clock input T1CKI, which can
be synchronized to the microcontroller system clock or
can run asynchronously.
When used as a timer with a clock oscillator, an
external 32.768 kHz crystal can be used in conjunction
with the dedicated internal oscillator circuit.
Note: In Counter mode, a falling edge must be
registered by the counter prior to the first
incrementing rising edge after any one or
more of the following conditions:
• Timer1 enabled after POR
• Write to TMR1H or TMR1L
• Timer1 is disabled
• Timer1 is disabled (TMR1ON = 0)
when T1CKI is high then Timer1 is
enabled (TMR1ON=1) when T1CKI is
low.

TABLE 25-2: CLOCK SOURCE SELECTIONS

TMR1CS<1:0> T1OSCEN Clock Source
11 x LFINTOSC
10 0 External Clocking on T1CKI Pin
01 x System Clock (FOSC)
00 x Instruction Clock (FOSC/4)

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25.3 Timer1 Prescaler 25.5.1 READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER
Timer1 has four prescaler options allowing 1, 2, 4 or 8
MODE
divisions of the clock input. The T1CKPS bits of the
T1CON register control the prescale counter. The Reading TMR1H or TMR1L while the timer is running
prescale counter is not directly readable or writable; from an external asynchronous clock will ensure a valid
however, the prescaler counter is cleared upon a write to read (taken care of in hardware). However, the user
TMR1H or TMR1L. should keep in mind that reading the 16-bit timer in two
8-bit values itself, poses certain problems, since the
25.4 Timer1 (Secondary) Oscillator timer may overflow between the reads.
For writes, it is recommended that the user simply stop
A dedicated low-power 32.768 kHz oscillator circuit is
the timer and write the desired values. A write
built-in between pins SOSCI (input) and SOSCO
contention may occur by writing to the timer registers,
(amplifier output). This internal circuit is to be used in
while the register is incrementing. This may produce an
conjunction with an external 32.768 kHz crystal.
unpredictable value in the TMR1H:TMR1L register pair.
The oscillator circuit is enabled by setting the
T1OSCEN bit of the T1CON register. The oscillator will 25.6 Timer1 Gate
continue to run during Sleep.
Timer1 can be configured to count freely or the count
Note: The oscillator requires a start-up and can be enabled and disabled using Timer1 gate
stabilization time before use. Thus, circuitry. This is also referred to as Timer1 Gate Enable.
T1OSCEN should be set and a suitable
delay observed prior to using Timer1. A Timer1 gate can also be driven by multiple selectable
suitable delay similar to the OST delay sources.
can be implemented in software by
clearing the TMR1IF bit then presetting 25.6.1 TIMER1 GATE ENABLE
the TMR1H:TMR1L register pair to The Timer1 Gate Enable mode is enabled by setting
FC00h. The TMR1IF flag will be set when the TMR1GE bit of the T1GCON register. The polarity
1024 clock cycles have elapsed, thereby of the Timer1 Gate Enable mode is configured using
indicating that the oscillator is running and the T1GPOL bit of the T1GCON register.
reasonably stable. When Timer1 Gate Enable mode is enabled, Timer1
will increment on the rising edge of the Timer1 clock
25.5 Timer1 Operation in source. When Timer1 Gate Enable mode is disabled,
Asynchronous Counter Mode no incrementing will occur and Timer1 will hold the
current count. See Figure 25-3 for timing details.
If the control bit T1SYNC of the T1CON register is set,
the external clock input is not synchronized. The timer
increments asynchronously to the internal phase TABLE 25-3: TIMER1 GATE ENABLE
clocks. If the external clock source is selected then the SELECTIONS
timer will continue to run during Sleep and can T1CLK T1GPOL T1G Timer1 Operation
generate an interrupt on overflow, which will wake-up
the processor. However, special precautions in  0 0 Counts
software are needed to read/write the timer (see  0 1 Holds Count
Section 25.5.1 “Reading and Writing Timer1 in  1 0 Holds Count
Asynchronous Counter Mode”).
 1 1 Counts
Note: When switching from synchronous to
asynchronous operation, it is possible to
skip an increment. When switching from
asynchronous to synchronous operation,
it is possible to produce an additional
increment.

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25.6.2 TIMER1 GATE SOURCE Timer1 Gate Toggle mode is enabled by setting the
SELECTION T1GTM bit of the T1GCON register. When the T1GTM
bit is cleared, the flip-flop is cleared and held clear. This
Timer1 gate source selections are shown in Table 25-4.
is necessary in order to control which edge is
Source selection is controlled by the T1GSS bits of the
measured.
T1GCON register. The polarity for each available source
is also selectable. Polarity selection is controlled by the Note: Enabling Toggle mode at the same time
T1GPOL bit of the T1GCON register. as changing the gate polarity may result in
indeterminate operation.
TABLE 25-4: TIMER1 GATE SOURCES
25.6.4 TIMER1 GATE SINGLE-PULSE
T1GSS Timer1 Gate Source
MODE
00 Timer1 Gate Pin
When Timer1 Gate Single-Pulse mode is enabled, it is
01 Overflow of Timer0 possible to capture a single-pulse gate event. Timer1
(TMR0 increments from FFh to 00h) Gate Single-Pulse mode is first enabled by setting the
10 Comparator 1 Output sync_C1OUT T1GSPM bit in the T1GCON register. Next, the
(optionally Timer1 synchronized output) T1GGO/DONE bit in the T1GCON register must be set.
Comparator 2 Output sync_C2OUT The Timer1 will be fully enabled on the next
11
(optionally Timer1 synchronized output) incrementing edge. On the next trailing edge of the
pulse, the T1GGO/DONE bit will automatically be
cleared. No other gate events will be allowed to
25.6.2.1 T1G Pin Gate Operation
increment Timer1 until the T1GGO/DONE bit is once
The T1G pin is one source for Timer1 gate control. It again set in software. See Figure 25-5 for timing details.
can be used to supply an external source to the Timer1
If the Single-Pulse Gate mode is disabled by clearing the
gate circuitry.
T1GSPM bit in the T1GCON register, the T1GGO/DONE
25.6.2.2 Timer0 Overflow Gate Operation bit should also be cleared.

When Timer0 increments from FFh to 00h, a Enabling the Toggle mode and the Single-Pulse mode
low-to-high pulse will automatically be generated and simultaneously will permit both sections to work
internally supplied to the Timer1 gate circuitry. together. This allows the cycle times on the Timer1 gate
source to be measured. See Figure 25-6 for timing
25.6.2.3 Comparator C1 Gate Operation details.
The output resulting from a Comparator 1 operation can 25.6.5 TIMER1 GATE VALUE STATUS
be selected as a source for Timer1 gate control. The
Comparator 1 output (sync_C1OUT) can be When Timer1 Gate Value Status is utilized, it is possible
synchronized to the Timer1 clock or left asynchronous. to read the most current level of the gate control value.
For more information see Section 16.4.1 “Comparator The value is stored in the T1GVAL bit in the T1GCON
Output Synchronization”. register. The T1GVAL bit is valid even when the Timer1
gate is not enabled (TMR1GE bit is cleared).
25.6.2.4 Comparator C2 Gate Operation
25.6.6 TIMER1 GATE EVENT INTERRUPT
The output resulting from a Comparator 2 operation
can be selected as a source for Timer1 gate control. When Timer1 Gate Event Interrupt is enabled, it is
The Comparator 2 output (sync_C2OUT) can be possible to generate an interrupt upon the completion
synchronized to the Timer1 clock or left asynchronous. of a gate event. When the falling edge of T1GVAL
For more information see Section 16.4.1 “Comparator occurs, the TMR1GIF flag bit in the PIR1 register will be
Output Synchronization”. set. If the TMR1GIE bit in the PIE1 register is set, then
an interrupt will be recognized.
25.6.3 TIMER1 GATE TOGGLE MODE The TMR1GIF flag bit operates even when the Timer1
When Timer1 Gate Toggle mode is enabled, it is gate is not enabled (TMR1GE bit is cleared).
possible to measure the full-cycle length of a Timer1
gate signal, as opposed to the duration of a single level
pulse.
The Timer1 gate source is routed through a flip-flop that
changes state on every incrementing edge of the
signal. See Figure 25-4 for timing details.

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25.7 Timer1 Interrupt 25.9 CCP Capture/Compare Time Base
The Timer1 register pair (TMR1H:TMR1L) increments The CCP modules use the TMR1H:TMR1L register
to FFFFh and rolls over to 0000h. When Timer1 rolls pair as the time base when operating in Capture or
over, the Timer1 interrupt flag bit of the PIR1 register is Compare mode.
set. To enable the interrupt on rollover, you must set In Capture mode, the value in the TMR1H:TMR1L
these bits: register pair is copied into the CCPR1H:CCPR1L
• TMR1ON bit of the T1CON register register pair on a configured event.
• TMR1IE bit of the PIE1 register In Compare mode, an event is triggered when the value
• PEIE bit of the INTCON register CCPR1H:CCPR1L register pair matches the value in
• GIE bit of the INTCON register the TMR1H:TMR1L register pair. This event can be an
Auto-conversion Trigger.
The interrupt is cleared by clearing the TMR1IF bit in
the Interrupt Service Routine. For more information, see Section 27.0
“Capture/Compare/PWM Modules”.
Note: The TMR1H:TMR1L register pair and the
TMR1IF bit should be cleared before
25.10 CCP Auto-Conversion Trigger
enabling interrupts.
When any of the CCP’s are configured to trigger an
25.8 Timer1 Operation During Sleep auto-conversion, the trigger will clear the
TMR1H:TMR1L register pair. This auto-conversion
Timer1 can only operate during Sleep when setup in does not cause a Timer1 interrupt. The CCP module
Asynchronous Counter mode. In this mode, an external may still be configured to generate a CCP interrupt.
crystal or clock source can be used to increment the
In this mode of operation, the CCPR1H:CCPR1L
counter. To set up the timer to wake the device:
register pair becomes the period register for Timer1.
• TMR1ON bit of the T1CON register must be set
Timer1 should be synchronized and FOSC/4 should be
• TMR1IE bit of the PIE1 register must be set selected as the clock source in order to utilize the
• PEIE bit of the INTCON register must be set Auto-conversion Trigger. Asynchronous operation of
• T1SYNC bit of the T1CON register must be set Timer1 can cause an Auto-conversion Trigger to be
• TMR1CS bits of the T1CON register must be missed.
configured In the event that a write to TMR1H or TMR1L coincides
• T1OSCEN bit of the T1CON register must be with an Auto-conversion Trigger from the CCP, the
configured write will take precedence.
The device will wake-up on an overflow and execute For more information, see Section 27.2.4 “Auto-Con-
the next instructions. If the GIE bit of the INTCON version Trigger”.
register is set, the device will call the Interrupt Service
Routine.
Secondary oscillator will continue to operate in Sleep
regardless of the T1SYNC bit setting.

FIGURE 25-2: TIMER1 INCREMENTING EDGE

T1CKI = 1
when TMR1
Enabled

T1CKI = 0
when TMR1
Enabled

Note 1: Arrows indicate counter increments.

2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.

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FIGURE 25-3: TIMER1 GATE ENABLE MODE

TMR1GE

T1GPOL

t1g_in

T1CKI

T1GVAL

Timer1 N N+1 N+2 N+3 N+4

FIGURE 25-4: TIMER1 GATE TOGGLE MODE

TMR1GE

T1GPOL

T1GTM

t1g_in

T1CKI

T1GVAL

Timer1 N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8

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FIGURE 25-5: TIMER1 GATE SINGLE-PULSE MODE

TMR1GE

T1GPOL

T1GSPM
Cleared by hardware on
T1GGO/ Set by software falling edge of T1GVAL
DONE
Counting enabled on
rising edge of T1G
t1g_in

T1CKI

T1GVAL

Timer1 N N+1 N+2

Cleared by
TMR1GIF Cleared by software Set by hardware on software
falling edge of T1GVAL

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FIGURE 25-6: TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE

TMR1GE

T1GPOL

T1GSPM

T1GTM

Cleared by hardware on
T1GGO/ Set by software falling edge of T1GVAL
DONE Counting enabled on
rising edge of T1G
t1g_in

T1CKI

T1GVAL

Timer1 N N+1 N+2 N+3 N+4

Set by hardware on Cleared by

TMR1GIF Cleared by software falling edge of T1GVAL software

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25.11 Register Definitions: Timer1 Control
T
REGISTER 25-1: T1CON: TIMER1 CONTROL REGISTER
R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u U-0 R/W-0/u
TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC — TMR1ON
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 TMR1CS<1:0>: Timer1 Clock Source Select bits

11 = LFINTOSC
10 = Timer1 clock source is pin or oscillator:
If T1OSCEN = 0:
External clock from T1CKI pin (on the rising edge)
If T1OSCEN = 1:
Crystal oscillator on SOSCI/SOSCO pins
01 = Timer1 clock source is system clock (FOSC)
00 = Timer1 clock source is instruction clock (FOSC/4)
bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 3 T1OSCEN: LP Oscillator Enable Control bit
1 = Dedicated secondary oscillator circuit enabled
0 = Dedicated secondary oscillator circuit disabled
bit 2 T1SYNC: Timer1 Synchronization Control bit
1 = Do not synchronize asynchronous clock input
0 = Synchronize asynchronous clock input with system clock (FOSC)
bit 1 Unimplemented: Read as ‘0’
bit 0 TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1 and clears Timer1 gate flip-flop

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REGISTER 25-2: T1GCON: TIMER1 GATE CONTROL REGISTER

R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W/HC-0/u R-x/x R/W-0/u R/W-0/u
TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS<1:0>
DONE
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware

bit 7 TMR1GE: Timer1 Gate Enable bit

If TMR1ON = 0:
This bit is ignored
If TMR1ON = 1:
1 = Timer1 counting is controlled by the Timer1 gate function
0 = Timer1 counts regardless of Timer1 gate function
bit 6 T1GPOL: Timer1 Gate Polarity bit
1 = Timer1 gate is active-high (Timer1 counts when gate is high)
0 = Timer1 gate is active-low (Timer1 counts when gate is low)
bit 5 T1GTM: Timer1 Gate Toggle Mode bit
1 = Timer1 Gate Toggle mode is enabled
0 = Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared
Timer1 gate flip-flop toggles on every rising edge.
bit 4 T1GSPM: Timer1 Gate Single-Pulse Mode bit
1 = Timer1 Gate Single-Pulse mode is enabled and is controlling Timer1 gate
0 = Timer1 Gate Single-Pulse mode is disabled
bit 3 T1GGO/DONE: Timer1 Gate Single-Pulse Acquisition Status bit
1 = Timer1 gate single-pulse acquisition is ready, waiting for an edge
0 = Timer1 gate single-pulse acquisition has completed or has not been started
bit 2 T1GVAL: Timer1 Gate Value Status bit
Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L
Unaffected by Timer1 Gate Enable (TMR1GE)
bit 1-0 T1GSS<1:0>: Timer1 Gate Source Select bits
11 = Comparator 2 optionally synchronized output (sync_C2OUT)
10 = Comparator 1 optionally synchronized output (sync_C1OUT)
01 = Timer0 overflow output
00 = Timer1 gate pin

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TABLE 25-5: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 122
CCP1CON — — DC1B<1:0> CCP1M<3:0> 267
CCP2CON — — DC2B<1:0> CCP2M<3:0> 267
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 85
PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 86
PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 89
TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 245*
TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register 245*
TRISA — — TRISA5 TRISA4 —(1) TRISA2 TRISA1 TRISA0 121
T1CON TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC — TMR1ON 253
T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS<1:0> 254
DONE
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the Timer1 module.
* Page provides register information.
Note 1: Unimplemented, read as ‘1’.

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26.0 TIMER2/4/6 MODULE
The Timer2/4/6 modules are 8-bit timers that
incorporate the following features:
• 8-bit Timer and Period registers (TMR2 and PR2,
respectively)
• Readable and writable (both registers)
• Software programmable prescaler (1:1, 1:4, 1:16,
and 1:64)
• Software programmable postscaler (1:1 to 1:16)
• Interrupt on TMR2 match with PR2, respectively
• Optional use as the shift clock for the MSSP
module
See Figure 26-1 for a block diagram of Timer2.
Three identical Timer2 modules are implemented on this
device. To maintain consistency with earlier devices, the
timers are named Timer2, Timer4, and Timer6. All
references to Timer2 apply as well to Timer4 and
Timer6.

FIGURE 26-1: TIMER2 BLOCK DIAGRAM

T2_match
Prescaler To Peripherals
TMR2 R
Fosc/4 1:1, 1:4, 1:16, 1:64

2
Postscaler set bit
T2CKPS<1:0> Comparator
1:1 to 1:16 TMR2IF

PR2 T2OUTPS<3:0>

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26.1 Timer2 Operation 26.3 Timer2 Output
The clock input to the Timer2 modules is the system The unscaled output of TMR2 is available primarily to
instruction clock (FOSC/4). the CCP modules, where it is used as a time base for
TMR2 increments from 00h on each clock edge. operations in PWM mode.

A 4-bit counter/prescaler on the clock input allows direct Timer2 can be optionally used as the shift clock source
input, divide-by-4 and divide-by-16 prescale options. for the MSSP module operating in SPI mode.
These options are selected by the prescaler control bits, Additional information is provided in Section 28.0
T2CKPS<1:0> of the T2CON register. The value of “Master Synchronous Serial Port (MSSP) Module”
TMR2 is compared to that of the Period register, PR2, on
each clock cycle. When the two values match, the 26.4 Timer2 Operation During Sleep
comparator generates a match signal as the timer
The Timer2 timers cannot be operated while the
output. This signal also resets the value of TMR2 to 00h
processor is in Sleep mode. The contents of the TMR2
on the next cycle and drives the output
and PR2 registers will remain unchanged while the
counter/postscaler (see Section 26.2 “Timer2
processor is in Sleep mode.
Interrupt”).
The TMR2 and PR2 registers are both directly readable
and writable. The TMR2 register is cleared on any
device Reset, whereas the PR2 register initializes to
FFh. Both the prescaler and postscaler counters are
cleared on the following events:
• a write to the TMR2 register
• a write to the T2CON register
• Power-on Reset (POR)
• Brown-out Reset (BOR)
• MCLR Reset
• Watchdog Timer (WDT) Reset
• Stack Overflow Reset
• Stack Underflow Reset
• RESET Instruction
Note: TMR2 is not cleared when T2CON is
written.

26.2 Timer2 Interrupt

Timer2 can also generate an optional device interrupt.
The Timer2 output signal (TMR2-to-PR2 match)
provides the input for the 4-bit counter/postscaler. This
counter generates the TMR2 match interrupt flag which
is latched in TMR2IF of the PIR1 register. The interrupt
is enabled by setting the TMR2 Match Interrupt Enable
bit, TMR2IE, of the PIE1 register.
A range of 16 postscale options (from 1:1 through 1:16
inclusive) can be selected with the postscaler control
bits, T2OUTPS<3:0>, of the T2CON register.

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26.5 Register Definitions: Timer2 Control

REGISTER 26-1: T2CON: TIMER2 CONTROL REGISTER

U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— T2OUTPS<3:0> TMR2ON T2CKPS<1:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 Unimplemented: Read as ‘0’

bit 6-3 T2OUTPS<3:0>: Timer2 Output Postscaler Select bits
1111 = 1:16 Postscaler
1110 = 1:15 Postscaler
1101 = 1:14 Postscaler
1100 = 1:13 Postscaler
1011 = 1:12 Postscaler
1010 = 1:11 Postscaler
1001 = 1:10 Postscaler
1000 = 1:9 Postscaler
0111 = 1:8 Postscaler
0110 = 1:7 Postscaler
0101 = 1:6 Postscaler
0100 = 1:5 Postscaler
0011 = 1:4 Postscaler
0010 = 1:3 Postscaler
0001 = 1:2 Postscaler
0000 = 1:1 Postscaler
bit 2 TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits
11 = Prescaler is 64
10 = Prescaler is 16
01 = Prescaler is 4
00 = Prescaler is 1

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TABLE 26-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
CCP2CON — — DC2B<1:0> CCP2M<3:0> 267
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 85
PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 86
PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 89
PR2 Timer2 Module Period Register 256*
T2CON — T2OUTPS<3:0> TMR2ON T2CKPS<1:0> 258
TMR2 Holding Register for the 8-bit TMR2 Register 256*
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Timer2 module.
* Page provides register information.

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26.6 CCP/PWM Clock Selection
The PIC16(L)F1704/8 allows each individual CCP and
PWM module to select the timer source that controls
the module. Each module has an independent
selection.
As there are up to three 8-bit timers with auto-reload
(Timer2, Timer4, and Timer6), PWM mode on the CCP
and PWM modules can use any of these timers.
The CCPTMRS register is used to select which timer is
used.

26.7 Register Definitions: CCP/PWM Timers Control

REGISTER 26-2: CCPTMRS: PWM TIMER SELECTION CONTROL REGISTER 0

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
P4TSEL<1:0> P3TSEL<1:0> C2TSEL<1:0> C1TSEL<1:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 P4TSEL<1:0>: PWM4 Timer Selection

11 = Reserved
10 = PWM4 is based off Timer6
01 = PWM4 is based off Timer4
00 = PWM4 is based off Timer2
bit 5-4 P3TSEL<1:0>: PWM3 Timer Selection
11 = Reserved
10 = PWM3 is based off Timer6
01 = PWM3 is based off Timer4
00 = PWM3 is based off Timer2
bit 3-2 C2TSEL<1:0>: CCP2 (PWM2) Timer Selection
11 = Reserved
10 = CCP2 is based off Timer6 in PWM mode
01 = CCP2 is based off Timer4 in PWM mode
00 = CCP2 is based off Timer2 in PWM mode
bit 1-0 C1TSEL<1:0>: CCP1 (PWM1) Timer Selection
11 = Reserved
10 = CCP1 is based off Timer6 in PWM mode
01 = CCP1 is based off Timer4 in PWM mode
00 = CCP1 is based off Timer2 in PWM mode

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27.0 CAPTURE/COMPARE/PWM Figure 27-1 shows a simplified diagram of the capture
operation.
MODULES
The Capture/Compare/PWM module is a peripheral 27.1.1 CCP PIN CONFIGURATION
which allows the user to time and control different In Capture mode, the CCPx pin should be configured
events, and to generate Pulse-Width Modulation as an input by setting the associated TRIS control bit.
(PWM) signals. In Capture mode, the peripheral allows
the timing of the duration of an event. The Compare Note: If the CCPx pin is configured as an output,
mode allows the user to trigger an external event when a write to the port can cause a capture
a predetermined amount of time has expired. The condition.
PWM mode can generate Pulse-Width Modulated
signals of varying frequency and duty cycle. FIGURE 27-1: CAPTURE MODE
This family of devices contains two standard OPERATION BLOCK
Capture/Compare/PWM modules (CCP1 and CCP2). DIAGRAM
Set Flag bit CCPxIF
The Capture and Compare functions are identical for all (PIRx register)
CCP modules. Prescaler
 1, 4, 16
Note 1: In devices with more than one CCP CCPx CCPRxH CCPRxL
module, it is very important to pay close pin

attention to the register names used. A and Capture

number placed after the module acronym Edge Detect Enable
is used to distinguish between separate TMR1H TMR1L
modules. For example, the CCP1CON CCPxM<3:0>
and CCP2CON control the same System Clock (FOSC)
operational aspects of two completely
different CCP modules.
2: Throughout this section, generic
references to a CCP module in any of its
operating modes may be interpreted as
being equally applicable to CCPx module.
Register names, module signals, I/O pins,
and bit names may use the generic
designator ‘x’ to indicate the use of a
numeral to distinguish a particular module,
when required.

27.1 Capture Mode

The Capture mode function described in this section is
available and identical for all CCP modules.
Capture mode makes use of the 16-bit Timer1
resource. When an event occurs on the CCPx pin, the
16-bit CCPRxH:CCPRxL register pair captures and
stores the 16-bit value of the TMR1H:TMR1L register
pair, respectively. An event is defined as one of the
following and is configured by the CCPxM<3:0> bits of
the CCPxCON register:
• Every falling edge
• Every rising edge
• Every 4th rising edge
• Every 16th rising edge
When a capture is made, the Interrupt Request Flag bit
CCPxIF of the PIRx register is set. The interrupt flag
must be cleared in software. If another capture occurs
before the value in the CCPRxH, CCPRxL register pair
is read, the old captured value is overwritten by the new
captured value.

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27.1.2 TIMER1 MODE RESOURCE 27.1.5 CAPTURE DURING SLEEP
Timer1 must be running in Timer mode or Synchronized Capture mode depends upon the Timer1 module for
Counter mode for the CCP module to use the capture proper operation. There are two options for driving the
feature. In Asynchronous Counter mode, the capture Timer1 module in Capture mode. It can be driven by the
operation may not work. instruction clock (FOSC/4), or by an external clock source.
See Section 25.0 “Timer1 Module with Gate When Timer1 is clocked by FOSC/4, Timer1 will not
Control” for more information on configuring Timer1. increment during Sleep. When the device wakes from
Sleep, Timer1 will continue from its previous state.
27.1.3 SOFTWARE INTERRUPT MODE
Capture mode will operate during Sleep when Timer1
When the Capture mode is changed, a false capture is clocked by an external clock source.
interrupt may be generated. The user should keep the
CCPxIE interrupt enable bit of the PIEx register clear to 27.2 Compare Mode
avoid false interrupts. Additionally, the user should
clear the CCPxIF interrupt flag bit of the PIRx register The Compare mode function described in this section
following any change in Operating mode. is available and identical for all CCP modules.
Note: Clocking Timer1 from the system clock Compare mode makes use of the 16-bit Timer1
(FOSC) should not be used in Capture resource. The 16-bit value of the CCPRxH:CCPRxL
mode. In order for Capture mode to register pair is constantly compared against the 16-bit
recognize the trigger event on the CCPx value of the TMR1H:TMR1L register pair. When a
pin, Timer1 must be clocked from the match occurs, one of the following events can occur:
instruction clock (FOSC/4) or from an • Toggle the CCPx output
external clock source. • Set the CCPx output
• Clear the CCPx output
27.1.4 CCP PRESCALER
• Generate an Auto-conversion Trigger
There are four prescaler settings specified by the • Generate a Software Interrupt
CCPxM<3:0> bits of the CCPxCON register. Whenever
the CCP module is turned off, or the CCP module is not The action on the pin is based on the value of the
in Capture mode, the prescaler counter is cleared. Any CCPxM<3:0> control bits of the CCPxCON register. At
Reset will clear the prescaler counter. the same time, the interrupt flag CCPxIF bit is set.
Switching from one capture prescaler to another does not All Compare modes can generate an interrupt.
clear the prescaler and may generate a false interrupt. To Figure 27-2 shows a simplified diagram of the compare
avoid this unexpected operation, turn the module off by operation.
clearing the CCPxCON register before changing the
prescaler. Example 27-1 demonstrates the code to FIGURE 27-2: COMPARE MODE
perform this function. OPERATION BLOCK
DIAGRAM
EXAMPLE 27-1: CHANGING BETWEEN
CAPTURE PRESCALERS CCPxM<3:0>
Mode Select
BANKSEL CCPxCON ;Set Bank bits to point
;to CCPxCON Set CCPxIF Interrupt Flag
CLRF CCPxCON ;Turn CCP module off (PIRx)
CCPx 4
MOVLW NEW_CAPT_PS ;Load the W reg with CCPRxH CCPRxL
Pin
;the new prescaler
;move value and CCP ON Q S
Output Comparator
MOVWF CCPxCON ;Load CCPxCON with this R Logic Match
;value
TMR1H TMR1L
TRIS
Output Enable

Auto-conversion Trigger

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27.2.1 CCPX PIN CONFIGURATION Refer to Section 20.2.5 “Auto-Conversion Trigger”
for more information.
The user must configure the CCPx pin as an output by
clearing the associated TRIS bit. Note 1: The Auto-conversion Trigger from the
CCP module does not set interrupt flag
Note: Clearing the CCPxCON register will force
bit TMR1IF of the PIR1 register.
the CCPx compare output latch to the
default low level. This is not the PORT I/O 2: Removing the match condition by
data latch. changing the contents of the CCPRxH
and CCPRxL register pair, between the
27.2.2 TIMER1 MODE RESOURCE clock edge that generates the
In Compare mode, Timer1 must be running in either Auto-conversion Trigger and the clock
Timer mode or Synchronized Counter mode. The edge that generates the Timer1 Reset,
compare operation may not work in Asynchronous will preclude the Reset from occurring.
Counter mode.
27.2.5 COMPARE DURING SLEEP
See Section 25.0 “Timer1 Module with Gate Control”
The Compare mode is dependent upon the system
for more information on configuring Timer1.
clock (FOSC) for proper operation. Since FOSC is shut
Note: Clocking Timer1 from the system clock down during Sleep mode, the Compare mode will not
(FOSC) should not be used in Compare function properly during Sleep.
mode. In order for Compare mode to
recognize the trigger event on the CCPx 27.3 PWM Overview
pin, TImer1 must be clocked from the
instruction clock (FOSC/4) or from an Pulse-Width Modulation (PWM) is a scheme that
external clock source. provides power to a load by switching quickly between
fully on and fully off states. The PWM signal resembles
27.2.3 SOFTWARE INTERRUPT MODE a square wave where the high portion of the signal is
considered the on state and the low portion of the signal
When Generate Software Interrupt mode is chosen is considered the off state. The high portion, also known
(CCPxM<3:0> = 1010), the CCPx module does not as the pulse width, can vary in time and is defined in
assert control of the CCPx pin (see the CCPxCON steps. A larger number of steps applied, which
register). lengthens the pulse width, also supplies more power to
the load. Lowering the number of steps applied, which
27.2.4 AUTO-CONVERSION TRIGGER
shortens the pulse width, supplies less power. The
When Auto-conversion Trigger mode is chosen PWM period is defined as the duration of one complete
(CCPxM<3:0> = 1011), the CCPx module does the cycle or the total amount of on and off time combined.
following:
PWM resolution defines the maximum number of steps
• Resets Timer1 that can be present in a single PWM period. A higher
• Starts an ADC conversion if ADC is enabled resolution allows for more precise control of the pulse
width time and in turn the power that is applied to the
The CCPx module does not assert control of the CCPx
load.
pin in this mode.
The term duty cycle describes the proportion of the on
The Auto-conversion Trigger output of the CCP occurs
time to the off time and is expressed in percentages,
immediately upon a match between the TMR1H,
where 0% is fully off and 100% is fully on. A lower duty
TMR1L register pair and the CCPRxH, CCPRxL
cycle corresponds to less power applied and a higher
register pair. The TMR1H, TMR1L register pair is not
duty cycle corresponds to more power applied.
reset until the next rising edge of the Timer1 clock. The
Auto-conversion Trigger output starts an ADC Figure 27-3 shows a typical waveform of the PWM
conversion (if the ADC module is enabled). This allows signal.
the CCPRxH, CCPRxL register pair to effectively
provide a 16-bit programmable period register for
Timer1.

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27.3.1 STANDARD PWM OPERATION 27.3.2 SETUP FOR PWM OPERATION
The standard PWM function described in this section is The following steps should be taken when configuring
available and identical for all CCP modules. the CCP module for standard PWM operation:
The standard PWM mode generates a Pulse-Width 1. Use the desired output pin RxyPPS control to
Modulation (PWM) signal on the CCPx pin with up to 10 select CCPx as the source and disable the
bits of resolution. The period, duty cycle, and resolution CCPx pin output driver by setting the associated
are controlled by the following registers: TRIS bit.
• PR2 registers 2. Load the PR2 register with the PWM period
• T2CON registers value.
• CCPRxL registers 3. Configure the CCP module for the PWM mode
by loading the CCPxCON register with the
• CCPxCON registers
appropriate values.
Figure 27-4 shows a simplified block diagram of PWM 4. Load the CCPRxL register and the DCxBx bits
operation. of the CCPxCON register, with the PWM duty
cycle value.
5. Configure and start Timer2:
Note: The corresponding TRIS bit must be
cleared to enable the PWM output on the • Clear the TMR2IF interrupt flag bit of the
CCPx pin. PIRx register. See Note below.
• Configure the T2CKPS bits of the T2CON
register with the Timer prescale value.
FIGURE 27-3: CCP PWM OUTPUT SIGNAL
• Enable the Timer by setting the TMR2ON
Period bit of the T2CON register.
6. Enable PWM output pin:
Pulse Width
TMR2 = PR2 • Wait until the Timer overflows and the
TMR2IF bit of the PIR1 register is set. See
TMR2 = CCPRxH:CCPxCON<5:4> Note below.
TMR2 = 0 • Enable the CCPx pin output driver by
clearing the associated TRIS bit.
Note: In order to send a complete duty cycle and
FIGURE 27-4: SIMPLIFIED PWM BLOCK period on the first PWM output, the above
DIAGRAM steps must be included in the setup
CCP1CON<5:4>
sequence. If it is not critical to start with a
Duty Cycle Registers complete PWM signal on the first output,
then step 6 may be ignored.
CCPR1L

27.3.3 TIMER2 TIMER RESOURCE

The PWM standard mode makes use of the 8-bit
CCPR1H(2) (Slave) Timer2 timer resources to specify the PWM period.
CCP1

Comparator R Q 27.3.4 PWM PERIOD

The PWM period is specified by the PR2 register of
TMR2 (1) S Timer2. The PWM period can be calculated using the
TRIS formula of Equation 27-1.

Comparator EQUATION 27-1: PWM PERIOD

Clear Timer,
toggle CCP1 pin and
PR2
latch duty cycle PWM Period =   PR2  + 1   4  T OSC 
(TMR2 Prescale Value)
Note 1: The 8-bit timer TMR2 register is
concatenated with the 2-bit internal system Note 1: TOSC = 1/FOSC
clock (FOSC), or two bits of the prescaler, to
create the 10-bit time base.
2: In PWM mode, CCPR1H is a read-only
register.

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When TMR2 is equal to PR2, the following three events 27.3.6 PWM RESOLUTION
occur on the next increment cycle:
The resolution determines the number of available duty
• TMR2 is cleared cycles for a given period. For example, a 10-bit resolution
• The CCPx pin is set. (Exception: If the PWM duty will result in 1024 discrete duty cycles, whereas an 8-bit
cycle = 0%, the pin will not be set.) resolution will result in 256 discrete duty cycles.
• The PWM duty cycle is latched from CCPRxL into The maximum PWM resolution is ten bits when PR2 is
CCPRxH. 255. The resolution is a function of the PR2 register
value as shown by Equation 27-4.
Note: The Timer postscaler (see Section 26.1
“Timer2 Operation”) is not used in the EQUATION 27-4: PWM RESOLUTION
determination of the PWM frequency.
log  4  PR2 + 1  
27.3.5 PWM DUTY CYCLE Resolution = ------------------------------------------ bits
log  2 
The PWM duty cycle is specified by writing a 10-bit
value to multiple registers: CCPRxL register and
DCxB<1:0> bits of the CCPxCON register. The Note: If the pulse width value is greater than the
CCPRxL contains the eight MSbs and the DCxB<1:0> period the assigned PWM pin(s) will
bits of the CCPxCON register contain the two LSbs. remain unchanged.
CCPRxL and DCxB<1:0> bits of the CCPxCON
register can be written to at any time. The duty cycle
value is not latched into CCPRxH until after the period
completes (i.e., a match between PR2 and TMR2
registers occurs). While using the PWM, the CCPRxH
register is read-only.
Equation 27-2 is used to calculate the PWM pulse
width.
Equation 27-3 is used to calculate the PWM duty cycle
ratio.

EQUATION 27-2: PULSE WIDTH

Pulse Width =  CCPRxL:CCPxCON<5:4>  

T OSC  (TMR2 Prescale Value)

EQUATION 27-3: DUTY CYCLE RATIO

 CCPRxL:CCPxCON<5:4> 
Duty Cycle Ratio = -----------------------------------------------------------------------
4  PR2 + 1 

The CCPRxH register and a 2-bit internal latch are

used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
The 8-bit timer TMR2 register is concatenated with
either the 2-bit internal system clock (FOSC), or two bits
of the prescaler, to create the 10-bit time base. The
system clock is used if the Timer2 prescaler is set to 1:1.
When the 10-bit time base matches the CCPRxH and
2-bit latch, then the CCPx pin is cleared (see
Figure 27-4).

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TABLE 27-1: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)
PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz
Timer Prescale 16 4 1 1 1 1
PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17
Maximum Resolution (bits) 10 10 10 8 7 6.6

TABLE 27-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz)

PWM Frequency 1.22 kHz 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz
Timer Prescale 16 4 1 1 1 1
PR2 Value 0x65 0x65 0x65 0x19 0x0C 0x09
Maximum Resolution (bits) 8 8 8 6 5 5

27.3.7 OPERATION IN SLEEP MODE 27.3.9 EFFECTS OF RESET

In Sleep mode, the TMR2 register will not increment Any Reset will force all ports to Input mode and the
and the state of the module will not change. If the CCPx CCP registers to their Reset states.
pin is driving a value, it will continue to drive that value.
When the device wakes up, TMR2 will continue from its
previous state.

27.3.8 CHANGES IN SYSTEM CLOCK

FREQUENCY
The PWM frequency is derived from the system clock
frequency. Any changes in the system clock frequency
will result in changes to the PWM frequency. See
Section 6.0 “Oscillator Module (with Fail-Safe
Clock Monitor)” for additional details.

TABLE 27-3: SUMMARY OF REGISTERS ASSOCIATED WITH STANDARD PWM

Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
CCP1CON — — DC1B<1:0> CCP1M<3:0> 267
CCPR1L Capture/Compare/PWM Register 1 (LSB) 265*
CCPTMRS P4TSEL<1:0> P3TSEL<1:0> C2TSEL<1:0> C1TSEL<1:0> 260
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 85
PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 86
PIE2 OSFIE C2IE C1IE — BCL1IE TMR6IE TMR4IE CCP2IE 87
PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 89
PIR2 OSFIF C2IF C1IF — BCL1IF TMR6IF TMR4IF CCP2IF 90
PR2 Timer2 Period Register 256*
RxyPPS — — — RxyPPS<4:0> 140
T2CON — T2OUTPS<3:0> TMR2ON T2CKPS<1:0> 258
TMR2 Timer2 Module Register 256
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the PWM.
* Page provides register information.
Note 1: Unimplemented, read as ‘1’.

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27.4 Register Definitions: CCP Control

REGISTER 27-1: CCPxCON: CCPx CONTROL REGISTER

U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — DCxB<1:0> CCPxM<3:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4 DCxB<1:0>: PWM Duty Cycle Least Significant bits
Capture mode:
Unused
Compare mode:
Unused
PWM mode:
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.
bit 3-0 CCPxM<3:0>: CCPx Mode Select bits
11xx = PWM mode

1011 = Compare mode: Auto-conversion Trigger (sets CCPxIF bit), starts ADC conversion if
TRIGSEL = CCPx (see Register 20-3)
1010 = Compare mode: generate software interrupt only
1001 = Compare mode: clear output on compare match (set CCPxIF)
1000 = Compare mode: set output on compare match (set CCPxIF)

0111 = Capture mode: every 16th rising edge

0110 = Capture mode: every 4th rising edge
0101 = Capture mode: every rising edge
0100 = Capture mode: every falling edge

0011 = Reserved
0010 = Compare mode: toggle output on match
0001 = Reserved
0000 = Capture/Compare/PWM off (resets CCPx module)

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28.0 MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
28.1 MSSP Module Overview
The Master Synchronous Serial Port (MSSP) module is
a serial interface useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers,
display drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I2C)
The SPI interface supports the following modes and
features:
• Master mode
• Slave mode
• Clock Parity
• Slave Select Synchronization (Slave mode only)
• Daisy-chain connection of slave devices
Figure 28-1 is a block diagram of the SPI interface
module.

FIGURE 28-1: MSSP BLOCK DIAGRAM (SPI MODE)

Data Bus
Read Write

SSPBUF Reg

SDI
SSPSR Reg
SDO bit 0 Shift
Clock

SS SS Control 2 (CKP, CKE)

Enable Clock Select

Edge
Select

SSPM<3:0>
4
( T2_match
2
)
SCK
Edge Prescaler TOSC
Select 4, 16, 64

Baud Rate
Generator
TRIS bit (SSPADD)

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The I2C interface supports the following modes and
features:
• Master mode
• Slave mode
• Byte NACKing (Slave mode)
• Limited multi-master support
• 7-bit and 10-bit addressing
• Start and Stop interrupts
• Interrupt masking
• Clock stretching
• Bus collision detection
• General call address matching
• Address masking
• Address Hold and Data Hold modes
• Selectable SDA hold times
Figure 28-2 is a block diagram of the I2C interface
module in Master mode. Figure 28-3 is a diagram of the
I2C interface module in Slave mode.

FIGURE 28-2: MSSP BLOCK DIAGRAM (I2C MASTER MODE)

Internal
data bus [SSPM<3:0>]
Read Write

SSP1BUF Baud Rate

Generator
(SSPADD)
SDA Shift
SDA in Clock

Clock arbitrate/BCOL detect

SSPSR
Clock Cntl

(Hold off clock source)

MSb LSb
Receive Enable (RCEN)

Start bit, Stop bit,

Acknowledge
Generate (SSPCON2)
SCL

Start bit detect,

Stop bit detect
SCL in Write collision detect Set/Reset: S, P, SSPSTAT, WCOL, SSPOV
Clock arbitration Reset SEN, PEN (SSPCON2)
Bus Collision State counter for Set SSP1IF, BCL1IF
end of XMIT/RCV
Address Match detect

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FIGURE 28-3: MSSP BLOCK DIAGRAM (I2C SLAVE MODE)

Internal
Data Bus

Read Write

SCL SSPBUF Reg

Shift
Clock

SSPSR Reg
SDA MSb LSb

SSPMSK Reg

Match Detect Addr Match

SSPADD Reg

Start and Set, Reset

Stop bit Detect S, P bits
(SSPSTAT Reg)

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28.2 SPI Mode Overview During each SPI clock cycle, a full-duplex data
transmission occurs. This means that while the master
The Serial Peripheral Interface (SPI) bus is a device is sending out the MSb from its shift register (on
synchronous serial data communication bus that its SDO pin) and the slave device is reading this bit and
operates in Full-Duplex mode. Devices communicate saving it as the LSb of its shift register, that the slave
in a master/slave environment where the master device device is also sending out the MSb from its shift register
initiates the communication. A slave device is (on its SDO pin) and the master device is reading this
controlled through a Chip Select known as Slave bit and saving it as the LSb of its shift register.
Select.
After eight bits have been shifted out, the master and
The SPI bus specifies four signal connections: slave have exchanged register values.
• Serial Clock (SCK) If there is more data to exchange, the shift registers are
• Serial Data Out (SDO) loaded with new data and the process repeats itself.
• Serial Data In (SDI) Whether the data is meaningful or not (dummy data),
• Slave Select (SS) depends on the application software. This leads to
Figure 28-1 shows the block diagram of the MSSP three scenarios for data transmission:
module when operating in SPI mode. • Master sends useful data and slave sends dummy
The SPI bus operates with a single master device and data.
one or more slave devices. When multiple slave • Master sends useful data and slave sends useful
devices are used, an independent Slave Select data.
connection is required from the master device to each • Master sends dummy data and slave sends useful
slave device. data.
Figure 28-4 shows a typical connection between a Transmissions may involve any number of clock
master device and multiple slave devices. cycles. When there is no more data to be transmitted,
The master selects only one slave at a time. Most slave the master stops sending the clock signal and it
devices have tri-state outputs so their output signal deselects the slave.
appears disconnected from the bus when they are not Every slave device connected to the bus that has not
selected. been selected through its slave select line must disre-
Transmissions involve two shift registers, eight bits in gard the clock and transmission signals and must not
size, one in the master and one in the slave. With either transmit out any data of its own.
the master or the slave device, data is always shifted
out one bit at a time, with the Most Significant bit (MSb)
shifted out first. At the same time, a new Least
Significant bit (LSb) is shifted into the same register.
Figure 28-5 shows a typical connection between two
processors configured as master and slave devices.
Data is shifted out of both shift registers on the
programmed clock edge and latched on the opposite
edge of the clock.
The master device transmits information out on its SDO
output pin which is connected to, and received by, the
slave’s SDI input pin. The slave device transmits
information out on its SDO output pin, which is
connected to, and received by, the master’s SDI input
pin.
To begin communication, the master device first sends
out the clock signal. Both the master and the slave
devices should be configured for the same clock
polarity.
The master device starts a transmission by sending out
the MSb from its shift register. The slave device reads
this bit from that same line and saves it into the LSb
position of its shift register.

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FIGURE 28-4: SPI MASTER AND MULTIPLE SLAVE CONNECTION

SCK SCK
SPI Master
SDO SDI SPI Slave
SDI SDO #1
General I/O SS
General I/O
General I/O SCK
SDI SPI Slave
SDO #2
SS

SCK
SDI SPI Slave
SDO #3
SS

28.2.1 SPI MODE REGISTERS

The MSSP module has five registers for SPI mode

operation. These are:
• MSSP STATUS register, SSPxSTAT (global)
• MSSP Control register 1, SSPxCON1 (global)
• MSSP Control register 3, SSPxCON3 (global)
• MSSP Data Buffer register, SSPxBUF (global)
• MSSP Address register, SSPxADD (global)
• MSSP Shift register (SSPSR)
(Not directly accessible)
SSPCON1 and SSPSTAT are the control and STATUS
registers in SPI mode operation. The SSPCON1
register is readable and writable. The lower six bits of
the SSPSTAT are read-only. The upper two bits of the
SSPSTAT are read/write.
In one SPI master mode, SSPADD can be loaded with
a value used in the Baud Rate Generator. More
information on the Baud Rate Generator is available in
Section 28.7 “Baud Rate Generator”.
SSPSR is the shift register used for shifting data in and
out. SSPBUF provides indirect access to the SSPSR
register. SSPBUF is the buffer register to which data
bytes are written, and from which data bytes are read.
In receive operations, SSPSR and SSPBUF together
create a buffered receiver. When SSPSR receives a
complete byte, it is transferred to SSPBUF and the
SSPIF interrupt is set.
During transmission, the SSPBUF is not buffered. A
write to SSPBUF will write to both SSPBUF and
SSPSR.

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28.2.2 SPI MODE OPERATION When the application software is expecting to receive
valid data, the SSPBUF should be read before the next
When initializing the SPI, several options need to be byte of data to transfer is written to the SSPBUF. The
specified. This is done by programming the appropriate Buffer Full bit, BF of the SSPSTAT register, indicates
control bits (SSPCON1<5:0> and SSPSTAT<7:6>). when SSPBUF has been loaded with the received data
These control bits allow the following to be specified: (transmission is complete). When the SSPBUF is read,
• Master mode (SCK is the clock output) the BF bit is cleared. This data may be irrelevant if the
• Slave mode (SCK is the clock input) SPI is only a transmitter. Generally, the MSSP interrupt
• Clock Polarity (Idle state of SCK) is used to determine when the transmission/reception
has completed. If the interrupt method is not going to
• Data Input Sample Phase (middle or end of data
be used, then software polling can be done to ensure
output time)
that a write collision does not occur.
• Clock Edge (output data on rising/falling edge of
SCK) The SSPSR is not directly readable or writable and can
only be accessed by addressing the SSPBUF register.
• Clock Rate (Master mode only)
Additionally, the SSPSTAT register indicates the
• Slave Select mode (Slave mode only) various Status conditions.
To enable the serial port, SSP Enable bit, SSPEN of the
SSPCON1 register, must be set. To reset or
reconfigure SPI mode, clear the SSPEN bit, re-initialize
the SSPCONx registers and then set the SSPEN bit.
This configures the SDI, SDO, SCK and SS pins as
serial port pins. For the pins to behave as the serial port
function, some must have their data direction bits (in
the TRIS register) appropriately programmed as
follows:
• SDI must have corresponding TRIS bit set
• SDO must have corresponding TRIS bit cleared
• SCK (Master mode) must have corresponding
TRIS bit cleared
• SCK (Slave mode) must have corresponding
TRIS bit set
• SS must have corresponding TRIS bit set
Any serial port function that is not desired may be
overridden by programming the corresponding data
direction (TRIS) register to the opposite value.
The MSSP consists of a transmit/receive shift register
(SSPSR) and a buffer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF holds the data that was written to the SSPSR
until the received data is ready. Once the eight bits of
data have been received, that byte is moved to the
SSPBUF register. Then, the Buffer Full Detect bit, BF
of the SSPSTAT register, and the interrupt flag bit,
SSPIF, are set. This double-buffering of the received
data (SSPBUF) allows the next byte to start reception
before reading the data that was just received. Any
write to the SSPBUF register during
transmission/reception of data will be ignored and the
write collision detect bit WCOL of the SSPCON1
register, will be set. User software must clear the
WCOL bit to allow the following write(s) to the SSPBUF
register to complete successfully.

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FIGURE 28-5: SPI MASTER/SLAVE CONNECTION

SPI Master SSPM<3:0> = 00xx SPI Slave SSPM<3:0> = 010x

= 1010
SDO SDI

Serial Input Buffer Serial Input Buffer

(BUF) (SSPBUF)

Shift Register SDI SDO Shift Register

(SSPSR) (SSPSR)
MSb LSb MSb LSb
Serial Clock
SCK SCK

Slave Select
General I/O SS
Processor 1 (optional) Processor 2

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28.2.3 SPI MASTER MODE The clock polarity is selected by appropriately
programming the CKP bit of the SSPCON1 register
The master can initiate the data transfer at any time
and the CKE bit of the SSPSTAT register. This then,
because it controls the SCK line. The master
would give waveforms for SPI communication as
determines when the slave (Processor 2, Figure 28-5)
shown in Figure 28-6, Figure 28-8, Figure 28-9 and
is to broadcast data by the software protocol.
Figure 28-10, where the MSB is transmitted first. In
In Master mode, the data is transmitted/received as Master mode, the SPI clock rate (bit rate) is user
soon as the SSPBUF register is written to. If the SPI is programmable to be one of the following:
only going to receive, the SDO output could be
• FOSC/4 (or TCY)
disabled (programmed as an input). The SSPSR
register will continue to shift in the signal present on the • FOSC/16 (or 4 * TCY)
SDI pin at the programmed clock rate. As each byte is • FOSC/64 (or 16 * TCY)
received, it will be loaded into the SSPBUF register as • Timer2 output/2
if a normal received byte (interrupts and Status bits • FOSC/(4 * (SSPADD + 1))
appropriately set).
Figure 28-6 shows the waveforms for Master mode.
When the CKE bit is set, the SDO data is valid before
there is a clock edge on SCK. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPBUF is loaded with the received
data is shown.
Note: In Master mode the clock signal output to
the SCK pin is also the clock signal input
to the peripheral. The pin selected for
output with the RxyPPS register must also
be selected as the peripheral input with
the SSPCLKPPS register.

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FIGURE 28-6: SPI MODE WAVEFORM (MASTER MODE)

Write to
SSPBUF

SCK
(CKP = 0
CKE = 0)

SCK
(CKP = 1
CKE = 0)
4 Clock
SCK Modes
(CKP = 0
CKE = 1)

SCK
(CKP = 1
CKE = 1)

SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

(CKE = 0)
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
(CKE = 1)
SDI
(SMP = 0) bit 7 bit 0
Input
Sample
(SMP = 0)
SDI
(SMP = 1) bit 0
bit 7

Input
Sample
(SMP = 1)
SSPIF

SSPSR to
SSPBUF

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28.2.4 SPI SLAVE MODE 28.2.5 SLAVE SELECT
In Slave mode, the data is transmitted and received as SYNCHRONIZATION
external clock pulses appear on SCK. When the last The Slave Select can also be used to synchronize
bit is latched, the SSPIF interrupt flag bit is set. communication. The Slave Select line is held high until
Before enabling the module in SPI Slave mode, the clock the master device is ready to communicate. When the
line must match the proper Idle state. The clock line can Slave Select line is pulled low, the slave knows that a
be observed by reading the SCK pin. The Idle state is new transmission is starting.
determined by the CKP bit of the SSPCON1 register. If the slave fails to receive the communication properly,
While in Slave mode, the external clock is supplied by it will be reset at the end of the transmission, when the
the external clock source on the SCK pin. This external Slave Select line returns to a high state. The slave is
clock must meet the minimum high and low times as then ready to receive a new transmission when the
specified in the electrical specifications. Slave Select line is pulled low again. If the Slave Select
line is not used, there is a risk that the slave will
While in Sleep mode, the slave can transmit/receive
eventually become out of sync with the master. If the
data. The shift register is clocked from the SCK pin
slave misses a bit, it will always be one bit off in future
input and when a byte is received, the device will
transmissions. Use of the Slave Select line allows the
generate an interrupt. If enabled, the device will
slave and master to align themselves at the beginning
wake-up from Sleep.
of each transmission.
28.2.4.1 Daisy-Chain Configuration The SS pin allows a Synchronous Slave mode. The
SPI must be in Slave mode with SS pin control enabled
The SPI bus can sometimes be connected in a
(SSPCON1<3:0> = 0100).
daisy-chain configuration. The first slave output is
connected to the second slave input, the second slave When the SS pin is low, transmission and reception are
output is connected to the third slave input, and so on. enabled and the SDO pin is driven.
The final slave output is connected to the master input. When the SS pin goes high, the SDO pin is no longer
Each slave sends out, during a second group of clock driven, even if in the middle of a transmitted byte and
pulses, an exact copy of what was received during the becomes a floating output. External pull-up/pull-down
first group of clock pulses. The whole chain acts as resistors may be desirable depending on the
one large communication shift register. The application.
daisy-chain feature only requires a single Slave Select
line from the master device. Note 1: When the SPI is in Slave mode with SS pin
control enabled (SSPCON1<3:0> =
Figure 28-7 shows the block diagram of a typical
0100), the SPI module will reset if the SS
daisy-chain connection when operating in SPI mode.
pin is set to VDD.
In a daisy-chain configuration, only the most recent
2: When the SPI is used in Slave mode with
byte on the bus is required by the slave. Setting the
CKE set; the user must enable SS pin
BOEN bit of the SSPCON3 register will enable writes
control.
to the SSPBUF register, even if the previous byte has
not been read. This allows the software to ignore data 3: While operated in SPI Slave mode the
that may not apply to it. SMP bit of the SSPSTAT register must
remain clear.
When the SPI module resets, the bit counter is forced
to ‘0’. This can be done by either forcing the SS pin to
a high level or clearing the SSPEN bit.

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FIGURE 28-7: SPI DAISY-CHAIN CONNECTION

SCK SCK
SPI Master
SDO SDI SPI Slave
SDI SDO #1
General I/O SS

SCK
SDI SPI Slave
SDO #2
SS

SCK
SDI SPI Slave
SDO #3
SS

FIGURE 28-8: SLAVE SELECT SYNCHRONOUS WAVEFORM

SS

SCK
(CKP = 0
CKE = 0)

SCK
(CKP = 1
CKE = 0)

Write to
SSPBUF
Shift register SSPSR
and bit count are reset
SSPBUF to
SSPSR

SDO bit 7 bit 6 bit 7 bit 6 bit 0

SDI bit 0
bit 7 bit 7
Input
Sample

SSPIF
Interrupt
Flag

SSPSR to
SSPBUF

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 PIC16(L)F1704/8
FIGURE 28-9: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)

SS
Optional

SCK
(CKP = 0
CKE = 0)

SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
Valid
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

SDI
bit 7 bit 0
Input
Sample

SSPIF
Interrupt
Flag
SSPSR to
SSPBUF

Write Collision
detection active

FIGURE 28-10: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)

SS
Not Optional

SCK
(CKP = 0
CKE = 1)

SCK
(CKP = 1
CKE = 1)
Write to
SSPBUF
Valid
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

SDI
bit 7 bit 0
Input
Sample

SSPIF
Interrupt
Flag

SSPSR to
SSPBUF

Write Collision
detection active

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28.2.6 SPI OPERATION IN SLEEP MODE In SPI Master mode, when the Sleep mode is selected,
all module clocks are halted and the
In SPI Master mode, module clocks may be operating transmission/reception will remain in that state until the
at a different speed than when in Full-Power mode; in device wakes. After the device returns to Run mode,
the case of the Sleep mode, all clocks are halted. the module will resume transmitting and receiving data.
Special care must be taken by the user when the MSSP In SPI Slave mode, the SPI Transmit/Receive Shift
clock is much faster than the system clock. register operates asynchronously to the device. This
In Slave mode, when MSSP interrupts are enabled, allows the device to be placed in Sleep mode and data
after the master completes sending data, an MSSP to be shifted into the SPI Transmit/Receive Shift
interrupt will wake the controller from Sleep. register. When all eight bits have been received, the
If an exit from Sleep mode is not desired, MSSP MSSP interrupt flag bit will be set and if enabled, will
interrupts should be disabled. wake the device.

TABLE 28-1: SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION

Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page

ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 122

ANSELC ANSC7(2) ANSC6(2) ANSC5(3) ANSC4(3) ANSC3 ANSC2 ANSC1 ANSC0 133
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 85
PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 86
PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 89
RxyPPS — — — RxyPPS<4:0> 140
SSPCLKPPS — — — SSPCLKPPS<4:0> 138, 139
SSPDATPPS — — — SSPDATPPS<4:0> 138, 139
SSPSSPPS — — — SSPSSPPS<4:0> 138, 139
SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register 272*
SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 319
SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 317
SSP1STAT SMP CKE D/A P S R/W UA BF 317
TRISA — — TRISA5 TRISA4 —(1) TRISA2 TRISA1 TRISA0 121
TRISB(2) TRISB7 TRISB6 TRISB5 TRISB4 — — — — 127
TRISC TRISC7(2) TRISC6(2) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISA0 132
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode.
* Page provides register information.
Note 1: Unimplemented, read as ‘1’.
2: PIC16(L)F1708 only.
3: PIC16(L)F1704 only.

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28.3 I2C MODE OVERVIEW FIGURE 28-11: I2C MASTER/
SLAVE CONNECTION
The Inter-Integrated Circuit (I2C) bus is a multi-master
serial data communication bus. Devices communicate
in a master/slave environment where the master VDD
devices initiate the communication. A slave device is
controlled through addressing. SCL SCL
The I2C bus specifies two signal connections:
VDD
• Serial Clock (SCL) Master Slave
• Serial Data (SDA)
SDA SDA
Figure 28-11 shows the block diagram of the MSSP
module when operating in I2C mode.
Both the SCL and SDA connections are bidirectional
open-drain lines, each requiring pull-up resistors for the The Acknowledge bit (ACK) is an active-low signal,
supply voltage. Pulling the line to ground is considered which holds the SDA line low to indicate to the
a logical zero and letting the line float is considered a transmitter that the slave device has received the
logical one. transmitted data and is ready to receive more.
Figure 28-11 shows a typical connection between two The transition of a data bit is always performed while
processors configured as master and slave devices. the SCL line is held low. Transitions that occur while the
The I2C bus can operate with one or more master SCL line is held high are used to indicate Start and Stop
devices and one or more slave devices. bits.
There are four potential modes of operation for a given If the master intends to write to the slave, then it
device: repeatedly sends out a byte of data, with the slave
responding after each byte with an ACK bit. In this
• Master Transmit mode
example, the master device is in Master Transmit mode
(master is transmitting data to a slave)
and the slave is in Slave Receive mode.
• Master Receive mode
(master is receiving data from a slave) If the master intends to read from the slave, then it
repeatedly receives a byte of data from the slave, and
• Slave Transmit mode
responds after each byte with an ACK bit. In this
(slave is transmitting data to a master)
example, the master device is in Master Receive mode
• Slave Receive mode and the slave is Slave Transmit mode.
(slave is receiving data from the master)
On the last byte of data communicated, the master
To begin communication, a master device starts out in device may end the transmission by sending a Stop bit.
Master Transmit mode. The master device sends out a If the master device is in Receive mode, it sends the
Start bit followed by the address byte of the slave it Stop bit in place of the last ACK bit. A Stop bit is
intends to communicate with. This is followed by a indicated by a low-to-high transition of the SDA line
single Read/Write bit, which determines whether the while the SCL line is held high.
master intends to transmit to or receive data from the
slave device. In some cases, the master may want to maintain
control of the bus and re-initiate another transmission.
If the requested slave exists on the bus, it will respond If so, the master device may send another Start bit in
with an Acknowledge bit, otherwise known as an ACK. place of the Stop bit or last ACK bit when it is in receive
The master then continues in either Transmit mode or mode.
Receive mode and the slave continues in the
complement, either in Receive mode or Transmit The I2C bus specifies three message protocols;
mode, respectively. • Single message where a master writes data to a
A Start bit is indicated by a high-to-low transition of the slave.
SDA line while the SCL line is held high. Address and • Single message where a master reads data from
data bytes are sent out, Most Significant bit (MSb) first. a slave.
The Read/Write bit is sent out as a logical one when the • Combined message where a master initiates a
master intends to read data from the slave, and is sent minimum of two writes, or two reads, or a
out as a logical zero when it intends to write data to the combination of writes and reads, to one or more
slave. slaves.

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When one device is transmitting a logical one, or letting 28.3.2 ARBITRATION
the line float, and a second device is transmitting a
Each master device must monitor the bus for Start and
logical zero, or holding the line low, the first device can
Stop bits. If the device detects that the bus is busy, it
detect that the line is not a logical one. This detection,
cannot begin a new message until the bus returns to an
when used on the SCL line, is called clock stretching.
Idle state.
Clock stretching gives slave devices a mechanism to
control the flow of data. When this detection is used on However, two master devices may try to initiate a
the SDA line, it is called arbitration. Arbitration ensures transmission on or about the same time. When this
that there is only one master device communicating at occurs, the process of arbitration begins. Each
any single time. transmitter checks the level of the SDA data line and
compares it to the level that it expects to find. The first
28.3.1 CLOCK STRETCHING transmitter to observe that the two levels do not match,
loses arbitration, and must stop transmitting on the
When a slave device has not completed processing
SDA line.
data, it can delay the transfer of more data through the
process of clock stretching. An addressed slave device For example, if one transmitter holds the SDA line to a
may hold the SCL clock line low after receiving or logical one (lets it float) and a second transmitter holds
sending a bit, indicating that it is not yet ready to it to a logical zero (pulls it low), the result is that the
continue. The master that is communicating with the SDA line will be low. The first transmitter then observes
slave will attempt to raise the SCL line in order to that the level of the line is different than expected and
transfer the next bit, but will detect that the clock line concludes that another transmitter is communicating.
has not yet been released. Because the SCL The first transmitter to notice this difference is the one
connection is open-drain, the slave has the ability to that loses arbitration and must stop driving the SDA
hold that line low until it is ready to continue line. If this transmitter is also a master device, it also
communicating. must stop driving the SCL line. It then can monitor the
Clock stretching allows receivers that cannot keep up lines for a Stop condition before trying to reissue its
with a transmitter to control the flow of incoming data. transmission. In the meantime, the other device that
has not noticed any difference between the expected
and actual levels on the SDA line continues with its
original transmission. It can do so without any
complications, because so far, the transmission
appears exactly as expected with no other transmitter
disturbing the message.
Slave Transmit mode can also be arbitrated, when a
master addresses multiple slaves, but this is less
common.
If two master devices are sending a message to two
different slave devices at the address stage, the master
sending the lower slave address always wins
arbitration. When two master devices send messages
to the same slave address, and addresses can
sometimes refer to multiple slaves, the arbitration
process must continue into the data stage.
Arbitration usually occurs very rarely, but it is a
necessary process for proper multi-master support.

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28.4 I2C MODE OPERATION TABLE 28-2: I2C BUS TERMS
TERM Description
All MSSP I2C communication is byte oriented and
shifted out MSb first. Six SFR registers and two Transmitter The device which shifts data out
interrupt flags interface the module with the PIC® onto the bus.
microcontroller and user software. Two pins, SDA and Receiver The device which shifts data in
SCL, are exercised by the module to communicate from the bus.
with other external I2C devices. Master The device that initiates a transfer,
28.4.1 BYTE FORMAT generates clock signals and termi-
nates a transfer.
All communication in I2C is done in 9-bit segments. A Slave The device addressed by the
byte is sent from a master to a slave or vice-versa, master.
followed by an Acknowledge bit sent back. After the Multi-master A bus with more than one device
eighth falling edge of the SCL line, the device that can initiate data transfers.
outputting data on the SDA changes that pin to an
Arbitration Procedure to ensure that only one
input and reads in an acknowledge value on the next
master at a time controls the bus.
clock pulse.
Winning arbitration ensures that
The clock signal, SCL, is provided by the master. Data the message is not corrupted.
is valid to change while the SCL signal is low, and Synchronization Procedure to synchronize the
sampled on the rising edge of the clock. Changes on clocks of two or more devices on
the SDA line while the SCL line is high define special the bus.
conditions on the bus, explained below.
Idle No master is controlling the bus,
28.4.2 DEFINITION OF I2C TERMINOLOGY and both SDA and SCL lines are
high.
There is language and terminology in the description
Active Any time one or more master
of I2C communication that have definitions specific to
devices are controlling the bus.
I2C. That word usage is defined below and may be
used in the rest of this document without explanation. Addressed Slave device that has received a
This table was adapted from the Philips I2C Slave matching address and is actively
specification. being clocked by a master.
Matching Address byte that is clocked into a
28.4.3 SDA AND SCL PINS Address slave that matches the value
stored in SSPADD.
Selection of any I2C mode with the SSPEN bit set,
forces the SCL and SDA pins to be open-drain. These Write Request Slave receives a matching
pins should be set by the user to inputs by setting the address with R/W bit clear, and is
appropriate TRIS bits. ready to clock in data.
Read Request Master sends an address byte with
Note 1: Data is tied to output zero when an I2C the R/W bit set, indicating that it
mode is enabled. wishes to clock data out of the
2: Any device pin can be selected for SDA Slave. This data is the next and all
and SCL functions with the PPS peripheral. following bytes until a Restart or
These functions are bidirectional. The SDA Stop.
input is selected with the SSPDATPPS Clock Stretching When a device on the bus hold
registers. The SCL input is selected with SCL low to stall communication.
the SSPCLKPPS registers. Outputs are Bus Collision Any time the SDA line is sampled
selected with the RxyPPS registers. It is the low by the module while it is out-
user’s responsibility to make the selections putting and expected high state.
so that both the input and the output for
each function is on the same pin.

28.4.4 SDA HOLD TIME

The hold time of the SDA pin is selected by the SDAHT

bit of the SSPCON3 register. Hold time is the time SDA
is held valid after the falling edge of SCL. Setting the
SDAHT bit selects a longer 300 ns minimum hold time
and may help on buses with large capacitance.

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28.4.5 START CONDITION 28.4.7 RESTART CONDITION

The I2C specification defines a Start condition as a A Restart is valid any time that a Stop would be valid.
transition of SDA from a high to a low state while SCL A master can issue a Restart if it wishes to hold the
line is high. A Start condition is always generated by bus after terminating the current transfer. A Restart
the master and signifies the transition of the bus from has the same effect on the slave that a Start would,
an Idle to an Active state. Figure 28-12 shows wave resetting all slave logic and preparing it to clock in an
forms for Start and Stop conditions. address. The master may want to address the same or
A bus collision can occur on a Start condition if the another slave. Figure 28-13 shows the wave form for a
module samples the SDA line low before asserting it Restart condition.
low. This does not conform to the I2C Specification that In 10-bit Addressing Slave mode a Restart is required
states no bus collision can occur on a Start. for the master to clock data out of the addressed
slave. Once a slave has been fully addressed,
28.4.6 STOP CONDITION matching both high and low address bytes, the master
A Stop condition is a transition of the SDA line from can issue a Restart and the high address byte with the
low-to-high state while the SCL line is high. R/W bit set. The slave logic will then hold the clock
and prepare to clock out data.
Note: At least one SCL low time must appear
After a full match with R/W clear in 10-bit mode, a prior
before a Stop is valid, therefore, if the SDA
match flag is set and maintained until a Stop condition, a
line goes low then high again while the SCL
high address with R/W clear, or high address match fails.
line stays high, only the Start condition is
detected. 28.4.8 START/STOP CONDITION INTERRUPT
MASKING

The SCIE and PCIE bits of the SSPCON3 register can

enable the generation of an interrupt in Slave modes
that do not typically support this function. Slave modes
where interrupt on Start and Stop detect are already
enabled, these bits will have no effect.

FIGURE 28-12: I2C START AND STOP CONDITIONS

SDA

SCL
S P
Change of Change of
Data Allowed Data Allowed
Start Stop
Condition Condition

FIGURE 28-13: I2C RESTART CONDITION

Sr

Change of Change of
Data Allowed Data Allowed
Restart
Condition

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28.4.9 ACKNOWLEDGE SEQUENCE 28.5 I2C SLAVE MODE OPERATION
The 9th SCL pulse for any transferred byte in I2C is The MSSP Slave mode operates in one of four modes
dedicated as an Acknowledge. It allows receiving selected by the SSPM bits of SSPCON1 register. The
devices to respond back to the transmitter by pulling modes can be divided into 7-bit and 10-bit Addressing
the SDA line low. The transmitter must release control mode. 10-bit Addressing modes operate the same as
of the line during this time to shift in the response. The 7-bit with some additional overhead for handling the
Acknowledge (ACK) is an active-low signal, pulling the larger addresses.
SDA line low indicates to the transmitter that the
device has received the transmitted data and is ready Modes with Start and Stop bit interrupts operate the
to receive more. same as the other modes with SSPIF additionally
getting set upon detection of a Start, Restart, or Stop
The result of an ACK is placed in the ACKSTAT bit of condition.
the SSPCON2 register.
28.5.1 SLAVE MODE ADDRESSES
Slave software, when the AHEN and DHEN bits are
set, allow the user to set the ACK value sent back to The SSPADD register (Register 28-6) contains the
the transmitter. The ACKDT bit of the SSPCON2 Slave mode address. The first byte received after a
register is set/cleared to determine the response. Start or Restart condition is compared against the
Slave hardware will generate an ACK response if the value stored in this register. If the byte matches, the
AHEN and DHEN bits of the SSPCON3 register are value is loaded into the SSPBUF register and an
clear. interrupt is generated. If the value does not match, the
module goes idle and no indication is given to the
There are certain conditions where an ACK will not be
software that anything happened.
sent by the slave. If the BF bit of the SSPSTAT register
or the SSPOV bit of the SSPCON1 register are set The SSP Mask register (Register 28-5) affects the
when a byte is received. address matching process. See Section 28.5.9 “SSP
Mask Register” for more information.
When the module is addressed, after the eighth falling
edge of SCL on the bus, the ACKTIM bit of the 28.5.1.1 I2C Slave 7-bit Addressing Mode
SSPCON3 register is set. The ACKTIM bit indicates
the acknowledge time of the active bus. The ACKTIM In 7-bit Addressing mode, the LSb of the received data
Status bit is only active when the AHEN bit or DHEN byte is ignored when determining if there is an address
bit is enabled. match.

28.5.1.2 I2C Slave 10-bit Addressing Mode

In 10-bit Addressing mode, the first received byte is
compared to the binary value of ‘1 1 1 1 0 A9 A8 0’. A9
and A8 are the two MSb’s of the 10-bit address and
stored in bits 2 and 1 of the SSPADD register.
After the acknowledge of the high byte the UA bit is set
and SCL is held low until the user updates SSPADD
with the low address. The low address byte is clocked
in and all eight bits are compared to the low address
value in SSPADD. Even if there is not an address
match; SSPIF and UA are set, and SCL is held low
until SSPADD is updated to receive a high byte again.
When SSPADD is updated the UA bit is cleared. This
ensures the module is ready to receive the high
address byte on the next communication.
A high and low address match as a write request is
required at the start of all 10-bit addressing communi-
cation. A transmission can be initiated by issuing a
Restart once the slave is addressed, and clocking in
the high address with the R/W bit set. The slave
hardware will then acknowledge the read request and
prepare to clock out data. This is only valid for a slave
after it has received a complete high and low address
byte match.

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28.5.2 SLAVE RECEPTION 28.5.2.2 7-bit Reception with AHEN and DHEN

When the R/W bit of a matching received address byte Slave device reception with AHEN and DHEN set
is clear, the R/W bit of the SSPSTAT register is cleared. operate the same as without these options with extra
The received address is loaded into the SSPBUF interrupts and clock stretching added after the eighth
register and acknowledged. falling edge of SCL. These additional interrupts allow
When the overflow condition exists for a received the slave software to decide whether it wants to ACK
address, then not Acknowledge is given. An overflow the receive address or data byte, rather than the
condition is defined as either bit BF of the SSPSTAT hardware. This functionality adds support for PMBus™
register is set, or bit SSPOV of the SSPCON1 register that was not present on previous versions of this
is set. The BOEN bit of the SSPCON3 register modifies module.
this operation. For more information see Register 28-4. This list describes the steps that need to be taken by
An MSSP interrupt is generated for each transferred slave software to use these options for I2C
data byte. Flag bit, SSPIF, must be cleared by software. communication. Figure 28-16 displays a module using
both address and data holding. Figure 28-17 includes
When the SEN bit of the SSPCON2 register is set, SCL the operation with the SEN bit of the SSPCON2
will be held low (clock stretch) following each received register set.
byte. The clock must be released by setting the CKP
bit of the SSPCON1 register, except sometimes in 1. S bit of SSPSTAT is set; SSPIF is set if interrupt
10-bit mode. See Section 28.5.6.2 “10-bit on Start detect is enabled.
Addressing Mode” for more detail. 2. Matching address with R/W bit clear is clocked
in. SSPIF is set and CKP cleared after the eighth
28.5.2.1 7-bit Addressing Reception falling edge of SCL.
This section describes a standard sequence of events 3. Slave clears the SSPIF.
for the MSSP module configured as an I2C slave in 4. Slave can look at the ACKTIM bit of the
7-bit Addressing mode. Figure 28-14 and Figure 28-15 SSPCON3 register to determine if the SSPIF
is used as a visual reference for this description. was after or before the ACK.
This is a step by step process of what typically must 5. Slave reads the address value from SSPBUF,
be done to accomplish I2C communication. clearing the BF flag.
6. Slave sets ACK value clocked out to the master
1. Start bit detected.
by setting ACKDT.
2. S bit of SSPSTAT is set; SSPIF is set if interrupt
7. Slave releases the clock by setting CKP.
on Start detect is enabled.
8. SSPIF is set after an ACK, not after a NACK.
3. Matching address with R/W bit clear is received.
9. If SEN = 1 the slave hardware will stretch the
4. The slave pulls SDA low sending an ACK to the
clock after the ACK.
master, and sets SSPIF bit.
10. Slave clears SSPIF.
5. Software clears the SSPIF bit.
6. Software reads received address from SSPBUF Note: SSPIF is still set after the ninth falling edge
clearing the BF flag. of SCL even if there is no clock stretching
and BF has been cleared. Only if NACK is
7. If SEN = 1; Slave software sets CKP bit to
sent to master is SSPIF not set
release the SCL line.
8. The master clocks out a data byte. 11. SSPIF set and CKP cleared after eighth falling
9. Slave drives SDA low sending an ACK to the edge of SCL for a received data byte.
master, and sets SSPIF bit. 12. Slave looks at ACKTIM bit of SSPCON3 to
10. Software clears SSPIF. determine the source of the interrupt.
11. Software reads the received byte from SSPBUF 13. Slave reads the received data from SSPBUF
clearing BF. clearing BF.
12. Steps 8-12 are repeated for all received bytes 14. Steps 7-14 are the same for each received data
from the master. byte.
13. Master sends Stop condition, setting P bit of 15. Communication is ended by either the slave
SSPSTAT, and the bus goes idle. sending an ACK = 1, or the master sending a
Stop condition. If a Stop is sent and Interrupt on
Stop Detect is disabled, the slave will only know
by polling the P bit of the SSTSTAT register.

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 FIGURE 28-14:

Bus Master sends

Stop condition
From Slave to Master

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Receiving Address Receiving Data Receiving Data ACK = 1
SDA
A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0

SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P

SSPIF
SSPIF set on 9th
Cleared by software Cleared by software falling edge of
SCL
BF
First byte
SSPBUF is read of data is
available
in SSPBUF
SSPOV

SSPOV set because

SSPBUF is still full.
ACK is not sent.
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 0, DHEN = 0)

DS40001715D-page 287
PIC16(L)F1704/8
 FIGURE 28-15:

Bus Master sends

Stop condition

DS40001715D-page 288
Receive Address Receive Data Receive Data ACK
SDA A7 A6 A5 A4 A3 A2 A1 R/W=0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0

SCL S 1 2 3 4 5 6 7 8 9 SEN 1 2 3 4 5 6 7 8 9 SEN 1 2 3 4 5 6 7 8 9 P

PIC16(L)F1704/8

Clock is held low until CKP is set to ‘1’

SSPIF

SSPIF set on 9th

Cleared by software Cleared by software falling edge of SCL

BF
First byte
of data is
SSPBUF is read available
in SSPBUF
SSPOV

SSPOV set because

SSPBUF is still full.
ACK is not sent.
CKP

SCL is not held

CKP is written to ‘1’ in software, CKP is written to ‘1’ in software,
low because
releasing SCL releasing SCL
ACK= 1
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0)

 2013-2015 Microchip Technology Inc.

 Master Releases SDA Master sends
to slave for ACK sequence Stop condition
FIGURE 28-16:

SDA Receiving Address Receiving Data ACK Received Data ACK=1

A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

SCL
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P

 2013-2015 Microchip Technology Inc.

SSPIF
If AHEN = 1: SSPIF is set on
SSPIF is set 9th falling edge of Cleared by software No interrupt
SCL, after ACK after not ACK
BF from Slave
Address is
read from Data is read from SSPBUF
ACKDT SSBUF

Slave software
clears ACKDT to Slave software
ACK the received sets ACKDT to
CKP byte not ACK

When AHEN=1:
When DHEN=1: CKP set by software,
CKP is cleared by hardware
CKP is cleared by SCL is released
and SCL is stretched hardware on 8th falling
edge of SCL
ACKTIM

ACKTIM set by hardware ACKTIM cleared by ACKTIM set by hardware

on 8th falling edge of SCL hardware in 9th on 8th falling edge of SCL
rising edge of SCL

P
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 1)

DS40001715D-page 289
PIC16(L)F1704/8
 Master sends
FIGURE 28-17:

Stop condition
Master releases
R/W = 0 SDA to slave for ACK sequence

DS40001715D-page 290
Receiving Address Receive Data Receive Data ACK
SDA ACK
A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0

SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
S
PIC16(L)F1704/8

SSPIF
Cleared by software No interrupt after
if not ACK
from Slave
BF
Received
address is loaded into Received data is SSPBUF can be
SSPBUF available on SSPBUF read any time before
next byte is loaded
ACKDT

Slave software clears

Slave sends
ACKDT to ACK not ACK
the received byte
CKP
When AHEN = 1; When DHEN = 1; CKP is not cleared
on the 8th falling edge on the 8th falling edge Set by software, if not ACK
of SCL of an address of SCL of a received release SCL
byte, CKP is cleared data byte, CKP is cleared

ACKTIM

ACKTIM is set by hardware ACKTIM is cleared by hardware

on 8th falling edge of SCL on 9th rising edge of SCL

P
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 1, DHEN = 1)

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 PIC16(L)F1704/8
28.5.3 SLAVE TRANSMISSION 28.5.3.2 7-bit Transmission
When the R/W bit of the incoming address byte is set A master device can transmit a read request to a
and an address match occurs, the R/W bit of the slave, and then clock data out of the slave. The list
SSPSTAT register is set. The received address is below outlines what software for a slave will need to
loaded into the SSPBUF register, and an ACK pulse is do to accomplish a standard transmission.
sent by the slave on the ninth bit. Figure 28-18 can be used as a reference to this list.
Following the ACK, slave hardware clears the CKP bit 1. Master sends a Start condition on SDA and
and the SCL pin is held low (see Section 28.5.6 SCL.
“Clock Stretching” for more detail). By stretching the 2. S bit of SSPSTAT is set; SSPIF is set if interrupt
clock, the master will be unable to assert another clock on Start detect is enabled.
pulse until the slave is done preparing the transmit 3. Matching address with R/W bit set is received by
data. the Slave setting SSPIF bit.
The transmit data must be loaded into the SSPBUF 4. Slave hardware generates an ACK and sets
register which also loads the SSPSR register. Then the SSPIF.
SCL pin should be released by setting the CKP bit of 5. SSPIF bit is cleared by user.
the SSPCON1 register. The eight data bits are shifted
6. Software reads the received address from
out on the falling edge of the SCL input. This ensures
SSPBUF, clearing BF.
that the SDA signal is valid during the SCL high time.
7. R/W is set so CKP was automatically cleared
The ACK pulse from the master-receiver is latched on after the ACK.
the rising edge of the ninth SCL input pulse. This ACK
8. The slave software loads the transmit data into
value is copied to the ACKSTAT bit of the SSPCON2
SSPBUF.
register. If ACKSTAT is set (not ACK), then the data
transfer is complete. In this case, when the not ACK is 9. CKP bit is set releasing SCL, allowing the
latched by the slave, the slave goes idle and waits for master to clock the data out of the slave.
another occurrence of the Start bit. If the SDA line was 10. SSPIF is set after the ACK response from the
low (ACK), the next transmit data must be loaded into master is loaded into the ACKSTAT register.
the SSPBUF register. Again, the SCL pin must be 11. SSPIF bit is cleared.
released by setting bit CKP. 12. The slave software checks the ACKSTAT bit to
An MSSP interrupt is generated for each data transfer see if the master wants to clock out more data.
byte. The SSPIF bit must be cleared by software and Note 1: If the master ACKs the clock will be
the SSPSTAT register is used to determine the status stretched.
of the byte. The SSPIF bit is set on the falling edge of
the ninth clock pulse. 2: ACKSTAT is the only bit updated on the
rising edge of SCL (9th) rather than the
28.5.3.1 Slave Mode Bus Collision falling.
A slave receives a Read request and begins shifting 13. Steps 9-13 are repeated for each transmitted
data out on the SDA line. If a bus collision is detected byte.
and the SBCDE bit of the SSPCON3 register is set, the 14. If the master sends a not ACK; the clock is not
BCLIF bit of the PIR register is set. Once a bus collision held, but SSPIF is still set.
is detected, the slave goes idle and waits to be 15. The master sends a Restart condition or a Stop.
addressed again. User software can use the BCLIF bit
16. The slave is no longer addressed.
to handle a slave bus collision.

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 Master sends
Stop condition
FIGURE 28-18:

Receiving Address Transmitting Data Automatic Transmitting Data ACK

R/W = 1 Automatic
SDA A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0

DS40001715D-page 292
SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P

SSPIF

Cleared by software
PIC16(L)F1704/8

BF
BF is automatically
Received address Data to transmit is cleared after 8th falling
is read from SSPBUF loaded into SSPBUF edge of SCL

CKP
When R/W is set CKP is not
SCL is always held for not
held low after 9th SCL Set by software ACK
falling edge
ACKSTAT

Masters not ACK

is copied to
ACKSTAT
R/W
R/W is copied from the
matching address byte
D/A
I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 0)

Indicates an address
has been received

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 PIC16(L)F1704/8
28.5.3.3 7-bit Transmission with Address
Hold Enabled
Setting the AHEN bit of the SSPCON3 register
enables additional clock stretching and interrupt
generation after the eighth falling edge of a received
matching address. Once a matching address has
been clocked in, CKP is cleared and the SSPIF
interrupt is set.
Figure 28-19 displays a standard waveform of a 7-bit
address slave transmission with AHEN enabled.
1. Bus starts Idle.
2. Master sends Start condition; the S bit of
SSPSTAT is set; SSPIF is set if interrupt on Start
detect is enabled.
3. Master sends matching address with R/W bit
set. After the eighth falling edge of the SCL line
the CKP bit is cleared and SSPIF interrupt is
generated.
4. Slave software clears SSPIF.
5. Slave software reads ACKTIM bit of SSPCON3
register, and R/W and D/A of the SSPSTAT
register to determine the source of the interrupt.
6. Slave reads the address value from the
SSPBUF register clearing the BF bit.
7. Slave software decides from this information if it
wishes to ACK or not ACK and sets the ACKDT
bit of the SSPCON2 register accordingly.
8. Slave sets the CKP bit releasing SCL.
9. Master clocks in the ACK value from the slave.
10. Slave hardware automatically clears the CKP bit
and sets SSPIF after the ACK if the R/W bit is
set.
11. Slave software clears SSPIF.
12. Slave loads value to transmit to the master into
SSPBUF setting the BF bit.
Note: SSPBUF cannot be loaded until after the
ACK.
13. Slave sets the CKP bit releasing the clock.
14. Master clocks out the data from the slave and
sends an ACK value on the ninth SCL pulse.
15. Slave hardware copies the ACK value into the
ACKSTAT bit of the SSPCON2 register.
16. Steps 10-15 are repeated for each byte
transmitted to the master from the slave.
17. If the master sends a not ACK the slave
releases the bus allowing the master to send a
Stop and end the communication.
Note: Master must send a not ACK on the last
byte to ensure that the slave releases the
SCL line to receive a Stop.

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 Master sends
Master releases SDA Stop condition
FIGURE 28-19:

to slave for ACK sequence

Receiving Address R/W = 1 Automatic Transmitting Data Automatic Transmitting Data ACK

DS40001715D-page 294
SDA ACK
A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0

SCL
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
P

SSPIF
Cleared by software
PIC16(L)F1704/8

BF BF is automatically
Received address Data to transmit is cleared after 8th falling
is read from SSPBUF loaded into SSPBUF edge of SCL

ACKDT

Slave clears
ACKDT to ACK
address

ACKSTAT
Master’s ACK
response is copied
to SSPSTAT
CKP
When AHEN = 1; CKP not cleared
CKP is cleared by hardware When R/W = 1; Set by software, after not ACK
after receiving matching CKP is always releases SCL
address. cleared after ACK

ACKTIM
I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 1)

ACKTIM is set on 8th falling ACKTIM is cleared

edge of SCL on 9th rising edge of SCL

R/W

D/A

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 PIC16(L)F1704/8
28.5.4 SLAVE MODE 10-BIT ADDRESS 28.5.5 10-BIT ADDRESSING WITH ADDRESS OR
RECEPTION DATA HOLD

This section describes a standard sequence of events Reception using 10-bit addressing with AHEN or
for the MSSP module configured as an I2C slave in DHEN set is the same as with 7-bit modes. The only
10-bit Addressing mode. difference is the need to update the SSPADD register
Figure 28-20 is used as a visual reference for this using the UA bit. All functionality, specifically when the
description. CKP bit is cleared and SCL line is held low are the
same. Figure 28-21 can be used as a reference of a
This is a step by step process of what must be done by slave in 10-bit addressing with AHEN set.
slave software to accomplish I2C communication.
Figure 28-22 shows a standard waveform for a slave
1. Bus starts Idle. transmitter in 10-bit Addressing mode.
2. Master sends Start condition; S bit of SSPSTAT
is set; SSPIF is set if interrupt on Start detect is
enabled.
3. Master sends matching high address with R/W
bit clear; UA bit of the SSPSTAT register is set.
4. Slave sends ACK and SSPIF is set.
5. Software clears the SSPIF bit.
6. Software reads received address from SSPBUF
clearing the BF flag.
7. Slave loads low address into SSPADD,
releasing SCL.
8. Master sends matching low address byte to the
slave; UA bit is set.
Note: Updates to the SSPADD register are not
allowed until after the ACK sequence.

9. Slave sends ACK and SSPIF is set.

Note: If the low address does not match, SSPIF
and UA are still set so that the slave
software can set SSPADD back to the high
address. BF is not set because there is no
match. CKP is unaffected.
10. Slave clears SSPIF.
11. Slave reads the received matching address
from SSPBUF clearing BF.
12. Slave loads high address into SSPADD.
13. Master clocks a data byte to the slave and
clocks out the slaves ACK on the 9th SCL pulse;
SSPIF is set.
14. If SEN bit of SSPCON2 is set, CKP is cleared by
hardware and the clock is stretched.
15. Slave clears SSPIF.
16. Slave reads the received byte from SSPBUF
clearing BF.
17. If SEN is set the slave sets CKP to release the
SCL.
18. Steps 13-17 repeat for each received byte.
19. Master sends Stop to end the transmission.

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 FIGURE 28-20:

Master sends
Stop condition

DS40001715D-page 296
Receive First Address Byte Receive Second Address Byte Receive Data Receive Data
SDA
1 1 1 1
0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK

SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
S
PIC16(L)F1704/8

SCL is held low

while CKP = 0

SSPIF
Set by hardware Cleared by software
on 9th falling edge

BF
If address matches Receive address is Data is read
SSPADD it is loaded into read from SSPBUF from SSPBUF
SSPBUF

UA
When UA = 1; Software updates SSPADD
SCL is held low and releases SCL

CKP

When SEN = 1; Set by software,

CKP is cleared after releasing SCL
9th falling edge of received byte
I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0)

 2013-2015 Microchip Technology Inc.

 Receive First Address Byte R/W = 0 Receive Second Address Byte Receive Data Receive Data
FIGURE 28-21:

SDA 1 1 1 1 0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5

SCL S 1 2 3 4 5 6 7 8 9 UA 1 2 3 4 5 6 7 8 9 UA 1 2 3 4 5 6 7 8 9 1 2

 2013-2015 Microchip Technology Inc.

SSPIF
Set by hardware Cleared by software Cleared by software
on 9th falling edge

BF

SSPBUF can be Received data

read anytime before is read from
the next received byte SSPBUF
ACKDT
Slave software clears
ACKDT to ACK
the received byte

UA

Update to SSPADD is Update of SSPADD,

not allowed until 9th
falling edge of SCL clears UA and releases
SCL

CKP If when AHEN = 1;

on the 8th falling edge Set CKP with software
of SCL of an address releases SCL
byte, CKP is cleared
ACKTIM
ACKTIM is set by hardware
on 8th falling edge of SCL
I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 0)

DS40001715D-page 297
PIC16(L)F1704/8
 FIGURE 28-22:

Master sends

DS40001715D-page 298
Master sends Stop condition
Restart event Master sends
not ACK

Receiving Address R/W = 0 Receiving Second Address Byte Receive First Address Byte Transmitting Data Byte ACK = 1
SDA 1 1 1 1 0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK 1 1 1 1 0 A9 A8 ACK D7 D6 D5 D4 D3 D2 D1 D0

SCL 1 2 3 4 5 6 7 8 9 1 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
PIC16(L)F1704/8

S 2 3 4 5 P
Sr

SSPIF

Set by hardware Cleared by software Set by hardware

BF

SSPBUF loaded Received address is Data to transmit is

with received address read from SSPBUF loaded into SSPBUF
UA
High address is loaded
UA indicates SSPADD After SSPADD is back into SSPADD
must be updated updated, UA is cleared
CKP and SCL is released

When R/W = 1; Set by software

ACKSTAT CKP is cleared on releases SCL
9th falling edge of SCL

Masters not ACK

is copied
R/W
R/W is copied from the
matching address byte
D/A

Indicates an address
has been received
I2C SLAVE, 10-BIT ADDRESS, TRANSMISSION (SEN = 0, AHEN = 0, DHEN = 0)

 2013-2015 Microchip Technology Inc.

 PIC16(L)F1704/8
28.5.6 CLOCK STRETCHING 28.5.7 CLOCK SYNCHRONIZATION AND
THE CKP BIT
Clock stretching occurs when a device on the bus
holds the SCL line low, effectively pausing Any time the CKP bit is cleared, the module will wait
communication. The slave may stretch the clock to for the SCL line to go low and then hold it. However,
allow more time to handle data or prepare a response clearing the CKP bit will not assert the SCL output low
for the master device. A master device is not until the SCL output is already sampled low.
concerned with stretching as anytime it is active on the Therefore, the CKP bit will not assert the SCL line until
bus and not transferring data it is stretching. Any an external I2C master device has already asserted
stretching done by a slave is invisible to the master the SCL line. The SCL output will remain low until the
software and handled by the hardware that generates CKP bit is set and all other devices on the I2C bus
SCL. have released SCL. This ensures that a write to the
The CKP bit of the SSPCON1 register is used to CKP bit will not violate the minimum high time
control stretching in software. Any time the CKP bit is requirement for SCL (see Figure 28-23).
cleared, the module will wait for the SCL line to go low
and then hold it. Setting CKP will release SCL and
allow more communication.

28.5.6.1 Normal Clock Stretching

Following an ACK if the R/W bit of SSPSTAT is set, a

read request, the slave hardware will clear CKP. This
allows the slave time to update SSPBUF with data to
transfer to the master. If the SEN bit of SSPCON2 is
set, the slave hardware will always stretch the clock
after the ACK sequence. Once the slave is ready; CKP
is set by software and communication resumes.
Note 1: The BF bit has no effect on if the clock will
be stretched or not. This is different than
previous versions of the module that
would not stretch the clock, clear CKP, if
SSPBUF was read before the ninth falling
edge of SCL.
2: Previous versions of the module did not
stretch the clock for a transmission if
SSPBUF was loaded before the 9th
falling edge of SCL. It is now always
cleared for read requests.

28.5.6.2 10-bit Addressing Mode

In 10-bit Addressing mode, when the UA bit is set the

clock is always stretched. This is the only time the SCL
is stretched without CKP being cleared. SCL is
released immediately after a write to SSPADD.
Note: Previous versions of the module did not
stretch the clock if the second address byte
did not match.

28.5.6.3 Byte NACKing

When AHEN bit of SSPCON3 is set; CKP is cleared by

hardware after the eighth falling edge of SCL for a
received matching address byte. When DHEN bit of
SSPCON3 is set; CKP is cleared after the eighth
falling edge of SCL for received data.
Stretching after the eighth falling edge of SCL allows
the slave to look at the received address or data and
decide if it wants to ACK the received data.

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PIC16(L)F1704/8
FIGURE 28-23: CLOCK SYNCHRONIZATION TIMING

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

SDA DX DX ‚ – 1

SCL

Master device
CKP asserts clock

Master device
releases clock
WR
SSPCON1

28.5.8 GENERAL CALL ADDRESS SUPPORT In 10-bit Address mode, the UA bit will not be set on
the reception of the general call address. The slave
The addressing procedure for the I2C bus is such that will prepare to receive the second byte as data, just as
the first byte after the Start condition usually it would in 7-bit mode.
determines which device will be the slave addressed
by the master device. The exception is the general call If the AHEN bit of the SSPCON3 register is set, just as
address which can address all devices. When this with any other address reception, the slave hardware
address is used, all devices should, in theory, respond will stretch the clock after the eighth falling edge of
with an acknowledge. SCL. The slave must then set its ACKDT value and
release the clock with communication progressing as it
The general call address is a reserved address in the would normally.
I2C protocol, defined as address 0x00. When the
GCEN bit of the SSPCON2 register is set, the slave
module will automatically ACK the reception of this
address regardless of the value stored in SSPADD.
After the slave clocks in an address of all zeros with
the R/W bit clear, an interrupt is generated and slave
software can read SSPBUF and respond.
Figure 28-24 shows a general call reception
sequence.

FIGURE 28-24: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE

Address is compared to General Call Address
after ACK, set interrupt

R/W = 0 Receiving Data ACK

SDA General Call Address ACK D7 D6 D5 D4 D3 D2 D1 D0

SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S

SSPIF

BF (SSPSTAT<0>)

Cleared by software
SSPBUF is read
GCEN (SSPCON2<7>)
’1’

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 PIC16(L)F1704/8
28.5.9 SSP MASK REGISTER

An SSP Mask (SSPMSK) register (Register 28-5) is Note 1: The MSSP module, when configured in
available in I2C Slave mode as a mask for the value I2C Master mode, does not allow queuing
held in the SSPSR register during an address of events. For instance, the user is not
comparison operation. A zero (‘0’) bit in the SSPMSK allowed to initiate a Start condition and
register has the effect of making the corresponding bit immediately write the SSPBUF register to
of the received address a “don’t care”. initiate transmission before the Start
condition is complete. In this case, the
This register is reset to all ‘1’s upon any Reset
SSPBUF will not be written to and the
condition and, therefore, has no effect on standard
WCOL bit will be set, indicating that a
SSP operation until written with a mask value.
write to the SSPBUF did not occur
The SSP Mask register is active during:
2: When in Master mode, Start/Stop
• 7-bit Address mode: address compare of A<7:1>. detection is masked and an interrupt is
• 10-bit Address mode: address compare of A<7:0> generated when the SEN/PEN bit is
only. The SSP mask has no effect during the cleared and the generation is complete.
reception of the first (high) byte of the address.

28.6 I2C Master Mode

Master mode is enabled by setting and clearing the
appropriate SSPM bits in the SSPCON1 register and
by setting the SSPEN bit. In Master mode, the SDA and
SCK pins must be configured as inputs. The MSSP
peripheral hardware will override the output driver TRIS
controls when necessary to drive the pins low.
Master mode of operation is supported by interrupt
generation on the detection of the Start and Stop
conditions. The Stop (P) and Start (S) bits are cleared
from a Reset or when the MSSP module is disabled.
Control of the I 2C bus may be taken when the P bit is
set, or the bus is Idle.
In Firmware Controlled Master mode, user code
conducts all I 2C bus operations based on Start and
Stop bit condition detection. Start and Stop condition
detection is the only active circuitry in this mode. All
other communication is done by the user software
directly manipulating the SDA and SCL lines.

The following events will cause the SSP Interrupt Flag

bit, SSPIF, to be set (SSP interrupt, if enabled):
• Start condition detected
• Stop condition detected
• Data transfer byte transmitted/received
• Acknowledge transmitted/received
• Repeated Start generated

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PIC16(L)F1704/8
28.6.1 I2C MASTER MODE OPERATION 28.6.2 CLOCK ARBITRATION
The master device generates all of the serial clock Clock arbitration occurs when the master, during any
pulses and the Start and Stop conditions. A transfer is receive, transmit or Repeated Start/Stop condition,
ended with a Stop condition or with a Repeated Start releases the SCL pin (SCL allowed to float high). When
condition. Since the Repeated Start condition is also the SCL pin is allowed to float high, the Baud Rate
the beginning of the next serial transfer, the I2C bus will Generator (BRG) is suspended from counting until the
not be released. SCL pin is actually sampled high. When the SCL pin is
In Master Transmitter mode, serial data is output sampled high, the Baud Rate Generator is reloaded
through SDA, while SCL outputs the serial clock. The with the contents of SSPADD<7:0> and begins
first byte transmitted contains the slave address of the counting. This ensures that the SCL high time will
receiving device (7 bits) and the Read/Write (R/W) bit. always be at least one BRG rollover count in the event
In this case, the R/W bit will be logic ‘0’. Serial data is that the clock is held low by an external device
transmitted eight bits at a time. After each byte is (Figure 28-25).
transmitted, an Acknowledge bit is received. Start and
Stop conditions are output to indicate the beginning
and the end of a serial transfer.
In Master Receive mode, the first byte transmitted
contains the slave address of the transmitting device
(7 bits) and the R/W bit. In this case, the R/W bit will be
logic ‘1’. Thus, the first byte transmitted is a 7-bit slave
address followed by a ‘1’ to indicate the receive bit.
Serial data is received via SDA, while SCL outputs the
serial clock. Serial data is received eight bits at a time.
After each byte is received, an Acknowledge bit is
transmitted. Start and Stop conditions indicate the
beginning and end of transmission.
A Baud Rate Generator is used to set the clock
frequency output on SCL. See Section 28.7 “Baud
Rate Generator” for more detail.

FIGURE 28-25: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION

SDA DX DX ‚ – 1

SCL deasserted but slave holds SCL allowed to transition high

SCL low (clock arbitration)
SCL

BRG decrements on
Q2 and Q4 cycles

BRG
03h 02h 01h 00h (hold off) 03h 02h
Value

SCL is sampled high, reload takes

place and BRG starts its count
BRG
Reload

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 PIC16(L)F1704/8
28.6.3 WCOL STATUS FLAG Start condition and causes the S bit of the SSPSTAT1
register to be set. Following this, the Baud Rate
If the user writes the SSPBUF when a Start, Restart, Generator is reloaded with the contents of
Stop, Receive or Transmit sequence is in progress, the SSPADD<7:0> and resumes its count. When the Baud
WCOL is set and the contents of the buffer are Rate Generator times out (TBRG), the SEN bit of the
unchanged (the write does not occur). Any time the SSPCON2 register will be automatically cleared by
WCOL bit is set it indicates that an action on SSPBUF hardware; the Baud Rate Generator is suspended,
was attempted while the module was not idle. leaving the SDA line held low and the Start condition is
Note: Because queuing of events is not allowed, complete.
writing to the lower five bits of SSPCON2 Note 1: If at the beginning of the Start condition,
is disabled until the Start condition is the SDA and SCL pins are already
complete. sampled low, or if during the Start
condition, the SCL line is sampled low
28.6.4 I2C MASTER MODE START
before the SDA line is driven low, a bus
CONDITION TIMING
collision occurs, the Bus Collision
To initiate a Start condition (Figure 28-26), the user Interrupt Flag, BCLIF, is set, the Start
sets the Start Enable bit, SEN bit of the SSPCON2 condition is aborted and the I2C module is
register. If the SDA and SCL pins are sampled high, reset into its Idle state.
the Baud Rate Generator is reloaded with the contents 2: The Philips I2C specification states that a
of SSPADD<7:0> and starts its count. If SCL and SDA bus collision cannot occur on a Start.
are both sampled high when the Baud Rate Generator
times out (TBRG), the SDA pin is driven low. The action
of the SDA being driven low while SCL is high is the

FIGURE 28-26: FIRST START BIT TIMING

Write to SEN bit occurs here Set S bit (SSPSTAT<3>)

At completion of Start bit,

SDA = 1,
SCL = 1 hardware clears SEN bit
and sets SSPIF bit
TBRG TBRG Write to SSPBUF occurs here
SDA 1st bit 2nd bit

TBRG
SCL
S
TBRG

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PIC16(L)F1704/8
28.6.5 I2C MASTER MODE REPEATED
START CONDITION TIMING
Note 1: If RSEN is programmed while any other
A Repeated Start condition (Figure 28-27) occurs when event is in progress, it will not take effect.
the RSEN bit of the SSPCON2 register is programmed
high and the master state machine is no longer active. 2: A bus collision during the Repeated Start
When the RSEN bit is set, the SCL pin is asserted low. condition occurs if:
When the SCL pin is sampled low, the Baud Rate • SDA is sampled low when SCL
Generator is loaded and begins counting. The SDA pin goes from low-to-high.
is released (brought high) for one Baud Rate Generator • SCL goes low before SDA is
count (TBRG). When the Baud Rate Generator times asserted low. This may indicate
out, if SDA is sampled high, the SCL pin will be that another master is attempting
deasserted (brought high). When SCL is sampled high, to transmit a data ‘1’.
the Baud Rate Generator is reloaded and begins
counting. SDA and SCL must be sampled high for one
TBRG. This action is then followed by assertion of the
SDA pin (SDA = 0) for one TBRG while SCL is high.
SCL is asserted low. Following this, the RSEN bit of the
SSPCON2 register will be automatically cleared and
the Baud Rate Generator will not be reloaded, leaving
the SDA pin held low. As soon as a Start condition is
detected on the SDA and SCL pins, the S bit of the
SSPSTAT register will be set. The SSPIF bit will not be
set until the Baud Rate Generator has timed out.

FIGURE 28-27: REPEATED START CONDITION WAVEFORM

S bit set by hardware

Write to SSPCON2
occurs here At completion of Start bit,
SDA = 1, SDA = 1,
hardware clears RSEN bit
SCL (no change) SCL = 1 and sets SSPIF

TBRG TBRG TBRG

SDA 1st bit

Write to SSPBUF occurs here

TBRG
SCL
Sr TBRG
Repeated Start

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 PIC16(L)F1704/8
28.6.6 I2C MASTER MODE TRANSMISSION 28.6.6.3 ACKSTAT Status Flag
Transmission of a data byte, a 7-bit address or the In Transmit mode, the ACKSTAT bit of the SSPCON2
other half of a 10-bit address is accomplished by simply register is cleared when the slave has sent an
writing a value to the SSPBUF register. This action will Acknowledge (ACK = 0) and is set when the slave
set the Buffer Full flag bit, BF, and allow the Baud Rate does not Acknowledge (ACK = 1). A slave sends an
Generator to begin counting and start the next Acknowledge when it has recognized its address
transmission. Each bit of address/data will be shifted (including a general call), or when the slave has
out onto the SDA pin after the falling edge of SCL is properly received its data.
asserted. SCL is held low for one Baud Rate Generator
28.6.6.4 Typical transmit sequence:
rollover count (TBRG). Data should be valid before SCL
is released high. When the SCL pin is released high, it 1. The user generates a Start condition by setting
is held that way for TBRG. The data on the SDA pin the SEN bit of the SSPCON2 register.
must remain stable for that duration and some hold 2. SSPIF is set by hardware on completion of the
time after the next falling edge of SCL. After the eighth Start.
bit is shifted out (the falling edge of the eighth clock),
3. SSPIF is cleared by software.
the BF flag is cleared and the master releases SDA.
This allows the slave device being addressed to 4. The MSSP module will wait the required start
respond with an ACK bit during the ninth bit time if an time before any other operation takes place.
address match occurred, or if data was received 5. The user loads the SSPBUF with the slave
properly. The status of ACK is written into the address to transmit.
ACKSTAT bit on the rising edge of the ninth clock. If the 6. Address is shifted out the SDA pin until all eight
master receives an Acknowledge, the Acknowledge bits are transmitted. Transmission begins as
Status bit, ACKSTAT, is cleared. If not, the bit is set. soon as SSPBUF is written to.
After the ninth clock, the SSPIF bit is set and the master 7. The MSSP module shifts in the ACK bit from the
clock (Baud Rate Generator) is suspended until the slave device and writes its value into the
next data byte is loaded into the SSPBUF, leaving SCL ACKSTAT bit of the SSPCON2 register.
low and SDA unchanged (Figure 28-28). 8. The MSSP module generates an interrupt at the
After the write to the SSPBUF, each bit of the address end of the ninth clock cycle by setting the SSPIF
will be shifted out on the falling edge of SCL until all bit.
seven address bits and the R/W bit are completed. On 9. The user loads the SSPBUF with eight bits of
the falling edge of the eighth clock, the master will data.
release the SDA pin, allowing the slave to respond with 10. Data is shifted out the SDA pin until all eight bits
an Acknowledge. On the falling edge of the ninth clock, are transmitted.
the master will sample the SDA pin to see if the address
11. The MSSP module shifts in the ACK bit from the
was recognized by a slave. The status of the ACK bit is
slave device and writes its value into the
loaded into the ACKSTAT Status bit of the SSPCON2
ACKSTAT bit of the SSPCON2 register.
register. Following the falling edge of the ninth clock
transmission of the address, the SSPIF is set, the BF 12. Steps 8-11 are repeated for all transmitted data
flag is cleared and the Baud Rate Generator is turned bytes.
off until another write to the SSPBUF takes place, 13. The user generates a Stop or Restart condition
holding SCL low and allowing SDA to float. by setting the PEN or RSEN bits of the
SSPCON2 register. Interrupt is generated once
28.6.6.1 BF Status Flag the Stop/Restart condition is complete.
In Transmit mode, the BF bit of the SSPSTAT register
is set when the CPU writes to SSPBUF and is cleared
when all eight bits are shifted out.

28.6.6.2 WCOL Status Flag

If the user writes the SSPBUF when a transmit is
already in progress (i.e., SSPSR is still shifting out a
data byte), the WCOL bit is set and the contents of the
buffer are unchanged (the write does not occur).
WCOL must be cleared by software before the next
transmission.

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 FIGURE 28-28:

DS40001715D-page 306
Write SSPCON2<0> SEN = 1 ACKSTAT in
Start condition begins SSPCON2 = 1
From slave, clear ACKSTAT bit SSPCON2<6>
SEN = 0
Transmitting Data or Second Half
Transmit Address to Slave R/W = 0 ACK
of 10-bit Address
SDA A7 A6 A5 A4 A3 A2 A1 ACK = 0 D7 D6 D5 D4 D3 D2 D1 D0

SSPBUF written with 7-bit address and R/W

start transmit
PIC16(L)F1704/8

SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
SCL held low
while CPU
responds to SSPIF
SSPIF
Cleared by software service routine
Cleared by software from SSP interrupt
Cleared by software

BF (SSPSTAT<0>)

SSPBUF written SSPBUF is written by software

SEN

After Start condition, SEN cleared by hardware

PEN

R/W
I2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)

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 PIC16(L)F1704/8
28.6.7 I2C MASTER MODE RECEPTION 28.6.7.4 Typical Receive Sequence:
Master mode reception (Figure 28-29) is enabled by 1. The user generates a Start condition by setting
programming the Receive Enable bit, RCEN bit of the the SEN bit of the SSPCON2 register.
SSP1CON2 register. 2. SSPIF is set by hardware on completion of the
Note: The MSSP module must be in an Idle Start.
state before the RCEN bit is set or the 3. SSPIF is cleared by software.
RCEN bit will be disregarded. 4. User writes SSPBUF with the slave address to
The Baud Rate Generator begins counting and on each transmit and the R/W bit set.
rollover, the state of the SCL pin changes 5. Address is shifted out the SDA pin until all eight
(high-to-low/low-to-high) and data is shifted into the bits are transmitted. Transmission begins as
SSPSR. After the falling edge of the eighth clock, the soon as SSPBUF is written to.
receive enable flag is automatically cleared, the 6. The MSSP module shifts in the ACK bit from the
contents of the SSPSR are loaded into the SSPBUF, slave device and writes its value into the
the BF flag bit is set, the SSPIF flag bit is set and the ACKSTAT bit of the SSPCON2 register.
Baud Rate Generator is suspended from counting, 7. The MSSP module generates an interrupt at the
holding SCL low. The MSSP is now in Idle state end of the ninth clock cycle by setting the SSPIF
awaiting the next command. When the buffer is read by bit.
the CPU, the BF flag bit is automatically cleared. The 8. User sets the RCEN bit of the SSPCON2 register
user can then send an Acknowledge bit at the end of and the master clocks in a byte from the slave.
reception by setting the Acknowledge Sequence
9. After the eighth falling edge of SCL, SSPIF and
Enable, ACKEN bit of the SSPCON2 register.
BF are set.
28.6.7.1 BF Status Flag 10. Master clears SSPIF and reads the received
byte from SSPUF, clears BF.
In receive operation, the BF bit is set when an address
or data byte is loaded into SSPBUF from SSPSR. It is 11. Master sets ACK value sent to slave in ACKDT
cleared when the SSPBUF register is read. bit of the SSPCON2 register and initiates the
ACK by setting the ACKEN bit.
28.6.7.2 SSPOV Status Flag 12. Master’s ACK is clocked out to the slave and
In receive operation, the SSPOV bit is set when eight SSPIF is set.
bits are received into the SSPSR and the BF flag bit is 13. User clears SSPIF.
already set from a previous reception. 14. Steps 8-13 are repeated for each received byte
from the slave.
28.6.7.3 WCOL Status Flag 15. Master sends a not ACK or Stop to end
If the user writes the SSPBUF when a receive is communication.
already in progress (i.e., SSPSR is still shifting in a data
byte), the WCOL bit is set and the contents of the buffer
are unchanged (the write does not occur).

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 Write to SSPCON2<4>
to start Acknowledge sequence
SDA = ACKDT (SSPCON2<5>) = 0
Write to SSPCON2<0> (SEN = 1),
FIGURE 28-29:

begin Start condition ACK from Master Set ACKEN, start Acknowledge sequence
Master configured as a receiver SDA = ACKDT = 0 SDA = ACKDT = 1
by programming SSPCON2<3> (RCEN = 1)

DS40001715D-page 308
SEN = 0
PEN bit = 1
Write to SSPBUF occurs here, RCEN cleared RCEN = 1, start RCEN cleared
ACK from Slave next receive automatically written here
start XMIT automatically
Transmit Address to Slave Receiving Data from Slave Receiving Data from Slave
SDA A7 A6 A5 A4 A3 A2 A1 R/W ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK

Bus master
ACK is not sent terminates
transfer
3 6 7 9
PIC16(L)F1704/8

1 2 4 5 8 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
SCL S P
Data shifted in on falling edge of CLK Set SSPIF at end
of receive Set SSPIF interrupt
Set SSPIF interrupt at end of Acknow-
Set SSPIF interrupt ledge sequence
at end of receive at end of Acknowledge
SSPIF sequence

Set P bit
Cleared by software Cleared by software Cleared by software Cleared by software (SSPSTAT<4>)
SDA = 0, SCL = 1 Cleared in
while CPU software and SSPIF
responds to SSPIF

BF
(SSPSTAT<0>) Last bit is shifted into SSPSR and
contents are unloaded into SSPBUF

SSPOV

SSPOV is set because

SSPBUF is still full

ACKEN
I2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)

RCEN

Master configured as a receiver RCEN cleared ACK from Master RCEN cleared
by programming SSPCON2<3> (RCEN = 1) automatically SDA = ACKDT = 0 automatically

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 PIC16(L)F1704/8
28.6.8 ACKNOWLEDGE SEQUENCE 28.6.9 STOP CONDITION TIMING
TIMING A Stop bit is asserted on the SDA pin at the end of a
An Acknowledge sequence is enabled by setting the receive/transmit by setting the Stop Sequence Enable
Acknowledge Sequence Enable bit, ACKEN bit of the bit, PEN bit of the SSPCON2 register. At the end of a
SSPCON2 register. When this bit is set, the SCL pin is receive/transmit, the SCL line is held low after the
pulled low and the contents of the Acknowledge data bit falling edge of the ninth clock. When the PEN bit is set,
are presented on the SDA pin. If the user wishes to the master will assert the SDA line low. When the SDA
generate an Acknowledge, then the ACKDT bit should line is sampled low, the Baud Rate Generator is
be cleared. If not, the user should set the ACKDT bit reloaded and counts down to ‘0’. When the Baud Rate
before starting an Acknowledge sequence. The Baud Generator times out, the SCL pin will be brought high
Rate Generator then counts for one rollover period and one TBRG (Baud Rate Generator rollover count)
(TBRG) and the SCL pin is deasserted (pulled high). later, the SDA pin will be deasserted. When the SDA
When the SCL pin is sampled high (clock arbitration), pin is sampled high while SCL is high, the P bit of the
the Baud Rate Generator counts for TBRG. The SCL pin SSPSTAT register is set. A TBRG later, the PEN bit is
is then pulled low. Following this, the ACKEN bit is cleared and the SSPIF bit is set (Figure 28-31).
automatically cleared, the Baud Rate Generator is
turned off and the MSSP module then goes into Idle 28.6.9.1 WCOL Status Flag
mode (Figure 28-30). If the user writes the SSPBUF when a Stop sequence
is in progress, then the WCOL bit is set and the
28.6.8.1 WCOL Status Flag contents of the buffer are unchanged (the write does
If the user writes the SSPBUF when an Acknowledge not occur).
sequence is in progress, then WCOL bit is set and the
contents of the buffer are unchanged (the write does
not occur).
FIGURE 28-30: ACKNOWLEDGE SEQUENCE WAVEFORM
Acknowledge sequence starts here, ACKEN automatically cleared
write to SSPCON2
ACKEN = 1, ACKDT = 0
TBRG TBRG
SDA D0 ACK

SCL 8 9

SSPIF

Cleared in
SSPIF set at software
the end of receive Cleared in
software SSPIF set at the end
of Acknowledge sequence
Note: TBRG = one Baud Rate Generator period.

FIGURE 28-31: STOP CONDITION RECEIVE OR TRANSMIT MODE

Write to SSPCON2, SCL = 1 for TBRG, followed by SDA = 1 for TBRG
set PEN after SDA sampled high. P bit (SSPSTAT<4>) is set.

Falling edge of PEN bit (SSPCON2<2>) is cleared by

9th clock hardware and the SSPIF bit is set
TBRG
SCL

SDA ACK

P
TBRG TBRG TBRG
SCL brought high after TBRG
SDA asserted low before rising edge of clock
to setup Stop condition

Note: TBRG = one Baud Rate Generator period.

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PIC16(L)F1704/8
28.6.10 SLEEP OPERATION 28.6.13 MULTI -MASTER COMMUNICATION,
While in Sleep mode, the I2C slavemodule can receive BUS COLLISION AND BUS
addresses or data and when an address match or ARBITRATION
complete byte transfer occurs, wake the processor Multi-Master mode support is achieved by bus
from Sleep (if the MSSP interrupt is enabled). arbitration. When the master outputs address/data bits
onto the SDA pin, arbitration takes place when the
28.6.11 EFFECTS OF A RESET master outputs a ‘1’ on SDA, by letting SDA float high
A Reset disables the MSSP module and terminates the and another master asserts a ‘0’. When the SCL pin
current transfer. floats high, data should be stable. If the expected data
on SDA is a ‘1’ and the data sampled on the SDA pin is
28.6.12 MULTI-MASTER MODE ‘0’, then a bus collision has taken place. The master will
In Multi-Master mode, the interrupt generation on the set the Bus Collision Interrupt Flag, BCLIF and reset
detection of the Start and Stop conditions allows the the I2C port to its Idle state (Figure 28-32).
determination of when the bus is free. The Stop (P) and If a transmit was in progress when the bus collision
Start (S) bits are cleared from a Reset or when the occurred, the transmission is halted, the BF flag is
MSSP module is disabled. Control of the I 2C bus may cleared, the SDA and SCL lines are deasserted and the
be taken when the P bit of the SSPSTAT register is set, SSPBUF can be written to. When the user services the
or the bus is Idle, with both the S and P bits clear. When bus collision Interrupt Service Routine and if the I2C
the bus is busy, enabling the SSP interrupt will bus is free, the user can resume communication by
generate the interrupt when the Stop condition occurs. asserting a Start condition.
In multi-master operation, the SDA line must be If a Start, Repeated Start, Stop or Acknowledge
monitored for arbitration to see if the signal level is the condition was in progress when the bus collision
expected output level. This check is performed by occurred, the condition is aborted, the SDA and SCL
hardware with the result placed in the BCLIF bit. lines are deasserted and the respective control bits in
The states where arbitration can be lost are: the SSPCON2 register are cleared. When the user
services the bus collision Interrupt Service Routine and
• Address Transfer if the I2C bus is free, the user can resume
• Data Transfer communication by asserting a Start condition.
• A Start Condition The master will continue to monitor the SDA and SCL
• A Repeated Start Condition pins. If a Stop condition occurs, the SSPIF bit will be set.
• An Acknowledge Condition A write to the SSPBUF will start the transmission of
data at the first data bit, regardless of where the
transmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of Start and Stop conditions allows the
determination of when the bus is free. Control of the I2C
bus can be taken when the P bit is set in the SSPSTAT
register, or the bus is Idle and the S and P bits are
cleared.

FIGURE 28-32: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE

Sample SDA. While SCL is high,
Data changes SDA line pulled low data does not match what is driven
while SCL = 0 by another source by the master.
Bus collision has occurred.
SDA released
by master

SDA

SCL Set bus collision

interrupt (BCLIF)

BCLIF

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 PIC16(L)F1704/8
28.6.13.1 Bus Collision During a Start If the SDA pin is sampled low during this count, the
Condition BRG is reset and the SDA line is asserted early
(Figure 28-35). If, however, a ‘1’ is sampled on the SDA
During a Start condition, a bus collision occurs if:
pin, the SDA pin is asserted low at the end of the BRG
a) SDA or SCL are sampled low at the beginning of count. The Baud Rate Generator is then reloaded and
the Start condition (Figure 28-33). counts down to zero; if the SCL pin is sampled as ‘0’
b) SCL is sampled low before SDA is asserted low during this time, a bus collision does not occur. At the
(Figure 28-34). end of the BRG count, the SCL pin is asserted low.
During a Start condition, both the SDA and the SCL Note: The reason that bus collision is not a
pins are monitored. factor during a Start condition is that no
If the SDA pin is already low, or the SCL pin is already two bus masters can assert a Start
low, then all of the following occur: condition at the exact same time.
Therefore, one master will always assert
• the Start condition is aborted,
SDA before the other. This condition does
• the BCLIF flag is set and not cause a bus collision because the two
• the MSSP module is reset to its Idle state masters must be allowed to arbitrate the
(Figure 28-33). first address following the Start condition.
The Start condition begins with the SDA and SCL pins If the address is the same, arbitration
deasserted. When the SDA pin is sampled high, the must be allowed to continue into the data
Baud Rate Generator is loaded and counts down. If the portion, Repeated Start or Stop
SCL pin is sampled low while SDA is high, a bus conditions.
collision occurs because it is assumed that another
master is attempting to drive a data ‘1’ during the Start
condition.

FIGURE 28-33: BUS COLLISION DURING START CONDITION (SDA ONLY)

SDA goes low before the SEN bit is set.
Set BCLIF,
S bit and SSPIF set because
SDA = 0, SCL = 1.

SDA

SCL
Set SEN, enable Start SEN cleared automatically because of bus collision.
condition if SDA = 1, SCL = 1 SSP module reset into Idle state.
SEN
SDA sampled low before
Start condition. Set BCLIF.
S bit and SSPIF set because
BCLIF SDA = 0, SCL = 1.
SSPIF and BCLIF are
cleared by software

SSPIF

SSPIF and BCLIF are

cleared by software

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PIC16(L)F1704/8
FIGURE 28-34: BUS COLLISION DURING START CONDITION (SCL = 0)
SDA = 0, SCL = 1

TBRG TBRG

SDA

SCL Set SEN, enable Start

sequence if SDA = 1, SCL = 1
SCL = 0 before SDA = 0,
bus collision occurs. Set BCLIF.
SEN
SCL = 0 before BRG time-out,
bus collision occurs. Set BCLIF.
BCLIF
Interrupt cleared
by software
S ’0’ ’0’

SSPIF ’0’ ’0’

FIGURE 28-35: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA = 0, SCL = 1
Set S Set SSPIF
Less than TBRG
TBRG

SDA SDA pulled low by other master.

Reset BRG and assert SDA.

SCL S
SCL pulled low after BRG
time-out
SEN
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
BCLIF ’0’

SSPIF
SDA = 0, SCL = 1, Interrupts cleared
set SSPIF by software

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 PIC16(L)F1704/8
28.6.13.2 Bus Collision During a Repeated If SDA is low, a bus collision has occurred (i.e., another
Start Condition master is attempting to transmit a data ‘0’, Figure 28-36).
If SDA is sampled high, the BRG is reloaded and begins
During a Repeated Start condition, a bus collision
counting. If SDA goes from high-to-low before the BRG
occurs if:
times out, no bus collision occurs because no two
a) A low level is sampled on SDA when SCL goes masters can assert SDA at exactly the same time.
from low level to high level (Case 1).
If SCL goes from high-to-low before the BRG times out
b) SCL goes low before SDA is asserted low, and SDA has not already been asserted, a bus collision
indicating that another master is attempting to occurs. In this case, another master is attempting to
transmit a data ‘1’ (Case 2). transmit a data ‘1’ during the Repeated Start condition,
When the user releases SDA and the pin is allowed to see Figure 28-37.
float high, the BRG is loaded with SSPADD and counts If, at the end of the BRG time-out, both SCL and SDA
down to zero. The SCL pin is then deasserted and are still high, the SDA pin is driven low and the BRG is
when sampled high, the SDA pin is sampled. reloaded and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated Start condition is
complete.

FIGURE 28-36: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)

SDA

SCL

Sample SDA when SCL goes high.

If SDA = 0, set BCLIF and release SDA and SCL.

RSEN

BCLIF

Cleared by software
S ’0’

SSPIF ’0’

FIGURE 28-37: BUS COLLISION DURING REPEATED START CONDITION (CASE 2)

TBRG TBRG

SDA

SCL

SCL goes low before SDA,

BCLIF set BCLIF. Release SDA and SCL.
Interrupt cleared
by software
RSEN

S ’0’

SSPIF

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PIC16(L)F1704/8
28.6.13.3 Bus Collision During a Stop The Stop condition begins with SDA asserted low.
Condition When SDA is sampled low, the SCL pin is allowed to
float. When the pin is sampled high (clock arbitration),
Bus collision occurs during a Stop condition if:
the Baud Rate Generator is loaded with SSPADD and
a) After the SDA pin has been deasserted and counts down to zero. After the BRG times out, SDA is
allowed to float high, SDA is sampled low after sampled. If SDA is sampled low, a bus collision has
the BRG has timed out (Case 1). occurred. This is due to another master attempting to
b) After the SCL pin is deasserted, SCL is sampled drive a data ‘0’ (Figure 28-38). If the SCL pin is sampled
low before SDA goes high (Case 2). low before SDA is allowed to float high, a bus collision
occurs. This is another case of another master
attempting to drive a data ‘0’ (Figure 28-39).

FIGURE 28-38: BUS COLLISION DURING A STOP CONDITION (CASE 1)

TBRG TBRG TBRG SDA sampled

low after TBRG,
set BCLIF
SDA

SDA asserted low

SCL

PEN

BCLIF

P ’0’

SSPIF ’0’

FIGURE 28-39: BUS COLLISION DURING A STOP CONDITION (CASE 2)

TBRG TBRG TBRG

SDA

Assert SDA SCL goes low before SDA goes high,

set BCLIF
SCL

PEN

BCLIF

P ’0’

SSPIF ’0’

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 PIC16(L)F1704/8
TABLE 28-3: SUMMARY OF REGISTERS ASSOCIATED WITH I2C OPERATION
Reset
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on
Page:

ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 122

ANSELB(1) — — ANSB5 ANSB4 — — — — 128
(1) (1) (2) (2)
ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 ANSC1 ANSC0 133
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 85
PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 86
PIE2 OSFIE C2IE C1IE — BCL1IE TMR6IE TMR4IE CCP2IE 87
PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 89
PIR2 OSFIF C2IF C1IF — BCL1IF TMR6IF TMR4IF CCP2IF 90
RxyPPS — — — RxyPPS<4:0> 140
SSPCLKPPS — — — SSPCLKPPS<4:0> 138, 139
SSPDATPPS — — — SSPDATPPS<4:0> 138, 139
SSPSSPPS — — — SSPSSPPS<4:0> 138, 139
SSP1ADD ADD<7:0> 323
SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register 272*
SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 319
SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 321
SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 322
SSP1MSK MSK<7:0> 323
SSP1STAT SMP CKE D/A P S R/W UA BF 317
TRISA — — TRISA5 TRISA4 —(3) TRISA2 TRISA1 TRISA0 121
(1)
TRISB TRISB7 TRISB6 TRISB5 TRISB4 — — — — 127
TRISC TRISC7(1) TRISC6(1) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISA0 132
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP module in I2C mode.
* Page provides register information.
Note 1: PIC16(L)F1708 only.
2: PIC16(L)F1704 only.
3: Unimplemented, read as ‘1’.

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PIC16(L)F1704/8
28.7 BAUD RATE GENERATOR clock line. The logic dictating when the reload signal is
asserted depends on the mode the MSSP is being
The MSSP module has a Baud Rate Generator operated in.
available for clock generation in both I2C SPI Master
Table 28-4 demonstrates clock rates based on
modes. The Baud Rate Generator (BRG) reload value
instruction cycles and the BRG value loaded into
is placed in the SSPADD register (Register 28-6).
SSPADD.
When a write occurs to SSPBUF, the Baud Rate
Generator will automatically begin counting down.
EQUATION 28-1:
Once the given operation is complete, the internal clock
will automatically stop counting and the clock pin will FOSC
remain in its last state. FCLOCK = -------------------------------------------------
 SSPxADD + 1   4 
An internal signal “Reload” in Figure 28-40 triggers the
value from SSPADD to be loaded into the BRG counter.
This occurs twice for each oscillation of the module

FIGURE 28-40: BAUD RATE GENERATOR BLOCK DIAGRAM

SSPM<3:0> SSPADD<7:0>

SSPM<3:0> Reload Reload

SCL Control

SSPCLK BRG Down Counter FOSC/2

Note: Values of 0x00, 0x01 and 0x02 are not valid

for SSPADD when used as a Baud Rate
Generator for I2C. This is an implementation
limitation.

TABLE 28-4: MSSP CLOCK RATE W/BRG

FCLOCK
FOSC FCY BRG Value
(2 Rollovers of BRG)
32 MHz 8 MHz 13h 400 kHz
32 MHz 8 MHz 19h 308 kHz
32 MHz 8 MHz 4Fh 100 kHz
16 MHz 4 MHz 09h 400 kHz
16 MHz 4 MHz 0Ch 308 kHz
16 MHz 4 MHz 27h 100 kHz
4 MHz 1 MHz 09h 100 kHz
Note: Refer to the I/O port electrical specifications in Table 32-4 to ensure the system is designed to support IOL
requirements.

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 PIC16(L)F1704/8
28.8 Register Definitions: MSSP Control
REGISTER 28-1: SSP1STAT: SSP STATUS REGISTER
R/W-0/0 R/W-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0
SMP CKE D/A P S R/W UA BF
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 SMP: SPI Data Input Sample bit

SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode
In I2 C Master or Slave mode:
1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz)
0 = Slew rate control enabled for High-Speed mode (400 kHz)
bit 6 CKE: SPI Clock Edge Select bit (SPI mode only)
In SPI Master or Slave mode:
1 = Transmit occurs on transition from active to Idle clock state
0 = Transmit occurs on transition from Idle to active clock state
In I2 C™ mode only:
1 = Enable input logic so that thresholds are compliant with SMBus specification
0 = Disable SMBus specific inputs
bit 5 D/A: Data/Address bit (I2C mode only)
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
bit 4 P: Stop bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1 = Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset)
0 = Stop bit was not detected last
bit 3 S: Start bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1 = Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset)
0 = Start bit was not detected last
bit 2 R/W: Read/Write bit information (I2C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from the
address match to the next Start bit, Stop bit, or not ACK bit.
In I2 C Slave mode:
1 = Read
0 = Write
In I2 C Master mode:
1 = Transmit is in progress
0 = Transmit is not in progress
OR-ing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Idle mode.
bit 1 UA: Update Address bit (10-bit I2C mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated

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REGISTER 28-1: SSP1STAT: SSP STATUS REGISTER (CONTINUED)
bit 0 BF: Buffer Full Status bit
Receive (SPI and I2 C modes):
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Transmit (I2 C mode only):
1 = Data transmit in progress (does not include the ACK and Stop bits), SSPBUF is full
0 = Data transmit complete (does not include the ACK and Stop bits), SSPBUF is empty

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REGISTER 28-2: SSP1CON1: SSP CONTROL REGISTER 1

R/C/HS-0/0 R/C/HS-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
WCOL SSPOV(1) SSPEN CKP SSPM<3:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS = Bit is set by hardware C = User cleared

bit 7 WCOL: Write Collision Detect bit

Master mode:
1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a trans-
mission to be started
0 = No collision
Slave mode:
1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software)
0 = No collision
bit 6 SSPOV: Receive Overflow Indicator bit(1)
In SPI mode:
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow,
the data in SSPSR is lost. Overflow can only occur in Slave mode. In Slave mode, the user must read
the SSPBUF, even if only transmitting data, to avoid setting overflow. In Master mode, the overflow bit
is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register
(must be cleared in software).
0 = No overflow
In I2 C mode:
1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a “don’t
care” in Transmit mode (must be cleared in software).
0 = No overflow
bit 5 SSPEN: Synchronous Serial Port Enable bit
In both modes, when enabled, these pins must be properly configured as input or output
In SPI mode:
1 = Enables serial port and configures SCK, SDO, SDI and SS as the source of the serial port pins(2)
0 = Disables serial port and configures these pins as I/O port pins
In I2 C mode:
1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins(3)
0 = Disables serial port and configures these pins as I/O port pins
bit 4 CKP: Clock Polarity Select bit
In SPI mode:
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
In I2 C Slave mode:
SCL release control
1 = Enable clock
0 = Holds clock low (clock stretch). (Used to ensure data setup time.)
In I2 C Master mode:
Unused in this mode

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REGISTER 28-2: SSP1CON1: SSP CONTROL REGISTER 1 (CONTINUED)
bit 3-0 SSPM<3:0>: Synchronous Serial Port Mode Select bits
1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
1101 = Reserved
1100 = Reserved
1011 = I2C firmware controlled Master mode (slave idle)
1010 = SPI Master mode, clock = FOSC/(4 * (SSPADD+1))(5)
1001 = Reserved
1000 = I2C Master mode, clock = FOSC / (4 * (SSPADD+1))(4)
0111 = I2C Slave mode, 10-bit address
0110 = I2C Slave mode, 7-bit address
0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin
0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled
0011 = SPI Master mode, clock = T2_match/2
0010 = SPI Master mode, clock = FOSC/64
0001 = SPI Master mode, clock = FOSC/16
0000 = SPI Master mode, clock = FOSC/4
Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by
writing to the SSPBUF register.
2: When enabled, these pins must be properly configured as input or output. Use SSPSSPPS, SSPCLKPPS,
SSPDATPPS, and RxyPPS to select the pins.
3: When enabled, the SDA and SCL pins must be configured as inputs. Use SSPCLKPPS, SSPDATPPS,
and RxyPPS to select the pins.
4: SSPADD values of 0, 1 or 2 are not supported for I2C mode.
5: SSPADD value of ‘0’ is not supported. Use SSPM = 0000 instead.

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REGISTER 28-3: SSP1CON2: SSP CONTROL REGISTER 2(1)

R/W-0/0 R-0/0 R/W-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/W/HS-0/0
GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HC = Cleared by hardware S = User set

bit 7 GCEN: General Call Enable bit (in I2C Slave mode only)
1 = Enable interrupt when a general call address (0x00 or 00h) is received in the SSPSR
0 = General call address disabled
bit 6 ACKSTAT: Acknowledge Status bit (in I2C mode only)
1 = Acknowledge was not received
0 = Acknowledge was received
bit 5 ACKDT: Acknowledge Data bit (in I2C mode only)
In Receive mode:
Value transmitted when the user initiates an Acknowledge sequence at the end of a receive
1 = Not Acknowledge
0 = Acknowledge
bit 4 ACKEN: Acknowledge Sequence Enable bit (in I2C Master mode only)
In Master Receive mode:
1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit.
Automatically cleared by hardware.
0 = Acknowledge sequence idle
bit 3 RCEN: Receive Enable bit (in I2C Master mode only)
1 = Enables Receive mode for I2C
0 = Receive idle
bit 2 PEN: Stop Condition Enable bit (in I2C Master mode only)
SCKMSSP Release Control:
1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Stop condition Idle
bit 1 RSEN: Repeated Start Condition Enable bit (in I2C Master mode only)
1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Repeated Start condition Idle
bit 0 SEN: Start Condition Enable/Stretch Enable bit
In Master mode:
1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Start condition Idle
In Slave mode:
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is disabled

Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be
set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled).

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REGISTER 28-4: SSP1CON3: SSP CONTROL REGISTER 3

R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
ACKTIM(3) PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 ACKTIM: Acknowledge Time Status bit (I2C mode only)(3)

1 = Indicates the I2C bus is in an Acknowledge sequence, set on eighth falling edge of SCL clock
0 = Not an Acknowledge sequence, cleared on 9TH rising edge of SCL clock
bit 6 PCIE: Stop Condition Interrupt Enable bit (I2C mode only)
1 = Enable interrupt on detection of Stop condition
0 = Stop detection interrupts are disabled(2)
bit 5 SCIE: Start Condition Interrupt Enable bit (I2C mode only)
1 = Enable interrupt on detection of Start or Restart conditions
0 = Start detection interrupts are disabled(2)
bit 4 BOEN: Buffer Overwrite Enable bit
In SPI Slave mode:(1)
1 = SSPBUF updates every time that a new data byte is shifted in ignoring the BF bit
0 = If new byte is received with BF bit of the SSPSTAT register already set, SSPOV bit of the
SSPCON1 register is set, and the buffer is not updated
In I2C Master mode and SPI Master mode:
This bit is ignored.
In I2C Slave mode:
1 = SSPBUF is updated and ACK is generated for a received address/data byte, ignoring the state
of the SSPOV bit only if the BF bit = 0.
0 = SSPBUF is only updated when SSPOV is clear
bit 3 SDAHT: SDA Hold Time Selection bit (I2C mode only)
1 = Minimum of 300 ns hold time on SDA after the falling edge of SCL
0 = Minimum of 100 ns hold time on SDA after the falling edge of SCL
bit 2 SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only)
If, on the rising edge of SCL, SDA is sampled low when the module is outputting a high state, the
BCL1IF bit of the PIR2 register is set, and bus goes idle
1 = Enable slave bus collision interrupts
0 = Slave bus collision interrupts are disabled
bit 1 AHEN: Address Hold Enable bit (I2C Slave mode only)
1 = Following the eighth falling edge of SCL for a matching received address byte; CKP bit of the
SSPCON1 register will be cleared and the SCL will be held low.
0 = Address holding is disabled
bit 0 DHEN: Data Hold Enable bit (I2C Slave mode only)
1 = Following the eighth falling edge of SCL for a received data byte; slave hardware clears the CKP
bit of the SSPCON1 register and SCL is held low.
0 = Data holding is disabled

Note 1: For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPOV is still set
when a new byte is received and BF = 1, but hardware continues to write the most recent byte to SSPBUF.
2: This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled.
3: The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set.

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REGISTER 28-5: SSP1MSK: SSP MASK REGISTER

R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1
MSK<7:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-1 MSK<7:1>: Mask bits

1 = The received address bit n is compared to SSPADD<n> to detect I2C address match
0 = The received address bit n is not used to detect I2C address match
bit 0 MSK<0>: Mask bit for I2C Slave mode, 10-bit Address
I2C Slave mode, 10-bit address (SSPM<3:0> = 0111 or 1111):
1 = The received address bit 0 is compared to SSPADD<0> to detect I2C address match
0 = The received address bit 0 is not used to detect I2C address match
I2C Slave mode, 7-bit address, the bit is ignored

REGISTER 28-6: SSP1ADD: MSSP ADDRESS AND BAUD RATE REGISTER (I2C MODE)
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
ADD<7:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

Master mode:

bit 7-0 ADD<7:0>: Baud Rate Clock Divider bits

SCL pin clock period = ((ADD<7:0> + 1) *4)/FOSC
10-Bit Slave mode – Most Significant Address Byte:

bit 7-3 Not used: Unused for Most Significant Address Byte. Bit state of this register is a “don’t care”. Bit
pattern sent by master is fixed by I2C specification and must be equal to ‘11110’. However, those bits
are compared by hardware and are not affected by the value in this register.
bit 2-1 ADD<2:1>: Two Most Significant bits of 10-bit address
bit 0 Not used: Unused in this mode. Bit state is a “don’t care”.
10-Bit Slave mode – Least Significant Address Byte:

bit 7-0 ADD<7:0>: Eight Least Significant bits of 10-bit address

7-Bit Slave mode:

bit 7-1 ADD<7:1>: 7-bit address

bit 0 Not used: Unused in this mode. Bit state is a “don’t care”.

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29.0 ENHANCED UNIVERSAL The EUSART module includes the following capabilities:
SYNCHRONOUS • Full-duplex asynchronous transmit and receive
ASYNCHRONOUS RECEIVER • Two-character input buffer
TRANSMITTER (EUSART) • One-character output buffer
• Programmable 8-bit or 9-bit character length
The Enhanced Universal Synchronous Asynchronous
• Address detection in 9-bit mode
Receiver Transmitter (EUSART) module is a serial I/O
communications peripheral. It contains all the clock • Input buffer overrun error detection
generators, shift registers and data buffers necessary • Received character framing error detection
to perform an input or output serial data transfer • Half-duplex synchronous master
independent of device program execution. The • Half-duplex synchronous slave
EUSART, also known as a Serial Communications • Programmable clock polarity in synchronous
Interface (SCI), can be configured as a full-duplex modes
asynchronous system or half-duplex synchronous
• Sleep operation
system. Full-Duplex mode is useful for
communications with peripheral systems, such as CRT The EUSART module implements the following
terminals and personal computers. Half-Duplex additional features, making it ideally suited for use in
Synchronous mode is intended for communications Local Interconnect Network (LIN) bus systems:
with peripheral devices, such as A/D or D/A integrated • Automatic detection and calibration of the baud rate
circuits, serial EEPROMs or other microcontrollers.
• Wake-up on Break reception
These devices typically do not have internal clocks for
baud rate generation and require the external clock • 13-bit Break character transmit
signal provided by a master synchronous device. Block diagrams of the EUSART transmitter and
receiver are shown in Figure 29-1 and Figure 29-2.
The EUSART transmit output (TX_out) is available to
the TX/CK pin and internally to the following peripherals:
• Configurable Logic Cell (CLC)

FIGURE 29-1: EUSART TRANSMIT BLOCK DIAGRAM

Data Bus
TXIE
Interrupt
TXREG Register TXIF
8
MSb LSb TX/CK pin
(8) 0 Pin Buffer
• • • and Control
Transmit Shift Register (TSR)
TX_out

TXEN

TRMT
Baud Rate Generator FOSC
÷n
TX9
BRG16 n
+1 Multiplier x4 x16 x64
TX9D
SYNC 1 X 0 0 0
SPBRGH SPBRGL BRGH X 1 1 0 0
BRG16 X 1 0 1 0

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FIGURE 29-2: EUSART RECEIVE BLOCK DIAGRAM

SPEN CREN OERR RCIDL

RX/DT pin MSb RSR Register LSb

Pin Buffer Data
and Control Recovery
Stop (8) 7 ••• 1 0 Start

Baud Rate Generator FOSC RX9

÷n

BRG16
+1 n
Multiplier x4 x16 x64
SYNC 1 X 0 0 0
SPBRGH SPBRGL BRGH FIFO
X 1 1 0 0 FERR RX9D RCREG Register
BRG16 X 1 0 1 0
8
Data Bus

RCIF Interrupt
RCIE

The operation of the EUSART module is controlled

through three registers:
• Transmit Status and Control (TXSTA)
• Receive Status and Control (RCSTA)
• Baud Rate Control (BAUDCON)
These registers are detailed in Register 29-1,
Register 29-2 and Register 29-3, respectively.
The RX and CK input pins are selected with the RXPPS
and CKPPS registers, respectively. TX, CK, and DT
output pins are selected with each pin’s RxyPPS register.
Since the RX input is coupled with the DT output in
Synchronous mode, it is the user’s responsibility to select
the same pin for both of these functions when operating
in Synchronous mode. The EUSART control logic will
control the data direction drivers automatically.

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29.1 EUSART Asynchronous Mode 29.1.1.2 Transmitting Data
The EUSART transmits and receives data using the A transmission is initiated by writing a character to the
standard non-return-to-zero (NRZ) format. NRZ is TXREG register. If this is the first character, or the
implemented with two levels: a VOH mark state which previous character has been completely flushed from
represents a ‘1’ data bit, and a VOL space state which the TSR, the data in the TXREG is immediately
represents a ‘0’ data bit. NRZ refers to the fact that transferred to the TSR register. If the TSR still contains
consecutively transmitted data bits of the same value all or part of a previous character, the new character
stay at the output level of that bit without returning to a data is held in the TXREG until the Stop bit of the
neutral level between each bit transmission. An NRZ previous character has been transmitted. The pending
transmission port idles in the mark state. Each character character in the TXREG is then transferred to the TSR
transmission consists of one Start bit followed by eight in one TCY immediately following the Stop bit
or nine data bits and is always terminated by one or transmission. The transmission of the Start bit, data bits
more Stop bits. The Start bit is always a space and the and Stop bit sequence commences immediately
Stop bits are always marks. The most common data following the transfer of the data to the TSR from the
format is eight bits. Each transmitted bit persists for a TXREG.
period of 1/(Baud Rate). An on-chip dedicated
8-bit/16-bit Baud Rate Generator is used to derive 29.1.1.3 Transmit Data Polarity
standard baud rate frequencies from the system The polarity of the transmit data can be controlled with
oscillator. See Table 29-5 for examples of baud rate the SCKP bit of the BAUDCON register. The default
configurations. state of this bit is ‘0’ which selects high true transmit idle
The EUSART transmits and receives the LSb first. The and data bits. Setting the SCKP bit to ‘1’ will invert the
EUSART’s transmitter and receiver are functionally transmit data resulting in low true idle and data bits. The
independent, but share the same data format and baud SCKP bit controls transmit data polarity in
rate. Parity is not supported by the hardware, but can Asynchronous mode only. In Synchronous mode, the
be implemented in software and stored as the ninth SCKP bit has a different function. See Section 29.5.1.2
data bit. “Clock Polarity”.

29.1.1 EUSART ASYNCHRONOUS 29.1.1.4 Transmit Interrupt Flag

TRANSMITTER The TXIF interrupt flag bit of the PIR1 register is set
whenever the EUSART transmitter is enabled and no
The EUSART transmitter block diagram is shown in
character is being held for transmission in the TXREG.
Figure 29-1. The heart of the transmitter is the serial
In other words, the TXIF bit is only clear when the TSR
Transmit Shift Register (TSR), which is not directly
is busy with a character and a new character has been
accessible by software. The TSR obtains its data from
queued for transmission in the TXREG. The TXIF flag bit
the transmit buffer, which is the TXREG register.
is not cleared immediately upon writing TXREG. TXIF
29.1.1.1 Enabling the Transmitter becomes valid in the second instruction cycle following
the write execution. Polling TXIF immediately following
The EUSART transmitter is enabled for asynchronous the TXREG write will return invalid results. The TXIF bit
operations by configuring the following three control is read-only, it cannot be set or cleared by software.
bits:
The TXIF interrupt can be enabled by setting the TXIE
• TXEN = 1 interrupt enable bit of the PIE1 register. However, the
• SYNC = 0 TXIF flag bit will be set whenever the TXREG is empty,
• SPEN = 1 regardless of the state of TXIE enable bit.
All other EUSART control bits are assumed to be in To use interrupts when transmitting data, set the TXIE
their default state. bit only when there is more data to send. Clear the
TXIE interrupt enable bit upon writing the last character
Setting the TXEN bit of the TXSTA register enables the
of the transmission to the TXREG.
transmitter circuitry of the EUSART. Clearing the SYNC
bit of the TXSTA register configures the EUSART for
asynchronous operation. Setting the SPEN bit of the
RCSTA register enables the EUSART and automatically
configures the TX/CK I/O pin as an output. If the TX/CK
pin is shared with an analog peripheral, the analog I/O
function must be disabled by clearing the corresponding
ANSEL bit.
Note: The TXIF Transmitter Interrupt flag is set
when the TXEN enable bit is set.

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29.1.1.5 TSR Status 29.1.1.7 Asynchronous Transmission Set-up:
The TRMT bit of the TXSTA register indicates the 1. Initialize the SPBRGH, SPBRGL register pair and
status of the TSR register. This is a read-only bit. The the BRGH and BRG16 bits to achieve the desired
TRMT bit is set when the TSR register is empty and is baud rate (see Section 29.4 “EUSART Baud
cleared when a character is transferred to the TSR Rate Generator (BRG)”).
register from the TXREG. The TRMT bit remains clear 2. Enable the asynchronous serial port by clearing
until all bits have been shifted out of the TSR register. the SYNC bit and setting the SPEN bit.
No interrupt logic is tied to this bit, so the user has to 3. If 9-bit transmission is desired, set the TX9
poll this bit to determine the TSR status. control bit. A set ninth data bit will indicate that
Note: The TSR register is not mapped in data the eight Least Significant data bits are an
memory, so it is not available to the user. address when the receiver is set for address
detection.
29.1.1.6 Transmitting 9-Bit Characters 4. Set SCKP bit if inverted transmit is desired.
The EUSART supports 9-bit character transmissions. 5. Enable the transmission by setting the TXEN
When the TX9 bit of the TXSTA register is set, the control bit. This will cause the TXIF interrupt bit
EUSART will shift nine bits out for each character to be set.
transmitted. The TX9D bit of the TXSTA register is the 6. If interrupts are desired, set the TXIE interrupt
ninth, and Most Significant data bit. When transmitting enable bit of the PIE1 register. An interrupt will
9-bit data, the TX9D data bit must be written before occur immediately provided that the GIE and
writing the eight Least Significant bits into the TXREG. PEIE bits of the INTCON register are also set.
All nine bits of data will be transferred to the TSR shift 7. If 9-bit transmission is selected, the ninth bit
register immediately after the TXREG is written. should be loaded into the TX9D data bit.
A special 9-bit Address mode is available for use with 8. Load 8-bit data into the TXREG register. This
multiple receivers. See Section 29.1.2.7 “Address will start the transmission.
Detection” for more information on the Address mode.

FIGURE 29-3: ASYNCHRONOUS TRANSMISSION

Write to TXREG
Word 1
BRG Output
(Shift Clock)
TX/CK
pin Start bit bit 0 bit 1 bit 7/8 Stop bit
Word 1
TXIF bit
(Transmit Buffer 1 TCY
Reg. Empty Flag)

TRMT bit Word 1

Transmit Shift Reg.
(Transmit Shift
Reg. Empty Flag)

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FIGURE 29-4: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)

Write to TXREG
Word 1 Word 2
BRG Output
(Shift Clock)
TX/CK
pin Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0
TXIF bit 1 TCY Word 1 Word 2
(Transmit Buffer
Reg. Empty Flag) 1 TCY

TRMT bit Word 1 Word 2

(Transmit Shift Transmit Shift Reg. Transmit Shift Reg.
Reg. Empty Flag)

Note: This timing diagram shows two consecutive transmissions.

TABLE 29-1: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION

Register on
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Page

ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 122

ANSELB(1) — — ANSB5 ANSB4 — — — — 128
ANSELC ANSC7(1) ANSC6(1) ANSC5(2) ANSC4(2) ANSC3 ANSC2 ANSC1 ANSC0 133
BAUD1CON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 336
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 85
PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 86
PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 89
RC1STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 335
RxyPPS — — — RxyPPS<4:0> 140
SP1BRGL BRG<7:0> 337*
SP1BRGH BRG<15:8> 337*
TRISA — — TRISA5 TRISA4 —(3) TRISA2 TRISA1 TRISA0 121
TRISB(2) TRISB7 TRISB6 TRISB5 TRISB4 — — — — 127
TRISC TRISC7(1) TRISC6(1) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 132
TX1REG EUSART Transmit Data Register 326*
TX1STA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 334
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for asynchronous transmission.
* Page provides register information.
Note 1: PIC16(L)F1708 only.
2: PIC16(L)F1704 only.
3: Unimplemented, read as ‘1’.

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29.1.2 EUSART ASYNCHRONOUS 29.1.2.2 Receiving Data
RECEIVER The receiver data recovery circuit initiates character
The Asynchronous mode is typically used in RS-232 reception on the falling edge of the first bit. The first bit,
systems. The receiver block diagram is shown in also known as the Start bit, is always a zero. The data
Figure 29-2. The data is received on the RX/DT pin and recovery circuit counts one-half bit time to the center of
drives the data recovery block. The data recovery block the Start bit and verifies that the bit is still a zero. If it is
is actually a high-speed shifter operating at 16 times not a zero then the data recovery circuit aborts
the baud rate, whereas the serial Receive Shift character reception, without generating an error, and
Register (RSR) operates at the bit rate. When all eight resumes looking for the falling edge of the Start bit. If
or nine bits of the character have been shifted in, they the Start bit zero verification succeeds then the data
are immediately transferred to a two character recovery circuit counts a full bit time to the center of the
First-In-First-Out (FIFO) memory. The FIFO buffering next bit. The bit is then sampled by a majority detect
allows reception of two complete characters and the circuit and the resulting ‘0’ or ‘1’ is shifted into the RSR.
start of a third character before software must start This repeats until all data bits have been sampled and
servicing the EUSART receiver. The FIFO and RSR shifted into the RSR. One final bit time is measured and
registers are not directly accessible by software. the level sampled. This is the Stop bit, which is always
Access to the received data is via the RCREG register. a ‘1’. If the data recovery circuit samples a ‘0’ in the
Stop bit position then a framing error is set for this
29.1.2.1 Enabling the Receiver character, otherwise the framing error is cleared for this
The EUSART receiver is enabled for asynchronous character. See Section 29.1.2.4 “Receive Framing
operation by configuring the following three control bits: Error” for more information on framing errors.

• CREN = 1 Immediately after all data bits and the Stop bit have
been received, the character in the RSR is transferred
• SYNC = 0
to the EUSART receive FIFO and the RCIF interrupt
• SPEN = 1 flag bit of the PIR1 register is set. The top character in
All other EUSART control bits are assumed to be in the FIFO is transferred out of the FIFO by reading the
their default state. RCREG register.
Setting the CREN bit of the RCSTA register enables the Note: If the receive FIFO is overrun, no additional
receiver circuitry of the EUSART. Clearing the SYNC bit characters will be received until the overrun
of the TXSTA register configures the EUSART for condition is cleared. See Section 29.1.2.5
asynchronous operation. Setting the SPEN bit of the “Receive Overrun Error” for more
RCSTA register enables the EUSART. The programmer information on overrun errors.
must set the corresponding TRIS bit to configure the
RX/DT I/O pin as an input. 29.1.2.3 Receive Interrupts
Note: If the RX/DT function is on an analog pin, The RCIF interrupt flag bit of the PIR1 register is set
the corresponding ANSEL bit must be whenever the EUSART receiver is enabled and there is
cleared for the receiver to function. an unread character in the receive FIFO. The RCIF
interrupt flag bit is read-only, it cannot be set or cleared
by software.
RCIF interrupts are enabled by setting all of the
following bits:
• RCIE, Interrupt Enable bit of the PIE1 register
• PEIE, Peripheral Interrupt Enable bit of the
INTCON register
• GIE, Global Interrupt Enable bit of the INTCON
register
The RCIF interrupt flag bit will be set when there is an
unread character in the FIFO, regardless of the state of
interrupt enable bits.

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29.1.2.4 Receive Framing Error 29.1.2.7 Address Detection
Each character in the receive FIFO buffer has a A special Address Detection mode is available for use
corresponding framing error Status bit. A framing error when multiple receivers share the same transmission
indicates that a Stop bit was not seen at the expected line, such as in RS-485 systems. Address detection is
time. The framing error status is accessed via the enabled by setting the ADDEN bit of the RCSTA
FERR bit of the RCSTA register. The FERR bit register.
represents the status of the top unread character in the Address detection requires 9-bit character reception.
receive FIFO. Therefore, the FERR bit must be read When address detection is enabled, only characters
before reading the RCREG. with the ninth data bit set will be transferred to the
The FERR bit is read-only and only applies to the top receive FIFO buffer, thereby setting the RCIF interrupt
unread character in the receive FIFO. A framing error bit. All other characters will be ignored.
(FERR = 1) does not preclude reception of additional Upon receiving an address character, user software
characters. It is not necessary to clear the FERR bit. determines if the address matches its own. Upon
Reading the next character from the FIFO buffer will address match, user software must disable address
advance the FIFO to the next character and the next detection by clearing the ADDEN bit before the next
corresponding framing error. Stop bit occurs. When user software detects the end of
The FERR bit can be forced clear by clearing the SPEN the message, determined by the message protocol
bit of the RCSTA register which resets the EUSART. used, software places the receiver back into the
Clearing the CREN bit of the RCSTA register does not Address Detection mode by setting the ADDEN bit.
affect the FERR bit. A framing error by itself does not
generate an interrupt.
Note: If all receive characters in the receive
FIFO have framing errors, repeated reads
of the RCREG will not clear the FERR bit.

29.1.2.5 Receive Overrun Error

The receive FIFO buffer can hold two characters. An
overrun error will be generated if a third character, in its
entirety, is received before the FIFO is accessed. When
this happens the OERR bit of the RCSTA register is set.
The characters already in the FIFO buffer can be read
but no additional characters will be received until the
error is cleared. The error must be cleared by either
clearing the CREN bit of the RCSTA register or by
resetting the EUSART by clearing the SPEN bit of the
RCSTA register.

29.1.2.6 Receiving 9-Bit Characters

The EUSART supports 9-bit character reception. When
the RX9 bit of the RCSTA register is set the EUSART
will shift nine bits into the RSR for each character
received. The RX9D bit of the RCSTA register is the
ninth and Most Significant data bit of the top unread
character in the receive FIFO. When reading 9-bit data
from the receive FIFO buffer, the RX9D data bit must
be read before reading the eight Least Significant bits
from the RCREG.

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29.1.2.8 Asynchronous Reception Set-up: 29.1.2.9 9-bit Address Detection Mode Set-up
1. Initialize the SPBRGH, SPBRGL register pair This mode would typically be used in RS-485 systems.
and the BRGH and BRG16 bits to achieve the To set up an Asynchronous Reception with Address
desired baud rate (see Section 29.4 “EUSART Detect Enable:
Baud Rate Generator (BRG)”). 1. Initialize the SPBRGH, SPBRGL register pair
2. Clear the ANSEL bit for the RX pin (if applicable). and the BRGH and BRG16 bits to achieve the
3. Enable the serial port by setting the SPEN bit. desired baud rate (see Section 29.4 “EUSART
The SYNC bit must be clear for asynchronous Baud Rate Generator (BRG)”).
operation. 2. Clear the ANSEL bit for the RX pin (if applicable).
4. If interrupts are desired, set the RCIE bit of the 3. Enable the serial port by setting the SPEN bit.
PIE1 register and the GIE and PEIE bits of the The SYNC bit must be clear for asynchronous
INTCON register. operation.
5. If 9-bit reception is desired, set the RX9 bit. 4. If interrupts are desired, set the RCIE bit of the
6. Enable reception by setting the CREN bit. PIE1 register and the GIE and PEIE bits of the
7. The RCIF interrupt flag bit will be set when a INTCON register.
character is transferred from the RSR to the 5. Enable 9-bit reception by setting the RX9 bit.
receive buffer. An interrupt will be generated if 6. Enable address detection by setting the ADDEN
the RCIE interrupt enable bit was also set. bit.
8. Read the RCSTA register to get the error flags 7. Enable reception by setting the CREN bit.
and, if 9-bit data reception is enabled, the ninth 8. The RCIF interrupt flag bit will be set when a
data bit. character with the ninth bit set is transferred
9. Get the received eight Least Significant data bits from the RSR to the receive buffer. An interrupt
from the receive buffer by reading the RCREG will be generated if the RCIE interrupt enable bit
register. was also set.
10. If an overrun occurred, clear the OERR flag by 9. Read the RCSTA register to get the error flags.
clearing the CREN receiver enable bit. The ninth data bit will always be set.
10. Get the received eight Least Significant data bits
from the receive buffer by reading the RCREG
register. Software determines if this is the
device’s address.
11. If an overrun occurred, clear the OERR flag by
clearing the CREN receiver enable bit.
12. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and generate interrupts.

FIGURE 29-5: ASYNCHRONOUS RECEPTION

Start Start Start
RX/DT pin bit bit 0 bit 1 bit 7/8 Stop bit bit 0 bit 7/8 Stop bit bit 7/8 Stop
bit bit bit
Rcv Shift
Reg
Rcv Buffer Reg.
Word 1 Word 2
RCREG RCREG
RCIDL

Read Rcv
Buffer Reg.
RCREG

RCIF
(Interrupt Flag)

OERR bit
CREN

Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.

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TABLE 29-2: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page

ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 122

ANSELB(1) — — ANSB5 ANSB4 — — — — 128
ANSELC ANSC7(1) ANSC6(1) ANSC5(2) ANSC4(2) ANSC3 ANSC2 ANSC1 ANSC0 133
BAUD1CON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 336
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 85
PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 86
PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 89
RC1REG EUSART Receive Data Register 329*
RC1STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 335
RxyPPS — — — RxyPPS<4:0> 140
SP1BRGL BRG<7:0> 337
SP1BRGH BRG<15:8> 337
TRISA — — TRISA5 TRISA4 —(3) TRISA2 TRISA1 TRISA0 121
TRISB(1) TRISB7 TRISB6 TRISB5 TRISB4 — — — — 127
(1) (1)
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISA0 132
TX1STA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 334
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for asynchronous reception.
* Page provides register information.
Note 1: PIC16(L)F1708 only.
2: PIC16(L)F1704 only.
3: Unimplemented, read as ‘1’.

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29.2 Clock Accuracy with
Asynchronous Operation
The factory calibrates the internal oscillator block
output (INTOSC). However, the INTOSC frequency
may drift as VDD or temperature changes, and this
directly affects the asynchronous baud rate. Two
methods may be used to adjust the baud rate clock, but
both require a reference clock source of some kind.
The first (preferred) method uses the OSCTUNE
register to adjust the INTOSC output. Adjusting the
value in the OSCTUNE register allows for fine resolution
changes to the system clock source. See
Section 6.2.2.3 “Internal Oscillator Frequency
Adjustment” for more information.
The other method adjusts the value in the Baud Rate
Generator. This can be done automatically with the
Auto-Baud Detect feature (see Section 29.4.1
“Auto-Baud Detect”). There may not be fine enough
resolution when adjusting the Baud Rate Generator to
compensate for a gradual change in the peripheral
clock frequency.

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29.3 Register Definitions: EUSART Control
REGISTER 29-1: TX1STA: TRANSMIT STATUS AND CONTROL REGISTER
R/W-/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-1/1 R/W-0/0
(1)
CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 CSRC: Clock Source Select bit

Asynchronous mode:
Don’t care
Synchronous mode:
1 = Master mode (clock generated internally from BRG)
0 = Slave mode (clock from external source)
bit 6 TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5 TXEN: Transmit Enable bit(1)
1 = Transmit enabled
0 = Transmit disabled
bit 4 SYNC: EUSART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 3 SENDB: Send Break Character bit
Asynchronous mode:
1 = Send Sync Break on next transmission (cleared by hardware upon completion)
0 = Sync Break transmission completed
Synchronous mode:
Don’t care
bit 2 BRGH: High Baud Rate Select bit
Asynchronous mode:
1 = High speed
0 = Low speed
Synchronous mode:
Unused in this mode
bit 1 TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
bit 0 TX9D: Ninth bit of Transmit Data
Can be address/data bit or a parity bit.

Note 1: SREN/CREN overrides TXEN in Sync mode.

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REGISTER 29-2: RC1STA: RECEIVE STATUS AND CONTROL REGISTER

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0 R-0/0 R-0/0
SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 SPEN: Serial Port Enable bit

1 = Serial port enabled
0 = Serial port disabled (held in Reset)
bit 6 RX9: 9-Bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5 SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care
Synchronous mode – Master:
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode – Slave
Don’t care
bit 4 CREN: Continuous Receive Enable bit
Asynchronous mode:
1 = Enables receiver
0 = Disables receiver
Synchronous mode:
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3 ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1 = Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set
0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit
Asynchronous mode 8-bit (RX9 = 0):
Don’t care
bit 2 FERR: Framing Error bit
1 = Framing error (can be updated by reading RCREG register and receive next valid byte)
0 = No framing error
bit 1 OERR: Overrun Error bit
1 = Overrun error (can be cleared by clearing bit CREN)
0 = No overrun error
bit 0 RX9D: Ninth bit of Received Data
This can be address/data bit or a parity bit and must be calculated by user firmware.

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REGISTER 29-3: BAUD1CON: BAUD RATE CONTROL REGISTER

R-0/0 R-1/1 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0
ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 ABDOVF: Auto-Baud Detect Overflow bit

Asynchronous mode:
1 = Auto-baud timer overflowed
0 = Auto-baud timer did not overflow
Synchronous mode:
Don’t care
bit 6 RCIDL: Receive Idle Flag bit
Asynchronous mode:
1 = Receiver is Idle
0 = Start bit has been received and the receiver is receiving
Synchronous mode:
Don’t care
bit 5 Unimplemented: Read as ‘0’
bit 4 SCKP: Synchronous Clock Polarity Select bit
Asynchronous mode:
1 = Transmit inverted data to the TX/CK pin
0 = Transmit non-inverted data to the TX/CK pin
Synchronous mode:
1 = Data is clocked on rising edge of the clock
0 = Data is clocked on falling edge of the clock
bit 3 BRG16: 16-bit Baud Rate Generator bit
1 = 16-bit Baud Rate Generator is used
0 = 8-bit Baud Rate Generator is used
bit 2 Unimplemented: Read as ‘0’
bit 1 WUE: Wake-up Enable bit
Asynchronous mode:
1 = Receiver is waiting for a falling edge. No character will be received, byte RCIF will be set. WUE
will automatically clear after RCIF is set.
0 = Receiver is operating normally
Synchronous mode:
Don’t care
bit 0 ABDEN: Auto-Baud Detect Enable bit
Asynchronous mode:
1 = Auto-Baud Detect mode is enabled (clears when auto-baud is complete)
0 = Auto-Baud Detect mode is disabled
Synchronous mode:
Don’t care

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29.4 EUSART Baud Rate Generator EXAMPLE 29-1: CALCULATING BAUD
(BRG) RATE ERROR
The Baud Rate Generator (BRG) is an 8-bit or 16-bit For a device with FOSC of 16 MHz, desired baud rate
timer that is dedicated to the support of both the of 9600, Asynchronous mode, 8-bit BRG:
asynchronous and synchronous EUSART operation. F OS C
Desired Baud Rate = ------------------------------------------------------------------------
By default, the BRG operates in 8-bit mode. Setting the 64  [SPBRGH:SPBRGL] + 1 
BRG16 bit of the BAUDCON register selects 16-bit Solving for SPBRGH:SPBRGL:
mode.
FOSC
The SPBRGH, SPBRGL register pair determines the ---------------------------------------------
Desired Baud Rate
period of the free running baud rate timer. In X = --------------------------------------------- – 1
64
Asynchronous mode the multiplier of the baud rate
16000000
period is determined by both the BRGH bit of the TXSTA ------------------------
9600
register and the BRG16 bit of the BAUDCON register. In = ------------------------ – 1
64
Synchronous mode, the BRGH bit is ignored.
=  25.042  = 25
Table 29-3 contains the formulas for determining the
baud rate. Example 29-1 provides a sample calculation 16000000
Calculated Baud Rate = ---------------------------
for determining the baud rate and baud rate error. 64  25 + 1 

Typical baud rates and error values for various = 9615

asynchronous modes have been computed for your
convenience and are shown in Table 29-5. It may be Calc. Baud Rate – Desired Baud Rate
Error = --------------------------------------------------------------------------------------------
advantageous to use the high baud rate (BRGH = 1), Desired Baud Rate
or the 16-bit BRG (BRG16 = 1) to reduce the baud rate
 9615 – 9600 
error. The 16-bit BRG mode is used to achieve slow = ---------------------------------- = 0.16%
9600
baud rates for fast oscillator frequencies.
Writing a new value to the SPBRGH, SPBRGL register
pair causes the BRG timer to be reset (or cleared). This
ensures that the BRG does not wait for a timer overflow
before outputting the new baud rate.
If the system clock is changed during an active receive
operation, a receive error or data loss may result. To
avoid this problem, check the status of the RCIDL bit to
make sure that the receive operation is idle before
changing the system clock.

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TABLE 29-3: BAUD RATE FORMULAS
Configuration Bits
BRG/EUSART Mode Baud Rate Formula
SYNC BRG16 BRGH

0 0 0 8-bit/Asynchronous FOSC/[64 (n+1)]

0 0 1 8-bit/Asynchronous
FOSC/[16 (n+1)]
0 1 0 16-bit/Asynchronous
0 1 1 16-bit/Asynchronous
1 0 x 8-bit/Synchronous FOSC/[4 (n+1)]
1 1 x 16-bit/Synchronous
Legend: x = Don’t care, n = value of SPBRGH, SPBRGL register pair.

TABLE 29-4: SUMMARY OF REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
BAUD1CON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 336
RC1STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 335
SP1BRGL BRG<7:0> 337
SP1BRGH BRG<15:8> 337
TX1STA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 334
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for the Baud Rate Generator.
* Page provides register information.

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TABLE 29-5: BAUD RATES FOR ASYNCHRONOUS MODES

SYNC = 0, BRGH = 0, BRG16 = 0
FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz
BAUD
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 — — — — — — — — — — — —
1200 — — — 1221 1.73 255 1200 0.00 239 1200 0.00 143
2400 2404 0.16 207 2404 0.16 129 2400 0.00 119 2400 0.00 71
9600 9615 0.16 51 9470 -1.36 32 9600 0.00 29 9600 0.00 17
10417 10417 0.00 47 10417 0.00 29 10286 -1.26 27 10165 -2.42 16
19.2k 19.23k 0.16 25 19.53k 1.73 15 19.20k 0.00 14 19.20k 0.00 8
57.6k 55.55k -3.55 3 — — — 57.60k 0.00 7 57.60k 0.00 2
115.2k — — — — — — — — — — — —

SYNC = 0, BRGH = 0, BRG16 = 0

FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
BAUD
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 — — — 300 0.16 207 300 0.00 191 300 0.16 51
1200 1202 0.16 103 1202 0.16 51 1200 0.00 47 1202 0.16 12
2400 2404 0.16 51 2404 0.16 25 2400 0.00 23 — — —
9600 9615 0.16 12 — — — 9600 0.00 5 — — —
10417 10417 0.00 11 10417 0.00 5 — — — — — —
19.2k — — — — — — 19.20k 0.00 2 — — —
57.6k — — — — — — 57.60k 0.00 0 — — —
115.2k — — — — — — — — — — — —

SYNC = 0, BRGH = 1, BRG16 = 0

BAUD FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 — — — — — — — — — — — —
1200 — — — — — — — — — — — —
2400 — — — — — — — — — — — —
9600 9615 0.16 207 9615 0.16 129 9600 0.00 119 9600 0.00 71
10417 10417 0.00 191 10417 0.00 119 10378 -0.37 110 10473 0.53 65
19.2k 19.23k 0.16 103 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35
57.6k 57.14k -0.79 34 56.82k -1.36 21 57.60k 0.00 19 57.60k 0.00 11
115.2k 117.64k 2.12 16 113.64k -1.36 10 115.2k 0.00 9 115.2k 0.00 5

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TABLE 29-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 1, BRG16 = 0

BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 — — — — — — — — — 300 0.16 207
1200 — — — 1202 0.16 207 1200 0.00 191 1202 0.16 51
2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25
9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — —
10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5
19.2k 19231 0.16 25 19.23k 0.16 12 19.2k 0.00 11 — — —
57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — —
115.2k — — — — — — 115.2k 0.00 1 — — —

SYNC = 0, BRGH = 0, BRG16 = 1

BAUD FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 300.0 0.00 6666 300.0 -0.01 4166 300.0 0.00 3839 300.0 0.00 2303
1200 1200 -0.02 3332 1200 -0.03 1041 1200 0.00 959 1200 0.00 575
2400 2401 -0.04 832 2399 -0.03 520 2400 0.00 479 2400 0.00 287
9600 9615 0.16 207 9615 0.16 129 9600 0.00 119 9600 0.00 71
10417 10417 0.00 191 10417 0.00 119 10378 -0.37 110 10473 0.53 65
19.2k 19.23k 0.16 103 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35
57.6k 57.14k -0.79 34 56.818 -1.36 21 57.60k 0.00 19 57.60k 0.00 11
115.2k 117.6k 2.12 16 113.636 -1.36 10 115.2k 0.00 9 115.2k 0.00 5

SYNC = 0, BRGH = 0, BRG16 = 1

BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 299.9 -0.02 1666 300.1 0.04 832 300.0 0.00 767 300.5 0.16 207
1200 1199 -0.08 416 1202 0.16 207 1200 0.00 191 1202 0.16 51
2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25
9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — —
10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5
19.2k 19.23k 0.16 25 19.23k 0.16 12 19.20k 0.00 11 — — —
57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — —
115.2k — — — — — — 115.2k 0.00 1 — — —

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TABLE 29-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1

BAUD FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 300.0 0.00 26666 300.0 0.00 16665 300.0 0.00 15359 300.0 0.00 9215
1200 1200 0.00 6666 1200 -0.01 4166 1200 0.00 3839 1200 0.00 2303
2400 2400 0.01 3332 2400 0.02 2082 2400 0.00 1919 2400 0.00 1151
9600 9604 0.04 832 9597 -0.03 520 9600 0.00 479 9600 0.00 287
10417 10417 0.00 767 10417 0.00 479 10425 0.08 441 10433 0.16 264
19.2k 19.18k -0.08 416 19.23k 0.16 259 19.20k 0.00 239 19.20k 0.00 143
57.6k 57.55k -0.08 138 57.47k -0.22 86 57.60k 0.00 79 57.60k 0.00 47
115.2k 115.9k 0.64 68 116.3k 0.94 42 115.2k 0.00 39 115.2k 0.00 23

SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1

BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 300.0 0.00 6666 300.0 0.01 3332 300.0 0.00 3071 300.1 0.04 832
1200 1200 -0.02 1666 1200 0.04 832 1200 0.00 767 1202 0.16 207
2400 2401 0.04 832 2398 0.08 416 2400 0.00 383 2404 0.16 103
9600 9615 0.16 207 9615 0.16 103 9600 0.00 95 9615 0.16 25
10417 10417 0 191 10417 0.00 95 10473 0.53 87 10417 0.00 23
19.2k 19.23k 0.16 103 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 12
57.6k 57.14k -0.79 34 58.82k 2.12 16 57.60k 0.00 15 — — —
115.2k 117.6k 2.12 16 111.1k -3.55 8 115.2k 0.00 7 — — —

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PIC16(L)F1704/8
29.4.1 AUTO-BAUD DETECT and SPBRGL registers are clocked at 1/8th the BRG
base clock rate. The resulting byte measurement is the
The EUSART module supports automatic detection
average bit time when clocked at full speed.
and calibration of the baud rate.
Note 1: If the WUE bit is set with the ABDEN bit,
In the Auto-Baud Detect (ABD) mode, the clock to the
auto-baud detection will occur on the byte
BRG is reversed. Rather than the BRG clocking the
following the Break character (see
incoming RX signal, the RX signal is timing the BRG.
Section 29.4.3 “Auto-Wake-up on
The Baud Rate Generator is used to time the period of
Break”).
a received 55h (ASCII “U”) which is the Sync character
for the LIN bus. The unique feature of this character is 2: It is up to the user to determine that the
that it has five rising edges including the Stop bit edge. incoming character baud rate is within the
range of the selected BRG clock source.
Setting the ABDEN bit of the BAUDCON register starts
Some combinations of oscillator frequency
the auto-baud calibration sequence. While the ABD
and EUSART baud rates are not possible.
sequence takes place, the EUSART state machine is
held in Idle. On the first rising edge of the receive line, 3: During the auto-baud process, the
after the Start bit, the SPBRG begins counting up using auto-baud counter starts counting at one.
the BRG counter clock as shown in Figure 29-6. The Upon completion of the auto-baud
fifth rising edge will occur on the RX pin at the end of sequence, to achieve maximum accuracy,
the eighth bit period. At that time, an accumulated subtract 1 from the SPBRGH:SPBRGL
value totaling the proper BRG period is left in the register pair.
SPBRGH, SPBRGL register pair, the ABDEN bit is
automatically cleared and the RCIF interrupt flag is set. TABLE 29-6: BRG COUNTER CLOCK RATES
The value in the RCREG needs to be read to clear the
BRG Base BRG ABD
RCIF interrupt. RCREG content should be discarded. BRG16 BRGH
Clock Clock
When calibrating for modes that do not use the
SPBRGH register the user can verify that the SPBRGL 0 0 FOSC/64 FOSC/512
register did not overflow by checking for 00h in the
SPBRGH register. 0 1 FOSC/16 FOSC/128

The BRG auto-baud clock is determined by the BRG16 1 0 FOSC/16 FOSC/128

and BRGH bits as shown in Table 29-6. During ABD, 1 1 FOSC/4 FOSC/32
both the SPBRGH and SPBRGL registers are used as Note: During the ABD sequence, SPBRGL and
a 16-bit counter, independent of the BRG16 bit setting. SPBRGH registers are both used as a 16-bit
While calibrating the baud rate period, the SPBRGH counter, independent of the BRG16 setting.

FIGURE 29-6: AUTOMATIC BAUD RATE CALIBRATION

BRG Value XXXXh 0000h 001Ch

Edge #1 Edge #2 Edge #3 Edge #4 Edge #5

RX pin Start bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Stop bit

BRG Clock

Set by User Auto Cleared

ABDEN bit

RCIDL

RCIF bit
(Interrupt)

Read
RCREG

SPBRGL XXh 1Ch

SPBRGH XXh 00h

Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode.

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29.4.2 AUTO-BAUD OVERFLOW 29.4.3.1 Special Considerations
During the course of automatic baud detection, the Break Character
ABDOVF bit of the BAUDxCON register will be set if To avoid character errors or character fragments during
the baud rate counter overflows before the fifth rising a wake-up event, the wake-up character must be all
edge is detected on the RX pin. The ABDOVF bit zeros.
indicates that the counter has exceeded the maximum
count that can fit in the 16 bits of the When the wake-up is enabled the function works
SPxBRGH:SPxBRGL register pair. The overflow independent of the low time on the data stream. If the
condition will set the RCIF flag. The counter continues WUE bit is set and a valid non-zero character is
to count until the fifth rising edge is detected on the RX received, the low time from the Start bit to the first rising
pin. The RCIDL bit will remain false (‘0’) until the fifth edge will be interpreted as the wake-up event. The
rising edge at which time the RCIDL bit will be set. If the remaining bits in the character will be received as a
RCREG is read after the overflow occurs but before the fragmented character and subsequent characters can
fifth rising edge, then the fifth rising edge will set the result in framing or overrun errors.
RCIF again. Therefore, the initial character in the transmission must
Terminating the auto-baud process early to clear an be all ‘0’s. This must be ten or more bit times, 13-bit
Overflow condition will prevent proper detection of the times recommended for LIN bus, or any number of bit
sync character fifth rising edge. If any falling edges of times for standard RS-232 devices.
the sync character have not yet occurred when the Oscillator Start-up Time
ABDEN bit is cleared, then those will be falsely
Oscillator start-up time must be considered, especially
detected as Start bits. The following steps are recom-
in applications using oscillators with longer start-up
mended to clear the Overflow condition:
intervals (i.e., LP, XT or HS/PLL mode). The Sync
1. Read RCREG to clear RCIF. Break (or wake-up signal) character must be of
2. If RCIDL is zero, then wait for RCIF and repeat sufficient length, and be followed by a sufficient
step 1. interval, to allow enough time for the selected oscillator
3. Clear the ABDOVF bit. to start and provide proper initialization of the EUSART.
WUE Bit
29.4.3 AUTO-WAKE-UP ON BREAK
The wake-up event causes a receive interrupt by
During Sleep mode, all clocks to the EUSART are setting the RCIF bit. The WUE bit is cleared in
suspended. Because of this, the Baud Rate Generator hardware by a rising edge on RX/DT. The interrupt
is inactive and a proper character reception cannot be condition is then cleared in software by reading the
performed. The Auto-Wake-up feature allows the RCREG register and discarding its contents.
controller to wake-up due to activity on the RX/DT line.
To ensure that no actual data is lost, check the RCIDL
This feature is available only in Asynchronous mode.
bit to verify that a receive operation is not in process
The Auto-Wake-up feature is enabled by setting the before setting the WUE bit. If a receive operation is not
WUE bit of the BAUDCON register. Once set, the normal occurring, the WUE bit may then be set just prior to
receive sequence on RX/DT is disabled, and the entering the Sleep mode.
EUSART remains in an Idle state, monitoring for a
wake-up event independent of the CPU mode. A
wake-up event consists of a high-to-low transition on the
RX/DT line. (This coincides with the start of a Sync Break
or a wake-up signal character for the LIN protocol.)
The EUSART module generates an RCIF interrupt
coincident with the wake-up event. The interrupt is
generated synchronously to the Q clocks in normal CPU
operating modes (Figure 29-7), and asynchronously if
the device is in Sleep mode (Figure 29-8). The interrupt
condition is cleared by reading the RCREG register.
The WUE bit is automatically cleared by the low-to-high
transition on the RX line at the end of the Break. This
signals to the user that the Break event is over. At this
point, the EUSART module is in Idle mode waiting to
receive the next character.

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FIGURE 29-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Bit set by user Auto Cleared
WUE bit
RX/DT Line

RCIF
Cleared due to User Read of RCREG

Note 1: The EUSART remains in Idle while the WUE bit is set.

FIGURE 29-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP

Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4

OSC1
Bit Set by User Auto Cleared
WUE bit
RX/DT Line Note 1
RCIF
Cleared due to User Read of RCREG
Sleep Command Executed Sleep Ends

Note 1: If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is
still active. This sequence should not depend on the presence of Q clocks.
2: The EUSART remains in Idle while the WUE bit is set.

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29.4.4 BREAK CHARACTER SEQUENCE 29.4.5 RECEIVING A BREAK CHARACTER
The EUSART module has the capability of sending the The Enhanced EUSART module can receive a Break
special Break character sequences that are required by character in two ways.
the LIN bus standard. A Break character consists of a The first method to detect a Break character uses the
Start bit, followed by 12 ‘0’ bits and a Stop bit. FERR bit of the RCSTA register and the received data
To send a Break character, set the SENDB and TXEN as indicated by RCREG. The Baud Rate Generator is
bits of the TXSTA register. The Break character trans- assumed to have been initialized to the expected baud
mission is then initiated by a write to the TXREG. The rate.
value of data written to TXREG will be ignored and all A Break character has been received when;
‘0’s will be transmitted.
• RCIF bit is set
The SENDB bit is automatically reset by hardware after
• FERR bit is set
the corresponding Stop bit is sent. This allows the user
to preload the transmit FIFO with the next transmit byte • RCREG = 00h
following the Break character (typically, the Sync The second method uses the Auto-Wake-up feature
character in the LIN specification). described in Section 29.4.3 “Auto-Wake-up on
The TRMT bit of the TXSTA register indicates when the Break”. By enabling this feature, the EUSART will
transmit operation is active or idle, just as it does during sample the next two transitions on RX/DT, cause an
normal transmission. See Figure 29-9 for the timing of RCIF interrupt, and receive the next data byte followed
the Break character sequence. by another interrupt.
Note that following a Break character, the user will
29.4.4.1 Break and Sync Transmit Sequence typically want to enable the Auto-Baud Detect feature.
The following sequence will start a message frame For both methods, the user can set the ABDEN bit of
header made up of a Break, followed by an auto-baud the BAUDCON register before placing the EUSART in
Sync byte. This sequence is typical of a LIN bus Sleep mode.
master.
1. Configure the EUSART for the desired mode.
2. Set the TXEN and SENDB bits to enable the
Break sequence.
3. Load the TXREG with a dummy character to
initiate transmission (the value is ignored).
4. Write ‘55h’ to TXREG to load the Sync character
into the transmit FIFO buffer.
5. After the Break has been sent, the SENDB bit is
reset by hardware and the Sync character is
then transmitted.
When the TXREG becomes empty, as indicated by the
TXIF, the next data byte can be written to TXREG.

FIGURE 29-9: SEND BREAK CHARACTER SEQUENCE

Write to TXREG
Dummy Write

BRG Output
(Shift Clock)
TX (pin) Start bit bit 0 bit 1 bit 11 Stop bit
Break
TXIF bit
(Transmit
Interrupt Flag)
TRMT bit
(Transmit Shift
Empty Flag)
SENDB Sampled Here Auto Cleared
SENDB
(send Break
control bit)

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29.5 EUSART Synchronous Mode Clearing the SCKP bit sets the Idle state as low. When
the SCKP bit is cleared, the data changes on the rising
Synchronous serial communications are typically used edge of each clock.
in systems with a single master and one or more
slaves. The master device contains the necessary 29.5.1.3 Synchronous Master Transmission
circuitry for baud rate generation and supplies the clock
Data is transferred out of the device on the RX/DT pin.
for all devices in the system. Slave devices can take
The RX/DT and TX/CK pin output drivers are
advantage of the master clock by eliminating the
automatically enabled when the EUSART is configured
internal clock generation circuitry.
for synchronous master transmit operation.
There are two signal lines in Synchronous mode: a
A transmission is initiated by writing a character to the
bidirectional data line and a clock line. Slaves use the
TXREG register. If the TSR still contains all or part of a
external clock supplied by the master to shift the serial
previous character the new character data is held in the
data into and out of their respective receive and
TXREG until the last bit of the previous character has
transmit shift registers. Since the data line is
been transmitted. If this is the first character, or the
bidirectional, synchronous operation is half-duplex
previous character has been completely flushed from
only. Half-duplex refers to the fact that master and
the TSR, the data in the TXREG is immediately
slave devices can receive and transmit data but not
transferred to the TSR. The transmission of the
both simultaneously. The EUSART can operate as
character commences immediately following the
either a master or slave device.
transfer of the data to the TSR from the TXREG.
Start and Stop bits are not used in synchronous
Each data bit changes on the leading edge of the
transmissions.
master clock and remains valid until the subsequent
leading clock edge.
29.5.1 SYNCHRONOUS MASTER MODE
The following bits are used to configure the EUSART Note: The TSR register is not mapped in data
for synchronous master operation: memory, so it is not available to the user.

• SYNC = 1 29.5.1.4 Synchronous Master Transmission

• CSRC = 1 Set-up:
• SREN = 0 (for transmit); SREN = 1 (for receive)
1. Initialize the SPBRGH, SPBRGL register pair
• CREN = 0 (for transmit); CREN = 1 (for receive) and the BRGH and BRG16 bits to achieve the
• SPEN = 1 desired baud rate (see Section 29.4 “EUSART
Setting the SYNC bit of the TXSTA register configures Baud Rate Generator (BRG)”).
the device for synchronous operation. Setting the CSRC 2. Enable the synchronous master serial port by
bit of the TXSTA register configures the device as a setting bits SYNC, SPEN and CSRC.
master. Clearing the SREN and CREN bits of the RCSTA 3. Disable Receive mode by clearing bits SREN
register ensures that the device is in the Transmit mode, and CREN.
otherwise the device will be configured to receive. Setting 4. Enable Transmit mode by setting the TXEN bit.
the SPEN bit of the RCSTA register enables the
5. If 9-bit transmission is desired, set the TX9 bit.
EUSART.
6. If interrupts are desired, set the TXIE bit of the
29.5.1.1 Master Clock PIE1 register and the GIE and PEIE bits of the
INTCON register.
Synchronous data transfers use a separate clock line,
which is synchronous with the data. A device config- 7. If 9-bit transmission is selected, the ninth bit
ured as a master transmits the clock on the TX/CK line. should be loaded in the TX9D bit.
The TX/CK pin output driver is automatically enabled 8. Start transmission by loading data to the TXREG
when the EUSART is configured for synchronous register.
transmit or receive operation. Serial data bits change
on the leading edge to ensure they are valid at the
trailing edge of each clock. One clock cycle is gener-
ated for each data bit. Only as many clock cycles are
generated as there are data bits.

29.5.1.2 Clock Polarity

A clock polarity option is provided for Microwire
compatibility. Clock polarity is selected with the SCKP
bit of the BAUDCON register. Setting the SCKP bit sets
the clock Idle state as high. When the SCKP bit is set,
the data changes on the falling edge of each clock.

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 PIC16(L)F1704/8
FIGURE 29-10: SYNCHRONOUS TRANSMISSION
RX/DT
pin bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7
Word 1 Word 2
TX/CK pin
(SCKP = 0)

TX/CK pin
(SCKP = 1)
Write to
TXREG Reg Write Word 1 Write Word 2
TXIF bit
(Interrupt Flag)

TRMT bit

‘1’ ‘1’
TXEN bit

Note: Sync Master mode, SPBRGL = 0, continuous transmission of two 8-bit words.

FIGURE 29-11: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)

RX/DT pin bit 0 bit 1 bit 2 bit 6 bit 7

TX/CK pin

Write to
TXREG reg

TXIF bit

TRMT bit

TXEN bit

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PIC16(L)F1704/8
TABLE 29-7: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER
TRANSMISSION
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page

ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 122

ANSELB(1) — — ANSB5 ANSB4 — — — — 128
ANSELC ANSC7(1) ANSC6(1) ANSC5(2) ANSC4(2) ANSC3 ANSC2 ANSC1 ANSC0 133
BAUD1CON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 336
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 85
PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 86
PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 89
RC1STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 335
RxyPPS — — — RxyPPS<4:0> 140
SP1BRGL BRG<7:0> 337
SP1BRGH BRG<15:8> 337
TRISA — — TRISA5 TRISA4 —(3) TRISA2 TRISA1 TRISA0 121
TRISB(1) TRISB7 TRISB6 TRISB5 TRISB4 — — — — 127
TRISC TRISC7(1) TRISC6(1) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISA0 132
TX1REG EUSART Transmit Data Register 326*
TX1STA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 334
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous master transmission.
* Page provides register information.
Note 1: PIC16(L)F1708 only.
2: PIC16(L)F1704 only.
3: Unimplemented, read as ‘1’.

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 PIC16(L)F1704/8
29.5.1.5 Synchronous Master Reception will be received until the error is cleared. The OERR bit
can only be cleared by clearing the overrun condition.
Data is received at the RX/DT pin. The RX/DT pin
If the overrun error occurred when the SREN bit is set
output driver is automatically disabled when the
and CREN is clear then the error is cleared by reading
EUSART is configured for synchronous master receive
RCREG. If the overrun occurred when the CREN bit is
operation.
set then the error condition is cleared by either clearing
In Synchronous mode, reception is enabled by setting the CREN bit of the RCSTA register or by clearing the
either the Single Receive Enable bit (SREN of the SPEN bit which resets the EUSART.
RCSTA register) or the Continuous Receive Enable bit
(CREN of the RCSTA register). 29.5.1.8 Receiving 9-bit Characters
When SREN is set and CREN is clear, only as many The EUSART supports 9-bit character reception. When
clock cycles are generated as there are data bits in a the RX9 bit of the RCSTA register is set the EUSART
single character. The SREN bit is automatically cleared will shift nine bits into the RSR for each character
at the completion of one character. When CREN is set, received. The RX9D bit of the RCSTA register is the
clocks are continuously generated until CREN is ninth, and Most Significant, data bit of the top unread
cleared. If CREN is cleared in the middle of a character character in the receive FIFO. When reading 9-bit data
the CK clock stops immediately and the partial from the receive FIFO buffer, the RX9D data bit must
character is discarded. If SREN and CREN are both be read before reading the eight Least Significant bits
set, then SREN is cleared at the completion of the first from the RCREG.
character and CREN takes precedence.
To initiate reception, set either SREN or CREN. Data is 29.5.1.9 Synchronous Master Reception
sampled at the RX/DT pin on the trailing edge of the Set-up:
TX/CK clock pin and is shifted into the Receive Shift 1. Initialize the SPBRGH, SPBRGL register pair for
Register (RSR). When a complete character is the appropriate baud rate. Set or clear the
received into the RSR, the RCIF bit is set and the BRGH and BRG16 bits, as required, to achieve
character is automatically transferred to the two the desired baud rate.
character receive FIFO. The Least Significant eight bits 2. Clear the ANSEL bit for the RX pin (if applicable).
of the top character in the receive FIFO are available in
3. Enable the synchronous master serial port by
RCREG. The RCIF bit remains set as long as there are
setting bits SYNC, SPEN and CSRC.
unread characters in the receive FIFO.
4. Ensure bits CREN and SREN are clear.
Note: If the RX/DT function is on an analog pin, 5. If interrupts are desired, set the RCIE bit of the
the corresponding ANSEL bit must be PIE1 register and the GIE and PEIE bits of the
cleared for the receiver to function. INTCON register.
6. If 9-bit reception is desired, set bit RX9.
29.5.1.6 Slave Clock
7. Start reception by setting the SREN bit or for
Synchronous data transfers use a separate clock line, continuous reception, set the CREN bit.
which is synchronous with the data. A device configured 8. Interrupt flag bit RCIF will be set when reception
as a slave receives the clock on the TX/CK line. The of a character is complete. An interrupt will be
TX/CK pin output driver is automatically disabled when generated if the enable bit RCIE was set.
the device is configured for synchronous slave transmit
9. Read the RCSTA register to get the ninth bit (if
or receive operation. Serial data bits change on the
enabled) and determine if any error occurred
leading edge to ensure they are valid at the trailing edge
during reception.
of each clock. One data bit is transferred for each clock
cycle. Only as many clock cycles should be received as 10. Read the 8-bit received data by reading the
there are data bits. RCREG register.
11. If an overrun error occurs, clear the error by
Note: If the device is configured as a slave and either clearing the CREN bit of the RCSTA
the TX/CK function is on an analog pin, the register or by clearing the SPEN bit which resets
corresponding ANSEL bit must be cleared. the EUSART.

29.5.1.7 Receive Overrun Error

The receive FIFO buffer can hold two characters. An
overrun error will be generated if a third character, in its
entirety, is received before RCREG is read to access
the FIFO. When this happens the OERR bit of the
RCSTA register is set. Previous data in the FIFO will
not be overwritten. The two characters in the FIFO
buffer can be read, however, no additional characters

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PIC16(L)F1704/8
FIGURE 29-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)

RX/DT
pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7

TX/CK pin
(SCKP = 0)

TX/CK pin
(SCKP = 1)

Write to
bit SREN

SREN bit

CREN bit ‘0’ ‘0’

RCIF bit
(Interrupt)
Read
RCREG

Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.

TABLE 29-8: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER

RECEPTION
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page

ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 122

ANSELB(1) — — ANSB5 ANSB4 — — — — 128
ANSELC ANSC7(1) ANSC6(1) ANSC5(2) ANSC4(2) ANSC3 ANSC2 ANSC1 ANSC0 133
BAUD1CON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 336
CKPPS — — — CKPPS<4:0> 138, 139
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 85
PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 86
PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 89
RC1REG EUSART Receive Data Register 329*
RC1STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 335
RXPPS — — — RXPPS<4:0> 138, 139
RxyPPS — — — RxyPPS<4:0> 140
SP1BRGL BRG<7:0> 337*
SP1BRGH BRG<15:8> 337*
TRISA — — TRISA5 TRISA4 —(3) TRISA2 TRISA1 TRISA0 121
(1)
TRISB TRISB7 TRISB6 TRISB5 TRISB4 — — — — 127
TRISC TRISC7(1) TRISC6(1) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISA0 132
TX1STA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 334
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous master reception.
* Page provides register information.
Note 1: PIC16(L)F1708 only.
2: PIC16(L)F1704 only.
3: Unimplemented, read as ‘1’.

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 PIC16(L)F1704/8
29.5.2 SYNCHRONOUS SLAVE MODE If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
The following bits are used to configure the EUSART
for synchronous slave operation: 1. The first character will immediately transfer to
the TSR register and transmit.
• SYNC = 1
2. The second word will remain in the TXREG
• CSRC = 0
register.
• SREN = 0 (for transmit); SREN = 1 (for receive)
3. The TXIF bit will not be set.
• CREN = 0 (for transmit); CREN = 1 (for receive)
4. After the first character has been shifted out of
• SPEN = 1 TSR, the TXREG register will transfer the second
Setting the SYNC bit of the TXSTA register configures the character to the TSR and the TXIF bit will now be
device for synchronous operation. Clearing the CSRC bit set.
of the TXSTA register configures the device as a slave. 5. If the PEIE and TXIE bits are set, the interrupt
Clearing the SREN and CREN bits of the RCSTA register will wake the device from Sleep and execute the
ensures that the device is in the Transmit mode, next instruction. If the GIE bit is also set, the
otherwise the device will be configured to receive. Setting program will call the Interrupt Service Routine.
the SPEN bit of the RCSTA register enables the
EUSART. 29.5.2.2 Synchronous Slave Transmission
Set-up:
29.5.2.1 EUSART Synchronous Slave
1. Set the SYNC and SPEN bits and clear the
Transmit
CSRC bit.
The operation of the Synchronous Master and Slave 2. Clear the ANSEL bit for the CK pin (if applicable).
modes are identical (see Section 29.5.1.3
3. Clear the CREN and SREN bits.
“Synchronous Master Transmission”), except in the
case of the Sleep mode. 4. If interrupts are desired, set the TXIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
5. If 9-bit transmission is desired, set the TX9 bit.
6. Enable transmission by setting the TXEN bit.
7. If 9-bit transmission is selected, insert the Most
Significant bit into the TX9D bit.
8. Start transmission by writing the Least
Significant eight bits to the TXREG register.

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PIC16(L)F1704/8
TABLE 29-9: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE
TRANSMISSION
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page

ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 122

ANSELB(1) — — ANSB5 ANSB4 — — — — 128
ANSELC ANSC7(1) ANSC6(1) ANSC5(2) ANSC4(2) ANSC3 ANSC2 ANSC1 ANSC0 133
BAUD1CON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 336
CKPPS — — — CKPPS<4:0> 138, 139
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 85
PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 86
PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 89
RC1STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 335
RXPPS — — — RXPPS<4:0> 138, 139
RxyPPS — — — RxyPPS<4:0> 140
TRISA — — TRISA5 TRISA4 —(3) TRISA2 TRISA1 TRISA0 121
TRISB(1) TRISB7 TRISB6 TRISB5 TRISB4 — — — — 127
TRISC TRISC7(1) TRISC6(1) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISA0 132
TX1REG EUSART Transmit Data Register 326*
TX1STA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 334
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
* Page provides register information.
Note 1: PIC16(L)F1708 only.
2: PIC16(L)F1704 only.
3: Unimplemented, read as ‘1’.

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 PIC16(L)F1704/8
29.5.2.3 EUSART Synchronous Slave 29.5.2.4 Synchronous Slave Reception
Reception Set-up:
The operation of the Synchronous Master and Slave 1. Set the SYNC and SPEN bits and clear the
modes is identical (Section 29.5.1.5 “Synchronous CSRC bit.
Master Reception”), with the following exceptions: 2. Clear the ANSEL bit for both the CK and DT pins
• Sleep (if applicable).
• CREN bit is always set, therefore the receiver is 3. If interrupts are desired, set the RCIE bit of the
never idle PIE1 register and the GIE and PEIE bits of the
• SREN bit, which is a “don’t care” in Slave mode INTCON register.
4. If 9-bit reception is desired, set the RX9 bit.
A character may be received while in Sleep mode by
setting the CREN bit prior to entering Sleep. Once the 5. Set the CREN bit to enable reception.
word is received, the RSR register will transfer the data 6. The RCIF bit will be set when reception is
to the RCREG register. If the RCIE enable bit is set, the complete. An interrupt will be generated if the
interrupt generated will wake the device from Sleep RCIE bit was set.
and execute the next instruction. If the GIE bit is also 7. If 9-bit mode is enabled, retrieve the Most
set, the program will branch to the interrupt vector. Significant bit from the RX9D bit of the RCSTA
register.
8. Retrieve the eight Least Significant bits from the
receive FIFO by reading the RCREG register.
9. If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCSTA
register or by clearing the SPEN bit which resets
the EUSART.

TABLE 29-10: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE

RECEPTION
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page

ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 122

(1)
ANSELB — — ANSB5 ANSB4 — — — — 128
ANSELC ANSC7(1) ANSC6(1) ANSC5(2) ANSC4(2) ANSC3 ANSC2 ANSC1 ANSC0 133
BAUD1CON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 336
CKPPS — — — CKPPS<4:0> 138, 139
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 85
PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 86
PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 89
RC1REG EUSART Receive Data Register 329*
RC1STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 335
RXPPS — — — RXPPS<4:0> 138, 139
TRISA — — TRISA5 TRISA4 —(3) TRISA2 TRISA1 TRISA0 121
TRISB(1) TRISB7 TRISB6 TRISB5 TRISB4 — — — — 127
TRISC TRISC7(1) TRISC6(1) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISA0 132
TX1STA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 334
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous slave reception.
* Page provides register information.
Note 1: PIC16(L)F1708 only.
2: PIC16(L)F1704 only.
3: Unimplemented, read as ‘1’.

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PIC16(L)F1704/8
29.6 EUSART Operation During Sleep 29.6.2 SYNCHRONOUS TRANSMIT
DURING SLEEP
The EUSART will remain active during Sleep only in the
Synchronous Slave mode. All other modes require the To transmit during Sleep, all the following conditions
system clock and therefore cannot generate the must be met before entering Sleep mode:
necessary signals to run the Transmit or Receive Shift • The RCSTA and TXSTA Control registers must be
registers during Sleep. configured for synchronous slave transmission
Synchronous Slave mode uses an externally generated (see Section 29.5.2.2 “Synchronous Slave
clock to run the Transmit and Receive Shift registers. Transmission Set-up:”).
• The TXIF interrupt flag must be cleared by writing
29.6.1 SYNCHRONOUS RECEIVE DURING the output data to the TXREG, thereby filling the
SLEEP TSR and transmit buffer.
To receive during Sleep, all the following conditions • If interrupts are desired, set the TXIE bit of the
must be met before entering Sleep mode: PIE1 register and the PEIE bit of the INTCON
register.
• RCSTA and TXSTA Control registers must be
configured for Synchronous Slave Reception (see • Interrupt enable bits TXIE of the PIE1 register and
Section 29.5.2.4 “Synchronous Slave PEIE of the INTCON register must set.
Reception Set-up:”). Upon entering Sleep mode, the device will be ready to
• If interrupts are desired, set the RCIE bit of the accept clocks on TX/CK pin and transmit data on the
PIE1 register and the GIE and PEIE bits of the RX/DT pin. When the data word in the TSR has been
INTCON register. completely clocked out by the external device, the
• The RCIF interrupt flag must be cleared by pending byte in the TXREG will transfer to the TSR and
reading RCREG to unload any pending the TXIF flag will be set. Thereby, waking the processor
characters in the receive buffer. from Sleep. At this point, the TXREG is available to
accept another character for transmission, which will
Upon entering Sleep mode, the device will be ready to clear the TXIF flag.
accept data and clocks on the RX/DT and TX/CK pins,
respectively. When the data word has been completely Upon waking from Sleep, the instruction following the
clocked in by the external device, the RCIF interrupt SLEEP instruction will be executed. If the Global
flag bit of the PIR1 register will be set. Thereby, waking Interrupt Enable (GIE) bit is also set then the Interrupt
the processor from Sleep. Service Routine at address 0004h will be called.

Upon waking from Sleep, the instruction following the

SLEEP instruction will be executed. If the Global
Interrupt Enable (GIE) bit of the INTCON register is
also set, then the Interrupt Service Routine at address
004h will be called.

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 PIC16(L)F1704/8
30.0 IN-CIRCUIT SERIAL 30.3 Common Programming Interfaces
PROGRAMMING™ (ICSP™) Connection to a target device is typically done through
ICSP™ programming allows customers to manufacture an ICSP™ header. A commonly found connector on
circuit boards with unprogrammed devices. Programming development tools is the RJ-11 in the 6P6C (6-pin,
can be done after the assembly process, allowing the 6-connector) configuration. See Figure 30-1.
device to be programmed with the most recent firmware
or a custom firmware. Five pins are needed for ICSP™ FIGURE 30-1: ICD RJ-11 STYLE
programming: CONNECTOR INTERFACE
• ICSPCLK
• ICSPDAT
• MCLR/VPP
• VDD
ICSPDAT
• VSS
2 4 6 NC
VDD
In Program/Verify mode the program memory, user IDs ICSPCLK
and the Configuration Words are programmed through 1 3 5
Target
serial communications. The ICSPDAT pin is a VPP/MCLR PC Board
VSS
bidirectional I/O used for transferring the serial data Bottom Side
and the ICSPCLK pin is the clock input. For more
information on ICSP™ refer to the “PIC16(L)F170X
Memory Programming Specification” (DS41683). Pin Description*

1 = VPP/MCLR
30.1 High-Voltage Programming Entry 2 = VDD Target
Mode 3 = VSS (ground)

The device is placed into High-Voltage Programming 4 = ICSPDAT

Entry mode by holding the ICSPCLK and ICSPDAT 5 = ICSPCLK

pins low then raising the voltage on MCLR/VPP to VIHH. 6 = No Connect

30.2 Low-Voltage Programming Entry Another connector often found in use with the PICkit™
Mode programmers is a standard 6-pin header with 0.1 inch
spacing. Refer to Figure 30-2.
The Low-Voltage Programming Entry mode allows the
PIC® Flash MCUs to be programmed using VDD only, For additional interface recommendations, refer to your
without high voltage. When the LVP bit of Configuration specific device programmer manual prior to PCB
Words is set to ‘1’, the low-voltage ICSP programming design.
entry is enabled. To disable the Low-Voltage ICSP It is recommended that isolation devices be used to
mode, the LVP bit must be programmed to ‘0’. separate the programming pins from other circuitry.
Entry into the Low-Voltage Programming Entry mode The type of isolation is highly dependent on the specific
requires the following steps: application and may include devices such as resistors,
diodes, or even jumpers. See Figure 30-3 for more
1. MCLR is brought to VIL.
information.
2. A 32-bit key sequence is presented on
ICSPDAT, while clocking ICSPCLK.
Once the key sequence is complete, MCLR must be
held at VIL for as long as Program/Verify mode is to be
maintained.
If low-voltage programming is enabled (LVP = 1), the
MCLR Reset function is automatically enabled and
cannot be disabled. See Section 5.5 “MCLR” for more
information.
The LVP bit can only be reprogrammed to ‘0’ by using
the High-Voltage Programming mode.

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PIC16(L)F1704/8
FIGURE 30-2: PICkit™ PROGRAMMER STYLE CONNECTOR INTERFACE

Pin 1 Indicator

Pin Description*
1 1 = VPP/MCLR
2
2 = VDD Target
3
4 3 = VSS (ground)
5
6 4 = ICSPDAT
5 = ICSPCLK
6 = No Connect

* The 6-pin header (0.100" spacing) accepts 0.025" square pins.

FIGURE 30-3: TYPICAL CONNECTION FOR ICSP™ PROGRAMMING

External
Programming VDD Device to be
Signals Programmed

VDD VDD

VPP MCLR/VPP
VSS VSS

Data ICSPDAT
Clock ICSPCLK

* * *

To Normal Connections

* Isolation devices (as required).

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 PIC16(L)F1704/8
31.0 INSTRUCTION SET SUMMARY 31.1 Read-Modify-Write Operations
Each instruction is a 14-bit word containing the Any instruction that specifies a file register as part of
operation code (opcode) and all required operands. the instruction performs a Read-Modify-Write (R-M-W)
The opcodes are broken into three broad categories. operation. The register is read, the data is modified,
and the result is stored according to either the
• Byte Oriented
instruction, or the destination designator ‘d’. A read
• Bit Oriented operation is performed on a register even if the
• Literal and Control instruction writes to that register.
The literal and control category contains the most
varied instruction word format. TABLE 31-1: OPCODE FIELD
Table 31-3 lists the instructions recognized by the DESCRIPTIONS
MPASMTM assembler. Field Description
All instructions are executed within a single instruction f Register file address (0x00 to 0x7F)
cycle, with the following exceptions, which may take
W Working register (accumulator)
two or three cycles:
b Bit address within an 8-bit file register
• Subroutine takes two cycles (CALL, CALLW)
• Returns from interrupts or subroutines take two k Literal field, constant data or label
cycles (RETURN, RETLW, RETFIE) x Don’t care location (= 0 or 1).
• Program branching takes two cycles (GOTO, BRA, The assembler will generate code with x = 0.
BRW, BTFSS, BTFSC, DECFSZ, INCSFZ) It is the recommended form of use for
• One additional instruction cycle will be used when compatibility with all Microchip software tools.
any instruction references an indirect file register d Destination select; d = 0: store result in W,
and the file select register is pointing to program d = 1: store result in file register f.
memory. Default is d = 1.
One instruction cycle consists of 4 oscillator cycles; for n FSR or INDF number. (0-1)
an oscillator frequency of 4 MHz, this gives a nominal mm Pre-post increment-decrement mode
instruction execution rate of 1 MHz.
selection
All instruction examples use the format ‘0xhh’ to
represent a hexadecimal number, where ‘h’ signifies a TABLE 31-2: ABBREVIATION
hexadecimal digit.
DESCRIPTIONS
Field Description
PC Program Counter
TO Time-Out bit
C Carry bit
DC Digit Carry bit
Z Zero bit
PD Power-Down bit

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PIC16(L)F1704/8
FIGURE 31-1: GENERAL FORMAT FOR
INSTRUCTIONS
Byte-oriented file register operations
13 8 7 6 0
OPCODE d f (FILE #)
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
Bit-oriented file register operations
13 10 9 7 6 0
OPCODE b (BIT #) f (FILE #)

b = 3-bit bit address

f = 7-bit file register address

Literal and control operations

General
13 8 7 0
OPCODE k (literal)

k = 8-bit immediate value

CALL and GOTO instructions only

13 11 10 0
OPCODE k (literal)
k = 11-bit immediate value

MOVLP instruction only

13 7 6 0
OPCODE k (literal)
k = 7-bit immediate value

MOVLB instruction only

13 5 4 0
OPCODE k (literal)

k = 5-bit immediate value

BRA instruction only

13 9 8 0
OPCODE k (literal)

k = 9-bit immediate value

FSR Offset instructions

13 7 6 5 0
OPCODE n k (literal)
n = appropriate FSR
k = 6-bit immediate value

FSR Increment instructions

13 3 2 1 0
OPCODE n m (mode)
n = appropriate FSR
m = 2-bit mode value

OPCODE only
13 0
OPCODE

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 PIC16(L)F1704/8
TABLE 31-3: PIC16(L)F1704/8 INSTRUCTION SET
Mnemonic, 14-Bit Opcode Status
Description Cycles Notes
Operands MSb LSb Affected

BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWF f, d Add W and f 1 00 0111 dfff ffff C, DC, Z 2
ADDWFC f, d Add with Carry W and f 1 11 1101 dfff ffff C, DC, Z 2
ANDWF f, d AND W with f 1 00 0101 dfff ffff Z 2
ASRF f, d Arithmetic Right Shift 1 11 0111 dfff ffff C, Z 2
LSLF f, d Logical Left Shift 1 11 0101 dfff ffff C, Z 2
LSRF f, d Logical Right Shift 1 11 0110 dfff ffff C, Z 2
CLRF f Clear f 1 00 0001 lfff ffff Z 2
CLRW – Clear W 1 00 0001 0000 00xx Z
COMF f, d Complement f 1 00 1001 dfff ffff Z 2
DECF f, d Decrement f 1 00 0011 dfff ffff Z 2
INCF f, d Increment f 1 00 1010 dfff ffff Z 2
IORWF f, d Inclusive OR W with f 1 00 0100 dfff ffff Z 2
MOVF f, d Move f 1 00 1000 dfff ffff Z 2
MOVWF f Move W to f 1 00 0000 1fff ffff 2
RLF f, d Rotate Left f through Carry 1 00 1101 dfff ffff C 2
RRF f, d Rotate Right f through Carry 1 00 1100 dfff ffff C 2
SUBWF f, d Subtract W from f 1 00 0010 dfff ffff C, DC, Z 2
SUBWFB f, d Subtract with Borrow W from f 1 11 1011 dfff ffff C, DC, Z 2
SWAPF f, d Swap nibbles in f 1 00 1110 dfff ffff 2
XORWF f, d Exclusive OR W with f 1 00 0110 dfff ffff Z 2
BYTE ORIENTED SKIP OPERATIONS

DECFSZ f, d Decrement f, Skip if 0 1(2) 00 1011 dfff ffff 1, 2

INCFSZ f, d Increment f, Skip if 0 1(2) 00 1111 dfff ffff 1, 2

BIT-ORIENTED FILE REGISTER OPERATIONS

BCF f, b Bit Clear f 1 01 00bb bfff ffff 2

BSF f, b Bit Set f 1 01 01bb bfff ffff 2

BIT-ORIENTED SKIP OPERATIONS

BTFSC f, b Bit Test f, Skip if Clear 1 (2) 01 10bb bfff ffff 1, 2
BTFSS f, b Bit Test f, Skip if Set 1 (2) 01 11bb bfff ffff 1, 2
LITERAL OPERATIONS
ADDLW k Add literal and W 1 11 1110 kkkk kkkk C, DC, Z
ANDLW k AND literal with W 1 11 1001 kkkk kkkk Z
IORLW k Inclusive OR literal with W 1 11 1000 kkkk kkkk Z
MOVLB k Move literal to BSR 1 00 0000 001k kkkk
MOVLP k Move literal to PCLATH 1 11 0001 1kkk kkkk
MOVLW k Move literal to W 1 11 0000 kkkk kkkk
SUBLW k Subtract W from literal 1 11 1100 kkkk kkkk C, DC, Z
XORLW k Exclusive OR literal with W 1 11 1010 kkkk kkkk Z
Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require
one additional instruction cycle.

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PIC16(L)F1704/8
TABLE 31-3: PIC16(L)F1704/8 INSTRUCTION SET (CONTINUED)
Mnemonic, 14-Bit Opcode Status
Description Cycles Notes
Operands MSb LSb Affected

CONTROL OPERATIONS
BRA k Relative Branch 2 11 001k kkkk kkkk
BRW – Relative Branch with W 2 00 0000 0000 1011
CALL k Call Subroutine 2 10 0kkk kkkk kkkk
CALLW – Call Subroutine with W 2 00 0000 0000 1010
GOTO k Go to address 2 10 1kkk kkkk kkkk
RETFIE k Return from interrupt 2 00 0000 0000 1001
RETLW k Return with literal in W 2 11 0100 kkkk kkkk
RETURN – Return from Subroutine 2 00 0000 0000 1000
INHERENT OPERATIONS
CLRWDT – Clear Watchdog Timer 1 00 0000 0110 0100 TO, PD
NOP – No Operation 1 00 0000 0000 0000
OPTION – Load OPTION_REG register with W 1 00 0000 0110 0010
RESET – Software device Reset 1 00 0000 0000 0001
SLEEP – Go into Standby mode 1 00 0000 0110 0011 TO, PD
TRIS f Load TRIS register with W 1 00 0000 0110 0fff
C-COMPILER OPTIMIZED
ADDFSR n, k Add Literal k to FSRn 1 11 0001 0nkk kkkk
MOVIW n mm Move Indirect FSRn to W with pre/post inc/dec 1 00 0000 0001 0nmm Z 2, 3
modifier, mm
k[n] Move INDFn to W, Indexed Indirect. 1 11 1111 0nkk kkkk Z 2
MOVWI n mm Move W to Indirect FSRn with pre/post inc/dec 1 00 0000 0001 1nmm 2, 3
modifier, mm
k[n] Move W to INDFn, Indexed Indirect. 1 11 1111 1nkk kkkk 2
Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require
one additional instruction cycle.
3: See Table in the MOVIW and MOVWI instruction descriptions.

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 PIC16(L)F1704/8
31.2 Instruction Descriptions

ADDFSR Add Literal to FSRn ANDLW AND literal with W

Syntax: [ label ] ADDFSR FSRn, k Syntax: [ label ] ANDLW k
Operands: -32  k  31 Operands: 0  k  255
n  [ 0, 1] Operation: (W) .AND. (k)  (W)
Operation: FSR(n) + k  FSR(n)
Status Affected: Z
Status Affected: None Description: The contents of W register are
Description: The signed 6-bit literal ‘k’ is added to AND’ed with the 8-bit literal ‘k’. The
the contents of the FSRnH:FSRnL result is placed in the W register.
register pair.

FSRn is limited to the range

0000h-FFFFh. Moving beyond these
bounds will cause the FSR to
wrap-around.

ANDWF AND W with f

ADDLW Add literal and W
Syntax: [ label ] ANDWF f,d
Syntax: [ label ] ADDLW k Operands: 0  f  127
Operands: 0  k  255 d 0,1
Operation: (W) + k  (W) Operation: (W) .AND. (f)  (destination)
Status Affected: C, DC, Z Status Affected: Z
Description: The contents of the W register are Description: AND the W register with register ‘f’. If
added to the 8-bit literal ‘k’ and the ‘d’ is ‘0’, the result is stored in the W
result is placed in the W register. register. If ‘d’ is ‘1’, the result is stored
back in register ‘f’.

ASRF Arithmetic Right Shift

ADDWF Add W and f
Syntax: [ label ] ASRF f {,d}
Syntax: [ label ] ADDWF f,d Operands: 0  f  127
Operands: 0  f  127 d [0,1]
d 0,1 Operation: (f<7>) dest<7>
Operation: (W) + (f)  (destination) (f<7:1>)  dest<6:0>,
(f<0>)  C,
Status Affected: C, DC, Z
Status Affected: C, Z
Description: Add the contents of the W register
with register ‘f’. If ‘d’ is ‘0’, the result is Description: The contents of register ‘f’ are shifted
stored in the W register. If ‘d’ is ‘1’, the one bit to the right through the Carry
result is stored back in register ‘f’. flag. The MSb remains unchanged. If
‘d’ is ‘0’, the result is placed in W. If ‘d’
is ‘1’, the result is stored back in
register ‘f’.

register f C
ADDWFC ADD W and CARRY bit to f
Syntax: [ label ] ADDWFC f {,d}
Operands: 0  f  127
d [0,1]
Operation: (W) + (f) + (C)  dest
Status Affected: C, DC, Z
Description: Add W, the Carry flag and data mem-
ory location ‘f’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed in data memory location ‘f’.

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BCF Bit Clear f BTFSC Bit Test f, Skip if Clear

Syntax: [ label ] BCF f,b Syntax: [ label ] BTFSC f,b

Operands: 0  f  127 Operands: 0  f  127

0b7 0b7

Operation: 0  (f<b>) Operation: skip if (f<b>) = 0

Status Affected: None Status Affected: None

Description: Bit ‘b’ in register ‘f’ is cleared. Description: If bit ‘b’ in register ‘f’ is ‘1’, the next
instruction is executed.
If bit ‘b’, in register ‘f’, is ‘0’, the next
instruction is discarded, and a NOP is
executed instead, making this a
2-cycle instruction.

BRA Relative Branch BTFSS Bit Test f, Skip if Set

Syntax: [ label ] BRA label Syntax: [ label ] BTFSS f,b
[ label ] BRA $+k Operands: 0  f  127
Operands: -256  label - PC + 1  255 0b<7
-256  k  255 Operation: skip if (f<b>) = 1
Operation: (PC) + 1 + k  PC Status Affected: None
Status Affected: None Description: If bit ‘b’ in register ‘f’ is ‘0’, the next
Description: Add the signed 9-bit literal ‘k’ to the instruction is executed.
PC. Since the PC will have If bit ‘b’ is ‘1’, then the next instruction
incremented to fetch the next is discarded and a NOP is executed
instruction, the new address will be instead, making this a 2-cycle
PC + 1 + k. This instruction is a instruction.
2-cycle instruction. This branch has a
limited range.

BRW Relative Branch with W

Syntax: [ label ] BRW
Operands: None
Operation: (PC) + (W)  PC
Status Affected: None
Description: Add the contents of W (unsigned) to
the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 1 + (W). This instruction is a
2-cycle instruction.

BSF Bit Set f

Syntax: [ label ] BSF f,b
Operands: 0  f  127
0b7
Operation: 1  (f<b>)
Status Affected: None
Description: Bit ‘b’ in register ‘f’ is set.

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CALL Call Subroutine CLRWDT Clear Watchdog Timer

Syntax: [ label ] CALL k Syntax: [ label ] CLRWDT
Operands: 0  k  2047 Operands: None
Operation: (PC)+ 1 TOS, Operation: 00h  WDT
k  PC<10:0>, 0  WDT prescaler,
(PCLATH<6:3>)  PC<14:11> 1  TO
Status Affected: None 1  PD
Description: Call Subroutine. First, return address Status Affected: TO, PD
(PC + 1) is pushed onto the stack. Description: CLRWDT instruction resets the Watch-
The 11-bit immediate address is dog Timer. It also resets the prescaler
loaded into PC bits <10:0>. The upper of the WDT. Status bits TO and PD
bits of the PC are loaded from are set.
PCLATH. CALL is a 2-cycle
instruction.

CALLW Subroutine Call With W COMF Complement f

Syntax: [ label ] CALLW Syntax: [ label ] COMF f,d

Operands: None Operands: 0  f  127

d  [0,1]
Operation: (PC) +1  TOS,
(W)  PC<7:0>, Operation: (f)  (destination)
(PCLATH<6:0>) PC<14:8> Status Affected: Z
Description: The contents of register ‘f’ are
Status Affected: None complemented. If ‘d’ is ‘0’, the result is
Description: Subroutine call with W. First, the stored in W. If ‘d’ is ‘1’, the result is
return address (PC + 1) is pushed stored back in register ‘f’.
onto the return stack. Then, the
contents of W is loaded into PC<7:0>,
and the contents of PCLATH into
PC<14:8>. CALLW is a 2-cycle
instruction.

CLRF Clear f DECF Decrement f

Syntax: [ label ] CLRF f Syntax: [ label ] DECF f,d
Operands: 0  f  127 Operands: 0  f  127
d  [0,1]
Operation: 00h  (f)
1Z Operation: (f) - 1  (destination)
Status Affected: Z Status Affected: Z
Description: The contents of register ‘f’ are cleared Description: Decrement register ‘f’. If ‘d’ is ‘0’, the
and the Z bit is set. result is stored in the W register. If ‘d’
is ‘1’, the result is stored back in
register ‘f’.
CLRW Clear W
Syntax: [ label ] CLRW
Operands: None
Operation: 00h  (W)
1Z
Status Affected: Z
Description: W register is cleared. Zero bit (Z) is
set.

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DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0

Syntax: [ label ] DECFSZ f,d Syntax: [ label ] INCFSZ f,d
Operands: 0  f  127 Operands: 0  f  127
d  [0,1] d  [0,1]
Operation: (f) - 1  (destination); Operation: (f) + 1  (destination),
skip if result = 0 skip if result = 0
Status Affected: None Status Affected: None
Description: The contents of register ‘f’ are decre- Description: The contents of register ‘f’ are incre-
mented. If ‘d’ is ‘0’, the result is placed mented. If ‘d’ is ‘0’, the result is placed
in the W register. If ‘d’ is ‘1’, the result in the W register. If ‘d’ is ‘1’, the result
is placed back in register ‘f’. is placed back in register ‘f’.
If the result is ‘1’, the next instruction is If the result is ‘1’, the next instruction is
executed. If the result is ‘0’, then a executed. If the result is ‘0’, a NOP is
NOP is executed instead, making it a executed instead, making it a 2-cycle
2-cycle instruction. instruction.

GOTO Unconditional Branch IORLW Inclusive OR literal with W

Syntax: [ label ] GOTO k Syntax: [ label ] IORLW k
Operands: 0  k  2047 Operands: 0  k  255
Operation: k  PC<10:0> Operation: (W) .OR. k  (W)
PCLATH<6:3>  PC<14:11> Status Affected: Z
Status Affected: None Description: The contents of the W register are
Description: GOTO is an unconditional branch. The OR’ed with the 8-bit literal ‘k’. The
11-bit immediate value is loaded into result is placed in the W register.
PC bits <10:0>. The upper bits of PC
are loaded from PCLATH<4:3>. GOTO
is a 2-cycle instruction.

INCF Increment f IORWF Inclusive OR W with f

Syntax: [ label ] INCF f,d Syntax: [ label ] IORWF f,d
Operands: 0  f  127 Operands: 0  f  127
d  [0,1] d  [0,1]
Operation: (f) + 1  (destination) Operation: (W) .OR. (f)  (destination)
Status Affected: Z Status Affected: Z
Description: The contents of register ‘f’ are incre- Description: Inclusive OR the W register with regis-
mented. If ‘d’ is ‘0’, the result is placed ter ‘f’. If ‘d’ is ‘0’, the result is placed in
in the W register. If ‘d’ is ‘1’, the result the W register. If ‘d’ is ‘1’, the result is
is placed back in register ‘f’. placed back in register ‘f’.

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LSLF Logical Left Shift MOVF Move f

Syntax: [ label ] LSLF f {,d} Syntax: [ label ] MOVF f,d
Operands: 0  f  127 Operands: 0  f  127
d [0,1] d  [0,1]
Operation: (f<7>)  C Operation: (f)  (dest)
(f<6:0>)  dest<7:1>
Status Affected: Z
0  dest<0>
Description: The contents of register f is moved to
Status Affected: C, Z
a destination dependent upon the
Description: The contents of register ‘f’ are shifted status of d. If d = 0, destination is W
one bit to the left through the Carry flag. register. If d = 1, the destination is file
A ‘0’ is shifted into the LSb. If ‘d’ is ‘0’, register f itself. d = 1 is useful to test a
the result is placed in W. If ‘d’ is ‘1’, the file register since status flag Z is
result is stored back in register ‘f’. affected.

C register f 0 Words: 1
Cycles: 1
Example: MOVF FSR, 0
After Instruction
LSRF Logical Right Shift
W = value in FSR register
Syntax: [ label ] LSRF f {,d} Z = 1
Operands: 0  f  127
d [0,1]
Operation: 0  dest<7>
(f<7:1>)  dest<6:0>,
(f<0>)  C,
Status Affected: C, Z
Description: The contents of register ‘f’ are shifted
one bit to the right through the Carry
flag. A ‘0’ is shifted into the MSb. If ‘d’ is
‘0’, the result is placed in W. If ‘d’ is ‘1’,
the result is stored back in register ‘f’.

0 register f C

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MOVIW Move INDFn to W MOVLP Move literal to PCLATH

Syntax: [ label ] MOVIW ++FSRn Syntax: [ label ] MOVLP k
[ label ] MOVIW --FSRn Operands: 0  k  127
[ label ] MOVIW FSRn++
[ label ] MOVIW FSRn-- Operation: k  PCLATH
[ label ] MOVIW k[FSRn] Status Affected: None
Operands: n  [0,1] Description: The 7-bit literal ‘k’ is loaded into the
mm  [00,01, 10, 11] PCLATH register.
-32  k  31
Operation: INDFn  W
Effective address is determined by MOVLW Move literal to W
• FSR + 1 (preincrement)
Syntax: [ label ] MOVLW k
• FSR - 1 (predecrement)
• FSR + k (relative offset) Operands: 0  k  255
After the Move, the FSR value will be
Operation: k  (W)
either:
• FSR + 1 (all increments) Status Affected: None
• FSR - 1 (all decrements) Description: The 8-bit literal ‘k’ is loaded into W reg-
• Unchanged ister. The “don’t cares” will assemble as
Status Affected: Z ‘0’s.
Words: 1

Mode Syntax mm Cycles: 1

Preincrement ++FSRn 00 Example: MOVLW 0x5A

Predecrement --FSRn 01 After Instruction

W = 0x5A
Postincrement FSRn++ 10
Postdecrement FSRn-- 11
MOVWF Move W to f
Syntax: [ label ] MOVWF f
Description: This instruction is used to move data
between W and one of the indirect Operands: 0  f  127
registers (INDFn). Before/after this Operation: (W)  (f)
move, the pointer (FSRn) is updated by
pre/post incrementing/decrementing it. Status Affected: None
Description: Move data from W register to register
Note: The INDFn registers are not ‘f’.
physical registers. Any instruction that Words: 1
accesses an INDFn register actually
accesses the register at the address Cycles: 1
specified by the FSRn. Example: MOVWF OPTION_REG
Before Instruction
FSRn is limited to the range 0000h -
FFFFh. Incrementing/decrementing it OPTION_REG = 0xFF
beyond these bounds will cause it to W = 0x4F
After Instruction
wrap-around.
OPTION_REG = 0x4F
W = 0x4F
MOVLB Move literal to BSR
Syntax: [ label ] MOVLB k
Operands: 0  k  31
Operation: k  BSR
Status Affected: None
Description: The 5-bit literal ‘k’ is loaded into the
Bank Select Register (BSR).

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MOVWI Move W to INDFn NOP No Operation

Syntax: [ label ] MOVWI ++FSRn Syntax: [ label ] NOP

[ label ] MOVWI --FSRn Operands: None
[ label ] MOVWI FSRn++ Operation: No operation
[ label ] MOVWI FSRn--
[ label ] MOVWI k[FSRn] Status Affected: None
Operands: n  [0,1] Description: No operation.
mm  [00,01, 10, 11] Words: 1
-32  k  31
Cycles: 1
Operation: W  INDFn
Effective address is determined by Example: NOP
• FSR + 1 (preincrement)
• FSR - 1 (predecrement)
• FSR + k (relative offset)
After the Move, the FSR value will be
either:
Load OPTION_REG Register
OPTION
• FSR + 1 (all increments) with W
• FSR - 1 (all decrements) Syntax: [ label ] OPTION
Unchanged
Operands: None
Status Affected: None
Operation: (W)  OPTION_REG
Status Affected: None
Mode Syntax mm
Description: Move data from W register to
Preincrement ++FSRn 00 OPTION_REG register.
Predecrement --FSRn 01
Postincrement FSRn++ 10 Words: 1
Postdecrement FSRn-- 11 Cycles: 1
Example: OPTION
Description: This instruction is used to move data Before Instruction
between W and one of the indirect OPTION_REG = 0xFF
registers (INDFn). Before/after this W = 0x4F
move, the pointer (FSRn) is updated by After Instruction
pre/post incrementing/decrementing it. OPTION_REG = 0x4F
W = 0x4F
Note: The INDFn registers are not
physical registers. Any instruction that
accesses an INDFn register actually
RESET Software Reset
accesses the register at the address
specified by the FSRn. Syntax: [ label ] RESET
Operands: None
FSRn is limited to the range
0000h-FFFFh. Operation: Execute a device Reset. Resets the
Incrementing/decrementing it beyond RI flag of the PCON register.
these bounds will cause it to Status Affected: None
wrap-around.
Description: This instruction provides a way to
The increment/decrement operation on execute a hardware Reset by
FSRn WILL NOT affect any Status bits. software.

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RETFIE Return from Interrupt RETURN Return from Subroutine

Syntax: [ label ] RETFIE k Syntax: [ label ] RETURN
Operands: None Operands: None
Operation: TOS  PC, Operation: TOS  PC
1  GIE Status Affected: None
Status Affected: None Description: Return from subroutine. The stack is
Description: Return from Interrupt. Stack is POPed POPed and the top of the stack (TOS)
and Top-of-Stack (TOS) is loaded in is loaded into the program counter.
the PC. Interrupts are enabled by This is a 2-cycle instruction.
setting Global Interrupt Enable bit,
GIE (INTCON<7>). This is a 2-cycle
instruction.
Words: 1
Cycles: 2
Example: RETFIE
After Interrupt
PC = TOS
GIE = 1

RETLW Return with literal in W

RLF Rotate Left f through Carry
Syntax: [ label ] RETLW k
Syntax: [ label ] RLF f,d
Operands: 0  k  255
Operands: 0  f  127
Operation: k  (W);
d  [ 0, 1]
TOS  PC
Operation: See description below
Status Affected: None
Status Affected: C
Description: The W register is loaded with the 8-bit
literal ‘k’. The program counter is Description: The contents of register ‘f’ are rotated
loaded from the top of the stack (the one bit to the left through the Carry
return address). This is a 2-cycle flag. If ‘d’ is ‘0’, the result is placed in
instruction. the W register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
Words: 1
C Register f
Cycles: 2
Example: CALL TABLE;W contains table Words: 1
;offset value
• ;W now has table value Cycles: 1
TABLE • Example: RLF REG1,0
•
Before Instruction
ADDWF PC ;W = offset
REG1 = 1110 0110
RETLW k1 ;Begin table
C = 0
RETLW k2 ;
After Instruction
•
REG1 = 1110 0110
•
W = 1100 1100
•
C = 1
RETLW kn ; End of table

Before Instruction
W = 0x07
After Instruction
W = value of k8

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SUBLW Subtract W from literal

RRF Rotate Right f through Carry
Syntax: [ label ] SUBLW k
Syntax: [ label ] RRF f,d
Operands: 0 k 255
Operands: 0  f  127
d  [0,1] Operation: k - (W) W)

Operation: See description below Status Affected: C, DC, Z

Status Affected: C Description: The W register is subtracted (2’s

complement method) from the 8-bit
Description: The contents of register ‘f’ are rotated literal ‘k’. The result is placed in the W
one bit to the right through the Carry register.
flag. If ‘d’ is ‘0’, the result is placed in
the W register. If ‘d’ is ‘1’, the result is C=0 Wk
placed back in register ‘f’.
C=1 Wk
C Register f
DC = 0 W<3:0>  k<3:0>
DC = 1 W<3:0>  k<3:0>

SLEEP Enter Sleep mode SUBWF Subtract W from f

Syntax: [ label ] SLEEP Syntax: [ label ] SUBWF f,d
Operands: None Operands: 0 f 127
d  [0,1]
Operation: 00h  WDT,
0  WDT prescaler, Operation: (f) - (W) destination)
1  TO, Status Affected: C, DC, Z
0  PD
Description: Subtract (2’s complement method) W
Status Affected: TO, PD register from register ‘f’. If ‘d’ is ‘0’, the
Description: The power-down Status bit, PD is result is stored in the W
cleared. Time-out Status bit, TO is register. If ‘d’ is ‘1’, the result is stored
set. Watchdog Timer and its back in register ‘f.
prescaler are cleared.
The processor is put into Sleep mode C=0 Wf
with the oscillator stopped. C=1 Wf
DC = 0 W<3:0>  f<3:0>
DC = 1 W<3:0>  f<3:0>

SUBWFB Subtract W from f with Borrow

Syntax: SUBWFB f {,d}
Operands: 0  f  127
d  [0,1]
Operation: (f) – (W) – (B) dest
Status Affected: C, DC, Z
Description: Subtract W and the BORROW flag
(CARRY) from register ‘f’ (2’s
complement method). If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’.

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SWAPF Swap Nibbles in f XORLW Exclusive OR literal with W

Syntax: [ label ] SWAPF f,d Syntax: [ label ] XORLW k
Operands: 0  f  127 Operands: 0 k 255
d  [0,1]
Operation: (W) .XOR. k W)
Operation: (f<3:0>)  (destination<7:4>),
Status Affected: Z
(f<7:4>)  (destination<3:0>)
Description: The contents of the W register are
Status Affected: None
XOR’ed with the 8-bit literal ‘k’. The
Description: The upper and lower nibbles of result is placed in the W register.
register ‘f’ are exchanged. If ‘d’ is ‘0’,
the result is placed in the W register. If
‘d’ is ‘1’, the result is placed in register
‘f’.

XORWF Exclusive OR W with f

TRIS Load TRIS Register with W
Syntax: [ label ] XORWF f,d
Syntax: [ label ] TRIS f
Operands: 0  f  127
Operands: 5f7
d  [0,1]
Operation: (W)  TRIS register ‘f’
Operation: (W) .XOR. (f) destination)
Status Affected: None
Status Affected: Z
Description: Move data from W register to TRIS
Description: Exclusive OR the contents of the W
register.
register with register ‘f’. If ‘d’ is ‘0’, the
When ‘f’ = 5, TRISA is loaded.
result is stored in the W register. If ‘d’
When ‘f’ = 6, TRISB is loaded.
is ‘1’, the result is stored back in
When ‘f’ = 7, TRISC is loaded.
register ‘f’.

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 PIC16(L)F1704/8
32.0 ELECTRICAL SPECIFICATIONS
32.1 Absolute Maximum Ratings(†)
Ambient temperature under bias...................................................................................................... -40°C to +125°C
Storage temperature ........................................................................................................................ -65°C to +150°C
Voltage on pins with respect to VSS
on VDD pin
PIC16F1704/8 ........................................................................................................... -0.3V to +6.5V
PIC16LF1704/8 ......................................................................................................... -0.3V to +4.0V
on MCLR pin ........................................................................................................................... -0.3V to +9.0V
on all other pins ............................................................................................................ -0.3V to (VDD + 0.3V)
Maximum current(1)
on VSS pin
-40°C  TA  +85°C, Industrial ............................................................................................. 250 mA
+85°C  TA  +125°C, Extended ............................................................................................ 85 mA
on VDD pin
-40°C  TA  +85°C, Industrial ............................................................................................. 250 mA
+85°C  TA  +125°C, Extended ............................................................................................ 85 mA
sunk by any I/O pin ................................................................................................................. 50 mA
sourced by any I/O pin ........................................................................................................... 50 mA
sourced by any op amp output pin...................................................................................... 100 mA
Clamp current, IK (VPIN < 0 or VPIN > VDD) ................................................................................................... 20 mA
Total power dissipation(2) ............................................................................................................................... 800 mW

Note 1: Maximum current rating requires even load distribution across I/O pins. Maximum current rating may be
limited by the device package power dissipation characterizations, see Table 32-3 to calculate device
specifications.
2: Power dissipation is calculated as follows:
PDIS = VDD x {IDD – ΣIOH} + Σ{VDD – VOH) x IOH} + Σ(VOL x IOI).

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for
extended periods may affect device reliability.

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PIC16(L)F1704/8
32.2 Standard Operating Conditions
The standard operating conditions for any device are defined as:
Operating Voltage: VDDMIN VDD VDDMAX
Operating Temperature: TA_MIN TA TA_MAX
VDD — Operating Supply Voltage(1)
PIC16LF1704/8
VDDMIN (Fosc  16 MHz).......................................................................................................... +1.8V
VDDMIN (Fosc  16 MHz).......................................................................................................... +2.5V
VDDMAX .................................................................................................................................... +3.6V
PIC16F1704/8
VDDMIN (Fosc  16 MHz).......................................................................................................... +2.3V
VDDMIN (16 MHz)................................................................................................................... +2.5V
VDDMAX .................................................................................................................................... +5.5V
TA — Operating Ambient Temperature Range
Industrial Temperature
TA_MIN ...................................................................................................................................... -40°C
TA_MAX .................................................................................................................................... +85°C
Extended Temperature
TA_MIN ...................................................................................................................................... -40°C
TA_MAX .................................................................................................................................. +125°C
Note 1: See Parameter D001, DS Characteristics: Supply Voltage.

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 PIC16(L)F1704/8
FIGURE 32-1: VOLTAGE FREQUENCY GRAPH, -40°C  TA +125°C, PIC16F1704/8 ONLY

5.5

VDD (V)

2.5

2.3

0 4 10 16 32
Frequency (MHz)

Note 1:The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 32-7 for each Oscillator mode’s supported frequencies.

FIGURE 32-2: VOLTAGE FREQUENCY GRAPH, -40°C  TA +125°C, PIC16LF1704/8 ONLY

VDD (V)

3.6

2.5

1.8

0 4 10 16 32
Frequency (MHz)

Note 1:The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 32-7 for each Oscillator mode’s supported frequencies.

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32.3 DC Characteristics
TABLE 32-1: SUPPLY VOLTAGE
PIC16LF1704/8 Standard Operating Conditions (unless otherwise stated)

PIC16F1704/8 Standard Operating Conditions (unless otherwise stated)

Param. Sym. Characteristic Min. Typ.† Max. Units Conditions
No.
D001 VDD Supply Voltage
PIC16LF1704/8 1.8 — 3.6 V FOSC  16 MHz
2.5 — 3.6 V FOSC  32 MHz (Note 2)
D001 PIC16F1704/8 2.3 — 5.5 V FOSC  16 MHz:
2.5 — 5.5 V FOSC  32 MHz (Note 2)
D002* VDR RAM Data Retention Voltage(1)
PIC16LF1704/8 1.5 — — V Device in Sleep mode
D002* PIC16F1704/8 1.7 — — V Device in Sleep mode
D002A* VPOR Power-on Reset Release Voltage(3)
PIC16LF1704/8 — 1.6 — V
D002A* PIC16F1704/8 — 1.6 — V
D002B* VPORR* Power-on Reset Rearm Voltage(3)
PIC16LF1704/8 — 0.8 — V
D002B* PIC16F1704/8 — 1.5 — V
D003 VFVR Fixed Voltage Reference Voltage
1x gain (1.024 nominal) -4 — +4 % VDD 2.5V, -40°C to 85°C
2x gain (2.048 nominal) -4 — +4 % VDD 2.5V, -40°C to 85°C
4x gain (4.096 nominal) -5 — +5 % VDD 4.75V, -40°C to 85°C
D004* SVDD VDD Rise Rate to ensure internal 0.05 — — V/ms See Section 5.1 “Power-On Reset
Power-on Reset signal(2) (POR)” for details.
* These parameters are characterized but not tested.
† Data in “Typ.” column is at 3.3V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
2: PLL required for 32 MHz operation.
3: See Figure 32-3: POR and POR Rearm with Slow Rising VDD.

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FIGURE 32-3: POR AND POR REARM WITH SLOW RISING VDD

VDD

VPOR
VPORR
SVDD

VSS
NPOR(1)

POR REARM

VSS

TVLOW(2) TPOR(3)

Note 1: When NPOR is low, the device is held in Reset.

2: TVLOW 2.7 s typical.
3: TPOR 1 s typical.

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TABLE 32-2: SUPPLY CURRENT (IDD)(1,2)

PIC16LF1704/8 Standard Operating Conditions (unless otherwise stated)

PIC16F1704/8 Standard Operating Conditions (unless otherwise stated)

Param. Device Conditions

Min. Typ.† Max. Units
No. Characteristics VDD Note

D009 LDO Regulator — 75 — A — High Power mode, normal operation

— 15 — A — Sleep, VREGCON<1> = 0
— 0.3 — A — Sleep, VREGCON<1> = 1
D010 — 5.0 12 A 1.8 FOSC = 32 kHz, LP Oscillator mode (Note 4),
— 8.0 18 A 3.0 -40°C  TA  +85°C
D010 — 16 26 A 2.3 FOSC = 32 kHz, LP Oscillator mode (Note 4,
— 18 32 A 3.0 Note 5),
-40°C  TA  +85°C
— 22 35 A 5.0
D012 — 160 240 A 1.8 FOSC = 4 MHz,
— 280 380 A 3.0 XT Oscillator mode

D012 — 250 320 A 2.3 FOSC = 4 MHz,

— 320 420 A 3.0 XT Oscillator mode (Note 5)
— 400 500 A 5.0
D014 — 140 180 A 1.8 FOSC = 4 MHz,
— 240 300 A 3.0 External Clock (ECM),
Medium-Power mode
D014 — 210 280 A 2.3 FOSC = 4 MHz,
— 280 350 A 3.0 External Clock (ECM),
Medium-Power mode
— 360 420 A 5.0
D015 — 1.9 2.6 mA 3.0 FOSC = 32 MHz,
— 2.4 3.0 mA 3.6 External Clock (ECH),
High-Power mode (Note 5)
D015 — 2 2.6 mA 3.0 FOSC = 32 MHz,
— 2.2 2.8 mA 5.0 External Clock (ECH),
High-Power mode (Note 5)
D017 — 115 170 A 1.8 FOSC = 500 kHz,
— 135 200 A 3.0 MFINTOSC mode
D017 — 150 200 A 2.3 FOSC = 500 kHz,
— 170 220 A 3.0 MFINTOSC mode
— 215 280 A 5.0
D019 — 0.7 1.1 mA 1.8 FOSC = 16 MHz,
— 1.2 1.8 mA 3.0 HFINTOSC mode
D019 — 0.9 1.5 mA 2.3 FOSC = 16 MHz,
— 1.3 1.8 mA 3.0 HFINTOSC mode

— 1.4 2.0 mA 5.0

† Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from
rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current
consumption.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended
by the formula IR = VDD/2REXT (mA) with REXT in k
4: FVR and BOR are disabled.
5: 8 MHz clock with 4x PLL enabled.

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TABLE 32-2: SUPPLY CURRENT (IDD)(1,2) (CONTINUED)
PIC16LF1704/8 Standard Operating Conditions (unless otherwise stated)

PIC16F1704/8 Standard Operating Conditions (unless otherwise stated)

Param. Device Conditions

Min. Typ.† Max. Units
No. Characteristics VDD Note
D020 — 2.3 3.0 mA 3.0 FOSC = 32 MHz,
— 2.8 3.5 mA 3.6 HFINTOSC mode (Note 5)

D020 — 2.4 3.1 mA 3.0 FOSC = 32 MHz,

— 2.6 3.4 mA 5.0 HFINTOSC mode (Note 5)
D022 — 2 3.0 mA 3.0 FOSC = 32 MHz,
— 2.6 3.5 mA 3.6 HS Oscillator mode (Note 5)
D022 — 2.1 3.0 mA 3.0 FOSC = 32 MHz,
— 3 3.5 mA 5.0 HS Oscillator mode (Note 5)

† Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from
rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current
consumption.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended
by the formula IR = VDD/2REXT (mA) with REXT in k
4: FVR and BOR are disabled.
5: 8 MHz clock with 4x PLL enabled.

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TABLE 32-3: POWER-DOWN CURRENTS (IPD)(1,2)

Standard Operating Conditions (unless otherwise stated)
PIC16LF1704/8
Low-Power Sleep Mode
PIC16F1704/8 Low-Power Sleep Mode, VREGPM = 1

Param. Max. Max. Conditions

Device Characteristics Min. Typ.† Units
No. +85°C +125°C VDD Note
D023 Base IPD — 0.05 1.0 8.0 A 1.8 WDT, BOR, FVR, and SOSC
— 0.08 2.0 9.0 A 3.0 disabled, all Peripherals Inactive
D023 Base IPD — 0.3 3.0 10 A 2.3 WDT, BOR, FVR, and SOSC
— 0.4 4.0 12 A 3.0 disabled, all Peripherals Inactive,
Low-Power Sleep mode
— 0.5 6.0 15 A 5.0
D023A Base IPD — 9.8 16 18 A 2.3 WDT, BOR, FVR and SOSC
— 10.3 18 20 A 3.0 disabled, all Peripherals inactive,
Normal-Power Sleep mode
— 11.5 21 26 A 5.0 VREGPM = 0
D024 — 0.5 6 14 A 1.8 WDT Current
— 0.8 7 17 A 3.0
D024 — 0.8 6 15 A 2.3 WDT Current
— 0.9 7 20 A 3.0
— 1.0 8 22 A 5.0
D025 — 15 28 30 A 1.8 FVR Current
— 18 30 33 A 3.0
D025 — 18 33 35 A 2.3 FVR Current
— 19 35 37 A 3.0
— 20 37 39 A 5.0
D026 — 7.5 25 28 A 3.0 BOR Current
D026 — 10 25 28 A 3.0 BOR Current
— 12 28 31 A 5.0
D027 — 0.5 4 10 A 3.0 LPBOR Current
D027 — 0.8 6 14 A 3.0 LPBOR Current
— 1 8 17 A 5.0
D028 — 0.5 5 9 A 1.8 SOSC Current
— 0.8 8.5 12 A 3.0
D028 — 1.1 6 10 A 2.3 SOSC Current
— 1.3 8.5 20 A 3.0
— 1.4 10 25 A 5.0
D029 — 0.05 2 9 A 1.8 ADC Current (Note 3),
— 0.08 3 10 A 3.0 no conversion in progress
D029 — 0.3 4 12 A 2.3 ADC Current (Note 3),
— 0.4 5 13 A 3.0 no conversion in progress

— 0.5 7 16 A 5.0
* These parameters are characterized but not tested.
† Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is
enabled. The peripheral  current can be determined by subtracting the base IDD or IPD current from this limit. Max val-
ues should be used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VSS.
3: ADC oscillator source is FRC.

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TABLE 32-3: POWER-DOWN CURRENTS (IPD)(1,2) (CONTINUED)
Standard Operating Conditions (unless otherwise stated)
PIC16LF1704/8
Low-Power Sleep Mode
PIC16F1704/8 Low-Power Sleep Mode, VREGPM = 1

Param. Max. Max. Conditions

Device Characteristics Min. Typ.† Units
No. +85°C +125°C VDD Note
D030 — 250 — — A 1.8 ADC Current (Note 3),
— 250 — — A 3.0 conversion in progress

D030 — 280 — — A 2.3 ADC Current (Note 3),

— 280 — — A 3.0 conversion in progress
— 280 — — A 5.0
D031 — 250 650 — A 3.0 Op Amp (High-power)
D031 — 250 650 — A 3.0 Op Amp (High-power)
— 350 850 — A 5.0
D032 — 250 600 — A 1.8 Comparator, CxSP = 1
— 300 650 — A 3.0
D032 — 280 600 — A 2.3 Comparator, CxSP = 1
— 300 650 — A 3.0 VREGPM = 0
— 310 650 — A 5.0
* These parameters are characterized but not tested.
† Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is
enabled. The peripheral  current can be determined by subtracting the base IDD or IPD current from this limit. Max val-
ues should be used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VSS.
3: ADC oscillator source is FRC.

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PIC16(L)F1704/8

TABLE 32-4: I/O PORTS

Standard Operating Conditions (unless otherwise stated)

Param.
Sym. Characteristic Min. Typ.† Max. Units Conditions
No.
VIL Input Low Voltage
I/O PORT:
D034 with TTL buffer — — 0.8 V 4.5V  VDD  5.5V
D034A — — 0.15 VDD V 1.8V  VDD  4.5V
D035 with Schmitt Trigger buffer — — 0.2 VDD V 2.0V  VDD  5.5V
with I2C levels — — 0.3 VDD V
with SMBus levels — — 0.8 V 2.7V  VDD  5.5V
D036 MCLR, OSC1 (RC mode) — — 0.2 VDD V (Note 1)
D036A OSC1 (HS mode) — — 0.3 VDD V
VIH Input High Voltage
I/O ports:
D040 with TTL buffer 2.0 — — V 4.5V  VDD 5.5V
D040A 0.25 VDD + — — V 1.8V  VDD  4.5V
0.8
D041 with Schmitt Trigger buffer 0.8 VDD — — V 2.0V  VDD  5.5V
with I2C levels 0.7 VDD — — V
with SMBus levels 2.1 — — V 2.7V  VDD  5.5V
D042 MCLR 0.8 VDD — — V
D043A OSC1 (HS mode) 0.7 VDD — — V
D043B OSC1 (RC oscillator) 0.9 VDD — — V VDD  2.0V (Note 1)
IIL Input Leakage Current(2)
D060 I/O Ports — ±5 ± 125 nA VSS  VPIN  VDD,
Pin at high-impedance, 85°C
— ±5 ± 1000 nA VSS  VPIN  VDD,
Pin at high-impedance, 125°C
D061 MCLR(3) — ±5 ± 200 nA VSS  VPIN  VDD,
Pin at high-impedance, 85°C
IPUR Weak Pull-up Current
D070* 25 100 200 A VDD = 3.3V, VPIN = VSS
VOL Output Low Voltage(4)
D080 I/O ports IOL = 8 mA, VDD = 5V
— — 0.6 V IOL = 6 mA, VDD = 3.3V
IOL = 1.8 mA, VDD = 1.8V
VOH Output High Voltage(4)
D090 I/O ports IOH = -3.5 mA, VDD = 5V
VDD – 0.7 — — V IOH = -3 mA, VDD = 3.3V
IOH = -1 mA, VDD = 1.8V
Capacitive Loading Specs on Output Pins
D101* COSC2 OSC2 pin — — 15 pF In XT, HS and LP modes when
external clock is used to drive
OSC1
D101A* CIO All I/O pins — — 50 pF
* These parameters are characterized but not tested.
† Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external
clock in RC mode.
2: Negative current is defined as current sourced by the pin.
3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
4: Including OSC2 in CLKOUT mode.

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TABLE 32-5: MEMORY PROGRAMMING SPECIFICATIONS

Standard Operating Conditions (unless otherwise stated)
Param.
Sym. Characteristic Min. Typ.† Max. Units Conditions
No.
Program Memory
Programming Specifications
D110 VIHH Voltage on MCLR/VPP pin 8.0 — 9.0 V (Note 1, Note 2)
D111 IDDP Supply Current during — — 10 mA
Programming
D112 VBE VDD for Bulk Erase 2.7 — VDDMAX V
D113 VPEW VDD for Write or Row Erase VDDMIN — VDDMAX V
D114 IPPGM Current on MCLR/VPP during — — 1.0 mA
Erase/Write
D115 IDDPGM Current on VDD during Erase/ — — 5.0 mA
Write
Program Flash Memory
D121 EP Cell Endurance 10K — — E/W -40C  TA  +85C
(Note 3)
D122 VPR VDD for Read VDDMIN — VDDMAX V
D123 TIW Self-timed Write Cycle Time — 2 2.5 ms
D124 TRETD Characteristic Retention — 40 — Year Provided no other
specifications are violated
D125 EHEFC High-Endurance Flash Cell 100K — — E/W 0C  TA  +60°C, Lower
byte last 128 addresses
† Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Required only if single-supply programming is disabled.
2: The MPLAB ICD2 does not support variable VPP output. Circuitry to limit the ICD2 VPP voltage must be
placed between the ICD2 and target system when programming or debugging with the ICD2.
3: Self-write and Block Erase.

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TABLE 32-6: THERMAL CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)

Param.
Sym. Characteristic Typ. Units Conditions
No.

TH01 JA Thermal Resistance Junction to Ambient 70.0 C/W 14-pin PDIP package
95.3 C/W 14-pin SOIC package
100.0 C/W 14-pin TSSOP package
51.5 C/W 16-pin QFN 4x4mm package
62.2 C/W 20-pin PDIP package
87.3 C/W 20-pin SSOP
77.7 C/W 20-pin SOIC package
43.0 C/W 20-pin QFN 4x4mm package
TH02 JC Thermal Resistance Junction to Case 32.75 C/W 14-pin PDIP package
31.0 C/W 14-pin SOIC package
24.4 C/W 14-pin TSSOP package
5.4 C/W 16-pin QFN 4x4mm package
27.5 C/W 20-pin PDIP package
31.1 C/W 20-pin SSOP
23.1 C/W 20-pin SOIC package
5.3 C/W 20-pin QFN 4x4mm package
TH03 TJMAX Maximum Junction Temperature 150 C
TH04 PD Power Dissipation — W PD = PINTERNAL + PI/O
TH05 PINTERNAL Internal Power Dissipation — W PINTERNAL = IDD x VDD(1)
TH06 PI/O I/O Power Dissipation — W PI/O =  (IOL * VOL) +  (IOH * (VDD - VOH))
TH07 PDER Derated Power — W PDER = PDMAX (TJ - TA)/JA(2)
Note 1: IDD is current to run the chip alone without driving any load on the output pins.
2: TA = Ambient Temperature, TJ = Junction Temperature

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32.4 AC Characteristics
Timing Parameter Symbology has been created with one of the following formats:
1. TppS2ppS
2. TppS
T
F Frequency T Time
Lowercase letters (pp) and their meanings:
pp
cc CCP1 osc OSC1
ck CLKOUT rd RD
cs CS rw RD or WR
di SDI sc SCK
do SDO ss SS
dt Data in t0 T0CKI
io I/O PORT t1 T1CKI
mc MCLR wr WR
Uppercase letters and their meanings:
S
F Fall P Period
H High R Rise
I Invalid (High-impedance) V Valid
L Low Z High-impedance

FIGURE 32-4: LOAD CONDITIONS

Load Condition

Pin CL

VSS

Legend: CL = 50 pF for all pins.

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PIC16(L)F1704/8
FIGURE 32-5: CLOCK TIMING

Q4 Q1 Q2 Q3 Q4 Q1

CLKIN
OS02 OS12 OS11

OS03

CLKOUT
(CLKOUT Mode)

Note 1: See Table 32-10.

TABLE 32-7: CLOCK OSCILLATOR TIMING REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Param.
Sym. Characteristic Min. Typ.† Max. Units Conditions
No.

OS01 FOSC External CLKIN Frequency(1) DC — 0.5 MHz EC Oscillator mode (low)
DC — 4 MHz EC Oscillator mode (medium)
DC — 32 MHz EC Oscillator mode (high)
(1)
Oscillator Frequency — 32.768 — kHz LP Oscillator mode
0.1 — 4 MHz XT Oscillator mode
1 — 4 MHz HS Oscillator mode
1 — 20 MHz HS Oscillator mode, VDD > 2.7V
DC — 4 MHz RC Oscillator mode, VDD > 2.0V
OS02 TOSC External CLKIN Period(1) 27 —  s LP Oscillator mode
250 —  ns XT Oscillator mode
50 —  ns HS Oscillator mode
31.25 —  ns EC Oscillator mode
Oscillator Period(1) — 30.5 — s LP Oscillator mode
250 — 10,000 ns XT Oscillator mode
50 — 1,000 ns HS Oscillator mode
250 — — ns RC Oscillator mode
OS03 TCY Instruction Cycle Time(1) 125 TCY DC ns TCY = 4/FOSC
OS04* TosH, External CLKIN High, 2 — — s LP Oscillator mode
TosL External CLKIN Low 100 — — ns XT Oscillator mode
20 — — ns HS Oscillator mode
OS05* TosR, External CLKIN Rise, 0 — — ns LP Oscillator mode
TosF External CLKIN Fall 0 — — ns XT Oscillator mode
0 — — ns HS Oscillator mode
* These parameters are characterized but not tested.
† Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing
code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current
consumption. All devices are tested to operate at “min” values with an external clock applied to OSC1 pin. When an
external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

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TABLE 32-8: OSCILLATOR PARAMETERS
Standard Operating Conditions (unless otherwise stated)

Param. Freq.
Sym. Characteristic Min. Typ.† Max. Units Conditions
No. Tolerance
OS08 HFOSC Internal Calibrated HFINTOSC ±2% — 16.0 — MHz 3.2V, 25°C
Frequency(1)
OS08A MFOSC Internal Calibrated MFINTOSC ±2% — 500 — kHz
Frequency(1)
OS09 LFOSC Internal LFINTOSC Frequency — — 31 — kHz -40°C  TA  +125°C
OS10* TIOSC ST HFINTOSC — — 3.2 8 s
Wake-up from Sleep Start-up Time
MFINTOSC — — 24 35 s
Wake-up from Sleep Start-up Time
* These parameters are characterized but not tested.
† Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing code.
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current
consumption. All devices are tested to operate at “min” values with an external clock applied to the OSC1 pin. When an
external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

FIGURE 32-6: HFINTOSC AND MFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND
TEMPERATURE

125
± 5%

85
± 3%
Temperature (°C)

60
± 2%

25

± 5%
-40
1.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

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TABLE 32-9: PLL CLOCK TIMING SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated)
Param.
Sym. Characteristic Min. Typ.† Max. Units Conditions
No.
F10 FOSC Oscillator Frequency Range 4 — 8 MHz
F11 FSYS On-Chip VCO System Frequency 16 — 32 MHz
F12 TRC PLL Start-up Time (Lock Time) — — 2 ms
F13* CLK CLKOUT Stability (Jitter) -0.25% — +0.25% %
* These parameters are characterized but not tested.
† Data in “Typ.” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.

FIGURE 32-7: CLKOUT AND I/O TIMING

Cycle Write Fetch Read Execute

Q4 Q1 Q2 Q3
FOSC
OS11 OS12
OS20
CLKOUT OS21
OS19 OS16 OS18
OS13 OS17
I/O pin
(Input)
OS15 OS14
I/O pin Old Value New Value
(Output)
OS18, OS19

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TABLE 32-10: CLKOUT AND I/O TIMING PARAMETERS
Standard Operating Conditions (unless otherwise stated)

Param.
Sym. Characteristic Min. Typ.† Max. Units Conditions
No.

OS11 TOSH2CKL FOSC to CLKOUT (1) — — 70 ns 3.3V  VDD 5.0V

OS12 TOSH2CKH FOSC to CLKOUT (1) — — 72 ns 3.3V  VDD 5.0V
OS13 TCKL2IOV CLKOUT to Port out valid(1) — — 20 ns
OS14 TIOV2CKH Port input valid before CLKOUT(1) TOSC + 200 ns — — ns
OS15 TOSH2IOV Fosc (Q1 cycle) to Port out valid — 50 70* ns 3.3V  VDD 5.0V
OS16 TOSH2IOI Fosc (Q2 cycle) to Port input invalid 50 — — ns 3.3V  VDD 5.0V
(I/O in hold time)
OS17 TIOV2OSH Port input valid to Fosc(Q2 cycle) 20 — — ns
(I/O in setup time)
OS18* TIOR Port output rise time(2) — 40 72 ns VDD = 1.8V
— 15 32 3.3V  VDD 5.0V
OS19* TIOF Port output fall time(2) — 28 55 ns VDD = 1.8V
— 15 30 3.3V  VDD 5.0V
OS20* TINP INT pin input high or low time 25 — — ns
OS21* TIOC Interrupt-on-change new input level time 25 — — ns
* These parameters are characterized but not tested.
† Data in “Typ.” column is at 3.0V, 25C unless otherwise stated.
Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.
2: Slew rate limited.

FIGURE 32-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING

VDD

MCLR

30
Internal
POR

33
PWRT
Time-out 32
OSC
Start-up Time

Internal Reset(1)

Watchdog Timer
Reset(1)
31
34
34
I/O pins

Note 1: Asserted low.

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TABLE 32-11: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET PARAMETERS
Standard Operating Conditions (unless otherwise stated)

Param .
Sym. Characteristic Min. Typ.† Max. Units Conditions
No.

30 TMCL MCLR Pulse Width (low) 2 — — s

31 TWDTLP Low-Power Watchdog Timer 10 16 27 ms 3.3V  VDD 5.0V
Time-out Period 1:512 Prescaler used
32 TOST Oscillator Start-up Timer Period(1,2) — 1024 — TOSC
33* TPWRT Power-up Timer Period, PWRTE = 0 40 65 140 ms
34* TIOZ I/O high-impedance from MCLR Low — — 2.0 s
or Watchdog Timer Reset
35 VBOR Brown-out Reset Voltage(3) 2.55 2.70 2.85 V BORV = 0

2.30 2.45 2.60 V BORV = 1 (PIC16F1704/8)

1.80 1.90 2.10 V BORV = 1 (PIC16LF1704/8)
35A VLPBOR Low-Power Brown-out(3) 1.80 2.1 2.5 V LPBOR = 1
36* VHYST Brown-out Reset Hysteresis(3) 0 25 75 mV -40°C  TA  +85°C
37* TBORDC Brown-out Reset DC Response 1 3 35 s VDD  VBOR
Time
*These parameters are characterized but not tested.
†Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values
are based on characterization data for that particular oscillator type under standard operating conditions
with the device executing code. Exceeding these specified limits may result in an unstable oscillator opera-
tion and/or higher than expected current consumption. All devices are tested to operate at “min” values
with an external clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time
limit is “DC” (no clock) for all devices.
2: Period of the slower clock.
3: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as
possible. 0.1 F and 0.01 F values in parallel are recommended.

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 PIC16(L)F1704/8
FIGURE 32-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS

T0CKI

40 41

42

T1CKI
45 46

47 49

TMR0 or
TMR1

FIGURE 32-10: BROWN-OUT RESET TIMING AND CHARACTERISTICS

VDD
VBOR and VHYST
VBOR

(Device in Brown-out Reset) (Device not in Brown-out Reset)

37

Reset
33(1)
(due to BOR)

Note 1: 64 ms delay only if PWRTE bit in the Configuration Word register is programmed to
‘0’.
2 ms delay if PWRTE = 0.

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PIC16(L)F1704/8
TABLE 32-12: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Param.
Sym. Characteristic Min. Typ.† Max. Units Conditions
No.
40* TT0H T0CKI High Pulse Width No Prescaler 0.5 TCY + 20 — — ns
With Prescaler 10 — — ns
41* TT0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20 — — ns
With Prescaler 10 — — ns
42* TT0P T0CKI Period Greater of: — — ns N = prescale value
20 or (2, 4, ..., 256)
(TCY + 40)*N
45* TT1H T1CKI High Synchronous, No Prescaler 0.5 TCY + 20 — — ns
Time Synchronous, with Prescaler 15 — — ns
Asynchronous 30 — — ns
46* TT1L T1CKI Low Synchronous, No Prescaler 0.5 TCY + 20 — — ns
Time Synchronous, with Prescaler 15 — — ns
Asynchronous 30 — — ns
47* TT1P T1CKI Input Synchronous Greater of: — — ns
Period 30 or
(TCY + 40)*N
Asynchronous 60 — — ns
48 FT1 Timer1 Oscillator Input Frequency Range 32.4 32.768 33.1 kHz
(oscillator enabled by setting bit T1OSCEN)
49* TCKEZTMR1 Delay from External Clock Edge to Timer 2 TOSC — 7 TOSC — Timers in Sync
Increment mode
* These parameters are characterized but not tested.
† Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.

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 PIC16(L)F1704/8
FIGURE 32-11: CAPTURE/COMPARE/PWM TIMINGS (CCP)
CCPx
(Capture mode)

CC01 CC02

CC03

Note: Refer to Figure 32-4 for load conditions.

TABLE 32-13: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP)

Standard Operating Conditions (unless otherwise stated)
Param.
Sym. Characteristic Min. Typ.† Max. Units Conditions
No.
CC01* TccL CCPx Input Low Time No Prescaler 0.5 TCY + 20 — — ns
With Prescaler 20 — — ns
CC02* TccH CCPx Input High Time No Prescaler 0.5 TCY + 20 — — ns
With Prescaler 20 — — ns
CC03* TccP CCPx Input Period 3 TCY + 40 — — ns N = prescale value
N (1, 4 or 16)
* These parameters are characterized but not tested.
† Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.

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PIC16(L)F1704/8
FIGURE 32-12: CLC PROPAGATION TIMING

CLC LCx_in[n](1) CLC CLC

CLCxINn
Input time Module Output time
CLCx
LCx_out(1)

CLC CLC CLC

CLCxINn
Input time Module Output time
CLCx
LCx_in[n](1) LCx_out(1)

CLC01 CLC02 CLC03

Note 1: See Figure 19-1 to identify specific CLC signals.

TABLE 32-14: CONFIGURATION LOGIC CELL (CLC) CHARACTERISTICS

Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +125°C
Param.
Sym. Characteristic Min. Typ.† Max. Units Conditions
No.
CLC01* TCLCIN CLC input pin (CKCxIN[n]) to CKC module input — 7 OS17 ns (Note 1)
select (LCx_in[n]) propagation time
CLC02* TCLC CLC module input to output progagation time — 24 — ns VDD = 1.8V
— 12 — ns VDD > 3.6V
CLC03* TCLCOUT CLC output time Rise Time — OS18 — — (Note 2)
Fall Time — OS19 — — (Note 2)
CLC04* FCLCMAX CLC maximum switching frequency — 45 — MHz
* These parameters are characterized but not tested.
† Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: I/O setup delay.
2: See Table 32-10 for OS17, OS18 and OS19 rise and fall times.

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 PIC16(L)F1704/8
TABLE 32-15: ANALOG-TO-DIGITAL CONVERTER (ADC) CHARACTERISTICS(1,2):
Standard Operating Conditions (unless otherwise stated)
Operating temperature: Tested at 25°C
Param.
Sym. Characteristic Min. Typ.† Max. Units Conditions
No.
AD01 NR Resolution — — 10 bit
AD02 EIL Integral Error — — ±1.7 LSb VREF = 3.0V
AD03 EDL Differential Error — — ±1 LSb No missing codes, VREF = 3.0V
AD04 EOFF Offset Error — — ±2.5 LSb VREF = 3.0V
AD05 EGN Gain Error — — ±2.0 LSb VREF = 3.0V
AD06 VREF Reference Voltage(3) 1.8 — VDD V VREF = (VREF+ minus VREF-)
AD07 VAIN Full-Scale Range VSS — VREF V
AD08 ZAIN Recommended Impedance of — — 10 k Can go higher if external 0.01 F capacitor is
Analog Voltage Source present on input pin.
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Total Absolute Error includes integral, differential, offset and gain errors.
2: The ADC conversion result never decreases with an increase in the input voltage and has no missing codes.
3: VREF = (VREF+ – VREF-); ADCREF+ may be VDD, VREF+ pin or FVR1_buffer. The ADCREF- may be VSS or VREF- pin. If
selecting the FVR1_buffer, the buffers output voltage must be 2.048V or 4.096V.

TABLE 32-16: ADC CONVERSION REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Param.
Sym. Characteristic Min. Typ.† Max. Units Conditions
No.
AD130* TAD ADC Clock Period (TADC) 1.0 — 9.0 s FOSC-based
FRC Oscillator Period (TFRC) 1.0 2 6.0 s ADCS<1:0> = 11 (ADC FRC mode)
AD131 TCNV Conversion Time (not including — 11 — TAD Set GO/DONE bit to conversion
Acquisition Time)(1) complete
AD132* TACQ Acquisition Time — 5.0 — s
AD133* THCD Holding Capacitor Disconnect Time — 0.5 TAD — ADCS<2:0>  x11 (FOSC based)
— 1/2 TAD + 1 TCY — ADCS<2:0> = x11 (FRC based)
*
These parameters are characterized but not tested.
†
Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: The ADRES register may be read on the following TCY cycle.

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FIGURE 32-13: ADC CONVERSION TIMING (ADC CLOCK FOSC-BASED)

BSF ADCON0, GO
1 TCY
AD133
AD131
Q4
AD130

ADC_clk

ADC Data 9 8 7 6 3 2 1 0

ADRES OLD_DATA NEW_DATA

ADIF 1 TCY

GO DONE
Sampling Stopped
Sample AD132

FIGURE 32-14: ADC CONVERSION TIMING (ADC CLOCK FROM FRC)

BSF ADCON0, GO
AD133 1 TCY
AD131
Q4
AD130
ADC_clk

ADC Data 9 8 7 6 3 2 1 0

ADRES OLD_DATA NEW_DATA

ADIF 1 TCY

GO DONE

AD132 Sampling Stopped

Sample

Note 1: If the ADC clock source is selected as FRC, a time of TCY is added before the ADC clock starts.
This allows the SLEEP instruction to be executed.

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 PIC16(L)F1704/8
TABLE 32-17: OPERATIONAL AMPLIFIER (OPA)
Standard Operating Conditions (unless otherwise stated)
VDD = 3.0V, TA = 25°C, OPAxSP = 1 (High GBWP mode)

Param.
Symbol Parameters Min. Typ. Max. Units Conditions
No.
OPA01* GBWP Gain Bandwidth Product — 3.5 — MHz
OPA02* TON Turn on Time — 10 — s
OPA03* PM Phase Margin — 40 — degrees
OPA04* SR Slew Rate — 3 — V/s
OPA05 OFF Offset — ±3 ±9 mV
OPA06 CMRR Common Mode Rejection Ratio 52 70 — dB
OPA07* AOL Open Loop Gain — 90 — dB
OPA08 VICM Common Mode Input Voltage 0 — VDD V VDD > 2.5V
OPA09* PSRR Power Supply Rejection Ratio — 80 — dB
* These parameters are characterized but not tested.

TABLE 32-18: COMPARATOR SPECIFICATIONS

Standard Operating Conditions (unless otherwise stated)
VDD = 3.0V, TA = 25°C
See Section 33.0 “DC and AC Characteristics Graphs and Charts” for operating characterization.

Param
Sym. Characteristics Min. Typ. Max. Units Comments
No.
CM01 VIOFF Input Offset Voltage — ±2.5 ±5 mV Normal-Power mode
measured at VDD/2
CM02 VICM Input Common Mode Voltage 0 — VDD V
CM03 CMRR Common Mode Rejection Ratio 40 50 — dB
CM04A Response Time Rising Edge — 60 125 ns Normal-Power mode
measured at VDD/2 (Note1)
CM04B Response Time Falling Edge — 60 110 ns Normal-Power mode
measured at VDD/2 (Note1)
TRESP(1)
CM04C Response Time Rising Edge — 85 — ns Low-Power mode
measured at VDD/2 (Note1)
CM04D Response Time Falling Edge — 85 — ns Low-Power mode
measured at VDD/2 (Note1)
CM05* TMC2OV Comparator Mode Change to — — 10 s
Output Valid*
CM06 CHYSTER Comparator Hysteresis 20 45 75 mV Hysteresis ON High-Power
mode measured at VDD/2
(Note 2)
* These parameters are characterized but not tested.
Note 1: Response time measured with one comparator input at VDD/2, while the other input transitions from VSS to
VDD.
2: Comparator hysteresis is available when the CxHYS bit of the CMxCON0 register is enabled.

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PIC16(L)F1704/8
TABLE 32-19: DIGITAL-TO-ANALOG CONVERTER (DAC) SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated)
VDD = 3.0V, TA = 25°C
See Section 33.0 “DC and AC Characteristics Graphs and Charts” for operating characterization.

Param.
Sym. Characteristics Min. Typ. Max. Units Comments
No.
DAC01* CLSB Step Size(1) — VDD/256 — V
DAC02* CACC Absolute Accuracy — —  1.5 LSb
DAC03* CR Unit Resistor Value® — 600 — 
DAC04* CST Settling Time (2)
— — 10 s
* These parameters are characterized but not tested.
Note 1: Comparator hysteresis is available when the CxHYS bit of the CMxCON0 register is enabled.
2: Response time measured with one comparator input at VDD/2 while other input transitions from VSS to
VDD.

TABLE 32-20: ZERO-CROSS PIN SPECIFICATIONS

Standard Operating Conditions (unless otherwise stated)
VDD = 3.0V, TA = 25°C
Param.
Sym. Characteristics Min. Typ. Max. Units Comments
No.
ZC01 ZCPINV Voltage on Zero-Cross Pin — 0.75 — V
ZC02 ZCSRC Source current — — -600 A ZCPINV = VSS
ZC03 ZCSNK Sink current 600 — — A ZCPINV = VDD
ZC04* ZCISW Response Time Rising Edge — 1 — s
Response Time Falling Edge — 1 — s
ZC05* ZCOUT Response Time Rising Edge — 1 — s
Response Time Falling Edge — 1 — s
* These parameters are characterized but not tested.

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FIGURE 32-15: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING

CK
US121 US121

DT

US120 US122

Note: Refer to Figure 32-4 for load conditions.

TABLE 32-21: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Param.
Symbol Characteristic Min. Max. Units Conditions
No.
US120 TCKH2DTV SYNC XMIT (Master and Slave) — 80 ns 3.0V  VDD  5.5V
Clock high to data-out valid — 100 ns 1.8V  VDD  5.5V
US121 TCKRF Clock out rise time and fall time — 45 ns 3.0V  VDD  5.5V
(Master mode) — 50 ns 1.8V  VDD  5.5V
US122 TDTRF Data-out rise time and fall time — 45 ns 3.0V  VDD  5.5V
— 50 ns 1.8V  VDD  5.5V

FIGURE 32-16: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING

CK
US125

DT
US126

Note: Refer to Figure 32-4 for load conditions.

TABLE 32-22: USART SYNCHRONOUS RECEIVE REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Param.
Symbol Characteristic Min. Max. Units Conditions
No.
US125 TDTV2CKL SYNC RCV (Master and Slave)
Data-setup before CK  (DT hold time) 10 — ns
US126 TCKL2DTL Data-hold after CK  (DT hold time) 15 — ns

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FIGURE 32-17: SPI MASTER MODE TIMING (CKE = 0, SMP = 0)

SS
SP81
SCK
(CKP = 0)
SP71 SP72
SP78 SP79

SCK
(CKP = 1)

SP79 SP78
SP80

SDO MSb bit 6 - - - - - -1 LSb

SP75, SP76

SDI MSb In bit 6 - - - -1 LSb In

SP74
SP73

Note: Refer to Figure 32-4 for load conditions.

FIGURE 32-18: SPI MASTER MODE TIMING (CKE = 1, SMP = 1)

SS

SP81
SCK
(CKP = 0)
SP71 SP72
SP79
SP73
SCK
(CKP = 1)

SP80
SP78

SDO MSb bit 6 - - - - - -1 LSb

SP75, SP76

SDI MSb In bit 6 - - - -1 LSb In

SP74

Note: Refer to Figure 32-4 for load conditions.

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 PIC16(L)F1704/8
FIGURE 32-19: SPI SLAVE MODE TIMING (CKE = 0)

SS

SP70

SCK SP83
(CKP = 0)
SP71 SP72
SP78 SP79

SCK
(CKP = 1)

SP79 SP78
SP80

SDO MSb bit 6 - - - - - -1 LSb

SP75, SP76 SP77

SDI MSb In bit 6 - - - -1 LSb In

SP74

SP73

Note: Refer to Figure 32-4 for load conditions.

FIGURE 32-20: SPI SLAVE MODE TIMING (CKE = 1)

SP82
SS

SP70
SCK SP83
(CKP = 0)

SP71 SP72

SCK
(CKP = 1)

SP80

SDO MSb bit 6 - - - - - -1 LSb

SP77
SP75, SP76

SDI
MSb In bit 6 - - - -1 LSb In

SP74

Note: Refer to Figure 32-4 for load conditions.

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PIC16(L)F1704/8
TABLE 32-23: SPI MODE REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)

Param .
Symbol Characteristic Min. Typ.† Max. Units Conditions
No.

SP70* TSSL2SCH, SS to SCK or SCK input 2.25 TCY — — ns

TSSL2SCL
SP71* TSCH SCK input high time (Slave mode) TCY + 20 — — ns
SP72* TSCL SCK input low time (Slave mode) TCY + 20 — — ns
SP73* TDIV2SCH, Setup time of SDI data input to SCK 100 — — ns
TDIV2SCL edge
SP74* TSCH2DIL, Hold time of SDI data input to SCK 100 — — ns
TSCL2DIL edge
SP75* TDOR SDO data output rise time — 10 25 ns 3.0V  VDD  5.5V
— 25 50 ns 1.8V  VDD  5.5V
SP76* TDOF SDO data output fall time — 10 25 ns
SP77* TSSH2DOZ SS to SDO output high-impedance 10 — 50 ns
SP78* TSCR SCK output rise time — 10 25 ns 3.0V  VDD  5.5V
(Master mode) — 25 50 ns 1.8V  VDD  5.5V
SP79* TSCF SCK output fall time (Master mode) — 10 25 ns
SP80* TSCH2DOV, SDO data output valid after SCK — — 50 ns 3.0V  VDD  5.5V
TSCL2DOV edge — — 145 ns 1.8V  VDD  5.5V
SP81* TDOV2SCH, SDO data output setup to SCK edge TCY — — ns
TDOV2SCL
SP82* TSSL2DOV SDO data output valid after SS — — 50 ns
edge
SP83* TSCH2SSH, SS after SCK edge 1.5 TCY + 40 — — ns
TSCL2SSH
* These parameters are characterized but not tested.
† Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.

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FIGURE 32-21: I2C BUS START/STOP BITS TIMING

SCL
SP91 SP93
SP90 SP92

SDA

Start Stop
Condition Condition

Note: Refer to Figure 32-4 for load conditions.

TABLE 32-24: I2C BUS START/STOP BITS REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Param.
Symbol Characteristic Min. Typ. Max. Units Conditions
No.

SP90* TSU:STA Start condition 100 kHz mode 4700 — — ns Only relevant for repeated
Setup time 400 kHz mode 600 — — Start condition
SP91* THD:STA Start condition 100 kHz mode 4000 — — ns After this period, the first
Hold time 400 kHz mode 600 — — clock pulse is generated
SP92* TSU:STO Stop condition 100 kHz mode 4700 — — ns
Setup time 400 kHz mode 600 — —
SP93 THD:STO Stop condition 100 kHz mode 4000 — — ns
Hold time 400 kHz mode 600 — —
* These parameters are characterized but not tested.

FIGURE 32-22: I2C BUS DATA TIMING

SP103 SP100 SP102

SP101

SCL
SP90
SP106
SP107
SP91 SP92
SDA
In
SP110
SP109
SP109
SDA
Out

Note: Refer to Figure 32-4 for load conditions.

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PIC16(L)F1704/8
TABLE 32-25: I2C BUS DATA REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)

Param.
Symbol Characteristic Min. Max. Units Conditions
No.
SP100* THIGH Clock high time 100 kHz mode 4.0 — s Device must operate at a
minimum of 1.5 MHz
400 kHz mode 0.6 — s Device must operate at a
minimum of 10 MHz
SSP module 1.5 TCY — —
SP101* TLOW Clock low time 100 kHz mode 4.7 — s Device must operate at a
minimum of 1.5 MHz
400 kHz mode 1.3 — s Device must operate at a
minimum of 10 MHz
SSP module 1.5 TCY — —
SP102* TR SDA and SCL rise 100 kHz mode — 1000 ns
time 400 kHz mode 20 + 0.1CB 300 ns CB is specified to be from
10-400 pF
SP103* TF SDA and SCL fall 100 kHz mode — 250 ns
time 400 kHz mode 20 + 0.1CB 250 ns CB is specified to be from
10-400 pF
SP106* THD:DAT Data input hold time 100 kHz mode 0 — ns
400 kHz mode 0 0.9 s
SP107* TSU:DAT Data input setup 100 kHz mode 250 — ns (Note 2)
time 400 kHz mode 100 — ns
SP109* TAA Output valid from 100 kHz mode — 3500 ns (Note 1)
clock 400 kHz mode — — ns
SP110* TBUF Bus free time 100 kHz mode 4.7 — s Time the bus must be free
400 kHz mode 1.3 — s before a new transmission
can start
SP111 CB Bus capacitive loading — 400 pF
* These parameters are characterized but not tested.
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
2: A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but the
requirement TSU:DAT 250 ns must then be met. This will automatically be the case if the device does not
stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it
must output the next data bit to the SDA line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the
Standard mode I2C bus specification), before the SCL line is released.

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 PIC16(L)F1704/8
33.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS
The graphs and tables provided in this section are for design guidance and are not tested.
In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD
range). This is for information only and devices are ensured to operate properly only within the specified range.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
“Typical” represents the mean of the distribution at 25C. “MAXIMUM”, “Max.”, “MINIMUM” or “Min.”
represents (mean + 3) or (mean - 3) respectively, where  is a standard deviation, over each
temperature range.

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PIC16(L)F1704/8
Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 µF, TA = 25°C.

10 400

Max: 85°C + 3ı 4 MHz XT

9 Typical: 25°C 350 Max: 85°C + 3ı

8 Max. 300

7 Typical
250
IDD (µA)

IDD (µA)
6 200

5 150 1 MHz XT

4 100

3 50

2 0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8

VDD (V) VDD (V)

FIGURE 33-1: IDD, LP Oscillator Mode, FIGURE 33-4: IDD Maximum, XT and
FOSC = 32 kHz. PIC16LF1704/8 Only. EXTRC Oscillator. PIC16LF1704/8 Only.

28
450
4 MHz XT
Max: 85°C + 3ı Max.
26
Typical: 25°C 400 Typical: 25°C

24
350
Typical
22
300
IDD (µA)

20
250
IDD (µA)

1 MHz XT
18 200

16 150

14 100

12 50

10 0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

VDD (V) VDD (V)

FIGURE 33-2: IDD, LP Oscillator Mode, FIGURE 33-5: IDD Typical, XT and EXTRC
FOSC = 32 kHz. PIC16F1704/8 Only. Oscillator. PIC16F1704/8 Only.

400 500
4 MHz XT
450 Max: 85°C + 3ı
350 Typical: 25°C

4 MHz XT 400
300
350
250
300
IDD (µA)

IDD (µA)

200 250 1 MHz XT

150 200
1 MHz XT
150
100
100
50
50

0 0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

VDD (V) VDD (V)

FIGURE 33-3: IDD Typical, XT and EXTRC FIGURE 33-6: IDD Maximum, XT and
Oscillator. PIC16LF1704/8 Only. EXTRC Oscillator. PIC16F1704/8 Only.

DS40001715D-page 404  2013-2015 Microchip Technology Inc.

 PIC16(L)F1704/8
Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 µF, TA = 25°C.

12 60
Max: 85°C + 3ı Max. Max.
Typical: 25°C 55 Max: 85°C + 3ı
10 Typical: 25°C

50
Typical
8
45

IDD (µA)
IDD (µA)

Typical
6 40

35
4

30
2
25

0 20
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

VDD (V) VDD (V)

FIGURE 33-7: IDD, EC Oscillator, Low-Power FIGURE 33-10: IDD, EC Oscillator, Low-Power
Mode, FOSC = 32 MHz. PIC16LF1704/8 Only. Mode, FOSC = 500 kHz. PIC16F1704/8 Only.

24 350

Max: 85°C + 3ı Typical: 25°C

22 Typical: 25°C Max. 300
4 MHz

20 250
Typical
IDD (µA)

18 200

16 IDD (µA) 150

14 100 1 MHz

12 50

10 0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8

VDD (V) VDD (V)

FIGURE 33-8: IDD, EC Oscillator, Low-Power FIGURE 33-11: IDD Typical, EC Oscillator,
Mode, FOSC = 32 MHz. PIC16F1704/8 Only. Medium-Power Mode. PIC16LF1704/8 Only.

50 350

45 Max: 85°C + 3ı Max: 85°C + 3ı 4 MHz

300
Typical: 25°C Max.
40
250

35
IDD (µA)

200
IDD (µA)

Typical
30

150
25
1 MHz
100
20

15 50

10
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V) VDD (V)

FIGURE 33-9: IDD, EC Oscillator, Low-Power FIGURE 33-12: IDD Maximum, EC Oscillator,
Mode, FOSC = 500 kHz. PIC16LF1704/8 Only. Medium-Power Mode. PIC16LF1704/8 Only.

 2013-2015 Microchip Technology Inc. DS40001715D-page 405

PIC16(L)F1704/8
Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 µF, TA = 25°C.

400 3.0

350 Typical: 25°C Max: 85°C + 3ı

4 MHz 2.5
32 MHz
300

2.0
250
IDD (µA)

IDD (mA)
200 1.5
1 MHz
150 16 MHz
1.0
100
8 MHz
0.5
50

0 0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8

VDD (V) VDD ((V))

FIGURE 33-13: IDD Typical, EC Oscillator, FIGURE 33-16: IDD Maximum, EC Oscillator,
Medium-Power Mode. PIC16F1704/8 Only. High-Power Mode. PIC16LF1704/8 Only.

450 2.5
32 MHz
400 Max: 85°C + 3ı Typical: 25°C

2.0
350 4 MHz

300
1.5
IDD (µA)

IDD (mA)
250
16 MHz

200
1 MHz 1.0
150 8 MHz

100
0.5

50

0 0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

VDD (V) VDD (V)

FIGURE 33-14: IDD Maximum, EC Oscillator, FIGURE 33-17: IDD Typical, EC Oscillator,
Medium-Power Mode. PIC16F1704/8 Only. High-Power Mode. PIC16F1704/8 Only.

2.5 2.5

Typical: 25°C 32 MHz Max: 85°C + 3ı

32 MHz
2.0 2.0

1.5 1.5
IDD (mA)

IDD (mA)

16 MHz

16 MHz
1.0 1.0
8 MHz

8 MHz
0.5 0.5

0.0 0.0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

VDD (V) VDD (V)

FIGURE 33-15: IDD Typical, EC Oscillator, FIGURE 33-18: IDD Maximum, EC Oscillator,
High-Power Mode. PIC16LF1704/8 Only. High-Power Mode. PIC16F1704/8 Only.

DS40001715D-page 406  2013-2015 Microchip Technology Inc.

 PIC16(L)F1704/8
Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 µF, TA = 25°C.

9 260
Max. Max.
8 240 Max: 85°C + 3ı
Max: 85°C + 3ı Typical: 25°C
Typical: 25°C Typical
7
220

6 Typical
200
IDD (µA)

IDD (µA)
5
180
4
160
3
140
2

120
1

0 100
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

VDD (V) VDD (V)

FIGURE 33-19: IDD, LFINTOSC Mode, FIGURE 33-22: IDD, MFINTOSC Mode,
FOSC = 31 kHz. PIC16LF1704/8 Only. FOSC = 500 kHz. PIC16F1704/8 Only.

24 1.6

Max. 16 MHz
22 1.4 Typical: 25°C

20 Typical 1.2
IDD (µA)

IDD (mA)
18 1.0
8 MHz

16 0.8
4 MHz
14 0.6
2 MHz

12 0.4
Max: 85°C + 3ı
Typical: 25°C 1 MHz
0.2
10
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
VDD (V)

FIGURE 33-20: IDD, LFINTOSC Mode, FIGURE 33-23: IDD Typical, HFINTOSC
FOSC = 31 kHz. PIC16F1704/8 Only. Mode. PIC16LF1704/8 Only.

180 1.6
16 MHz

170 Max: 85°C + 3ı Max: 85°C + 3ı

Typical: 25°C 1.4

160 Max.
1.2

150
IDD (mA)

1.0 8 MHz
IDD (µA)

Typical
140
0.8
130 4 MHz

0.6 2 MHz
120

0.4 1 MHz
110

100 0.2
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8

VDD (V) VDD (V)

FIGURE 33-21: IDD, MFINTOSC Mode, FIGURE 33-24: IDD Maximum, HFINTOSC
FOSC = 500 kHz. PIC16LF1704/8 Only. Mode. PIC16LF1704/8 Only.

 2013-2015 Microchip Technology Inc. DS40001715D-page 407

PIC16(L)F1704/8
Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 µF, TA = 25°C.

1.6 2.0

16 MHz 1.8 Max: 85°C + 3ı

1.4 Typical: 25°C
20 MHz
1.6

1.2 1.4
16 MHz
1.2
1.0 8 MHz
IDD (mA)

IDD (mA)
1.0
0.8
4 MHz 0.8

0.6 8 MHz
0.6 2 MHz

0.4
0.4 1 MHz 4 MHz
0.2

0.2 0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8

VDD (V) VDD (V)

FIGURE 33-25: IDD Typical, HFINTOSC FIGURE 33-28: IDD Maximum, HS Oscillator.
Mode. PIC16F1704/8 Only. PIC16LF1704/8 Only.

1.6 2.0
16 MHz
1.8 Typical: 25°C 20 MHz
1.4 Max: 85°C + 3ı
1.6
16 MHz
1.2 1.4

8 MHz 1.2
1.0
IDD (mA)

IDD (mA)

1.0
0.8 4 MHz
0.8 8 MHz

0.6 2 MHz 0.6

4 MHz
0.4
1 MHz
0.4
0.2

0.2 0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

VDD (V) VDD (V)

FIGURE 33-26: IDD Maximum, HFINTOSC FIGURE 33-29: IDD Typical, HS Oscillator,
Mode. PIC16F1704/8 Only. 25°C. PIC16F1704/8 Only.

2.0 2.2
Max: 85°C + 3ı
1.8 Typical: 25°C 2.0
20 MHz
1.6 1.8
20 MHz
1.4 1.6
16 MHz
1.2 16 MHz 1.4
IDD (mA)
IDD (mA)

1.0 1.2

0.8 1.0

0.6 8 MHz 0.8 8 MHz

0.4 0.6
4 MHz
0.2 0.4 4 MHz

0.0 0.2
2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

VDD (V) VDD (V)

FIGURE 33-27: IDD Typical, HS Oscillator, FIGURE 33-30: IDD Maximum, HS Oscillator.
25°C. PIC16LF1704/8 Only. PIC16F1704/8 Only.

DS40001715D-page 408  2013-2015 Microchip Technology Inc.

 PIC16(L)F1704/8
Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 µF, TA = 25°C.

3.0 1.2

Max.
Max. 1.0
2.5

0.8
Typical
2.0

IPD (µA)
Max: 85°C + 3ı
IDD (mA)

0.6 T i l 25°C
Typical:

1.5
0.4
Typical

1.0 0.2
Typical: 25°C
Max: 85°C + 3ı
0.0
0.5
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8

VDD (V)
VDD (V)

FIGURE 33-31: IDD, HS Oscillator, 32 MHz FIGURE 33-34: IPD Base, Low-Power Sleep
(8 MHz + 4x PLL). PIC16LF1704/8 Only. Mode (VREGPM = 1). PIC16F1704/8 Only.

3.5 3.0
Max: 85°C + 3ı
Typical: 25°C
2.5
3.0
Max.
Max.
2.0
2.5 Typical

µA)
IPD (µA)
15
1.5
IDD (mA)

2.0
1.0

Typical
1.5 0.5
Typical: 25°C
Max: 85°C + 3ı
0.0
1.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

VDD (V)
VDD (V)

FIGURE 33-32: IDD, HS Oscillator, 32 MHz FIGURE 33-35: IPD, Watchdog Timer (WDT).
(8 MHz + 4x PLL). PIC16F1704/8 Only. PIC16LF1704/8 Only.

450 2.5

400 Max: 85°C + 3ı

Max. Typical: 25°C
350 2.0
Max.

300

1.5
IDD (nA)

IPD (µA)

250

200 Max: 85°C + 3ı

Typical: 25°C
1.0
150
Typical
00
100
0.5
50 Typical

0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 0.0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V) VDD (V)

FIGURE 33-33: IPD Base, Low-Power Sleep FIGURE 33-36: IPD, Watchdog Timer (WDT).
Mode. PIC16LF1704/8 Only. PIC16F1704/8 Only.

 2013-2015 Microchip Technology Inc. DS40001715D-page 409

PIC16(L)F1704/8
Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 µF, TA = 25°C.

35 13
Max: 85°C + 3
M 3ı Max: 85°C + 3ı
Typical: 25°C 12 Typical: 25°C
30 Max.
11
Max.
25 10
IDD (nA)

IDD (nA)
nA)
Typical
20
8

Typical
7
15

10
5

4
5 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
VDD (V) VDD (V)

FIGURE 33-37: IPD, Fixed Voltage Reference FIGURE 33-40: IPD, Brown-out Reset (BOR),
(FVR). PIC16LF1704/8 Only. BORV = 1. PIC16F1704/8 Only.

35 1.8

1.6 Max.

30 Max. 1.4

1.2
25 Max: 85°C + 3ı
IDD (nA)

1.0 Typical: 25°C

IDD (nA)

Typical 0.8
20
0.6
Typical
0.4
15 Max: 85°C + 3ı
Typical: 25°C 0.2

10 0.0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7

VDD (V) VDD (V)

FIGURE 33-38: IPD, Fixed Voltage Reference FIGURE 33-41: IPD, Low-Power Brown-out
(FVR). PIC16F1704/8 Only. Reset, LPBOR = 0. PIC16LF1704/8 Only.

11 1.8
Max: 85°C + 3
M 3ı Max: 85°C + 3ı
Typical: 25°C 1.6 Typical: 25°C
10 Max. Max.
1.4
9
1.2
IDD (nA)

IDD (µA)

8 Typical 1.0

7 0.8

0.6
6
0.4 Typical

5
02
0.2

4 0.0
2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6

VDD (V) VDD (V)

FIGURE 33-39: IPD, Brown-out Reset (BOR), FIGURE 33-42: IPD, Low-Power Brown-out
BORV = 1. PIC16LF1704/8 Only. Reset, LPBOR = 0. PIC16F1704/8 Only.

DS40001715D-page 410  2013-2015 Microchip Technology Inc.

 PIC16(L)F1704/8
Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 µF, TA = 25°C.

7 900
Max: 8
M 85°C
°C + 3
3ı
Max: 85°C + 3ı
800 Typical: 25°C
6 Typical: 25°C Max.
Max.
700
5
600
IDD (µA)

IDD (µA)
500
Typical

3 400

Typical 300
2
200

1
100

0 0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

VDD (V) VDD (V)

FIGURE 33-43: IPD, Timer1 Oscillator, FIGURE 33-46: IPD, Op Amp, High GBWP
FOSC = 32 kHz. PIC16LF1704/8 Only. Mode (OPAxSP = 1). PIC16F1704/8 Only.

12 500
Max: 85°C + 3
M 3ı Max: 85°C + 3ı
Typical: 25°C 450 Typical: 25°C
10 Max.
400

350
8 Max.
300

µA)
IDD (µA)
µA)
IDD (µA)

6 250
Typical
200
4
150

100
2
50 Typical

0 0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8

VDD (V) VDD (V)

FIGURE 33-44: IPD, Timer1 Oscillator, FIGURE 33-47: IPD, ADC Non-Converting.
FOSC = 32 kHz. PIC16F1704/8 Only. PIC16LF1704/8 Only.

700 1.4

Max: 85°C + 3ı Max: 85°C + 3ı

600 Typical: 25°C 1.2 Typical: 25°C Max.

Max.
500 1.0

400 0.8
µA)
IDD (µA)
µA)
IDD (µA)

Typical
300 0.6

200 0.4
Typical

100 0.2

0 0.0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

VDD (V)
VDD (V)

FIGURE 33-45: IPD, Op Amp, High GBWP FIGURE 33-48: IPD, ADC Non-Converting.
Mode (OPAxSP = 1). PIC16LF1704/8 Only. PIC16F1704/8 Only.

 2013-2015 Microchip Technology Inc. DS40001715D-page 411

PIC16(L)F1704/8
Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 µF, TA = 25°C.

800
5
Max: -40°C + 3ı Graph represents 3ı Limits
Typical: 25°C
700 Max.
4

600

Typical
D (µA)

VOL (V)
500
IDD

-40°C

2 Typical
400
125°C

300 1

200
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 0
0 10 20 30 40 50 60 70 80
VDD (V) IOL (mA)

FIGURE 33-49: Ipd, Comparator, FIGURE 33-52: VOL vs. IOL Over
Normal-Power Mode (CxSP = 1). PIC16LF1704/8 Temperature, VDD = 5.0V. PIC16F1704/8 Only.
Only.

800 3.5

Max: -40°C + 3ı Graph represents 3ı Limits

Typical: 25°C Max.
3.0
700

2.5
600

2.0
VOH (V)

Typical
IDD (µA)

500
1.5
125°C

400 Typical
1.0

-40°C
300 0.5

200 0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 -14 -12 -10 -8 -6 -4 -2 0

VDD (V) IOH (mA)

FIGURE 33-50: Ipd, Comparator, FIGURE 33-53: VOH vs. IOH, Over
Normal-Power Mode (CxSP = 1). PIC16F1704/8 Temperature, VDD = 3.0V.
Only.

6 3.0

Graph represents 3ı Limits Graph represents 3ı Limits

2.5
5

2.0
4
VOL (V)

-40°C
VOH (V)

-40°C
1.5 Typical
3

125°C
125°C 1.0
2 Typical

0.5
1

0.0
0
0 5 10 15 20 25 30
-30 -25 -20 -15 -10 -5 0
IOL (mA)
IOH (mA)

FIGURE 33-51: VOH vs. IOH, Over FIGURE 33-54: VOL vs. IOL, Over
Temperature, VDD = 5.0V. PIC16F1704/8 Only. Temperature, VDD = 3.0V.

DS40001715D-page 412  2013-2015 Microchip Technology Inc.

 PIC16(L)F1704/8
Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 µF, TA = 25°C.

2.0 40,000
Graph represents 3ı Limits
1.8 38,000
Max.
1.6 36,000

1.4 34,000
Typical

Frequency (Hz)
1.2 32,000
VOH (V)

1.0 125°C 30,000

Min.
0.8 28,000
Typical
0.6 -40°C 26,000

0.4 24,000
Max: Typical + 3ı (-40°C to +125°C)
22,000 Typical; statistical mean @ 25°C
0.2 Min: Typical - 3ı (-40°C to +125°C)

0.0 20,000
-4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

VDD (V)
IOH (mA)

FIGURE 33-55: VoH vs. IoH, Over FIGURE 33-58: LFINTOSC Frequency.
Temperature, VDD = 1.8V. PIC16LF1704/8 Only. PIC16F1704/8 Only.

1.8 24
Graph represents 3ı Limits
1.6
22
Max.
1.4
20
1.2

Time (ms)
18
Vol (V)

1.0 Typical
125°C Typical
0.8 16
-40°C
Min.
0.6
14
0.4
Max: Typical + 3ı (-40°C to +125°C)
12 Typical; statistical mean @ 25°C
0.2 Min: Typical - 3ı (-40°C to +125°C)

0.0 10
0 1 2 3 4 5 6 7 8 9 10 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

IOL (mA) VDD (V)

FIGURE 33-56: VoL vs. IoL, Over FIGURE 33-59: WDT Time-Out Period.
Temperature, VDD = 1.8V. PIC16LF1704/8 Only. PIC16F1704/8 Only.

40,000 24

38,000
Max. 22
36,000 Max.

34,000 20
Typical
Frequency (Hz)

32,000
Time (ms)

18
30,000 Typical
Min.
28,000 16

26,000 Min.
14
24,000
Max: Typical + 3ı (-40°C to +125°C) Max: Typical + 3ı (-40°C to +125°C)
Typical; statistical mean @ 25°C 12 Typical; statistical mean @ 25°C
22,000 Min: Typical - 3ı (-40°C to +125°C) Min: Typical - 3ı (-40°C to +125°C)

20,000 10
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
VDD (V)

FIGURE 33-57: LFINTOSC Frequency. FIGURE 33-60: WDT Time-Out Period.

PIC16LF1704/8 Only. PIC16LF1704/8 Only.

 2013-2015 Microchip Technology Inc. DS40001715D-page 413

PIC16(L)F1704/8
Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 µF, TA = 25°C.

2.00 70.0
Max: Typical + 3ı
Typical: statistical mean
Max. 60.0 Min: Typical - 3ı
Max.
1.95
50.0
Typical
Voltage (V)

Voltage (mV)
40.0
1.90 Typical
30.0
Min.

20.0
1.85
Max: Typical + 3ı Min.
Typical: statistical mean 10.0
Min: Typical - 3ı

1.80 0.0
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140

Temperature (°C)
( C)
Temperature (°C)

FIGURE 33-61: Brown-out Reset Voltage, FIGURE 33-64: Brown-out Reset Hysteresis,
Low Trip Point (BORV = 1). PIC16LF1704/8 Only. Low Trip Point (BORV = 1). PIC16F1704/8 Only.

70 2.85
Max: Typical + 3ı
Typical: statistical mean Max: Typical + 3ı
60 Typical: statistical mean
Min: Typical - 3ı
2.80 Min: Typical - 3ı
50 Max. Max.
Voltage (mV)

40 Voltage (V) 2.75

Typical

30
2.70 Min.
Typical

20

Min. 2.65
10

0 2.60
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140

Temperature (°C) Temperature (°C)

FIGURE 33-62: Brown-out Reset Hysteresis, FIGURE 33-65: Brown-out Reset Voltage,
Low Trip Point (BORV = 1). PIC16LF1704/8 Only. High Trip Point (BORV = 0).

2.60 80
Max: Typical + 3ı
70 Typical: statistical mean
Min: Typical - 3ı
2.55 Max.
Max.
60
Typical
2.50
50
Voltage (mV)
Voltage (V)

Min. Typical
2.45 40

30
2.40
Max: Typical + 3ı 20
Typical: statistical mean Min.
2.35 Min: Typical - 3ı
10

2.30 0
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140

Temperature (°C)
( C)
Temperature (°C)

FIGURE 33-63: Brown-out Reset Voltage, FIGURE 33-66: Brown-out Reset Hysteresis,
High Trip Point (BORV = 1). PIC16F1704/8 Only. High Trip Point (BORV = 0).

DS40001715D-page 414  2013-2015 Microchip Technology Inc.

 PIC16(L)F1704/8
Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 µF, TA = 25°C.

2.7 100
Max: Typical + 3ı Max: Typical + 3ı (-40°C to +125°C)
2.6 Typical: statistical mean Typical; statistical mean @ 25°C
Min: Typical - 3ı (-40°C to +125°C)
Min: Typical - 3ı Max. 90
2.5
Max.
2.4
80
Voltage (V)

2.3

Time (ms)
Typical
2.2 70
Typical
2.1
60
2.0 Min.

1.9
Min. 50
1.8

1.7 40
-60 -40 -20 0 20 40 60 80 100 120 140 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8

Temperature (°C)
VDD (V)

FIGURE 33-67: LPBOR Reset Voltage. FIGURE 33-70: PWRT Period. PIC16LF1704/8
Only.

50 1.70

45 Max: Typical + 3ı 1.68

Typical: statistical mean Max.
40 Max.
1.66

35 1.64
Typical
Voltage (mV)

30

Voltage (V)
1.62

25 1.60
Min.
20 1.58
Typical
15 1.56

10 1.54 Max: Typical + 3ı

Typical: statistical mean
5 1.52 Min: Typical - 3ı

0 1.50
-60 -40 -20 0 20 40 60 80 100 120 140 -50 -25 0 25 50 75 100 125 150

Temperature (°C) Temperature (°C)

FIGURE 33-68: LPBOR Reset Hysteresis. FIGURE 33-71: POR Release Voltage. All
devices

1.58
1.58
100
Max: Typical + 3ı
Max: Typical + 3ı (-40°C to +125°C)
Typical; statistical mean @ 25°C 1.56 Typical: 25°C
1.56 Min: Typical - 3ı
90 Min: Typical - 3ı (-40°C to +125°C)
Max.
Max. 1.54
1.54
(V) (V)

80 Typical
Voltage

1.52
Time (ms)

1.52
Voltage

Typical
70 1.5
1.50
Min. 1.48 Min.
60
1.48
1.46
Max: Typical + 3ı 0
50 1.46 -40 Typical:-20
statistical mean
20 40 60 80 100 120

Min: Typical - 3ı Temperature (°C)

40 1.44
2 2.5 3 3.5 4 4.5 5 5.5 6 -50 -25 0 25 50 75 100 125 150

Temperature (°C)
VDD (V)

FIGURE 33-69: PWRT Period, FIGURE 33-72: POR Rearm Voltage,

PIC16F1704/8 Only. Normal Power Mode (VREGPM 1 = 0),
PIC16F1704/8 Only.

 2013-2015 Microchip Technology Inc. DS40001715D-page 415

PIC16(L)F1704/8
Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 µF, TA = 25°C.

1.4 40

Max: Typical + 3ı
1.3 Typical: statistical mean @ 25°C
35
Max.
1.2
Max.
30
1.1

Time (µs)
Voltage (V)

Typical
25 Typical
1.0

0.9
Min. 20

0.8
Note:
Max: Typical + 3ı 15 The FVR Stabiliztion Period applies when coming out of RESET
0.7 Typical: statistical mean or exiting sleep mode.
Min: Typical - 3ı
0.6 10
-50 -25 0 25 50 75 100 125 150 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8

Temperature (°C) VDD (V)

FIGURE 33-73: POR Rearm Voltage, FIGURE 33-76: FVR Stabilization Period.
Normal Power Mode. PIC16LF1704/8 Only. PIC16LF1704/8 Only.

12 1.0
Max: Typical + 3ı (-40°C to +125°C)
Typical; statistical mean @ 25°C
10 Min: Typical - 3ı (-40°C to +125°C)

0.5
8
DNL(LSb)
Time (µs)

Max.
6 0.0
Typical

Ͳ0.5
2

0 Ͳ1.0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0 128 256 384 512 640 768 896 1024

VDD (V) OutputCode

FIGURE 33-74: Wake from Sleep, FIGURE 33-77: ADC 10-Bit Mode,
VREGPM = 0. Single-Ended DNL, VDD = 3.0V, TAD = 1 us, 25°C.

50 1.0

45

40
Max. 0.5
35
DNL(LSb)
Time (µs)

30
Typical
25 0.0

20

15
Ͳ0.5
10 Max: Typical + 3ı (-40°C to +125°C)
Typical; statistical mean @ 25°C
5 Min: Typical - 3ı (-40°C to +125°C)

0 Ͳ1.0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0 128 256 384 512 640 768 896 1024

OutputCode
VDD (V)

FIGURE 33-75: Wake from Sleep, FIGURE 33-78: ADC 10-Bit Mode,
VREGPM = 1. Single-Ended DNL, VDD = 3.0V, TAD = 4 us, 25°C.

DS40001715D-page 416  2013-2015 Microchip Technology Inc.

 PIC16(L)F1704/8
Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 µF, TA = 25°C.
, , , ,
1.5
1.0
MaxͲ40°C

1.0
Max25°C

0.5
Max125°C
0.5
INL(LSb)

INL(LSb)
0.0 0.0
Min25°C

Min125°C
Ͳ0.5 MinͲ40°C

Ͳ0.5

Ͳ1.0

Ͳ1.0 Ͳ1.5
0 128 256 384 512 640 768 896 1024 5.00EͲ07 1.00EͲ06 2.00EͲ06 4.00EͲ06 8.00EͲ06
OutputCode TADs

FIGURE 33-79: ADC 10-Bit Mode, FIGURE 33-82: ADC 10-Bit Mode,
Single-Ended INL, VDD = 3.0V, TAD = 1 us, 25°C. Single-Ended INL, VDD = 3.0V, VREF = 3.0V.

2.0 1.5
1.0
1.5
1.0
1.0
0.5
0.5
DNL(LSb)

MaxͲ40°C
0.5
0.0 Max25°C
INL(LSb)

Max125°C

DNL(LSb)
Ͳ0.5
0.0 0.0
Ͳ1.0

Ͳ1.5 Ͳ0.5 Min125°C

Ͳ0.5
Ͳ2.0 Min25°C
0 512 1024 1536 2048 2560 3072 3584 4096
MinͲ40°C
Ͳ1.0
OutputCode

Ͳ1.0
0 128 256 384 512 640 768 896 1024
Ͳ1.5
1.8 2.3 3
OutputCode VREF

FIGURE 33-80: ADC 10-Bit Mode, FIGURE 33-83: ADC 10-Bit Mode,
Single-Ended INL, VDD = 3.0V, TAD = 4 us, 25°C. Single-Ended DNL, VDD = 3.0V, TAD = 1 us.

1.5
1.5

MinͲ40°C MaxͲ40°C
1.0 1.0
Min25°C
Max25°C
0.5
Min125°C
0.5 Max125°C
INL(LSb)
DNL(LSb)

0.0
Min125°C
0.0
Ͳ0.5 Min25°C
Min125°C
MinͲ40°C
MinͲ40°C
Ͳ0.5
Ͳ1.0 Min25°C

Ͳ1.5 Ͳ1.0
5.00EͲ07 1.00EͲ06 2.00EͲ06 4.00EͲ06 8.00EͲ06 1.8 2.3 3
TADs VREF

FIGURE 33-81: ADC 10-Bit Mode, FIGURE 33-84: ADC 10-Bit Mode,
Single-Ended DNL, VDD = 3.0V, VREF = 3.0V. Single-Ended INL, VDD = 3.0V, TAD = 1 us.

 2013-2015 Microchip Technology Inc. DS40001715D-page 417

PIC16(L)F1704/8
Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 µF, TA = 25°C.

800 150
ADC VREF+ SET TO VDD ADC VREF+ SET TO VDD Max.
ADC VREF- SET TO GND 125 ADC VREF- SET TO GND Typical
700
Max.
100
600
Typical Min.
75
500

ADC Output Codes

ADC Output Codes

Min.
50
400
25
300
0
200
-25
Max: Typical + 3ı Max: Typical + 3ı
100 Typical; statistical mean Typical; statistical mean
Min: Typical - 3ı -50
Min: Typical - 3ı
0
-75
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
-50 -25 0 25 50 75 100 125 150

VDD (V) Temperature (°C)

( C)

FIGURE 33-85: Temperature Indicator Initial FIGURE 33-88: Temperature Indicator Slope
Offset, High Range, Temp. = 20°C, PIC16F1704/8 Normalized to 20°C, High Range, VDD = 5.5V,
Only. PIC16LF1704/8 Only.

900 250
ADC VREF+ SET TO VDD ADC VREF+ SET TO VDD
ADC VREF- SET TO GND Max. Max.
ADC VREF- SET TO GND
200
Typical
800 Typical
150 Min.
Min.
700
100
ADC Output Codes
ADC Output Codes

600 50

0
500
-50
Max: Typical + 3ı
400 Typical; statistical mean Max: Typical + 3ı
Min: Typical - 3ı -100 Typical; statistical mean
Min: Typical - 3ı

300 -150
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 -50 -25 0 25 50 75 100 125 150

VDD (V) Temperature (°C)

( C)

FIGURE 33-86: Temperature Indicator Initial FIGURE 33-89: Temperature Indicator Slope
Offset, Low Range, Temp. = 20°C, PIC16F1704/8 Normalized to 20°C, High Range, VDD = 3V,
Only. PIC16F1704/8 Only.

800 150
ADC VREF+ SET TO VDD ADC VREF+ SET TO VDD Max.
ADC VREF- SET TO GND 125 ADC VREF- SET TO GND
700 Max. Typical
Typical 100
600 Min.
Min. 75
ADC Output Codes
ADC Output Codes

500 50

25
400

0
300
-25
Max: Typical + 3ı Max: Typical + 3ı
200 Typical; statistical mean
Typical; statistical mean -50
Min: Typical - 3ı Min: Typical - 3ı

100 -75
1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6 3.9 -50 -25 0 25 50 75 100 125 150

VDD (V) Temperature (°C)

( C)

FIGURE 33-87: Temperature Indicator Initial FIGURE 33-90: Temperature Indicator Slope
Offset, Low Range, Temp. = 20°C, Normalized to 20°C, Low Range, VDD = 3.0V,
PIC16LF1704/8 Only. PIC16F1704/8 Only.

DS40001715D-page 418  2013-2015 Microchip Technology Inc.

 PIC16(L)F1704/8
Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 µF, TA = 25°C.

250 80
ADC VREF+ SET TO VDD Max.
ADC VREF- SET TO GND
200 Typical 75
Max.
150 70
Min.

CMRR (dB)
100 65
ADC Output Codes

Typical
50 60

0 55 Min.

-50 50
Max: Typical + 3ı
Max: Typical + 3ı Typical; statistical mean
-100 45
Typical; statistical mean Min: Typical - 3ı
Min: Typical - 3ı
-150 40
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Temperature (°C)
Temperature (°C)
( C)

FIGURE 33-91: Temperature Indicator Slope FIGURE 33-94: Op Amp, Common Mode
Normalized to 20°C, Low Range, VDD = 1.8V, Rejection Ratio (CMRR), VDD = 3.0V.
PIC16LF1704/8 Only.

150 80
ADC VREF+ SET TO VDD Max.
ADC VREF- SET TO GND
75
Typical
100 Max.
Min.
70

CMRR (dB)
65
ADC Output Codes

50
Typical

60

0
55 Min.

50
-50
Max: Typical + 3ı Max: Typical + 3ı
Typical; statistical mean Typical; statistical mean
45 Min: Typical - 3ı
Min: Typical - 3ı

-100
40
-50 -25 0 25 50 75 100 125 150
-50 -25 0 25 50 75 100 125 150
Temperature (°C)
Temperature (°C)
( C)

FIGURE 33-92: Temperature Indicator Slope FIGURE 33-95: Op Amp, Common Mode
Normalized to 20°C, Low Range, VDD = 3.0V, Rejection Ratio (CMRR), VDD = 3.0V.
PIC16LF1704/8 Only.

35%
250
ADC VREF+ SET TO VDD Sample Size = 3,200 -40°C
Max.
ADC VREF- SET TO GND 25°C
200 30%
Typical 85°C
150 125°C
Min. 25%
Percent of Units

100
ADC Output Codes

20%
50

15%
0

-50 10%

Max: Typical + 3ı
-100 Typical; statistical mean
Min: Typical - 3ı 5%

-150
-50 -25 0 25 50 75 100 125 150 0%
-7 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7
Temperature (°C) Offset Voltage (mV)

FIGURE 33-93: Temperature Indicator Slope FIGURE 33-96: Op Amp, Offset Voltage
Normalized to 20°C, High Range, VDD = 3.6V, Histogram, VDD = 3.0V, VCM = VDD/2
PIC16LF1704/8 Only.

 2013-2015 Microchip Technology Inc. DS40001715D-page 419

PIC16(L)F1704/8
Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 µF, TA = 25°C.

8 45
Max.
6 43
-40°C
41
4
39
Offset Voltage (V)

Typical

Hysteresis (mV)
25°C
2
37 85°C
0 35
125°C
-2 33

31
-4
Min. 29
Max: Typical + 3ı
-6 Typical; statistical mean
Min: Typical - 3ı 27

-8 25
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

Common Mode Voltage (V) Common Mode Voltage (V)

FIGURE 33-97: Op Amp, Offset over FIGURE 33-100: Comparator Hysteresis,

Common Mode Voltage, Vdd = 5.0V, Temp = 25°C Normal-Power Mode (CxSP = 1), VDD = 3.0V,
PIC16F1704/8 Only. Typical Measured Values.

3.8 30
VDD = 3.6V
3.7 25

20
3.6 Max.
VDD = 5.5V 15
Slew Rate (V/µs)

Offset Voltage (mV)

3.5
10

3.4 VDD = 2.3V 5

3.3 0
Min.
VDD = 3V
-5
3.2
-10
3.1
-15

3.0 -20
-60 -40 -20 0 20 40 60 80 100 120 140 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

Temperature (°C)
Common Mode Voltage (V)

FIGURE 33-98: Op Amp, Output Slew Rate, FIGURE 33-101: Comparator Offset,
Rising Edge, PIC16F1704/8 Only. Normal-Power Mode (CxSP = 1), VDD = 3.0V,
Typical Measured Values at 25°C.

30
5.4
25
5.2 Max.
20
5.0 VDD = 2.3V 15
Offset Voltage (mV)
Slew Rate (V/µs)

4.8
10
4.6 5

4.4 0
VDD = 3.6V
Min.
4.2 VDD = 5.5V -5

4.0 -10

-15
3.8 VDD = 3V
-20
3.6 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
-60 -40 -20 0 20 40 60 80 100 120 140
Common Mode Voltage (V)
Temperature (°C)

FIGURE 33-99: Op Amp, Output Slew Rate, FIGURE 33-102: Comparator Offset,
Falling Edge, PIC16F1704/8 Only. Normal-Power Mode (CxSP = 1), VDD = 3.0V,
Typical Measured Values from -40°C to 125°C.

DS40001715D-page 420  2013-2015 Microchip Technology Inc.

 PIC16(L)F1704/8
Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 µF, TA = 25°C.

140
50
Max: Typical + 3ı (-40°C to +125°C)
120 Typical; statistical mean @ 25°C
45 Min: Typical - 3ı (-40°C to +125°C)
-40°C
100
Hysteresis (mV)

40
25°C

Time (ns)
85°C 80
35 125°C
60
Max.
30
40 Typical

Min.
25
20

20 0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 1.5 2.0 2.5 3.0 3.5 4.0
Common Mode Voltage (V) VDD (V)

FIGURE 33-103: Comparator Hysteresis, FIGURE 33-106: Comparator Response Time

Normal-Power Mode (CxSP = 1), VDD = 5.5V, over Voltage, Normal-Power Mode (CxSP = 1),
Typical Measured Values, PIC16F1704/8 Only. Typical Measured Values, PIC16LF1704/8 Only.

90
30
Max: Typical + 3ı (-40°C to +125°C)
25 80 Typical; statistical mean @ 25°C
Min: Typical - 3ı (-40°C to +125°C)
20 Max. 70

15
60
Hysteresis (mV)

Time (ns)
10
50
5 Max.
40
0 Typical
Min.
30
-5 Min.

-10 20

-15 10

-20 0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Common Mode Voltage (V) VDD (V)

FIGURE 33-104: Comparator Offset, FIGURE 33-107: Comparator Response Time

Normal-Power Mode (CxSP = 1), VDD = 5.0V, over Voltage, Normal-Power Mode (CxSP = 1),
Typical Measured Values at 25°C, PIC16F1704/8 Typical Measured Values, PIC16F1704/8 Only.
Only.
TYPICAL MEASURED VALUES

1,400
40
Max: Typical + 3ı (-40°C to +125°C)
1,200 Typical; statistical mean @ 25°C
30 Min: Typical - 3ı (-40°C to +125°C)
Max.
1,000
Offset Voltage (mV)

20
Time (ns)

800
10
600

0
400
Min.
Max.
-10 Typical
200
Min.
-20 0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1.5 2.0 2.5 3.0 3.5 4.0

Common Mode Voltage (V) VDD (V)

FIGURE 33-105: Comparator Offset, FIGURE 33-108: Comparator Output Filter

Normal-Power Mode (CxSP = 1), VDD = 5.5V, Delay Time over Temperature, Normal-Power
Typical Measured Values from -40°C to 125°C, Mode, Typical Measured Values, PIC16LF1704/8
PIC16F1704/8 Only. Only.

 2013-2015 Microchip Technology Inc. DS40001715D-page 421

PIC16(L)F1704/8
Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 µF, TA = 25°C.
TYPICAL MEASURED VALUES
0.020
800 -40°C

Max: Typical + 3ı (-40°C to +125°C) 25°C

0.015
700 Typical; statistical mean @ 25°C 85°C
Min: Typical - 3ı (-40°C to +125°C)
125°C
600 0.010

500

DNL (LSb)
0.005
Time (ns)

400
0.000

300
-0.005
200 Max.

Typical -0.010
100
Min.

0 -0.015
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240
VDD (V) Output Code

FIGURE 33-109: Comparator Output Filter FIGURE 33-112: Typical DAC INL Error,
Delay Time over Temperature, Normal-Power VDD = 5.0V, VREF = External 5V, PIC16F1704/8
Mode, Typical Measured Values, PIC16F1704/8 Only.
Only.
0.025 0.00
-40°C
0.020 -0.05
25°C
85°C -0.10
0.015
125°C
0.010 -0.15
DNL (LSb)

INL (LSb)

0.005 -0.20

0.000 -0.25

-0.005 -0.30

-40°C
-0.010 -0.35
25°C

-0.015 -0.40 85°C

125°C
-0.020 -0.45
0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240
Output Code Output Code

FIGURE 33-110: Typical DAC DNL Error, FIGURE 33-113: Typical DAC INL Error,
VDD = 3.0V, VREF = External 3V. VDD = 5.0V, VREF = External 5V, PIC16F1704/8
Only.

0.00
24

-0.05
22 Max.
-0.10
20
-0.15
DNL (LSb)

18
INL (LSb)

-0.20
Typical
-0.25 16

-0.30
14
-40°C
-0.35 25°C Min.
12 Max: Typical + 3ı (-40°C to +125°C)
85°C Typical; statistical mean @ 25°C
-0.40 Min: Typical - 3ı (-40°C to +125°C)
125°C
10
-0.45 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8
0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240
Output Code
Output Code

FIGURE 33-111: Typical DAC INL Error, FIGURE 33-114: DAC INL Error, VDD = 3.0V,
VDD = 3.0V, VREF = External 3V. PIC16LF1704/8 Only.

DS40001715D-page 422  2013-2015 Microchip Technology Inc.

 PIC16(L)F1704/8
Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 µF, TA = 25°C.

0.4
0.45
0.85
0.4 VREF = INT. VDD
VREF = EXT. 1.8V
0.35
VREF = EXT. 2.0V
DNL (LSb)

0.3
0.3 0.80
VREF = EXT. 3.0V
-40°C
0.25 Vref = Int. Vdd
DNL (LSb)

ZCD Pin Voltage (V)

Vref = Ext. 1.8V
Absolute

0.2 0.75
Vref = Ext. 2.0V
0.15
0.2 25°C
Absolute

Vref = Ext. 3.0V

0.1
0.70
0.05
85°C
0.10
-50 0 50 100 150 0.65 125°C
Temperature (°C)

0.60
0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
-60 -40 -20 0 20 40 60 80 100 120 140
VDD (V)
Temperature (°C)
( C)

FIGURE 33-115: Absolute Value of DAC DNL FIGURE 33-118: ZCD Pin Voltage. Typical
Error, VDD = 3.0V, VREF = VDD. Measured Values.

0.90 1.4
-2.1 VREF = INT. VDD
Fall-2.3V
-2.3 VREF = EXT. 1.8V 1.2
0.88 Fall-3.0V
VREF = EXT. 2.0V
INL (LSb)

Fall-5.5V
-2.5
VREF = EXT. 3.0V 1.0
0.86 -40
INL (LSb)

-2.7
Absolute

25 0.8

Time (µs)
-2.9
85
0.84
Absolute

-3.1 125 0.6

-3.3
0.82 0.4
Rise-2.3V
-3.5
Rise-3.0V
0.0 1.0 2.0 3.0 4.0 5.0
0.2 Rise-5.5V
0.80 Temperature (°C)

0.0
0.78 -50 -25 0 25 50 75 100 125 150
-60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C)
Temperature (°C)
( C)

FIGURE 33-116: Absolute Value of DAC INL FIGURE 33-119: ZCD Response Time over
Error, VDD = 3.0V, VREF = VDD. Voltage, Typical Measured Values.

0.30
0.3 8.0
5.5V
VREF = INT. VDD
0.25 3.0V
ZCD Source/Sink Current (mA)

VREF = EXT. 1.8V 6.0

0.26
DNL (LSb)

0.2 VREF = EXT. 2.0V

VREF = EXT. 3.0V 2.3V

-40 4.0
DNL (LSb)

0.15
0.22 VREF = EXT. 5.0V 25
Absolute

85 2.0 1.8V
0.1
Absolute

125
0.18
0.05
0.0

0
0.14 0.0 1.0 2.0 3.0 4.0 5.0 6.0 -2.0
Temperature (°C)

-4.0
0.10 -0.20 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00 2.20
-60 -40 -20 0 20 40 60 80 100 120 140
ZCD Pin Voltage (V)
Temperature (°C)
( C)

FIGURE 33-117: Absolute Value of DAC DNL FIGURE 33-120: ZCD Pin Current over ZCD
Error, VDD = 5.0V, VREF = VDD, PIC16F1704/8 Pin Voltage, Typical Measured Values from
Only. -40°C to 125°C.

 2013-2015 Microchip Technology Inc. DS40001715D-page 423

PIC16(L)F1704/8
Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 µF, TA = 25°C.

0.45

1.00 0.40 Max: Typical + 3ı Max.

Typical; statistical mean
0.90 Min: Typical - 3ı
0.35 Typical
0.80
0.30
Min.
0.70
0.25

Time (µs)
0.60
Time (µs)

0.20
0.50
0.15
0.40
0.10
0.30 1.8V
2.3V 0.05
0.20 3.0V
5.5V 0.00
0.10 0 10 20 30 40 50 60 70
0 100 200 300 400 500
DBR/DBF Value
ZCD Source/Sink Current (uA)

FIGURE 33-121: ZCD Pin Response Time FIGURE 33-124: COG Dead-Band Delay per
Over Current, Typical Measured Values from Step, Typical Measured Values.
-40°C to 125°C.

0.07
0.28
Max.
Max: Typical + 3ı
0.06
0.26 Typical; statistical mean
Min: Typical - 3ı Typical

0.05
0.24
Time (µs)

Min.
0.04
0.22
Time (µs)

0.20 0.03

0.18 0.02
125°C
85°C
0.16 25°C 0.01
-40°C

0.14 0.00
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0 1 2 3 4 5 6 7 8 9 10 11
VDD (V) DBR/DBF Value

FIGURE 33-122: COG Dead-Band Delay, FIGURE 33-125: COG Dead-Band Delay per
DBR/DBF = 32, Typical Measured Values. Step, Zoomed to First 10 Codes, Typical
Measured Values.
9.0

8.5

8.0

7.5
Time (ns)

7.0

6.5

6.0

5.5 125°C
85°C
5.0 25°C
-40°C
4.5
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

FIGURE 33-123: COG Dead-Band DBR/DBF

Delay Per Step, Typical Measured Values.

DS40001715D-page 424  2013-2015 Microchip Technology Inc.

 PIC16(L)F1704/8
34.0 DEVELOPMENT SUPPORT 34.1 MPLAB X Integrated Development
Environment Software
The PIC® microcontrollers (MCU) and dsPIC® digital
signal controllers (DSC) are supported with a full range The MPLAB X IDE is a single, unified graphical user
of software and hardware development tools: interface for Microchip and third-party software, and
• Integrated Development Environment hardware development tool that runs on Windows®,
Linux and Mac OS® X. Based on the NetBeans IDE,
- MPLAB® X IDE Software
MPLAB X IDE is an entirely new IDE with a host of free
• Compilers/Assemblers/Linkers software components and plug-ins for high-
- MPLAB XC Compiler performance application development and debugging.
- MPASMTM Assembler Moving between tools and upgrading from software
- MPLINKTM Object Linker/ simulators to hardware debugging and programming
MPLIBTM Object Librarian tools is simple with the seamless user interface.
- MPLAB Assembler/Linker/Librarian for With complete project management, visual call graphs,
Various Device Families a configurable watch window and a feature-rich editor
• Simulators that includes code completion and context menus,
- MPLAB X SIM Software Simulator MPLAB X IDE is flexible and friendly enough for new
users. With the ability to support multiple tools on
• Emulators
multiple projects with simultaneous debugging, MPLAB
- MPLAB REAL ICE™ In-Circuit Emulator X IDE is also suitable for the needs of experienced
• In-Circuit Debuggers/Programmers users.
- MPLAB ICD 3 Feature-Rich Editor:
- PICkit™ 3
• Color syntax highlighting
• Device Programmers
• Smart code completion makes suggestions and
- MPLAB PM3 Device Programmer provides hints as you type
• Low-Cost Demonstration/Development Boards, • Automatic code formatting based on user-defined
Evaluation Kits and Starter Kits rules
• Third-party development tools • Live parsing
User-Friendly, Customizable Interface:
• Fully customizable interface: toolbars, toolbar
buttons, windows, window placement, etc.
• Call graph window
Project-Based Workspaces:
• Multiple projects
• Multiple tools
• Multiple configurations
• Simultaneous debugging sessions
File History and Bug Tracking:
• Local file history feature
• Built-in support for Bugzilla issue tracker

 2013-2015 Microchip Technology Inc. DS40001715D-page 425

PIC16(L)F1704/8
34.2 MPLAB XC Compilers 34.4 MPLINK Object Linker/
The MPLAB XC Compilers are complete ANSI C
MPLIB Object Librarian
compilers for all of Microchip’s 8, 16, and 32-bit MCU The MPLINK Object Linker combines relocatable
and DSC devices. These compilers provide powerful objects created by the MPASM Assembler. It can link
integration capabilities, superior code optimization and relocatable objects from precompiled libraries, using
ease of use. MPLAB XC Compilers run on Windows, directives from a linker script.
Linux or MAC OS X.
The MPLIB Object Librarian manages the creation and
For easy source level debugging, the compilers provide modification of library files of precompiled code. When
debug information that is optimized to the MPLAB X a routine from a library is called from a source file, only
IDE. the modules that contain that routine will be linked in
The free MPLAB XC Compiler editions support all with the application. This allows large libraries to be
devices and commands, with no time or memory used efficiently in many different applications.
restrictions, and offer sufficient code optimization for The object linker/library features include:
most applications.
• Efficient linking of single libraries instead of many
MPLAB XC Compilers include an assembler, linker and smaller files
utilities. The assembler generates relocatable object • Enhanced code maintainability by grouping
files that can then be archived or linked with other related modules together
relocatable object files and archives to create an
• Flexible creation of libraries with easy module
executable file. MPLAB XC Compiler uses the
listing, replacement, deletion and extraction
assembler to produce its object file. Notable features of
the assembler include:
34.5 MPLAB Assembler, Linker and
• Support for the entire device instruction set
Librarian for Various Device
• Support for fixed-point and floating-point data
Families
• Command-line interface
• Rich directive set MPLAB Assembler produces relocatable machine
• Flexible macro language code from symbolic assembly language for PIC24,
PIC32 and dsPIC DSC devices. MPLAB XC Compiler
• MPLAB X IDE compatibility
uses the assembler to produce its object file. The
assembler generates relocatable object files that can
34.3 MPASM Assembler then be archived or linked with other relocatable object
The MPASM Assembler is a full-featured, universal files and archives to create an executable file. Notable
macro assembler for PIC10/12/16/18 MCUs. features of the assembler include:

The MPASM Assembler generates relocatable object • Support for the entire device instruction set
files for the MPLINK Object Linker, Intel® standard HEX • Support for fixed-point and floating-point data
files, MAP files to detail memory usage and symbol • Command-line interface
reference, absolute LST files that contain source lines • Rich directive set
and generated machine code, and COFF files for • Flexible macro language
debugging.
• MPLAB X IDE compatibility
The MPASM Assembler features include:
• Integration into MPLAB X IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multipurpose
source files
• Directives that allow complete control over the
assembly process

DS40001715D-page 426  2013-2015 Microchip Technology Inc.

 PIC16(L)F1704/8
34.6 MPLAB X SIM Software Simulator 34.8 MPLAB ICD 3 In-Circuit Debugger
The MPLAB X SIM Software Simulator allows code
System
development in a PC-hosted environment by The MPLAB ICD 3 In-Circuit Debugger System is
simulating the PIC MCUs and dsPIC DSCs on an Microchip’s most cost-effective, high-speed hardware
instruction level. On any given instruction, the data debugger/programmer for Microchip Flash DSC and
areas can be examined or modified and stimuli can be MCU devices. It debugs and programs PIC Flash
applied from a comprehensive stimulus controller. microcontrollers and dsPIC DSCs with the powerful,
Registers can be logged to files for further run-time yet easy-to-use graphical user interface of the MPLAB
analysis. The trace buffer and logic analyzer display IDE.
extend the power of the simulator to record and track
The MPLAB ICD 3 In-Circuit Debugger probe is
program execution, actions on I/O, most peripherals
connected to the design engineer’s PC using a high-
and internal registers.
speed USB 2.0 interface and is connected to the target
The MPLAB X SIM Software Simulator fully supports with a connector compatible with the MPLAB ICD 2 or
symbolic debugging using the MPLAB XC Compilers, MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3
and the MPASM and MPLAB Assemblers. The supports all MPLAB ICD 2 headers.
software simulator offers the flexibility to develop and
debug code outside of the hardware laboratory 34.9 PICkit 3 In-Circuit Debugger/
environment, making it an excellent, economical
software development tool.
Programmer
The MPLAB PICkit 3 allows debugging and
34.7 MPLAB REAL ICE In-Circuit programming of PIC and dsPIC Flash microcontrollers
Emulator System at a most affordable price point using the powerful
graphical user interface of the MPLAB IDE. The
The MPLAB REAL ICE In-Circuit Emulator System is MPLAB PICkit 3 is connected to the design engineer’s
Microchip’s next generation high-speed emulator for PC using a full-speed USB interface and can be
Microchip Flash DSC and MCU devices. It debugs and connected to the target via a Microchip debug (RJ-11)
programs all 8, 16 and 32-bit MCU, and DSC devices connector (compatible with MPLAB ICD 3 and MPLAB
with the easy-to-use, powerful graphical user interface of REAL ICE). The connector uses two device I/O pins
the MPLAB X IDE. and the Reset line to implement in-circuit debugging
The emulator is connected to the design engineer’s and In-Circuit Serial Programming™ (ICSP™).
PC using a high-speed USB 2.0 interface and is
connected to the target with either a connector 34.10 MPLAB PM3 Device Programmer
compatible with in-circuit debugger systems (RJ-11)
or with the new high-speed, noise tolerant, Low- The MPLAB PM3 Device Programmer is a universal,
Voltage Differential Signal (LVDS) interconnection CE compliant device programmer with programmable
(CAT5). voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
The emulator is field upgradeable through future firm- (128 x 64) for menus and error messages, and a
ware downloads in MPLAB X IDE. MPLAB REAL ICE modular, detachable socket assembly to support
offers significant advantages over competitive emulators various package types. The ICSP cable assembly is
including full-speed emulation, run-time variable included as a standard item. In Stand-Alone mode, the
watches, trace analysis, complex breakpoints, logic MPLAB PM3 Device Programmer can read, verify and
probes, a ruggedized probe interface and long (up to program PIC devices without a PC connection. It can
three meters) interconnection cables. also set code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices, and incorporates an MMC card for file
storage and data applications.

 2013-2015 Microchip Technology Inc. DS40001715D-page 427

PIC16(L)F1704/8
34.11 Demonstration/Development 34.12 Third-Party Development Tools
Boards, Evaluation Kits, and Microchip also offers a great collection of tools from
Starter Kits third-party vendors. These tools are carefully selected
A wide variety of demonstration, development and to offer good value and unique functionality.
evaluation boards for various PIC MCUs and dsPIC • Device Programmers and Gang Programmers
DSCs allows quick application development on fully from companies, such as SoftLog and CCS
functional systems. Most boards include prototyping • Software Tools from companies, such as Gimpel
areas for adding custom circuitry and provide and Trace Systems
application firmware and source code for examination • Protocol Analyzers from companies, such as
and modification. Saleae and Total Phase
The boards support a variety of features, including LEDs, • Demonstration Boards from companies, such as
temperature sensors, switches, speakers, RS-232 MikroElektronika, Digilent® and Olimex
interfaces, LCD displays, potentiometers and additional • Embedded Ethernet Solutions from companies,
EEPROM memory. such as EZ Web Lynx, WIZnet and IPLogika®
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™
demonstration/development board series of circuits,
Microchip has a line of evaluation kits and
demonstration software for analog filter design,
KEELOQ® security ICs, CAN, IrDA®, PowerSmart
battery management, SEEVAL® evaluation system,
Sigma-Delta ADC, flow rate sensing, plus many more.
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.

DS40001715D-page 428  2013-2015 Microchip Technology Inc.

 PIC16(L)F1704/8
35.0 PACKAGING INFORMATION
35.1 Package Marking Information

14-Lead PDIP (300 mil) Example

PIC16F1704
P e3
1304017

14-Lead SOIC (3.90 mm) Example

PIC16F1704
SO e3
1304017

14-Lead TSSOP (4.4 mm) Example

XXXXXXXX 16F1704
YYWW 1304
NNN 017

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
e3 Pb-free JEDEC® designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC® designator ( e3 )
can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

 2013-2015 Microchip Technology Inc. DS40001715D-page 429

PIC16(L)F1704/8
Package Marking Information (Continued)

16-Lead QFN (4x4x0.9 mm) Example

PIN 1 PIN 1
PIC16
F1704
MV e3

130417

20-Lead PDIP (300 mil) Example

XXXXXXXXXXXXXXXXX PIC16F1708
XXXXXXXXXXXXXXXXX ML e3
YYWWNNN 130417

20-Lead SSOP (5.30 mm) Example

PIC16F1708
PT e3
130417

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
e3 Pb-free JEDEC® designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC® designator ( e3)
can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

DS40001715D-page 430  2013-2015 Microchip Technology Inc.

 PIC16(L)F1704/8
Package Marking Information (Continued)

20-Lead SOIC (7.50 mm) Example

PIC16F1708
PT e3
130417

20-Lead QFN (4x4x0.9 mm) Example

PIN 1 PIN 1
PIC16
F1708
MV e3

130417

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
e3 Pb-free JEDEC® designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC® designator ( e3 )
can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

 2013-2015 Microchip Technology Inc. DS40001715D-page 431

PIC16(L)F1704/8
35.2 Package Details
The following sections give the technical details of the packages.

             

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DS40001715D-page 432  2013-2015 Microchip Technology Inc.

 PIC16(L)F1704/8

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

 2013-2015 Microchip Technology Inc. DS40001715D-page 433

PIC16(L)F1704/8

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

DS40001715D-page 434  2013-2015 Microchip Technology Inc.

 PIC16(L)F1704/8

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 2013-2015 Microchip Technology Inc. DS40001715D-page 435

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Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

DS40001715D-page 436  2013-2015 Microchip Technology Inc.

 PIC16(L)F1704/8

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

 2013-2015 Microchip Technology Inc. DS40001715D-page 437

PIC16(L)F1704/8

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DS40001715D-page 438  2013-2015 Microchip Technology Inc.

 PIC16(L)F1704/8

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http://www.microchip.com/packaging

 2013-2015 Microchip Technology Inc. DS40001715D-page 439

PIC16(L)F1704/8

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 2013-2015 Microchip Technology Inc. DS40001715D-page 441

PIC16(L)F1704/8

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

DS40001715D-page 442  2013-2015 Microchip Technology Inc.

 PIC16(L)F1704/8

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

 2013-2015 Microchip Technology Inc. DS40001715D-page 443

PIC16(L)F1704/8

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

DS40001715D-page 444  2013-2015 Microchip Technology Inc.

 PIC16(L)F1704/8

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

 2013-2015 Microchip Technology Inc. DS40001715D-page 445

PIC16(L)F1704/8

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 2013-2015 Microchip Technology Inc. DS40001715D-page 447

PIC16(L)F1704/8
APPENDIX A: DATA SHEET
REVISION HISTORY

Revision A (07/2013)
Initial release.

Revision B (09/2013)
Moved Note 1 from Table 3-10 to Table 3-9; Register
4-2, Removed overbar from bit 7; Table 8-1, removed
IOCBF, IOCBN, IOCBP; Register 12-3, revised bit 4-0;
Revised Table 32-1, Param. D003; Revised Table 32-2,
added Note 5 to D015, revised Note 5; Revised Table
32-7, OS03 Min.; Revised Table 32-17, OPA06, Min.;
Revised Register 21-1, bit 6 description.

Revision C (03/2015)
Updated data sheet to Final status; Updated Sections
3.4.2, 8.2.2, 18.1.1, 20.1.2, 20.1.3, 21.1, 21.1.1, 22.3,
28.2.1, 29.4.2, 32.0 (“Electrical Specifications”) and
33.0 (“DC and AC Characteristics Graphs and Charts”);
Updated introductory paragraph of Section 21.0;
Added Sections 3.2 (“High-Endurance Flash”) and 14.3
(“FVR Buffer Stabilization Period”); Updated Tables 1,
2, 1-2, 6-1, 17-3, 19-1 and 20-3; Updated legend in
Table 12-1; Updated note references and bit 2 of
ADCON1 register in Table 3-10; Updated Figures 6-7,
14-1, 16-2, 18-2 through 18-6, 20-1, 21-1, 22-1, 25-1;
Updated Registers 18-6, 18-7, 18-9, 20-1, 20-2, 21-1,
25-1; Other minor corrections.

Revision D (10/2015)
Added High-Endurance Flash Data Memory (HEF)
bullet and updated XLP Features for consistency on
front page. Added Section 6.3.5: Clock Switching
Before Sleep.
Updated PIC16(L)F170x Family Types Table. Updated
Example 20-1; Section 20.2.6; and Tables 1-2 and
32-11.

DS40001715D-page 448  2013-2015 Microchip Technology Inc.

 PIC16(L)F1704/8
THE MICROCHIP WEB SITE CUSTOMER SUPPORT
Microchip provides online support via our web site at Users of Microchip products can receive assistance
www.microchip.com. This web site is used as a means through several channels:
to make files and information easily available to • Distributor or Representative
customers. Accessible by using your favorite Internet
• Local Sales Office
browser, the web site contains the following
information: • Field Application Engineer (FAE)
• Technical Support
• Product Support – Data sheets and errata,
application notes and sample programs, design Customers should contact their distributor,
resources, user’s guides and hardware support representative or Field Application Engineer (FAE) for
documents, latest software releases and archived support. Local sales offices are also available to help
software customers. A listing of sales offices and locations is
• General Technical Support – Frequently Asked included in the back of this document.
Questions (FAQ), technical support requests, Technical support is available through the web site
online discussion groups, Microchip consultant at: http://www.microchip.com/support
program member listing
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.

 2013-2015 Microchip Technology Inc. DS40001715D-page 449

PIC16(L)F1704/8
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. [X](1) - X /XX XXX
Examples:
Device Tape and Reel Temperature Package Pattern a) PIC16LF1704- I/P
Option Range Industrial temperature
PDIP package
b) PIC16F1708- E/SS
Extended temperature,
Device: PIC16F1704, PIC16LF1704, SSOP package
PIC16F1708, PIC16LF1708

Tape and Reel Blank = Standard packaging (tube or tray)

Option: T = Tape and Reel(1)

Temperature I = -40C to +85C (Industrial)

Range: E = -40C to +125C (Extended)

Package:(2) ML = QFN
P = PDIP Note 1: Tape and Reel identifier only appears in
SP = SPDIP the catalog part number description. This
ST = TSSOP identifier is used for ordering purposes and
SL = SOIC
SO = SOIC is not printed on the device package.
SS = SSOP Check with your Microchip Sales Office
for package availability with the Tape and
Reel option.
Pattern: QTP, SQTP, Code or Special Requirements 2: Small form-factor packaging options may
(blank otherwise) be available. Please check
www.microchip.com/packaging for
small-form factor package availability, or
contact your local Sales Office.

DS40001715D-page 450  2013-2015 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC,
and may be superseded by updates. It is your responsibility to
FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,
ensure that your application meets with your specifications. LANCheck, MediaLB, MOST, MOST logo, MPLAB,
MICROCHIP MAKES NO REPRESENTATIONS OR OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC,
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
SST, SST Logo, SuperFlash and UNI/O are registered
IMPLIED, WRITTEN OR ORAL, STATUTORY OR trademarks of Microchip Technology Incorporated in the
OTHERWISE, RELATED TO THE INFORMATION, U.S.A. and other countries.
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR The Embedded Control Solutions Company and mTouch are
FITNESS FOR PURPOSE. Microchip disclaims all liability registered trademarks of Microchip Technology Incorporated
arising from this information and its use. Use of Microchip in the U.S.A.
devices in life support and/or safety applications is entirely at Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,
the buyer’s risk, and the buyer agrees to defend, indemnify and CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit
hold harmless Microchip from any and all damages, claims, Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,
suits, or expenses resulting from such use. No licenses are KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB
conveyed, implicitly or otherwise, under any Microchip Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
intellectual property rights unless otherwise stated. Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O,
Total Endurance, TSHARC, USBCheck, VariSense,
ViewSpan, WiperLock, Wireless DNA, and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2013-2015, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
ISBN: 978-1-63277-888-8

QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures

== ISO/TS 16949 ==
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

 2013-2015 Microchip Technology Inc. DS40001715D-page 451

 Worldwide Sales and Service
AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE
Corporate Office Asia Pacific Office China - Xiamen Austria - Wels
2355 West Chandler Blvd. Suites 3707-14, 37th Floor Tel: 86-592-2388138 Tel: 43-7242-2244-39
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Tel: 480-792-7200 Harbour City, Kowloon China - Zhuhai Denmark - Copenhagen
Fax: 480-792-7277 Hong Kong Tel: 86-756-3210040 Tel: 45-4450-2828
Technical Support: Tel: 852-2943-5100 Fax: 86-756-3210049 Fax: 45-4485-2829
http://www.microchip.com/ Fax: 852-2401-3431 India - Bangalore France - Paris
support Tel: 91-80-3090-4444 Tel: 33-1-69-53-63-20
Australia - Sydney
Web Address:
Tel: 61-2-9868-6733 Fax: 91-80-3090-4123 Fax: 33-1-69-30-90-79
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Atlanta China - Beijing Tel: 91-11-4160-8631 Tel: 49-2129-3766400
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Tel: 678-957-9614 Germany - Munich
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New York, NY
Tel: 631-435-6000 China - Xian Tel: 886-2-2508-8600
Tel: 86-29-8833-7252 Fax: 886-2-2508-0102
San Jose, CA
Tel: 408-735-9110 Fax: 86-29-8833-7256 Thailand - Bangkok
Tel: 66-2-694-1351
Canada - Toronto
Tel: 905-673-0699 Fax: 66-2-694-1350
Fax: 905-673-6509
01/27/15

DS40001715D-page 452  2013-2015 Microchip Technology Inc.