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EECS151/251A
Introduction to Digital Design and ICs
Lecture 14: Inverter Delay Sophia Shao
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Shao Fall 2022 © UCB

Review
• CMOS Transistors and Gates
• CMOS Transistors
• MOS Transistor as a Switch
• NMOS & PMOS
• CMOS Gates
• Inverter
• Complex Gates

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 • Inverter Delay
• Overview
• Inverter RC Delay
• Inverter Size
• Inverter Chain

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Processor Frequency Scaling

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Delay Optimization
• Critical paths limit the operating speed of the system.
• Four main levels:
• Architectural/Microarchitectural Level, e.g., # of pipeline stages
• Logic Level, e.g., types of functional blocks
• Circuit Level, e.g., transistor sizings
• Layout Level, e.g., floorplanning

• This lecture: using simple models that offer designers intuitions on logic and
circuit optimizations.
• Invertor RC delay model: transistor -> resistor + capacitor
• Transistor Sizing & Logical effort (next lecture)
• Generalize to other gates (next lecture)

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 • Inverter Delay
• Overview
• Inverter RC Delay
• Inverter Size
• Inverter Chain

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 Inverter Delay: High-to-low
In Out
VDD
Vin
VDD
Req,p

In Out 0
Cp + CL
Req,n Vout "t
VDD Vout=𝑉!! e τ
VDD/2

Out
0 tp

Cp + CL τ = Req,n(Cp+CL)
Req,n

In
tp,HL= (ln2)τ = 0.7 Req,n(Cp+CL)

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 Inverter Delay: Low-to-high
In Out VDD

Vin
VDD
Req,p

In Out
0
Cp + CL
Req,n "t
Vout Vout=VDD(1−e τ )
VDD

VDD/2
VDD

In 0 tp

Req,p
tp,LH= (ln2)τ = 0.7 Req,p(Cp+CL)
Out

Cp + CL

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 Equivalent Resistances
Req (VGS=VDD, VDS=VDD/2)
• Transistor IDS-VDS trajectory
IDS VGS= VDD
• Averaging produces Req
Req (VGS=VDD, VDS=VD
Out
Vin
Cp + CL VDD
Req,n
VGS= 0

VDD V
0 VDD/2 DS
t
IDS

0
Vout t
VDD
VDD/2

t
9
0
EECS151 L14 INVERTER DELAY
tp
Shao Fall 2022 © UCB
 Equivalent Resistances Req (VGS=VDD, VDS=VDD/2)

• Transistor IDS-VDS trajectory IDS VGS= VDD

• Averaging produces Req Req (VGS=VDD, VDS=VDD)

Out
Vin
Cp + CL VDD VGS= 0
Req,n
VDD V
VDD/2 DS
0
t
IDS

0
Vout t Req = (Req,start + Req,mid)/2
VDD
VDD/2

t
10
0
EECS151 L14 INVERTER DELAY
tp
Shao Fall 2022 © UCB
 Impact of Rise/Fall times
• Impacts the IDS-VDS trajectory
Out
Vin
VGS
Cp + CL VDD IDS
Req,n

0
t
IDS
VDS
0
Vout t
VDD
tp (tr)
VDD/2

t
0 tp (tr=0)

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 Impact of Rise/Fall times
• Impacts the IDS-VDS trajectory
Out
Vin
VGS
Cp + CL VDD IDS
Req,n

0
t
IDS
VDS
0
Vout t
VDD
tp (tr)
VDD/2

t
0 t (tr=0)
p

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 Quiz: Inverter RC Delay
• If we double the load capacitance, assuming the default Vout shown in blue,
which of the following waveforms shows the new Vout?
Vout
Out VDD

Req,n
Cp + CL Vin A VDD/2
0
VDD tp
Vout
0 VDD
B VDD/2
Vout
VDD 0 tp
VDD/2 Vout
VDD
0 tp C VDD/2
0
13 EECS151 L14 INVERTER DELAY
tp
Shao Fall 2022 © UCB
 • Inverter Delay
• Overview
• Inverter RC Delay
• Inverter Size
• Inverter Chain

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Capacitances
VDD

INVX1
• Cin (input capacitance)
M2 Wp • Largely set by the gate cap Cg ~ WL
A Out • Inverter: Cin= Cg,pmos + Cg,nmos
Cp • (W -> 2W) => 2xCin
Cin M1 Wn

Source (S)
Gate (G)
Drain (D)
INVX2 • Cp (parasitic capacitance)
• Largely set by the drain cap Cd ~W
(drain area/perimeter)
L • Inverter: Cp= Cd,pmos + Cd,nmos
• (W -> 2W) => 2xCp
W
• Cd = gCg (g =1)
• Inverter: Cp = gCin
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Inverter Sizing
• A size “2” inverter:
• Wp,inv_x2 = 2 * Wp,inv_x1
• Wn,inv_x2 = 2 * Wn,inv_x1

• Doubling the gate size (by doubling Ws):

VDD
• Doubles Cin
Wp
A
M2
Out
• Doubles Cp
!
• Halves equivalent gate resistance R = 𝜌 "#
M1 Wn • Delivers 2x current to flow
Cp
Cin

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Inverter Wp vs Wn
• Optimal Wp/Wn to have the same low-to-high and high-to-low delays.
Vout
VDD VDD
VDD
VDD/2

Wp Req,p
M2 0 tp
A Out Out
Vout
Req,n VDD
M1 Wn
VDD/2

0 tp

!
• In the past, to have equal resistance, 𝜌! > 𝜌" , Wp > Wn R = 𝜌
"#
• In modern processes (FinFET), 𝜌! = 𝜌" , Wp = Wn
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 Inverter RC Delay
VDD

Req, Cp Req,p
In Out
In Out
Cp + CL
Req,n
CL

• tp = ln2 * Req(Cp + CL)

• Parasitic/Intrinsic delay: ln2* ReqCp

• tp = ln2 * Req (g Cin + CL) = ln2 * ReqCin(g +CL/Cin)

• g=1

• tp = tINV(1+f) Normalized Delay to tINV

• tINV= ln2 * ReqCin D (inv) = tp /tINV = 1 + f

• tINV is independent of transistor sizes.

Parasitic delay Effort delay
• Fanout = f = CL/Cin

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Quiz: Inverter Delay
• How does the inverter delay change if the widths of both PMOS and NMOS
of the inverter are doubled? VDD

• tp = ln2 * ReqCin(1+CL/Cin) = tINV(1+f)

M2 Wp
• f = fanout = CL/Cin
A Out

CL
A: tp,inv_x2 > tp,inv_x1 M1
Wn
B: tp,inv_x2 < tp,inv_x1 Cp
Cin
C: tp,inv_x2 = tp,inv_x1

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Administrivia
• No new Lab this week.
• Continue working on lab4/5.

• FPGA will start project next week.

• ASIC will start lab 6 next week.
• New HW out this week.

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 • Inverter Delay
• Overview
• Inverter RC Delay
• Inverter Size
• Inverter Chain

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 Inverter Chain

In Out

D=1+f
CL
1 2 N

• CL,i = Cin,i+1 (the load of the i-th stage is the input capacitance of the next stage.)
• N: # of inverters in the chains
• Cin,1 =1
• Given N and CL , how to size each inverter in the chain to achieve minimum
delay?

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 Inverter Chain

In Out

D=1+f
CL
1 2 N

• Path Delay = tp1 + tp2 + … +tpN

= (1+f1) + (1+f2) + … +(1+fN)
• f1= Cin,2/Cin,1, f2 = Cin,3/Cin,2 , …

• Path Fanout = CL/Cin,1 = f1 f2 … fN

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Minimizing the delay of an inverter chain

In Out

D=1+f
CL
1 2 N

• Delay is minimized when each stage • Delay = tp1 + tp2 + … +tpN

has the same delay. = (1+f1) + (1+f2) + … +(1+fN)

• !
f= 𝐹 = !
𝐶! /𝐶"#,% • f1= Cin,2/Cin,1, f2 = Cin,3/Cin,2 , …
• Minimum path delay: • Path Fanout F = CL/Cin,1 = f1 f2 … fN
• D = (1+f1) + (1+f2) + … +(1+fN)
𝑵
= Nf + N = N 𝑭 +N

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Example: Minimizing the delay of an inverter chain

In Out

CL
1 2 N
• Delay is minimized when each
stage has the same fanout.
• N = 3, CL = 8, C in,1 =1
• !
f= 𝐹 = !
𝐶! /𝐶"#,%
• To minimize the delay, CL/Cin,1 has to be evenly
distributed across N=3 stages. • Minimum path delay:
• #
f= 8 =2 • D = Nf + N = N
𝑵
𝑭 +N
• Recall f1= Cin,2/Cin,1, f2 = Cin,3/Cin,2 , f3= CL/Cin,3
• Size inverters from the back
• Cin,3 = CL/ f3 =8/2 = 4
• Cin,2 = Cin,3/ f2 =4/2 = 2

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Example: Minimizing the delay of an inverter chain

In Out

CL
1 2 N
• Delay is minimized when each
stage has the same fanout.
• N = 3, CL = 8, C in,1 =1
• !
f= 𝐹 = !
𝐶! /𝐶"#,%
• To minimize the delay, CL/Cin,1 has to be evenly
distributed across N=3 stages. • Minimum path delay:
• #
f= 8 =2 • D = Nf + N = N
𝑵
𝑭 +N
• Recall f1= Cin,2/Cin,1, f2 = Cin,3/Cin,2 , f3= CL/Cin,3
• Size inverters from the back
• Cin,3 = CL/ f3 =8/2 = 4
• Cin,2 = Cin,3/ f2 =4/2 = 2

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Example: Best Number of Stages
• How many stages should a path use?
• Minimizing number of stages is not always fastest

• Example: drive 64-unit load with inverters Initial Driver 1 1 1 1

8 4 2.8
D = NF1/N + N
16 8
= N(64)1/N + N
23

Datapath Load 64 64 64 64

N: 1 2 3 4
f: 64 8 4 2.8
D: 65 18 15 15.3
Fastest

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Example: Best Number of Stages
• How many stages should a path use?
• Minimizing number of stages is not always fastest

• Example: drive 64-unit load with inverters Initial Driver 1 1 1 1

8 4 2.8
D = NF1/N + N
16 8
= N(64)1/N + N
23

Datapath Load 64 64 64 64

N: 1 2 3 4
f: 64 8 4 2.8
D: 65 18 15 15.3
Fastest

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Quiz: Inverter Chain
• If we increase the load from 64 to 256,Initial
which
Driver of the
1 following
1 1 1

choices will have the smallest delay?

8 4 2.8

• A. Remove the size 16 inverter. 16 8

• B. Add a size 64 inverter.

23
• C. Do nothing.
Datapath Load 64 64 64 256
64

N: 1 2 3 4
f: 64 8 4 2.8
D: 65 18 15 15.3
Fastest

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Inverter and Inverter Chain Recap
• Inverter Delay
• tp = ln2 * ReqCin(1+CL/Cin) = tINV(1+f)
• tINV= ln2 * ReqCin
• Fanout = f = CL/Cin
• Normalized Delay to tINV
• D (inv) = 1 + f
Parasitic delay Effort delay
• Inverter Chain
• Path Delay 𝐷𝑒𝑙𝑎𝑦 = ∑ 1 + 𝑓" = 𝑁 + ∑ 𝑓𝑖
• Path Fanout Effort 𝐹 = ∏ 𝑓" = 𝐶! /𝐶"#,%
• Size the inverters to minimize the delay of an inverter chain
• Every inverter stage has the same effort delay, i.e., 𝑓" = 𝐹
!

• The size of each inverter stage can be determined by working backward

+&,'
• 𝐶(),( = ,'

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Review
• CMOS Transistors and Gates
• MOS transistor as a switch
• Pull-up and Pull-down for CMOS design
• CMOS Gates

• Inverter Delay
• Delay affects achievable frequency.
• Propagation delay from input to output
• RC Delay model

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