EE292A

Electronic Design Automation (EDA) and

Machine Learning Hardware

Raúl Camposano Antun Domic Patrick Groeneveld

Silvaco and Silicon Catalyst Kepler AMD
[email protected] [email protected] [email protected]
Copyright ©2024 by Raúl Camposano, Antun Domic and Patrick Groeneveld
Outline
• Course Overview
• Goals
• Introductions
• Administrative stuff: Logistics, schedule,
labs, grading
• What you will learn, design methodology,
digital and a bit of analog
• Syllabus

• The Lab: Designing an ARC 605LE core

• Integrated Circuits and Machine Learning
Hardware in the wild
• History, enablers and future trends

April 2, 2024 Stanford EE292A Lecture 1 2

“It seems probable that
once the machine thinking
method had started, it
would not take long to
outstrip our feeble
powers…”

Alan Turing, 1912-1954

Mathematician, computer scientist,

logician, cryptanalyst, philosopher, and theoretical
biologist
EE292A Course Overview
Goals
A state-of-the art “chip” (integrated circuit, die) consists of up to tens of
billions of transistors. These are designed using Electronic Design
Automation (EDA) tools. In this course you will
• understand the inner workings of key EDA tools and
• how to use them effectively to design digital hardware; you will design
a Synopsys ARC 605LE Processor core
• Hands-on encounter with production tools of Cadence, Synopsys and
Siemens

April 4, 2024 Stanford EE292A Lecture 1 4

Course Logistics
• 19 Lectures
• Tuesdays and Thursdays, 10:30-11:50
• In person, no Zoom. April 2 – June 1
• 3 Lecturers
• Raúl Camposano
[email protected]
• Antun Domic
[email protected]
• Patrick Groeneveld
[email protected]
• 1 TA
• Nicole Heflin
[email protected]

April 2, 2024 Stanford EE292A Lecture 1 5

 Course Logistics (continued)
• Canvas: Course/Lab Notes
• Pdfs posted before each class
• Ed: Q&A, General communication
• Update: We moved from Piazza to Ed
• Office hours:
• After each in-person class, or anytime on request
• Homework: Canvas
• Homework assignment most weeks
• 4 lab assignments (more later)
• Grading: Your choice of letter grade or credit/no-credit
• 50% homework
• 30% lab
• 20% final lab project

April 2, 2024 Stanford EE292A Lecture 1 6

Syllabus
Lecture 1 Introduction, Semiconductor impact, Machine Learning Hardware
Lecture 2 From TensorFlow to Machine Learning Hardware: real-life implementation flows
Lecture 3 Design Abstractions, The Digital Design Flow
Lecture 4 The Verification Flow
Lecture 5 High Level Synthesis, HLS Overview, Scheduling
Lecture 6 High Level Synthesis, Scheduling II
Lecture 7 High-Level Synthesis, Allocation
Lecture 8 Logic Synthesis I: Basics
Lecture 9 Logic Synthesis II: More Basics
Lecture 10 Logic Synthesis III: Multi-Level Synthesis, Mapping
Lecture 11 Graph Representations
Lecture 12 Timing and Power: Circuit Abstractions for Cells
Lecture 13 Timing models, cells and interconnect
Lecture 14 Physical Foundation and Standard cells
Lecture 15 Floorplanning
Lecture 16 Placement
Lecture 17 Detailed placement and path search
Lecture 18 Routing and Physical Synthesis
Lecture 19 The Electronic Design Automation Industry in the context of the Semiconductor Industry
April 2, 2024 Stanford EE292A Lecture 1 7
 Student
Introductions

• Your name
• What you do (e.g. 3rd yr EE)
• What interests you in this course
• (optional) Fun fact about yourself
• E.g. play the bass in a band

April 2, 2024 Stanford EE292A Lecture 1 8

Outline
• Course Overview
• Goals
• Introductions
• Administrative stuff: Logistics, schedule, labs,
grading
• What you will learn, design methodology,
digital and a bit of analog
• Syllabus

• The Lab: Designing an ARC 605LE core

• Integrated Circuits and Machine Learning Hardware
in the wild
• History, enablers and future trends
April 2, 2024 Stanford EE292A Lecture 1 9
Labs (Nicole)

• A state-of-the-art processor core, Synopsys’

DesignWare® ARC® 605LE
• A 32-bit microprocessor
• Gate count of around 35K
• Used in deeply embedded applications where
small size, low power and 32-bit performance is
required.
• 4 Labs Total
• Lab 1 à Intro to design compiler tool &
mflowgen
• Lab 2 à Explore different compile options
• Lab 3 à Explore different technology nodes
• Lab 4 à Put everything together to achieve an
optimized design
• Synthesis takes a while to run (~30 min to 1 hr), start
labs early!

March 31, 2024 Stanford EE292A Lecture 1 10

Lab Schedule

Release Date Due Date Time Weight

Lab1 Thursday, April 4, 2024 Thursday, April 18, 2024 2 weeks 10

Lab2 Thursday, April 18, 2024 Thursday, May 2, 2024 2 weeks 10

Lab3 Thursday, May 2, 2024 Thursday, May 16, 2024 2 weeks 10

Final Lab Thursday, May 16, 2024 Tuesday, June 4, 2024 2.5 weeks 20

March 31, 2024 Stanford EE292A Lecture 1 11

Lab Logistics
• Office Hours: TBD via Zoom (see Canvas for link)
• Post questions on Ed
• Email: [email protected]

• Max 2 people/group
• Submit on Canvas (1 submission/group)
• Fill out partner form by Thursday April 11th
https://tinyurl.com/hhwnr4wb

March 31, 2024 Stanford EE292A Lecture 1 12

 Mflowgen Tool Flow Graph
design.vcs.v

design.v design.spef.gz Timing Signoff

RTL design.pt.sdc
SNPS PrimeTime
pdk

design.v
constraints.tcl Synthesis design.sdc
Place & Route
pdk
DRC
CONSTRAINTS

SNPS-DC pdk Cadence-Innovus design.gds Open Magic

pdk design.lvs.v LVS

PDK
pdk
Mentor Calibre

April 2, 2024 Stanford EE292A Lecture 1 13

 constraints rtl skywater-130nm info

constraints.tcl design.v adk

adk constraints.tcl design.upf design.v run.saif

synopsys-dc-synthesis

design.namemap design.sdc design.svf design.upf design.v

adk design.sdc design.v

cadence-innovus-flowsetup

innovus-foundation-flow

adk design.sdc design.v innovus-foundation-flow

cadence-innovus-init

design.checkpoint

adk design.checkpoint design.sdc innovus-foundation-flow

cadence-innovus-power

design.checkpoint

adk design.checkpoint design.sdc innovus-foundation-flow

cadence-innovus-place

design.checkpoint

adk design.checkpoint design.sdc innovus-foundation-flow

cadence-innovus-cts

design.checkpoint

adk design.checkpoint innovus-foundation-flow

cadence-innovus-postcts_hold

design.checkpoint

adk design.checkpoint innovus-foundation-flow

cadence-innovus-route

design.checkpoint

adk design.checkpoint innovus-foundation-flow

cadence-innovus-postroute

design.checkpoint

adk design.checkpoint innovus-foundation-flow

cadence-innovus-signoff

design-merged.gds design.checkpoint design.def.gz design.gds.gz design.lef design.lvs.v design.pt.sdc design.rcbest.spef.gz design.sdf design.spef.gz design.vcs.pg.v design.vcs.v design.virtuoso.v

adk design.pt.sdc design.spef.gz design.vcs.v adk design.gds.gz

synopsys-pt-timing-signoff mentor-calibre-gdsmerge

design.sdf design_merged.gds

adk design_merged.gds adk design_merged.gds adk design_merged.gds

open-magic-antenna open-magic-drc open-magic-gds2spice

antenna_check.log drc_results.log design_extracted.spice

adk design.lvs.v design_extracted.spice

mentor-calibre-comparison

lvs.report
 Outline
• Course Overview
– Goals
– Introductions
– Administrative stuff: Logistics, schedule,
labs, grading
– What you will learn, design methodology,
digital and a bit of analog
– Syllabus

• The Lab: Designing an ARC 605LE core

• Integrated Circuits and Machine Learning
Hardware in the wild
– History, enablers and future trends

April 2, 2024 Stanford EE292A Lecture 1 15

Johannes Vermeer. View of Delft 1660
April 2, 2024 Stanford EE292A Lecture 1
17
 The Semiconductor Hardware Ecosystem
$500B/yr (smartphones)
+$500B/yr (others)

$580B/yr
Tooling Idea Components
Software Industry
PyTorch, CUDA Oracle, IBM,
Embedded software SalesForce,
Compiler, CUDAML, $200B/yr OpenAI, Adobe
ARM, Snps-ARC
Semiconductor IP Architecture Fabless Fab
RISC-V Semiconductor
Many AI Startups Industry Semicon.
Architectural synthesis ip ip
System Apple
System (C++/MLIR) ip nVidia Intel Amazon
High-level Synthesis Qualcomm Samsung Microsoft
Broadcom Google
Synopsys RTL (verilog) RTL NXP
Electronic Meta
Abstraction Level

Cadence AMD Tesla

Design Logic Synthesis
Siemens EDA Mediatek Facebook
$14 B/yr
Automation Circuit (gates) Circuit
Marvell Samsung
Industry ONSemi
Physical synthesis Cisco
Cerebras
Mask (transistors) Mask Physical

ASML Mask fabrication

Applied Materials Semiconductor IC Fab (silicon) TSMC, Samsung
$150B/yr
KLA, LAM Equipment GlobalFoundries
Wafer
Tokyo Electron. Industry UMC
$20 B/yr
Package (chips)
Chip
Jabil PCB Equipment TTM, Compeq,
Würth $5 B/yr Printed Circuit Board $75B/yr
Industry AT&S, Rayming
TTM Board
Factory Automation Foxconn,
Hardware Assembly Flextronics,
Equipment
Consumer product
 Major Abstraction Levels in Microelectronic Design
C++/Tensorflow/PyTorch

Architectural Synthesis ip ip
System
ip
High Level Synthesis

RTL

Logic Synthesis
Circuit

Physical Synthesis (Place and Route)

Mask Physical

Chip tapeout, sent to IC fab

 The Magic of Electronic Design Automation
Analysis (Verification) Specification (C++, MLIR from PyTorch) Synthesis (Design)
IP blocks
ip ip
System
Formal Verification ip
Floor Planning, Design Space Exploration

RTL High Level Synthesis

Verilog Simulation

Logic Synthesis
HW and SW Emulation Circuit
Static Timing Analysis
Physical Synthesis
Analog Mixed-signal, Spice Mask Physical Place & Route Standard cell
Physical DRC, LVS Memory libraries

Yield optimization, OPC

20
wafer
 EDA: From Concept to Chip,
Fully Automated e
on cach
In stru c ti

Data cache

EDA Lo ad
-S tor
e Un
it

flow

Block Diagram of a RISC-V processor

Source: Florian Zaruba, ETH Zürich
https://riscv.org/wp-content/uploads/2018/05/14.15-14.40-FlorianZaruba_riscv_workshop-1.pdf
ASIC Layout
 EDA Industry: Semiconductor + Software
Company Employees Annual Sales Market value Major Locations

Synopsys ~16,000 $5.8B $88B Mountain View, Portland, India, China, Europe, Armenia, Chile

Cadence ~12,000 $4.0B $85B San Jose, India, China, Europe, Taiwan, Brazil

Siemens EDA (formerly Mentor) ~6,000 ~$2.2B ~$20B Portland, San Jose, India

Other EDA (Ansys, etc) ~20,000 ~$2B $10B Worldwide

Total EDA approx. ~54,000 ~$14B $203B Worldwide

Semiconductor companies

Software companies
EDA = 2.5% of EDA = 2.4% of
Semiconductors Software

22
Is there
The BigEvidence
Picture for the End of Moore’s Law?
discrete Bayraktar
components Reaper

Tomahawk

Sidewinder
V2
Custom Hardware
Norden Proximity for
Bomb Fuze Machine Learning
Sight High-resolution
CCD cameras

Custom Hardware
for
Micro Digital Spread Spectrum
Processor Communication

April 2, 2024 23 Stanford EE292A Lecture 1

Moore’s Law:
The Number of Transistors Doubles Every 2 Years

April 2, 2024 24 Stanford EE292A Lecture 1

Moore’s Law
Just in case someone has not seen it…. Moore’s Original graph

Rock’s Law
The cost of semiconductor chip
fabrication doubles every 4 years
(Arthur Rock, VC, 1965?)

“This fab could cost upwards of $20 billion

and represents TSMC’s commitment to drive
technology forward,” Co-Chief Executive
Mark Liu…

Source: Gordon E. Moore,

Cramming More Components onto Integrated Circuits,
Electronics, pp. 114–117, April 19, 1965.

April 2, 2024 Stanford EE292A Lecture 1 25

 The Trends Before Moore’s Law
Apollo Guidance Computer

Source: Gordon E. Moore,

Cramming More Components onto Integrated Circuits,
Electronics, pp. 114–117, April 19, 1965.

26
Lithography

DUV 193nm -> EUV 13.5nm wavelength

…and each unit has a starting price of $400M

April 2, 2024 Stanford EE292A Lecture 1 27
IC Manufacturing: Transport of an EUV System

April 2, 2024 Stanford EE292A Lecture 1 28

The Center of Gravity Matters!

April 2, 2024 Stanford EE292A Lecture 1 29

What Electronic Design Automation can do
(..and Mechanical Design Automation can’t)

IC

• 10,000,000,000 transistors • 4,000,000 parts 0.0005x

• Development cost: $50M • Development cost: $20B 400x
• Development time: < 1 year • Development time: 10 years 10x
• Development team size: 100 • Development team size: 10,000 100x
• EDA software: ~$14B/year • MCAD software: ~$12B/year
April 2, 2024 Stanford EE292A Lecture 1 30
 Moore’s Law and the
Design Automation Conference

April 2, 2024 Stanford EE292A Lecture 1 31

 60 Years of Relentless Scaling
1964 Historic 2024 Today

Cerebras CS-2: 2.4T

5.3T
2.4T

92B 137B
40B 80B
16B
Transistor Count [log scale]

68K

2K

Largest Flash: 5.3T

32
 Microelectronics: Mindboggling Scale
1964 Historic 2024 Today

5.3T
2.4T 2.4T
190B
92B 137B 80B 100B
40B 80B
16B 7B 10B 13B
Transistor Count [log scale]

40M
8.9M

68K 100K
10K
2K

s
ar
st
e
bl
V isi

33
 Imagine:
If the Wires on a 5nm Mobile SoC
were as wide as 2-lane Roads…
IC Wire pitch at 3nm: 28nm
2-lane Road width: 10m (30feet)
Scaling factor = 393Million

Scaled up, the wire is a road. The USA contains

The A16 Chip (iPhone 14) contains: 2.7 million miles of
~14 million miles paved roads in 1 layer.
wires in 13 layers. Connecting
Connecting 0.31 Billion people
~16 Billion transistors 0.26 Billion cars
~1.2 Billion standard cells 0.14 Billion homes
Consumes ~2 GigaWatt Consumes ~400 GigaWatt

2560miles/4100km 34
 Moore’s Law Ending?

March 28, 2022 Stanford EE292A Lecture 1 35

13 Generations of Apple Mobile System-on-Chips
Chip A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16
Year 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022
Device iPhone iPhone iPhone iPhone iPhone iPhone iPhone iPhone iPhone iPhone iPhone iPhone iPhone
4 4s 5 5s 6 6s 7 8&X Xs 11 12 13 14

Node 45nm 45nm 32nm 28nm 20nm 16nm 16nm 10nm ‘7’nm 7nm 5nm 5nm 4nm
Samsung Samsung Samsung Samsung TSMC TSMC TSMC TSMC TSMC TSMC TSMC TSMC TSMC
Area 0.52 1.25 0.96 1.03 0.89 1.05 1.25 0.88 0.83 0.98 0.88 1.08 1.14
[cm2]

Die photos: 36
chipworks/TechInsights/Angstonomics
Data source: wikipedia
2010

iPhone 4

45nm Samsung

A4 SoC

Die photos:
chipworks/TechInsights/Angstonomics
Data source: wikipedia
2011

iPhone 4s

45nm Samsung

A5 SoC

Die photos:
chipworks/TechInsights/Angstonomics
Data source: wikipedia
2012

iPhone 5

32nm Samsung

A6 SoC

Die photos:
chipworks/TechInsights/Angstonomics
Data source: wikipedia
2013

iPhone 5s

28nm Samsung

A7 SoC

Die photos:
chipworks/TechInsights/Angstonomics
Data source: wikipedia
2014

iPhone 6

20nm TSMC

A8 SoC

Die photos:
chipworks/TechInsights/Angstonomics
Data source: wikipedia
2015

iPhone 6s

16nm TSMC

A9 SoC

Die photos:
chipworks/TechInsights/Angstonomics
Data source: wikipedia
2016

iPhone 7

16nm TSMC

A10 SoC

Die photos:
chipworks/TechInsights/Angstonomics
Data source: wikipedia
2017

iPhone X & 8

10nm TSMC

A11 SoC

A11 SoC

Die photos:
chipworks/TechInsights/Angstonomics
Data source: wikipedia
2018

iPhone Xs

‘7’nm TSMC

A12 SoC

A12 SoC

Die photos:
chipworks/TechInsights/Angstonomics
Data source: wikipedia
2019

iPhone 11

7nm TSMC

A13 SoC

A13 SoC

Die photos:
chipworks/TechInsights/Angstonomics
Data source: wikipedia
2020

iPhone 12

5nm TSMC

A14 SoC

Die photos:
chipworks/TechInsights/Angstonomics
Data source: wikipedia
2021

iPhone 13

5nm TSMC

A15 SoC

Die photos: Data source: wikipedia

chipworks/TechInsights/Angstonomics
2022

iPhone 14

4nm TSMC

A16 SoC

Die photos: Data source: wikipedia

chipworks/TechInsights/Angstonomi
cs
50X
Die photos: Data source: wikipedia
chipworks/TechInsights/Angstonomi
cs
Automotive Progress vs SoC Progress, Same Period
1.2X
2010 2023 2010
50X
2010 2023
16B
15B

12B

8B
7B

4B

1B

51
 Claasen’s Law

a smartphone

Technology Scale
Usefulness of

Usefulness
sistors
Tran

52
Like Sand onasthe
Numerous Beach
Sand on the Beach…

1000 BCE / Bible, Genesis 22 verse 17:

I will surely bless you and make your descendants as
numerous as the stars in the sky and as the sand on the
seashore

1980 CE / Carl Sagan, Cosmos:

There are more stars in the universe than there are
grains of sand on all the beaches of Earth

2024 CE / Some dude (Brady Booch) on Twitter:

There are more transistors on earth than grains of sand
on all the beaches of Earth
April 4, 2023 Stanford EE292A Lecture 1 53
Sand as a Parable for MOS Transistors
 Sand as a Parable for MOS Transistors
Water

Grain of sand

pressure

g
s d

current
 Beach Sand or Stars: Which is Greater?
• There are ~ 𝟔 ∗ 𝟏𝟎𝟐𝟏 (6 sextillion) grains of sand on beaches
• Sand is grains of mainly 𝑆𝑖𝑂! , typically 0.5mm diameter. 0.19mm2
-> a cubic meter of sand contains ~8B grains
• Assuming a beach is 200 meter wide and sand layer is 20 meters
deep, then one km of beach has 1000 * 200 * 20 * 8B grains Room for
= 3.2 ∗ 10"# grains per km of beach. 0.5mm ~39,000,000
• The world has 620,000 km of coastline, of which 31% is sandy Transistors in 5nm
(Source: NASA)
• There are between 𝟏𝟎𝟐𝟐 and 𝟏𝟎𝟐𝟒 stars in the universe
• Between 10"" (100B) and 10"! (1T) stars per galaxy
• Between 10"" and 10"! galaxies in the universe (source: ESA)
10!! − 10!"

10!! − 10!"
56
NASA/Hubble
How many Transistors are “Alive” in the World?
• Approx. 8 ∗ 10$% in 2023 based on number of 12” wafers :
• TSMC made 13M wafers, most in dense technologies of ~3T transistors/wafer = 2.9 ∗ 10"$ .
They have ~40% of the market.
• Approx. 72M raw 12-inch wafers were produced in 2022 @ ~1T transistors per wafer
• Approx. 1.8 ∗ 10&$ in 2023 alone based on NAND FLASH memory market data:
• Flash memory market was ~$70B in 2023
• at $100/Terabyte means that ~700M TB were produced = 1.8 ∗ 10!" Transistors
(assuming 2.6 ∗ 10"! transistors per TB = 6 bits per cell)
• With average product life of 3 years, we have 𝟔 ∗ 𝟏𝟎𝟐𝟏 transistors running, most
of them as memory

• Conclusions:
• There are approximately as many transistors as grains of sand on all beaches in the world
57
• There are still more stars than transistors in the universe
 Astronomical Number
of Transistors
Today’s big chips
Transistor Count [log scale]

s
ar
st
e
bl
V isi
 Electronic Design Automation
at Astronomical Scale

• EDA design methodologies

still pull it off , somehow

• How?
• Successful algorithms that we’ll
address in this course
• Gradual transition through abstraction level
• Strict verification

• Next steps:
• Harness Machine Learning
.. And gen-AI
Summary
• Hardware is very exciting (again)!
To design good HW you need to understand the
tools that do it – EDA

• Dozens synthesis and verification tools are employed to design

state-of-the-art integrated circuits

• The scale of chips is astronomical, quite literally

• You will use EDA to design a state-of-the-art processor core

April 2, 2024 Stanford EE292A Lecture 1 60

References
1. Gordon E. Moore, Cramming More Components onto Integrated Circuits, Electronics, pp. 114–117, April 19, 1965
2. R.H. Dennard, F. Gaensslen,, H.N. Yu, L. Rideout, E. Bassous, A. LeBlanc, Design of ion-implanted MOSFET's with very small
physical dimensions, IEEE Journal of Solid-State Circuits, October 1974
3. Ricardo Gonzalez, Benjamin M. Gordon, and Mark A. Horowitz, Supply and Threshold Voltage Scaling for Low Power CMOS;
IEEE Journal of Solid State Circuits, Vol. 32, No. 8, August 1997
4. F. Maloberty, A.C. Davies, A short History of Circuits and Systems, River Publishers, 2016
5. P. McLellan, EDAgraffiti, available at semiwiki.com, 2010
6. A. Sangiovanni-Vincentelli, The Tides of EDA, IEEE D&T of Computers, Nov-Dec 2003
7. http://www.cadhistory.net/toc.htm
8. Carl Sagan, Ann Druyan, Neil DeGrasse Tyson, ”Cosmos”, 1980, ISBN 978-0-345-53943-4
9. I. E. Sutherland, “Sketch pad a man-machine graphical communication system,” in Proceedings of the SHARE design
automation workshop, New York, NY, USA, Jan. 1964, p. 6.329-6.346. doi: 10.1145/800265.810742.
10. John L. Hennessy and David A. Patterson, A New Golden Age for Computer Architecture, Comm. ACM, February 2019
11. Integrated Circuits in the Apollo Guidance Computer http://klabs.org/history/history_docs/integrated_circuits/ic4-po.pdf
12. Tesla Autonomy Day https://www.youtube.com/watch?v=-b041NXGPZ8
April 2, 2024 Stanford EE292A Lecture 1 61
13. Jeff Hawkins. A Thousand Brains, Basic Books, 2021