Lecture 4

The Verifica+on Flow

Raúl Camposano
Silvaco and Silicon Catalyst
[email protected]

Copyright ©2024 by Raúl Camposano, Antun Domic and Patrick Groeneveld

“THE MAN OF SCIENCE HAS LEARNED TO BELIEVE IN
JUSTIFICATION. NOT BY FAITH. BUT BY VERIFICATION”
Thomas Henry Huxley
“Darwin’s Bulldog”
Outline
• Functional verification
• Electrical verification
• Physical verification
• Signoff

April 11, 2024 Stanford EE292A Lecture 18 3

Verification
C++/Tensorflow/PyTorch

ip ip
System
ip

HLS
Functional
Verification
RTL

Synthesis
Logic
Check
Equiv.
Electrical Circuit
Verification

Physical
Design
Extraction
LVS Mask Physical
Physical
Verification

SIGNOFF: Chip tapeout, sent to IC fab

April 11, 2024 Stanford EE292A Lecture 18 4
Func2onal Verifica2on

Design
, DUT
clk=0, reset=0, load=0, count=00
Results
Simulator
clk=1, reset=0, load=0, count=01
clk=0, reset=0, load=0, count=01
01000101010001111101010

e stb e n ch Functionality clk=1, reset=0, load=0, count=10

rst_l = 0; T clk=0, reset=0, load=0, count=10

clk = 1’b0;
count_input= 8’h0; out = 8’b0;
enable = 1’b1;
load = 1’b1;
count_input= 8’h0;
out = 8’b0;

• Designs are written in Verilog, SystemVerilog, SystemC, C++

• Functional testbenches are built in UVM (Universal Verification Methodology) [1]
• De facto standard methodology for functional design verification in the semiconductor industry
• Framework of SystemVerilog classes for creating modular, reusable testbench components
• Set of guidelines and best practices for developing testbenches
• Methodology for running simulations and analyzing results
• Testbenches are often generated by weighted random pattern generators

April 11, 2024 Stanford EE292A Lecture 18 5

System Level Simulation
• Essentially compiling and executing a formal language
• In IC design: SystemVerilog [2], SystemC [3]
• SystemVerilog
• Extension of Verilog, used in industry along with Verilog, numerous libraries
• Closer to HW, “lower level” than SystemC
• Better synthesis support, used for verification
• SystemC
• C++ plus Hardware modeling (concurrency, timing, signal, port, etc)
• “Higher level”, better for large systems
• Commercial tools
• Integrates better with SW, design environments (Visual C++)

April 11, 2024 Stanford EE292A Lecture 18 6

RTL Simulation
• Essentially compiling and executing a hardware
description language (HDL)
• HDL can model “Blocking”
z = t1 | t2 a

• Parallelism, concurrency, continuous t2 = ˜a & b

b
a
z

assignment, declarative language like t1 = a & ˜c c

Scala, Verilog
“Non-blocking”
• Sequential behavior, imperative / Always @(posedge clk)
procedural language like C, Java begin z

z <= t1 | t2 a
t2 <= ˜a & b b t2
t1 <= a & ˜c a
Verilog IEEE standard 1800-2012 c t1
VHDL IEEE standard 1076-2008
clk
April 11, 2024 Stanford EE292A Lecture 18 7
Main Simulation Approaches
Approx. achievable speed
• Simulation
102Hz
• HW acceleration
• Runs simulator in special purpose HW
• Testbench on computer or HW 104Hz
• Emulation
• Emulating a design on a special purpose 106Hz
emulation system, typically FPGA based
• Requires “synthesis” to the target system
• FPGA prototype
108Hz

April 11, 2024 Stanford EE292A Lecture 18 8

Formal Verification
• Equivalence checking of combinational circuits Design 1 a

Are two designs the same? f(X) = 0 X f(X)

• Methods used Design 2 b a 0
b 1
• Random simulation 0 0 1
• Binary Decision Diagrams (BDD) [4] 1 1 0
• Satisfiability [5]
• In practice, also exploit structural similarity SAT f(X) ∃ 𝑥 ∈ 𝑋 | 𝑓 𝑥 = 1
𝐷𝑒𝑠𝑖𝑔𝑛1 ≠ 𝐷𝑒𝑠𝑖𝑔𝑛2

April 11, 2024 Stanford EE292A Lecture 18 9

Formal Verification
• Equivalence checking of Finite State Machines

State1
out1
Design 1
X1, X2, X3… f(X1, X2, X3…)

Design 2 out2

FSM1 and FSM2 are equivalent iff

State2

f = 0 for all valid input sequences X1, X2, X3…

April 11, 2024 Stanford EE292A Lecture 18 10

Equivalence Checking of FSM
• If the same state encoding is used, this simplifies to the
combinational equivalence of
• output function
• next state function
• Otherwise, difficult, e.g., sequential don’t cares, retiming, …
• Reachability analysis [6, 7]
• State space partitioning [8]

April 11, 2024 Stanford EE292A Lecture 18 11

Formal Verification
Property / model checking [9,10]
• A property always holds, e.g. if (request 0->1 && enable == 1) {
after 2 CYCLES acknowledge 1->0;
}
• Boils down to
• traversing a sequential system (FSM)
• check if a property, expressed in some temporal logic, holds
• Counter examples falsify indisputably
• “Proof” can run very long

April 11, 2024 Stanford EE292A Lecture 18 12

Other Things to Verify at a High Level
Memory Consistency
• Problem arises when there are mulXple processors accessing common memory
• Memory Consistency Model (MCM)
• Strict consistency. Strict consistency is the strongest consistency model. ...
• SequenFal consistency proposed by Lamport(1979). ...
• Causal consistency. ...
• Generate tests which are likely to expose bugs in MCM using a geneXc algorithm
with a special crossover funcXon [11]
More examples: Memory [12], Security[13], Trojans[14], Side Channel
Leakage[15], Single Bit Flips[16]…

April 11, 2024 Stanford EE292A Lecture 18 13

Electrical Verification

• SPICE: Simulation Program with Integrated Circuit Emphasis,

Berkeley 1973 [17,18]

G C L
Initial operating point
DC 1/R I=0 V=0
Linearize G Conductances
Transient 1/R I=C dV/dt I=1/L⎰Vdt
Solve G V = I V Voltages
I Currents AC 1/R I=jwCV I=V/jwL
Next t
V,I, controlled sources, mutual Inductors…
Kirchhoff
Nodal Analysis

April 11, 2024 Stanford EE292A Lecture 18 14

Circuit Simulation (aka Spice)
• Solved by Modified Nodal Analysis
• “Modified” to deal with voltage sources
b 𝑉𝑏 = 𝑉𝑎 + 𝑉𝑎𝑏
0 = $ 𝐼𝑎
Vab

0 = $ 𝐼𝑏
a

• DC and AC solve the matrix (sparse)

• Transient: Differential equations solution, nonlinearities
iteratively, e.g. Newton-Raphson
April 11, 2024 Stanford EE292A Lecture 18 15
Circuit Simulation (aka Spice)
• Kirchhoff’s laws ⇒ lumped elements
Signals are slow compared to EM waves, distances << wavelength
𝑑𝜙𝐵
𝑑𝑡
=0 No magnetic field density change in a closed path
𝑑𝑄
=0 No charge change at a node
𝑑𝑡

• Otherwise
• Distributed elements, transmission lines
• Electromagnetic solver

April 11, 2024 Stanford EE292A Lecture 18 16

Static Timing Analysis [19-21]
• In a synchronous design, find longest path Input a
c
Output
• Timing model for standard cells (delay, load)
a
a c
b
a

and for wires (RC)

a
a c
b
c
a a
ba c b
S
• False paths, multiple clocks, crosstalk… T
c c
b
a c
a
c
A b

• Taking into account variability

b
T a c
c
E
(statistical timing analysis) b
c

April 11, 2024 Stanford EE292A Lecture 18 17

Physical Verification
distance
• DRC – Design Rule Check width
• no design rule violations, examples:
• Also, density, antenna, coloring, connectivity, contact
voltage domains, … coverage

• Key operations over gate

• Boolean mask operations, e.g. AND, OR, XOR, … for extension
auxiliary and derived layers
• Measuring areas, distances Poly&Diff active Gate
WG Poly&Diff
• ERC – Electrical Rule Check Source/Drain Poly&Diff
• electrostatic discharge, transistor size in voltage
domains, max C, … WD

April 11, 2024 Stanford EE292A Lecture 18 18

Physical Verification
Parasitic Extraction
• In cell based digital design, standard cells are characterized by
spice simulation, so their characteristics are known, e.g., gate
capacitances, delay, power…

• Interconnect (wires, vias) parasitics (R, C sometimes L) need to

be extracted for a given layout and included in circuit simulation

• Custom/AMS designs may also require custom transistor models

April 11, 2024 Stanford EE292A Lecture 18 19

Physical Verification
• Parasitic extraction key operations 𝐿
• R can be extracted locally R = 𝜌𝐿/𝐴 𝐴
𝑑
𝜌 Resistivity
w
C = 𝜀𝐿𝑤/𝑑
• C can be extracted locally 𝜀 Permitivity

• L requires current return paths, only for high I

• To be really accurate requires a field solver

I
V
Skin effect Electric field Magnetic field
April 11, 2024 Stanford EE292A Lecture 18 20
Layout versus Schematics
• LVS ensures that the physical design (layout) is the same
than the circuit (schematics)
a
c

=
a
b

a
c

a
b

=
April 11, 2024 Stanford EE292A Lecture 18 21
Signoff
Fab / Foundry Design

PDK
Symbol Schematic Timing
P DRM
Pcell
PEX
Layout
Extraction
DRC / ERC / LVS
Power
Process & Design Rule Rules DRC
MDP limits Manual Model Spice

April 11, 2024 Stanford EE292A Lecture 18 22

Signoff
Signoff essentially means all the verification done before tape-out
• Physical (DRC/LVS) verification passes
• Timing closure and Signal integrity
• Power Closure and thermal design

April 11, 2024 Stanford EE292A Lecture 18 23

Signoff
Timing Closure [22, 23]
• The design is fast enough, in digital circuits the
critical path is faster than the clock
data tsetup thold
• Setup, how “fast” the logic needs to be
clock
• Hold, how “slow” the logic needs to be
• Signal Integrity, noise violations, e.g., clock noise

April 11, 2024 Stanford EE292A Lecture 18 24

Timing Closure
• Dynamic simulation, e.g., SPICE
• Yields detailed waveforms but
• Slow
• Requires input vectors (may miss a critical input value)

• Static Timing Analysis (STA)

• Simpler models, e.g., gate delay, wire delay
• Faster
• Static, no input vectors

April 11, 2024 Stanford EE292A Lecture 18 25

Signoff
Power closure, power integrity [24]

• Dynamic Power
• Transistor switching 𝛼 CVDD2f
• Gate + wire capacitance
• nMOS and pMOS both “on” is ~10% dynamic power
Gate IGate

• Static Power Source Drain

ISub IJ
• Leakage: Gate, junction, subthreshold

April 11, 2024 Stanford EE292A Lecture 18 26

Signoff
Power closure on the Power Grid
I

VDD-IR VDD
• IR drop 𝐴

R = 𝜌𝐿/𝐴 𝐿
𝜌 = 1.637 𝜇Ohm / cm for copper https://www.semiwiki.com/forum/content/
2957-signoff-summit-voltus.html

• Current densities J=I/A

Jmax is 100-1000 A/mm2 for copper depending on T

• Electromigration. High current densities

cause transport of material [25]

April 11, 2024 Stanford EE292A Lecture 18 27

Summary
• IC design verification includes functionality, electrical and physical
properties
• Equivalence checking and LVS checks for the same functionality
among different levels of representation
• Verification at higher levels also includes memory consistency,
security, effect of random errors, …
• Timing, power and geometry can be verified accurately only in
later stages of design (circuit and physical)
• Signoff is the contract with the fab that agrees on timing, power,
area and functioning devices – but not functionality of the design

April 11, 2024 Stanford EE292A Lecture 18 28

References
1. UVM https://www.accellera.org/downloads/standards/uvm, also IEEE Std 1800.2-2017
2. SystemVerilog
3. SystemC
4. R.E. Bryant, Graph Based Algorithms for Boolean Function Manipulation, IEEE Transactions on Computing, August 1986
5. Goldberg, M. Prasad, R. Brayton, Using sat for combinational equivalence checking, Proceedings of DATE’01, pages 114–
121, 2001
6. O.Coudert, C. Berthet, J.C. Madre, Verification of synchronous sequential machines based on symbolic execution, Proc.
CAV 1989, Springer
7. A. Kuehlmann, K. McMillan, R. Brayton: Probabilistic state space search, ICCAD 1999
8. J.H. Hong, R. Jiang, R.K. Brayton, On the verification of Sequential Equivalence, IEEE Transactions on CAD of Integrated
Circuits and Systems, June 2003
9. K. L. McMillan, Symbolic Model Checking. Norwell, MA: Kluwer, 1993
10. E. M. Clarke, O. Grumberg, and D. Peled, Model Checking. MA: MIT Press, 1999
11. M. Elver and V. Nagarajan, "McVerSi: A test generation framework for fast memory consistency verification in
simulation," 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA), 2016, pp. 618-630
April 11, 2024 Stanford EE292A Lecture 18 29
References
12. Y.A. Manerkar et al “RTLCheck: Verifying the Memory Consistency of RTL Designs”, in MICRO-50, 2017, Cambridge, MA
13. W. Hu et al , “Register transfer level informajon flow tracking for provably secure hardware design”, in 2017 Design and
Test In Europe
14. Farimah Farahmandi et al “Trojan localizajon using symbolic algebra”, in 2017 22nd Asia and South Pacific Design
Automajon Conference (ASP-DAC)
15. M. He at al “RTL-PSC: Automated Power Side-Channel Leakage Assessment at Register-Transfer Level”, in 2019 IEEE 37th
VLSI Test Symposium
16. Julian Hoefer, Fabian Kempf, Tim Honilter, Fabian Kreß, Tanja Harbaum, and Jürgen Becker. 2023. “SiFI-AI: A Fast and
Flexible RTL Fault Simulajon Framework Tailored for AI Models and Accelerators” In Proceedings of theGreat Lakes
Symposium on VLSI 2023 (GLSVLSI ’23), June 5–7, 2023
17. L. Nagel, D.O. Pederson, SPICE, Memorandum No. ERL-M382, University of California, Berkeley, Apr. 1973
18. L. Nagel, W. Laurence, SPICE2: A Computer Program to Simulate Semiconductor Circuits, Memorandum No. ERL-M520,
University of California, Berkeley, May 1975

April 11, 2024 Stanford EE292A Lecture 18 30

References
19 T. I. Kirkpatrick, N. R. Clark, “PERT as an aid to logic design,” IBM Journal of Research and Development, March 1966
20 Kukimoto Y., Berkelaar M., Sakallah K. Static Timing Analysis. In: Hassoun S., Sasao T. (eds) Logic Synthesis and
Verification, Springe, Boston, MA, 2002
21 C. Visweswariah et al, First-Order Incremental Block-Based Statistical Timing Analysis, Proc. DAC 2004
22 http://vlsicad.ucsd.edu/DAC15/MACDONALD_TIMINGCLOSURE.pdf
23 A.B. Khang , New Game, New Goal Posts: A Recent History of Timing Closure, DAC 2015
24 N. Weste, D. Harris, CMOS VLSI Design: A Circuits and Systems Perspective, Chapter 5 Power, Addison-Wesley
25 K. Kyung-Hoae, ‘‘Comparison study of future on-chip interconnects for high performance VLSI applications,’’ Ph.D., Dept.
Elect. Eng., Stanford Univ., Mar. 2011
26 https://semiwiki.com/tag/raul-camposano/ and other Semiwiki blogs by Murphy, Cunningham and Camposano

April 11, 2024 Stanford EE292A Lecture 18 31