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7 views32 pages

Computer Organization & Architecture - CHAPTER-6.Pdf - 3580

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ujjwalbhujel333
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CHAPTER-6

Arithmetic Unit
Shift-add multiplication:
=> multiplication of unsigned numbers.
=> multiplication can be performed by repeated addition of multiplicand and shifting
Contd…
RTL code for shift-add multiplication
Contd…
Example UV <- X x Y; X= 1101 and Y=1011.
Booth Algorithm

 It reduces the number of addition.


 Negative multiplier, positive multiplier are treated the same.
 For negative numbers multiplication, the operation is performed by representing the
negative numbers in it’s 2’s complement form.
 ADVANTAGES:
=>When there are lot of ones, all will be cancelled and replaced with zeros.
=> More zeros means, it reduces the addition(no operation is done with zeros)
=> But shift remains the same, can’t be reduced.
Contd…
Multiply 9 x 3 using booth algorithm.
Contd…

 Result Verification:
1111100101
Since there is end around carry, we find it’s 2’s complement and place ‘-’ sign before the
equivalent decimal.
i.e. 0 0 0 0 0 1 1 0 1 1
i.e. -27
RTL code for Booth algorithm

1: U <- 0, Y-1 <- 0, I <- n


Y0Y-1’2: U <- U + X’ + 1
Y0’Y-12: U <- U + X
2: i <- i – 1
3: ashr(UV), cir(Y), Y-1 <- Y0
Z’3: goto 2
Z3: FINISH <- 1
Perform 9 x -3 multiplication using Booth algorithm.
Here,
X = 9 = 01001
Y = -3= 11101
Shift subtract division
(Before we look at the operation of the entire algorithm, consider the circumstances under which the first step terminates
the algorithm. For 112÷7 with n=4, UV= 0111 0000 and X= 0111. Since, U≥X, the algorithm exists immediately. Had it
proceeded, it should have produced a result of 16 (1 0000) and a remainder of 0. The value 1 0000 cannot be stored in a 4-
bit register), this is the reason for the overflow.
Contd…
Trace of the RTL code for the operation 147 ÷ 13.
Here, U = 1001, V = 0011, X = 1101 and n=4.
Binary Coded Decimal(BCD)
BCD adder:
(When two decimal numbers are added, the maximum result is 19 => (9 + 9 +1(carry)))
Contd…
(The condition for the correction and setting c=1 is:
c = k + z8z4 + z8z2 = 1)
Specialized Arithmetic hardware
1. PIPELINING

T1 = time taken by non-pipelined unit to calculate 1 result. Requires n.T1 time to calculate n results.
Pipelined unit requires k time units, each of duration Tk , to move the first piece of data through the pipeline.
Because, additional data enters the pipeline during every cycle, it will output the remaining n-1 results during next n-1 cycles.
=> thus, the pipelined unit requires (k + n – 1) cycles, each of Tk time, to calculate same results.
The speedup can be calculated by the formula above.
Contd…..

 Data enters into a stage of the pipeline, which performs some arithmetic operations on
those data.
 The results are then passed to next stage which performs its operation and so on until the
final computation ha been performed.
 Each stage performs only its specific function, no need to be capable of performing the task
of any other stage.
 A pipeline does not speed up an individual computation. It improves the performance by
overlapping computations where each stage can operate on different data simultaneously.
 The net effect is that output appears more quickly than in non-pipeline arithmetic unit,
thereby increasing the throughput.
2. Lookup Tables:
 Any combinational circuit can be implemented by ROM is a lookup table.
 Inputs to the combinational circuit serve as the address input of the ROM.
 Data outputs of the ROM corresponds to the output of the combinational circuit.
 ROM is programmed with data such that the correct values are output for any possible
input values.
 Consider a 4 x 1 ROM programmed to mimic a two input AND gate.

AND gate

Lookup ROM equivalent

 By programming ROM with data shown, it outputs the same values as the AND gate for all
possible values of X and Y.
Contd..(a multiplier implemented using a lookup ROM)
Contd…

 Registers X and Y supply the address inputs to lookup ROM.


 It’s outputs are the product of X and Y, and are routed to registers U and V.
 Each of 256 locations must contain the 8-bit product of X and Y.
 For example, location 1011 1101 contains the data 1000 1111, 143, the product of 1011(11)
and 1101(13).
 Advantages:
=> the hardware may be less complex than that of the original shift-add implementation.
=> can multiply numbers more quickly than the shift-add hardware.
=> However, size of the lookup ROM grows rapidly as the size of the operands increases.
3. Wallace Tree

 Combinational circuit used to multiply two numbers.


 Instead of performing additions using standard parallel adder, Wallace tree uses carry save
adder and only one parallel adder.
 Carry save adder can add 3 values simultaneously. However, it does not output a single
result, but provides both sum and a set of carry bits as output.

 To form the final sum, S and C must be added together because carry bits do not propagate
through the adder.
 To use a carry save adder to perform multiplication, we first calculate the partial product of
the multiplication and input them to carry save adder.

Fig: Generating partial products for multiplication using Wallace tree.


A 3 x 3 multiplier constructed using carry save adder.
Contd..
A 4 x 4 Wallace tree multiplier.
Contd…
An 8 x 8 Wallace tree multiplier.
Floating point numbers
 Floating point format is similar to scientific notation.
 Using scientific notation, we can express a number in different ways.
i.e. -1234.5678 = -1.2345678 x 103
= -1234567.8 x 10-3
 Computers can be efficient if each number can have only one representation (unique).
 So, floating point numbers must be normalized i.e. each number significand is a fraction
with no leading zeros.
 Thus, the only valid floating point representation for this number is
-.12345678 x 104
The normalized representation works well for every possible numbers except 0
 A computer stores floating point numbers in a pre-defined format.
=> Each number requires signed bit.
=> A significand of some pre-defined length.
=> An exponent of some given length.
i.e.XSXFXE where XS=1, XF=12345678 and XE=4
Contd…

 To represent negative exponents, one possibility is to use two’s complement values, the
prevalent practice is to use biasing.
 Assume that XE has four bits, and should be able to represent all exponents from -8 to +7.
 To do so, a set bias value is added to the actual exponent and result is stored in XE.
 -8 is represented as -8 + bias = -8 +8 = 0(0000).
 +7 is represented as +7 + bias = +7 +8 = 15(1111).
IEEE 754 floating point standard
 Defines set format and operation modes. Doesn’t specify arithmetic procedures and
hardware to be used.
 IEEE 754 standard is used in virtually all CPUs that have floating point capability.
 IEEE 754 standard specifies two precisions for floating point numbers.
1. single precision number having 32 bits
2. double precision number having 64 bits
 In single precision,
1 bit for sign, 8 bit for exponent & 23 bit for significand
 In double precision,
1 bit for sign, 11 bit for exponent & 52 bit for significand
 Significand falls in the range 1 ≤ significand < 2.
 Exponent uses a bias of 127, having range -126 t0 127.
 Exponent values 0000 0000(-127) and 1111 1111(128) are used for special numbers.
Contd…

 +19.5 = 10011.1 or 1.00111 x 24 in binary.


Not included, presence is implicit in this standard.
 For +19.5
sign = 0
significand = 001 1100 0000 0000 0000 0000
exponent = 1000 0011 (131 = 4 + 127)
 For 0
sign = 0
significand = 000 0000 0000 0000 0000 0000
exponent = 0000 0000
Addition and subtraction in Signed Notation
Contd…

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