CMOS

Digital Integrated
Circuits
Analysis and Design

Chapter 9
Dynamic Logic Circuits

1
Introduction
• Static logic circuit
– Output corresponding to the input voltage after a
certain time delay
– Preserving its output level as long as the power
supply is provided
– Large area, time delay
• Dynamic logic circuit
– The operation of all dynamic logic gates depends on
temporary (transient) storage of charge in
parasitic node capacitances
– Need periodic clock signals ⇒charge refreshing
– Smaller silicon area
– Consume less power

2
Example 9.1
• CK=1, MP on
– Cx charging, or
discharging ⇒ Q=D
• CK=0 MP off
– Cx isolated from D
– Q=Vx (depend on the charge store in Cx)
• 2nd inverter remove
– Transistor counts ↓
– Q=-D
• Assuming VOL=0V, VIL=2.1V, VIH=2.9V, VOH=5.0V,
VTn=0.8V
– CK=1, MP on
• Vin=VOH=5V, Vx=5-0.8=4.2V, higher than VIH so VQ=VDD
– CK=0, M off
• Vx=4.2V, if charge leakage ⇒ Vx<2.9V, can’t be interpreted as a
logic “1”

3
Basic principles of pass transistor circuits
• The fundamental building block of nMOS
dynamic logic circuits
– An nMOS pass transistor driving the gate of
another nMOS transistor
• MP
– Driving by the periodic clock signal
– Acts as access switch
– If CK=1
• Logic “1” transfer
• Logic “0” transfer
– If CK=0
• Cease to conduct and the charge store In the parasitic
capacitance
4
 Logic “1’ transfer
Intially Vx (t = 0) = 0V, Vin = VOH = VDD , CK : 0 → 1
MP on in saturation region starts to charge up the C x

= (VDD − Vx − VT ,n )
dVx k n 2
Cx
dt 2
2C x dVx 2C x ⎛⎜ 1 ⎞V
⎟ 0x
t Vx
∫0 dt =
kn∫0 (VDD − Vx − VT ,n )2 kn ⎜ (VDD − Vx − VT ,n )
=
⎟
⎝ ⎠
2C x ⎡⎛⎜ 1 ⎞ ⎛
⎟ ⎜ 1 ⎞⎤
⎟⎥
t= ⎢ −
k n ⎢⎣⎝ (VDD − Vx − VT ,n ) ⎠ ⎝ (VDD − VT ,n ) ⎟⎠⎥⎦
⎜ ⎟ ⎜

⎛ k n (VDD − VT ,n ) ⎞
⎜⎜ ⎟⎟t
Vx (t ) = (VDD − VT ,n ) ⎝ ⎠
2 C x

⎛ k (V − V ) ⎞
1 + ⎜⎜ n DD T ,n ⎟⎟t
⎝ 2C x ⎠
Vmax = Vx t →∞ = VDD − VT ,n = VDD − VT 0,n − γ ( 2φF + Vmax − 2φF )
The node Vx has an upper limit of Vmax=(VDD-VT,n)
5
Logic “1’ transfer

VT ,n1 = VT 0,n − γ ( 2φF + Vmax1 − 2φF )

VT ,n 2 = VT 0,n −γ ( 2φF + Vmax 2 − 2φF )
....
. 6
 Logic “0” transfer The pass transistor operates in the linear region
throughout this cycle, since VDS<VGS-VT,n
− Cx
dVx k n
dt
=
2
(
2(VDD − VT ,n )Vx − Vx2 )
2C dVx
dt = − x ⋅
k n 2(VDD − VT ,n )Vx − Vx2
⎛ 1 1 ⎞
⎜ ⎟
t 2C x Vx ⎜ 2(VDD − VT ,n ) 2(VDD − VT ,n ) ⎟
∫0 dt = − kn ∫VDD−VT ,n ⎜ 2(VDD − VT ,n ) − Vx + Vx dV
⎟ x
⎜ ⎟
⎝ ⎠
Cx ⎡ ⎛ 2(VDD − VT ,n ) − Vx ⎞⎤ Vx
t= ⎢ln⎜ ⎟⎟⎥ VDD −VT ,n
k n (VDD − VT ,n ) ⎣ ⎜⎝ Vx ⎠⎦
Cx ⎛ 2(V − V ) − Vx ⎞
t= ln⎜⎜ DD T ,n ⎟⎟
k n (VDD − VT ,n ) ⎝ Vx ⎠
Cx ⎛ (2 − 0.9)(VDD − VT ,n ) ⎞ Cx ⎛ 1 .1 ⎞
t90% = ln⎜⎜ ⎟= ⎜ ⎟
k n (VDD − VT ,n ) ⎝ 0.9(VDD − VT ,n ) ⎟⎠ k n (VDD − VT ,n ) ⎝ 0.9 ⎠
ln

Cx ⎛ 1 .9 ⎞
t10% = ln⎜ ⎟
k n (VDD − VT ,n ) ⎝ 0.1 ⎠

τ fall = t10% − t90% =

Cx
[ln(19) − ln(1.22)] = 2.74 Cx
k n (VDD − VT ,n ) k n (VDD − VT ,n )

7
Charge storage and charge leakage

Ileakage=Isubthreshold(MP) +Ireverse(MP)
8
 Equivalent circuit used for analyzing the
charge leakage process Q = Q (V ) + Q where Q = C ⋅V j x in in in x

Cin = C gb + C poly + Cmetal

dQ dQ j(Vx ) dQin
I leakage = = +
dt dt dt
dQ j(Vx ) A ⋅ C j0 qε Si N A
where = C j (Vx ) = = A⋅
dVx V 2(φ0 + Vx )
1+ x
φ0
kT ⎛ N D ⋅ N A ⎞ qε Si N A N D qε Si N A
φ0 = ln⎜⎜ ⎟, C = ≈
q ⎝ ni2 ⎟⎠ 2( N A + N D )φ0 2φ0
j 0

C x ,min = C gb + C poly + Cmetal + Cdb ,min

ΔQcritical ,min ⎛ V ⎞
t hold = where ΔQcritical ,min = C x ,min ⎜Vmax − DD ⎟
I leakage,max ⎝ 2 ⎠
Cin: these constant capacitance components
Cx: due to reverse biased drain-substrate junction
Cx,min: the minimum combined soft-node capacitance
Cdb.mim: the minimum junction capacitance, obtained under the bias condition Vx=Vmax
thold: worst-case holding time—the shortest time required for the soft-node voltage to
drop from the initial logic high value to the logic threshold voltage due to leakage

9
Example 2

10
Example 2 (cont.)

11
 Voltage bootstrapping

• To overcome threshold voltage drops in digital circuits

• Figure 9.11
– Considering Vx ≤ VDD ⇒ M2 in saturation , Vout(max)=Vx-VT2(Vout)
– To obtain a full logic-high level VDD, the voltage Vx must be increased
• Figure 9.12
– A third transistor has been added to the circuit
– Cs: dynamic couple to the ground
– Cboot: dynamic couple to Vx
– This circuit produce a high Vx during switching
• Vx≥VDD+VT2(Vout)
12
Voltage bootstrapping
Vx = VDD − VT 3 (Vx )
dVx d (Vout − Vx )
iCs ≈ iCboot ⇔ C s ≈ Cboot
dt dt
(Cs + Cboot ) dVx ≈ Cboot dVout ⇒ dVx ≈ Cboot dVout
dt dt dt (Cs + Cboot ) dt
Vx Cboot VDD Cboot
∫VDD −VT 3
dVx = ∫
(Cs + Cboot ) VOL
dVout ⇒ Vx = (VDD − VT 3 ) + (V − V )
(Cs + Cboot ) DD OL
if Cboot is much larger than Cs ⇒ Vx( max ) = 2VDD -VT 3-VOL

= (VDD − VT 3 (Vx ) ) +
Cboot
Vx (min) = VDD + VT 2 (V − V )
VOUT =VDD
(Cs + Cboot ) DD OL
Cboot VT 2 VOUT =VDD +VT 3 Vx
=
(Cs + Cboot ) (VDD − VOL )

Cboot VT 2 VOUT =VDD +VT 3 Vx

=
Cs VDD − VOL − VT 2 VOUT =VDD −VT 3 Vx
*Cs: the sum of the parasitic source-to-substrate cap. ofM3 and the
gate-to substrate cap of M2
*To obtain a sufficiently large bootstrap cap. Cboot in comparison to
Cs, an extra “dummy” transistor is added
*The dummy transistor acts as an MOS capacitor between Vx and
Vout

13
Example 9.3

14
Synchronous dynamic circuit techniques
• Previous section
– Basic concepts associated with temporary
storage of logic levels in capacitive circuit
nodes
• This section
– Pay attention to digital circuit design
– Different examples of synchronous dynamic
circuit
• Depletion-load nMOS
• Enhancement-load nMOS
• CMOS building block

15
Dynamic pass transistor circuits
• Cascaded
combinational logic
stage
• Interconnected
through nMOS
transistor
• All input of each
combinational logic
block are driven by
a single clock
signal
• Two phase clocking

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Depletion-load nMOS dynamic shift register circuit

• Φ1 active
– Vin is transferred to Cin1 ⇒ Vout1 is determined
• Φ2 active
– Vout1 is transferred to Cin2 ⇒ Vout2 is determined
– Cin1 retain its previous level via charge storage
• Φ1 active again
– The original data bit written into the register (3rd)
– !st stage accept new data
17
Depletion-load nMOS dynamic shift register circuit

• Maximum clock frequency

– Being determined by
• the signal propagation delay through one inverter stage
– One half–period of the clock signal must be long enough
to allow
• Cin to charge up or down
• and the logic level to propagate to the output by charging
Cout
• Logic-high input level of each inverter stage is one
threshold voltage lower than the power supply
level
18
A two-stage synchronous complex logic circuit

• The same operation principle extended to

synchronous complex logic
• In order to guarantee correct logic levels are
propagated during each active clock cycle
– The half period length of the clock signal must be longer
than the largest signal-stage signal propagation delay found
in the cirucit
19
Enhancement-load dynamic shift register (ratioed
logic)(1)

• One important difference

– Applying the clock signal to the gate of the load transistor
• Power dissipation and the silicon area can be reduced
significantly
• The input pass transistor and load transistor are
driven by opposite clock phase

20
Enhancement-load dynamic shift register (ratioed
logic)(2)

• Φ1 active
– Vin ⇒ Cin1, nMOS load off
• Φ2 active
– nMOS load on, the output of 1st inverter attains its valid logic (Cin1 preserved)
– Pass transistor of 2nd stage on
• Cout1 ⇒ Cin2
• Φ1 active
– Cout2 is determined and transferred into Cin3
– Also, a new input level can be accepted into Cin1
• VOL of each stage is strictly determined by the driver to load ratio (ratioed-
dynamic logic)

21
 General circuit structure of ratioed
synchronous dynamic logic

• Extended to arbitrary complex logic

22
Enhancement-load dynamic shift register (ratioless
logic)(1)

• In each stage, the input pass transistor and the load transistor
are driven by the same clock phase
• Φ1 active
– Vin transfer to Cin ⇒ 1st inverter is active ⇒ Vout1 attains its valid
logic level
• Φ2 active
– 2nd pass transistor on ⇒ the logic level is transferred onto the
next stage

23
Enhancement-load dynamic shift register (ratioless
logic)(2)

• Considering two cases

– Case 1
• If Cout1 high at the end of the active Φ1 phase
– By mean of Cin1 low input ⇒ nMOS driver off ⇒Vout1=VDD-VTn
• Φ2 active
– The voltage level is transfer to Cin2 via charge sharing over the
pass transistor
– Cout/Cin ↑ to correctly transfer a logic-high level

24
Enhancement-load dynamic shift register (ratioless
logic)(3)

• Considering two cases

– Case 2
• If Vout1 is logic-low at the end of the active Φ1 phase
– Cin1 high, nMOS driver on⇒ Vout1=0V
• As Φ2 active
– Transfer by pass transistor
• Ratioless dynamic logic
– VOL=0, independent of driver-to-load ratio

25
General circuit structure of ratioless synchronous
dynamic logic

26
Dynamic CMOS transmission gate logic

• Totally, require four clock signals

27
CMOS transmission gate dynamic shift register

• Low on-resistance of transmission gate (ref.p310)

– Smaller transfer time (RC↓)
• No threshold voltage drop

28
Single-phase CMOS transmission gate
dynamic shift register

• Ideally, CK=1
– Odd on, even off⇒ isolated
• In practical, do not truly nonoverlapping
– CLK have finite tr and tf
– So, prefer Φ1, Φ2
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Dynamic CMOS logic gate implementing a complex
Boolean function(1)

F = ( A1 A2 A3 + B1 B2 )

• Significantly reduce the number of transistors used to

implement any logic function
• Operation
– First precharging the output node capacitance
– Evaluating the output level according to the applied inputs
– Both of theses of operations are scheduled by a single clock
signal
• Which drives one nMOS and one pMOS transistor in each dynamic 30
stage
Dynamic CMOS logic gate implementing a complex
Boolean function(2)

• Φ=0 (precharge phase)

– Mp on, Me off ⇒ the parasitic capacitance of the circuit is charged up to
Vout=VDD
• The input voltages are also applied during this phase⇒ no influence on the output
• Φ=1 (evaluate phase)
– Mp off, Me on ⇒ the output voltage depend on the input voltage levels
• VOL or VDD
• The practical multi-stage applications, however, the dynamic CMOS gate
presents a significant problem
31
Illustration of the cascading problem in
dynamic CMOS logic(1)

• Assume
– During the precharge phase
• Both output voltages Vout1 and Vout2 are pulled up
– During evaluation phase
• The input variables of 1st stage assume to be such that
– Output Vout1 drop to logic “0”
• The external input of 2nd stage assume to be logic ‘1’
• As evaluation
– Beginning
• Both Vout1 an d Vout2 are logic-high
– Then
• Vout1 drops to its correct logic after a certain time delay
• Vout2
– Starting with the high value of Vout1 at the beginning of the evaluation phase, the output voltage Vout2 at
the end of the evaluation phase will be erroneously low

32
Illustration of the cascading problem in dynamic
CMOS logic(1)
• This example illustrates that
– Dynamic CMOS logic gates driven by the
same clock signal cannot be cascade
directly
– This limitation undermine some advantages,
such as
• Low power dissipation
• Large noise margins
• Low transistor count

33
High-performance dynamic CMOS circuits
• Base on the basic dynamic CMOS logic gate
structure
• Design to take full advantage of the obvious
benefits of dynamic operation
• To all unrestricted cascading of multiple
stages
• The ultimate goal is to achieve…,using the
least complicated clocking scheme possible
– Reliable
– High-speed
– Compact circuit

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