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Unit - 5 DPCO

Unit -5 DPCO

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Gopika Siva
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153 views35 pages

Unit - 5 DPCO

Unit -5 DPCO

Uploaded by

Gopika Siva
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© © All Rights Reserved
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Unit 5 - Memory and I/O eee . 2th os oes Y © 4 Cache Memory O = Sw _L Cache Memory is a special very Gich-apes} memory. Itis used to speed up and synchronizing with high-speed CPU Cache memory is costlier than main memory or disk memory but economical than CPU registers. Cache memory is an extremely fast memory type that acts as a butfer between RAM and the cPpuY ae Itholds frequently requested data and instructions so that they are immediately available to the CPU when needed. Simple Cache ro % x © Processor requests are each one word ua Be and the blocks also Xan2 Xn-2 consist of a single word Kans % % 4. Bofore the relerence to X,, _b. After the reference to X,, FIGURE 6.7 The cache just before and just after a reference to a word X, that is not Initially in the cache. This reference causes a miss that forces the cache to fetch X, from memory and {insert it into the cache. Swe S Xn Simple Cache’ — Bsvots Bem tw X wi X% word Xyoe Xan Xoo Ken % % X % @btore te rteronce 1X, '. After the reference to X,, its ee FIGURE 5.7 The cache Just before and just after a reference to a word {ttiaty tn the cane. Tis reference cane amis that fore the cache toch Xo memory eat {insert it into the cache, Processor request: are each one word and the blocks also consist of a single word Weds —> Cade El Cache Mapping- Direct Mapping Eg. 22- Apple.26- Orange, 22,26,16- Guava.18-Mango i = j modulo m where iscache line number j= main memory block number menumber of lines in the cache slolalaloln Weds —> Cade El aret Cache Mapping- Direct Mapping aa cearnaind a “ ee = r us = yy @ where ee te. apple %6- orange QQ2810- 3 oe ng nD arcusber of lines ia the cache Guava,18-Mango ) ~ Caceres D 22 —peacke hit 0 1G 4)26 encke RIF ; 5) IGA O @s 2e © [978 =2 3 Weds —> Cade EE) diet Cache Mapping- Direct Mapping wher Me oY iscache line number ehumtome@hed © yes eee, Guava.1&-Mango a) 2674.2 2 Cacke =8 D 22 —pcache hit 0 1G 24,23 10,16 az ceed 21 —_—— 2 eas oe A> 213 © [ere =27 3 24 5 >e a2y 7 Momory 01205) c. After handling a miss of address (21010,.,) 4. Aftor handling @ miss of address (10000...) c. After handling @ miss of address (11010...) one 19M? aanaze frst 267k ‘Memory (10110), 4. After handing @ miss of BdGr08S (10000) Need of Tag bits and Valid bits 1. Thetags contain the address information required to identify whether a word in the cache corresponds to the requested word. 2. Valid bit used to indicate whether an entry contains a valid address. If the bit is not set. there cannot be a match for this block. Key points of Direct Mapping “ oe In Direct mapping, assign each memory block to pectic ine)h the cache. Ifa line is previously taken up by a memory block when a new block needs to be loaded, the old block is yashed. ‘An address space is split into two parts index field and a tag field. The cache is used to store the tag field whereas the rest is stored in the main memory. Direct mapping's performance is directly proportional to the Hit ratio.” Cache cs Aso bye ge ——_ wen my Handling Cache Miss a . Send the original PC value (current PC - 4) to the memory. Y Eat . Instruct main memory to perform a read and wait for the memory to complete its access. . Write the cache entry, putting the data from memory in the data portion of the entry, writing the upper bits of the address (from the ALU) into the tag field, and turning the valid bit on. . Restart the instruction execution at the first step, which will refetch the instruction, this time finding it in the cache. Cocke present (HD vv x KX cut ee 24,18, 19, 64 552 Aik ohio av Cache Performance Q. The performance of the cache is in terms of ahi ratio) AT Q The CPU searches the data in the hen it ting or read any data from the In cs the daa in thea} when it equtes writing or read any dat from the main meme this case, two cases may occur as follows © ithe CPU finds that datain the Gob aGache hid)pecurs and it reads the data from the cache. © On the other hand, if it does not find that data in the cache, che mi urs. Furthermore, during cache miss, the cache allows the entry of data and then reads from the main memory © Therefore, we can define the hit ratio as th{ number of hits givided by the sum of hits and misses. Measuring and Improving Cache Performance CPU time = (CPU execution clock cycles + Memory-stall clock cycles) X Clock cycle time Memory-stall clock cycles = (Read-stall cycles + Write-stall cycles) Reads Read-stall cycles = X Read miss rate X Read miss penalty Program Write-stall cycles = Waites Write miss rate X Write miss penalty Program + Write buffer stalls Memory-stall clock cycles = Gemory access, Miss rate X Miss penalty aes Program Hit ratio = hit / (hit + miss) = no. of hits/total accesses AMAT = Time for a hit + Miss rate X Miss penalty Calculating Average Memory Access Time Find the AMAT for a processor with a 1 ns clock cycle time, a miss penalty of 20 clock cycles, a miss rate of 0.05 misses per instruction, and a cache access time (including hit detection) of 1 clock cycle. Assume that the read and write miss penalties are the same and ignore other write stalls. AMAT = Time for a hit + Miss rate X Miss penalty Calculating Average Memory co Time Gis the AMAT for a eae) with al Cns cocycle time, dais penalty yf Qoklock cycles, amiss rat isses per instruction, and a cache access time (including hit detection) of co lock cycle. Assume that the read and write miss penalties are the same and ignore other write stalls. AMAT = Time for a hit + Miss rate X Miss penalty = A. 4 0105 X2D = 2 Ak eyches =Qxte 2M Assovakve —> ontree gue erouah ve Reducing Cache Misses 1. Reducing Cache Misses by More Flexible Placement of Blocks shag > aos te @ sens. _ Seto Y ey“ [| block can map to [| Set-2 2. Reducing the Miss Penalty) ising Multilevel Caches —___—— 1. L1 cache, or primary cache, is extremely fast but relatively small, and is usually embedded in the processor —— chip as CPU cache. 2. L2 cache, or secondary cache, is often more capacious than L1. L2 cache may be embedded on the CPU, or it can be on a separate chip or coprocessor and have a high-speed alternative system bus connecting the cache and CPU. That way it doesn't get slowed by traffic on the main system bus. 3. Level 3 (L3) cache is specialized memory developed to improve the performance of L1 and L2. L1 or L2 can be significantly faster than L3, though L3 is usually double the speed of DRAM. Cache Replacement Algorithms Aone Least Recently Used Random Replacement FIFO > Most Recently used hac, 2 amie Cade / — ho spaceX, Random Replacement k ged Qo y|& Be meee NB.erD/ErF GH ©o0@ FIFOY Fst a Sout onl a 7 e © ® £ F ] @ € F G © e€ +f G tig yp VP AB 53 EpFfe BC #35860 A 3 ce D € we c D c D Least Recently Used i 1235 6 - a och@s F Life. at Most Recently Used be Be A A A A BEww oP nH HEM How this happens? o > Move — Laptop Thuppaki las RAM C848) Appl rnerie/ Gnme > RAM _ Virtual Memory ° ' 2 3 a leb>5 yo ece 4 cse 1 cece 5 sed ° OC 6] ey ( | alan [4 | > CN Virtual Memory oO or 7, Lab Exar ees Lab=>5 eyo dees ecé 4 coe 1 ece 5 ese Virtual Memory ° ' 2 3 & CY Lab Exon oe Gdos Mom mly => SO ego eses ecé 4 cse 1 ece 5 ese dl 9 Ov Ov @v v2. ou tveaah adi odds u Gana Sym Caan eo) Address Translation 48 14191211 100 @f--9 240 Physical page number Page offset Key Points 1. Virtual Memory is a storage scheme that provides user an illusion of having a very big main memory. This is done by treating a part of secondary memory as the main memory. 2. In this scheme, User can load the bigger size processes than the available main memory by having the illusion that the memory is available to load the process. 3. Instead of loading one big process in the main memory, the Operating System loads the different parts of more than one process in the main memory. 4. By doing this, the degree of multiprogramming will be increased and therefore, the CPU utilization will also be increased. - swury? ep

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