Scribd
Upload
37 views

HDLlab

The document outlines 52 hardware design problems related to digital logic circuits that can be implemented using VHDL or Verilog for an FPGA course. The problems include generating clock signals, frequency division, flip-flops, adders/subtractors, counters, comparators, multipliers, dividers, decoders, RAM, ALU components, and finite state machines.

Uploaded by

poonam390
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
37 views

HDLlab

The document outlines 52 hardware design problems related to digital logic circuits that can be implemented using VHDL or Verilog for an FPGA course. The problems include generating clock signals, frequency division, flip-flops, adders/subtractors, counters, comparators, multipliers, dividers, decoders, RAM, ALU components, and finite state machines.

Uploaded by

poonam390
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
You are on page 1/ 2

HDL Lab

M.Tech (VLSI Design-1st Semester)


All Design Based on VHDL and Verilog HDL & Implementation on FPGA Kit
1 2 Generate a Clock having duty cycle 40% and Clock period 20ns. Implement a circuit to divide the frequency of current signal by factor of two. Assume present frequency of signal is 20 MHz. 3 Implement T Flip-Flop using D Flip-Flop 4 Implement a 2 bit full subtractor using NAND gates. 5 Implement a 1-bit full adder using NAND gates and then use this as basic building block and design 1 bit full subtractor. 6 Generate a circuit to determine factorial of given number. 7 Design 4-bit synchronous counter with and without reset. 8 Implement a 2-bit comparator using NAND gates. 9 Design a circuit to divide frequency of clock cycle by two 10 Design of FSM 11 Design a Transmission Gate-based D-Latch. 12 Counts the number of leading zeros in binary vector. 13 Sequential detector 14 Barrel Shifter 15 32-bit signed Divider 16 Signed Multiplier 17 4 X 4 binary multiplier 18 32-bit Adder 19 BCD Adder 20 BCD Counter 21 BCD to Seven segment converter 22 Floating point Multiplier 23 Floating point Adder 24 RAM system 25 Signed and unsigned Comparator 26 Carry Ripple and Carry look ahead adder 27 Parallel to serial data converter 28 Signal Generator 29 3-bit counters 30 Arithmetic logic unit 31 Shifter unit 32 Swap unit 33 Normalizing Unit 34 Parity encoder 35 Dual Priority encoder 36 Ones counter-32 bit 37 Generate 10 deep, 8-bit Stack using 8-bit register 38 Gated crossed coupled latch circuit 39 Model a memory as a two dimensional array flip-flops, considering a 40 Generic RAM model in which each memory element is a GATED-FF component 41 Design a pulse counter and simulate with writing test bench 42 Generate binary multiplier and simulate with writing test bench 43 Traffic light control 44 16- bit CPU design 45 FIR filter 46 Neural Network 47 ex, Sinx, Cosx, Sin-1x, Cos-1x, Sinhx, Coshx 48 A 4 x 4 Array Multiplier HDL designer 49 Design a FSM of a two input, two output sequence detector which produce an output 1 every time the sequence 0101 is detected, and output 0 at all other times 50 Design a FSM of a Modulo-8 binary counter is to ne design with one input terminal which receivers pulse signals and one output terminals 51 Design a FSM of a serial parity bit generator is a two terminal circuit which receives coded message and is to add a parity bit to every in bit message, so that resulting outcome is an error detecting coded message

52

Multiplexer description using Truth table entry

You might also like