Chapter 5

Interfacing and Communication

Input-Output organization:
The input-output subsystem of a computer, referred to as I/O, provides an efficient mode of communication
between the central system and the outside environment.
Three types of devices:
Input device – key board, mouse
Output device – monitor, printer
Input-output device – magnetic tape, magnetic disk

I/O Interface: (Hardware component between CPU and I/O devices)

I/O interface provides a method for transferring information between internal storage and external I/O
devices. The purpose of interface is to resolve the differences that exist between the CPU and each peripheral.
The major differences are:
1. Peripherals are electromechanical and electromagnetic devices and their manner of operation is different
from the operation of the CPU and memory – which are electronic devices.
Therefore, a conversion of signal values may be required.

2. The data transfer rate of peripherals is usually slower than the transfer rate of the CPU, and
consequently, a synchronization mechanism may be needed.

3. Data codes and formats in peripherals differ from the word format in the CPU and memory.

4. The operating modes of peripherals are different from each other and each must be controlled so as not
to disturb the operation of other peripherals connected to the CPU.

The word “Interface” is a general term for the point of contact between two parts of a system. Two types of
interfaces are:
1. CPU Interface – that corresponds to the system bus
2. I/O Interface – that depends on the nature of I/O device.

The main function of I/O interface circuit is:

1. Data Conversion – refers to conversion between digital and analog signals, and conversion between
serial and parallel data formats.
2. Synchronization – refers to matching of operating speeds of CPU and other peripherals.
3. Device selection – refers to the selection of I/O device by CPU in a queue manner.

In addition, each device may have its own controller that supervises the operations of the particular mechanism
in the peripheral.
Each peripheral device has associated with it an interface unit. Each interface decodes the address and control
received from I/O bus, interprets them for the peripheral, and provides signal for peripheral controller. It also
synchronizes the data flow and supervises the transfer between peripherals and processor.

I/O commands: The interface responds to the I/O command from the processor and executes it. There are four
types of I/O commands:
Control command, status command, output data command, Input data command.

I/O Versus Memory Bus: In addition to communicating with I/O, the processor must communicate with the
memory unit. Like the I/O, the memory bus contains data, address, and read/write control lines.

There are three ways that computer buses can be used to communicate with memory and I/O:
1. Use two separate buses, one for memory and the other for I/O.
2. Use one common bus for both memory and I/O but have separate control lines for each.
3. Use one common bus for memory and I/O with common control lines.

1. Using Separate I/O processor:

In the first method, the computer has independent set of data, address and control buses, one for
accessing memory and other for I/O. The memory communicates with both the CPU and the IOP
through memory bus.

The I/O processor is sometimes called a data channel.

2. Using Isolated I/O:

Many computers use one common bus to transfer information between memory (or) I/O and the CPU.

The distinction between a memory transfer and I/O transfer is made through separate read and write lines. The
CPU specifies whether the address on the address lines is for a memory word or for an interface register by
enabling one of two possible read or write lines.

This configuration isolates all I/O interface addresses from the addresses assigned to memory and is referred to
as the isolated I/O method for assigning addresses in a common bus.
 3. Memory – mapped I/O:
The other alternative is to use the same address space for both memory and I/O. This is the case
computers that employ only one set of read and write signals and do not distinguish between memory
and I/O addresses.

The computer treats an interface register as being part of the memory system. Therefore, no specific I/O
instructions required separately.

Asynchronous Data Transfer:

The internal operations in a digital system are synchronized by means of clock pulses supplied by
common pulse generator. Clock pulses are applied to all registers within a unit and all data transfer among
internal registers occur simultaneously during the occurrence of the clock pulse.

Synchronous Transfer:
Two units such as CPU and an I/O interface are designed independently of each other. If the registers in
the interface share a common clock with the CPU registers, the transfer between the two units is said to be
synchronous.

Asynchronous Transfer:
In most cases, the internal timing in each unit is independent from the other, in that each uses its own
private clock for internal registers. In that case, the two units are said to be asynchronous to each other. This
approach is widely used in most computers.

Asynchronous Transfer methods:

Asynchronous data transfer between two independent units requires that control signals be transmitted
between the communicating units to indicate the time at which data is being transmitted.
1. Strobe method: One way to achieving asynchronous data transfer is by means of strobe pulse supplied
by one of the units to indicate to the other unit when the transfer has to occur.

2. Handshaking method: Another method commonly used is to accompany each data item being
transferred with a control signal that indicates the presence of data in the bus. The unit receiving the data
item responds with another control signal to acknowledge receipt of data. This type of agreement
between two independent units is referred to as handshaking.
Modes of Transfer:
Binary information received from an external device is usually stored in memory for later processing.
Information transferred from the CPU into an external device originates in the memory unit. The CPU merely
executes the I/O instructions and may accept the data temporarily, but the ultimate source or destination is the
memory unit.

Data transfer to and from peripheral may be handled in one of three possible modes:
1. Programmed I/O - uses CPU as an intermediate path
2. Interrupt-initiated I/O - uses CPU as an intermediate path.
3. Direct memory Access (DMA) – transfer data directly to and from the memory unit.

Programmed I/O:
Each data transfer is initiated by an instruction in the program. Usually the transfer is to and from a CPU
register and peripherals. Other instructions are needed to transfer the data to and from CPU and memory.

In the programmed I/O method, the CPU stays in a program loop (constant monitoring of the peripheral) until
the I/O unit indicates that it is ready for data transfer. This is a time-consuming process since it keeps the
processor busy needlessly.

Example: Data Transfer from I/O device to CPU

In this method, I/O device does not have direct access to memory. The data is transferred from I/O device to
CPU data register and then stored into a memory. It is assumed that the device is sending a sequence of bytes
that must be stored in memory. The transfer of each byte requires three instructions.
1. Read the status register
2. Check the status of the flag bit, if it is not set( i.e. 0) go to step 1, if it is set (i.e. 1) go to step 3.
3. Read the data register and store into memory.

The programmed I/O method is particularly useful in small low-speed computers. The difference in data
transfer rate between the CPU and the I/O device makes this type of transfer inefficient.

Interrupt-Initiated I/O:
An alternative to the CPU constantly monitoring the flag is to let the interface inform the computer when it is
ready to transfer data, using interrupt facility.

When the flag is set, the computer is momentarily interrupted from proceeding with the current program and
informed of the fact that the flag has been set. The CPU deviates from what is doing to take care of the input or
output transfer.

After the transfer is completed, the computer returns to the previous program to continue what it was doing
before the interrupt.
The CPU responds to the interrupt signal by storing the return address from the program counter into a memory
stack and then control branches to a service routine that processes the required I/O transfer.

The way that the processor chooses the branch address of the service routine varies from one unit to another.
There are two methods of accomplishing this.
1. Non vectored interrupt: In this method, the branch address is assigned to a fixed location in memory.
2. Vectored interrupt: In this method, the source (device) that interrupts supplies the branch information
to the computer. This information is called the interrupt vector.

In some computers the interrupt vector is the front address of the I/O service routine. In some computers the
interrupt vector is an address that points to a location in memory where the beginning address of the I/O service
routine is stored.

Priority Interrupt: Priority interrupt is a system that establishes a priority over the various sources to
determine which condition is to be serviced first when two or more requests arrive simultaneously.

In a typical application a more number of I/O devices are attached to the computer, with each device being able
to originate an interrupt request. Devices with high speed transfers such as magnetic disks are given high
priority and slow devices such as key boards receive low priority.
 Polling method: Establishing the priority of simultaneous interrupts can be done by software or
hardware. A polling procedure is used to identify the highest priority source by software means.

In this method, there is one common branch address for all interrupts. The program that takes care of interrupts
begins at the branch address and polls the interrupt sources in sequence.

The order in which they are tested determines the priority of each interrupt. The highest-priority source is tested
first, and if its interrupt signs are on, control branches to a service routine for this source. Otherwise, the next
lower-priority source is tested and so on.

Note: Thus the initial service routine for all interrupts consists of a program that tests the interrupt source in
sequence and branches to one of many possible service routines.

Disadvantage of the software method is that if there are many interrupts, the time required to poll them can
exceed the time available to service the I/O device. In this situation a hardware priority-interrupt unit can be
used to speed up the operation.

The Hardware Priority unit functions as an overall manager in an interrupt system environment. It
accepts interrupt requests from many sources, determines which of the incoming requests has the highest
priority and issues an interrupt request to the computer based on this determination.

To speed up the operation, each interrupt source has its own interrupt vector to access its own service routine
directly. The hardware priority function can be established by either a serial or a parallel connection of
interrupts lines.
1. Daisy-chain priority method (Serial)
2. Parallel priority interrupt method

Direct Memory Access (DMA):

The transfer of data between a fast storage device such as magnetic disk and memory is often limited by
the speed of the CPU. Removing the CPU from the path and letting the peripheral device manage the
memory buses directly would improve the speed of transfer. This transfer technique is called direct memory
access.
During DMA transfer, the CPU is idle and has no control of the memory buses. A DMA controller takes over
the buses to manage the transfer directly between the I/O device and memory.

Bus Request and Bus Grant: The two control signals in the CPU that facilitate the DMA transfer.

Bus Request (BR) – input is used by the DMA controller to request the CPU to relinquish control of the buses.
When this input is active, the CPU terminates the execution of the current instruction and places the address
bus, the data bus, and the read and write lines into a high-impedance state.

Bus Grant: The CPU activates the bus grant (BG) output to inform the external DMA that the buses are in the
high-impedance state. The DMA that originated the bus request can now take control of the buses to conduct
memory transfers without processor intervention.

When the DMA terminates the transfer, it disables the bus request line. The CPU disables the bus grant line,
takes control of the buses, and return to its normal operation.

Two types of DMA Transfer: When the DMA takes control of the bus system, it communicates directly with
the memory.
 Burst Transfer: In this method, a block sequence consisting of a number of memory words is
transferred in a continuous burst. This mode of transfer is needed for fast devices such as magnetic disks, where
data transmission cannot be stopped or slowed down until an entire block is transferred.

Cycle stealing: An alternative technique called cycle stealing allows the DMA controller to transfer one
data word at a time, after which it must return control of the buses to the CPU. The CPU merely delays it
operation for one memory cycle to allow the direct memory I/O transfer to “steal” one memory cycle.

Block diagram of DMA controller:

The DMA is first initialized by the CPU. After that, the DMA starts and continues to transfer data between
memory and peripheral unit until an entire block is transferred.

The CPU initializes the DMA by sending the following information through the data bus:
1. The starting address of the memory block where data are available (for read) or where data to be stored
(for write)
2. The word count, which is the number of words in the memory block.
3. Control to specify the mode of transfer such as read or write.
4. A control to start the DMA transfer.

The starting address is stored in the address register. The word count is stored in the word count register, and
the control information in the control register.

Once the DMA is initialized, the CPU stops communicating with the DMA controller unless it receives an
interrupt signal or if it wants to check how many words have been transferred.

Note: That the RD and WR lines in the DMA controller are bidirectional. The direction of transfer depends on
the states of the BG line.

When BG=0, the RD and WR are input lines allowing the CPU to communicate with the internal DMA
registers. When BG=1, the RD and WR are output lines from the DMA controller to the random-access memory
to specify the read or write operation for the data.